src/cmd/internal/obj/arm64/encoding_gen.go

// Code generated by 'instgen -o=$GOROOT # from go install golang.org/x/arch/arm64/instgen@latest'.

package arm64

const (
	enc_NIL component = iota
	enc_i1_tsz
	enc_i2h_i2l
	enc_i3h_i3l
	enc_i4h_i4l
	enc_imm2_tsz
	enc_tszh_tszl
	enc_M
	enc_PNd
	enc_PNn
	enc_Pd
	enc_Pdm
	enc_Pdn
	enc_Pg
	enc_Pm
	enc_Pn
	enc_Pv
	enc_Rd
	enc_Rdn
	enc_Rm
	enc_Rn
	enc_Vd
	enc_Vdn
	enc_Vm
	enc_Vn
	enc_Za
	enc_Zd
	enc_Zda
	enc_Zdn
	enc_Zk
	enc_Zm
	enc_Zn
	enc_i1
	enc_i2
	enc_imm2
	enc_size
	enc_size0
	enc_sz
	enc_tsz
)

// encodeArngBCheck is the implementation of the following encoding logic:
// Check this is a B arrangement
func encodeArngBCheck(v uint32) (uint32, bool) {
	if v == ARNG_B {
		return 0, true
	}
	return 0, false
}

// encodeArngDCheck is the implementation of the following encoding logic:
// Check this is a D arrangement
func encodeArngDCheck(v uint32) (uint32, bool) {
	if v == ARNG_D {
		return 0, true
	}
	return 0, false
}

// encodeArngHCheck is the implementation of the following encoding logic:
// Check this is a H arrangement
func encodeArngHCheck(v uint32) (uint32, bool) {
	if v == ARNG_H {
		return 0, true
	}
	return 0, false
}

// encodeArngQCheck is the implementation of the following encoding logic:
// Check this is a Q arrangement
func encodeArngQCheck(v uint32) (uint32, bool) {
	if v == ARNG_Q {
		return 0, true
	}
	return 0, false
}

// encodeArngSCheck is the implementation of the following encoding logic:
// Check this is a S arrangement
func encodeArngSCheck(v uint32) (uint32, bool) {
	if v == ARNG_S {
		return 0, true
	}
	return 0, false
}

// encodeMergePredCheck is the implementation of the following encoding logic:
// Check this is a merging predication
func encodeMergePredCheck(v uint32) (uint32, bool) {
	if v == PRED_M {
		return 0, true
	}
	return 0, false
}

// encodeZeroPredCheck is the implementation of the following encoding logic:
// Check this is a zeroing predication
func encodeZeroPredCheck(v uint32) (uint32, bool) {
	if v == PRED_Z {
		return 0, true
	}
	return 0, false
}

// encodeI2_1921_16To32Bit is the implementation of the following encoding logic:
// For the "16-bit to 32-bit" variant: is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
// bit range mappings:
// i2: [19:21)
func encodeI2_1921_16To32Bit(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 19, true
}

// encodeI1_2021_16To64Bit is the implementation of the following encoding logic:
// For the "16-bit to 64-bit" variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field.
// bit range mappings:
// i1: [20:21)
func encodeI1_2021_16To64Bit(v uint32) (uint32, bool) {
	if v > 1 {
		return 0, false
	}
	return v << 20, true
}

// encodeZm1620_16To64Bit is the implementation of the following encoding logic:
// For the "16-bit to 64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:20)
func encodeZm1620_16To64Bit(v uint32) (uint32, bool) {
	if v > 15 {
		return 0, false
	}
	return v << 16, true
}

// encodeZm1619_16Bit32Bit is the implementation of the following encoding logic:
// For the "16-bit" and "32-bit" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:19)
func encodeZm1619_16Bit32Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return v << 16, true
}

// encodeI3hI3l_1923_16Bit is the implementation of the following encoding logic:
// For the "16-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [22:23)
// i3l: [19:21)
func encodeI3hI3l_1923_16Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&3)<<19 | (v>>2)<<22, true
}

// encodeI2_1921_32Bit is the implementation of the following encoding logic:
// For the "32-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field.
// bit range mappings:
// i2: [19:21)
func encodeI2_1921_32Bit(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 19, true
}

// encodeI3hI3l_1119_32Bit is the implementation of the following encoding logic:
// For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [19:21)
// i3l: [11:12)
func encodeI3hI3l_1119_32Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&1)<<11 | (v>>1)<<19, true
}

// encodeZm1619_32Bit is the implementation of the following encoding logic:
// For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:19)
func encodeZm1619_32Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return v << 16, true
}

// encodeI1_2021_64Bit is the implementation of the following encoding logic:
// For the "64-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field.
// bit range mappings:
// i1: [20:21)
func encodeI1_2021_64Bit(v uint32) (uint32, bool) {
	if v > 1 {
		return 0, false
	}
	return v << 20, true
}

// encodeI2hI2l_1120_64Bit is the implementation of the following encoding logic:
// For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.
// bit range mappings:
// i2h: [20:21)
// i2l: [11:12)
func encodeI2hI2l_1120_64Bit(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return (v&1)<<11 | (v>>1)<<20, true
}

// encodeZm1620_64Bit is the implementation of the following encoding logic:
// For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:20)
func encodeZm1620_64Bit(v uint32) (uint32, bool) {
	if v > 15 {
		return 0, false
	}
	return v << 16, true
}

// encodeI3hI3l_1923_8To16Bit is the implementation of the following encoding logic:
// For the "8-bit to 16-bit" variant: is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [22:23)
// i3l: [19:21)
func encodeI3hI3l_1923_8To16Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&3)<<19 | (v>>2)<<22, true
}

// encodeI2_1921_8To32Bit is the implementation of the following encoding logic:
// For the "8-bit to 32-bit" variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
// bit range mappings:
// i2: [19:21)
func encodeI2_1921_8To32Bit(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 19, true
}

// encodeZm1619_8To32Bit is the implementation of the following encoding logic:
// For the "8-bit to 32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:19)
func encodeZm1619_8To32Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return v << 16, true
}

// encodeSzByteHalfword is the implementation of the following encoding logic:
// For the "Byte and halfword" variant: is the size specifier,
// sz	<T>
// 0	B
// 1	H
// bit range mappings:
// sz: [22:23)
func encodeSzByteHalfword(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0, true
	case ARNG_H:
		return 1 << 22, true
	}
	return 0, false
}

// encodeSizeByteMergeZero is the implementation of the following encoding logic:
// For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier,
// size	<T>
// 00	RESERVED
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [22:24)
func encodeSizeByteMergeZero(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeI1_2021_DoublePrecision is the implementation of the following encoding logic:
// For the "Double-precision" variant: is the immediate index, in the range 0 to 1, encoded in the "i1" field.
// bit range mappings:
// i1: [20:21)
func encodeI1_2021_DoublePrecision(v uint32) (uint32, bool) {
	if v > 1 {
		return 0, false
	}
	return v << 20, true
}

// encodeZm1620_DoublePrecision is the implementation of the following encoding logic:
// For the "Double-precision" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:20)
func encodeZm1620_DoublePrecision(v uint32) (uint32, bool) {
	if v > 15 {
		return 0, false
	}
	return v << 16, true
}

// encodeI3hI3l_1722_Doubleword is the implementation of the following encoding logic:
// For the "Doubleword" variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [22:23)
// i3l: [17:19)
func encodeI3hI3l_1722_Doubleword(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&3)<<17 | (v>>2)<<22, true
}

// encodeZm1619_HalfSinglePrecision is the implementation of the following encoding logic:
// For the "Half-precision" and "Single-precision" variants: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:19)
func encodeZm1619_HalfSinglePrecision(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return v << 16, true
}

// encodeI3hI3l_1923_HalfPrecision is the implementation of the following encoding logic:
// For the "Half-precision" variant: is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [22:23)
// i3l: [19:21)
func encodeI3hI3l_1923_HalfPrecision(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&3)<<19 | (v>>2)<<22, true
}

// encodeI1_1718_Halfword is the implementation of the following encoding logic:
// For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field.
// bit range mappings:
// i1: [17:18)
func encodeI1_1718_Halfword(v uint32) (uint32, bool) {
	if v > 1 {
		return 0, false
	}
	return v << 17, true
}

// encodeSize0HalfwordMergeZero is the implementation of the following encoding logic:
// For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier,
// size[0]	<T>
// 0	S
// 1	D
// bit range mappings:
// size: [22:23)
func encodeSize0HalfwordMergeZero(v uint32) (uint32, bool) {
	switch v {
	case ARNG_S:
		return 0, true
	case ARNG_D:
		return 1 << 22, true
	}
	return 0, false
}

// encodeI2_1921_SinglePrecision is the implementation of the following encoding logic:
// For the "Single-precision" variant: is the immediate index, in the range 0 to 3, encoded in the "i2" field.
// bit range mappings:
// i2: [19:21)
func encodeI2_1921_SinglePrecision(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 19, true
}

// encodeSzWordDoubleword is the implementation of the following encoding logic:
// For the "Word and doubleword" variant: is the size specifier,
// sz	<T>
// 0	S
// 1	D
// bit range mappings:
// sz: [22:23)
func encodeSzWordDoubleword(v uint32) (uint32, bool) {
	switch v {
	case ARNG_S:
		return 0, true
	case ARNG_D:
		return 1 << 22, true
	}
	return 0, false
}

// encodeI2_1719_Word is the implementation of the following encoding logic:
// For the "Word" variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field.
// bit range mappings:
// i2: [17:19)
func encodeI2_1719_Word(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 17, true
}

// encodeSize16B8H4S2D is the implementation of the following encoding logic:
// Is an arrangement specifier,
// size	<T>
// 00	16B
// 01	8H
// 10	4S
// 11	2D
// bit range mappings:
// size: [22:24)
func encodeSize16B8H4S2D(v uint32) (uint32, bool) {
	switch v {
	case ARNG_16B:
		return 0, true
	case ARNG_8H:
		return 1 << 22, true
	case ARNG_4S:
		return 2 << 22, true
	case ARNG_2D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSize8H4S2D is the implementation of the following encoding logic:
// Is an arrangement specifier,
// size	<T>
// 00	RESERVED
// 01	8H
// 10	4S
// 11	2D
// bit range mappings:
// size: [22:24)
func encodeSize8H4S2D(v uint32) (uint32, bool) {
	switch v {
	case ARNG_8H:
		return 1 << 22, true
	case ARNG_4S:
		return 2 << 22, true
	case ARNG_2D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeWdn05 is the implementation of the following encoding logic:
// Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
// bit range mappings:
// Rdn: [0:5)
func encodeWdn05(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return v & 31, true
}

// encodeVd0564 is the implementation of the following encoding logic:
// Is the 64-bit name of the destination SIMD&FP register, encoded in the "Vd" field.
// bit range mappings:
// Vd: [0:5)
func encodeVd0564(v uint32) (uint32, bool) {
	return v & 31, true
}

// encodeRd05 is the implementation of the following encoding logic:
// Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field.
// bit range mappings:
// Rd: [0:5)
func encodeRd05(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return v & 31, true
}

// encodeRn510 is the implementation of the following encoding logic:
// Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field.
// bit range mappings:
// Rn: [5:10)
func encodeRn510(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return (v & 31) << 5, true
}

// encodeRm1621 is the implementation of the following encoding logic:
// Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field.
// bit range mappings:
// Rm: [16:21)
func encodeRm1621(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return (v & 31) << 16, true
}

// encodeXdn05 is the implementation of the following encoding logic:
// Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.
// bit range mappings:
// Rdn: [0:5)
func encodeXdn05(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return v & 31, true
}

// encodeI2_1921_8BitGroup is the implementation of the following encoding logic:
// Is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
// bit range mappings:
// i2: [19:21)
func encodeI2_1921_8BitGroup(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 19, true
}

// encodeI2_1921_Pair16Bit is the implementation of the following encoding logic:
// Is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
// bit range mappings:
// i2: [19:21)
func encodeI2_1921_Pair16Bit(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 19, true
}

// encodeI3hI3l_1119_Pair8Bit is the implementation of the following encoding logic:
// Is the immediate index of a pair of 8-bit elements within each 128-bit vector segment, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [19:21)
// i3l: [11:12)
func encodeI3hI3l_1119_Pair8Bit(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&1)<<11 | (v>>1)<<19, true
}

// encodeI4hI4l_1019 is the implementation of the following encoding logic:
// Is the immediate index, in the range 0 to 15, encoded in the "i4h:i4l" fields.
// bit range mappings:
// i4h: [19:21)
// i4l: [10:12)
func encodeI4hI4l_1019(v uint32) (uint32, bool) {
	if v > 15 {
		return 0, false
	}
	return (v&3)<<10 | (v>>2)<<19, true
}

// encodeI3hI3l_1119 is the implementation of the following encoding logic:
// Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [19:21)
// i3l: [11:12)
func encodeI3hI3l_1119(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&1)<<11 | (v>>1)<<19, true
}

// encodeI3hI3l_1922 is the implementation of the following encoding logic:
// Is the immediate index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
// bit range mappings:
// i3h: [22:23)
// i3l: [19:21)
func encodeI3hI3l_1922(v uint32) (uint32, bool) {
	if v > 7 {
		return 0, false
	}
	return (v&3)<<19 | (v>>2)<<22, true
}

// encodeI1Tsz_Delegate is the implementation of the following encoding logic:
// Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz".
// bit range mappings:
// i1: [20:21)
// tsz: [16:20)
func encodeI1Tsz_Delegate(v uint32) (uint32, bool) {
	// The statement "range 0 to one less than the number of elements in 128 bits"
	// is not possible to handle here, we delegate this to the caller.
	return codeI1Tsz, false
}

// encodeImm2Tsz_Delegate is the implementation of the following encoding logic:
// Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".
// bit range mappings:
// imm2: [22:24)
// tsz: [16:21)
func encodeImm2Tsz_Delegate(v uint32) (uint32, bool) {
	// The statement "range 0 to one less than the number of elements in 512 bits"
	// is not possible to handle here, we delegate this to the caller.
	return codeImm2Tsz, false
}

// encodeVd is the implementation of the following encoding logic:
// Is the name of the destination SIMD&FP register, encoded in the "Vd" field.
// bit range mappings:
// Vd: [0:5)
func encodeVd(v uint32) (uint32, bool) {
	return v & 31, true
}

// encodePNd is the implementation of the following encoding logic:
// Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field.
// bit range mappings:
// PNd: [0:3)
func encodePNd(v uint32) (uint32, bool) {
	if v >= 24 && v <= 31 {
		// PN registers starts from 16.
		return v - 24, true
	}
	return 0, false
}

// encodePd is the implementation of the following encoding logic:
// Is the name of the destination scalable predicate register, encoded in the "Pd" field.
// bit range mappings:
// Pd: [0:4)
func encodePd(v uint32) (uint32, bool) {
	return v, true
}

// encodeZd is the implementation of the following encoding logic:
// Is the name of the destination scalable vector register, encoded in the "Zd" field.
// bit range mappings:
// Zd: [0:5)
func encodeZd(v uint32) (uint32, bool) {
	return v, true
}

// encodePdnDest is the implementation of the following encoding logic:
// Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field.
// bit range mappings:
// Pdn: [0:4)
func encodePdnDest(v uint32) (uint32, bool) {
	return v, true
}

// encodeZdnDest is the implementation of the following encoding logic:
// Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
// bit range mappings:
// Zdn: [0:5)
func encodeZdnDest(v uint32) (uint32, bool) {
	return v, true
}

// encodePnN_58 is the implementation of the following encoding logic:
// Is the name of the first source scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNn" field.
// bit range mappings:
// PNn: [5:8)
func encodePnN_58(v uint32) (uint32, bool) {
	if v >= 24 && v <= 31 {
		// PN registers starts from 16.
		return (v - 24) << 5, true
	}
	return 0, false
}

// encodePn59 is the implementation of the following encoding logic:
// Is the name of the first source scalable predicate register, encoded in the "Pn" field.
// bit range mappings:
// Pn: [5:9)
func encodePn59(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodeZn510 is the implementation of the following encoding logic:
// Is the name of the first source scalable vector register, encoded in the "Zn" field.
// bit range mappings:
// Zn: [5:10)
func encodeZn510(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodePg1013 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
// bit range mappings:
// Pg: [10:13)
func encodePg1013(v uint32) (uint32, bool) {
	if v <= 7 {
		return v << 10, true
	}
	return 0, false
}

// encodePg1014 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register, encoded in the "Pg" field.
// bit range mappings:
// Pg: [10:14)
func encodePg1014(v uint32) (uint32, bool) {
	return v << 10, true
}

// encodePg59 is the implementation of the following encoding logic:
// Is the name of the governing scalable predicate register, encoded in the "Pg" field.
// bit range mappings:
// Pg: [5:9)
func encodePg59(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodePdmDest is the implementation of the following encoding logic:
// Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
// bit range mappings:
// Pdm: [0:4)
func encodePdmDest(v uint32) (uint32, bool) {
	return v, true
}

// encodeZdaDest is the implementation of the following encoding logic:
// Is the name of the second source and destination scalable vector register, encoded in the "Zda" field.
// bit range mappings:
// Zda: [0:5)
func encodeZdaDest(v uint32) (uint32, bool) {
	return v, true
}

// encodePm1620 is the implementation of the following encoding logic:
// Is the name of the second source scalable predicate register, encoded in the "Pm" field.
// bit range mappings:
// Pm: [16:20)
func encodePm1620(v uint32) (uint32, bool) {
	return v << 16, true
}

// encodeZm_1619_Range0_7 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:19)
func encodeZm_1619_Range0_7(v uint32) (uint32, bool) {
	if v <= 7 {
		return v << 16, true
	}
	return 0, false
}

// encodeZm1621 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [16:21)
func encodeZm1621(v uint32) (uint32, bool) {
	return v << 16, true
}

// encodeZm510V1 is the implementation of the following encoding logic:
// Is the name of the second source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [5:10)
func encodeZm510V1(v uint32) (uint32, bool) {
	return (v & 31) << 5, true
}

// encodePdnSrcDst is the implementation of the following encoding logic:
// Is the name of the source and destination scalable predicate register, encoded in the "Pdn" field.
// bit range mappings:
// Pdn: [0:4)
func encodePdnSrcDst(v uint32) (uint32, bool) {
	return v, true
}

// encodeZdnSrcDst is the implementation of the following encoding logic:
// Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
// bit range mappings:
// Zdn: [0:5)
func encodeZdnSrcDst(v uint32) (uint32, bool) {
	return v, true
}

// encodePm59v1 is the implementation of the following encoding logic:
// Is the name of the source scalable predicate register, encoded in the "Pm" field.
// bit range mappings:
// Pm: [5:9)
func encodePm59v1(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodePn59v2 is the implementation of the following encoding logic:
// Is the name of the source scalable predicate register, encoded in the "Pn" field.
// bit range mappings:
// Pn: [5:9)
func encodePn59v2(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodeZm510V2 is the implementation of the following encoding logic:
// Is the name of the source scalable vector register, encoded in the "Zm" field.
// bit range mappings:
// Zm: [5:10)
func encodeZm510V2(v uint32) (uint32, bool) {
	return (v & 31) << 5, true
}

// encodeZn510Src is the implementation of the following encoding logic:
// Is the name of the source scalable vector register, encoded in the "Zn" field.
// bit range mappings:
// Zn: [5:10)
func encodeZn510Src(v uint32) (uint32, bool) {
	return (v & 31) << 5, true
}

// encodeZda3RdSrcDst is the implementation of the following encoding logic:
// Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
// bit range mappings:
// Zda: [0:5)
func encodeZda3RdSrcDst(v uint32) (uint32, bool) {
	return v, true
}

// encodeZa16213Rd is the implementation of the following encoding logic:
// Is the name of the third source scalable vector register, encoded in the "Za" field.
// bit range mappings:
// Za: [16:21)
func encodeZa16213Rd(v uint32) (uint32, bool) {
	return v << 16, true
}

// encodeZa5103Rd is the implementation of the following encoding logic:
// Is the name of the third source scalable vector register, encoded in the "Za" field.
// bit range mappings:
// Za: [5:10)
func encodeZa5103Rd(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodeZk5103Rd is the implementation of the following encoding logic:
// Is the name of the third source scalable vector register, encoded in the "Zk" field.
// bit range mappings:
// Zk: [5:10)
func encodeZk5103Rd(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodePv1013 is the implementation of the following encoding logic:
// Is the name of the vector select predicate register P0-P7, encoded in the "Pv" field.
// bit range mappings:
// Pv: [10:13)
func encodePv1013(v uint32) (uint32, bool) {
	return v << 10, true
}

// encodePv1014 is the implementation of the following encoding logic:
// Is the name of the vector select predicate register, encoded in the "Pv" field.
// bit range mappings:
// Pv: [10:14)
func encodePv1014(v uint32) (uint32, bool) {
	return v << 10, true
}

// encodePv59 is the implementation of the following encoding logic:
// Is the name of the vector select predicate register, encoded in the "Pv" field.
// bit range mappings:
// Pv: [5:9)
func encodePv59(v uint32) (uint32, bool) {
	return v << 5, true
}

// encodeRd05ZR is the implementation of the following encoding logic:
// Is the number [0-30] of the destination general-purpose register or the name ZR (31), encoded in the "Rd" field.
// bit range mappings:
// Rd: [0:5)
func encodeRd05ZR(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	// ZR is just R31
	return v & 31, true
}

// encodeRn510SP is the implementation of the following encoding logic:
// Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.
// bit range mappings:
// Rn: [5:10)
func encodeRn510SP(v uint32) (uint32, bool) {
	if v == REG_R31 {
		return 0, false
	}
	if v == REG_RSP {
		return (REG_R31 & 31) << 5, true
	}
	return (v & 31) << 5, true
}

// encodeRdn05ZR is the implementation of the following encoding logic:
// Is the number [0-30] of the source and destination general-purpose register or the name ZR (31), encoded in the "Rdn" field.
// bit range mappings:
// Rdn: [0:5)
func encodeRdn05ZR(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return v & 31, true
}

// encodeRm1621ZR is the implementation of the following encoding logic:
// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.
// bit range mappings:
// Rm: [16:21)
func encodeRm1621ZR(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return (v & 31) << 16, true
}

// encodeRm510ZR is the implementation of the following encoding logic:
// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.
// bit range mappings:
// Rm: [5:10)
func encodeRm510ZR(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return (v & 31) << 5, true
}

// encodeRn510ZR is the implementation of the following encoding logic:
// Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.
// bit range mappings:
// Rn: [5:10)
func encodeRn510ZR(v uint32) (uint32, bool) {
	if v == REG_RSP {
		return 0, false
	}
	return (v & 31) << 5, true
}

// encodeVd05 is the implementation of the following encoding logic:
// Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.
// bit range mappings:
// Vd: [0:5)
func encodeVd05(v uint32) (uint32, bool) {
	return v & 31, true
}

// encodeVm510 is the implementation of the following encoding logic:
// Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field.
// bit range mappings:
// Vm: [5:10)
func encodeVm510(v uint32) (uint32, bool) {
	return (v & 31) << 5, true
}

// encodeVn510 is the implementation of the following encoding logic:
// Is the number [0-31] of the source SIMD&FP register, encoded in the "Vn" field.
// bit range mappings:
// Vn: [5:10)
func encodeVn510(v uint32) (uint32, bool) {
	return (v & 31) << 5, true
}

// encodeVdn05 is the implementation of the following encoding logic:
// Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.
// bit range mappings:
// Vdn: [0:5)
func encodeVdn05(v uint32) (uint32, bool) {
	return v & 31, true
}

// encodeImm2_810 is the implementation of the following encoding logic:
// Is the portion index, in the range 0 to 3, encoded in the "imm2" field.
// bit range mappings:
// imm2: [8:10)
func encodeImm2_810(v uint32) (uint32, bool) {
	if v > 3 {
		return 0, false
	}
	return v << 8, true
}

// encodePredQualM1617 is the implementation of the following encoding logic:
// Is the predication qualifier,
// M	<ZM>
// 0	Z
// 1	M
// bit range mappings:
// M: [16:17)
func encodePredQualM1617(v uint32) (uint32, bool) {
	switch v {
	case PRED_Z:
		return 0, true
	case PRED_M:
		return 1 << 16, true
	}
	return 0, false
}

// encodePredQualM45 is the implementation of the following encoding logic:
// Is the predication qualifier,
// M	<ZM>
// 0	Z
// 1	M
// bit range mappings:
// M: [4:5)
func encodePredQualM45(v uint32) (uint32, bool) {
	switch v {
	case PRED_Z:
		return 0, true
	case PRED_M:
		return 1 << 4, true
	}
	return 0, false
}

// encodeSizeBHSD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 00	B
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [22:24)
func encodeSizeBHSD2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0 << 22, true
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeBHS2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 00	B
// 01	H
// 10	S
// 11	RESERVED
// bit range mappings:
// size: [22:24)
func encodeSizeBHS2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0 << 22, true
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	}
	return 0, false
}

// encodeSizeBHS2224Offset1 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 00	RESERVED
// 01	B
// 10	H
// 11	S
// bit range mappings:
// size: [22:24)
func encodeSizeBHS2224Offset1(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 1 << 22, true
	case ARNG_H:
		return 2 << 22, true
	case ARNG_S:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeHSD1315 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 00	RESERVED
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [13:15)
func encodeSizeHSD1315(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 13, true
	case ARNG_S:
		return 2 << 13, true
	case ARNG_D:
		return 3 << 13, true
	}
	return 0, false
}

// encodeSizeHSD1719 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 00	RESERVED
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [17:19)
func encodeSizeHSD1719(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 17, true
	case ARNG_S:
		return 2 << 17, true
	case ARNG_D:
		return 3 << 17, true
	}
	return 0, false
}

// encodeSizeHSD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 00	RESERVED
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [22:24)
func encodeSizeHSD2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeHSD2224No00 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [22:24)
func encodeSizeHSD2224No00(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeHD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<T>
// 01	H
// 1x	D
// bit range mappings:
// size: [22:24)
func encodeSizeHD2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeTbBHSD2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<Tb>
// 00	B
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [22:24)
func encodeSizeTbBHSD2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0 << 22, true
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeTbBHS2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<Tb>
// 00	RESERVED
// 01	B
// 10	H
// 11	S
// bit range mappings:
// size: [22:24)
func encodeSizeTbBHS2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 1 << 22, true
	case ARNG_H:
		return 2 << 22, true
	case ARNG_S:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeTbHSD2224Offset1 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<Tb>
// 00	RESERVED
// 01	H
// 10	S
// 11	D
// bit range mappings:
// size: [22:24)
func encodeSizeTbHSD2224Offset1(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 1 << 22, true
	case ARNG_S:
		return 2 << 22, true
	case ARNG_D:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSizeTbBS2224 is the implementation of the following encoding logic:
// Is the size specifier,
// size	<Tb>
// 01	B
// 1x	S
// bit range mappings:
// size: [22:24)
func encodeSizeTbBS2224(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 1 << 22, true
	case ARNG_S:
		return 3 << 22, true
	}
	return 0, false
}

// encodeSize0BH2223 is the implementation of the following encoding logic:
// Is the size specifier,
// size[0]	<T>
// 0	B
// 1	H
// bit range mappings:
// size: [22:23)
func encodeSize0BH2223(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0 << 22, true
	case ARNG_H:
		return 1 << 22, true
	}
	return 0, false
}

// encodeSize0SD2223 is the implementation of the following encoding logic:
// Is the size specifier,
// size[0]	<T>
// 0	S
// 1	D
// bit range mappings:
// size: [22:23)
func encodeSize0SD2223(v uint32) (uint32, bool) {
	switch v {
	case ARNG_S:
		return 0 << 22, true
	case ARNG_D:
		return 1 << 22, true
	}
	return 0, false
}

// encodeSize0TbBH2223 is the implementation of the following encoding logic:
// Is the size specifier,
// size[0]	<Tb>
// 0	B
// 1	H
// bit range mappings:
// size: [22:23)
func encodeSize0TbBH2223(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0 << 22, true
	case ARNG_H:
		return 1 << 22, true
	}
	return 0, false
}

// encodeSzSD1415 is the implementation of the following encoding logic:
// Is the size specifier,
// sz	<T>
// 0	S
// 1	D
// bit range mappings:
// sz: [14:15)
func encodeSzSD1415(v uint32) (uint32, bool) {
	switch v {
	case ARNG_S:
		return 0 << 14, true
	case ARNG_D:
		return 1 << 14, true
	}
	return 0, false
}

// encodeSzSD1718 is the implementation of the following encoding logic:
// Is the size specifier,
// sz	<T>
// 0	S
// 1	D
// bit range mappings:
// sz: [17:18)
func encodeSzSD1718(v uint32) (uint32, bool) {
	switch v {
	case ARNG_S:
		return 0 << 17, true
	case ARNG_D:
		return 1 << 17, true
	}
	return 0, false
}

// encodeSzSD2223 is the implementation of the following encoding logic:
// Is the size specifier,
// sz	<T>
// 0	S
// 1	D
// bit range mappings:
// sz: [22:23)
func encodeSzSD2223(v uint32) (uint32, bool) {
	switch v {
	case ARNG_S:
		return 0 << 22, true
	case ARNG_D:
		return 1 << 22, true
	}
	return 0, false
}

// encodeTsz_1620_SizeSpecifier4 is the implementation of the following encoding logic:
// Is the size specifier,
// tsz	<T>
// 0000	RESERVED
// xxx1	B
// xx10	H
// x100	S
// 1000	D
// bit range mappings:
// tsz: [16:20)
func encodeTsz_1620_SizeSpecifier4(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 1 << 16, true
	case ARNG_H:
		return 2 << 16, true
	case ARNG_S:
		return 4 << 16, true
	case ARNG_D:
		return 8 << 16, true
	}
	return 0, false
}

// encodeTsz_1621_SizeSpecifier5 is the implementation of the following encoding logic:
// Is the size specifier,
// tsz	<T>
// 00000	RESERVED
// xxxx1	B
// xxx10	H
// xx100	S
// x1000	D
// 10000	Q
// bit range mappings:
// tsz: [16:21)
func encodeTsz_1621_SizeSpecifier5(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 1 << 16, true
	case ARNG_H:
		return 2 << 16, true
	case ARNG_S:
		return 4 << 16, true
	case ARNG_D:
		return 8 << 16, true
	case ARNG_Q:
		return 16 << 16, true
	}
	return 0, false
}

// encodeTszhTszlBHS is the implementation of the following encoding logic:
// Is the size specifier,
// tszh	tszl	<T>
// 0	00	RESERVED
// 0	01	B
// 0	10	H
// 0	11	RESERVED
// 1	00	S
// 1	01	RESERVED
// 1	1x	RESERVED
// bit range mappings:
// tszh: [22:23)
// tszl: [19:21)
func encodeTszhTszlBHS(v uint32) (uint32, bool) {
	switch v {
	case ARNG_B:
		return 0<<22 | 1<<19, true
	case ARNG_H:
		return 0<<22 | 2<<19, true
	case ARNG_S:
		return 1 << 22, true
	}
	return 0, false
}

// encodeTszhTszlTbHSD is the implementation of the following encoding logic:
// Is the size specifier,
// tszh	tszl	<Tb>
// 0	00	RESERVED
// 0	01	H
// 0	10	S
// 0	11	RESERVED
// 1	00	D
// 1	01	RESERVED
// 1	1x	RESERVED
// bit range mappings:
// tszh: [22:23)
// tszl: [19:21)
func encodeTszhTszlTbHSD(v uint32) (uint32, bool) {
	switch v {
	case ARNG_H:
		return 0<<22 | 1<<19, true
	case ARNG_S:
		return 0<<22 | 2<<19, true
	case ARNG_D:
		return 1 << 22, true
	}
	return 0, false
}

// encodeNoop is the implementation of the following encoding logic:
// No-op check, returns true
func encodeNoop(v uint32) (uint32, bool) {
	return 0, true
}