| // Code generated by 'simdgen -o godefs -goroot $GOROOT -arch arm64 -arm64Path $ARM64_ISA_PATH go_arm64.yaml types.yaml categories.yaml'; DO NOT EDIT. |
| |
| (VFCVTL4S (VDUPDextr [1] x)) => (VFCVTL2_4S x) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VFCVTN2D y))) => (VFCVTN2_2D dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN2D [c] y))) => (VSHRN2_2D dst [c] y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN4S [c] y))) => (VSHRN2_4S dst [c] y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSHRN8H [c] y))) => (VSHRN2_8H dst [c] y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN2D y))) => (VSQXTN2_2D dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN4S y))) => (VSQXTN2_4S dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTN8H y))) => (VSQXTN2_8H dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN2D y))) => (VSQXTUN2_2D dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN4S y))) => (VSQXTUN2_4S dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VSQXTUN8H y))) => (VSQXTUN2_8H dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN2D y))) => (VUQXTN2_2D dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN4S y))) => (VUQXTN2_4S dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VUQXTN8H y))) => (VUQXTN2_8H dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VXTN2D y))) => (VXTN2_2D dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VXTN4S y))) => (VXTN2_4S dst y) |
| (VMOVDins0 [1] dst (VDUPDextr [0] (VXTN8H y))) => (VXTN2_8H dst y) |
| (VPMULL2D (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VPMULL2_2D x y) |
| (VSMULL16B (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VSMULL2_16B x y) |
| (VSMULL4S (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VSMULL2_4S x y) |
| (VSMULL8H (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VSMULL2_8H x y) |
| (VSSHLL16B [a] (VDUPDextr [1] x)) => (VSSHLL2_16B [a] x) |
| (VSSHLL4S [a] (VDUPDextr [1] x)) => (VSSHLL2_4S [a] x) |
| (VSSHLL8H [a] (VDUPDextr [1] x)) => (VSSHLL2_8H [a] x) |
| (VSXTL16B (VDUPDextr [1] x)) => (VSXTL2_16B x) |
| (VSXTL4S (VDUPDextr [1] x)) => (VSXTL2_4S x) |
| (VSXTL8H (VDUPDextr [1] x)) => (VSXTL2_8H x) |
| (VUMULL16B (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VUMULL2_16B x y) |
| (VUMULL4S (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VUMULL2_4S x y) |
| (VUMULL8H (VDUPDextr [1] x) (VDUPDextr [1] y)) => (VUMULL2_8H x y) |
| (VUSHLL16B [a] (VDUPDextr [1] x)) => (VUSHLL2_16B [a] x) |
| (VUSHLL4S [a] (VDUPDextr [1] x)) => (VUSHLL2_4S [a] x) |
| (VUSHLL8H [a] (VDUPDextr [1] x)) => (VUSHLL2_8H [a] x) |
| (VUXTL16B (VDUPDextr [1] x)) => (VUXTL2_16B x) |
| (VUXTL4S (VDUPDextr [1] x)) => (VUXTL2_4S x) |
| (VUXTL8H (VDUPDextr [1] x)) => (VUXTL2_8H x) |
| (AbsFloat32x4 ...) => (VFABS4S ...) // pureVreg |
| (AbsFloat64x2 ...) => (VFABS2D ...) // pureVreg |
| (AbsInt8x16 ...) => (VABS16B ...) // pureVreg |
| (AbsInt16x8 ...) => (VABS8H ...) // pureVreg |
| (AbsInt32x4 ...) => (VABS4S ...) // pureVreg |
| (AbsInt64x2 ...) => (VABS2D ...) // pureVreg |
| (AddFloat32x4 ...) => (VFADD4S ...) // pureVreg |
| (AddFloat64x2 ...) => (VFADD2D ...) // pureVreg |
| (AddInt8x16 ...) => (VADD16B ...) // pureVreg |
| (AddInt16x8 ...) => (VADD8H ...) // pureVreg |
| (AddInt32x4 ...) => (VADD4S ...) // pureVreg |
| (AddInt64x2 ...) => (VADD2D ...) // pureVreg |
| (AddUint8x16 ...) => (VADD16B ...) // pureVreg |
| (AddUint16x8 ...) => (VADD8H ...) // pureVreg |
| (AddUint32x4 ...) => (VADD4S ...) // pureVreg |
| (AddUint64x2 ...) => (VADD2D ...) // pureVreg |
| (AddSaturatedInt8x16 ...) => (VSQADD16B ...) // pureVreg |
| (AddSaturatedInt16x8 ...) => (VSQADD8H ...) // pureVreg |
| (AddSaturatedInt32x4 ...) => (VSQADD4S ...) // pureVreg |
| (AddSaturatedInt64x2 ...) => (VSQADD2D ...) // pureVreg |
| (AddSaturatedUint8x16 ...) => (VUQADD16B ...) // pureVreg |
| (AddSaturatedUint16x8 ...) => (VUQADD8H ...) // pureVreg |
| (AddSaturatedUint32x4 ...) => (VUQADD4S ...) // pureVreg |
| (AddSaturatedUint64x2 ...) => (VUQADD2D ...) // pureVreg |
| (AndInt8x16 ...) => (VAND16B ...) // pureVreg |
| (AndInt16x8 ...) => (VAND16B ...) // pureVreg |
| (AndInt32x4 ...) => (VAND16B ...) // pureVreg |
| (AndInt64x2 ...) => (VAND16B ...) // pureVreg |
| (AndUint8x16 ...) => (VAND16B ...) // pureVreg |
| (AndUint16x8 ...) => (VAND16B ...) // pureVreg |
| (AndUint32x4 ...) => (VAND16B ...) // pureVreg |
| (AndUint64x2 ...) => (VAND16B ...) // pureVreg |
| (AndNotInt8x16 ...) => (VBIC16B ...) // pureVreg |
| (AndNotInt16x8 ...) => (VBIC16B ...) // pureVreg |
| (AndNotInt32x4 ...) => (VBIC16B ...) // pureVreg |
| (AndNotInt64x2 ...) => (VBIC16B ...) // pureVreg |
| (AndNotUint8x16 ...) => (VBIC16B ...) // pureVreg |
| (AndNotUint16x8 ...) => (VBIC16B ...) // pureVreg |
| (AndNotUint32x4 ...) => (VBIC16B ...) // pureVreg |
| (AndNotUint64x2 ...) => (VBIC16B ...) // pureVreg |
| (AverageInt8x16 ...) => (VSRHADD16B ...) // pureVreg |
| (AverageInt16x8 ...) => (VSRHADD8H ...) // pureVreg |
| (AverageInt32x4 ...) => (VSRHADD4S ...) // pureVreg |
| (AverageUint8x16 ...) => (VURHADD16B ...) // pureVreg |
| (AverageUint16x8 ...) => (VURHADD8H ...) // pureVreg |
| (AverageUint32x4 ...) => (VURHADD4S ...) // pureVreg |
| (CeilFloat32x4 ...) => (VFRINTP4S ...) // pureVreg |
| (CeilFloat64x2 ...) => (VFRINTP2D ...) // pureVreg |
| (ConcatAddPairsFloat32x4 ...) => (VFADDP4S ...) // pureVreg |
| (ConcatAddPairsFloat64x2 ...) => (VFADDP2D ...) // pureVreg |
| (ConcatAddPairsInt16x8 ...) => (VADDP8H ...) // pureVreg |
| (ConcatAddPairsInt32x4 ...) => (VADDP4S ...) // pureVreg |
| (ConcatAddPairsInt64x2 ...) => (VADDP2D ...) // pureVreg |
| (ConcatAddPairsUint16x8 ...) => (VADDP8H ...) // pureVreg |
| (ConcatAddPairsUint32x4 ...) => (VADDP4S ...) // pureVreg |
| (ConcatAddPairsUint64x2 ...) => (VADDP2D ...) // pureVreg |
| (ConcatEvenInt8x16 ...) => (VUZP116B ...) // pureVreg |
| (ConcatEvenInt16x8 ...) => (VUZP18H ...) // pureVreg |
| (ConcatEvenInt32x4 ...) => (VUZP14S ...) // pureVreg |
| (ConcatEvenInt64x2 ...) => (VUZP12D ...) // pureVreg |
| (ConcatEvenUint8x16 ...) => (VUZP116B ...) // pureVreg |
| (ConcatEvenUint16x8 ...) => (VUZP18H ...) // pureVreg |
| (ConcatEvenUint32x4 ...) => (VUZP14S ...) // pureVreg |
| (ConcatEvenUint64x2 ...) => (VUZP12D ...) // pureVreg |
| (ConcatOddInt8x16 ...) => (VUZP216B ...) // pureVreg |
| (ConcatOddInt16x8 ...) => (VUZP28H ...) // pureVreg |
| (ConcatOddInt32x4 ...) => (VUZP24S ...) // pureVreg |
| (ConcatOddInt64x2 ...) => (VUZP22D ...) // pureVreg |
| (ConcatOddUint8x16 ...) => (VUZP216B ...) // pureVreg |
| (ConcatOddUint16x8 ...) => (VUZP28H ...) // pureVreg |
| (ConcatOddUint32x4 ...) => (VUZP24S ...) // pureVreg |
| (ConcatOddUint64x2 ...) => (VUZP22D ...) // pureVreg |
| (ConcatShiftBytesRightUint8x16 ...) => (VEXT16B ...) // pureVreg |
| (ConvertLo2ToFloat64Float32x4 ...) => (VFCVTL4S ...) // pureVreg |
| (ConvertToFloat32Float64x2 ...) => (VFCVTN2D ...) // pureVreg |
| (ConvertToFloat32Int32x4 ...) => (VSCVTF4S ...) // pureVreg |
| (ConvertToFloat32Uint32x4 ...) => (VUCVTF4S ...) // pureVreg |
| (ConvertToFloat64Int64x2 ...) => (VSCVTF2D ...) // pureVreg |
| (ConvertToFloat64Uint64x2 ...) => (VUCVTF2D ...) // pureVreg |
| (ConvertToInt32Float32x4 ...) => (VFCVTZS4S ...) // pureVreg |
| (ConvertToInt64Float64x2 ...) => (VFCVTZS2D ...) // pureVreg |
| (ConvertToUint32Float32x4 ...) => (VFCVTZU4S ...) // pureVreg |
| (ConvertToUint64Float64x2 ...) => (VFCVTZU2D ...) // pureVreg |
| (DivFloat32x4 ...) => (VFDIV4S ...) // pureVreg |
| (DivFloat64x2 ...) => (VFDIV2D ...) // pureVreg |
| (EqualFloat32x4 ...) => (VFCMEQ4S ...) // pureVreg |
| (EqualFloat64x2 ...) => (VFCMEQ2D ...) // pureVreg |
| (EqualInt8x16 ...) => (VCMEQ16B ...) // pureVreg |
| (EqualInt16x8 ...) => (VCMEQ8H ...) // pureVreg |
| (EqualInt32x4 ...) => (VCMEQ4S ...) // pureVreg |
| (EqualInt64x2 ...) => (VCMEQ2D ...) // pureVreg |
| (EqualUint8x16 ...) => (VCMEQ16B ...) // pureVreg |
| (EqualUint16x8 ...) => (VCMEQ8H ...) // pureVreg |
| (EqualUint32x4 ...) => (VCMEQ4S ...) // pureVreg |
| (EqualUint64x2 ...) => (VCMEQ2D ...) // pureVreg |
| (ExtendLo2ToInt64Int32x4 ...) => (VSXTL4S ...) // pureVreg |
| (ExtendLo2ToUint64Uint32x4 ...) => (VUXTL4S ...) // pureVreg |
| (ExtendLo4ToInt32Int16x8 ...) => (VSXTL8H ...) // pureVreg |
| (ExtendLo4ToUint32Uint16x8 ...) => (VUXTL8H ...) // pureVreg |
| (ExtendLo8ToInt16Int8x16 ...) => (VSXTL16B ...) // pureVreg |
| (ExtendLo8ToUint16Uint8x16 ...) => (VUXTL16B ...) // pureVreg |
| (FloorFloat32x4 ...) => (VFRINTM4S ...) // pureVreg |
| (FloorFloat64x2 ...) => (VFRINTM2D ...) // pureVreg |
| (GetElemFloat32x4 ...) => (VDUPSextr ...) // pureVreg |
| (GetElemFloat64x2 ...) => (VDUPDextr ...) // pureVreg |
| (GetElemInt8x16 ...) => (VMOVBextr ...) // pureVreg |
| (GetElemInt16x8 ...) => (VMOVHextr ...) // pureVreg |
| (GetElemInt32x4 ...) => (VMOVSextr ...) // pureVreg |
| (GetElemInt64x2 ...) => (VMOVDextr ...) // pureVreg |
| (GetElemUint8x16 ...) => (VMOVBextr ...) // pureVreg |
| (GetElemUint16x8 ...) => (VMOVHextr ...) // pureVreg |
| (GetElemUint32x4 ...) => (VMOVSextr ...) // pureVreg |
| (GetElemUint64x2 ...) => (VMOVDextr ...) // pureVreg |
| (GreaterFloat32x4 ...) => (VFCMGT4S ...) // pureVreg |
| (GreaterFloat64x2 ...) => (VFCMGT2D ...) // pureVreg |
| (GreaterInt8x16 ...) => (VCMGT16B ...) // pureVreg |
| (GreaterInt16x8 ...) => (VCMGT8H ...) // pureVreg |
| (GreaterInt32x4 ...) => (VCMGT4S ...) // pureVreg |
| (GreaterInt64x2 ...) => (VCMGT2D ...) // pureVreg |
| (GreaterUint8x16 ...) => (VCMHI16B ...) // pureVreg |
| (GreaterUint16x8 ...) => (VCMHI8H ...) // pureVreg |
| (GreaterUint32x4 ...) => (VCMHI4S ...) // pureVreg |
| (GreaterUint64x2 ...) => (VCMHI2D ...) // pureVreg |
| (GreaterEqualFloat32x4 ...) => (VFCMGE4S ...) // pureVreg |
| (GreaterEqualFloat64x2 ...) => (VFCMGE2D ...) // pureVreg |
| (GreaterEqualInt8x16 ...) => (VCMGE16B ...) // pureVreg |
| (GreaterEqualInt16x8 ...) => (VCMGE8H ...) // pureVreg |
| (GreaterEqualInt32x4 ...) => (VCMGE4S ...) // pureVreg |
| (GreaterEqualInt64x2 ...) => (VCMGE2D ...) // pureVreg |
| (GreaterEqualUint8x16 ...) => (VCMHS16B ...) // pureVreg |
| (GreaterEqualUint16x8 ...) => (VCMHS8H ...) // pureVreg |
| (GreaterEqualUint32x4 ...) => (VCMHS4S ...) // pureVreg |
| (GreaterEqualUint64x2 ...) => (VCMHS2D ...) // pureVreg |
| (InterleaveEvenInt8x16 ...) => (VTRN116B ...) // pureVreg |
| (InterleaveEvenInt16x8 ...) => (VTRN18H ...) // pureVreg |
| (InterleaveEvenInt32x4 ...) => (VTRN14S ...) // pureVreg |
| (InterleaveEvenInt64x2 ...) => (VTRN12D ...) // pureVreg |
| (InterleaveEvenUint8x16 ...) => (VTRN116B ...) // pureVreg |
| (InterleaveEvenUint16x8 ...) => (VTRN18H ...) // pureVreg |
| (InterleaveEvenUint32x4 ...) => (VTRN14S ...) // pureVreg |
| (InterleaveEvenUint64x2 ...) => (VTRN12D ...) // pureVreg |
| (InterleaveHiInt8x16 ...) => (VZIP216B ...) // pureVreg |
| (InterleaveHiInt16x8 ...) => (VZIP28H ...) // pureVreg |
| (InterleaveHiInt32x4 ...) => (VZIP24S ...) // pureVreg |
| (InterleaveHiInt64x2 ...) => (VZIP22D ...) // pureVreg |
| (InterleaveHiUint8x16 ...) => (VZIP216B ...) // pureVreg |
| (InterleaveHiUint16x8 ...) => (VZIP28H ...) // pureVreg |
| (InterleaveHiUint32x4 ...) => (VZIP24S ...) // pureVreg |
| (InterleaveHiUint64x2 ...) => (VZIP22D ...) // pureVreg |
| (InterleaveLoInt8x16 ...) => (VZIP116B ...) // pureVreg |
| (InterleaveLoInt16x8 ...) => (VZIP18H ...) // pureVreg |
| (InterleaveLoInt32x4 ...) => (VZIP14S ...) // pureVreg |
| (InterleaveLoInt64x2 ...) => (VZIP12D ...) // pureVreg |
| (InterleaveLoUint8x16 ...) => (VZIP116B ...) // pureVreg |
| (InterleaveLoUint16x8 ...) => (VZIP18H ...) // pureVreg |
| (InterleaveLoUint32x4 ...) => (VZIP14S ...) // pureVreg |
| (InterleaveLoUint64x2 ...) => (VZIP12D ...) // pureVreg |
| (InterleaveOddInt8x16 ...) => (VTRN216B ...) // pureVreg |
| (InterleaveOddInt16x8 ...) => (VTRN28H ...) // pureVreg |
| (InterleaveOddInt32x4 ...) => (VTRN24S ...) // pureVreg |
| (InterleaveOddInt64x2 ...) => (VTRN22D ...) // pureVreg |
| (InterleaveOddUint8x16 ...) => (VTRN216B ...) // pureVreg |
| (InterleaveOddUint16x8 ...) => (VTRN28H ...) // pureVreg |
| (InterleaveOddUint32x4 ...) => (VTRN24S ...) // pureVreg |
| (InterleaveOddUint64x2 ...) => (VTRN22D ...) // pureVreg |
| (LeadingSignBitsInt8x16 ...) => (VCLS16B ...) // pureVreg |
| (LeadingSignBitsInt16x8 ...) => (VCLS8H ...) // pureVreg |
| (LeadingSignBitsInt32x4 ...) => (VCLS4S ...) // pureVreg |
| (LeadingSignBitsUint8x16 ...) => (VCLS16B ...) // pureVreg |
| (LeadingSignBitsUint16x8 ...) => (VCLS8H ...) // pureVreg |
| (LeadingSignBitsUint32x4 ...) => (VCLS4S ...) // pureVreg |
| (LeadingZerosInt8x16 ...) => (VCLZ16B ...) // pureVreg |
| (LeadingZerosInt16x8 ...) => (VCLZ8H ...) // pureVreg |
| (LeadingZerosInt32x4 ...) => (VCLZ4S ...) // pureVreg |
| (LeadingZerosUint8x16 ...) => (VCLZ16B ...) // pureVreg |
| (LeadingZerosUint16x8 ...) => (VCLZ8H ...) // pureVreg |
| (LeadingZerosUint32x4 ...) => (VCLZ4S ...) // pureVreg |
| (LookupOrZeroInt8x16 ...) => (VTBL16B ...) // pureVreg |
| (LookupOrZeroUint8x16 ...) => (VTBL16B ...) // pureVreg |
| (MaxFloat32x4 ...) => (VFMAX4S ...) // pureVreg |
| (MaxFloat64x2 ...) => (VFMAX2D ...) // pureVreg |
| (MaxInt8x16 ...) => (VSMAX16B ...) // pureVreg |
| (MaxInt16x8 ...) => (VSMAX8H ...) // pureVreg |
| (MaxInt32x4 ...) => (VSMAX4S ...) // pureVreg |
| (MaxUint8x16 ...) => (VUMAX16B ...) // pureVreg |
| (MaxUint16x8 ...) => (VUMAX8H ...) // pureVreg |
| (MaxUint32x4 ...) => (VUMAX4S ...) // pureVreg |
| (MinFloat32x4 ...) => (VFMIN4S ...) // pureVreg |
| (MinFloat64x2 ...) => (VFMIN2D ...) // pureVreg |
| (MinInt8x16 ...) => (VSMIN16B ...) // pureVreg |
| (MinInt16x8 ...) => (VSMIN8H ...) // pureVreg |
| (MinInt32x4 ...) => (VSMIN4S ...) // pureVreg |
| (MinUint8x16 ...) => (VUMIN16B ...) // pureVreg |
| (MinUint16x8 ...) => (VUMIN8H ...) // pureVreg |
| (MinUint32x4 ...) => (VUMIN4S ...) // pureVreg |
| (MulFloat32x4 ...) => (VFMUL4S ...) // pureVreg |
| (MulFloat64x2 ...) => (VFMUL2D ...) // pureVreg |
| (MulInt8x16 ...) => (VMUL16B ...) // pureVreg |
| (MulInt16x8 ...) => (VMUL8H ...) // pureVreg |
| (MulInt32x4 ...) => (VMUL4S ...) // pureVreg |
| (MulUint8x16 ...) => (VMUL16B ...) // pureVreg |
| (MulUint16x8 ...) => (VMUL8H ...) // pureVreg |
| (MulUint32x4 ...) => (VMUL4S ...) // pureVreg |
| (MulAddFloat32x4 x y z) => (VFMLA4S z x y) // specialLower |
| (MulAddFloat64x2 x y z) => (VFMLA2D z x y) // specialLower |
| (MulAddInt8x16 x y z) => (VMLA16B z x y) // specialLower |
| (MulAddInt16x8 x y z) => (VMLA8H z x y) // specialLower |
| (MulAddInt32x4 x y z) => (VMLA4S z x y) // specialLower |
| (MulAddUint8x16 x y z) => (VMLA16B z x y) // specialLower |
| (MulAddUint16x8 x y z) => (VMLA8H z x y) // specialLower |
| (MulAddUint32x4 x y z) => (VMLA4S z x y) // specialLower |
| (MulWidenLoInt8x16 ...) => (VSMULL16B ...) // pureVreg |
| (MulWidenLoInt16x8 ...) => (VSMULL8H ...) // pureVreg |
| (MulWidenLoInt32x4 ...) => (VSMULL4S ...) // pureVreg |
| (MulWidenLoUint8x16 ...) => (VUMULL16B ...) // pureVreg |
| (MulWidenLoUint16x8 ...) => (VUMULL8H ...) // pureVreg |
| (MulWidenLoUint32x4 ...) => (VUMULL4S ...) // pureVreg |
| (NegFloat32x4 ...) => (VFNEG4S ...) // pureVreg |
| (NegFloat64x2 ...) => (VFNEG2D ...) // pureVreg |
| (NegInt8x16 ...) => (VNEG16B ...) // pureVreg |
| (NegInt16x8 ...) => (VNEG8H ...) // pureVreg |
| (NegInt32x4 ...) => (VNEG4S ...) // pureVreg |
| (NegInt64x2 ...) => (VNEG2D ...) // pureVreg |
| (NotInt8x16 ...) => (VNOT16B ...) // pureVreg |
| (NotInt16x8 ...) => (VNOT16B ...) // pureVreg |
| (NotInt32x4 ...) => (VNOT16B ...) // pureVreg |
| (NotInt64x2 ...) => (VNOT16B ...) // pureVreg |
| (NotUint8x16 ...) => (VNOT16B ...) // pureVreg |
| (NotUint16x8 ...) => (VNOT16B ...) // pureVreg |
| (NotUint32x4 ...) => (VNOT16B ...) // pureVreg |
| (NotUint64x2 ...) => (VNOT16B ...) // pureVreg |
| (OnesCountInt8x16 ...) => (VCNT16B ...) // pureVreg |
| (OnesCountUint8x16 ...) => (VCNT16B ...) // pureVreg |
| (OrInt8x16 ...) => (VORR16B ...) // pureVreg |
| (OrInt16x8 ...) => (VORR16B ...) // pureVreg |
| (OrInt32x4 ...) => (VORR16B ...) // pureVreg |
| (OrInt64x2 ...) => (VORR16B ...) // pureVreg |
| (OrUint8x16 ...) => (VORR16B ...) // pureVreg |
| (OrUint16x8 ...) => (VORR16B ...) // pureVreg |
| (OrUint32x4 ...) => (VORR16B ...) // pureVreg |
| (OrUint64x2 ...) => (VORR16B ...) // pureVreg |
| (OrNotInt8x16 ...) => (VORN16B ...) // pureVreg |
| (OrNotInt16x8 ...) => (VORN16B ...) // pureVreg |
| (OrNotInt32x4 ...) => (VORN16B ...) // pureVreg |
| (OrNotInt64x2 ...) => (VORN16B ...) // pureVreg |
| (OrNotUint8x16 ...) => (VORN16B ...) // pureVreg |
| (OrNotUint16x8 ...) => (VORN16B ...) // pureVreg |
| (OrNotUint32x4 ...) => (VORN16B ...) // pureVreg |
| (OrNotUint64x2 ...) => (VORN16B ...) // pureVreg |
| (RoundFloat32x4 ...) => (VFRINTN4S ...) // pureVreg |
| (RoundFloat64x2 ...) => (VFRINTN2D ...) // pureVreg |
| (SaturateToInt8Int16x8 ...) => (VSQXTN8H ...) // pureVreg |
| (SaturateToInt16Int32x4 ...) => (VSQXTN4S ...) // pureVreg |
| (SaturateToInt32Int64x2 ...) => (VSQXTN2D ...) // pureVreg |
| (SaturateToUint8Int16x8 ...) => (VSQXTUN8H ...) // pureVreg |
| (SaturateToUint8Uint16x8 ...) => (VUQXTN8H ...) // pureVreg |
| (SaturateToUint16Int32x4 ...) => (VSQXTUN4S ...) // pureVreg |
| (SaturateToUint16Uint32x4 ...) => (VUQXTN4S ...) // pureVreg |
| (SaturateToUint32Int64x2 ...) => (VSQXTUN2D ...) // pureVreg |
| (SaturateToUint32Uint64x2 ...) => (VUQXTN2D ...) // pureVreg |
| (SetElemFloat32x4 ...) => (VMOVSins0 ...) // pureVreg |
| (VMOVSins0 [0] (VMOVI16B [0]) y:(VDUPSextr [i] _)) => y // specialLower |
| (SetElemFloat64x2 ...) => (VMOVDins0 ...) // pureVreg |
| (VMOVDins0 [0] (VMOVI16B [0]) y:(VDUPDextr [i] _)) => y // specialLower |
| (SetElemInt8x16 ...) => (VMOVBins ...) // pureVreg |
| (SetElemInt16x8 ...) => (VMOVHins ...) // pureVreg |
| (SetElemInt32x4 ...) => (VMOVSins ...) // pureVreg |
| (SetElemInt64x2 ...) => (VMOVDins ...) // pureVreg |
| (SetElemUint8x16 ...) => (VMOVBins ...) // pureVreg |
| (SetElemUint16x8 ...) => (VMOVHins ...) // pureVreg |
| (SetElemUint32x4 ...) => (VMOVSins ...) // pureVreg |
| (SetElemUint64x2 ...) => (VMOVDins ...) // pureVreg |
| (ShiftInt8x16 ...) => (VSSHL16B ...) // pureVreg |
| (ShiftInt16x8 ...) => (VSSHL8H ...) // pureVreg |
| (ShiftInt32x4 ...) => (VSSHL4S ...) // pureVreg |
| (ShiftInt64x2 ...) => (VSSHL2D ...) // pureVreg |
| (ShiftUint8x16 ...) => (VUSHL16B ...) // pureVreg |
| (ShiftUint16x8 ...) => (VUSHL8H ...) // pureVreg |
| (ShiftUint32x4 ...) => (VUSHL4S ...) // pureVreg |
| (ShiftUint64x2 ...) => (VUSHL2D ...) // pureVreg |
| (ShiftAllLeftInt8x16 x y) => (VSSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftInt16x8 x y) => (VSSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftInt32x4 x y) => (VSSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftInt64x2 x y) => (VSSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftUint8x16 x y) => (VUSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftUint16x8 x y) => (VUSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftUint32x4 x y) => (VUSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllLeftUint64x2 x y) => (VUSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y))))) // specialLower |
| (ShiftAllRightInt8x16 x y) => (VSSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightInt16x8 x y) => (VSSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightInt32x4 x y) => (VSSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightInt64x2 x y) => (VSSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightUint8x16 x y) => (VUSHL16B x (VDUPBbcast [0] (VMOVBins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightUint16x8 x y) => (VUSHL8H x (VDUPHbcast [0] (VMOVHins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightUint32x4 x y) => (VUSHL4S x (VDUPSbcast [0] (VMOVSins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftAllRightUint64x2 x y) => (VUSHL2D x (VDUPDbcast [0] (VMOVDins [0] x (NEG <typ.Int64> (CSEL <typ.UInt64> [OpARM64LessThanU] y (MOVDconst [127]) (CMPconst [127] y)))))) // specialLower |
| (ShiftSaturatedInt8x16 ...) => (VSQSHL16B ...) // pureVreg |
| (ShiftSaturatedInt16x8 ...) => (VSQSHL8H ...) // pureVreg |
| (ShiftSaturatedInt32x4 ...) => (VSQSHL4S ...) // pureVreg |
| (ShiftSaturatedInt64x2 ...) => (VSQSHL2D ...) // pureVreg |
| (ShiftSaturatedUint8x16 ...) => (VUQSHL16B ...) // pureVreg |
| (ShiftSaturatedUint16x8 ...) => (VUQSHL8H ...) // pureVreg |
| (ShiftSaturatedUint32x4 ...) => (VUQSHL4S ...) // pureVreg |
| (ShiftSaturatedUint64x2 ...) => (VUQSHL2D ...) // pureVreg |
| (SqrtFloat32x4 ...) => (VFSQRT4S ...) // pureVreg |
| (SqrtFloat64x2 ...) => (VFSQRT2D ...) // pureVreg |
| (SubFloat32x4 ...) => (VFSUB4S ...) // pureVreg |
| (SubFloat64x2 ...) => (VFSUB2D ...) // pureVreg |
| (SubInt8x16 ...) => (VSUB16B ...) // pureVreg |
| (SubInt16x8 ...) => (VSUB8H ...) // pureVreg |
| (SubInt32x4 ...) => (VSUB4S ...) // pureVreg |
| (SubInt64x2 ...) => (VSUB2D ...) // pureVreg |
| (SubUint8x16 ...) => (VSUB16B ...) // pureVreg |
| (SubUint16x8 ...) => (VSUB8H ...) // pureVreg |
| (SubUint32x4 ...) => (VSUB4S ...) // pureVreg |
| (SubUint64x2 ...) => (VSUB2D ...) // pureVreg |
| (SubSaturatedInt8x16 ...) => (VSQSUB16B ...) // pureVreg |
| (SubSaturatedInt16x8 ...) => (VSQSUB8H ...) // pureVreg |
| (SubSaturatedInt32x4 ...) => (VSQSUB4S ...) // pureVreg |
| (SubSaturatedInt64x2 ...) => (VSQSUB2D ...) // pureVreg |
| (SubSaturatedUint8x16 ...) => (VUQSUB16B ...) // pureVreg |
| (SubSaturatedUint16x8 ...) => (VUQSUB8H ...) // pureVreg |
| (SubSaturatedUint32x4 ...) => (VUQSUB4S ...) // pureVreg |
| (SubSaturatedUint64x2 ...) => (VUQSUB2D ...) // pureVreg |
| (TruncFloat32x4 ...) => (VFRINTZ4S ...) // pureVreg |
| (TruncFloat64x2 ...) => (VFRINTZ2D ...) // pureVreg |
| (TruncToInt8Int16x8 ...) => (VXTN8H ...) // pureVreg |
| (TruncToInt16Int32x4 ...) => (VXTN4S ...) // pureVreg |
| (TruncToInt32Int64x2 ...) => (VXTN2D ...) // pureVreg |
| (TruncToUint8Uint16x8 ...) => (VXTN8H ...) // pureVreg |
| (TruncToUint16Uint32x4 ...) => (VXTN4S ...) // pureVreg |
| (TruncToUint32Uint64x2 ...) => (VXTN2D ...) // pureVreg |
| (XorInt8x16 ...) => (VEOR16B ...) // pureVreg |
| (XorInt16x8 ...) => (VEOR16B ...) // pureVreg |
| (XorInt32x4 ...) => (VEOR16B ...) // pureVreg |
| (XorInt64x2 ...) => (VEOR16B ...) // pureVreg |
| (XorUint8x16 ...) => (VEOR16B ...) // pureVreg |
| (XorUint16x8 ...) => (VEOR16B ...) // pureVreg |
| (XorUint32x4 ...) => (VEOR16B ...) // pureVreg |
| (XorUint64x2 ...) => (VEOR16B ...) // pureVreg |
| (bitSelectInt8x16 ...) => (VBIT16B ...) // pureVreg |
| (VBIT16B x y (VNOT16B mask)) => (VBIF16B x y mask) // specialLower |
| (bitSelectNotInt8x16 ...) => (VBIF16B ...) // pureVreg |
| (VBIF16B x y (VNOT16B mask)) => (VBIT16B x y mask) // specialLower |
| (broadcast1To2Float64x2 x) => (VDUPDbcast [0] x) // pureVreg |
| (broadcast1To2Int64x2 x) => (VDUPDbcast [0] x) // pureVreg |
| (broadcast1To2Uint64x2 x) => (VDUPDbcast [0] x) // pureVreg |
| (broadcast1To4Float32x4 x) => (VDUPSbcast [0] x) // pureVreg |
| (broadcast1To4Int32x4 x) => (VDUPSbcast [0] x) // pureVreg |
| (broadcast1To4Uint32x4 x) => (VDUPSbcast [0] x) // pureVreg |
| (broadcast1To8Int16x8 x) => (VDUPHbcast [0] x) // pureVreg |
| (broadcast1To8Uint16x8 x) => (VDUPHbcast [0] x) // pureVreg |
| (broadcast1To16Int8x16 x) => (VDUPBbcast [0] x) // pureVreg |
| (VDUPBbcast [i] (VMOVBins [j] _ (MOVDconst [c]))) && i == j && c>=-128 && c<=255 => (VMOVI16B [uint8(c)]) // specialLower |
| (broadcast1To16Uint8x16 x) => (VDUPBbcast [0] x) // pureVreg |
| (carrylessMultiplyWidenLoUint64x2 ...) => (VPMULL2D ...) // pureVreg |
| (reduceMaxFloat32x4 ...) => (VFMAXV4S ...) // pureVreg |
| (reduceMaxInt8x16 ...) => (VSMAXV16B ...) // pureVreg |
| (reduceMaxInt16x8 ...) => (VSMAXV8H ...) // pureVreg |
| (reduceMaxInt32x4 ...) => (VSMAXV4S ...) // pureVreg |
| (reduceMaxUint8x16 ...) => (VUMAXV16B ...) // pureVreg |
| (reduceMaxUint16x8 ...) => (VUMAXV8H ...) // pureVreg |
| (reduceMaxUint32x4 ...) => (VUMAXV4S ...) // pureVreg |
| (reduceMinFloat32x4 ...) => (VFMINV4S ...) // pureVreg |
| (reduceMinInt8x16 ...) => (VSMINV16B ...) // pureVreg |
| (reduceMinInt16x8 ...) => (VSMINV8H ...) // pureVreg |
| (reduceMinInt32x4 ...) => (VSMINV4S ...) // pureVreg |
| (reduceMinUint8x16 ...) => (VUMINV16B ...) // pureVreg |
| (reduceMinUint16x8 ...) => (VUMINV8H ...) // pureVreg |
| (reduceMinUint32x4 ...) => (VUMINV4S ...) // pureVreg |
| (reduceSumInt8x16 ...) => (VADDV16B ...) // pureVreg |
| (reduceSumInt16x8 ...) => (VADDV8H ...) // pureVreg |
| (reduceSumInt32x4 ...) => (VADDV4S ...) // pureVreg |
| (reduceSumUint8x16 ...) => (VADDV16B ...) // pureVreg |
| (reduceSumUint16x8 ...) => (VADDV8H ...) // pureVreg |
| (reduceSumUint32x4 ...) => (VADDV4S ...) // pureVreg |
| (VSHL16B [a] x) && a==0 => x // asmRule |
| (VSHL8H [a] x) && a==0 => x // asmRule |
| (VSHL4S [a] x) && a==0 => x // asmRule |
| (VSHL2D [a] x) && a==0 => x // asmRule |
| (VSSHR16B [a] x) && a==0 => x // asmRule |
| (VSSHR8H [a] x) && a==0 => x // asmRule |
| (VSSHR4S [a] x) && a==0 => x // asmRule |
| (VSSHR2D [a] x) && a==0 => x // asmRule |
| (VUSHR16B [a] x) && a==0 => x // asmRule |
| (VUSHR8H [a] x) && a==0 => x // asmRule |
| (VUSHR4S [a] x) && a==0 => x // asmRule |
| (VUSHR2D [a] x) && a==0 => x // asmRule |
| (VSQSHL16Bconst [a] x) && a==0 => x // asmRule |
| (VSQSHL8Hconst [a] x) && a==0 => x // asmRule |
| (VSQSHL4Sconst [a] x) && a==0 => x // asmRule |
| (VSQSHL2Dconst [a] x) && a==0 => x // asmRule |
| (VUQSHL16Bconst [a] x) && a==0 => x // asmRule |
| (VUQSHL8Hconst [a] x) && a==0 => x // asmRule |
| (VUQSHL4Sconst [a] x) && a==0 => x // asmRule |
| (VUQSHL2Dconst [a] x) && a==0 => x // asmRule |
| (VSHRN8H [0] x) => (VXTN8H x) // specialLower |
| (VSHRN4S [0] x) => (VXTN4S x) // specialLower |
| (VSHRN2D [0] x) => (VXTN2D x) // specialLower |
