commit e7f5f3eca42a98340e4eb4fc5d490a9aa4bd5054
author fanzha02 <fannie.zhang@arm.com> Mon Sep 10 02:22:48 2018 +0000
committer Cherry Zhang <cherryyz@google.com> Wed Sep 12 15:45:13 2018 +0000
tree b21f9398016f2eaa4e4ab13400845488bc665b56
parent d5377c2026b18e1307c6fd243ece98afc6330b71

cmd/internal/obj/arm64: add error report for invalid base register

The current assembler accepts the non-integer register as the base register,
which should be an illegal combination.

Add the test cases.

Change-Id: Ia21596bbb5b1e212e34bd3a170748ae788860422
Reviewed-on: https://go-review.googlesource.com/134575
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>

src/cmd/asm/internal/asm/testdata/arm64error.s

diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s
index bbdce47..357db80 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64error.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64error.s
@@ -110,4 +110,6 @@
 	FLDPD	(R1), (F2, F2)                                   // ERROR "constrained unpredictable behavior"
 	FLDPS	(R2), (F3, F3)                                   // ERROR "constrained unpredictable behavior"
 	FSTPD	(R1, R2), (R0)                                   // ERROR "invalid register pair"
+	FMOVS	(F2), F0                                         // ERROR "illegal combination"
+	FMOVD	F0, (F1)                                         // ERROR "illegal combination"
 	RET

src/cmd/internal/obj/arm64/asm7.go

diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 09ffc5d..46fdcdc 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -1426,6 +1426,10 @@
 		return C_LIST
 
 	case obj.TYPE_MEM:
+		// The base register should be an integer register.
+		if int16(REG_F0) <= a.Reg && a.Reg <= int16(REG_V31) {
+			break
+		}
 		switch a.Name {
 		case obj.NAME_EXTERN, obj.NAME_STATIC:
 			if a.Sym == nil {
@@ -2968,7 +2972,7 @@
 		}
 
 	case 22: /* movT (R)O!,R; movT O(R)!, R -> ldrT */
-		if p.As != AFMOVS && p.As != AFMOVD && p.From.Reg != REGSP && p.From.Reg == p.To.Reg {
+		if p.From.Reg != REGSP && p.From.Reg == p.To.Reg {
 			c.ctxt.Diag("constrained unpredictable behavior: %v", p)
 		}
 
@@ -2986,7 +2990,7 @@
 		o1 |= ((uint32(v) & 0x1FF) << 12) | (uint32(p.From.Reg&31) << 5) | uint32(p.To.Reg&31)
 
 	case 23: /* movT R,(R)O!; movT O(R)!, R -> strT */
-		if p.As != AFMOVS && p.As != AFMOVD && p.To.Reg != REGSP && p.From.Reg == p.To.Reg {
+		if p.To.Reg != REGSP && p.From.Reg == p.To.Reg {
 			c.ctxt.Diag("constrained unpredictable behavior: %v", p)
 		}