src/simd/archsimd/_gen/simdgen/ops/BitwiseLogic/go_sve.yaml

!sum
# And — bitwise AND, both signednesses. The unpredicated ZAND is a single
# width-agnostic .D encoding that the loader emits at every element width; its
# predicated sibling merges per <T>, so the merging machine ops stay per width.
- go: And
  asm: "ZAND"
  in:
  - &int
    go: $t
    base: int
  - *int
  out:
  - *int

- go: And
  asm: "ZAND"
  in:
  - &uint
    go: $t
    base: uint
  - *uint
  out:
  - *uint

# Or — bitwise inclusive OR, ZORR. Width-agnostic like ZAND.
- go: Or
  asm: "ZORR"
  in:
  - *int
  - *int
  out:
  - *int

- go: Or
  asm: "ZORR"
  in:
  - *uint
  - *uint
  out:
  - *uint

# Xor — bitwise exclusive OR, ZEOR. Width-agnostic like ZAND.
- go: Xor
  asm: "ZEOR"
  in:
  - *int
  - *int
  out:
  - *int

- go: Xor
  asm: "ZEOR"
  in:
  - *uint
  - *uint
  out:
  - *uint

# AndNot — bitwise x &^ y, ZBIC. Width-agnostic like ZAND.
- go: AndNot
  asm: "ZBIC"
  in:
  - *int
  - *int
  out:
  - *int

- go: AndNot
  asm: "ZBIC"
  in:
  - *uint
  - *uint
  out:
  - *uint