| // Code generated from gen/ARM64.rules; DO NOT EDIT. |
| // generated with: cd gen; go run *.go |
| |
| package ssa |
| |
| import "fmt" |
| import "math" |
| import "cmd/internal/obj" |
| import "cmd/internal/objabi" |
| import "cmd/compile/internal/types" |
| |
| var _ = fmt.Println // in case not otherwise used |
| var _ = math.MinInt8 // in case not otherwise used |
| var _ = obj.ANOP // in case not otherwise used |
| var _ = objabi.GOROOT // in case not otherwise used |
| var _ = types.TypeMem // in case not otherwise used |
| |
| func rewriteValueARM64(v *Value) bool { |
| switch v.Op { |
| case OpARM64ADCSflags: |
| return rewriteValueARM64_OpARM64ADCSflags_0(v) |
| case OpARM64ADD: |
| return rewriteValueARM64_OpARM64ADD_0(v) || rewriteValueARM64_OpARM64ADD_10(v) || rewriteValueARM64_OpARM64ADD_20(v) |
| case OpARM64ADDconst: |
| return rewriteValueARM64_OpARM64ADDconst_0(v) |
| case OpARM64ADDshiftLL: |
| return rewriteValueARM64_OpARM64ADDshiftLL_0(v) |
| case OpARM64ADDshiftRA: |
| return rewriteValueARM64_OpARM64ADDshiftRA_0(v) |
| case OpARM64ADDshiftRL: |
| return rewriteValueARM64_OpARM64ADDshiftRL_0(v) |
| case OpARM64AND: |
| return rewriteValueARM64_OpARM64AND_0(v) || rewriteValueARM64_OpARM64AND_10(v) |
| case OpARM64ANDconst: |
| return rewriteValueARM64_OpARM64ANDconst_0(v) |
| case OpARM64ANDshiftLL: |
| return rewriteValueARM64_OpARM64ANDshiftLL_0(v) |
| case OpARM64ANDshiftRA: |
| return rewriteValueARM64_OpARM64ANDshiftRA_0(v) |
| case OpARM64ANDshiftRL: |
| return rewriteValueARM64_OpARM64ANDshiftRL_0(v) |
| case OpARM64BIC: |
| return rewriteValueARM64_OpARM64BIC_0(v) |
| case OpARM64BICshiftLL: |
| return rewriteValueARM64_OpARM64BICshiftLL_0(v) |
| case OpARM64BICshiftRA: |
| return rewriteValueARM64_OpARM64BICshiftRA_0(v) |
| case OpARM64BICshiftRL: |
| return rewriteValueARM64_OpARM64BICshiftRL_0(v) |
| case OpARM64CMN: |
| return rewriteValueARM64_OpARM64CMN_0(v) |
| case OpARM64CMNW: |
| return rewriteValueARM64_OpARM64CMNW_0(v) |
| case OpARM64CMNWconst: |
| return rewriteValueARM64_OpARM64CMNWconst_0(v) |
| case OpARM64CMNconst: |
| return rewriteValueARM64_OpARM64CMNconst_0(v) |
| case OpARM64CMNshiftLL: |
| return rewriteValueARM64_OpARM64CMNshiftLL_0(v) |
| case OpARM64CMNshiftRA: |
| return rewriteValueARM64_OpARM64CMNshiftRA_0(v) |
| case OpARM64CMNshiftRL: |
| return rewriteValueARM64_OpARM64CMNshiftRL_0(v) |
| case OpARM64CMP: |
| return rewriteValueARM64_OpARM64CMP_0(v) |
| case OpARM64CMPW: |
| return rewriteValueARM64_OpARM64CMPW_0(v) |
| case OpARM64CMPWconst: |
| return rewriteValueARM64_OpARM64CMPWconst_0(v) |
| case OpARM64CMPconst: |
| return rewriteValueARM64_OpARM64CMPconst_0(v) |
| case OpARM64CMPshiftLL: |
| return rewriteValueARM64_OpARM64CMPshiftLL_0(v) |
| case OpARM64CMPshiftRA: |
| return rewriteValueARM64_OpARM64CMPshiftRA_0(v) |
| case OpARM64CMPshiftRL: |
| return rewriteValueARM64_OpARM64CMPshiftRL_0(v) |
| case OpARM64CSEL: |
| return rewriteValueARM64_OpARM64CSEL_0(v) |
| case OpARM64CSEL0: |
| return rewriteValueARM64_OpARM64CSEL0_0(v) |
| case OpARM64DIV: |
| return rewriteValueARM64_OpARM64DIV_0(v) |
| case OpARM64DIVW: |
| return rewriteValueARM64_OpARM64DIVW_0(v) |
| case OpARM64EON: |
| return rewriteValueARM64_OpARM64EON_0(v) |
| case OpARM64EONshiftLL: |
| return rewriteValueARM64_OpARM64EONshiftLL_0(v) |
| case OpARM64EONshiftRA: |
| return rewriteValueARM64_OpARM64EONshiftRA_0(v) |
| case OpARM64EONshiftRL: |
| return rewriteValueARM64_OpARM64EONshiftRL_0(v) |
| case OpARM64Equal: |
| return rewriteValueARM64_OpARM64Equal_0(v) |
| case OpARM64FADDD: |
| return rewriteValueARM64_OpARM64FADDD_0(v) |
| case OpARM64FADDS: |
| return rewriteValueARM64_OpARM64FADDS_0(v) |
| case OpARM64FCMPD: |
| return rewriteValueARM64_OpARM64FCMPD_0(v) |
| case OpARM64FCMPS: |
| return rewriteValueARM64_OpARM64FCMPS_0(v) |
| case OpARM64FMOVDfpgp: |
| return rewriteValueARM64_OpARM64FMOVDfpgp_0(v) |
| case OpARM64FMOVDgpfp: |
| return rewriteValueARM64_OpARM64FMOVDgpfp_0(v) |
| case OpARM64FMOVDload: |
| return rewriteValueARM64_OpARM64FMOVDload_0(v) |
| case OpARM64FMOVDloadidx: |
| return rewriteValueARM64_OpARM64FMOVDloadidx_0(v) |
| case OpARM64FMOVDstore: |
| return rewriteValueARM64_OpARM64FMOVDstore_0(v) |
| case OpARM64FMOVDstoreidx: |
| return rewriteValueARM64_OpARM64FMOVDstoreidx_0(v) |
| case OpARM64FMOVSload: |
| return rewriteValueARM64_OpARM64FMOVSload_0(v) |
| case OpARM64FMOVSloadidx: |
| return rewriteValueARM64_OpARM64FMOVSloadidx_0(v) |
| case OpARM64FMOVSstore: |
| return rewriteValueARM64_OpARM64FMOVSstore_0(v) |
| case OpARM64FMOVSstoreidx: |
| return rewriteValueARM64_OpARM64FMOVSstoreidx_0(v) |
| case OpARM64FMULD: |
| return rewriteValueARM64_OpARM64FMULD_0(v) |
| case OpARM64FMULS: |
| return rewriteValueARM64_OpARM64FMULS_0(v) |
| case OpARM64FNEGD: |
| return rewriteValueARM64_OpARM64FNEGD_0(v) |
| case OpARM64FNEGS: |
| return rewriteValueARM64_OpARM64FNEGS_0(v) |
| case OpARM64FNMULD: |
| return rewriteValueARM64_OpARM64FNMULD_0(v) |
| case OpARM64FNMULS: |
| return rewriteValueARM64_OpARM64FNMULS_0(v) |
| case OpARM64FSUBD: |
| return rewriteValueARM64_OpARM64FSUBD_0(v) |
| case OpARM64FSUBS: |
| return rewriteValueARM64_OpARM64FSUBS_0(v) |
| case OpARM64GreaterEqual: |
| return rewriteValueARM64_OpARM64GreaterEqual_0(v) |
| case OpARM64GreaterEqualF: |
| return rewriteValueARM64_OpARM64GreaterEqualF_0(v) |
| case OpARM64GreaterEqualU: |
| return rewriteValueARM64_OpARM64GreaterEqualU_0(v) |
| case OpARM64GreaterThan: |
| return rewriteValueARM64_OpARM64GreaterThan_0(v) |
| case OpARM64GreaterThanF: |
| return rewriteValueARM64_OpARM64GreaterThanF_0(v) |
| case OpARM64GreaterThanU: |
| return rewriteValueARM64_OpARM64GreaterThanU_0(v) |
| case OpARM64LessEqual: |
| return rewriteValueARM64_OpARM64LessEqual_0(v) |
| case OpARM64LessEqualF: |
| return rewriteValueARM64_OpARM64LessEqualF_0(v) |
| case OpARM64LessEqualU: |
| return rewriteValueARM64_OpARM64LessEqualU_0(v) |
| case OpARM64LessThan: |
| return rewriteValueARM64_OpARM64LessThan_0(v) |
| case OpARM64LessThanF: |
| return rewriteValueARM64_OpARM64LessThanF_0(v) |
| case OpARM64LessThanU: |
| return rewriteValueARM64_OpARM64LessThanU_0(v) |
| case OpARM64MADD: |
| return rewriteValueARM64_OpARM64MADD_0(v) || rewriteValueARM64_OpARM64MADD_10(v) || rewriteValueARM64_OpARM64MADD_20(v) |
| case OpARM64MADDW: |
| return rewriteValueARM64_OpARM64MADDW_0(v) || rewriteValueARM64_OpARM64MADDW_10(v) || rewriteValueARM64_OpARM64MADDW_20(v) |
| case OpARM64MNEG: |
| return rewriteValueARM64_OpARM64MNEG_0(v) || rewriteValueARM64_OpARM64MNEG_10(v) || rewriteValueARM64_OpARM64MNEG_20(v) |
| case OpARM64MNEGW: |
| return rewriteValueARM64_OpARM64MNEGW_0(v) || rewriteValueARM64_OpARM64MNEGW_10(v) || rewriteValueARM64_OpARM64MNEGW_20(v) |
| case OpARM64MOD: |
| return rewriteValueARM64_OpARM64MOD_0(v) |
| case OpARM64MODW: |
| return rewriteValueARM64_OpARM64MODW_0(v) |
| case OpARM64MOVBUload: |
| return rewriteValueARM64_OpARM64MOVBUload_0(v) |
| case OpARM64MOVBUloadidx: |
| return rewriteValueARM64_OpARM64MOVBUloadidx_0(v) |
| case OpARM64MOVBUreg: |
| return rewriteValueARM64_OpARM64MOVBUreg_0(v) |
| case OpARM64MOVBload: |
| return rewriteValueARM64_OpARM64MOVBload_0(v) |
| case OpARM64MOVBloadidx: |
| return rewriteValueARM64_OpARM64MOVBloadidx_0(v) |
| case OpARM64MOVBreg: |
| return rewriteValueARM64_OpARM64MOVBreg_0(v) |
| case OpARM64MOVBstore: |
| return rewriteValueARM64_OpARM64MOVBstore_0(v) || rewriteValueARM64_OpARM64MOVBstore_10(v) || rewriteValueARM64_OpARM64MOVBstore_20(v) || rewriteValueARM64_OpARM64MOVBstore_30(v) || rewriteValueARM64_OpARM64MOVBstore_40(v) |
| case OpARM64MOVBstoreidx: |
| return rewriteValueARM64_OpARM64MOVBstoreidx_0(v) || rewriteValueARM64_OpARM64MOVBstoreidx_10(v) |
| case OpARM64MOVBstorezero: |
| return rewriteValueARM64_OpARM64MOVBstorezero_0(v) |
| case OpARM64MOVBstorezeroidx: |
| return rewriteValueARM64_OpARM64MOVBstorezeroidx_0(v) |
| case OpARM64MOVDload: |
| return rewriteValueARM64_OpARM64MOVDload_0(v) |
| case OpARM64MOVDloadidx: |
| return rewriteValueARM64_OpARM64MOVDloadidx_0(v) |
| case OpARM64MOVDloadidx8: |
| return rewriteValueARM64_OpARM64MOVDloadidx8_0(v) |
| case OpARM64MOVDreg: |
| return rewriteValueARM64_OpARM64MOVDreg_0(v) |
| case OpARM64MOVDstore: |
| return rewriteValueARM64_OpARM64MOVDstore_0(v) |
| case OpARM64MOVDstoreidx: |
| return rewriteValueARM64_OpARM64MOVDstoreidx_0(v) |
| case OpARM64MOVDstoreidx8: |
| return rewriteValueARM64_OpARM64MOVDstoreidx8_0(v) |
| case OpARM64MOVDstorezero: |
| return rewriteValueARM64_OpARM64MOVDstorezero_0(v) |
| case OpARM64MOVDstorezeroidx: |
| return rewriteValueARM64_OpARM64MOVDstorezeroidx_0(v) |
| case OpARM64MOVDstorezeroidx8: |
| return rewriteValueARM64_OpARM64MOVDstorezeroidx8_0(v) |
| case OpARM64MOVHUload: |
| return rewriteValueARM64_OpARM64MOVHUload_0(v) |
| case OpARM64MOVHUloadidx: |
| return rewriteValueARM64_OpARM64MOVHUloadidx_0(v) |
| case OpARM64MOVHUloadidx2: |
| return rewriteValueARM64_OpARM64MOVHUloadidx2_0(v) |
| case OpARM64MOVHUreg: |
| return rewriteValueARM64_OpARM64MOVHUreg_0(v) || rewriteValueARM64_OpARM64MOVHUreg_10(v) |
| case OpARM64MOVHload: |
| return rewriteValueARM64_OpARM64MOVHload_0(v) |
| case OpARM64MOVHloadidx: |
| return rewriteValueARM64_OpARM64MOVHloadidx_0(v) |
| case OpARM64MOVHloadidx2: |
| return rewriteValueARM64_OpARM64MOVHloadidx2_0(v) |
| case OpARM64MOVHreg: |
| return rewriteValueARM64_OpARM64MOVHreg_0(v) || rewriteValueARM64_OpARM64MOVHreg_10(v) |
| case OpARM64MOVHstore: |
| return rewriteValueARM64_OpARM64MOVHstore_0(v) || rewriteValueARM64_OpARM64MOVHstore_10(v) || rewriteValueARM64_OpARM64MOVHstore_20(v) |
| case OpARM64MOVHstoreidx: |
| return rewriteValueARM64_OpARM64MOVHstoreidx_0(v) || rewriteValueARM64_OpARM64MOVHstoreidx_10(v) |
| case OpARM64MOVHstoreidx2: |
| return rewriteValueARM64_OpARM64MOVHstoreidx2_0(v) |
| case OpARM64MOVHstorezero: |
| return rewriteValueARM64_OpARM64MOVHstorezero_0(v) |
| case OpARM64MOVHstorezeroidx: |
| return rewriteValueARM64_OpARM64MOVHstorezeroidx_0(v) |
| case OpARM64MOVHstorezeroidx2: |
| return rewriteValueARM64_OpARM64MOVHstorezeroidx2_0(v) |
| case OpARM64MOVQstorezero: |
| return rewriteValueARM64_OpARM64MOVQstorezero_0(v) |
| case OpARM64MOVWUload: |
| return rewriteValueARM64_OpARM64MOVWUload_0(v) |
| case OpARM64MOVWUloadidx: |
| return rewriteValueARM64_OpARM64MOVWUloadidx_0(v) |
| case OpARM64MOVWUloadidx4: |
| return rewriteValueARM64_OpARM64MOVWUloadidx4_0(v) |
| case OpARM64MOVWUreg: |
| return rewriteValueARM64_OpARM64MOVWUreg_0(v) || rewriteValueARM64_OpARM64MOVWUreg_10(v) |
| case OpARM64MOVWload: |
| return rewriteValueARM64_OpARM64MOVWload_0(v) |
| case OpARM64MOVWloadidx: |
| return rewriteValueARM64_OpARM64MOVWloadidx_0(v) |
| case OpARM64MOVWloadidx4: |
| return rewriteValueARM64_OpARM64MOVWloadidx4_0(v) |
| case OpARM64MOVWreg: |
| return rewriteValueARM64_OpARM64MOVWreg_0(v) || rewriteValueARM64_OpARM64MOVWreg_10(v) |
| case OpARM64MOVWstore: |
| return rewriteValueARM64_OpARM64MOVWstore_0(v) || rewriteValueARM64_OpARM64MOVWstore_10(v) |
| case OpARM64MOVWstoreidx: |
| return rewriteValueARM64_OpARM64MOVWstoreidx_0(v) |
| case OpARM64MOVWstoreidx4: |
| return rewriteValueARM64_OpARM64MOVWstoreidx4_0(v) |
| case OpARM64MOVWstorezero: |
| return rewriteValueARM64_OpARM64MOVWstorezero_0(v) |
| case OpARM64MOVWstorezeroidx: |
| return rewriteValueARM64_OpARM64MOVWstorezeroidx_0(v) |
| case OpARM64MOVWstorezeroidx4: |
| return rewriteValueARM64_OpARM64MOVWstorezeroidx4_0(v) |
| case OpARM64MSUB: |
| return rewriteValueARM64_OpARM64MSUB_0(v) || rewriteValueARM64_OpARM64MSUB_10(v) || rewriteValueARM64_OpARM64MSUB_20(v) |
| case OpARM64MSUBW: |
| return rewriteValueARM64_OpARM64MSUBW_0(v) || rewriteValueARM64_OpARM64MSUBW_10(v) || rewriteValueARM64_OpARM64MSUBW_20(v) |
| case OpARM64MUL: |
| return rewriteValueARM64_OpARM64MUL_0(v) || rewriteValueARM64_OpARM64MUL_10(v) || rewriteValueARM64_OpARM64MUL_20(v) |
| case OpARM64MULW: |
| return rewriteValueARM64_OpARM64MULW_0(v) || rewriteValueARM64_OpARM64MULW_10(v) || rewriteValueARM64_OpARM64MULW_20(v) |
| case OpARM64MVN: |
| return rewriteValueARM64_OpARM64MVN_0(v) |
| case OpARM64MVNshiftLL: |
| return rewriteValueARM64_OpARM64MVNshiftLL_0(v) |
| case OpARM64MVNshiftRA: |
| return rewriteValueARM64_OpARM64MVNshiftRA_0(v) |
| case OpARM64MVNshiftRL: |
| return rewriteValueARM64_OpARM64MVNshiftRL_0(v) |
| case OpARM64NEG: |
| return rewriteValueARM64_OpARM64NEG_0(v) |
| case OpARM64NEGshiftLL: |
| return rewriteValueARM64_OpARM64NEGshiftLL_0(v) |
| case OpARM64NEGshiftRA: |
| return rewriteValueARM64_OpARM64NEGshiftRA_0(v) |
| case OpARM64NEGshiftRL: |
| return rewriteValueARM64_OpARM64NEGshiftRL_0(v) |
| case OpARM64NotEqual: |
| return rewriteValueARM64_OpARM64NotEqual_0(v) |
| case OpARM64OR: |
| return rewriteValueARM64_OpARM64OR_0(v) || rewriteValueARM64_OpARM64OR_10(v) || rewriteValueARM64_OpARM64OR_20(v) || rewriteValueARM64_OpARM64OR_30(v) || rewriteValueARM64_OpARM64OR_40(v) |
| case OpARM64ORN: |
| return rewriteValueARM64_OpARM64ORN_0(v) |
| case OpARM64ORNshiftLL: |
| return rewriteValueARM64_OpARM64ORNshiftLL_0(v) |
| case OpARM64ORNshiftRA: |
| return rewriteValueARM64_OpARM64ORNshiftRA_0(v) |
| case OpARM64ORNshiftRL: |
| return rewriteValueARM64_OpARM64ORNshiftRL_0(v) |
| case OpARM64ORconst: |
| return rewriteValueARM64_OpARM64ORconst_0(v) |
| case OpARM64ORshiftLL: |
| return rewriteValueARM64_OpARM64ORshiftLL_0(v) || rewriteValueARM64_OpARM64ORshiftLL_10(v) || rewriteValueARM64_OpARM64ORshiftLL_20(v) |
| case OpARM64ORshiftRA: |
| return rewriteValueARM64_OpARM64ORshiftRA_0(v) |
| case OpARM64ORshiftRL: |
| return rewriteValueARM64_OpARM64ORshiftRL_0(v) |
| case OpARM64RORWconst: |
| return rewriteValueARM64_OpARM64RORWconst_0(v) |
| case OpARM64RORconst: |
| return rewriteValueARM64_OpARM64RORconst_0(v) |
| case OpARM64SBCSflags: |
| return rewriteValueARM64_OpARM64SBCSflags_0(v) |
| case OpARM64SLL: |
| return rewriteValueARM64_OpARM64SLL_0(v) |
| case OpARM64SLLconst: |
| return rewriteValueARM64_OpARM64SLLconst_0(v) |
| case OpARM64SRA: |
| return rewriteValueARM64_OpARM64SRA_0(v) |
| case OpARM64SRAconst: |
| return rewriteValueARM64_OpARM64SRAconst_0(v) |
| case OpARM64SRL: |
| return rewriteValueARM64_OpARM64SRL_0(v) |
| case OpARM64SRLconst: |
| return rewriteValueARM64_OpARM64SRLconst_0(v) || rewriteValueARM64_OpARM64SRLconst_10(v) |
| case OpARM64STP: |
| return rewriteValueARM64_OpARM64STP_0(v) |
| case OpARM64SUB: |
| return rewriteValueARM64_OpARM64SUB_0(v) || rewriteValueARM64_OpARM64SUB_10(v) |
| case OpARM64SUBconst: |
| return rewriteValueARM64_OpARM64SUBconst_0(v) |
| case OpARM64SUBshiftLL: |
| return rewriteValueARM64_OpARM64SUBshiftLL_0(v) |
| case OpARM64SUBshiftRA: |
| return rewriteValueARM64_OpARM64SUBshiftRA_0(v) |
| case OpARM64SUBshiftRL: |
| return rewriteValueARM64_OpARM64SUBshiftRL_0(v) |
| case OpARM64TST: |
| return rewriteValueARM64_OpARM64TST_0(v) |
| case OpARM64TSTW: |
| return rewriteValueARM64_OpARM64TSTW_0(v) |
| case OpARM64TSTWconst: |
| return rewriteValueARM64_OpARM64TSTWconst_0(v) |
| case OpARM64TSTconst: |
| return rewriteValueARM64_OpARM64TSTconst_0(v) |
| case OpARM64TSTshiftLL: |
| return rewriteValueARM64_OpARM64TSTshiftLL_0(v) |
| case OpARM64TSTshiftRA: |
| return rewriteValueARM64_OpARM64TSTshiftRA_0(v) |
| case OpARM64TSTshiftRL: |
| return rewriteValueARM64_OpARM64TSTshiftRL_0(v) |
| case OpARM64UBFIZ: |
| return rewriteValueARM64_OpARM64UBFIZ_0(v) |
| case OpARM64UBFX: |
| return rewriteValueARM64_OpARM64UBFX_0(v) |
| case OpARM64UDIV: |
| return rewriteValueARM64_OpARM64UDIV_0(v) |
| case OpARM64UDIVW: |
| return rewriteValueARM64_OpARM64UDIVW_0(v) |
| case OpARM64UMOD: |
| return rewriteValueARM64_OpARM64UMOD_0(v) |
| case OpARM64UMODW: |
| return rewriteValueARM64_OpARM64UMODW_0(v) |
| case OpARM64XOR: |
| return rewriteValueARM64_OpARM64XOR_0(v) || rewriteValueARM64_OpARM64XOR_10(v) |
| case OpARM64XORconst: |
| return rewriteValueARM64_OpARM64XORconst_0(v) |
| case OpARM64XORshiftLL: |
| return rewriteValueARM64_OpARM64XORshiftLL_0(v) |
| case OpARM64XORshiftRA: |
| return rewriteValueARM64_OpARM64XORshiftRA_0(v) |
| case OpARM64XORshiftRL: |
| return rewriteValueARM64_OpARM64XORshiftRL_0(v) |
| case OpAbs: |
| return rewriteValueARM64_OpAbs_0(v) |
| case OpAdd16: |
| return rewriteValueARM64_OpAdd16_0(v) |
| case OpAdd32: |
| return rewriteValueARM64_OpAdd32_0(v) |
| case OpAdd32F: |
| return rewriteValueARM64_OpAdd32F_0(v) |
| case OpAdd64: |
| return rewriteValueARM64_OpAdd64_0(v) |
| case OpAdd64F: |
| return rewriteValueARM64_OpAdd64F_0(v) |
| case OpAdd8: |
| return rewriteValueARM64_OpAdd8_0(v) |
| case OpAddPtr: |
| return rewriteValueARM64_OpAddPtr_0(v) |
| case OpAddr: |
| return rewriteValueARM64_OpAddr_0(v) |
| case OpAnd16: |
| return rewriteValueARM64_OpAnd16_0(v) |
| case OpAnd32: |
| return rewriteValueARM64_OpAnd32_0(v) |
| case OpAnd64: |
| return rewriteValueARM64_OpAnd64_0(v) |
| case OpAnd8: |
| return rewriteValueARM64_OpAnd8_0(v) |
| case OpAndB: |
| return rewriteValueARM64_OpAndB_0(v) |
| case OpAtomicAdd32: |
| return rewriteValueARM64_OpAtomicAdd32_0(v) |
| case OpAtomicAdd32Variant: |
| return rewriteValueARM64_OpAtomicAdd32Variant_0(v) |
| case OpAtomicAdd64: |
| return rewriteValueARM64_OpAtomicAdd64_0(v) |
| case OpAtomicAdd64Variant: |
| return rewriteValueARM64_OpAtomicAdd64Variant_0(v) |
| case OpAtomicAnd8: |
| return rewriteValueARM64_OpAtomicAnd8_0(v) |
| case OpAtomicCompareAndSwap32: |
| return rewriteValueARM64_OpAtomicCompareAndSwap32_0(v) |
| case OpAtomicCompareAndSwap64: |
| return rewriteValueARM64_OpAtomicCompareAndSwap64_0(v) |
| case OpAtomicExchange32: |
| return rewriteValueARM64_OpAtomicExchange32_0(v) |
| case OpAtomicExchange64: |
| return rewriteValueARM64_OpAtomicExchange64_0(v) |
| case OpAtomicLoad32: |
| return rewriteValueARM64_OpAtomicLoad32_0(v) |
| case OpAtomicLoad64: |
| return rewriteValueARM64_OpAtomicLoad64_0(v) |
| case OpAtomicLoad8: |
| return rewriteValueARM64_OpAtomicLoad8_0(v) |
| case OpAtomicLoadPtr: |
| return rewriteValueARM64_OpAtomicLoadPtr_0(v) |
| case OpAtomicOr8: |
| return rewriteValueARM64_OpAtomicOr8_0(v) |
| case OpAtomicStore32: |
| return rewriteValueARM64_OpAtomicStore32_0(v) |
| case OpAtomicStore64: |
| return rewriteValueARM64_OpAtomicStore64_0(v) |
| case OpAtomicStorePtrNoWB: |
| return rewriteValueARM64_OpAtomicStorePtrNoWB_0(v) |
| case OpAvg64u: |
| return rewriteValueARM64_OpAvg64u_0(v) |
| case OpBitLen32: |
| return rewriteValueARM64_OpBitLen32_0(v) |
| case OpBitLen64: |
| return rewriteValueARM64_OpBitLen64_0(v) |
| case OpBitRev16: |
| return rewriteValueARM64_OpBitRev16_0(v) |
| case OpBitRev32: |
| return rewriteValueARM64_OpBitRev32_0(v) |
| case OpBitRev64: |
| return rewriteValueARM64_OpBitRev64_0(v) |
| case OpBitRev8: |
| return rewriteValueARM64_OpBitRev8_0(v) |
| case OpBswap32: |
| return rewriteValueARM64_OpBswap32_0(v) |
| case OpBswap64: |
| return rewriteValueARM64_OpBswap64_0(v) |
| case OpCeil: |
| return rewriteValueARM64_OpCeil_0(v) |
| case OpClosureCall: |
| return rewriteValueARM64_OpClosureCall_0(v) |
| case OpCom16: |
| return rewriteValueARM64_OpCom16_0(v) |
| case OpCom32: |
| return rewriteValueARM64_OpCom32_0(v) |
| case OpCom64: |
| return rewriteValueARM64_OpCom64_0(v) |
| case OpCom8: |
| return rewriteValueARM64_OpCom8_0(v) |
| case OpCondSelect: |
| return rewriteValueARM64_OpCondSelect_0(v) |
| case OpConst16: |
| return rewriteValueARM64_OpConst16_0(v) |
| case OpConst32: |
| return rewriteValueARM64_OpConst32_0(v) |
| case OpConst32F: |
| return rewriteValueARM64_OpConst32F_0(v) |
| case OpConst64: |
| return rewriteValueARM64_OpConst64_0(v) |
| case OpConst64F: |
| return rewriteValueARM64_OpConst64F_0(v) |
| case OpConst8: |
| return rewriteValueARM64_OpConst8_0(v) |
| case OpConstBool: |
| return rewriteValueARM64_OpConstBool_0(v) |
| case OpConstNil: |
| return rewriteValueARM64_OpConstNil_0(v) |
| case OpCtz16: |
| return rewriteValueARM64_OpCtz16_0(v) |
| case OpCtz16NonZero: |
| return rewriteValueARM64_OpCtz16NonZero_0(v) |
| case OpCtz32: |
| return rewriteValueARM64_OpCtz32_0(v) |
| case OpCtz32NonZero: |
| return rewriteValueARM64_OpCtz32NonZero_0(v) |
| case OpCtz64: |
| return rewriteValueARM64_OpCtz64_0(v) |
| case OpCtz64NonZero: |
| return rewriteValueARM64_OpCtz64NonZero_0(v) |
| case OpCtz8: |
| return rewriteValueARM64_OpCtz8_0(v) |
| case OpCtz8NonZero: |
| return rewriteValueARM64_OpCtz8NonZero_0(v) |
| case OpCvt32Fto32: |
| return rewriteValueARM64_OpCvt32Fto32_0(v) |
| case OpCvt32Fto32U: |
| return rewriteValueARM64_OpCvt32Fto32U_0(v) |
| case OpCvt32Fto64: |
| return rewriteValueARM64_OpCvt32Fto64_0(v) |
| case OpCvt32Fto64F: |
| return rewriteValueARM64_OpCvt32Fto64F_0(v) |
| case OpCvt32Fto64U: |
| return rewriteValueARM64_OpCvt32Fto64U_0(v) |
| case OpCvt32Uto32F: |
| return rewriteValueARM64_OpCvt32Uto32F_0(v) |
| case OpCvt32Uto64F: |
| return rewriteValueARM64_OpCvt32Uto64F_0(v) |
| case OpCvt32to32F: |
| return rewriteValueARM64_OpCvt32to32F_0(v) |
| case OpCvt32to64F: |
| return rewriteValueARM64_OpCvt32to64F_0(v) |
| case OpCvt64Fto32: |
| return rewriteValueARM64_OpCvt64Fto32_0(v) |
| case OpCvt64Fto32F: |
| return rewriteValueARM64_OpCvt64Fto32F_0(v) |
| case OpCvt64Fto32U: |
| return rewriteValueARM64_OpCvt64Fto32U_0(v) |
| case OpCvt64Fto64: |
| return rewriteValueARM64_OpCvt64Fto64_0(v) |
| case OpCvt64Fto64U: |
| return rewriteValueARM64_OpCvt64Fto64U_0(v) |
| case OpCvt64Uto32F: |
| return rewriteValueARM64_OpCvt64Uto32F_0(v) |
| case OpCvt64Uto64F: |
| return rewriteValueARM64_OpCvt64Uto64F_0(v) |
| case OpCvt64to32F: |
| return rewriteValueARM64_OpCvt64to32F_0(v) |
| case OpCvt64to64F: |
| return rewriteValueARM64_OpCvt64to64F_0(v) |
| case OpDiv16: |
| return rewriteValueARM64_OpDiv16_0(v) |
| case OpDiv16u: |
| return rewriteValueARM64_OpDiv16u_0(v) |
| case OpDiv32: |
| return rewriteValueARM64_OpDiv32_0(v) |
| case OpDiv32F: |
| return rewriteValueARM64_OpDiv32F_0(v) |
| case OpDiv32u: |
| return rewriteValueARM64_OpDiv32u_0(v) |
| case OpDiv64: |
| return rewriteValueARM64_OpDiv64_0(v) |
| case OpDiv64F: |
| return rewriteValueARM64_OpDiv64F_0(v) |
| case OpDiv64u: |
| return rewriteValueARM64_OpDiv64u_0(v) |
| case OpDiv8: |
| return rewriteValueARM64_OpDiv8_0(v) |
| case OpDiv8u: |
| return rewriteValueARM64_OpDiv8u_0(v) |
| case OpEq16: |
| return rewriteValueARM64_OpEq16_0(v) |
| case OpEq32: |
| return rewriteValueARM64_OpEq32_0(v) |
| case OpEq32F: |
| return rewriteValueARM64_OpEq32F_0(v) |
| case OpEq64: |
| return rewriteValueARM64_OpEq64_0(v) |
| case OpEq64F: |
| return rewriteValueARM64_OpEq64F_0(v) |
| case OpEq8: |
| return rewriteValueARM64_OpEq8_0(v) |
| case OpEqB: |
| return rewriteValueARM64_OpEqB_0(v) |
| case OpEqPtr: |
| return rewriteValueARM64_OpEqPtr_0(v) |
| case OpFloor: |
| return rewriteValueARM64_OpFloor_0(v) |
| case OpGeq16: |
| return rewriteValueARM64_OpGeq16_0(v) |
| case OpGeq16U: |
| return rewriteValueARM64_OpGeq16U_0(v) |
| case OpGeq32: |
| return rewriteValueARM64_OpGeq32_0(v) |
| case OpGeq32F: |
| return rewriteValueARM64_OpGeq32F_0(v) |
| case OpGeq32U: |
| return rewriteValueARM64_OpGeq32U_0(v) |
| case OpGeq64: |
| return rewriteValueARM64_OpGeq64_0(v) |
| case OpGeq64F: |
| return rewriteValueARM64_OpGeq64F_0(v) |
| case OpGeq64U: |
| return rewriteValueARM64_OpGeq64U_0(v) |
| case OpGeq8: |
| return rewriteValueARM64_OpGeq8_0(v) |
| case OpGeq8U: |
| return rewriteValueARM64_OpGeq8U_0(v) |
| case OpGetCallerPC: |
| return rewriteValueARM64_OpGetCallerPC_0(v) |
| case OpGetCallerSP: |
| return rewriteValueARM64_OpGetCallerSP_0(v) |
| case OpGetClosurePtr: |
| return rewriteValueARM64_OpGetClosurePtr_0(v) |
| case OpGreater16: |
| return rewriteValueARM64_OpGreater16_0(v) |
| case OpGreater16U: |
| return rewriteValueARM64_OpGreater16U_0(v) |
| case OpGreater32: |
| return rewriteValueARM64_OpGreater32_0(v) |
| case OpGreater32F: |
| return rewriteValueARM64_OpGreater32F_0(v) |
| case OpGreater32U: |
| return rewriteValueARM64_OpGreater32U_0(v) |
| case OpGreater64: |
| return rewriteValueARM64_OpGreater64_0(v) |
| case OpGreater64F: |
| return rewriteValueARM64_OpGreater64F_0(v) |
| case OpGreater64U: |
| return rewriteValueARM64_OpGreater64U_0(v) |
| case OpGreater8: |
| return rewriteValueARM64_OpGreater8_0(v) |
| case OpGreater8U: |
| return rewriteValueARM64_OpGreater8U_0(v) |
| case OpHmul32: |
| return rewriteValueARM64_OpHmul32_0(v) |
| case OpHmul32u: |
| return rewriteValueARM64_OpHmul32u_0(v) |
| case OpHmul64: |
| return rewriteValueARM64_OpHmul64_0(v) |
| case OpHmul64u: |
| return rewriteValueARM64_OpHmul64u_0(v) |
| case OpInterCall: |
| return rewriteValueARM64_OpInterCall_0(v) |
| case OpIsInBounds: |
| return rewriteValueARM64_OpIsInBounds_0(v) |
| case OpIsNonNil: |
| return rewriteValueARM64_OpIsNonNil_0(v) |
| case OpIsSliceInBounds: |
| return rewriteValueARM64_OpIsSliceInBounds_0(v) |
| case OpLeq16: |
| return rewriteValueARM64_OpLeq16_0(v) |
| case OpLeq16U: |
| return rewriteValueARM64_OpLeq16U_0(v) |
| case OpLeq32: |
| return rewriteValueARM64_OpLeq32_0(v) |
| case OpLeq32F: |
| return rewriteValueARM64_OpLeq32F_0(v) |
| case OpLeq32U: |
| return rewriteValueARM64_OpLeq32U_0(v) |
| case OpLeq64: |
| return rewriteValueARM64_OpLeq64_0(v) |
| case OpLeq64F: |
| return rewriteValueARM64_OpLeq64F_0(v) |
| case OpLeq64U: |
| return rewriteValueARM64_OpLeq64U_0(v) |
| case OpLeq8: |
| return rewriteValueARM64_OpLeq8_0(v) |
| case OpLeq8U: |
| return rewriteValueARM64_OpLeq8U_0(v) |
| case OpLess16: |
| return rewriteValueARM64_OpLess16_0(v) |
| case OpLess16U: |
| return rewriteValueARM64_OpLess16U_0(v) |
| case OpLess32: |
| return rewriteValueARM64_OpLess32_0(v) |
| case OpLess32F: |
| return rewriteValueARM64_OpLess32F_0(v) |
| case OpLess32U: |
| return rewriteValueARM64_OpLess32U_0(v) |
| case OpLess64: |
| return rewriteValueARM64_OpLess64_0(v) |
| case OpLess64F: |
| return rewriteValueARM64_OpLess64F_0(v) |
| case OpLess64U: |
| return rewriteValueARM64_OpLess64U_0(v) |
| case OpLess8: |
| return rewriteValueARM64_OpLess8_0(v) |
| case OpLess8U: |
| return rewriteValueARM64_OpLess8U_0(v) |
| case OpLoad: |
| return rewriteValueARM64_OpLoad_0(v) |
| case OpLocalAddr: |
| return rewriteValueARM64_OpLocalAddr_0(v) |
| case OpLsh16x16: |
| return rewriteValueARM64_OpLsh16x16_0(v) |
| case OpLsh16x32: |
| return rewriteValueARM64_OpLsh16x32_0(v) |
| case OpLsh16x64: |
| return rewriteValueARM64_OpLsh16x64_0(v) |
| case OpLsh16x8: |
| return rewriteValueARM64_OpLsh16x8_0(v) |
| case OpLsh32x16: |
| return rewriteValueARM64_OpLsh32x16_0(v) |
| case OpLsh32x32: |
| return rewriteValueARM64_OpLsh32x32_0(v) |
| case OpLsh32x64: |
| return rewriteValueARM64_OpLsh32x64_0(v) |
| case OpLsh32x8: |
| return rewriteValueARM64_OpLsh32x8_0(v) |
| case OpLsh64x16: |
| return rewriteValueARM64_OpLsh64x16_0(v) |
| case OpLsh64x32: |
| return rewriteValueARM64_OpLsh64x32_0(v) |
| case OpLsh64x64: |
| return rewriteValueARM64_OpLsh64x64_0(v) |
| case OpLsh64x8: |
| return rewriteValueARM64_OpLsh64x8_0(v) |
| case OpLsh8x16: |
| return rewriteValueARM64_OpLsh8x16_0(v) |
| case OpLsh8x32: |
| return rewriteValueARM64_OpLsh8x32_0(v) |
| case OpLsh8x64: |
| return rewriteValueARM64_OpLsh8x64_0(v) |
| case OpLsh8x8: |
| return rewriteValueARM64_OpLsh8x8_0(v) |
| case OpMod16: |
| return rewriteValueARM64_OpMod16_0(v) |
| case OpMod16u: |
| return rewriteValueARM64_OpMod16u_0(v) |
| case OpMod32: |
| return rewriteValueARM64_OpMod32_0(v) |
| case OpMod32u: |
| return rewriteValueARM64_OpMod32u_0(v) |
| case OpMod64: |
| return rewriteValueARM64_OpMod64_0(v) |
| case OpMod64u: |
| return rewriteValueARM64_OpMod64u_0(v) |
| case OpMod8: |
| return rewriteValueARM64_OpMod8_0(v) |
| case OpMod8u: |
| return rewriteValueARM64_OpMod8u_0(v) |
| case OpMove: |
| return rewriteValueARM64_OpMove_0(v) || rewriteValueARM64_OpMove_10(v) |
| case OpMul16: |
| return rewriteValueARM64_OpMul16_0(v) |
| case OpMul32: |
| return rewriteValueARM64_OpMul32_0(v) |
| case OpMul32F: |
| return rewriteValueARM64_OpMul32F_0(v) |
| case OpMul64: |
| return rewriteValueARM64_OpMul64_0(v) |
| case OpMul64F: |
| return rewriteValueARM64_OpMul64F_0(v) |
| case OpMul64uhilo: |
| return rewriteValueARM64_OpMul64uhilo_0(v) |
| case OpMul8: |
| return rewriteValueARM64_OpMul8_0(v) |
| case OpNeg16: |
| return rewriteValueARM64_OpNeg16_0(v) |
| case OpNeg32: |
| return rewriteValueARM64_OpNeg32_0(v) |
| case OpNeg32F: |
| return rewriteValueARM64_OpNeg32F_0(v) |
| case OpNeg64: |
| return rewriteValueARM64_OpNeg64_0(v) |
| case OpNeg64F: |
| return rewriteValueARM64_OpNeg64F_0(v) |
| case OpNeg8: |
| return rewriteValueARM64_OpNeg8_0(v) |
| case OpNeq16: |
| return rewriteValueARM64_OpNeq16_0(v) |
| case OpNeq32: |
| return rewriteValueARM64_OpNeq32_0(v) |
| case OpNeq32F: |
| return rewriteValueARM64_OpNeq32F_0(v) |
| case OpNeq64: |
| return rewriteValueARM64_OpNeq64_0(v) |
| case OpNeq64F: |
| return rewriteValueARM64_OpNeq64F_0(v) |
| case OpNeq8: |
| return rewriteValueARM64_OpNeq8_0(v) |
| case OpNeqB: |
| return rewriteValueARM64_OpNeqB_0(v) |
| case OpNeqPtr: |
| return rewriteValueARM64_OpNeqPtr_0(v) |
| case OpNilCheck: |
| return rewriteValueARM64_OpNilCheck_0(v) |
| case OpNot: |
| return rewriteValueARM64_OpNot_0(v) |
| case OpOffPtr: |
| return rewriteValueARM64_OpOffPtr_0(v) |
| case OpOr16: |
| return rewriteValueARM64_OpOr16_0(v) |
| case OpOr32: |
| return rewriteValueARM64_OpOr32_0(v) |
| case OpOr64: |
| return rewriteValueARM64_OpOr64_0(v) |
| case OpOr8: |
| return rewriteValueARM64_OpOr8_0(v) |
| case OpOrB: |
| return rewriteValueARM64_OpOrB_0(v) |
| case OpPanicBounds: |
| return rewriteValueARM64_OpPanicBounds_0(v) |
| case OpPopCount16: |
| return rewriteValueARM64_OpPopCount16_0(v) |
| case OpPopCount32: |
| return rewriteValueARM64_OpPopCount32_0(v) |
| case OpPopCount64: |
| return rewriteValueARM64_OpPopCount64_0(v) |
| case OpRotateLeft16: |
| return rewriteValueARM64_OpRotateLeft16_0(v) |
| case OpRotateLeft32: |
| return rewriteValueARM64_OpRotateLeft32_0(v) |
| case OpRotateLeft64: |
| return rewriteValueARM64_OpRotateLeft64_0(v) |
| case OpRotateLeft8: |
| return rewriteValueARM64_OpRotateLeft8_0(v) |
| case OpRound: |
| return rewriteValueARM64_OpRound_0(v) |
| case OpRound32F: |
| return rewriteValueARM64_OpRound32F_0(v) |
| case OpRound64F: |
| return rewriteValueARM64_OpRound64F_0(v) |
| case OpRoundToEven: |
| return rewriteValueARM64_OpRoundToEven_0(v) |
| case OpRsh16Ux16: |
| return rewriteValueARM64_OpRsh16Ux16_0(v) |
| case OpRsh16Ux32: |
| return rewriteValueARM64_OpRsh16Ux32_0(v) |
| case OpRsh16Ux64: |
| return rewriteValueARM64_OpRsh16Ux64_0(v) |
| case OpRsh16Ux8: |
| return rewriteValueARM64_OpRsh16Ux8_0(v) |
| case OpRsh16x16: |
| return rewriteValueARM64_OpRsh16x16_0(v) |
| case OpRsh16x32: |
| return rewriteValueARM64_OpRsh16x32_0(v) |
| case OpRsh16x64: |
| return rewriteValueARM64_OpRsh16x64_0(v) |
| case OpRsh16x8: |
| return rewriteValueARM64_OpRsh16x8_0(v) |
| case OpRsh32Ux16: |
| return rewriteValueARM64_OpRsh32Ux16_0(v) |
| case OpRsh32Ux32: |
| return rewriteValueARM64_OpRsh32Ux32_0(v) |
| case OpRsh32Ux64: |
| return rewriteValueARM64_OpRsh32Ux64_0(v) |
| case OpRsh32Ux8: |
| return rewriteValueARM64_OpRsh32Ux8_0(v) |
| case OpRsh32x16: |
| return rewriteValueARM64_OpRsh32x16_0(v) |
| case OpRsh32x32: |
| return rewriteValueARM64_OpRsh32x32_0(v) |
| case OpRsh32x64: |
| return rewriteValueARM64_OpRsh32x64_0(v) |
| case OpRsh32x8: |
| return rewriteValueARM64_OpRsh32x8_0(v) |
| case OpRsh64Ux16: |
| return rewriteValueARM64_OpRsh64Ux16_0(v) |
| case OpRsh64Ux32: |
| return rewriteValueARM64_OpRsh64Ux32_0(v) |
| case OpRsh64Ux64: |
| return rewriteValueARM64_OpRsh64Ux64_0(v) |
| case OpRsh64Ux8: |
| return rewriteValueARM64_OpRsh64Ux8_0(v) |
| case OpRsh64x16: |
| return rewriteValueARM64_OpRsh64x16_0(v) |
| case OpRsh64x32: |
| return rewriteValueARM64_OpRsh64x32_0(v) |
| case OpRsh64x64: |
| return rewriteValueARM64_OpRsh64x64_0(v) |
| case OpRsh64x8: |
| return rewriteValueARM64_OpRsh64x8_0(v) |
| case OpRsh8Ux16: |
| return rewriteValueARM64_OpRsh8Ux16_0(v) |
| case OpRsh8Ux32: |
| return rewriteValueARM64_OpRsh8Ux32_0(v) |
| case OpRsh8Ux64: |
| return rewriteValueARM64_OpRsh8Ux64_0(v) |
| case OpRsh8Ux8: |
| return rewriteValueARM64_OpRsh8Ux8_0(v) |
| case OpRsh8x16: |
| return rewriteValueARM64_OpRsh8x16_0(v) |
| case OpRsh8x32: |
| return rewriteValueARM64_OpRsh8x32_0(v) |
| case OpRsh8x64: |
| return rewriteValueARM64_OpRsh8x64_0(v) |
| case OpRsh8x8: |
| return rewriteValueARM64_OpRsh8x8_0(v) |
| case OpSelect0: |
| return rewriteValueARM64_OpSelect0_0(v) |
| case OpSelect1: |
| return rewriteValueARM64_OpSelect1_0(v) |
| case OpSignExt16to32: |
| return rewriteValueARM64_OpSignExt16to32_0(v) |
| case OpSignExt16to64: |
| return rewriteValueARM64_OpSignExt16to64_0(v) |
| case OpSignExt32to64: |
| return rewriteValueARM64_OpSignExt32to64_0(v) |
| case OpSignExt8to16: |
| return rewriteValueARM64_OpSignExt8to16_0(v) |
| case OpSignExt8to32: |
| return rewriteValueARM64_OpSignExt8to32_0(v) |
| case OpSignExt8to64: |
| return rewriteValueARM64_OpSignExt8to64_0(v) |
| case OpSlicemask: |
| return rewriteValueARM64_OpSlicemask_0(v) |
| case OpSqrt: |
| return rewriteValueARM64_OpSqrt_0(v) |
| case OpStaticCall: |
| return rewriteValueARM64_OpStaticCall_0(v) |
| case OpStore: |
| return rewriteValueARM64_OpStore_0(v) |
| case OpSub16: |
| return rewriteValueARM64_OpSub16_0(v) |
| case OpSub32: |
| return rewriteValueARM64_OpSub32_0(v) |
| case OpSub32F: |
| return rewriteValueARM64_OpSub32F_0(v) |
| case OpSub64: |
| return rewriteValueARM64_OpSub64_0(v) |
| case OpSub64F: |
| return rewriteValueARM64_OpSub64F_0(v) |
| case OpSub8: |
| return rewriteValueARM64_OpSub8_0(v) |
| case OpSubPtr: |
| return rewriteValueARM64_OpSubPtr_0(v) |
| case OpTrunc: |
| return rewriteValueARM64_OpTrunc_0(v) |
| case OpTrunc16to8: |
| return rewriteValueARM64_OpTrunc16to8_0(v) |
| case OpTrunc32to16: |
| return rewriteValueARM64_OpTrunc32to16_0(v) |
| case OpTrunc32to8: |
| return rewriteValueARM64_OpTrunc32to8_0(v) |
| case OpTrunc64to16: |
| return rewriteValueARM64_OpTrunc64to16_0(v) |
| case OpTrunc64to32: |
| return rewriteValueARM64_OpTrunc64to32_0(v) |
| case OpTrunc64to8: |
| return rewriteValueARM64_OpTrunc64to8_0(v) |
| case OpWB: |
| return rewriteValueARM64_OpWB_0(v) |
| case OpXor16: |
| return rewriteValueARM64_OpXor16_0(v) |
| case OpXor32: |
| return rewriteValueARM64_OpXor32_0(v) |
| case OpXor64: |
| return rewriteValueARM64_OpXor64_0(v) |
| case OpXor8: |
| return rewriteValueARM64_OpXor8_0(v) |
| case OpZero: |
| return rewriteValueARM64_OpZero_0(v) || rewriteValueARM64_OpZero_10(v) || rewriteValueARM64_OpZero_20(v) |
| case OpZeroExt16to32: |
| return rewriteValueARM64_OpZeroExt16to32_0(v) |
| case OpZeroExt16to64: |
| return rewriteValueARM64_OpZeroExt16to64_0(v) |
| case OpZeroExt32to64: |
| return rewriteValueARM64_OpZeroExt32to64_0(v) |
| case OpZeroExt8to16: |
| return rewriteValueARM64_OpZeroExt8to16_0(v) |
| case OpZeroExt8to32: |
| return rewriteValueARM64_OpZeroExt8to32_0(v) |
| case OpZeroExt8to64: |
| return rewriteValueARM64_OpZeroExt8to64_0(v) |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADCSflags_0(v *Value) bool { |
| b := v.Block |
| typ := &b.Func.Config.Types |
| // match: (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (ADCzerocarry <typ.UInt64> c)))) |
| // cond: |
| // result: (ADCSflags x y c) |
| for { |
| _ = v.Args[2] |
| x := v.Args[0] |
| y := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpSelect1 { |
| break |
| } |
| if v_2.Type != types.TypeFlags { |
| break |
| } |
| v_2_0 := v_2.Args[0] |
| if v_2_0.Op != OpARM64ADDSconstflags { |
| break |
| } |
| if v_2_0.AuxInt != -1 { |
| break |
| } |
| v_2_0_0 := v_2_0.Args[0] |
| if v_2_0_0.Op != OpARM64ADCzerocarry { |
| break |
| } |
| if v_2_0_0.Type != typ.UInt64 { |
| break |
| } |
| c := v_2_0_0.Args[0] |
| v.reset(OpARM64ADCSflags) |
| v.AddArg(x) |
| v.AddArg(y) |
| v.AddArg(c) |
| return true |
| } |
| // match: (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (MOVDconst [0])))) |
| // cond: |
| // result: (ADDSflags x y) |
| for { |
| _ = v.Args[2] |
| x := v.Args[0] |
| y := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpSelect1 { |
| break |
| } |
| if v_2.Type != types.TypeFlags { |
| break |
| } |
| v_2_0 := v_2.Args[0] |
| if v_2_0.Op != OpARM64ADDSconstflags { |
| break |
| } |
| if v_2_0.AuxInt != -1 { |
| break |
| } |
| v_2_0_0 := v_2_0.Args[0] |
| if v_2_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2_0_0.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64ADDSflags) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADD_0(v *Value) bool { |
| // match: (ADD x (MOVDconst [c])) |
| // cond: |
| // result: (ADDconst [c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADD (MOVDconst [c]) x) |
| // cond: |
| // result: (ADDconst [c] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADD a l:(MUL x y)) |
| // cond: l.Uses==1 && clobber(l) |
| // result: (MADD a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| l := v.Args[1] |
| if l.Op != OpARM64MUL { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD l:(MUL x y) a) |
| // cond: l.Uses==1 && clobber(l) |
| // result: (MADD a x y) |
| for { |
| a := v.Args[1] |
| l := v.Args[0] |
| if l.Op != OpARM64MUL { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD a l:(MNEG x y)) |
| // cond: l.Uses==1 && clobber(l) |
| // result: (MSUB a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| l := v.Args[1] |
| if l.Op != OpARM64MNEG { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MSUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD l:(MNEG x y) a) |
| // cond: l.Uses==1 && clobber(l) |
| // result: (MSUB a x y) |
| for { |
| a := v.Args[1] |
| l := v.Args[0] |
| if l.Op != OpARM64MNEG { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MSUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD a l:(MULW x y)) |
| // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) |
| // result: (MADDW a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| l := v.Args[1] |
| if l.Op != OpARM64MULW { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MADDW) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD l:(MULW x y) a) |
| // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) |
| // result: (MADDW a x y) |
| for { |
| a := v.Args[1] |
| l := v.Args[0] |
| if l.Op != OpARM64MULW { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MADDW) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD a l:(MNEGW x y)) |
| // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) |
| // result: (MSUBW a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| l := v.Args[1] |
| if l.Op != OpARM64MNEGW { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MSUBW) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD l:(MNEGW x y) a) |
| // cond: a.Type.Size() != 8 && l.Uses==1 && clobber(l) |
| // result: (MSUBW a x y) |
| for { |
| a := v.Args[1] |
| l := v.Args[0] |
| if l.Op != OpARM64MNEGW { |
| break |
| } |
| y := l.Args[1] |
| x := l.Args[0] |
| if !(a.Type.Size() != 8 && l.Uses == 1 && clobber(l)) { |
| break |
| } |
| v.reset(OpARM64MSUBW) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADD_10(v *Value) bool { |
| b := v.Block |
| typ := &b.Func.Config.Types |
| // match: (ADD x (NEG y)) |
| // cond: |
| // result: (SUB x y) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64NEG { |
| break |
| } |
| y := v_1.Args[0] |
| v.reset(OpARM64SUB) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD (NEG y) x) |
| // cond: |
| // result: (SUB x y) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64NEG { |
| break |
| } |
| y := v_0.Args[0] |
| v.reset(OpARM64SUB) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ADDshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD x1:(SLLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ADDshiftLL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ADDshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD x1:(SRLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ADDshiftRL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ADDshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD x1:(SRAconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ADDshiftRA x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD (SLL x (ANDconst <t> [63] y)) (CSEL0 <typ.UInt64> {cc} (SRL <typ.UInt64> x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0.Args[1] |
| x := v_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt64 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SRL { |
| break |
| } |
| if v_1_0.Type != typ.UInt64 { |
| break |
| } |
| _ = v_1_0.Args[1] |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ADD (CSEL0 <typ.UInt64> {cc} (SRL <typ.UInt64> x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))) (SLL x (ANDconst <t> [63] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt64 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0_0.Type != typ.UInt64 { |
| break |
| } |
| _ = v_0_0.Args[1] |
| x := v_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1.Args[1] |
| if x != v_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADD_20(v *Value) bool { |
| b := v.Block |
| typ := &b.Func.Config.Types |
| // match: (ADD (SRL <typ.UInt64> x (ANDconst <t> [63] y)) (CSEL0 <typ.UInt64> {cc} (SLL x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0.Type != typ.UInt64 { |
| break |
| } |
| _ = v_0.Args[1] |
| x := v_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt64 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1_0.Args[1] |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD (CSEL0 <typ.UInt64> {cc} (SLL x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))) (SRL <typ.UInt64> x (ANDconst <t> [63] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt64 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0_0.Args[1] |
| x := v_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRL { |
| break |
| } |
| if v_1.Type != typ.UInt64 { |
| break |
| } |
| _ = v_1.Args[1] |
| if x != v_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD (SLL x (ANDconst <t> [31] y)) (CSEL0 <typ.UInt32> {cc} (SRL <typ.UInt32> (MOVWUreg x) (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0.Args[1] |
| x := v_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt32 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SRL { |
| break |
| } |
| if v_1_0.Type != typ.UInt32 { |
| break |
| } |
| _ = v_1_0.Args[1] |
| v_1_0_0 := v_1_0.Args[0] |
| if v_1_0_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| if x != v_1_0_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ADD (CSEL0 <typ.UInt32> {cc} (SRL <typ.UInt32> (MOVWUreg x) (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))) (SLL x (ANDconst <t> [31] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt32 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0_0.Type != typ.UInt32 { |
| break |
| } |
| _ = v_0_0.Args[1] |
| v_0_0_0 := v_0_0.Args[0] |
| if v_0_0_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_0_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1.Args[1] |
| if x != v_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ADD (SRL <typ.UInt32> (MOVWUreg x) (ANDconst <t> [31] y)) (CSEL0 <typ.UInt32> {cc} (SLL x (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0.Type != typ.UInt32 { |
| break |
| } |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_0_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt32 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1_0.Args[1] |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (ADD (CSEL0 <typ.UInt32> {cc} (SLL x (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))) (SRL <typ.UInt32> (MOVWUreg x) (ANDconst <t> [31] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt32 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0_0.Args[1] |
| x := v_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRL { |
| break |
| } |
| if v_1.Type != typ.UInt32 { |
| break |
| } |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADDconst_0(v *Value) bool { |
| // match: (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) |
| // cond: |
| // result: (MOVDaddr [off1+off2] {sym} ptr) |
| for { |
| off1 := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym := v_0.Aux |
| ptr := v_0.Args[0] |
| v.reset(OpARM64MOVDaddr) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| return true |
| } |
| // match: (ADDconst [0] x) |
| // cond: |
| // result: x |
| for { |
| if v.AuxInt != 0 { |
| break |
| } |
| x := v.Args[0] |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDconst [c] (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [c+d]) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c + d |
| return true |
| } |
| // match: (ADDconst [c] (ADDconst [d] x)) |
| // cond: |
| // result: (ADDconst [c+d] x) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| d := v_0.AuxInt |
| x := v_0.Args[0] |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c + d |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDconst [c] (SUBconst [d] x)) |
| // cond: |
| // result: (ADDconst [c-d] x) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SUBconst { |
| break |
| } |
| d := v_0.AuxInt |
| x := v_0.Args[0] |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c - d |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADDshiftLL_0(v *Value) bool { |
| b := v.Block |
| typ := &b.Func.Config.Types |
| // match: (ADDshiftLL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (ADDconst [c] (SLLconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ADDshiftLL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ADDconst x [int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = int64(uint64(c) << uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftLL [c] (SRLconst x [64-c]) x) |
| // cond: |
| // result: (RORconst [64-c] x) |
| for { |
| c := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| if v_0.AuxInt != 64-c { |
| break |
| } |
| if x != v_0.Args[0] { |
| break |
| } |
| v.reset(OpARM64RORconst) |
| v.AuxInt = 64 - c |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftLL <t> [c] (UBFX [bfc] x) x) |
| // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) |
| // result: (RORWconst [32-c] x) |
| for { |
| t := v.Type |
| c := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64UBFX { |
| break |
| } |
| bfc := v_0.AuxInt |
| if x != v_0.Args[0] { |
| break |
| } |
| if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { |
| break |
| } |
| v.reset(OpARM64RORWconst) |
| v.AuxInt = 32 - c |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftLL <typ.UInt16> [8] (UBFX <typ.UInt16> [armBFAuxInt(8, 8)] x) x) |
| // cond: |
| // result: (REV16W x) |
| for { |
| if v.Type != typ.UInt16 { |
| break |
| } |
| if v.AuxInt != 8 { |
| break |
| } |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64UBFX { |
| break |
| } |
| if v_0.Type != typ.UInt16 { |
| break |
| } |
| if v_0.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| if x != v_0.Args[0] { |
| break |
| } |
| v.reset(OpARM64REV16W) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftLL [c] (SRLconst x [64-c]) x2) |
| // cond: |
| // result: (EXTRconst [64-c] x2 x) |
| for { |
| c := v.AuxInt |
| x2 := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| if v_0.AuxInt != 64-c { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64EXTRconst) |
| v.AuxInt = 64 - c |
| v.AddArg(x2) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftLL <t> [c] (UBFX [bfc] x) x2) |
| // cond: c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) |
| // result: (EXTRWconst [32-c] x2 x) |
| for { |
| t := v.Type |
| c := v.AuxInt |
| x2 := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64UBFX { |
| break |
| } |
| bfc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)) { |
| break |
| } |
| v.reset(OpARM64EXTRWconst) |
| v.AuxInt = 32 - c |
| v.AddArg(x2) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADDshiftRA_0(v *Value) bool { |
| b := v.Block |
| // match: (ADDshiftRA (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (ADDconst [c] (SRAconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ADDshiftRA x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ADDconst x [c>>uint64(d)]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c >> uint64(d) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ADDshiftRL_0(v *Value) bool { |
| b := v.Block |
| // match: (ADDshiftRL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (ADDconst [c] (SRLconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ADDshiftRL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ADDconst x [int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = int64(uint64(c) >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftRL [c] (SLLconst x [64-c]) x) |
| // cond: |
| // result: (RORconst [ c] x) |
| for { |
| c := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 64-c { |
| break |
| } |
| if x != v_0.Args[0] { |
| break |
| } |
| v.reset(OpARM64RORconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (ADDshiftRL <t> [c] (SLLconst x [32-c]) (MOVWUreg x)) |
| // cond: c < 32 && t.Size() == 4 |
| // result: (RORWconst [c] x) |
| for { |
| t := v.Type |
| c := v.AuxInt |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 32-c { |
| break |
| } |
| x := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWUreg { |
| break |
| } |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c < 32 && t.Size() == 4) { |
| break |
| } |
| v.reset(OpARM64RORWconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64AND_0(v *Value) bool { |
| // match: (AND x (MOVDconst [c])) |
| // cond: |
| // result: (ANDconst [c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (AND (MOVDconst [c]) x) |
| // cond: |
| // result: (ANDconst [c] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (AND x x) |
| // cond: |
| // result: x |
| for { |
| x := v.Args[1] |
| if x != v.Args[0] { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (AND x (MVN y)) |
| // cond: |
| // result: (BIC x y) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MVN { |
| break |
| } |
| y := v_1.Args[0] |
| v.reset(OpARM64BIC) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (AND (MVN y) x) |
| // cond: |
| // result: (BIC x y) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MVN { |
| break |
| } |
| y := v_0.Args[0] |
| v.reset(OpARM64BIC) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (AND x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ANDshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ANDshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (AND x1:(SLLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ANDshiftLL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ANDshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (AND x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ANDshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ANDshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (AND x1:(SRLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ANDshiftRL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ANDshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (AND x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ANDshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ANDshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64AND_10(v *Value) bool { |
| // match: (AND x1:(SRAconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ANDshiftRA x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ANDshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ANDconst_0(v *Value) bool { |
| // match: (ANDconst [0] _) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| if v.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (ANDconst [-1] x) |
| // cond: |
| // result: x |
| for { |
| if v.AuxInt != -1 { |
| break |
| } |
| x := v.Args[0] |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDconst [c] (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [c&d]) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c & d |
| return true |
| } |
| // match: (ANDconst [c] (ANDconst [d] x)) |
| // cond: |
| // result: (ANDconst [c&d] x) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| d := v_0.AuxInt |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & d |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDconst [c] (MOVWUreg x)) |
| // cond: |
| // result: (ANDconst [c&(1<<32-1)] x) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & (1<<32 - 1) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDconst [c] (MOVHUreg x)) |
| // cond: |
| // result: (ANDconst [c&(1<<16-1)] x) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVHUreg { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & (1<<16 - 1) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDconst [c] (MOVBUreg x)) |
| // cond: |
| // result: (ANDconst [c&(1<<8-1)] x) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVBUreg { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & (1<<8 - 1) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDconst [ac] (SLLconst [sc] x)) |
| // cond: isARM64BFMask(sc, ac, sc) |
| // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) |
| for { |
| ac := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, ac, sc)) { |
| break |
| } |
| v.reset(OpARM64UBFIZ) |
| v.AuxInt = armBFAuxInt(sc, arm64BFWidth(ac, sc)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDconst [ac] (SRLconst [sc] x)) |
| // cond: isARM64BFMask(sc, ac, 0) |
| // result: (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) |
| for { |
| ac := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, ac, 0)) { |
| break |
| } |
| v.reset(OpARM64UBFX) |
| v.AuxInt = armBFAuxInt(sc, arm64BFWidth(ac, 0)) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ANDshiftLL_0(v *Value) bool { |
| b := v.Block |
| // match: (ANDshiftLL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (ANDconst [c] (SLLconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ANDshiftLL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ANDconst x [int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = int64(uint64(c) << uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDshiftLL x y:(SLLconst x [c]) [d]) |
| // cond: c==d |
| // result: y |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| y := v.Args[1] |
| if y.Op != OpARM64SLLconst { |
| break |
| } |
| c := y.AuxInt |
| if x != y.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = y.Type |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ANDshiftRA_0(v *Value) bool { |
| b := v.Block |
| // match: (ANDshiftRA (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (ANDconst [c] (SRAconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ANDshiftRA x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ANDconst x [c>>uint64(d)]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c >> uint64(d) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDshiftRA x y:(SRAconst x [c]) [d]) |
| // cond: c==d |
| // result: y |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| y := v.Args[1] |
| if y.Op != OpARM64SRAconst { |
| break |
| } |
| c := y.AuxInt |
| if x != y.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = y.Type |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64ANDshiftRL_0(v *Value) bool { |
| b := v.Block |
| // match: (ANDshiftRL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (ANDconst [c] (SRLconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (ANDshiftRL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ANDconst x [int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = int64(uint64(c) >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (ANDshiftRL x y:(SRLconst x [c]) [d]) |
| // cond: c==d |
| // result: y |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| y := v.Args[1] |
| if y.Op != OpARM64SRLconst { |
| break |
| } |
| c := y.AuxInt |
| if x != y.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = y.Type |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64BIC_0(v *Value) bool { |
| // match: (BIC x (MOVDconst [c])) |
| // cond: |
| // result: (ANDconst [^c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = ^c |
| v.AddArg(x) |
| return true |
| } |
| // match: (BIC x x) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| x := v.Args[1] |
| if x != v.Args[0] { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (BIC x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (BICshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64BICshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (BIC x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (BICshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64BICshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (BIC x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (BICshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64BICshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64BICshiftLL_0(v *Value) bool { |
| // match: (BICshiftLL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ANDconst x [^int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = ^int64(uint64(c) << uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (BICshiftLL x (SLLconst x [c]) [d]) |
| // cond: c==d |
| // result: (MOVDconst [0]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| c := v_1.AuxInt |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64BICshiftRA_0(v *Value) bool { |
| // match: (BICshiftRA x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ANDconst x [^(c>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = ^(c >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (BICshiftRA x (SRAconst x [c]) [d]) |
| // cond: c==d |
| // result: (MOVDconst [0]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRAconst { |
| break |
| } |
| c := v_1.AuxInt |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64BICshiftRL_0(v *Value) bool { |
| // match: (BICshiftRL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (ANDconst x [^int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = ^int64(uint64(c) >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (BICshiftRL x (SRLconst x [c]) [d]) |
| // cond: c==d |
| // result: (MOVDconst [0]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| c := v_1.AuxInt |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMN_0(v *Value) bool { |
| // match: (CMN x (MOVDconst [c])) |
| // cond: |
| // result: (CMNconst [c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (CMN (MOVDconst [c]) x) |
| // cond: |
| // result: (CMNconst [c] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (CMN x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (CMNshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMNshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMN x1:(SLLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (CMNshiftLL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMNshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMN x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (CMNshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMNshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMN x1:(SRLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (CMNshiftRL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMNshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMN x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (CMNshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMNshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMN x1:(SRAconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (CMNshiftRA x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMNshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMNW_0(v *Value) bool { |
| // match: (CMNW x (MOVDconst [c])) |
| // cond: |
| // result: (CMNWconst [c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMNWconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (CMNW (MOVDconst [c]) x) |
| // cond: |
| // result: (CMNWconst [c] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64CMNWconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMNWconst_0(v *Value) bool { |
| // match: (CMNWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)==int32(-y) |
| // result: (FlagEQ) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) == int32(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagEQ) |
| return true |
| } |
| // match: (CMNWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)<int32(-y) && uint32(x)<uint32(-y) |
| // result: (FlagLT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) < int32(-y) && uint32(x) < uint32(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMNWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)<int32(-y) && uint32(x)>uint32(-y) |
| // result: (FlagLT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) < int32(-y) && uint32(x) > uint32(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_UGT) |
| return true |
| } |
| // match: (CMNWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)>int32(-y) && uint32(x)<uint32(-y) |
| // result: (FlagGT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) > int32(-y) && uint32(x) < uint32(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_ULT) |
| return true |
| } |
| // match: (CMNWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)>int32(-y) && uint32(x)>uint32(-y) |
| // result: (FlagGT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) > int32(-y) && uint32(x) > uint32(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_UGT) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMNconst_0(v *Value) bool { |
| // match: (CMNconst (MOVDconst [x]) [y]) |
| // cond: int64(x)==int64(-y) |
| // result: (FlagEQ) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int64(x) == int64(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagEQ) |
| return true |
| } |
| // match: (CMNconst (MOVDconst [x]) [y]) |
| // cond: int64(x)<int64(-y) && uint64(x)<uint64(-y) |
| // result: (FlagLT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int64(x) < int64(-y) && uint64(x) < uint64(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMNconst (MOVDconst [x]) [y]) |
| // cond: int64(x)<int64(-y) && uint64(x)>uint64(-y) |
| // result: (FlagLT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int64(x) < int64(-y) && uint64(x) > uint64(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_UGT) |
| return true |
| } |
| // match: (CMNconst (MOVDconst [x]) [y]) |
| // cond: int64(x)>int64(-y) && uint64(x)<uint64(-y) |
| // result: (FlagGT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int64(x) > int64(-y) && uint64(x) < uint64(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_ULT) |
| return true |
| } |
| // match: (CMNconst (MOVDconst [x]) [y]) |
| // cond: int64(x)>int64(-y) && uint64(x)>uint64(-y) |
| // result: (FlagGT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int64(x) > int64(-y) && uint64(x) > uint64(-y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_UGT) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMNshiftLL_0(v *Value) bool { |
| b := v.Block |
| // match: (CMNshiftLL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (CMNconst [c] (SLLconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMNshiftLL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (CMNconst x [int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = int64(uint64(c) << uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMNshiftRA_0(v *Value) bool { |
| b := v.Block |
| // match: (CMNshiftRA (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (CMNconst [c] (SRAconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMNshiftRA x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (CMNconst x [c>>uint64(d)]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = c >> uint64(d) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMNshiftRL_0(v *Value) bool { |
| b := v.Block |
| // match: (CMNshiftRL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (CMNconst [c] (SRLconst <x.Type> x [d])) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) |
| v0.AuxInt = d |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMNshiftRL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (CMNconst x [int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMNconst) |
| v.AuxInt = int64(uint64(c) >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMP_0(v *Value) bool { |
| b := v.Block |
| // match: (CMP x (MOVDconst [c])) |
| // cond: |
| // result: (CMPconst [c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMPconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (CMP (MOVDconst [c]) x) |
| // cond: |
| // result: (InvertFlags (CMPconst [c] x)) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) |
| v0.AuxInt = c |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMP x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (CMPshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMPshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMP x0:(SLLconst [c] y) x1) |
| // cond: clobberIfDead(x0) |
| // result: (InvertFlags (CMPshiftLL x1 y [c])) |
| for { |
| x1 := v.Args[1] |
| x0 := v.Args[0] |
| if x0.Op != OpARM64SLLconst { |
| break |
| } |
| c := x0.AuxInt |
| y := x0.Args[0] |
| if !(clobberIfDead(x0)) { |
| break |
| } |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPshiftLL, types.TypeFlags) |
| v0.AuxInt = c |
| v0.AddArg(x1) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMP x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (CMPshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMPshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMP x0:(SRLconst [c] y) x1) |
| // cond: clobberIfDead(x0) |
| // result: (InvertFlags (CMPshiftRL x1 y [c])) |
| for { |
| x1 := v.Args[1] |
| x0 := v.Args[0] |
| if x0.Op != OpARM64SRLconst { |
| break |
| } |
| c := x0.AuxInt |
| y := x0.Args[0] |
| if !(clobberIfDead(x0)) { |
| break |
| } |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRL, types.TypeFlags) |
| v0.AuxInt = c |
| v0.AddArg(x1) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMP x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (CMPshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64CMPshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (CMP x0:(SRAconst [c] y) x1) |
| // cond: clobberIfDead(x0) |
| // result: (InvertFlags (CMPshiftRA x1 y [c])) |
| for { |
| x1 := v.Args[1] |
| x0 := v.Args[0] |
| if x0.Op != OpARM64SRAconst { |
| break |
| } |
| c := x0.AuxInt |
| y := x0.Args[0] |
| if !(clobberIfDead(x0)) { |
| break |
| } |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPshiftRA, types.TypeFlags) |
| v0.AuxInt = c |
| v0.AddArg(x1) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMPW_0(v *Value) bool { |
| b := v.Block |
| // match: (CMPW x (MOVDconst [c])) |
| // cond: |
| // result: (CMPWconst [int64(int32(c))] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMPWconst) |
| v.AuxInt = int64(int32(c)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (CMPW (MOVDconst [c]) x) |
| // cond: |
| // result: (InvertFlags (CMPWconst [int64(int32(c))] x)) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPWconst, types.TypeFlags) |
| v0.AuxInt = int64(int32(c)) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMPWconst_0(v *Value) bool { |
| // match: (CMPWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)==int32(y) |
| // result: (FlagEQ) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) == int32(y)) { |
| break |
| } |
| v.reset(OpARM64FlagEQ) |
| return true |
| } |
| // match: (CMPWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)<int32(y) && uint32(x)<uint32(y) |
| // result: (FlagLT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) < int32(y) && uint32(x) < uint32(y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)<int32(y) && uint32(x)>uint32(y) |
| // result: (FlagLT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) < int32(y) && uint32(x) > uint32(y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_UGT) |
| return true |
| } |
| // match: (CMPWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)>int32(y) && uint32(x)<uint32(y) |
| // result: (FlagGT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) > int32(y) && uint32(x) < uint32(y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_ULT) |
| return true |
| } |
| // match: (CMPWconst (MOVDconst [x]) [y]) |
| // cond: int32(x)>int32(y) && uint32(x)>uint32(y) |
| // result: (FlagGT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(int32(x) > int32(y) && uint32(x) > uint32(y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_UGT) |
| return true |
| } |
| // match: (CMPWconst (MOVBUreg _) [c]) |
| // cond: 0xff < int32(c) |
| // result: (FlagLT_ULT) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVBUreg { |
| break |
| } |
| if !(0xff < int32(c)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPWconst (MOVHUreg _) [c]) |
| // cond: 0xffff < int32(c) |
| // result: (FlagLT_ULT) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVHUreg { |
| break |
| } |
| if !(0xffff < int32(c)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMPconst_0(v *Value) bool { |
| // match: (CMPconst (MOVDconst [x]) [y]) |
| // cond: x==y |
| // result: (FlagEQ) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(x == y) { |
| break |
| } |
| v.reset(OpARM64FlagEQ) |
| return true |
| } |
| // match: (CMPconst (MOVDconst [x]) [y]) |
| // cond: x<y && uint64(x)<uint64(y) |
| // result: (FlagLT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(x < y && uint64(x) < uint64(y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPconst (MOVDconst [x]) [y]) |
| // cond: x<y && uint64(x)>uint64(y) |
| // result: (FlagLT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(x < y && uint64(x) > uint64(y)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_UGT) |
| return true |
| } |
| // match: (CMPconst (MOVDconst [x]) [y]) |
| // cond: x>y && uint64(x)<uint64(y) |
| // result: (FlagGT_ULT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(x > y && uint64(x) < uint64(y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_ULT) |
| return true |
| } |
| // match: (CMPconst (MOVDconst [x]) [y]) |
| // cond: x>y && uint64(x)>uint64(y) |
| // result: (FlagGT_UGT) |
| for { |
| y := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| x := v_0.AuxInt |
| if !(x > y && uint64(x) > uint64(y)) { |
| break |
| } |
| v.reset(OpARM64FlagGT_UGT) |
| return true |
| } |
| // match: (CMPconst (MOVBUreg _) [c]) |
| // cond: 0xff < c |
| // result: (FlagLT_ULT) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVBUreg { |
| break |
| } |
| if !(0xff < c) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPconst (MOVHUreg _) [c]) |
| // cond: 0xffff < c |
| // result: (FlagLT_ULT) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVHUreg { |
| break |
| } |
| if !(0xffff < c) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPconst (MOVWUreg _) [c]) |
| // cond: 0xffffffff < c |
| // result: (FlagLT_ULT) |
| for { |
| c := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| if !(0xffffffff < c) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPconst (ANDconst _ [m]) [n]) |
| // cond: 0 <= m && m < n |
| // result: (FlagLT_ULT) |
| for { |
| n := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| m := v_0.AuxInt |
| if !(0 <= m && m < n) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| // match: (CMPconst (SRLconst _ [c]) [n]) |
| // cond: 0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n) |
| // result: (FlagLT_ULT) |
| for { |
| n := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n)) { |
| break |
| } |
| v.reset(OpARM64FlagLT_ULT) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMPshiftLL_0(v *Value) bool { |
| b := v.Block |
| // match: (CMPshiftLL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (InvertFlags (CMPconst [c] (SLLconst <x.Type> x [d]))) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) |
| v0.AuxInt = c |
| v1 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v1.AuxInt = d |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMPshiftLL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (CMPconst x [int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMPconst) |
| v.AuxInt = int64(uint64(c) << uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMPshiftRA_0(v *Value) bool { |
| b := v.Block |
| // match: (CMPshiftRA (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (InvertFlags (CMPconst [c] (SRAconst <x.Type> x [d]))) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) |
| v0.AuxInt = c |
| v1 := b.NewValue0(v.Pos, OpARM64SRAconst, x.Type) |
| v1.AuxInt = d |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMPshiftRA x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (CMPconst x [c>>uint64(d)]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMPconst) |
| v.AuxInt = c >> uint64(d) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CMPshiftRL_0(v *Value) bool { |
| b := v.Block |
| // match: (CMPshiftRL (MOVDconst [c]) x [d]) |
| // cond: |
| // result: (InvertFlags (CMPconst [c] (SRLconst <x.Type> x [d]))) |
| for { |
| d := v.AuxInt |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64CMPconst, types.TypeFlags) |
| v0.AuxInt = c |
| v1 := b.NewValue0(v.Pos, OpARM64SRLconst, x.Type) |
| v1.AuxInt = d |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (CMPshiftRL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (CMPconst x [int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64CMPconst) |
| v.AuxInt = int64(uint64(c) >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CSEL_0(v *Value) bool { |
| // match: (CSEL {cc} x (MOVDconst [0]) flag) |
| // cond: |
| // result: (CSEL0 {cc} x flag) |
| for { |
| cc := v.Aux |
| flag := v.Args[2] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64CSEL0) |
| v.Aux = cc |
| v.AddArg(x) |
| v.AddArg(flag) |
| return true |
| } |
| // match: (CSEL {cc} (MOVDconst [0]) y flag) |
| // cond: |
| // result: (CSEL0 {arm64Negate(cc.(Op))} y flag) |
| for { |
| cc := v.Aux |
| flag := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != 0 { |
| break |
| } |
| y := v.Args[1] |
| v.reset(OpARM64CSEL0) |
| v.Aux = arm64Negate(cc.(Op)) |
| v.AddArg(y) |
| v.AddArg(flag) |
| return true |
| } |
| // match: (CSEL {cc} x y (InvertFlags cmp)) |
| // cond: |
| // result: (CSEL {arm64Invert(cc.(Op))} x y cmp) |
| for { |
| cc := v.Aux |
| _ = v.Args[2] |
| x := v.Args[0] |
| y := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64InvertFlags { |
| break |
| } |
| cmp := v_2.Args[0] |
| v.reset(OpARM64CSEL) |
| v.Aux = arm64Invert(cc.(Op)) |
| v.AddArg(x) |
| v.AddArg(y) |
| v.AddArg(cmp) |
| return true |
| } |
| // match: (CSEL {cc} x _ flag) |
| // cond: ccARM64Eval(cc, flag) > 0 |
| // result: x |
| for { |
| cc := v.Aux |
| flag := v.Args[2] |
| x := v.Args[0] |
| if !(ccARM64Eval(cc, flag) > 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (CSEL {cc} _ y flag) |
| // cond: ccARM64Eval(cc, flag) < 0 |
| // result: y |
| for { |
| cc := v.Aux |
| flag := v.Args[2] |
| y := v.Args[1] |
| if !(ccARM64Eval(cc, flag) < 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = y.Type |
| v.AddArg(y) |
| return true |
| } |
| // match: (CSEL {cc} x y (CMPWconst [0] boolval)) |
| // cond: cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil |
| // result: (CSEL {boolval.Op} x y flagArg(boolval)) |
| for { |
| cc := v.Aux |
| _ = v.Args[2] |
| x := v.Args[0] |
| y := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64CMPWconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| boolval := v_2.Args[0] |
| if !(cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil) { |
| break |
| } |
| v.reset(OpARM64CSEL) |
| v.Aux = boolval.Op |
| v.AddArg(x) |
| v.AddArg(y) |
| v.AddArg(flagArg(boolval)) |
| return true |
| } |
| // match: (CSEL {cc} x y (CMPWconst [0] boolval)) |
| // cond: cc.(Op) == OpARM64Equal && flagArg(boolval) != nil |
| // result: (CSEL {arm64Negate(boolval.Op)} x y flagArg(boolval)) |
| for { |
| cc := v.Aux |
| _ = v.Args[2] |
| x := v.Args[0] |
| y := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64CMPWconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| boolval := v_2.Args[0] |
| if !(cc.(Op) == OpARM64Equal && flagArg(boolval) != nil) { |
| break |
| } |
| v.reset(OpARM64CSEL) |
| v.Aux = arm64Negate(boolval.Op) |
| v.AddArg(x) |
| v.AddArg(y) |
| v.AddArg(flagArg(boolval)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64CSEL0_0(v *Value) bool { |
| // match: (CSEL0 {cc} x (InvertFlags cmp)) |
| // cond: |
| // result: (CSEL0 {arm64Invert(cc.(Op))} x cmp) |
| for { |
| cc := v.Aux |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64InvertFlags { |
| break |
| } |
| cmp := v_1.Args[0] |
| v.reset(OpARM64CSEL0) |
| v.Aux = arm64Invert(cc.(Op)) |
| v.AddArg(x) |
| v.AddArg(cmp) |
| return true |
| } |
| // match: (CSEL0 {cc} x flag) |
| // cond: ccARM64Eval(cc, flag) > 0 |
| // result: x |
| for { |
| cc := v.Aux |
| flag := v.Args[1] |
| x := v.Args[0] |
| if !(ccARM64Eval(cc, flag) > 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (CSEL0 {cc} _ flag) |
| // cond: ccARM64Eval(cc, flag) < 0 |
| // result: (MOVDconst [0]) |
| for { |
| cc := v.Aux |
| flag := v.Args[1] |
| if !(ccARM64Eval(cc, flag) < 0) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (CSEL0 {cc} x (CMPWconst [0] boolval)) |
| // cond: cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil |
| // result: (CSEL0 {boolval.Op} x flagArg(boolval)) |
| for { |
| cc := v.Aux |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CMPWconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| boolval := v_1.Args[0] |
| if !(cc.(Op) == OpARM64NotEqual && flagArg(boolval) != nil) { |
| break |
| } |
| v.reset(OpARM64CSEL0) |
| v.Aux = boolval.Op |
| v.AddArg(x) |
| v.AddArg(flagArg(boolval)) |
| return true |
| } |
| // match: (CSEL0 {cc} x (CMPWconst [0] boolval)) |
| // cond: cc.(Op) == OpARM64Equal && flagArg(boolval) != nil |
| // result: (CSEL0 {arm64Negate(boolval.Op)} x flagArg(boolval)) |
| for { |
| cc := v.Aux |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CMPWconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| boolval := v_1.Args[0] |
| if !(cc.(Op) == OpARM64Equal && flagArg(boolval) != nil) { |
| break |
| } |
| v.reset(OpARM64CSEL0) |
| v.Aux = arm64Negate(boolval.Op) |
| v.AddArg(x) |
| v.AddArg(flagArg(boolval)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64DIV_0(v *Value) bool { |
| // match: (DIV (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [c/d]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c / d |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64DIVW_0(v *Value) bool { |
| // match: (DIVW (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [int64(int32(c)/int32(d))]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int32(c) / int32(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64EON_0(v *Value) bool { |
| // match: (EON x (MOVDconst [c])) |
| // cond: |
| // result: (XORconst [^c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64XORconst) |
| v.AuxInt = ^c |
| v.AddArg(x) |
| return true |
| } |
| // match: (EON x x) |
| // cond: |
| // result: (MOVDconst [-1]) |
| for { |
| x := v.Args[1] |
| if x != v.Args[0] { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -1 |
| return true |
| } |
| // match: (EON x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (EONshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64EONshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (EON x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (EONshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64EONshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (EON x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (EONshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64EONshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64EONshiftLL_0(v *Value) bool { |
| // match: (EONshiftLL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (XORconst x [^int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64XORconst) |
| v.AuxInt = ^int64(uint64(c) << uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (EONshiftLL x (SLLconst x [c]) [d]) |
| // cond: c==d |
| // result: (MOVDconst [-1]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| c := v_1.AuxInt |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -1 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64EONshiftRA_0(v *Value) bool { |
| // match: (EONshiftRA x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (XORconst x [^(c>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64XORconst) |
| v.AuxInt = ^(c >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (EONshiftRA x (SRAconst x [c]) [d]) |
| // cond: c==d |
| // result: (MOVDconst [-1]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRAconst { |
| break |
| } |
| c := v_1.AuxInt |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -1 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64EONshiftRL_0(v *Value) bool { |
| // match: (EONshiftRL x (MOVDconst [c]) [d]) |
| // cond: |
| // result: (XORconst x [^int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64XORconst) |
| v.AuxInt = ^int64(uint64(c) >> uint64(d)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (EONshiftRL x (SRLconst x [c]) [d]) |
| // cond: c==d |
| // result: (MOVDconst [-1]) |
| for { |
| d := v.AuxInt |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| c := v_1.AuxInt |
| if x != v_1.Args[0] { |
| break |
| } |
| if !(c == d) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -1 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64Equal_0(v *Value) bool { |
| // match: (Equal (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (Equal (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (Equal (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (Equal (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (Equal (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (Equal (InvertFlags x)) |
| // cond: |
| // result: (Equal x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64Equal) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FADDD_0(v *Value) bool { |
| // match: (FADDD a (FMULD x y)) |
| // cond: |
| // result: (FMADDD a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMULD { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMADDD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FADDD (FMULD x y) a) |
| // cond: |
| // result: (FMADDD a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMULD { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FMADDD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FADDD a (FNMULD x y)) |
| // cond: |
| // result: (FMSUBD a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNMULD { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMSUBD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FADDD (FNMULD x y) a) |
| // cond: |
| // result: (FMSUBD a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNMULD { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FMSUBD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FADDS_0(v *Value) bool { |
| // match: (FADDS a (FMULS x y)) |
| // cond: |
| // result: (FMADDS a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMULS { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMADDS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FADDS (FMULS x y) a) |
| // cond: |
| // result: (FMADDS a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMULS { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FMADDS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FADDS a (FNMULS x y)) |
| // cond: |
| // result: (FMSUBS a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNMULS { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMSUBS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FADDS (FNMULS x y) a) |
| // cond: |
| // result: (FMSUBS a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNMULS { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FMSUBS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FCMPD_0(v *Value) bool { |
| b := v.Block |
| // match: (FCMPD x (FMOVDconst [0])) |
| // cond: |
| // result: (FCMPD0 x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64FCMPD0) |
| v.AddArg(x) |
| return true |
| } |
| // match: (FCMPD (FMOVDconst [0]) x) |
| // cond: |
| // result: (InvertFlags (FCMPD0 x)) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMOVDconst { |
| break |
| } |
| if v_0.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64FCMPD0, types.TypeFlags) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FCMPS_0(v *Value) bool { |
| b := v.Block |
| // match: (FCMPS x (FMOVSconst [0])) |
| // cond: |
| // result: (FCMPS0 x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVSconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64FCMPS0) |
| v.AddArg(x) |
| return true |
| } |
| // match: (FCMPS (FMOVSconst [0]) x) |
| // cond: |
| // result: (InvertFlags (FCMPS0 x)) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMOVSconst { |
| break |
| } |
| if v_0.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64InvertFlags) |
| v0 := b.NewValue0(v.Pos, OpARM64FCMPS0, types.TypeFlags) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVDfpgp_0(v *Value) bool { |
| b := v.Block |
| // match: (FMOVDfpgp <t> (Arg [off] {sym})) |
| // cond: |
| // result: @b.Func.Entry (Arg <t> [off] {sym}) |
| for { |
| t := v.Type |
| v_0 := v.Args[0] |
| if v_0.Op != OpArg { |
| break |
| } |
| off := v_0.AuxInt |
| sym := v_0.Aux |
| b = b.Func.Entry |
| v0 := b.NewValue0(v.Pos, OpArg, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.AuxInt = off |
| v0.Aux = sym |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVDgpfp_0(v *Value) bool { |
| b := v.Block |
| // match: (FMOVDgpfp <t> (Arg [off] {sym})) |
| // cond: |
| // result: @b.Func.Entry (Arg <t> [off] {sym}) |
| for { |
| t := v.Type |
| v_0 := v.Args[0] |
| if v_0.Op != OpArg { |
| break |
| } |
| off := v_0.AuxInt |
| sym := v_0.Aux |
| b = b.Func.Entry |
| v0 := b.NewValue0(v.Pos, OpArg, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.AuxInt = off |
| v0.Aux = sym |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVDload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) |
| // cond: |
| // result: (FMOVDgpfp val) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDstore { |
| break |
| } |
| if v_1.AuxInt != off { |
| break |
| } |
| if v_1.Aux != sym { |
| break |
| } |
| _ = v_1.Args[2] |
| if ptr != v_1.Args[0] { |
| break |
| } |
| val := v_1.Args[1] |
| v.reset(OpARM64FMOVDgpfp) |
| v.AddArg(val) |
| return true |
| } |
| // match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVDload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVDload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (FMOVDloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64FMOVDloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVDload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVDloadidx_0(v *Value) bool { |
| // match: (FMOVDloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (FMOVDload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64FMOVDload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (FMOVDload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64FMOVDload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVDstore_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) |
| // cond: |
| // result: (MOVDstore [off] {sym} ptr val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVDgpfp { |
| break |
| } |
| val := v_1.Args[0] |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVDstore [off1+off2] {sym} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVDstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDstore [off] {sym} (ADD ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (FMOVDstoreidx ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64FMOVDstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVDstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVDstoreidx_0(v *Value) bool { |
| // match: (FMOVDstoreidx ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (FMOVDstore [c] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64FMOVDstore) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVDstoreidx (MOVDconst [c]) idx val mem) |
| // cond: |
| // result: (FMOVDstore [c] idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64FMOVDstore) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVSload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) |
| // cond: |
| // result: (FMOVSgpfp val) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWstore { |
| break |
| } |
| if v_1.AuxInt != off { |
| break |
| } |
| if v_1.Aux != sym { |
| break |
| } |
| _ = v_1.Args[2] |
| if ptr != v_1.Args[0] { |
| break |
| } |
| val := v_1.Args[1] |
| v.reset(OpARM64FMOVSgpfp) |
| v.AddArg(val) |
| return true |
| } |
| // match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVSload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVSload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (FMOVSloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64FMOVSloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVSload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVSloadidx_0(v *Value) bool { |
| // match: (FMOVSloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (FMOVSload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64FMOVSload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (FMOVSload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64FMOVSload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVSstore_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) |
| // cond: |
| // result: (MOVWstore [off] {sym} ptr val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVSgpfp { |
| break |
| } |
| val := v_1.Args[0] |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVSstore [off1+off2] {sym} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVSstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSstore [off] {sym} (ADD ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (FMOVSstoreidx ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64FMOVSstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64FMOVSstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMOVSstoreidx_0(v *Value) bool { |
| // match: (FMOVSstoreidx ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (FMOVSstore [c] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64FMOVSstore) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (FMOVSstoreidx (MOVDconst [c]) idx val mem) |
| // cond: |
| // result: (FMOVSstore [c] idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64FMOVSstore) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMULD_0(v *Value) bool { |
| // match: (FMULD (FNEGD x) y) |
| // cond: |
| // result: (FNMULD x y) |
| for { |
| y := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNEGD { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMULD) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FMULD y (FNEGD x)) |
| // cond: |
| // result: (FNMULD x y) |
| for { |
| _ = v.Args[1] |
| y := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNEGD { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64FNMULD) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FMULS_0(v *Value) bool { |
| // match: (FMULS (FNEGS x) y) |
| // cond: |
| // result: (FNMULS x y) |
| for { |
| y := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNEGS { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMULS) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FMULS y (FNEGS x)) |
| // cond: |
| // result: (FNMULS x y) |
| for { |
| _ = v.Args[1] |
| y := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNEGS { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64FNMULS) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FNEGD_0(v *Value) bool { |
| // match: (FNEGD (FMULD x y)) |
| // cond: |
| // result: (FNMULD x y) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMULD { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMULD) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FNEGD (FNMULD x y)) |
| // cond: |
| // result: (FMULD x y) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNMULD { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FMULD) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FNEGS_0(v *Value) bool { |
| // match: (FNEGS (FMULS x y)) |
| // cond: |
| // result: (FNMULS x y) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMULS { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMULS) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FNEGS (FNMULS x y)) |
| // cond: |
| // result: (FMULS x y) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNMULS { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FMULS) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FNMULD_0(v *Value) bool { |
| // match: (FNMULD (FNEGD x) y) |
| // cond: |
| // result: (FMULD x y) |
| for { |
| y := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNEGD { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64FMULD) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FNMULD y (FNEGD x)) |
| // cond: |
| // result: (FMULD x y) |
| for { |
| _ = v.Args[1] |
| y := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNEGD { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64FMULD) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FNMULS_0(v *Value) bool { |
| // match: (FNMULS (FNEGS x) y) |
| // cond: |
| // result: (FMULS x y) |
| for { |
| y := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNEGS { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64FMULS) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FNMULS y (FNEGS x)) |
| // cond: |
| // result: (FMULS x y) |
| for { |
| _ = v.Args[1] |
| y := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNEGS { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64FMULS) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FSUBD_0(v *Value) bool { |
| // match: (FSUBD a (FMULD x y)) |
| // cond: |
| // result: (FMSUBD a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMULD { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMSUBD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FSUBD (FMULD x y) a) |
| // cond: |
| // result: (FNMSUBD a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMULD { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMSUBD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FSUBD a (FNMULD x y)) |
| // cond: |
| // result: (FMADDD a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNMULD { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMADDD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FSUBD (FNMULD x y) a) |
| // cond: |
| // result: (FNMADDD a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNMULD { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMADDD) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64FSUBS_0(v *Value) bool { |
| // match: (FSUBS a (FMULS x y)) |
| // cond: |
| // result: (FMSUBS a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMULS { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMSUBS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FSUBS (FMULS x y) a) |
| // cond: |
| // result: (FNMSUBS a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FMULS { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMSUBS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FSUBS a (FNMULS x y)) |
| // cond: |
| // result: (FMADDS a x y) |
| for { |
| _ = v.Args[1] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FNMULS { |
| break |
| } |
| y := v_1.Args[1] |
| x := v_1.Args[0] |
| v.reset(OpARM64FMADDS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (FSUBS (FNMULS x y) a) |
| // cond: |
| // result: (FNMADDS a x y) |
| for { |
| a := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FNMULS { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64FNMADDS) |
| v.AddArg(a) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64GreaterEqual_0(v *Value) bool { |
| // match: (GreaterEqual (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterEqual (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterEqual (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterEqual (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterEqual (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterEqual (InvertFlags x)) |
| // cond: |
| // result: (LessEqual x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64LessEqual) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64GreaterEqualF_0(v *Value) bool { |
| // match: (GreaterEqualF (InvertFlags x)) |
| // cond: |
| // result: (LessEqualF x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64LessEqualF) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64GreaterEqualU_0(v *Value) bool { |
| // match: (GreaterEqualU (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterEqualU (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterEqualU (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterEqualU (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterEqualU (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterEqualU (InvertFlags x)) |
| // cond: |
| // result: (LessEqualU x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64LessEqualU) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64GreaterThan_0(v *Value) bool { |
| // match: (GreaterThan (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterThan (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterThan (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterThan (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterThan (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterThan (InvertFlags x)) |
| // cond: |
| // result: (LessThan x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64LessThan) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64GreaterThanF_0(v *Value) bool { |
| // match: (GreaterThanF (InvertFlags x)) |
| // cond: |
| // result: (LessThanF x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64LessThanF) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64GreaterThanU_0(v *Value) bool { |
| // match: (GreaterThanU (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterThanU (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterThanU (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterThanU (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (GreaterThanU (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (GreaterThanU (InvertFlags x)) |
| // cond: |
| // result: (LessThanU x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64LessThanU) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64LessEqual_0(v *Value) bool { |
| // match: (LessEqual (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessEqual (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessEqual (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessEqual (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessEqual (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessEqual (InvertFlags x)) |
| // cond: |
| // result: (GreaterEqual x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64GreaterEqual) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64LessEqualF_0(v *Value) bool { |
| // match: (LessEqualF (InvertFlags x)) |
| // cond: |
| // result: (GreaterEqualF x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64GreaterEqualF) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64LessEqualU_0(v *Value) bool { |
| // match: (LessEqualU (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessEqualU (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessEqualU (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessEqualU (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessEqualU (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessEqualU (InvertFlags x)) |
| // cond: |
| // result: (GreaterEqualU x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64GreaterEqualU) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64LessThan_0(v *Value) bool { |
| // match: (LessThan (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessThan (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessThan (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessThan (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessThan (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessThan (InvertFlags x)) |
| // cond: |
| // result: (GreaterThan x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64GreaterThan) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64LessThanF_0(v *Value) bool { |
| // match: (LessThanF (InvertFlags x)) |
| // cond: |
| // result: (GreaterThanF x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64GreaterThanF) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64LessThanU_0(v *Value) bool { |
| // match: (LessThanU (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessThanU (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessThanU (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessThanU (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (LessThanU (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (LessThanU (InvertFlags x)) |
| // cond: |
| // result: (GreaterThanU x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64GreaterThanU) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MADD_0(v *Value) bool { |
| b := v.Block |
| // match: (MADD a x (MOVDconst [-1])) |
| // cond: |
| // result: (SUB a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != -1 { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADD a _ (MOVDconst [0])) |
| // cond: |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [1])) |
| // cond: |
| // result: (ADD a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 1 { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (ADDshiftLL a x [log2(c)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && c>=3 |
| // result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && c>=7 |
| // result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MADD_10(v *Value) bool { |
| b := v.Block |
| // match: (MADD a (MOVDconst [-1]) x) |
| // cond: |
| // result: (SUB a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != -1 { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADD a (MOVDconst [0]) _) |
| // cond: |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MADD a (MOVDconst [1]) x) |
| // cond: |
| // result: (ADD a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (ADDshiftLL a x [log2(c)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && c>=3 |
| // result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && c>=7 |
| // result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MADD_20(v *Value) bool { |
| b := v.Block |
| // match: (MADD (MOVDconst [c]) x y) |
| // cond: |
| // result: (ADDconst [c] (MUL <x.Type> x y)) |
| for { |
| y := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v.Args[1] |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64MUL, x.Type) |
| v0.AddArg(x) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADD a (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (ADDconst [c*d] a) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_2.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c * d |
| v.AddArg(a) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MADDW_0(v *Value) bool { |
| b := v.Block |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: int32(c)==-1 |
| // result: (SUB a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADDW a _ (MOVDconst [c])) |
| // cond: int32(c)==0 |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: int32(c)==1 |
| // result: (ADD a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (ADDshiftLL a x [log2(c)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && int32(c)>=3 |
| // result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && int32(c)>=7 |
| // result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MADDW_10(v *Value) bool { |
| b := v.Block |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: int32(c)==-1 |
| // result: (SUB a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) _) |
| // cond: int32(c)==0 |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: int32(c)==1 |
| // result: (ADD a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (ADDshiftLL a x [log2(c)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && int32(c)>=3 |
| // result: (ADD a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && int32(c)>=7 |
| // result: (SUB a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MADDW_20(v *Value) bool { |
| b := v.Block |
| // match: (MADDW (MOVDconst [c]) x y) |
| // cond: |
| // result: (ADDconst [c] (MULW <x.Type> x y)) |
| for { |
| y := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v.Args[1] |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64MULW, x.Type) |
| v0.AddArg(x) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MADDW a (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (ADDconst [int64(int32(c)*int32(d))] a) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_2.AuxInt |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = int64(int32(c) * int32(d)) |
| v.AddArg(a) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MNEG_0(v *Value) bool { |
| b := v.Block |
| // match: (MNEG x (MOVDconst [-1])) |
| // cond: |
| // result: x |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != -1 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEG (MOVDconst [-1]) x) |
| // cond: |
| // result: x |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != -1 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEG _ (MOVDconst [0])) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MNEG (MOVDconst [0]) _) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MNEG x (MOVDconst [1])) |
| // cond: |
| // result: (NEG x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEG (MOVDconst [1]) x) |
| // cond: |
| // result: (NEG x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c)] x)) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c)] x)) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && c >= 3 |
| // result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && c >= 3 |
| // result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MNEG_10(v *Value) bool { |
| b := v.Block |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && c >= 7 |
| // result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && c >= 7 |
| // result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 5) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 2 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 5) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 2 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 9) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 3 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEG (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 9) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 3 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MNEG_20(v *Value) bool { |
| // match: (MNEG (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [-c*d]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -c * d |
| return true |
| } |
| // match: (MNEG (MOVDconst [d]) (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [-c*d]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -c * d |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MNEGW_0(v *Value) bool { |
| b := v.Block |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: int32(c)==-1 |
| // result: x |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: int32(c)==-1 |
| // result: x |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEGW _ (MOVDconst [c])) |
| // cond: int32(c)==0 |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) _) |
| // cond: int32(c)==0 |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: int32(c)==1 |
| // result: (NEG x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: int32(c)==1 |
| // result: (NEG x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c)] x)) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c)] x)) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && int32(c) >= 3 |
| // result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && int32(c) >= 3 |
| // result: (NEG (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MNEGW_10(v *Value) bool { |
| b := v.Block |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && int32(c) >= 7 |
| // result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && int32(c) >= 7 |
| // result: (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log2(c+1)])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (SLLconst <x.Type> [log2(c/3)] (SUBshiftLL <x.Type> x x [2])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 5) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 2 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 5) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 2 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (SLLconst <x.Type> [log2(c/7)] (SUBshiftLL <x.Type> x x [3])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.Type = x.Type |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 9) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 3 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (NEG (SLLconst <x.Type> [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, x.Type) |
| v0.AuxInt = log2(c / 9) |
| v1 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v1.AuxInt = 3 |
| v1.AddArg(x) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MNEGW_20(v *Value) bool { |
| // match: (MNEGW (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [-int64(int32(c)*int32(d))]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -int64(int32(c) * int32(d)) |
| return true |
| } |
| // match: (MNEGW (MOVDconst [d]) (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [-int64(int32(c)*int32(d))]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -int64(int32(c) * int32(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOD_0(v *Value) bool { |
| // match: (MOD (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [c%d]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c % d |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MODW_0(v *Value) bool { |
| // match: (MODW (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [int64(int32(c)%int32(d))]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int32(c) % int32(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBUload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBUload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBUload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBUload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVBUloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVBUloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBUload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVBstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MOVBUload [off] {sym} (SB) _) |
| // cond: symIsRO(sym) |
| // result: (MOVDconst [int64(read8(sym, off))]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpSB { |
| break |
| } |
| if !(symIsRO(sym)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(read8(sym, off)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBUloadidx_0(v *Value) bool { |
| // match: (MOVBUloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVBUload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVBUload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBUloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVBUload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVBUload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVBstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBUreg_0(v *Value) bool { |
| // match: (MOVBUreg x:(MOVBUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBUreg x:(MOVBUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBUreg (ANDconst [c] x)) |
| // cond: |
| // result: (ANDconst [c&(1<<8-1)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & (1<<8 - 1) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBUreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(uint8(c))]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(uint8(c)) |
| return true |
| } |
| // match: (MOVBUreg x) |
| // cond: x.Type.IsBoolean() |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if !(x.Type.IsBoolean()) { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBUreg (SLLconst [sc] x)) |
| // cond: isARM64BFMask(sc, 1<<8-1, sc) |
| // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(1<<8-1, sc))] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, 1<<8-1, sc)) { |
| break |
| } |
| v.reset(OpARM64UBFIZ) |
| v.AuxInt = armBFAuxInt(sc, arm64BFWidth(1<<8-1, sc)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBUreg (SRLconst [sc] x)) |
| // cond: isARM64BFMask(sc, 1<<8-1, 0) |
| // result: (UBFX [armBFAuxInt(sc, 8)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, 1<<8-1, 0)) { |
| break |
| } |
| v.reset(OpARM64UBFX) |
| v.AuxInt = armBFAuxInt(sc, 8) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVBloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVBloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVBstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBloadidx_0(v *Value) bool { |
| // match: (MOVBloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVBload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVBload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVBload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVBload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVBstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBreg_0(v *Value) bool { |
| // match: (MOVBreg x:(MOVBload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBreg x:(MOVBloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBreg x:(MOVBreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVBreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(int8(c))]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int8(c)) |
| return true |
| } |
| // match: (MOVBreg (SLLconst [lc] x)) |
| // cond: lc < 8 |
| // result: (SBFIZ [armBFAuxInt(lc, 8-lc)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| lc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(lc < 8) { |
| break |
| } |
| v.reset(OpARM64SBFIZ) |
| v.AuxInt = armBFAuxInt(lc, 8-lc) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstore_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBstore [off1+off2] {sym} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} (ADD ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVBstoreidx ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVBstorezero [off] {sym} ptr mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVBstorezero) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVBreg x) mem) |
| // cond: |
| // result: (MOVBstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVBreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) |
| // cond: |
| // result: (MOVBstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVBUreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVHreg x) mem) |
| // cond: |
| // result: (MOVBstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVHreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) |
| // cond: |
| // result: (MOVBstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVHUreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVWreg x) mem) |
| // cond: |
| // result: (MOVBstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVBstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstore_10(v *Value) bool { |
| // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 8 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] w) x:(MOVBstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 8 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 8)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr0 (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstore [i-1] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(8, 24)] w) x:(MOVBstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr0 (SRLconst [8] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 8 { |
| break |
| } |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [8] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 8 { |
| break |
| } |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] w) mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| w0 := x.Args[1] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-8 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w0 mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-8 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstore_20(v *Value) bool { |
| b := v.Block |
| // match: (MOVBstore [i] {s} ptr0 (UBFX [bfc] w) x:(MOVBstore [i-1] {s} ptr1 w0:(UBFX [bfc2] w) mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && getARM64BFwidth(bfc) == 32 - getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32 - getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc) - 8 && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| bfc := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| w0 := x.Args[1] |
| if w0.Op != OpARM64UBFX { |
| break |
| } |
| bfc2 := w0.AuxInt |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && getARM64BFwidth(bfc) == 32-getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32-getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc)-8 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (UBFX [bfc] w) x:(MOVBstoreidx ptr1 idx1 w0:(UBFX [bfc2] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && getARM64BFwidth(bfc) == 32 - getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32 - getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc) - 8 && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w0 mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| bfc := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64UBFX { |
| break |
| } |
| bfc2 := w0.AuxInt |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && getARM64BFwidth(bfc) == 32-getARM64BFlsb(bfc) && getARM64BFwidth(bfc2) == 32-getARM64BFlsb(bfc2) && getARM64BFlsb(bfc2) == getARM64BFlsb(bfc)-8 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr0 (SRLconst [j] (MOVDreg w)) x:(MOVBstore [i-1] {s} ptr1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr0 w0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| w0 := x.Args[1] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-8 { |
| break |
| } |
| w0_0 := w0.Args[0] |
| if w0_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != w0_0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr0 idx0) (SRLconst [j] (MOVDreg w)) x:(MOVBstoreidx ptr1 idx1 w0:(SRLconst [j-8] (MOVDreg w)) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr1 idx1 w0 mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-8 { |
| break |
| } |
| w0_0 := w0.Args[0] |
| if w0_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != w0_0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) x3:(MOVBstore [i-4] {s} ptr (SRLconst [32] w) x4:(MOVBstore [i-5] {s} ptr (SRLconst [40] w) x5:(MOVBstore [i-6] {s} ptr (SRLconst [48] w) x6:(MOVBstore [i-7] {s} ptr (SRLconst [56] w) mem)))))))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) |
| // result: (MOVDstore [i-7] {s} ptr (REV <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != i-1 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x0_1.AuxInt != 8 { |
| break |
| } |
| if w != x0_1.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != i-2 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x1_1.AuxInt != 16 { |
| break |
| } |
| if w != x1_1.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstore { |
| break |
| } |
| if x2.AuxInt != i-3 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| _ = x2.Args[2] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x2_1.AuxInt != 24 { |
| break |
| } |
| if w != x2_1.Args[0] { |
| break |
| } |
| x3 := x2.Args[2] |
| if x3.Op != OpARM64MOVBstore { |
| break |
| } |
| if x3.AuxInt != i-4 { |
| break |
| } |
| if x3.Aux != s { |
| break |
| } |
| _ = x3.Args[2] |
| if ptr != x3.Args[0] { |
| break |
| } |
| x3_1 := x3.Args[1] |
| if x3_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x3_1.AuxInt != 32 { |
| break |
| } |
| if w != x3_1.Args[0] { |
| break |
| } |
| x4 := x3.Args[2] |
| if x4.Op != OpARM64MOVBstore { |
| break |
| } |
| if x4.AuxInt != i-5 { |
| break |
| } |
| if x4.Aux != s { |
| break |
| } |
| _ = x4.Args[2] |
| if ptr != x4.Args[0] { |
| break |
| } |
| x4_1 := x4.Args[1] |
| if x4_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x4_1.AuxInt != 40 { |
| break |
| } |
| if w != x4_1.Args[0] { |
| break |
| } |
| x5 := x4.Args[2] |
| if x5.Op != OpARM64MOVBstore { |
| break |
| } |
| if x5.AuxInt != i-6 { |
| break |
| } |
| if x5.Aux != s { |
| break |
| } |
| _ = x5.Args[2] |
| if ptr != x5.Args[0] { |
| break |
| } |
| x5_1 := x5.Args[1] |
| if x5_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x5_1.AuxInt != 48 { |
| break |
| } |
| if w != x5_1.Args[0] { |
| break |
| } |
| x6 := x5.Args[2] |
| if x6.Op != OpARM64MOVBstore { |
| break |
| } |
| if x6.AuxInt != i-7 { |
| break |
| } |
| if x6.Aux != s { |
| break |
| } |
| mem := x6.Args[2] |
| if ptr != x6.Args[0] { |
| break |
| } |
| x6_1 := x6.Args[1] |
| if x6_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x6_1.AuxInt != 56 { |
| break |
| } |
| if w != x6_1.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { |
| break |
| } |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = i - 7 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x6.Pos, OpARM64REV, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [7] {s} p w x0:(MOVBstore [6] {s} p (SRLconst [8] w) x1:(MOVBstore [5] {s} p (SRLconst [16] w) x2:(MOVBstore [4] {s} p (SRLconst [24] w) x3:(MOVBstore [3] {s} p (SRLconst [32] w) x4:(MOVBstore [2] {s} p (SRLconst [40] w) x5:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [48] w) x6:(MOVBstoreidx ptr0 idx0 (SRLconst [56] w) mem)))))))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6) |
| // result: (MOVDstoreidx ptr0 idx0 (REV <w.Type> w) mem) |
| for { |
| if v.AuxInt != 7 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| p := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != 6 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if p != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x0_1.AuxInt != 8 { |
| break |
| } |
| if w != x0_1.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != 5 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| if p != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x1_1.AuxInt != 16 { |
| break |
| } |
| if w != x1_1.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstore { |
| break |
| } |
| if x2.AuxInt != 4 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| _ = x2.Args[2] |
| if p != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x2_1.AuxInt != 24 { |
| break |
| } |
| if w != x2_1.Args[0] { |
| break |
| } |
| x3 := x2.Args[2] |
| if x3.Op != OpARM64MOVBstore { |
| break |
| } |
| if x3.AuxInt != 3 { |
| break |
| } |
| if x3.Aux != s { |
| break |
| } |
| _ = x3.Args[2] |
| if p != x3.Args[0] { |
| break |
| } |
| x3_1 := x3.Args[1] |
| if x3_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x3_1.AuxInt != 32 { |
| break |
| } |
| if w != x3_1.Args[0] { |
| break |
| } |
| x4 := x3.Args[2] |
| if x4.Op != OpARM64MOVBstore { |
| break |
| } |
| if x4.AuxInt != 2 { |
| break |
| } |
| if x4.Aux != s { |
| break |
| } |
| _ = x4.Args[2] |
| if p != x4.Args[0] { |
| break |
| } |
| x4_1 := x4.Args[1] |
| if x4_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x4_1.AuxInt != 40 { |
| break |
| } |
| if w != x4_1.Args[0] { |
| break |
| } |
| x5 := x4.Args[2] |
| if x5.Op != OpARM64MOVBstore { |
| break |
| } |
| if x5.AuxInt != 1 { |
| break |
| } |
| if x5.Aux != s { |
| break |
| } |
| _ = x5.Args[2] |
| p1 := x5.Args[0] |
| if p1.Op != OpARM64ADD { |
| break |
| } |
| idx1 := p1.Args[1] |
| ptr1 := p1.Args[0] |
| x5_1 := x5.Args[1] |
| if x5_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x5_1.AuxInt != 48 { |
| break |
| } |
| if w != x5_1.Args[0] { |
| break |
| } |
| x6 := x5.Args[2] |
| if x6.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x6.Args[3] |
| ptr0 := x6.Args[0] |
| idx0 := x6.Args[1] |
| x6_2 := x6.Args[2] |
| if x6_2.Op != OpARM64SRLconst { |
| break |
| } |
| if x6_2.AuxInt != 56 { |
| break |
| } |
| if w != x6_2.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && x4.Uses == 1 && x5.Uses == 1 && x6.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(x4) && clobber(x5) && clobber(x6)) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(x5.Pos, OpARM64REV, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [i-2] {s} ptr (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstore [i-3] {s} ptr (UBFX [armBFAuxInt(24, 8)] w) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstore [i-3] {s} ptr (REVW <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != i-1 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64UBFX { |
| break |
| } |
| if x0_1.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| if w != x0_1.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != i-2 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64UBFX { |
| break |
| } |
| if x1_1.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| if w != x1_1.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstore { |
| break |
| } |
| if x2.AuxInt != i-3 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| mem := x2.Args[2] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64UBFX { |
| break |
| } |
| if x2_1.AuxInt != armBFAuxInt(24, 8) { |
| break |
| } |
| if w != x2_1.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 3 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(24, 8)] w) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstoreidx ptr0 idx0 (REVW <w.Type> w) mem) |
| for { |
| if v.AuxInt != 3 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| p := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != 2 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if p != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64UBFX { |
| break |
| } |
| if x0_1.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| if w != x0_1.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != 1 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| p1 := x1.Args[0] |
| if p1.Op != OpARM64ADD { |
| break |
| } |
| idx1 := p1.Args[1] |
| ptr1 := p1.Args[0] |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64UBFX { |
| break |
| } |
| if x1_1.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| if w != x1_1.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x2.Args[3] |
| ptr0 := x2.Args[0] |
| idx0 := x2.Args[1] |
| x2_2 := x2.Args[2] |
| if x2_2.Op != OpARM64UBFX { |
| break |
| } |
| if x2_2.AuxInt != armBFAuxInt(24, 8) { |
| break |
| } |
| if w != x2_2.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] (MOVDreg w)) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] (MOVDreg w)) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstore [i-3] {s} ptr (REVW <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != i-1 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x0_1.AuxInt != 8 { |
| break |
| } |
| x0_1_0 := x0_1.Args[0] |
| if x0_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x0_1_0.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != i-2 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x1_1.AuxInt != 16 { |
| break |
| } |
| x1_1_0 := x1_1.Args[0] |
| if x1_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x1_1_0.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstore { |
| break |
| } |
| if x2.AuxInt != i-3 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| mem := x2.Args[2] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x2_1.AuxInt != 24 { |
| break |
| } |
| x2_1_0 := x2_1.Args[0] |
| if x2_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x2_1_0.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 3 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] (MOVDreg w)) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] (MOVDreg w)) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] (MOVDreg w)) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstoreidx ptr0 idx0 (REVW <w.Type> w) mem) |
| for { |
| if v.AuxInt != 3 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| p := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != 2 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if p != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x0_1.AuxInt != 8 { |
| break |
| } |
| x0_1_0 := x0_1.Args[0] |
| if x0_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x0_1_0.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != 1 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| p1 := x1.Args[0] |
| if p1.Op != OpARM64ADD { |
| break |
| } |
| idx1 := p1.Args[1] |
| ptr1 := p1.Args[0] |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x1_1.AuxInt != 16 { |
| break |
| } |
| x1_1_0 := x1_1.Args[0] |
| if x1_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x1_1_0.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x2.Args[3] |
| ptr0 := x2.Args[0] |
| idx0 := x2.Args[1] |
| x2_2 := x2.Args[2] |
| if x2_2.Op != OpARM64SRLconst { |
| break |
| } |
| if x2_2.AuxInt != 24 { |
| break |
| } |
| x2_2_0 := x2_2.Args[0] |
| if x2_2_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x2_2_0.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstore_30(v *Value) bool { |
| b := v.Block |
| // match: (MOVBstore [i] {s} ptr w x0:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) x1:(MOVBstore [i-2] {s} ptr (SRLconst [16] w) x2:(MOVBstore [i-3] {s} ptr (SRLconst [24] w) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstore [i-3] {s} ptr (REVW <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != i-1 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x0_1.AuxInt != 8 { |
| break |
| } |
| if w != x0_1.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != i-2 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x1_1.AuxInt != 16 { |
| break |
| } |
| if w != x1_1.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstore { |
| break |
| } |
| if x2.AuxInt != i-3 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| mem := x2.Args[2] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x2_1.AuxInt != 24 { |
| break |
| } |
| if w != x2_1.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 3 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x2.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [3] {s} p w x0:(MOVBstore [2] {s} p (SRLconst [8] w) x1:(MOVBstore [1] {s} p1:(ADD ptr1 idx1) (SRLconst [16] w) x2:(MOVBstoreidx ptr0 idx0 (SRLconst [24] w) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstoreidx ptr0 idx0 (REVW <w.Type> w) mem) |
| for { |
| if v.AuxInt != 3 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| p := v.Args[0] |
| w := v.Args[1] |
| x0 := v.Args[2] |
| if x0.Op != OpARM64MOVBstore { |
| break |
| } |
| if x0.AuxInt != 2 { |
| break |
| } |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[2] |
| if p != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x0_1.AuxInt != 8 { |
| break |
| } |
| if w != x0_1.Args[0] { |
| break |
| } |
| x1 := x0.Args[2] |
| if x1.Op != OpARM64MOVBstore { |
| break |
| } |
| if x1.AuxInt != 1 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[2] |
| p1 := x1.Args[0] |
| if p1.Op != OpARM64ADD { |
| break |
| } |
| idx1 := p1.Args[1] |
| ptr1 := p1.Args[0] |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x1_1.AuxInt != 16 { |
| break |
| } |
| if w != x1_1.Args[0] { |
| break |
| } |
| x2 := x1.Args[2] |
| if x2.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x2.Args[3] |
| ptr0 := x2.Args[0] |
| idx0 := x2.Args[1] |
| x2_2 := x2.Args[2] |
| if x2_2.Op != OpARM64SRLconst { |
| break |
| } |
| if x2_2.AuxInt != 24 { |
| break |
| } |
| if w != x2_2.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(x1.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] w) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| x_1 := x.Args[1] |
| if x_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x_1.AuxInt != 8 { |
| break |
| } |
| if w != x_1.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx1 := v_0.Args[1] |
| ptr1 := v_0.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr0 := x.Args[0] |
| idx0 := x.Args[1] |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64SRLconst { |
| break |
| } |
| if x_2.AuxInt != 8 { |
| break |
| } |
| if w != x_2.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 8)] w) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| x_1 := x.Args[1] |
| if x_1.Op != OpARM64UBFX { |
| break |
| } |
| if x_1.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| if w != x_1.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 8)] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx1 := v_0.Args[1] |
| ptr1 := v_0.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr0 := x.Args[0] |
| idx0 := x.Args[1] |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64UBFX { |
| break |
| } |
| if x_2.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| if w != x_2.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| x_1 := x.Args[1] |
| if x_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x_1.AuxInt != 8 { |
| break |
| } |
| x_1_0 := x_1.Args[0] |
| if x_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x_1_0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx1 := v_0.Args[1] |
| ptr1 := v_0.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr0 := x.Args[0] |
| idx0 := x.Args[1] |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64SRLconst { |
| break |
| } |
| if x_2.AuxInt != 8 { |
| break |
| } |
| x_2_0 := x_2.Args[0] |
| if x_2_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x_2_0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (UBFX [armBFAuxInt(8, 24)] w) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| x_1 := x.Args[1] |
| if x_1.Op != OpARM64UBFX { |
| break |
| } |
| if x_1.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| if w != x_1.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (UBFX [armBFAuxInt(8, 24)] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx1 := v_0.Args[1] |
| ptr1 := v_0.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr0 := x.Args[0] |
| idx0 := x.Args[1] |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64UBFX { |
| break |
| } |
| if x_2.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| if w != x_2.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstore_40(v *Value) bool { |
| b := v.Block |
| // match: (MOVBstore [i] {s} ptr w x:(MOVBstore [i-1] {s} ptr (SRLconst [8] (MOVDreg w)) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstore [i-1] {s} ptr (REV16W <w.Type> w) mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstore { |
| break |
| } |
| if x.AuxInt != i-1 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| x_1 := x.Args[1] |
| if x_1.Op != OpARM64SRLconst { |
| break |
| } |
| if x_1.AuxInt != 8 { |
| break |
| } |
| x_1_0 := x_1.Args[0] |
| if x_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x_1_0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = i - 1 |
| v.Aux = s |
| v.AddArg(ptr) |
| v0 := b.NewValue0(x.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstore [1] {s} (ADD ptr1 idx1) w x:(MOVBstoreidx ptr0 idx0 (SRLconst [8] (MOVDreg w)) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstoreidx ptr0 idx0 (REV16W <w.Type> w) mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx1 := v_0.Args[1] |
| ptr1 := v_0.Args[0] |
| w := v.Args[1] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr0 := x.Args[0] |
| idx0 := x.Args[1] |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64SRLconst { |
| break |
| } |
| if x_2.AuxInt != 8 { |
| break |
| } |
| x_2_0 := x_2.Args[0] |
| if x_2_0.Op != OpARM64MOVDreg { |
| break |
| } |
| if w != x_2_0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr0) |
| v.AddArg(idx0) |
| v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstoreidx_0(v *Value) bool { |
| // match: (MOVBstoreidx ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVBstore [c] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx (MOVDconst [c]) idx val mem) |
| // cond: |
| // result: (MOVBstore [c] idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVBstore) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVBstorezeroidx ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVBstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVBreg x) mem) |
| // cond: |
| // result: (MOVBstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVBreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVBUreg x) mem) |
| // cond: |
| // result: (MOVBstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVBUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVHreg x) mem) |
| // cond: |
| // result: (MOVBstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVHUreg x) mem) |
| // cond: |
| // result: (MOVBstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVWreg x) mem) |
| // cond: |
| // result: (MOVBstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVBstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVBstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr (ADDconst [1] idx) (SRLconst [8] w) x:(MOVBstoreidx ptr idx w mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstoreidx ptr idx w mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64SRLconst { |
| break |
| } |
| if v_2.AuxInt != 8 { |
| break |
| } |
| w := v_2.Args[0] |
| x := v.Args[3] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstoreidx_10(v *Value) bool { |
| b := v.Block |
| // match: (MOVBstoreidx ptr (ADDconst [3] idx) w x0:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(24, 8)] w) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstoreidx ptr idx (REVW <w.Type> w) mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 3 { |
| break |
| } |
| idx := v_1.Args[0] |
| w := v.Args[2] |
| x0 := v.Args[3] |
| if x0.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| _ = x0.Args[3] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x0_1.AuxInt != 2 { |
| break |
| } |
| if idx != x0_1.Args[0] { |
| break |
| } |
| x0_2 := x0.Args[2] |
| if x0_2.Op != OpARM64UBFX { |
| break |
| } |
| if x0_2.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| if w != x0_2.Args[0] { |
| break |
| } |
| x1 := x0.Args[3] |
| if x1.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| _ = x1.Args[3] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x1_1.AuxInt != 1 { |
| break |
| } |
| if idx != x1_1.Args[0] { |
| break |
| } |
| x1_2 := x1.Args[2] |
| if x1_2.Op != OpARM64UBFX { |
| break |
| } |
| if x1_2.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| if w != x1_2.Args[0] { |
| break |
| } |
| x2 := x1.Args[3] |
| if x2.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x2.Args[3] |
| if ptr != x2.Args[0] { |
| break |
| } |
| if idx != x2.Args[1] { |
| break |
| } |
| x2_2 := x2.Args[2] |
| if x2_2.Op != OpARM64UBFX { |
| break |
| } |
| if x2_2.AuxInt != armBFAuxInt(24, 8) { |
| break |
| } |
| if w != x2_2.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v0 := b.NewValue0(v.Pos, OpARM64REVW, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx w x0:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 24)] w) x1:(MOVBstoreidx ptr (ADDconst [2] idx) (UBFX [armBFAuxInt(16, 16)] w) x2:(MOVBstoreidx ptr (ADDconst [3] idx) (UBFX [armBFAuxInt(24, 8)] w) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2) |
| // result: (MOVWstoreidx ptr idx w mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| w := v.Args[2] |
| x0 := v.Args[3] |
| if x0.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| _ = x0.Args[3] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x0_1.AuxInt != 1 { |
| break |
| } |
| if idx != x0_1.Args[0] { |
| break |
| } |
| x0_2 := x0.Args[2] |
| if x0_2.Op != OpARM64UBFX { |
| break |
| } |
| if x0_2.AuxInt != armBFAuxInt(8, 24) { |
| break |
| } |
| if w != x0_2.Args[0] { |
| break |
| } |
| x1 := x0.Args[3] |
| if x1.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| _ = x1.Args[3] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x1_1.AuxInt != 2 { |
| break |
| } |
| if idx != x1_1.Args[0] { |
| break |
| } |
| x1_2 := x1.Args[2] |
| if x1_2.Op != OpARM64UBFX { |
| break |
| } |
| if x1_2.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| if w != x1_2.Args[0] { |
| break |
| } |
| x2 := x1.Args[3] |
| if x2.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x2.Args[3] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x2_1.AuxInt != 3 { |
| break |
| } |
| if idx != x2_1.Args[0] { |
| break |
| } |
| x2_2 := x2.Args[2] |
| if x2_2.Op != OpARM64UBFX { |
| break |
| } |
| if x2_2.AuxInt != armBFAuxInt(24, 8) { |
| break |
| } |
| if w != x2_2.Args[0] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && clobber(x0) && clobber(x1) && clobber(x2)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr (ADDconst [1] idx) w x:(MOVBstoreidx ptr idx (UBFX [armBFAuxInt(8, 8)] w) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstoreidx ptr idx (REV16W <w.Type> w) mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| w := v.Args[2] |
| x := v.Args[3] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64UBFX { |
| break |
| } |
| if x_2.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| if w != x_2.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v0 := b.NewValue0(v.Pos, OpARM64REV16W, w.Type) |
| v0.AddArg(w) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstoreidx ptr idx w x:(MOVBstoreidx ptr (ADDconst [1] idx) (UBFX [armBFAuxInt(8, 8)] w) mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstoreidx ptr idx w mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| w := v.Args[2] |
| x := v.Args[3] |
| if x.Op != OpARM64MOVBstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| if ptr != x.Args[0] { |
| break |
| } |
| x_1 := x.Args[1] |
| if x_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x_1.AuxInt != 1 { |
| break |
| } |
| if idx != x_1.Args[0] { |
| break |
| } |
| x_2 := x.Args[2] |
| if x_2.Op != OpARM64UBFX { |
| break |
| } |
| if x_2.AuxInt != armBFAuxInt(8, 8) { |
| break |
| } |
| if w != x_2.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstorezero_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBstorezero [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVBstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstorezero [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVBstorezeroidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVBstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstorezero [i] {s} ptr0 x:(MOVBstorezero [j] {s} ptr1 mem)) |
| // cond: x.Uses == 1 && areAdjacentOffsets(i,j,1) && is32Bit(min(i,j)) && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVHstorezero [min(i,j)] {s} ptr0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[1] |
| ptr0 := v.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVBstorezero { |
| break |
| } |
| j := x.AuxInt |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[1] |
| ptr1 := x.Args[0] |
| if !(x.Uses == 1 && areAdjacentOffsets(i, j, 1) && is32Bit(min(i, j)) && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = min(i, j) |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstorezero [1] {s} (ADD ptr0 idx0) x:(MOVBstorezeroidx ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVHstorezeroidx ptr1 idx1 mem) |
| for { |
| if v.AuxInt != 1 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVBstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVBstorezeroidx_0(v *Value) bool { |
| // match: (MOVBstorezeroidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVBstorezero [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVBstorezero) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstorezeroidx (MOVDconst [c]) idx mem) |
| // cond: |
| // result: (MOVBstorezero [c] idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| v.reset(OpARM64MOVBstorezero) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVBstorezeroidx ptr (ADDconst [1] idx) x:(MOVBstorezeroidx ptr idx mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVHstorezeroidx ptr idx mem) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVBstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) |
| // cond: |
| // result: (FMOVDfpgp val) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVDstore { |
| break |
| } |
| if v_1.AuxInt != off { |
| break |
| } |
| if v_1.Aux != sym { |
| break |
| } |
| _ = v_1.Args[2] |
| if ptr != v_1.Args[0] { |
| break |
| } |
| val := v_1.Args[1] |
| v.reset(OpARM64FMOVDfpgp) |
| v.AddArg(val) |
| return true |
| } |
| // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVDload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVDload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVDloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVDloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVDloadidx8 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 3 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVDloadidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVDload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MOVDload [off] {sym} (SB) _) |
| // cond: symIsRO(sym) |
| // result: (MOVDconst [int64(read64(sym, off, config.BigEndian))]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpSB { |
| break |
| } |
| if !(symIsRO(sym)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(read64(sym, off, config.BigEndian)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDloadidx_0(v *Value) bool { |
| // match: (MOVDloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVDload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVDload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVDload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDloadidx ptr (SLLconst [3] idx) mem) |
| // cond: |
| // result: (MOVDloadidx8 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 3 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVDloadidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDloadidx (SLLconst [3] idx) ptr mem) |
| // cond: |
| // result: (MOVDloadidx8 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 3 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVDloadidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDloadidx8_0(v *Value) bool { |
| // match: (MOVDloadidx8 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVDload [c<<3] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDload) |
| v.AuxInt = c << 3 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) |
| // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDstorezeroidx8 { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDreg_0(v *Value) bool { |
| // match: (MOVDreg x) |
| // cond: x.Uses == 1 |
| // result: (MOVDnop x) |
| for { |
| x := v.Args[0] |
| if !(x.Uses == 1) { |
| break |
| } |
| v.reset(OpARM64MOVDnop) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVDreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [c]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDstore_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) |
| // cond: |
| // result: (FMOVDstore [off] {sym} ptr val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVDfpgp { |
| break |
| } |
| val := v_1.Args[0] |
| v.reset(OpARM64FMOVDstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVDstore [off1+off2] {sym} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstore [off] {sym} (ADD ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVDstoreidx ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVDstoreidx8 ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 3 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVDstorezero [off] {sym} ptr mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDstoreidx_0(v *Value) bool { |
| // match: (MOVDstoreidx ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVDstore [c] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstoreidx (MOVDconst [c]) idx val mem) |
| // cond: |
| // result: (MOVDstore [c] idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstoreidx ptr (SLLconst [3] idx) val mem) |
| // cond: |
| // result: (MOVDstoreidx8 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 3 { |
| break |
| } |
| idx := v_1.Args[0] |
| val := v.Args[2] |
| v.reset(OpARM64MOVDstoreidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstoreidx (SLLconst [3] idx) ptr val mem) |
| // cond: |
| // result: (MOVDstoreidx8 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 3 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVDstoreidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstoreidx ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVDstorezeroidx ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDstoreidx8_0(v *Value) bool { |
| // match: (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVDstore [c<<3] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = c << 3 |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVDstorezeroidx8 ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDstorezero_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVDstorezero [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezero [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVDstorezeroidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVDstorezeroidx8 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 3 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezero [i] {s} ptr0 x:(MOVDstorezero [j] {s} ptr1 mem)) |
| // cond: x.Uses == 1 && areAdjacentOffsets(i,j,8) && is32Bit(min(i,j)) && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVQstorezero [min(i,j)] {s} ptr0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[1] |
| ptr0 := v.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVDstorezero { |
| break |
| } |
| j := x.AuxInt |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[1] |
| ptr1 := x.Args[0] |
| if !(x.Uses == 1 && areAdjacentOffsets(i, j, 8) && is32Bit(min(i, j)) && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVQstorezero) |
| v.AuxInt = min(i, j) |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezero [8] {s} p0:(ADD ptr0 idx0) x:(MOVDstorezeroidx ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVQstorezero [0] {s} p0 mem) |
| for { |
| if v.AuxInt != 8 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| p0 := v.Args[0] |
| if p0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := p0.Args[1] |
| ptr0 := p0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVDstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVQstorezero) |
| v.AuxInt = 0 |
| v.Aux = s |
| v.AddArg(p0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezero [8] {s} p0:(ADDshiftLL [3] ptr0 idx0) x:(MOVDstorezeroidx8 ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVQstorezero [0] {s} p0 mem) |
| for { |
| if v.AuxInt != 8 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| p0 := v.Args[0] |
| if p0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if p0.AuxInt != 3 { |
| break |
| } |
| idx0 := p0.Args[1] |
| ptr0 := p0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVDstorezeroidx8 { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVQstorezero) |
| v.AuxInt = 0 |
| v.Aux = s |
| v.AddArg(p0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDstorezeroidx_0(v *Value) bool { |
| // match: (MOVDstorezeroidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVDstorezero [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezeroidx (MOVDconst [c]) idx mem) |
| // cond: |
| // result: (MOVDstorezero [c] idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezeroidx ptr (SLLconst [3] idx) mem) |
| // cond: |
| // result: (MOVDstorezeroidx8 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 3 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVDstorezeroidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVDstorezeroidx (SLLconst [3] idx) ptr mem) |
| // cond: |
| // result: (MOVDstorezeroidx8 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 3 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVDstorezeroidx8) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVDstorezeroidx8_0(v *Value) bool { |
| // match: (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVDstorezero [c<<3] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = c << 3 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHUload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHUload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHUload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHUloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHUloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHUloadidx2 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHUloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHUload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVHstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MOVHUload [off] {sym} (SB) _) |
| // cond: symIsRO(sym) |
| // result: (MOVDconst [int64(read16(sym, off, config.BigEndian))]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpSB { |
| break |
| } |
| if !(symIsRO(sym)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(read16(sym, off, config.BigEndian)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHUloadidx_0(v *Value) bool { |
| // match: (MOVHUloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVHUload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVHUload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVHUload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVHUload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUloadidx ptr (SLLconst [1] idx) mem) |
| // cond: |
| // result: (MOVHUloadidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVHUloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUloadidx ptr (ADD idx idx) mem) |
| // cond: |
| // result: (MOVHUloadidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADD { |
| break |
| } |
| idx := v_1.Args[1] |
| if idx != v_1.Args[0] { |
| break |
| } |
| v.reset(OpARM64MOVHUloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUloadidx (ADD idx idx) ptr mem) |
| // cond: |
| // result: (MOVHUloadidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| if idx != v_0.Args[0] { |
| break |
| } |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVHUloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHUloadidx2_0(v *Value) bool { |
| // match: (MOVHUloadidx2 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVHUload [c<<1] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVHUload) |
| v.AuxInt = c << 1 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) |
| // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHstorezeroidx2 { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHUreg_0(v *Value) bool { |
| // match: (MOVHUreg x:(MOVBUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg x:(MOVHUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg x:(MOVBUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg x:(MOVHUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg x:(MOVHUloadidx2 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUloadidx2 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg x:(MOVBUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg x:(MOVHUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg (ANDconst [c] x)) |
| // cond: |
| // result: (ANDconst [c&(1<<16-1)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & (1<<16 - 1) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHUreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(uint16(c))]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(uint16(c)) |
| return true |
| } |
| // match: (MOVHUreg (SLLconst [sc] x)) |
| // cond: isARM64BFMask(sc, 1<<16-1, sc) |
| // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(1<<16-1, sc))] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, 1<<16-1, sc)) { |
| break |
| } |
| v.reset(OpARM64UBFIZ) |
| v.AuxInt = armBFAuxInt(sc, arm64BFWidth(1<<16-1, sc)) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHUreg_10(v *Value) bool { |
| // match: (MOVHUreg (SRLconst [sc] x)) |
| // cond: isARM64BFMask(sc, 1<<16-1, 0) |
| // result: (UBFX [armBFAuxInt(sc, 16)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, 1<<16-1, 0)) { |
| break |
| } |
| v.reset(OpARM64UBFX) |
| v.AuxInt = armBFAuxInt(sc, 16) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHloadidx2 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVHstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHloadidx_0(v *Value) bool { |
| // match: (MOVHloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVHload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVHload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVHload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVHload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHloadidx ptr (SLLconst [1] idx) mem) |
| // cond: |
| // result: (MOVHloadidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVHloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHloadidx ptr (ADD idx idx) mem) |
| // cond: |
| // result: (MOVHloadidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADD { |
| break |
| } |
| idx := v_1.Args[1] |
| if idx != v_1.Args[0] { |
| break |
| } |
| v.reset(OpARM64MOVHloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHloadidx (ADD idx idx) ptr mem) |
| // cond: |
| // result: (MOVHloadidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| if idx != v_0.Args[0] { |
| break |
| } |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVHloadidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHloadidx2_0(v *Value) bool { |
| // match: (MOVHloadidx2 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVHload [c<<1] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVHload) |
| v.AuxInt = c << 1 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) |
| // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHstorezeroidx2 { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHreg_0(v *Value) bool { |
| // match: (MOVHreg x:(MOVBload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVBUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVHload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVBloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVBUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVHloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVHloadidx2 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHloadidx2 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVBreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVBUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVHreg x:(MOVHreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHreg_10(v *Value) bool { |
| // match: (MOVHreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(int16(c))]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int16(c)) |
| return true |
| } |
| // match: (MOVHreg (SLLconst [lc] x)) |
| // cond: lc < 16 |
| // result: (SBFIZ [armBFAuxInt(lc, 16-lc)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| lc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(lc < 16) { |
| break |
| } |
| v.reset(OpARM64SBFIZ) |
| v.AuxInt = armBFAuxInt(lc, 16-lc) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstore_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHstore [off1+off2] {sym} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} (ADD ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHstoreidx ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHstoreidx2 ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVHstorezero [off] {sym} ptr mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} ptr (MOVHreg x) mem) |
| // cond: |
| // result: (MOVHstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVHreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) |
| // cond: |
| // result: (MOVHstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVHUreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} ptr (MOVWreg x) mem) |
| // cond: |
| // result: (MOVHstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVHstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVWstore [i-2] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 16 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstore { |
| break |
| } |
| if x.AuxInt != i-2 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 2 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstore_10(v *Value) bool { |
| b := v.Block |
| // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVWstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 16 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVWstoreidx ptr1 (SLLconst <idx1.Type> [1] idx1) w mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 16 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx2 { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [i] {s} ptr0 (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstore [i-2] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVWstore [i-2] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstore { |
| break |
| } |
| if x.AuxInt != i-2 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 2 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVWstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (UBFX [armBFAuxInt(16, 16)] w) x:(MOVHstoreidx2 ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVWstoreidx ptr1 (SLLconst <idx1.Type> [1] idx1) w mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| if v_1.AuxInt != armBFAuxInt(16, 16) { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx2 { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [i] {s} ptr0 (SRLconst [16] (MOVDreg w)) x:(MOVHstore [i-2] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVWstore [i-2] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 16 { |
| break |
| } |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstore { |
| break |
| } |
| if x.AuxInt != i-2 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 2 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVWstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 16 { |
| break |
| } |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [16] (MOVDreg w)) x:(MOVHstoreidx2 ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVWstoreidx ptr1 (SLLconst <idx1.Type> [1] idx1) w mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 16 { |
| break |
| } |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVDreg { |
| break |
| } |
| w := v_1_0.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx2 { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVHstore [i-2] {s} ptr1 w0:(SRLconst [j-16] w) mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVWstore [i-2] {s} ptr0 w0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstore { |
| break |
| } |
| if x.AuxInt != i-2 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| w0 := x.Args[1] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-16 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = i - 2 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstore [2] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx ptr1 idx1 w0:(SRLconst [j-16] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVWstoreidx ptr1 idx1 w0 mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-16 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstore_20(v *Value) bool { |
| b := v.Block |
| // match: (MOVHstore [2] {s} (ADDshiftLL [1] ptr0 idx0) (SRLconst [j] w) x:(MOVHstoreidx2 ptr1 idx1 w0:(SRLconst [j-16] w) mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVWstoreidx ptr1 (SLLconst <idx1.Type> [1] idx1) w0 mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstoreidx2 { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-16 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstoreidx_0(v *Value) bool { |
| // match: (MOVHstoreidx ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVHstore [c] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx (MOVDconst [c]) idx val mem) |
| // cond: |
| // result: (MOVHstore [c] idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr (SLLconst [1] idx) val mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr (ADD idx idx) val mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADD { |
| break |
| } |
| idx := v_1.Args[1] |
| if idx != v_1.Args[0] { |
| break |
| } |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx (SLLconst [1] idx) ptr val mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx (ADD idx idx) ptr val mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| if idx != v_0.Args[0] { |
| break |
| } |
| ptr := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVHstorezeroidx ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr idx (MOVHreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr idx (MOVHUreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr idx (MOVWreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstoreidx_10(v *Value) bool { |
| // match: (MOVHstoreidx ptr idx (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx ptr (ADDconst [2] idx) (SRLconst [16] w) x:(MOVHstoreidx ptr idx w mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVWstoreidx ptr idx w mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 2 { |
| break |
| } |
| idx := v_1.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64SRLconst { |
| break |
| } |
| if v_2.AuxInt != 16 { |
| break |
| } |
| w := v_2.Args[0] |
| x := v.Args[3] |
| if x.Op != OpARM64MOVHstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstoreidx2_0(v *Value) bool { |
| // match: (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVHstore [c<<1] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVHstore) |
| v.AuxInt = c << 1 |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVHstorezeroidx2 ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx2 ptr idx (MOVHreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVHUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx2 ptr idx (MOVWreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVHstoreidx2 ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVHstoreidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstorezero_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHstorezero [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezero [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHstorezeroidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVHstorezeroidx2 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezero [i] {s} ptr0 x:(MOVHstorezero [j] {s} ptr1 mem)) |
| // cond: x.Uses == 1 && areAdjacentOffsets(i,j,2) && is32Bit(min(i,j)) && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVWstorezero [min(i,j)] {s} ptr0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[1] |
| ptr0 := v.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVHstorezero { |
| break |
| } |
| j := x.AuxInt |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[1] |
| ptr1 := x.Args[0] |
| if !(x.Uses == 1 && areAdjacentOffsets(i, j, 2) && is32Bit(min(i, j)) && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = min(i, j) |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezero [2] {s} (ADD ptr0 idx0) x:(MOVHstorezeroidx ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVWstorezeroidx ptr1 idx1 mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVHstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezero [2] {s} (ADDshiftLL [1] ptr0 idx0) x:(MOVHstorezeroidx2 ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVWstorezeroidx ptr1 (SLLconst <idx1.Type> [1] idx1) mem) |
| for { |
| if v.AuxInt != 2 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVHstorezeroidx2 { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstorezeroidx_0(v *Value) bool { |
| // match: (MOVHstorezeroidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVHstorezero [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezeroidx (MOVDconst [c]) idx mem) |
| // cond: |
| // result: (MOVHstorezero [c] idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezeroidx ptr (SLLconst [1] idx) mem) |
| // cond: |
| // result: (MOVHstorezeroidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVHstorezeroidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezeroidx ptr (ADD idx idx) mem) |
| // cond: |
| // result: (MOVHstorezeroidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADD { |
| break |
| } |
| idx := v_1.Args[1] |
| if idx != v_1.Args[0] { |
| break |
| } |
| v.reset(OpARM64MOVHstorezeroidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezeroidx (SLLconst [1] idx) ptr mem) |
| // cond: |
| // result: (MOVHstorezeroidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVHstorezeroidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezeroidx (ADD idx idx) ptr mem) |
| // cond: |
| // result: (MOVHstorezeroidx2 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| if idx != v_0.Args[0] { |
| break |
| } |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVHstorezeroidx2) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVHstorezeroidx ptr (ADDconst [2] idx) x:(MOVHstorezeroidx ptr idx mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVWstorezeroidx ptr idx mem) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 2 { |
| break |
| } |
| idx := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVHstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVHstorezeroidx2_0(v *Value) bool { |
| // match: (MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVHstorezero [c<<1] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVHstorezero) |
| v.AuxInt = c << 1 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVQstorezero_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVQstorezero [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVQstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVQstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWUload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) |
| // cond: |
| // result: (FMOVSfpgp val) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVSstore { |
| break |
| } |
| if v_1.AuxInt != off { |
| break |
| } |
| if v_1.Aux != sym { |
| break |
| } |
| _ = v_1.Args[2] |
| if ptr != v_1.Args[0] { |
| break |
| } |
| val := v_1.Args[1] |
| v.reset(OpARM64FMOVSfpgp) |
| v.AddArg(val) |
| return true |
| } |
| // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWUload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWUload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWUloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWUloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWUloadidx4 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWUloadidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWUload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MOVWUload [off] {sym} (SB) _) |
| // cond: symIsRO(sym) |
| // result: (MOVDconst [int64(read32(sym, off, config.BigEndian))]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpSB { |
| break |
| } |
| if !(symIsRO(sym)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(read32(sym, off, config.BigEndian)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWUloadidx_0(v *Value) bool { |
| // match: (MOVWUloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVWUload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVWUload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVWUload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVWUload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUloadidx ptr (SLLconst [2] idx) mem) |
| // cond: |
| // result: (MOVWUloadidx4 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 2 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVWUloadidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUloadidx (SLLconst [2] idx) ptr mem) |
| // cond: |
| // result: (MOVWUloadidx4 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVWUloadidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWUloadidx4_0(v *Value) bool { |
| // match: (MOVWUloadidx4 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVWUload [c<<2] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVWUload) |
| v.AuxInt = c << 2 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) |
| // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWstorezeroidx4 { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWUreg_0(v *Value) bool { |
| // match: (MOVWUreg x:(MOVBUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVHUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVWUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVBUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVHUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVWUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVHUloadidx2 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUloadidx2 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVWUloadidx4 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWUloadidx4 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVBUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg x:(MOVHUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWUreg_10(v *Value) bool { |
| // match: (MOVWUreg x:(MOVWUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg (ANDconst [c] x)) |
| // cond: |
| // result: (ANDconst [c&(1<<32-1)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v_0.Args[0] |
| v.reset(OpARM64ANDconst) |
| v.AuxInt = c & (1<<32 - 1) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(uint32(c))]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(uint32(c)) |
| return true |
| } |
| // match: (MOVWUreg (SLLconst [sc] x)) |
| // cond: isARM64BFMask(sc, 1<<32-1, sc) |
| // result: (UBFIZ [armBFAuxInt(sc, arm64BFWidth(1<<32-1, sc))] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, 1<<32-1, sc)) { |
| break |
| } |
| v.reset(OpARM64UBFIZ) |
| v.AuxInt = armBFAuxInt(sc, arm64BFWidth(1<<32-1, sc)) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWUreg (SRLconst [sc] x)) |
| // cond: isARM64BFMask(sc, 1<<32-1, 0) |
| // result: (UBFX [armBFAuxInt(sc, 32)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRLconst { |
| break |
| } |
| sc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(isARM64BFMask(sc, 1<<32-1, 0)) { |
| break |
| } |
| v.reset(OpARM64UBFX) |
| v.AuxInt = armBFAuxInt(sc, 32) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWload_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWload [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWload) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWload [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWloadidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWloadidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWloadidx4 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWloadidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWload) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) |
| // cond: sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) |
| // result: (MOVDconst [0]) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| _ = v.Args[1] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWstorezero { |
| break |
| } |
| off2 := v_1.AuxInt |
| sym2 := v_1.Aux |
| _ = v_1.Args[1] |
| ptr2 := v_1.Args[0] |
| if !(sym == sym2 && off == off2 && isSamePtr(ptr, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWloadidx_0(v *Value) bool { |
| // match: (MOVWloadidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVWload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVWload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWloadidx (MOVDconst [c]) ptr mem) |
| // cond: |
| // result: (MOVWload [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVWload) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWloadidx ptr (SLLconst [2] idx) mem) |
| // cond: |
| // result: (MOVWloadidx4 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 2 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVWloadidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWloadidx (SLLconst [2] idx) ptr mem) |
| // cond: |
| // result: (MOVWloadidx4 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVWloadidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) |
| // cond: (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWstorezeroidx { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWloadidx4_0(v *Value) bool { |
| // match: (MOVWloadidx4 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVWload [c<<2] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVWload) |
| v.AuxInt = c << 2 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) |
| // cond: isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWstorezeroidx4 { |
| break |
| } |
| _ = v_2.Args[2] |
| ptr2 := v_2.Args[0] |
| idx2 := v_2.Args[1] |
| if !(isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2)) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWreg_0(v *Value) bool { |
| // match: (MOVWreg x:(MOVBload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVBUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHUload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVWload _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWload { |
| break |
| } |
| _ = x.Args[1] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVBloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVBUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHUloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVWloadidx _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWloadidx { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWreg_10(v *Value) bool { |
| // match: (MOVWreg x:(MOVHloadidx2 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHloadidx2 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHUloadidx2 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHUloadidx2 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVWloadidx4 _ _ _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWloadidx4 { |
| break |
| } |
| _ = x.Args[2] |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVBreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVBUreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVBUreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVHreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVHreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg x:(MOVWreg _)) |
| // cond: |
| // result: (MOVDreg x) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64MOVWreg { |
| break |
| } |
| v.reset(OpARM64MOVDreg) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MOVWreg (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(int32(c))]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int32(c)) |
| return true |
| } |
| // match: (MOVWreg (SLLconst [lc] x)) |
| // cond: lc < 32 |
| // result: (SBFIZ [armBFAuxInt(lc, 32-lc)] x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| lc := v_0.AuxInt |
| x := v_0.Args[0] |
| if !(lc < 32) { |
| break |
| } |
| v.reset(OpARM64SBFIZ) |
| v.AuxInt = armBFAuxInt(lc, 32-lc) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstore_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) |
| // cond: |
| // result: (FMOVSstore [off] {sym} ptr val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64FMOVSfpgp { |
| break |
| } |
| val := v_1.Args[0] |
| v.reset(OpARM64FMOVSstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWstore [off1+off2] {sym} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off] {sym} (ADD ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWstoreidx ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWstoreidx4 ptr idx val mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWstoreidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| val := v.Args[1] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVWstorezero [off] {sym} ptr mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off] {sym} ptr (MOVWreg x) mem) |
| // cond: |
| // result: (MOVWstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVWstore [off] {sym} ptr x mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = off |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [i] {s} ptr0 (SRLconst [32] w) x:(MOVWstore [i-4] {s} ptr1 w mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVDstore [i-4] {s} ptr0 w mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 32 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstore { |
| break |
| } |
| if x.AuxInt != i-4 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| if w != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = i - 4 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVDstoreidx ptr1 idx1 w mem) |
| for { |
| if v.AuxInt != 4 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 32 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstore_10(v *Value) bool { |
| b := v.Block |
| // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [32] w) x:(MOVWstoreidx4 ptr1 idx1 w mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVDstoreidx ptr1 (SLLconst <idx1.Type> [2] idx1) w mem) |
| for { |
| if v.AuxInt != 4 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| if v_1.AuxInt != 32 { |
| break |
| } |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstoreidx4 { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [i] {s} ptr0 (SRLconst [j] w) x:(MOVWstore [i-4] {s} ptr1 w0:(SRLconst [j-32] w) mem)) |
| // cond: x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVDstore [i-4] {s} ptr0 w0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[2] |
| ptr0 := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstore { |
| break |
| } |
| if x.AuxInt != i-4 { |
| break |
| } |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| w0 := x.Args[1] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-32 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstore) |
| v.AuxInt = i - 4 |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [4] {s} (ADD ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx ptr1 idx1 w0:(SRLconst [j-32] w) mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVDstoreidx ptr1 idx1 w0 mem) |
| for { |
| if v.AuxInt != 4 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-32 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstore [4] {s} (ADDshiftLL [2] ptr0 idx0) (SRLconst [j] w) x:(MOVWstoreidx4 ptr1 idx1 w0:(SRLconst [j-32] w) mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVDstoreidx ptr1 (SLLconst <idx1.Type> [2] idx1) w0 mem) |
| for { |
| if v.AuxInt != 4 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRLconst { |
| break |
| } |
| j := v_1.AuxInt |
| w := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstoreidx4 { |
| break |
| } |
| mem := x.Args[3] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| w0 := x.Args[2] |
| if w0.Op != OpARM64SRLconst { |
| break |
| } |
| if w0.AuxInt != j-32 { |
| break |
| } |
| if w != w0.Args[0] { |
| break |
| } |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(w0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstoreidx_0(v *Value) bool { |
| // match: (MOVWstoreidx ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVWstore [c] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx (MOVDconst [c]) idx val mem) |
| // cond: |
| // result: (MOVWstore [c] idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx ptr (SLLconst [2] idx) val mem) |
| // cond: |
| // result: (MOVWstoreidx4 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 2 { |
| break |
| } |
| idx := v_1.Args[0] |
| val := v.Args[2] |
| v.reset(OpARM64MOVWstoreidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx (SLLconst [2] idx) ptr val mem) |
| // cond: |
| // result: (MOVWstoreidx4 ptr idx val mem) |
| for { |
| mem := v.Args[3] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| val := v.Args[2] |
| v.reset(OpARM64MOVWstoreidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVWstorezeroidx ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx ptr idx (MOVWreg x) mem) |
| // cond: |
| // result: (MOVWstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx ptr idx (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVWstoreidx ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVWstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx ptr (ADDconst [4] idx) (SRLconst [32] w) x:(MOVWstoreidx ptr idx w mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVDstoreidx ptr idx w mem) |
| for { |
| _ = v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 4 { |
| break |
| } |
| idx := v_1.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64SRLconst { |
| break |
| } |
| if v_2.AuxInt != 32 { |
| break |
| } |
| w := v_2.Args[0] |
| x := v.Args[3] |
| if x.Op != OpARM64MOVWstoreidx { |
| break |
| } |
| mem := x.Args[3] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| if w != x.Args[2] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstoreidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(w) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstoreidx4_0(v *Value) bool { |
| // match: (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) |
| // cond: |
| // result: (MOVWstore [c<<2] ptr val mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| val := v.Args[2] |
| v.reset(OpARM64MOVWstore) |
| v.AuxInt = c << 2 |
| v.AddArg(ptr) |
| v.AddArg(val) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) |
| // cond: |
| // result: (MOVWstorezeroidx4 ptr idx mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx4 ptr idx (MOVWreg x) mem) |
| // cond: |
| // result: (MOVWstoreidx4 ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVWstoreidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) |
| // cond: |
| // result: (MOVWstoreidx4 ptr idx x mem) |
| for { |
| mem := v.Args[3] |
| ptr := v.Args[0] |
| idx := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_2.Args[0] |
| v.reset(OpARM64MOVWstoreidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(x) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstorezero_0(v *Value) bool { |
| b := v.Block |
| config := b.Func.Config |
| // match: (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) |
| // cond: is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWstorezero [off1+off2] {sym} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDconst { |
| break |
| } |
| off2 := v_0.AuxInt |
| ptr := v_0.Args[0] |
| if !(is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = sym |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) |
| // cond: canMergeSym(sym1,sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared) |
| // result: (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) |
| for { |
| off1 := v.AuxInt |
| sym1 := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDaddr { |
| break |
| } |
| off2 := v_0.AuxInt |
| sym2 := v_0.Aux |
| ptr := v_0.Args[0] |
| if !(canMergeSym(sym1, sym2) && is32Bit(off1+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_shared)) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = off1 + off2 |
| v.Aux = mergeSym(sym1, sym2) |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezero [off] {sym} (ADD ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWstorezeroidx ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) |
| // cond: off == 0 && sym == nil |
| // result: (MOVWstorezeroidx4 ptr idx mem) |
| for { |
| off := v.AuxInt |
| sym := v.Aux |
| mem := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[1] |
| ptr := v_0.Args[0] |
| if !(off == 0 && sym == nil) { |
| break |
| } |
| v.reset(OpARM64MOVWstorezeroidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezero [i] {s} ptr0 x:(MOVWstorezero [j] {s} ptr1 mem)) |
| // cond: x.Uses == 1 && areAdjacentOffsets(i,j,4) && is32Bit(min(i,j)) && isSamePtr(ptr0, ptr1) && clobber(x) |
| // result: (MOVDstorezero [min(i,j)] {s} ptr0 mem) |
| for { |
| i := v.AuxInt |
| s := v.Aux |
| _ = v.Args[1] |
| ptr0 := v.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVWstorezero { |
| break |
| } |
| j := x.AuxInt |
| if x.Aux != s { |
| break |
| } |
| mem := x.Args[1] |
| ptr1 := x.Args[0] |
| if !(x.Uses == 1 && areAdjacentOffsets(i, j, 4) && is32Bit(min(i, j)) && isSamePtr(ptr0, ptr1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezero) |
| v.AuxInt = min(i, j) |
| v.Aux = s |
| v.AddArg(ptr0) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezero [4] {s} (ADD ptr0 idx0) x:(MOVWstorezeroidx ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x) |
| // result: (MOVDstorezeroidx ptr1 idx1 mem) |
| for { |
| if v.AuxInt != 4 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADD { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVWstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx) |
| v.AddArg(ptr1) |
| v.AddArg(idx1) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezero [4] {s} (ADDshiftLL [2] ptr0 idx0) x:(MOVWstorezeroidx4 ptr1 idx1 mem)) |
| // cond: x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x) |
| // result: (MOVDstorezeroidx ptr1 (SLLconst <idx1.Type> [2] idx1) mem) |
| for { |
| if v.AuxInt != 4 { |
| break |
| } |
| s := v.Aux |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ADDshiftLL { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx0 := v_0.Args[1] |
| ptr0 := v_0.Args[0] |
| x := v.Args[1] |
| if x.Op != OpARM64MOVWstorezeroidx4 { |
| break |
| } |
| mem := x.Args[2] |
| ptr1 := x.Args[0] |
| idx1 := x.Args[1] |
| if !(x.Uses == 1 && s == nil && isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx) |
| v.AddArg(ptr1) |
| v0 := b.NewValue0(v.Pos, OpARM64SLLconst, idx1.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(idx1) |
| v.AddArg(v0) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstorezeroidx_0(v *Value) bool { |
| // match: (MOVWstorezeroidx ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVWstorezero [c] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = c |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezeroidx (MOVDconst [c]) idx mem) |
| // cond: |
| // result: (MOVWstorezero [c] idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| idx := v.Args[1] |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = c |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezeroidx ptr (SLLconst [2] idx) mem) |
| // cond: |
| // result: (MOVWstorezeroidx4 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLLconst { |
| break |
| } |
| if v_1.AuxInt != 2 { |
| break |
| } |
| idx := v_1.Args[0] |
| v.reset(OpARM64MOVWstorezeroidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezeroidx (SLLconst [2] idx) ptr mem) |
| // cond: |
| // result: (MOVWstorezeroidx4 ptr idx mem) |
| for { |
| mem := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLLconst { |
| break |
| } |
| if v_0.AuxInt != 2 { |
| break |
| } |
| idx := v_0.Args[0] |
| ptr := v.Args[1] |
| v.reset(OpARM64MOVWstorezeroidx4) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| // match: (MOVWstorezeroidx ptr (ADDconst [4] idx) x:(MOVWstorezeroidx ptr idx mem)) |
| // cond: x.Uses == 1 && clobber(x) |
| // result: (MOVDstorezeroidx ptr idx mem) |
| for { |
| _ = v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ADDconst { |
| break |
| } |
| if v_1.AuxInt != 4 { |
| break |
| } |
| idx := v_1.Args[0] |
| x := v.Args[2] |
| if x.Op != OpARM64MOVWstorezeroidx { |
| break |
| } |
| mem := x.Args[2] |
| if ptr != x.Args[0] { |
| break |
| } |
| if idx != x.Args[1] { |
| break |
| } |
| if !(x.Uses == 1 && clobber(x)) { |
| break |
| } |
| v.reset(OpARM64MOVDstorezeroidx) |
| v.AddArg(ptr) |
| v.AddArg(idx) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MOVWstorezeroidx4_0(v *Value) bool { |
| // match: (MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) |
| // cond: |
| // result: (MOVWstorezero [c<<2] ptr mem) |
| for { |
| mem := v.Args[2] |
| ptr := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVWstorezero) |
| v.AuxInt = c << 2 |
| v.AddArg(ptr) |
| v.AddArg(mem) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MSUB_0(v *Value) bool { |
| b := v.Block |
| // match: (MSUB a x (MOVDconst [-1])) |
| // cond: |
| // result: (ADD a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != -1 { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUB a _ (MOVDconst [0])) |
| // cond: |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 0 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [1])) |
| // cond: |
| // result: (SUB a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_2.AuxInt != 1 { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (SUBshiftLL a x [log2(c)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && c>=3 |
| // result: (SUB a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && c>=7 |
| // result: (ADD a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MSUB_10(v *Value) bool { |
| b := v.Block |
| // match: (MSUB a (MOVDconst [-1]) x) |
| // cond: |
| // result: (ADD a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != -1 { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [0]) _) |
| // cond: |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [1]) x) |
| // cond: |
| // result: (SUB a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (SUBshiftLL a x [log2(c)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && c>=3 |
| // result: (SUB a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && c>=7 |
| // result: (ADD a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MSUB_20(v *Value) bool { |
| b := v.Block |
| // match: (MSUB (MOVDconst [c]) x y) |
| // cond: |
| // result: (ADDconst [c] (MNEG <x.Type> x y)) |
| for { |
| y := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v.Args[1] |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64MNEG, x.Type) |
| v0.AddArg(x) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUB a (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (SUBconst [c*d] a) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_2.AuxInt |
| v.reset(OpARM64SUBconst) |
| v.AuxInt = c * d |
| v.AddArg(a) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MSUBW_0(v *Value) bool { |
| b := v.Block |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: int32(c)==-1 |
| // result: (ADD a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUBW a _ (MOVDconst [c])) |
| // cond: int32(c)==0 |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: int32(c)==1 |
| // result: (SUB a x) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (SUBshiftLL a x [log2(c)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && int32(c)>=3 |
| // result: (SUB a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && int32(c)>=7 |
| // result: (ADD a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| x := v.Args[1] |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_2.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MSUBW_10(v *Value) bool { |
| b := v.Block |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: int32(c)==-1 |
| // result: (ADD a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) _) |
| // cond: int32(c)==0 |
| // result: a |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = a.Type |
| v.AddArg(a) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: int32(c)==1 |
| // result: (SUB a x) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (SUBshiftLL a x [log2(c)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c) |
| v.AddArg(a) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && int32(c)>=3 |
| // result: (SUB a (ADDshiftLL <x.Type> x x [log2(c-1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64SUB) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = log2(c - 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && int32(c)>=7 |
| // result: (ADD a (SUBshiftLL <x.Type> x x [log2(c+1)])) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64ADD) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = log2(c + 1) |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log2(c/3)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 3) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log2(c/5)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 5) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log2(c/7)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c / 7) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64SUBshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log2(c/9)]) |
| for { |
| x := v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SUBshiftLL) |
| v.AuxInt = log2(c / 9) |
| v.AddArg(a) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MSUBW_20(v *Value) bool { |
| b := v.Block |
| // match: (MSUBW (MOVDconst [c]) x y) |
| // cond: |
| // result: (ADDconst [c] (MNEGW <x.Type> x y)) |
| for { |
| y := v.Args[2] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| x := v.Args[1] |
| v.reset(OpARM64ADDconst) |
| v.AuxInt = c |
| v0 := b.NewValue0(v.Pos, OpARM64MNEGW, x.Type) |
| v0.AddArg(x) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MSUBW a (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (SUBconst [int64(int32(c)*int32(d))] a) |
| for { |
| _ = v.Args[2] |
| a := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v_2 := v.Args[2] |
| if v_2.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_2.AuxInt |
| v.reset(OpARM64SUBconst) |
| v.AuxInt = int64(int32(c) * int32(d)) |
| v.AddArg(a) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MUL_0(v *Value) bool { |
| // match: (MUL (NEG x) y) |
| // cond: |
| // result: (MNEG x y) |
| for { |
| y := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64NEG { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64MNEG) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (MUL y (NEG x)) |
| // cond: |
| // result: (MNEG x y) |
| for { |
| _ = v.Args[1] |
| y := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64NEG { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MNEG) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (MUL x (MOVDconst [-1])) |
| // cond: |
| // result: (NEG x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != -1 { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL (MOVDconst [-1]) x) |
| // cond: |
| // result: (NEG x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != -1 { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL _ (MOVDconst [0])) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MUL (MOVDconst [0]) _) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != 0 { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MUL x (MOVDconst [1])) |
| // cond: |
| // result: x |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1.AuxInt != 1 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL (MOVDconst [1]) x) |
| // cond: |
| // result: x |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0.AuxInt != 1 { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (SLLconst [log2(c)] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (SLLconst [log2(c)] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MUL_10(v *Value) bool { |
| b := v.Block |
| // match: (MUL x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && c >= 3 |
| // result: (ADDshiftLL x x [log2(c-1)]) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c - 1) |
| v.AddArg(x) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && c >= 3 |
| // result: (ADDshiftLL x x [log2(c-1)]) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c-1) && c >= 3) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c - 1) |
| v.AddArg(x) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && c >= 7 |
| // result: (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)]) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c + 1) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && c >= 7 |
| // result: (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)]) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c+1) && c >= 7) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c + 1) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MUL x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) |
| // result: (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 5) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) |
| // result: (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 5) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) |
| // result: (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MUL_20(v *Value) bool { |
| b := v.Block |
| // match: (MUL x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 9) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) |
| // result: (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 9) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MUL (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [c*d]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c * d |
| return true |
| } |
| // match: (MUL (MOVDconst [d]) (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [c*d]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = c * d |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MULW_0(v *Value) bool { |
| // match: (MULW (NEG x) y) |
| // cond: |
| // result: (MNEGW x y) |
| for { |
| y := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64NEG { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64MNEGW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (MULW y (NEG x)) |
| // cond: |
| // result: (MNEGW x y) |
| for { |
| _ = v.Args[1] |
| y := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64NEG { |
| break |
| } |
| x := v_1.Args[0] |
| v.reset(OpARM64MNEGW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: int32(c)==-1 |
| // result: (NEG x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: int32(c)==-1 |
| // result: (NEG x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(int32(c) == -1) { |
| break |
| } |
| v.reset(OpARM64NEG) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW _ (MOVDconst [c])) |
| // cond: int32(c)==0 |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) _) |
| // cond: int32(c)==0 |
| // result: (MOVDconst [0]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(int32(c) == 0) { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: int32(c)==1 |
| // result: x |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: int32(c)==1 |
| // result: x |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(int32(c) == 1) { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c) |
| // result: (SLLconst [log2(c)] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c) |
| // result: (SLLconst [log2(c)] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MULW_10(v *Value) bool { |
| b := v.Block |
| // match: (MULW x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c-1) && int32(c) >= 3 |
| // result: (ADDshiftLL x x [log2(c-1)]) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c - 1) |
| v.AddArg(x) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c-1) && int32(c) >= 3 |
| // result: (ADDshiftLL x x [log2(c-1)]) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c-1) && int32(c) >= 3) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c - 1) |
| v.AddArg(x) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: isPowerOfTwo(c+1) && int32(c) >= 7 |
| // result: (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)]) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c + 1) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: isPowerOfTwo(c+1) && int32(c) >= 7 |
| // result: (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)]) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(isPowerOfTwo(c+1) && int32(c) >= 7) { |
| break |
| } |
| v.reset(OpARM64ADDshiftLL) |
| v.AuxInt = log2(c + 1) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| v.AddArg(x) |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) |
| // result: (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 3) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 1 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 5) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) |
| // result: (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 5) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 2 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW x (MOVDconst [c])) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) |
| // result: (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 7) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v1 := b.NewValue0(v.Pos, OpARM64NEG, x.Type) |
| v1.AddArg(x) |
| v0.AddArg(v1) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MULW_20(v *Value) bool { |
| b := v.Block |
| // match: (MULW x (MOVDconst [c])) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 9) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) x) |
| // cond: c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) |
| // result: (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3])) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| if !(c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c)) { |
| break |
| } |
| v.reset(OpARM64SLLconst) |
| v.AuxInt = log2(c / 9) |
| v0 := b.NewValue0(v.Pos, OpARM64ADDshiftLL, x.Type) |
| v0.AuxInt = 3 |
| v0.AddArg(x) |
| v0.AddArg(x) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (MULW (MOVDconst [c]) (MOVDconst [d])) |
| // cond: |
| // result: (MOVDconst [int64(int32(c)*int32(d))]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int32(c) * int32(d)) |
| return true |
| } |
| // match: (MULW (MOVDconst [d]) (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [int64(int32(c)*int32(d))]) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| d := v_0.AuxInt |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = int64(int32(c) * int32(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MVN_0(v *Value) bool { |
| // match: (MVN (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [^c]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = ^c |
| return true |
| } |
| // match: (MVN x:(SLLconst [c] y)) |
| // cond: clobberIfDead(x) |
| // result: (MVNshiftLL [c] y) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64SLLconst { |
| break |
| } |
| c := x.AuxInt |
| y := x.Args[0] |
| if !(clobberIfDead(x)) { |
| break |
| } |
| v.reset(OpARM64MVNshiftLL) |
| v.AuxInt = c |
| v.AddArg(y) |
| return true |
| } |
| // match: (MVN x:(SRLconst [c] y)) |
| // cond: clobberIfDead(x) |
| // result: (MVNshiftRL [c] y) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64SRLconst { |
| break |
| } |
| c := x.AuxInt |
| y := x.Args[0] |
| if !(clobberIfDead(x)) { |
| break |
| } |
| v.reset(OpARM64MVNshiftRL) |
| v.AuxInt = c |
| v.AddArg(y) |
| return true |
| } |
| // match: (MVN x:(SRAconst [c] y)) |
| // cond: clobberIfDead(x) |
| // result: (MVNshiftRA [c] y) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64SRAconst { |
| break |
| } |
| c := x.AuxInt |
| y := x.Args[0] |
| if !(clobberIfDead(x)) { |
| break |
| } |
| v.reset(OpARM64MVNshiftRA) |
| v.AuxInt = c |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MVNshiftLL_0(v *Value) bool { |
| // match: (MVNshiftLL (MOVDconst [c]) [d]) |
| // cond: |
| // result: (MOVDconst [^int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = ^int64(uint64(c) << uint64(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MVNshiftRA_0(v *Value) bool { |
| // match: (MVNshiftRA (MOVDconst [c]) [d]) |
| // cond: |
| // result: (MOVDconst [^(c>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = ^(c >> uint64(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64MVNshiftRL_0(v *Value) bool { |
| // match: (MVNshiftRL (MOVDconst [c]) [d]) |
| // cond: |
| // result: (MOVDconst [^int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = ^int64(uint64(c) >> uint64(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64NEG_0(v *Value) bool { |
| // match: (NEG (MUL x y)) |
| // cond: |
| // result: (MNEG x y) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MUL { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64MNEG) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (NEG (MULW x y)) |
| // cond: |
| // result: (MNEGW x y) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MULW { |
| break |
| } |
| y := v_0.Args[1] |
| x := v_0.Args[0] |
| v.reset(OpARM64MNEGW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (NEG (MOVDconst [c])) |
| // cond: |
| // result: (MOVDconst [-c]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -c |
| return true |
| } |
| // match: (NEG x:(SLLconst [c] y)) |
| // cond: clobberIfDead(x) |
| // result: (NEGshiftLL [c] y) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64SLLconst { |
| break |
| } |
| c := x.AuxInt |
| y := x.Args[0] |
| if !(clobberIfDead(x)) { |
| break |
| } |
| v.reset(OpARM64NEGshiftLL) |
| v.AuxInt = c |
| v.AddArg(y) |
| return true |
| } |
| // match: (NEG x:(SRLconst [c] y)) |
| // cond: clobberIfDead(x) |
| // result: (NEGshiftRL [c] y) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64SRLconst { |
| break |
| } |
| c := x.AuxInt |
| y := x.Args[0] |
| if !(clobberIfDead(x)) { |
| break |
| } |
| v.reset(OpARM64NEGshiftRL) |
| v.AuxInt = c |
| v.AddArg(y) |
| return true |
| } |
| // match: (NEG x:(SRAconst [c] y)) |
| // cond: clobberIfDead(x) |
| // result: (NEGshiftRA [c] y) |
| for { |
| x := v.Args[0] |
| if x.Op != OpARM64SRAconst { |
| break |
| } |
| c := x.AuxInt |
| y := x.Args[0] |
| if !(clobberIfDead(x)) { |
| break |
| } |
| v.reset(OpARM64NEGshiftRA) |
| v.AuxInt = c |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64NEGshiftLL_0(v *Value) bool { |
| // match: (NEGshiftLL (MOVDconst [c]) [d]) |
| // cond: |
| // result: (MOVDconst [-int64(uint64(c)<<uint64(d))]) |
| for { |
| d := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -int64(uint64(c) << uint64(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64NEGshiftRA_0(v *Value) bool { |
| // match: (NEGshiftRA (MOVDconst [c]) [d]) |
| // cond: |
| // result: (MOVDconst [-(c>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -(c >> uint64(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64NEGshiftRL_0(v *Value) bool { |
| // match: (NEGshiftRL (MOVDconst [c]) [d]) |
| // cond: |
| // result: (MOVDconst [-int64(uint64(c)>>uint64(d))]) |
| for { |
| d := v.AuxInt |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = -int64(uint64(c) >> uint64(d)) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64NotEqual_0(v *Value) bool { |
| // match: (NotEqual (FlagEQ)) |
| // cond: |
| // result: (MOVDconst [0]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagEQ { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 0 |
| return true |
| } |
| // match: (NotEqual (FlagLT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (NotEqual (FlagLT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagLT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (NotEqual (FlagGT_ULT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_ULT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (NotEqual (FlagGT_UGT)) |
| // cond: |
| // result: (MOVDconst [1]) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64FlagGT_UGT { |
| break |
| } |
| v.reset(OpARM64MOVDconst) |
| v.AuxInt = 1 |
| return true |
| } |
| // match: (NotEqual (InvertFlags x)) |
| // cond: |
| // result: (NotEqual x) |
| for { |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64InvertFlags { |
| break |
| } |
| x := v_0.Args[0] |
| v.reset(OpARM64NotEqual) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64OR_0(v *Value) bool { |
| // match: (OR x (MOVDconst [c])) |
| // cond: |
| // result: (ORconst [c] x) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_1.AuxInt |
| v.reset(OpARM64ORconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (OR (MOVDconst [c]) x) |
| // cond: |
| // result: (ORconst [c] x) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MOVDconst { |
| break |
| } |
| c := v_0.AuxInt |
| v.reset(OpARM64ORconst) |
| v.AuxInt = c |
| v.AddArg(x) |
| return true |
| } |
| // match: (OR x x) |
| // cond: |
| // result: x |
| for { |
| x := v.Args[1] |
| if x != v.Args[0] { |
| break |
| } |
| v.reset(OpCopy) |
| v.Type = x.Type |
| v.AddArg(x) |
| return true |
| } |
| // match: (OR x (MVN y)) |
| // cond: |
| // result: (ORN x y) |
| for { |
| _ = v.Args[1] |
| x := v.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64MVN { |
| break |
| } |
| y := v_1.Args[0] |
| v.reset(OpARM64ORN) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR (MVN y) x) |
| // cond: |
| // result: (ORN x y) |
| for { |
| x := v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64MVN { |
| break |
| } |
| y := v_0.Args[0] |
| v.reset(OpARM64ORN) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR x0 x1:(SLLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ORshiftLL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ORshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR x1:(SLLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ORshiftLL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SLLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ORshiftLL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR x0 x1:(SRLconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ORshiftRL x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ORshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR x1:(SRLconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ORshiftRL x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRLconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ORshiftRL) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR x0 x1:(SRAconst [c] y)) |
| // cond: clobberIfDead(x1) |
| // result: (ORshiftRA x0 y [c]) |
| for { |
| _ = v.Args[1] |
| x0 := v.Args[0] |
| x1 := v.Args[1] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ORshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64OR_10(v *Value) bool { |
| b := v.Block |
| typ := &b.Func.Config.Types |
| // match: (OR x1:(SRAconst [c] y) x0) |
| // cond: clobberIfDead(x1) |
| // result: (ORshiftRA x0 y [c]) |
| for { |
| x0 := v.Args[1] |
| x1 := v.Args[0] |
| if x1.Op != OpARM64SRAconst { |
| break |
| } |
| c := x1.AuxInt |
| y := x1.Args[0] |
| if !(clobberIfDead(x1)) { |
| break |
| } |
| v.reset(OpARM64ORshiftRA) |
| v.AuxInt = c |
| v.AddArg(x0) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR (SLL x (ANDconst <t> [63] y)) (CSEL0 <typ.UInt64> {cc} (SRL <typ.UInt64> x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0.Args[1] |
| x := v_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt64 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SRL { |
| break |
| } |
| if v_1_0.Type != typ.UInt64 { |
| break |
| } |
| _ = v_1_0.Args[1] |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (OR (CSEL0 <typ.UInt64> {cc} (SRL <typ.UInt64> x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))) (SLL x (ANDconst <t> [63] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt64 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0_0.Type != typ.UInt64 { |
| break |
| } |
| _ = v_0_0.Args[1] |
| x := v_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1.Args[1] |
| if x != v_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (OR (SRL <typ.UInt64> x (ANDconst <t> [63] y)) (CSEL0 <typ.UInt64> {cc} (SLL x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0.Type != typ.UInt64 { |
| break |
| } |
| _ = v_0.Args[1] |
| x := v_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt64 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1_0.Args[1] |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR (CSEL0 <typ.UInt64> {cc} (SLL x (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y))) (CMPconst [64] (SUB <t> (MOVDconst [64]) (ANDconst <t> [63] y)))) (SRL <typ.UInt64> x (ANDconst <t> [63] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (ROR x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt64 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0_0.Args[1] |
| x := v_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 64 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 63 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 64 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 63 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRL { |
| break |
| } |
| if v_1.Type != typ.UInt64 { |
| break |
| } |
| _ = v_1.Args[1] |
| if x != v_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 63 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64ROR) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR (SLL x (ANDconst <t> [31] y)) (CSEL0 <typ.UInt32> {cc} (SRL <typ.UInt32> (MOVWUreg x) (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0.Args[1] |
| x := v_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt32 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SRL { |
| break |
| } |
| if v_1_0.Type != typ.UInt32 { |
| break |
| } |
| _ = v_1_0.Args[1] |
| v_1_0_0 := v_1_0.Args[0] |
| if v_1_0_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| if x != v_1_0_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (OR (CSEL0 <typ.UInt32> {cc} (SRL <typ.UInt32> (MOVWUreg x) (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))) (SLL x (ANDconst <t> [31] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x (NEG <t> y)) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt32 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0_0.Type != typ.UInt32 { |
| break |
| } |
| _ = v_0_0.Args[1] |
| v_0_0_0 := v_0_0.Args[0] |
| if v_0_0_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_0_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1.Args[1] |
| if x != v_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v0 := b.NewValue0(v.Pos, OpARM64NEG, t) |
| v0.AddArg(y) |
| v.AddArg(v0) |
| return true |
| } |
| // match: (OR (SRL <typ.UInt32> (MOVWUreg x) (ANDconst <t> [31] y)) (CSEL0 <typ.UInt32> {cc} (SLL x (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64SRL { |
| break |
| } |
| if v_0.Type != typ.UInt32 { |
| break |
| } |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| x := v_0_0.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| t := v_0_1.Type |
| if v_0_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_1.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_1.Type != typ.UInt32 { |
| break |
| } |
| cc := v_1.Aux |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_1_0.Args[1] |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_0_1 := v_1_0.Args[1] |
| if v_1_0_1.Op != OpARM64SUB { |
| break |
| } |
| if v_1_0_1.Type != t { |
| break |
| } |
| _ = v_1_0_1.Args[1] |
| v_1_0_1_0 := v_1_0_1.Args[0] |
| if v_1_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_1_0_1_1 := v_1_0_1.Args[1] |
| if v_1_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_0_1_1.Type != t { |
| break |
| } |
| if v_1_0_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_0_1_1.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_1_1.AuxInt != 64 { |
| break |
| } |
| v_1_1_0 := v_1_1.Args[0] |
| if v_1_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_1_1_0.Type != t { |
| break |
| } |
| _ = v_1_1_0.Args[1] |
| v_1_1_0_0 := v_1_1_0.Args[0] |
| if v_1_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_1_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_1_1_0_1 := v_1_1_0.Args[1] |
| if v_1_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1_0_1.Type != t { |
| break |
| } |
| if v_1_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1_0_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR (CSEL0 <typ.UInt32> {cc} (SLL x (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y))) (CMPconst [64] (SUB <t> (MOVDconst [32]) (ANDconst <t> [31] y)))) (SRL <typ.UInt32> (MOVWUreg x) (ANDconst <t> [31] y))) |
| // cond: cc.(Op) == OpARM64LessThanU |
| // result: (RORW x y) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64CSEL0 { |
| break |
| } |
| if v_0.Type != typ.UInt32 { |
| break |
| } |
| cc := v_0.Aux |
| _ = v_0.Args[1] |
| v_0_0 := v_0.Args[0] |
| if v_0_0.Op != OpARM64SLL { |
| break |
| } |
| _ = v_0_0.Args[1] |
| x := v_0_0.Args[0] |
| v_0_0_1 := v_0_0.Args[1] |
| if v_0_0_1.Op != OpARM64SUB { |
| break |
| } |
| t := v_0_0_1.Type |
| _ = v_0_0_1.Args[1] |
| v_0_0_1_0 := v_0_0_1.Args[0] |
| if v_0_0_1_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_0_1_0.AuxInt != 32 { |
| break |
| } |
| v_0_0_1_1 := v_0_0_1.Args[1] |
| if v_0_0_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_0_1_1.Type != t { |
| break |
| } |
| if v_0_0_1_1.AuxInt != 31 { |
| break |
| } |
| y := v_0_0_1_1.Args[0] |
| v_0_1 := v_0.Args[1] |
| if v_0_1.Op != OpARM64CMPconst { |
| break |
| } |
| if v_0_1.AuxInt != 64 { |
| break |
| } |
| v_0_1_0 := v_0_1.Args[0] |
| if v_0_1_0.Op != OpARM64SUB { |
| break |
| } |
| if v_0_1_0.Type != t { |
| break |
| } |
| _ = v_0_1_0.Args[1] |
| v_0_1_0_0 := v_0_1_0.Args[0] |
| if v_0_1_0_0.Op != OpARM64MOVDconst { |
| break |
| } |
| if v_0_1_0_0.AuxInt != 32 { |
| break |
| } |
| v_0_1_0_1 := v_0_1_0.Args[1] |
| if v_0_1_0_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_0_1_0_1.Type != t { |
| break |
| } |
| if v_0_1_0_1.AuxInt != 31 { |
| break |
| } |
| if y != v_0_1_0_1.Args[0] { |
| break |
| } |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64SRL { |
| break |
| } |
| if v_1.Type != typ.UInt32 { |
| break |
| } |
| _ = v_1.Args[1] |
| v_1_0 := v_1.Args[0] |
| if v_1_0.Op != OpARM64MOVWUreg { |
| break |
| } |
| if x != v_1_0.Args[0] { |
| break |
| } |
| v_1_1 := v_1.Args[1] |
| if v_1_1.Op != OpARM64ANDconst { |
| break |
| } |
| if v_1_1.Type != t { |
| break |
| } |
| if v_1_1.AuxInt != 31 { |
| break |
| } |
| if y != v_1_1.Args[0] { |
| break |
| } |
| if !(cc.(Op) == OpARM64LessThanU) { |
| break |
| } |
| v.reset(OpARM64RORW) |
| v.AddArg(x) |
| v.AddArg(y) |
| return true |
| } |
| // match: (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) |
| // cond: ac == ^((1<<uint(getARM64BFwidth(bfc))-1) << uint(getARM64BFlsb(bfc))) |
| // result: (BFI [bfc] y x) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64UBFIZ { |
| break |
| } |
| bfc := v_0.AuxInt |
| x := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ANDconst { |
| break |
| } |
| ac := v_1.AuxInt |
| y := v_1.Args[0] |
| if !(ac == ^((1<<uint(getARM64BFwidth(bfc)) - 1) << uint(getARM64BFlsb(bfc)))) { |
| break |
| } |
| v.reset(OpARM64BFI) |
| v.AuxInt = bfc |
| v.AddArg(y) |
| v.AddArg(x) |
| return true |
| } |
| return false |
| } |
| func rewriteValueARM64_OpARM64OR_20(v *Value) bool { |
| b := v.Block |
| // match: (OR (ANDconst [ac] y) (UBFIZ [bfc] x)) |
| // cond: ac == ^((1<<uint(getARM64BFwidth(bfc))-1) << uint(getARM64BFlsb(bfc))) |
| // result: (BFI [bfc] y x) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| ac := v_0.AuxInt |
| y := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFIZ { |
| break |
| } |
| bfc := v_1.AuxInt |
| x := v_1.Args[0] |
| if !(ac == ^((1<<uint(getARM64BFwidth(bfc)) - 1) << uint(getARM64BFlsb(bfc)))) { |
| break |
| } |
| v.reset(OpARM64BFI) |
| v.AuxInt = bfc |
| v.AddArg(y) |
| v.AddArg(x) |
| return true |
| } |
| // match: (OR (UBFX [bfc] x) (ANDconst [ac] y)) |
| // cond: ac == ^(1<<uint(getARM64BFwidth(bfc))-1) |
| // result: (BFXIL [bfc] y x) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64UBFX { |
| break |
| } |
| bfc := v_0.AuxInt |
| x := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64ANDconst { |
| break |
| } |
| ac := v_1.AuxInt |
| y := v_1.Args[0] |
| if !(ac == ^(1<<uint(getARM64BFwidth(bfc)) - 1)) { |
| break |
| } |
| v.reset(OpARM64BFXIL) |
| v.AuxInt = bfc |
| v.AddArg(y) |
| v.AddArg(x) |
| return true |
| } |
| // match: (OR (ANDconst [ac] y) (UBFX [bfc] x)) |
| // cond: ac == ^(1<<uint(getARM64BFwidth(bfc))-1) |
| // result: (BFXIL [bfc] y x) |
| for { |
| _ = v.Args[1] |
| v_0 := v.Args[0] |
| if v_0.Op != OpARM64ANDconst { |
| break |
| } |
| ac := v_0.AuxInt |
| y := v_0.Args[0] |
| v_1 := v.Args[1] |
| if v_1.Op != OpARM64UBFX { |
| break |
| } |
| bfc := v_1.AuxInt |
| x := v_1.Args[0] |
| if !(ac == ^(1<<uint(getARM64BFwidth(bfc)) - 1)) { |
| break |
| } |
| v.reset(OpARM64BFXIL) |
| v.AuxInt = bfc |
| v.AddArg(y) |
| v.AddArg(x) |
| return true |
| } |
| // match: (OR <t> o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i1] {s} p mem))) y3:(MOVDnop x3:(MOVBUload [i0] {s} p mem))) |
| // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0) |
| // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUload <t> {s} (OffPtr <p.Type> [i0] p) mem) |
| for { |
| t := v.Type |
| _ = v.Args[1] |
| o0 := v.Args[0] |
| if o0.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o0.AuxInt != 8 { |
| break |
| } |
| _ = o0.Args[1] |
| o1 := o0.Args[0] |
| if o1.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o1.AuxInt != 16 { |
| break |
| } |
| _ = o1.Args[1] |
| s0 := o1.Args[0] |
| if s0.Op != OpARM64SLLconst { |
| break |
| } |
| if s0.AuxInt != 24 { |
| break |
| } |
| y0 := s0.Args[0] |
| if y0.Op != OpARM64MOVDnop { |
| break |
| } |
| x0 := y0.Args[0] |
| if x0.Op != OpARM64MOVBUload { |
| break |
| } |
| i3 := x0.AuxInt |
| s := x0.Aux |
| mem := x0.Args[1] |
| p := x0.Args[0] |
| y1 := o1.Args[1] |
| if y1.Op != OpARM64MOVDnop { |
| break |
| } |
| x1 := y1.Args[0] |
| if x1.Op != OpARM64MOVBUload { |
| break |
| } |
| i2 := x1.AuxInt |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[1] |
| if p != x1.Args[0] { |
| break |
| } |
| if mem != x1.Args[1] { |
| break |
| } |
| y2 := o0.Args[1] |
| if y2.Op != OpARM64MOVDnop { |
| break |
| } |
| x2 := y2.Args[0] |
| if x2.Op != OpARM64MOVBUload { |
| break |
| } |
| i1 := x2.AuxInt |
| if x2.Aux != s { |
| break |
| } |
| _ = x2.Args[1] |
| if p != x2.Args[0] { |
| break |
| } |
| if mem != x2.Args[1] { |
| break |
| } |
| y3 := v.Args[1] |
| if y3.Op != OpARM64MOVDnop { |
| break |
| } |
| x3 := y3.Args[0] |
| if x3.Op != OpARM64MOVBUload { |
| break |
| } |
| i0 := x3.AuxInt |
| if x3.Aux != s { |
| break |
| } |
| _ = x3.Args[1] |
| if p != x3.Args[0] { |
| break |
| } |
| if mem != x3.Args[1] { |
| break |
| } |
| if !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0)) { |
| break |
| } |
| b = mergePoint(b, x0, x1, x2, x3) |
| v0 := b.NewValue0(x3.Pos, OpARM64MOVWUload, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.Aux = s |
| v1 := b.NewValue0(x3.Pos, OpOffPtr, p.Type) |
| v1.AuxInt = i0 |
| v1.AddArg(p) |
| v0.AddArg(v1) |
| v0.AddArg(mem) |
| return true |
| } |
| // match: (OR <t> y3:(MOVDnop x3:(MOVBUload [i0] {s} p mem)) o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [i3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [i2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [i1] {s} p mem)))) |
| // cond: i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0) |
| // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUload <t> {s} (OffPtr <p.Type> [i0] p) mem) |
| for { |
| t := v.Type |
| _ = v.Args[1] |
| y3 := v.Args[0] |
| if y3.Op != OpARM64MOVDnop { |
| break |
| } |
| x3 := y3.Args[0] |
| if x3.Op != OpARM64MOVBUload { |
| break |
| } |
| i0 := x3.AuxInt |
| s := x3.Aux |
| mem := x3.Args[1] |
| p := x3.Args[0] |
| o0 := v.Args[1] |
| if o0.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o0.AuxInt != 8 { |
| break |
| } |
| _ = o0.Args[1] |
| o1 := o0.Args[0] |
| if o1.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o1.AuxInt != 16 { |
| break |
| } |
| _ = o1.Args[1] |
| s0 := o1.Args[0] |
| if s0.Op != OpARM64SLLconst { |
| break |
| } |
| if s0.AuxInt != 24 { |
| break |
| } |
| y0 := s0.Args[0] |
| if y0.Op != OpARM64MOVDnop { |
| break |
| } |
| x0 := y0.Args[0] |
| if x0.Op != OpARM64MOVBUload { |
| break |
| } |
| i3 := x0.AuxInt |
| if x0.Aux != s { |
| break |
| } |
| _ = x0.Args[1] |
| if p != x0.Args[0] { |
| break |
| } |
| if mem != x0.Args[1] { |
| break |
| } |
| y1 := o1.Args[1] |
| if y1.Op != OpARM64MOVDnop { |
| break |
| } |
| x1 := y1.Args[0] |
| if x1.Op != OpARM64MOVBUload { |
| break |
| } |
| i2 := x1.AuxInt |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[1] |
| if p != x1.Args[0] { |
| break |
| } |
| if mem != x1.Args[1] { |
| break |
| } |
| y2 := o0.Args[1] |
| if y2.Op != OpARM64MOVDnop { |
| break |
| } |
| x2 := y2.Args[0] |
| if x2.Op != OpARM64MOVBUload { |
| break |
| } |
| i1 := x2.AuxInt |
| if x2.Aux != s { |
| break |
| } |
| _ = x2.Args[1] |
| if p != x2.Args[0] { |
| break |
| } |
| if mem != x2.Args[1] { |
| break |
| } |
| if !(i1 == i0+1 && i2 == i0+2 && i3 == i0+3 && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0)) { |
| break |
| } |
| b = mergePoint(b, x0, x1, x2, x3) |
| v0 := b.NewValue0(x2.Pos, OpARM64MOVWUload, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.Aux = s |
| v1 := b.NewValue0(x2.Pos, OpOffPtr, p.Type) |
| v1.AuxInt = i0 |
| v1.AddArg(p) |
| v0.AddArg(v1) |
| v0.AddArg(mem) |
| return true |
| } |
| // match: (OR <t> o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr0 idx0 mem))) |
| // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0) |
| // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx <t> ptr0 idx0 mem) |
| for { |
| t := v.Type |
| _ = v.Args[1] |
| o0 := v.Args[0] |
| if o0.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o0.AuxInt != 8 { |
| break |
| } |
| _ = o0.Args[1] |
| o1 := o0.Args[0] |
| if o1.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o1.AuxInt != 16 { |
| break |
| } |
| _ = o1.Args[1] |
| s0 := o1.Args[0] |
| if s0.Op != OpARM64SLLconst { |
| break |
| } |
| if s0.AuxInt != 24 { |
| break |
| } |
| y0 := s0.Args[0] |
| if y0.Op != OpARM64MOVDnop { |
| break |
| } |
| x0 := y0.Args[0] |
| if x0.Op != OpARM64MOVBUload { |
| break |
| } |
| if x0.AuxInt != 3 { |
| break |
| } |
| s := x0.Aux |
| mem := x0.Args[1] |
| p := x0.Args[0] |
| y1 := o1.Args[1] |
| if y1.Op != OpARM64MOVDnop { |
| break |
| } |
| x1 := y1.Args[0] |
| if x1.Op != OpARM64MOVBUload { |
| break |
| } |
| if x1.AuxInt != 2 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[1] |
| if p != x1.Args[0] { |
| break |
| } |
| if mem != x1.Args[1] { |
| break |
| } |
| y2 := o0.Args[1] |
| if y2.Op != OpARM64MOVDnop { |
| break |
| } |
| x2 := y2.Args[0] |
| if x2.Op != OpARM64MOVBUload { |
| break |
| } |
| if x2.AuxInt != 1 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| _ = x2.Args[1] |
| p1 := x2.Args[0] |
| if p1.Op != OpARM64ADD { |
| break |
| } |
| idx1 := p1.Args[1] |
| ptr1 := p1.Args[0] |
| if mem != x2.Args[1] { |
| break |
| } |
| y3 := v.Args[1] |
| if y3.Op != OpARM64MOVDnop { |
| break |
| } |
| x3 := y3.Args[0] |
| if x3.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x3.Args[2] |
| ptr0 := x3.Args[0] |
| idx0 := x3.Args[1] |
| if mem != x3.Args[2] { |
| break |
| } |
| if !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0)) { |
| break |
| } |
| b = mergePoint(b, x0, x1, x2, x3) |
| v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.AddArg(ptr0) |
| v0.AddArg(idx0) |
| v0.AddArg(mem) |
| return true |
| } |
| // match: (OR <t> y3:(MOVDnop x3:(MOVBUloadidx ptr0 idx0 mem)) o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUload [3] {s} p mem))) y1:(MOVDnop x1:(MOVBUload [2] {s} p mem))) y2:(MOVDnop x2:(MOVBUload [1] {s} p1:(ADD ptr1 idx1) mem)))) |
| // cond: s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0) |
| // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx <t> ptr0 idx0 mem) |
| for { |
| t := v.Type |
| _ = v.Args[1] |
| y3 := v.Args[0] |
| if y3.Op != OpARM64MOVDnop { |
| break |
| } |
| x3 := y3.Args[0] |
| if x3.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| mem := x3.Args[2] |
| ptr0 := x3.Args[0] |
| idx0 := x3.Args[1] |
| o0 := v.Args[1] |
| if o0.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o0.AuxInt != 8 { |
| break |
| } |
| _ = o0.Args[1] |
| o1 := o0.Args[0] |
| if o1.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o1.AuxInt != 16 { |
| break |
| } |
| _ = o1.Args[1] |
| s0 := o1.Args[0] |
| if s0.Op != OpARM64SLLconst { |
| break |
| } |
| if s0.AuxInt != 24 { |
| break |
| } |
| y0 := s0.Args[0] |
| if y0.Op != OpARM64MOVDnop { |
| break |
| } |
| x0 := y0.Args[0] |
| if x0.Op != OpARM64MOVBUload { |
| break |
| } |
| if x0.AuxInt != 3 { |
| break |
| } |
| s := x0.Aux |
| _ = x0.Args[1] |
| p := x0.Args[0] |
| if mem != x0.Args[1] { |
| break |
| } |
| y1 := o1.Args[1] |
| if y1.Op != OpARM64MOVDnop { |
| break |
| } |
| x1 := y1.Args[0] |
| if x1.Op != OpARM64MOVBUload { |
| break |
| } |
| if x1.AuxInt != 2 { |
| break |
| } |
| if x1.Aux != s { |
| break |
| } |
| _ = x1.Args[1] |
| if p != x1.Args[0] { |
| break |
| } |
| if mem != x1.Args[1] { |
| break |
| } |
| y2 := o0.Args[1] |
| if y2.Op != OpARM64MOVDnop { |
| break |
| } |
| x2 := y2.Args[0] |
| if x2.Op != OpARM64MOVBUload { |
| break |
| } |
| if x2.AuxInt != 1 { |
| break |
| } |
| if x2.Aux != s { |
| break |
| } |
| _ = x2.Args[1] |
| p1 := x2.Args[0] |
| if p1.Op != OpARM64ADD { |
| break |
| } |
| idx1 := p1.Args[1] |
| ptr1 := p1.Args[0] |
| if mem != x2.Args[1] { |
| break |
| } |
| if !(s == nil && x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && (isSamePtr(ptr0, ptr1) && isSamePtr(idx0, idx1) || isSamePtr(ptr0, idx1) && isSamePtr(idx0, ptr1)) && isSamePtr(p1, p) && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0)) { |
| break |
| } |
| b = mergePoint(b, x0, x1, x2, x3) |
| v0 := b.NewValue0(x2.Pos, OpARM64MOVWUloadidx, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.AddArg(ptr0) |
| v0.AddArg(idx0) |
| v0.AddArg(mem) |
| return true |
| } |
| // match: (OR <t> o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [1] idx) mem))) y3:(MOVDnop x3:(MOVBUloadidx ptr idx mem))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0) |
| // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx <t> ptr idx mem) |
| for { |
| t := v.Type |
| _ = v.Args[1] |
| o0 := v.Args[0] |
| if o0.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o0.AuxInt != 8 { |
| break |
| } |
| _ = o0.Args[1] |
| o1 := o0.Args[0] |
| if o1.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o1.AuxInt != 16 { |
| break |
| } |
| _ = o1.Args[1] |
| s0 := o1.Args[0] |
| if s0.Op != OpARM64SLLconst { |
| break |
| } |
| if s0.AuxInt != 24 { |
| break |
| } |
| y0 := s0.Args[0] |
| if y0.Op != OpARM64MOVDnop { |
| break |
| } |
| x0 := y0.Args[0] |
| if x0.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| mem := x0.Args[2] |
| ptr := x0.Args[0] |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x0_1.AuxInt != 3 { |
| break |
| } |
| idx := x0_1.Args[0] |
| y1 := o1.Args[1] |
| if y1.Op != OpARM64MOVDnop { |
| break |
| } |
| x1 := y1.Args[0] |
| if x1.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x1.Args[2] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x1_1.AuxInt != 2 { |
| break |
| } |
| if idx != x1_1.Args[0] { |
| break |
| } |
| if mem != x1.Args[2] { |
| break |
| } |
| y2 := o0.Args[1] |
| if y2.Op != OpARM64MOVDnop { |
| break |
| } |
| x2 := y2.Args[0] |
| if x2.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x2.Args[2] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x2_1.AuxInt != 1 { |
| break |
| } |
| if idx != x2_1.Args[0] { |
| break |
| } |
| if mem != x2.Args[2] { |
| break |
| } |
| y3 := v.Args[1] |
| if y3.Op != OpARM64MOVDnop { |
| break |
| } |
| x3 := y3.Args[0] |
| if x3.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x3.Args[2] |
| if ptr != x3.Args[0] { |
| break |
| } |
| if idx != x3.Args[1] { |
| break |
| } |
| if mem != x3.Args[2] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0)) { |
| break |
| } |
| b = mergePoint(b, x0, x1, x2, x3) |
| v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.AddArg(ptr) |
| v0.AddArg(idx) |
| v0.AddArg(mem) |
| return true |
| } |
| // match: (OR <t> y3:(MOVDnop x3:(MOVBUloadidx ptr idx mem)) o0:(ORshiftLL [8] o1:(ORshiftLL [16] s0:(SLLconst [24] y0:(MOVDnop x0:(MOVBUloadidx ptr (ADDconst [3] idx) mem))) y1:(MOVDnop x1:(MOVBUloadidx ptr (ADDconst [2] idx) mem))) y2:(MOVDnop x2:(MOVBUloadidx ptr (ADDconst [1] idx) mem)))) |
| // cond: x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b,x0,x1,x2,x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0) |
| // result: @mergePoint(b,x0,x1,x2,x3) (MOVWUloadidx <t> ptr idx mem) |
| for { |
| t := v.Type |
| _ = v.Args[1] |
| y3 := v.Args[0] |
| if y3.Op != OpARM64MOVDnop { |
| break |
| } |
| x3 := y3.Args[0] |
| if x3.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| mem := x3.Args[2] |
| ptr := x3.Args[0] |
| idx := x3.Args[1] |
| o0 := v.Args[1] |
| if o0.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o0.AuxInt != 8 { |
| break |
| } |
| _ = o0.Args[1] |
| o1 := o0.Args[0] |
| if o1.Op != OpARM64ORshiftLL { |
| break |
| } |
| if o1.AuxInt != 16 { |
| break |
| } |
| _ = o1.Args[1] |
| s0 := o1.Args[0] |
| if s0.Op != OpARM64SLLconst { |
| break |
| } |
| if s0.AuxInt != 24 { |
| break |
| } |
| y0 := s0.Args[0] |
| if y0.Op != OpARM64MOVDnop { |
| break |
| } |
| x0 := y0.Args[0] |
| if x0.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x0.Args[2] |
| if ptr != x0.Args[0] { |
| break |
| } |
| x0_1 := x0.Args[1] |
| if x0_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x0_1.AuxInt != 3 { |
| break |
| } |
| if idx != x0_1.Args[0] { |
| break |
| } |
| if mem != x0.Args[2] { |
| break |
| } |
| y1 := o1.Args[1] |
| if y1.Op != OpARM64MOVDnop { |
| break |
| } |
| x1 := y1.Args[0] |
| if x1.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x1.Args[2] |
| if ptr != x1.Args[0] { |
| break |
| } |
| x1_1 := x1.Args[1] |
| if x1_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x1_1.AuxInt != 2 { |
| break |
| } |
| if idx != x1_1.Args[0] { |
| break |
| } |
| if mem != x1.Args[2] { |
| break |
| } |
| y2 := o0.Args[1] |
| if y2.Op != OpARM64MOVDnop { |
| break |
| } |
| x2 := y2.Args[0] |
| if x2.Op != OpARM64MOVBUloadidx { |
| break |
| } |
| _ = x2.Args[2] |
| if ptr != x2.Args[0] { |
| break |
| } |
| x2_1 := x2.Args[1] |
| if x2_1.Op != OpARM64ADDconst { |
| break |
| } |
| if x2_1.AuxInt != 1 { |
| break |
| } |
| if idx != x2_1.Args[0] { |
| break |
| } |
| if mem != x2.Args[2] { |
| break |
| } |
| if !(x0.Uses == 1 && x1.Uses == 1 && x2.Uses == 1 && x3.Uses == 1 && y0.Uses == 1 && y1.Uses == 1 && y2.Uses == 1 && y3.Uses == 1 && o0.Uses == 1 && o1.Uses == 1 && s0.Uses == 1 && mergePoint(b, x0, x1, x2, x3) != nil && clobber(x0) && clobber(x1) && clobber(x2) && clobber(x3) && clobber(y0) && clobber(y1) && clobber(y2) && clobber(y3) && clobber(o0) && clobber(o1) && clobber(s0)) { |
| break |
| } |
| b = mergePoint(b, x0, x1, x2, x3) |
| v0 := b.NewValue0(v.Pos, OpARM64MOVWUloadidx, t) |
| v.reset(OpCopy) |
| v.AddArg(v0) |
| v0.AddArg(ptr) |
| v0.AddArg(idx) |
| v0.A
|
