| // Code generated by mkpreempt.go; DO NOT EDIT. |
| |
| #include "go_asm.h" |
| #include "textflag.h" |
| |
| TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0 |
| MOVD R30, -240(RSP) |
| SUB $240, RSP |
| MOVD R29, -8(RSP) |
| SUB $8, RSP, R29 |
| #ifdef GOOS_ios |
| MOVD R30, (RSP) |
| #endif |
| // Save GPs |
| STP (R0, R1), 8(RSP) |
| STP (R2, R3), 24(RSP) |
| STP (R4, R5), 40(RSP) |
| STP (R6, R7), 56(RSP) |
| STP (R8, R9), 72(RSP) |
| STP (R10, R11), 88(RSP) |
| STP (R12, R13), 104(RSP) |
| STP (R14, R15), 120(RSP) |
| STP (R16, R17), 136(RSP) |
| STP (R19, R20), 152(RSP) |
| STP (R21, R22), 168(RSP) |
| STP (R23, R24), 184(RSP) |
| STP (R25, R26), 200(RSP) |
| MOVD NZCV, R0 |
| MOVD R0, 216(RSP) |
| MOVD FPSR, R0 |
| MOVD R0, 224(RSP) |
| // Save extended register state to p.xRegs.scratch |
| MOVD g_m(g), R0 |
| MOVD m_p(R0), R0 |
| ADD $(p_xRegs+xRegPerP_scratch), R0, R0 |
| #ifdef GOEXPERIMENT_simd |
| MOVBU internal∕cpu·ARM64+const_offsetARM64HasSVE(SB), R27 |
| CMP $1, R27 |
| BNE saveNEON |
| RDVL $1, R27 |
| CMP $32, R27 |
| BGT saveNEON |
| ZSTR Z0, (VL*0)(R0) |
| ZSTR Z1, (VL*1)(R0) |
| ZSTR Z2, (VL*2)(R0) |
| ZSTR Z3, (VL*3)(R0) |
| ZSTR Z4, (VL*4)(R0) |
| ZSTR Z5, (VL*5)(R0) |
| ZSTR Z6, (VL*6)(R0) |
| ZSTR Z7, (VL*7)(R0) |
| ZSTR Z8, (VL*8)(R0) |
| ZSTR Z9, (VL*9)(R0) |
| ZSTR Z10, (VL*10)(R0) |
| ZSTR Z11, (VL*11)(R0) |
| ZSTR Z12, (VL*12)(R0) |
| ZSTR Z13, (VL*13)(R0) |
| ZSTR Z14, (VL*14)(R0) |
| ZSTR Z15, (VL*15)(R0) |
| ZSTR Z16, (VL*16)(R0) |
| ZSTR Z17, (VL*17)(R0) |
| ZSTR Z18, (VL*18)(R0) |
| ZSTR Z19, (VL*19)(R0) |
| ZSTR Z20, (VL*20)(R0) |
| ZSTR Z21, (VL*21)(R0) |
| ZSTR Z22, (VL*22)(R0) |
| ZSTR Z23, (VL*23)(R0) |
| ZSTR Z24, (VL*24)(R0) |
| ZSTR Z25, (VL*25)(R0) |
| ZSTR Z26, (VL*26)(R0) |
| ZSTR Z27, (VL*27)(R0) |
| ZSTR Z28, (VL*28)(R0) |
| ZSTR Z29, (VL*29)(R0) |
| ZSTR Z30, (VL*30)(R0) |
| ZSTR Z31, (VL*31)(R0) |
| RDVL $1, R27 |
| LSL $5, R27 |
| ADD R0, R27 |
| PSTR P0, (VL*0)(R27) |
| PSTR P1, (VL*1)(R27) |
| PSTR P2, (VL*2)(R27) |
| PSTR P3, (VL*3)(R27) |
| PSTR P4, (VL*4)(R27) |
| PSTR P5, (VL*5)(R27) |
| PSTR P6, (VL*6)(R27) |
| PSTR P7, (VL*7)(R27) |
| PSTR P8, (VL*8)(R27) |
| PSTR P9, (VL*9)(R27) |
| PSTR P10, (VL*10)(R27) |
| PSTR P11, (VL*11)(R27) |
| PSTR P12, (VL*12)(R27) |
| PSTR P13, (VL*13)(R27) |
| PSTR P14, (VL*14)(R27) |
| PSTR P15, (VL*15)(R27) |
| JMP preempt |
| #endif |
| saveNEON: |
| VST1.P [V0.B16, V1.B16, V2.B16, V3.B16], 64(R0) |
| VST1.P [V4.B16, V5.B16, V6.B16, V7.B16], 64(R0) |
| VST1.P [V8.B16, V9.B16, V10.B16, V11.B16], 64(R0) |
| VST1.P [V12.B16, V13.B16, V14.B16, V15.B16], 64(R0) |
| VST1.P [V16.B16, V17.B16, V18.B16, V19.B16], 64(R0) |
| VST1.P [V20.B16, V21.B16, V22.B16, V23.B16], 64(R0) |
| VST1.P [V24.B16, V25.B16, V26.B16, V27.B16], 64(R0) |
| VST1.P [V28.B16, V29.B16, V30.B16, V31.B16], 64(R0) |
| preempt: |
| CALL ·asyncPreempt2(SB) |
| // Restore non-GPs from *p.xRegs.cache |
| MOVD g_m(g), R0 |
| MOVD m_p(R0), R0 |
| MOVD (p_xRegs+xRegPerP_cache)(R0), R0 |
| #ifdef GOEXPERIMENT_simd |
| MOVBU internal∕cpu·ARM64+const_offsetARM64HasSVE(SB), R27 |
| CMP $1, R27 |
| BNE restoreNEON |
| RDVL $1, R27 |
| CMP $32, R27 |
| BGT restoreNEON |
| ZLDR (VL*0)(R0), Z0 |
| ZLDR (VL*1)(R0), Z1 |
| ZLDR (VL*2)(R0), Z2 |
| ZLDR (VL*3)(R0), Z3 |
| ZLDR (VL*4)(R0), Z4 |
| ZLDR (VL*5)(R0), Z5 |
| ZLDR (VL*6)(R0), Z6 |
| ZLDR (VL*7)(R0), Z7 |
| ZLDR (VL*8)(R0), Z8 |
| ZLDR (VL*9)(R0), Z9 |
| ZLDR (VL*10)(R0), Z10 |
| ZLDR (VL*11)(R0), Z11 |
| ZLDR (VL*12)(R0), Z12 |
| ZLDR (VL*13)(R0), Z13 |
| ZLDR (VL*14)(R0), Z14 |
| ZLDR (VL*15)(R0), Z15 |
| ZLDR (VL*16)(R0), Z16 |
| ZLDR (VL*17)(R0), Z17 |
| ZLDR (VL*18)(R0), Z18 |
| ZLDR (VL*19)(R0), Z19 |
| ZLDR (VL*20)(R0), Z20 |
| ZLDR (VL*21)(R0), Z21 |
| ZLDR (VL*22)(R0), Z22 |
| ZLDR (VL*23)(R0), Z23 |
| ZLDR (VL*24)(R0), Z24 |
| ZLDR (VL*25)(R0), Z25 |
| ZLDR (VL*26)(R0), Z26 |
| ZLDR (VL*27)(R0), Z27 |
| ZLDR (VL*28)(R0), Z28 |
| ZLDR (VL*29)(R0), Z29 |
| ZLDR (VL*30)(R0), Z30 |
| ZLDR (VL*31)(R0), Z31 |
| RDVL $1, R27 |
| LSL $5, R27 |
| ADD R0, R27 |
| PLDR (VL*0)(R27), P0 |
| PLDR (VL*1)(R27), P1 |
| PLDR (VL*2)(R27), P2 |
| PLDR (VL*3)(R27), P3 |
| PLDR (VL*4)(R27), P4 |
| PLDR (VL*5)(R27), P5 |
| PLDR (VL*6)(R27), P6 |
| PLDR (VL*7)(R27), P7 |
| PLDR (VL*8)(R27), P8 |
| PLDR (VL*9)(R27), P9 |
| PLDR (VL*10)(R27), P10 |
| PLDR (VL*11)(R27), P11 |
| PLDR (VL*12)(R27), P12 |
| PLDR (VL*13)(R27), P13 |
| PLDR (VL*14)(R27), P14 |
| PLDR (VL*15)(R27), P15 |
| JMP restoreGPs |
| #endif |
| restoreNEON: |
| VLD1.P 64(R0), [V0.B16, V1.B16, V2.B16, V3.B16] |
| VLD1.P 64(R0), [V4.B16, V5.B16, V6.B16, V7.B16] |
| VLD1.P 64(R0), [V8.B16, V9.B16, V10.B16, V11.B16] |
| VLD1.P 64(R0), [V12.B16, V13.B16, V14.B16, V15.B16] |
| VLD1.P 64(R0), [V16.B16, V17.B16, V18.B16, V19.B16] |
| VLD1.P 64(R0), [V20.B16, V21.B16, V22.B16, V23.B16] |
| VLD1.P 64(R0), [V24.B16, V25.B16, V26.B16, V27.B16] |
| VLD1.P 64(R0), [V28.B16, V29.B16, V30.B16, V31.B16] |
| restoreGPs: |
| // Restore GPs |
| MOVD 224(RSP), R0 |
| MOVD R0, FPSR |
| MOVD 216(RSP), R0 |
| MOVD R0, NZCV |
| LDP 200(RSP), (R25, R26) |
| LDP 184(RSP), (R23, R24) |
| LDP 168(RSP), (R21, R22) |
| LDP 152(RSP), (R19, R20) |
| LDP 136(RSP), (R16, R17) |
| LDP 120(RSP), (R14, R15) |
| LDP 104(RSP), (R12, R13) |
| LDP 88(RSP), (R10, R11) |
| LDP 72(RSP), (R8, R9) |
| LDP 56(RSP), (R6, R7) |
| LDP 40(RSP), (R4, R5) |
| LDP 24(RSP), (R2, R3) |
| LDP 8(RSP), (R0, R1) |
| MOVD 240(RSP), R30 |
| MOVD -8(RSP), R29 |
| MOVD (RSP), R27 |
| ADD $256, RSP |
| RET (R27) |
