commit 2ef8abb41f2565e38e520c18773308b3cf005af6
author fanzha02 <fannie.zhang@arm.com> Thu Feb 21 07:53:15 2019 +0000
committer Ben Shi <powerman1st@163.com> Fri Feb 22 09:29:27 2019 +0000
tree 869cf19c33a02d205519baf598dba2a53261798f
parent 0349f29a55fc194e3d51f748ec9ddceab87a5668

cmd/internal/obj/arm64: fix the bug assembling TSTW

Current assembler reports error when it assembles
"TSTW $1689262177517664, R3", but go1.11 was building
fine.

Fixes #30334

Change-Id: I9c16d36717cd05df2134e8eb5b17edc385aff0a9
Reviewed-on: https://go-review.googlesource.com/c/163259
Run-TryBot: Ben Shi <powerman1st@163.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Ben Shi <powerman1st@163.com>

src/cmd/asm/internal/asm/testdata/arm64.s

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index d025543..b54fd86 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -261,6 +261,18 @@
 	ORRW	$0x1b000, R2, R3                    // ORRW	$110592, R2, R3                 // 1b0096523b00a07243001b2a
 	TSTW	$0x500000, R1                       // TSTW	$5242880, R1                    // 1b0aa0523f001b6a
 	TSTW	$0xff00ff, R1                       // TSTW	$16711935, R1                   // 3f9c0072
+	TSTW	$0x60060, R5                        // TSTW	$393312, R5                     // 1b0c8052db00a072bf001b6a
+	TSTW	$0x6006000060060, R5                // TSTW	$1689262177517664, R5           // 1b0c8052db00a072bf001b6a
+	ANDW	$0x6006000060060, R5                // ANDW	$1689262177517664, R5           // 1b0c8052db00a072a5001b0a
+	ANDSW	$0x6006000060060, R5                // ANDSW	$1689262177517664, R5           // 1b0c8052db00a072a5001b6a
+	EORW	$0x6006000060060, R5                // EORW	$1689262177517664, R5           // 1b0c8052db00a072a5001b4a
+	ORRW	$0x6006000060060, R5                // ORRW	$1689262177517664, R5           // 1b0c8052db00a072a5001b2a
+	BICW	$0x6006000060060, R5                // BICW	$1689262177517664, R5           // 1b0c8052db00a072a5003b0a
+	EONW	$0x6006000060060, R5                // EONW	$1689262177517664, R5           // 1b0c8052db00a072a5003b4a
+	ORNW	$0x6006000060060, R5                // ORNW	$1689262177517664, R5           // 1b0c8052db00a072a5003b2a
+	BICSW	$0x6006000060060, R5                // BICSW	$1689262177517664, R5           // 1b0c8052db00a072a5003b6a
+	ADDW	$0x60060, R2                        // ADDW	$393312, R2                     // 4280011142804111
+	CMPW	$0x60060, R2                        // CMPW	$393312, R2                     // 1b0c8052db00a0725f001b6b
 
 	AND	$8, R0, RSP // 1f007d92
 	ORR	$8, R0, RSP // 1f007db2

src/cmd/internal/obj/arm64/asm7.go

diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 093b222..cbe5796 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -2986,7 +2986,7 @@
 		num := uint8(0)
 		cls := oclass(&p.From)
 		if isADDWop(p.As) {
-			if (cls != C_LCON) && (cls != C_ADDCON2) {
+			if !cmp(C_LCON, cls) {
 				c.ctxt.Diag("illegal combination: %v", p)
 			}
 			num = c.omovlconst(AMOVW, p, &p.From, REGTMP, os[:])
@@ -3271,7 +3271,7 @@
 		num := uint8(0)
 		cls := oclass(&p.From)
 		if isANDWop(p.As) {
-			if (cls != C_LCON) && (cls != C_ADDCON) {
+			if !cmp(C_LCON, cls) {
 				c.ctxt.Diag("illegal combination: %v", p)
 			}
 			num = c.omovlconst(AMOVW, p, &p.From, REGTMP, os[:])