commit 02816a2cad23a9399a6ad18033db0586c110de70
author Joel Sing <joel@sing.id.au> Mon Jan 20 02:00:44 2020 +1100
committer Joel Sing <joel@sing.id.au> Sun Jan 19 15:28:32 2020 +0000
tree b0283cf9ffbc23000ca74fa9314c4545c419addb
parent 8e0be05ec7c369387c0ed3c9cf37968c6d3afbbd

reflect: correct riscv64 assembly

R0 is not a thing in riscv64 assembly - use ZERO (rather than X0) since
the rest of this currently uses ABI names.

Updates #27532

Change-Id: I28fb68e9f80d05231a07c5921e7062777234e2c5
Reviewed-on: https://go-review.googlesource.com/c/go/+/215437
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>

src/reflect/asm_riscv64.s

diff --git a/src/reflect/asm_riscv64.s b/src/reflect/asm_riscv64.s
index f5886e5..e6fab39 100644
--- a/src/reflect/asm_riscv64.s
+++ b/src/reflect/asm_riscv64.s
@@ -16,7 +16,7 @@
 	MOV	T0, 16(SP)
 	ADD	$32, SP, T1
 	MOV	T1, 24(SP)
-	MOVB	R0, 32(SP)
+	MOVB	ZERO, 32(SP)
 	CALL	·callReflect(SB)
 	RET
 
@@ -31,6 +31,6 @@
 	MOV	T0, 16(SP)
 	ADD	$32, SP, T1
 	MOV	T1, 24(SP)
-	MOVB	R0, 32(SP)
+	MOVB	ZERO, 32(SP)
 	CALL	·callMethod(SB)
 	RET