internal/simdgen: add pairwise add/sub Change-Id: Id0b678ec956e0c4ebdaae7f8b0a7ad01365f92df Reviewed-on: https://go-review.googlesource.com/c/arch/+/678376 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
diff --git a/internal/simdgen/categories.yaml b/internal/simdgen/categories.yaml index dfc6545..aae0cc9 100644 --- a/internal/simdgen/categories.yaml +++ b/internal/simdgen/categories.yaml
@@ -27,6 +27,22 @@ masked: "true" commutative: "true" extension: "AVX.*" +- go: PairwiseAdd + commutative: "false" + extension: "AVX.*" + documentation: "Add pairs of elements in vector x and store them in higher half of the target; Add pairs of elements in vector y and store them in lower half of the target" +- go: PairwiseSub + commutative: "false" + extension: "AVX.*" + documentation: "Sub pairs of elements in vector x and store them in higher half of the target; Sub pairs of elements in vector y and store them in lower half of the target" +- go: SaturatedPairwiseAdd + commutative: "false" + extension: "AVX.*" + documentation: "Add pairs of elements in vector x and store them in higher half of the target; Add pairs of elements in vector y and store them in lower half of the target; With saturation" +- go: SaturatedPairwiseSub + commutative: "false" + extension: "AVX.*" + documentation: "Sub pairs of elements in vector x and store them in higher half of the target; Sub pairs of elements in vector y and store them in lower half of the target; With saturation" - go: And commutative: "true" extension: "AVX.*"
diff --git a/internal/simdgen/go.yaml b/internal/simdgen/go.yaml index ed7c7b1..35f0bf7 100644 --- a/internal/simdgen/go.yaml +++ b/internal/simdgen/go.yaml
@@ -55,10 +55,10 @@ # Sub - go: Sub asm: "VPSUB[BWDQ]|VADDP[SD]" - in: + in: &2any - *any - *any - out: + out: &1any - *any - go: MaskedSub asm: "VPSUB[BWDQ]|VADDP[SD]" @@ -71,10 +71,10 @@ # Saturated Sub - go: SaturatedSub asm: "VPSUBS[BWDQ]" - in: + in: &2int - *int - *int - out: + out: &1int - *int - go: SaturatedSub asm: "VPSUBS[BWDQ]" @@ -99,6 +99,30 @@ - *uint out: - *uint +- go: PairwiseAdd + asm: "VPHADD[DW]" + in: *2any + out: *1any +- go: PairwiseSub + asm: "VPHSUB[DW]" + in: *2any + out: *1any +- go: PairwiseAdd + asm: "VHADDP[SD]" # floats + in: *2any + out: *1any +- go: PairwiseSub + asm: "VHSUBP[SD]" # floats + in: *2any + out: *1any +- go: SaturatedPairwiseAdd + asm: "VPHADDS[DW]" + in: *2int + out: *1int +- go: SaturatedPairwiseSub + asm: "VPHSUBS[DW]" + in: *2int + out: *1int # In the XED data, *all* floating point bitwise logic operation has their # operand type marked as uint. We are not trying to understand why Intel # decided that they want FP bit-wise logic operations, but this irregularity
diff --git a/internal/simdgen/ops/AddSub/categories.yaml b/internal/simdgen/ops/AddSub/categories.yaml index 8da031f..e44412c 100644 --- a/internal/simdgen/ops/AddSub/categories.yaml +++ b/internal/simdgen/ops/AddSub/categories.yaml
@@ -26,4 +26,20 @@ - go: MaskedSaturatedSub masked: "true" commutative: "true" - extension: "AVX.*" \ No newline at end of file + extension: "AVX.*" +- go: PairwiseAdd + commutative: "false" + extension: "AVX.*" + documentation: "Add pairs of elements in vector x and store them in higher half of the target; Add pairs of elements in vector y and store them in lower half of the target" +- go: PairwiseSub + commutative: "false" + extension: "AVX.*" + documentation: "Sub pairs of elements in vector x and store them in higher half of the target; Sub pairs of elements in vector y and store them in lower half of the target" +- go: SaturatedPairwiseAdd + commutative: "false" + extension: "AVX.*" + documentation: "Add pairs of elements in vector x and store them in higher half of the target; Add pairs of elements in vector y and store them in lower half of the target; With saturation" +- go: SaturatedPairwiseSub + commutative: "false" + extension: "AVX.*" + documentation: "Sub pairs of elements in vector x and store them in higher half of the target; Sub pairs of elements in vector y and store them in lower half of the target; With saturation" \ No newline at end of file
diff --git a/internal/simdgen/ops/AddSub/go.yaml b/internal/simdgen/ops/AddSub/go.yaml index 9e8dc57..75222a1 100644 --- a/internal/simdgen/ops/AddSub/go.yaml +++ b/internal/simdgen/ops/AddSub/go.yaml
@@ -55,10 +55,10 @@ # Sub - go: Sub asm: "VPSUB[BWDQ]|VADDP[SD]" - in: + in: &2any - *any - *any - out: + out: &1any - *any - go: MaskedSub asm: "VPSUB[BWDQ]|VADDP[SD]" @@ -71,10 +71,10 @@ # Saturated Sub - go: SaturatedSub asm: "VPSUBS[BWDQ]" - in: + in: &2int - *int - *int - out: + out: &1int - *int - go: SaturatedSub asm: "VPSUBS[BWDQ]" @@ -99,3 +99,27 @@ - *uint out: - *uint +- go: PairwiseAdd + asm: "VPHADD[DW]" + in: *2any + out: *1any +- go: PairwiseSub + asm: "VPHSUB[DW]" + in: *2any + out: *1any +- go: PairwiseAdd + asm: "VHADDP[SD]" # floats + in: *2any + out: *1any +- go: PairwiseSub + asm: "VHSUBP[SD]" # floats + in: *2any + out: *1any +- go: SaturatedPairwiseAdd + asm: "VPHADDS[DW]" + in: *2int + out: *1int +- go: SaturatedPairwiseSub + asm: "VPHSUBS[DW]" + in: *2int + out: *1int