cmd/objdump: fix REP/REPN Plan 9 disassembly
This change contains two fixes:
1. emit REP/REPNE as separate instructions, not prefixes
2. don't emit REP/REPNE when the prefix is implied by instruction
text
Both make the objdump output more consistent with the code in Go tree
and with the output of binutils objdump.
1. According to http://doc.cat-v.org/plan_9/4th_edition/papers/asm
"Only REP and REPN are recognized repeaters. These are not prefixes,
but rather stand-alone opcodes that precede the strings"
For example, before this change "f3a6" was disassembled as:
REP CMPSB ES:0(DI), DS:0(SI)
After this change it becomes:
REP; CMPSB ES:0(DI), DS:0(SI)
2. According to Intel Manuals (Vol. 2A)
"Repeat prefixes (F2H, F3H) cause an instruction to be repeated for
each element of a string. Use these prefixes only with string and I/O
instructions (MOVS, CMPS, SCAS, LODS, STOS, INS, and OUTS). Use of
repeat prefixes and/or undefined opcodes with other Intel 64 or IA-32
instructions is reserved; such use may cause unpredictable behavior"
Certain instruction imply repeat prefixes. For example POCNT is
"F30F", which has the "F3" prefix. Before this change we would emit
"REP" prefix for such instructions:
REP POPCNT 0(CX), DX
After this change
POPCNT 0(CX), DX
The "REP RET" optimization.
The AMD Software Optimization Guide describes "Two-Byte Near-Return
RET Instruction" (adding REP prefix to RET: "f3c3"; instead of just
RET "c3"). In this case the prefix is not implied by the instruction,
but RET is not one of the string instructions either. It's unclear
whether it should
(binutils objdump does).
Fixes golang/go#17410
Change-Id: I7ec9de7f99b0e1fd5f7b96d1dc6dcb977f6454a6
Reviewed-on: https://go-review.googlesource.com/36770
Reviewed-by: Keith Randall <khr@golang.org>
diff --git a/x86/x86asm/plan9x.go b/x86/x86asm/plan9x.go
index 06ffd4d..41cfc08 100644
--- a/x86/x86asm/plan9x.go
+++ b/x86/x86asm/plan9x.go
@@ -29,20 +29,32 @@
args = append(args, plan9Arg(&inst, pc, symname, a))
}
+ var rep string
var last Prefix
for _, p := range inst.Prefix {
if p == 0 || p.IsREX() || p.IsVEX() {
break
}
- last = p
+
+ switch {
+ // Don't show prefixes implied by the instruction text.
+ case p&0xFF00 == PrefixImplicit:
+ continue
+ // Only REP and REPN are recognized repeaters. Plan 9 syntax
+ // treats them as separate opcodes.
+ case p&0xFF == PrefixREP:
+ rep = "REP; "
+ case p&0xFF == PrefixREPN:
+ rep = "REPNE; "
+ default:
+ last = p
+ }
}
prefix := ""
switch last & 0xFF {
case 0, 0x66, 0x67:
// ignore
- case PrefixREPN:
- prefix += "REPNE "
default:
prefix += last.String() + " "
}
@@ -69,7 +81,7 @@
op += " " + strings.Join(args, ", ")
}
- return prefix + op
+ return rep + prefix + op
}
func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
diff --git a/x86/x86asm/testdata/decode.txt b/x86/x86asm/testdata/decode.txt
index 9ae027a..5203789 100644
--- a/x86/x86asm/testdata/decode.txt
+++ b/x86/x86asm/testdata/decode.txt
@@ -2009,7 +2009,7 @@
2511223344|556677885f5f5f5f5f5f5f 64 intel and eax, 0x44332211
2511223344|556677885f5f5f5f5f5f5f 64 plan9 ANDL $0x44332211, AX
266e|11223344556677885f5f5f5f5f5f 32 intel outsb es
-266e|11223344556677885f5f5f5f5f5f 32 plan9 ES OUTSB ES:0(SI), DX
+266e|11223344556677885f5f5f5f5f5f 32 plan9 OUTSB ES:0(SI), DX
266e|11223344556677885f5f5f5f5f5f 64 gnu outsb %ds:%es:(%rsi),(%dx)
266e|11223344556677885f5f5f5f5f5f 64 intel outsb
266e|11223344556677885f5f5f5f5f5f 64 plan9 ES OUTSB DS:0(SI), DX
@@ -2022,7 +2022,7 @@
26a01122334455667788|5f5f5f5f5f5f 64 intel mov al, byte ptr [0x8877665544332211]
26a01122334455667788|5f5f5f5f5f5f 64 plan9 ES MOVB -0x778899aabbccddef, AL
26a011223344|556677885f5f5f5f5f5f 32 intel mov al, byte ptr es:[0x44332211]
-26a011223344|556677885f5f5f5f5f5f 32 plan9 ES MOVB ES:0x44332211, AL
+26a011223344|556677885f5f5f5f5f5f 32 plan9 MOVB ES:0x44332211, AL
26|8211223344556677885f5f5f5f5f5f 32 intel es
26|8211223344556677885f5f5f5f5f5f 32 plan9 ES Op(0)
26|8211223344556677885f5f5f5f5f5f 64 gnu es
@@ -2155,10 +2155,10 @@
3e67e011|223344556677885f5f5f5f5f 64 intel addr32 loopne .+0x11
3e67e011|223344556677885f5f5f5f5f 64 plan9 LOOPNE .+17
3ef367660f38f011|223344556677885f 32 intel movbe dx, word ptr [bx+di*1]
-3ef367660f38f011|223344556677885f 32 plan9 MOVBE DS:0(BX)(DI*1), DX
+3ef367660f38f011|223344556677885f 32 plan9 REP; MOVBE DS:0(BX)(DI*1), DX
3ef367660f38f011|223344556677885f 64 gnu rep movbe %ds:(%ecx),%dx
3ef367660f38f011|223344556677885f 64 intel movbe dx, word ptr [ecx]
-3ef367660f38f011|223344556677885f 64 plan9 MOVBE 0(CX), DX
+3ef367660f38f011|223344556677885f 64 plan9 REP; MOVBE 0(CX), DX
3f|11223344556677885f5f5f5f5f5f5f 32 intel aas
3f|11223344556677885f5f5f5f5f5f5f 32 plan9 AAS
3f|11223344556677885f5f5f5f5f5f5f 64 gnu error: unrecognized instruction
@@ -4666,53 +4666,53 @@
66ef|11223344556677885f5f5f5f5f5f 64 intel out dx, ax
66ef|11223344556677885f5f5f5f5f5f 64 plan9 OUTW AX, DX
66f20f2a11|223344556677885f5f5f5f 32 intel cvtsi2sd xmm2, dword ptr [ecx]
-66f20f2a11|223344556677885f5f5f5f 32 plan9 REPNE CVTSI2SDL 0(CX), X2
+66f20f2a11|223344556677885f5f5f5f 32 plan9 CVTSI2SDL 0(CX), X2
66f20f2a11|223344556677885f5f5f5f 64 gnu cvtsi2sdl (%rcx),%xmm2
66f20f2a11|223344556677885f5f5f5f 64 intel cvtsi2sd xmm2, dword ptr [rcx]
-66f20f2a11|223344556677885f5f5f5f 64 plan9 REPNE CVTSI2SDL 0(CX), X2
+66f20f2a11|223344556677885f5f5f5f 64 plan9 CVTSI2SDL 0(CX), X2
# the Q extension is the size of the source float64 in memory. The destination is L.
66f20f2c11|223344556677885f5f5f5f 32 intel cvttsd2si edx, qword ptr [ecx]
-66f20f2c11|223344556677885f5f5f5f 32 plan9 REPNE CVTTSD2SIQ 0(CX), DX
+66f20f2c11|223344556677885f5f5f5f 32 plan9 CVTTSD2SIQ 0(CX), DX
66f20f2c11|223344556677885f5f5f5f 64 gnu cvttsd2si (%rcx),%dx
66f20f2c11|223344556677885f5f5f5f 64 intel cvttsd2si edx, qword ptr [rcx]
-66f20f2c11|223344556677885f5f5f5f 64 plan9 REPNE CVTTSD2SIQ 0(CX), DX
+66f20f2c11|223344556677885f5f5f5f 64 plan9 CVTTSD2SIQ 0(CX), DX
66f20f2d11|223344556677885f5f5f5f 32 intel cvtsd2si edx, qword ptr [ecx]
-66f20f2d11|223344556677885f5f5f5f 32 plan9 REPNE CVTSD2SIQ 0(CX), DX
+66f20f2d11|223344556677885f5f5f5f 32 plan9 CVTSD2SIQ 0(CX), DX
66f20f2d11|223344556677885f5f5f5f 64 gnu cvtsd2si (%rcx),%dx
66f20f2d11|223344556677885f5f5f5f 64 intel cvtsd2si edx, qword ptr [rcx]
-66f20f2d11|223344556677885f5f5f5f 64 plan9 REPNE CVTSD2SIQ 0(CX), DX
+66f20f2d11|223344556677885f5f5f5f 64 plan9 CVTSD2SIQ 0(CX), DX
66f20f38f011|223344556677885f5f5f 32 intel crc32 edx, byte ptr [ecx]
-66f20f38f011|223344556677885f5f5f 32 plan9 REPNE CRC32 0(CX), DX
+66f20f38f011|223344556677885f5f5f 32 plan9 CRC32 0(CX), DX
66f20f38f011|223344556677885f5f5f 64 gnu crc32b (%rcx),%edx
66f20f38f011|223344556677885f5f5f 64 intel crc32 edx, byte ptr [rcx]
-66f20f38f011|223344556677885f5f5f 64 plan9 REPNE CRC32 0(CX), DX
+66f20f38f011|223344556677885f5f5f 64 plan9 CRC32 0(CX), DX
66f30f2c11|223344556677885f5f5f5f 32 intel cvttss2si edx, dword ptr [ecx]
-66f30f2c11|223344556677885f5f5f5f 32 plan9 REP CVTTSS2SIL 0(CX), DX
+66f30f2c11|223344556677885f5f5f5f 32 plan9 CVTTSS2SIL 0(CX), DX
66f30f2c11|223344556677885f5f5f5f 64 gnu cvttss2si (%rcx),%dx
66f30f2c11|223344556677885f5f5f5f 64 intel cvttss2si edx, dword ptr [rcx]
-66f30f2c11|223344556677885f5f5f5f 64 plan9 REP CVTTSS2SIL 0(CX), DX
+66f30f2c11|223344556677885f5f5f5f 64 plan9 CVTTSS2SIL 0(CX), DX
66f30f2d11|223344556677885f5f5f5f 32 intel cvtss2si edx, dword ptr [ecx]
-66f30f2d11|223344556677885f5f5f5f 32 plan9 REP CVTSS2SIL 0(CX), DX
+66f30f2d11|223344556677885f5f5f5f 32 plan9 CVTSS2SIL 0(CX), DX
66f30f2d11|223344556677885f5f5f5f 64 gnu cvtss2si (%rcx),%dx
66f30f2d11|223344556677885f5f5f5f 64 intel cvtss2si edx, dword ptr [rcx]
-66f30f2d11|223344556677885f5f5f5f 64 plan9 REP CVTSS2SIL 0(CX), DX
+66f30f2d11|223344556677885f5f5f5f 64 plan9 CVTSS2SIL 0(CX), DX
66f30fae11|223344556677885f5f5f5f 64 gnu wrfsbasel (%rcx)
66f30fae11|223344556677885f5f5f5f 64 intel wrfsbase dword ptr [rcx]
-66f30fae11|223344556677885f5f5f5f 64 plan9 REP WRFSBASE 0(CX)
+66f30fae11|223344556677885f5f5f5f 64 plan9 WRFSBASE 0(CX)
66f30fae18|11223344556677885f5f5f 64 gnu wrgsbasel (%rax)
66f30fae18|11223344556677885f5f5f 64 intel wrgsbase dword ptr [rax]
-66f30fae18|11223344556677885f5f5f 64 plan9 REP WRGSBASE 0(AX)
+66f30fae18|11223344556677885f5f5f 64 plan9 WRGSBASE 0(AX)
66f30faec0|11223344556677885f5f5f 64 gnu rdfsbase %eax
66f30faec0|11223344556677885f5f5f 64 intel rdfsbase eax
-66f30faec0|11223344556677885f5f5f 64 plan9 REP RDFSBASE AX
+66f30faec0|11223344556677885f5f5f 64 plan9 RDFSBASE AX
66f30faec8|11223344556677885f5f5f 64 gnu rdgsbase %eax
66f30faec8|11223344556677885f5f5f 64 intel rdgsbase eax
-66f30faec8|11223344556677885f5f5f 64 plan9 REP RDGSBASE AX
+66f30faec8|11223344556677885f5f5f 64 plan9 RDGSBASE AX
66f30fd6c5|11223344556677885f5f5f 32 intel movq2dq xmm0, mmx5
-66f30fd6c5|11223344556677885f5f5f 32 plan9 REP MOVQ2DQ M5, X0
+66f30fd6c5|11223344556677885f5f5f 32 plan9 MOVQ2DQ M5, X0
66f30fd6c5|11223344556677885f5f5f 64 gnu movq2dq %mm5,%xmm0
66f30fd6c5|11223344556677885f5f5f 64 intel movq2dq xmm0, mmx5
-66f30fd6c5|11223344556677885f5f5f 64 plan9 REP MOVQ2DQ M5, X0
+66f30fd6c5|11223344556677885f5f5f 64 plan9 MOVQ2DQ M5, X0
66f7001122|3344556677885f5f5f5f5f 32 intel test word ptr [eax], 0x2211
66f7001122|3344556677885f5f5f5f5f 32 plan9 TESTW $0x2211, 0(AX)
66f7001122|3344556677885f5f5f5f5f 64 gnu testw $0x2211,(%rax)
@@ -6236,327 +6236,327 @@
f1|11223344556677885f5f5f5f5f5f5f 64 intel int1
f1|11223344556677885f5f5f5f5f5f5f 64 plan9 ICEBP
f20f1011|223344556677885f5f5f5f5f 32 intel movsd xmm2, qword ptr [ecx]
-f20f1011|223344556677885f5f5f5f5f 32 plan9 REPNE MOVSD_XMM 0(CX), X2
+f20f1011|223344556677885f5f5f5f5f 32 plan9 MOVSD_XMM 0(CX), X2
f20f1011|223344556677885f5f5f5f5f 64 gnu movsd (%rcx),%xmm2
f20f1011|223344556677885f5f5f5f5f 64 intel movsd xmm2, qword ptr [rcx]
-f20f1011|223344556677885f5f5f5f5f 64 plan9 REPNE MOVSD_XMM 0(CX), X2
+f20f1011|223344556677885f5f5f5f5f 64 plan9 MOVSD_XMM 0(CX), X2
f20f1122|3344556677885f5f5f5f5f5f 32 intel movsd qword ptr [edx], xmm4
-f20f1122|3344556677885f5f5f5f5f5f 32 plan9 REPNE MOVSD_XMM X4, 0(DX)
+f20f1122|3344556677885f5f5f5f5f5f 32 plan9 MOVSD_XMM X4, 0(DX)
f20f1122|3344556677885f5f5f5f5f5f 64 gnu movsd %xmm4,(%rdx)
f20f1122|3344556677885f5f5f5f5f5f 64 intel movsd qword ptr [rdx], xmm4
-f20f1122|3344556677885f5f5f5f5f5f 64 plan9 REPNE MOVSD_XMM X4, 0(DX)
+f20f1122|3344556677885f5f5f5f5f5f 64 plan9 MOVSD_XMM X4, 0(DX)
f20f1211|223344556677885f5f5f5f5f 32 intel movddup xmm2, qword ptr [ecx]
-f20f1211|223344556677885f5f5f5f5f 32 plan9 REPNE MOVDDUP 0(CX), X2
+f20f1211|223344556677885f5f5f5f5f 32 plan9 MOVDDUP 0(CX), X2
f20f1211|223344556677885f5f5f5f5f 64 gnu movddup (%rcx),%xmm2
f20f1211|223344556677885f5f5f5f5f 64 intel movddup xmm2, qword ptr [rcx]
-f20f1211|223344556677885f5f5f5f5f 64 plan9 REPNE MOVDDUP 0(CX), X2
+f20f1211|223344556677885f5f5f5f5f 64 plan9 MOVDDUP 0(CX), X2
f20f2a11|223344556677885f5f5f5f5f 32 intel cvtsi2sd xmm2, dword ptr [ecx]
-f20f2a11|223344556677885f5f5f5f5f 32 plan9 REPNE CVTSI2SDL 0(CX), X2
+f20f2a11|223344556677885f5f5f5f5f 32 plan9 CVTSI2SDL 0(CX), X2
f20f2a11|223344556677885f5f5f5f5f 64 gnu cvtsi2sdl (%rcx),%xmm2
f20f2a11|223344556677885f5f5f5f5f 64 intel cvtsi2sd xmm2, dword ptr [rcx]
-f20f2a11|223344556677885f5f5f5f5f 64 plan9 REPNE CVTSI2SDL 0(CX), X2
+f20f2a11|223344556677885f5f5f5f5f 64 plan9 CVTSI2SDL 0(CX), X2
f20f2c11|223344556677885f5f5f5f5f 32 intel cvttsd2si edx, qword ptr [ecx]
-f20f2c11|223344556677885f5f5f5f5f 32 plan9 REPNE CVTTSD2SIQ 0(CX), DX
+f20f2c11|223344556677885f5f5f5f5f 32 plan9 CVTTSD2SIQ 0(CX), DX
f20f2c11|223344556677885f5f5f5f5f 64 gnu cvttsd2si (%rcx),%edx
f20f2c11|223344556677885f5f5f5f5f 64 intel cvttsd2si edx, qword ptr [rcx]
-f20f2c11|223344556677885f5f5f5f5f 64 plan9 REPNE CVTTSD2SIQ 0(CX), DX
+f20f2c11|223344556677885f5f5f5f5f 64 plan9 CVTTSD2SIQ 0(CX), DX
f20f2d11|223344556677885f5f5f5f5f 32 intel cvtsd2si edx, qword ptr [ecx]
-f20f2d11|223344556677885f5f5f5f5f 32 plan9 REPNE CVTSD2SIQ 0(CX), DX
+f20f2d11|223344556677885f5f5f5f5f 32 plan9 CVTSD2SIQ 0(CX), DX
f20f2d11|223344556677885f5f5f5f5f 64 gnu cvtsd2si (%rcx),%edx
f20f2d11|223344556677885f5f5f5f5f 64 intel cvtsd2si edx, qword ptr [rcx]
-f20f2d11|223344556677885f5f5f5f5f 64 plan9 REPNE CVTSD2SIQ 0(CX), DX
+f20f2d11|223344556677885f5f5f5f5f 64 plan9 CVTSD2SIQ 0(CX), DX
f20f38f011|223344556677885f5f5f5f 32 intel crc32 edx, byte ptr [ecx]
-f20f38f011|223344556677885f5f5f5f 32 plan9 REPNE CRC32 0(CX), DX
+f20f38f011|223344556677885f5f5f5f 32 plan9 CRC32 0(CX), DX
f20f38f011|223344556677885f5f5f5f 64 gnu crc32b (%rcx),%edx
f20f38f011|223344556677885f5f5f5f 64 intel crc32 edx, byte ptr [rcx]
-f20f38f011|223344556677885f5f5f5f 64 plan9 REPNE CRC32 0(CX), DX
+f20f38f011|223344556677885f5f5f5f 64 plan9 CRC32 0(CX), DX
f20f38f111|223344556677885f5f5f5f 32 intel crc32 edx, dword ptr [ecx]
-f20f38f111|223344556677885f5f5f5f 32 plan9 REPNE CRC32 0(CX), DX
+f20f38f111|223344556677885f5f5f5f 32 plan9 CRC32 0(CX), DX
f20f38f111|223344556677885f5f5f5f 64 gnu crc32l (%rcx),%edx
f20f38f111|223344556677885f5f5f5f 64 intel crc32 edx, dword ptr [rcx]
-f20f38f111|223344556677885f5f5f5f 64 plan9 REPNE CRC32 0(CX), DX
+f20f38f111|223344556677885f5f5f5f 64 plan9 CRC32 0(CX), DX
f20f5111|223344556677885f5f5f5f5f 32 intel sqrtsd xmm2, qword ptr [ecx]
-f20f5111|223344556677885f5f5f5f5f 32 plan9 REPNE SQRTSD 0(CX), X2
+f20f5111|223344556677885f5f5f5f5f 32 plan9 SQRTSD 0(CX), X2
f20f5111|223344556677885f5f5f5f5f 64 gnu sqrtsd (%rcx),%xmm2
f20f5111|223344556677885f5f5f5f5f 64 intel sqrtsd xmm2, qword ptr [rcx]
-f20f5111|223344556677885f5f5f5f5f 64 plan9 REPNE SQRTSD 0(CX), X2
+f20f5111|223344556677885f5f5f5f5f 64 plan9 SQRTSD 0(CX), X2
f20f5811|223344556677885f5f5f5f5f 32 intel addsd xmm2, qword ptr [ecx]
-f20f5811|223344556677885f5f5f5f5f 32 plan9 REPNE ADDSD 0(CX), X2
+f20f5811|223344556677885f5f5f5f5f 32 plan9 ADDSD 0(CX), X2
f20f5811|223344556677885f5f5f5f5f 64 gnu addsd (%rcx),%xmm2
f20f5811|223344556677885f5f5f5f5f 64 intel addsd xmm2, qword ptr [rcx]
-f20f5811|223344556677885f5f5f5f5f 64 plan9 REPNE ADDSD 0(CX), X2
+f20f5811|223344556677885f5f5f5f5f 64 plan9 ADDSD 0(CX), X2
f20f5911|223344556677885f5f5f5f5f 32 intel mulsd xmm2, qword ptr [ecx]
-f20f5911|223344556677885f5f5f5f5f 32 plan9 REPNE MULSD 0(CX), X2
+f20f5911|223344556677885f5f5f5f5f 32 plan9 MULSD 0(CX), X2
f20f5911|223344556677885f5f5f5f5f 64 gnu mulsd (%rcx),%xmm2
f20f5911|223344556677885f5f5f5f5f 64 intel mulsd xmm2, qword ptr [rcx]
-f20f5911|223344556677885f5f5f5f5f 64 plan9 REPNE MULSD 0(CX), X2
+f20f5911|223344556677885f5f5f5f5f 64 plan9 MULSD 0(CX), X2
f20f5a11|223344556677885f5f5f5f5f 32 intel cvtsd2ss xmm2, qword ptr [ecx]
-f20f5a11|223344556677885f5f5f5f5f 32 plan9 REPNE CVTSD2SS 0(CX), X2
+f20f5a11|223344556677885f5f5f5f5f 32 plan9 CVTSD2SS 0(CX), X2
f20f5a11|223344556677885f5f5f5f5f 64 gnu cvtsd2ss (%rcx),%xmm2
f20f5a11|223344556677885f5f5f5f5f 64 intel cvtsd2ss xmm2, qword ptr [rcx]
-f20f5a11|223344556677885f5f5f5f5f 64 plan9 REPNE CVTSD2SS 0(CX), X2
+f20f5a11|223344556677885f5f5f5f5f 64 plan9 CVTSD2SS 0(CX), X2
f20f5c11|223344556677885f5f5f5f5f 32 intel subsd xmm2, qword ptr [ecx]
-f20f5c11|223344556677885f5f5f5f5f 32 plan9 REPNE SUBSD 0(CX), X2
+f20f5c11|223344556677885f5f5f5f5f 32 plan9 SUBSD 0(CX), X2
f20f5c11|223344556677885f5f5f5f5f 64 gnu subsd (%rcx),%xmm2
f20f5c11|223344556677885f5f5f5f5f 64 intel subsd xmm2, qword ptr [rcx]
-f20f5c11|223344556677885f5f5f5f5f 64 plan9 REPNE SUBSD 0(CX), X2
+f20f5c11|223344556677885f5f5f5f5f 64 plan9 SUBSD 0(CX), X2
f20f5d11|223344556677885f5f5f5f5f 32 intel minsd xmm2, qword ptr [ecx]
-f20f5d11|223344556677885f5f5f5f5f 32 plan9 REPNE MINSD 0(CX), X2
+f20f5d11|223344556677885f5f5f5f5f 32 plan9 MINSD 0(CX), X2
f20f5d11|223344556677885f5f5f5f5f 64 gnu minsd (%rcx),%xmm2
f20f5d11|223344556677885f5f5f5f5f 64 intel minsd xmm2, qword ptr [rcx]
-f20f5d11|223344556677885f5f5f5f5f 64 plan9 REPNE MINSD 0(CX), X2
+f20f5d11|223344556677885f5f5f5f5f 64 plan9 MINSD 0(CX), X2
f20f5e11|223344556677885f5f5f5f5f 32 intel divsd xmm2, qword ptr [ecx]
-f20f5e11|223344556677885f5f5f5f5f 32 plan9 REPNE DIVSD 0(CX), X2
+f20f5e11|223344556677885f5f5f5f5f 32 plan9 DIVSD 0(CX), X2
f20f5e11|223344556677885f5f5f5f5f 64 gnu divsd (%rcx),%xmm2
f20f5e11|223344556677885f5f5f5f5f 64 intel divsd xmm2, qword ptr [rcx]
-f20f5e11|223344556677885f5f5f5f5f 64 plan9 REPNE DIVSD 0(CX), X2
+f20f5e11|223344556677885f5f5f5f5f 64 plan9 DIVSD 0(CX), X2
f20f5f11|223344556677885f5f5f5f5f 32 intel maxsd xmm2, qword ptr [ecx]
-f20f5f11|223344556677885f5f5f5f5f 32 plan9 REPNE MAXSD 0(CX), X2
+f20f5f11|223344556677885f5f5f5f5f 32 plan9 MAXSD 0(CX), X2
f20f5f11|223344556677885f5f5f5f5f 64 gnu maxsd (%rcx),%xmm2
f20f5f11|223344556677885f5f5f5f5f 64 intel maxsd xmm2, qword ptr [rcx]
-f20f5f11|223344556677885f5f5f5f5f 64 plan9 REPNE MAXSD 0(CX), X2
+f20f5f11|223344556677885f5f5f5f5f 64 plan9 MAXSD 0(CX), X2
f20f701122|3344556677885f5f5f5f5f 32 intel pshuflw xmm2, xmmword ptr [ecx], 0x22
-f20f701122|3344556677885f5f5f5f5f 32 plan9 REPNE PSHUFLW $0x22, 0(CX), X2
+f20f701122|3344556677885f5f5f5f5f 32 plan9 PSHUFLW $0x22, 0(CX), X2
f20f701122|3344556677885f5f5f5f5f 64 gnu pshuflw $0x22,(%rcx),%xmm2
f20f701122|3344556677885f5f5f5f5f 64 intel pshuflw xmm2, xmmword ptr [rcx], 0x22
-f20f701122|3344556677885f5f5f5f5f 64 plan9 REPNE PSHUFLW $0x22, 0(CX), X2
+f20f701122|3344556677885f5f5f5f5f 64 plan9 PSHUFLW $0x22, 0(CX), X2
f20f7c11|223344556677885f5f5f5f5f 32 intel haddps xmm2, xmmword ptr [ecx]
-f20f7c11|223344556677885f5f5f5f5f 32 plan9 REPNE HADDPS 0(CX), X2
+f20f7c11|223344556677885f5f5f5f5f 32 plan9 HADDPS 0(CX), X2
f20f7c11|223344556677885f5f5f5f5f 64 gnu haddps (%rcx),%xmm2
f20f7c11|223344556677885f5f5f5f5f 64 intel haddps xmm2, xmmword ptr [rcx]
-f20f7c11|223344556677885f5f5f5f5f 64 plan9 REPNE HADDPS 0(CX), X2
+f20f7c11|223344556677885f5f5f5f5f 64 plan9 HADDPS 0(CX), X2
f20f7d11|223344556677885f5f5f5f5f 32 intel hsubps xmm2, xmmword ptr [ecx]
-f20f7d11|223344556677885f5f5f5f5f 32 plan9 REPNE HSUBPS 0(CX), X2
+f20f7d11|223344556677885f5f5f5f5f 32 plan9 HSUBPS 0(CX), X2
f20f7d11|223344556677885f5f5f5f5f 64 gnu hsubps (%rcx),%xmm2
f20f7d11|223344556677885f5f5f5f5f 64 intel hsubps xmm2, xmmword ptr [rcx]
-f20f7d11|223344556677885f5f5f5f5f 64 plan9 REPNE HSUBPS 0(CX), X2
+f20f7d11|223344556677885f5f5f5f5f 64 plan9 HSUBPS 0(CX), X2
f20fc21122|3344556677885f5f5f5f5f 32 intel cmpsd_xmm xmm2, qword ptr [ecx], 0x22
-f20fc21122|3344556677885f5f5f5f5f 32 plan9 REPNE CMPSD_XMM $0x22, 0(CX), X2
+f20fc21122|3344556677885f5f5f5f5f 32 plan9 CMPSD_XMM $0x22, 0(CX), X2
f20fc21122|3344556677885f5f5f5f5f 64 gnu cmpsd $0x22,(%rcx),%xmm2
f20fc21122|3344556677885f5f5f5f5f 64 intel cmpsd_xmm xmm2, qword ptr [rcx], 0x22
-f20fc21122|3344556677885f5f5f5f5f 64 plan9 REPNE CMPSD_XMM $0x22, 0(CX), X2
+f20fc21122|3344556677885f5f5f5f5f 64 plan9 CMPSD_XMM $0x22, 0(CX), X2
f20fd011|223344556677885f5f5f5f5f 32 intel addsubps xmm2, xmmword ptr [ecx]
-f20fd011|223344556677885f5f5f5f5f 32 plan9 REPNE ADDSUBPS 0(CX), X2
+f20fd011|223344556677885f5f5f5f5f 32 plan9 ADDSUBPS 0(CX), X2
f20fd011|223344556677885f5f5f5f5f 64 gnu addsubps (%rcx),%xmm2
f20fd011|223344556677885f5f5f5f5f 64 intel addsubps xmm2, xmmword ptr [rcx]
-f20fd011|223344556677885f5f5f5f5f 64 plan9 REPNE ADDSUBPS 0(CX), X2
+f20fd011|223344556677885f5f5f5f5f 64 plan9 ADDSUBPS 0(CX), X2
f20fd6c0|11223344556677885f5f5f5f 32 intel movdq2q mmx0, xmm0
-f20fd6c0|11223344556677885f5f5f5f 32 plan9 REPNE MOVDQ2Q X0, M0
+f20fd6c0|11223344556677885f5f5f5f 32 plan9 MOVDQ2Q X0, M0
f20fd6c0|11223344556677885f5f5f5f 64 gnu movdq2q %xmm0,%mm0
f20fd6c0|11223344556677885f5f5f5f 64 intel movdq2q mmx0, xmm0
-f20fd6c0|11223344556677885f5f5f5f 64 plan9 REPNE MOVDQ2Q X0, M0
+f20fd6c0|11223344556677885f5f5f5f 64 plan9 MOVDQ2Q X0, M0
f20fe611|223344556677885f5f5f5f5f 32 intel cvtpd2dq xmm2, xmmword ptr [ecx]
-f20fe611|223344556677885f5f5f5f5f 32 plan9 REPNE CVTPD2DQ 0(CX), X2
+f20fe611|223344556677885f5f5f5f5f 32 plan9 CVTPD2DQ 0(CX), X2
f20fe611|223344556677885f5f5f5f5f 64 gnu cvtpd2dq (%rcx),%xmm2
f20fe611|223344556677885f5f5f5f5f 64 intel cvtpd2dq xmm2, xmmword ptr [rcx]
-f20fe611|223344556677885f5f5f5f5f 64 plan9 REPNE CVTPD2DQ 0(CX), X2
+f20fe611|223344556677885f5f5f5f5f 64 plan9 CVTPD2DQ 0(CX), X2
f20ff011|223344556677885f5f5f5f5f 32 intel lddqu xmm2, xmmword ptr [ecx]
-f20ff011|223344556677885f5f5f5f5f 32 plan9 REPNE LDDQU 0(CX), X2
+f20ff011|223344556677885f5f5f5f5f 32 plan9 LDDQU 0(CX), X2
f20ff011|223344556677885f5f5f5f5f 64 gnu lddqu (%rcx),%xmm2
f20ff011|223344556677885f5f5f5f5f 64 intel lddqu xmm2, xmmword ptr [rcx]
-f20ff011|223344556677885f5f5f5f5f 64 plan9 REPNE LDDQU 0(CX), X2
+f20ff011|223344556677885f5f5f5f5f 64 plan9 LDDQU 0(CX), X2
f2480f2a11|223344556677885f5f5f5f 64 gnu cvtsi2sdq (%rcx),%xmm2
f2480f2a11|223344556677885f5f5f5f 64 intel cvtsi2sd xmm2, qword ptr [rcx]
-f2480f2a11|223344556677885f5f5f5f 64 plan9 REPNE CVTSI2SDQ 0(CX), X2
+f2480f2a11|223344556677885f5f5f5f 64 plan9 CVTSI2SDQ 0(CX), X2
f2480f2c11|223344556677885f5f5f5f 64 gnu cvttsd2si (%rcx),%rdx
f2480f2c11|223344556677885f5f5f5f 64 intel cvttsd2si rdx, qword ptr [rcx]
-f2480f2c11|223344556677885f5f5f5f 64 plan9 REPNE CVTTSD2SIQ 0(CX), DX
+f2480f2c11|223344556677885f5f5f5f 64 plan9 CVTTSD2SIQ 0(CX), DX
f2480f2d11|223344556677885f5f5f5f 64 gnu cvtsd2si (%rcx),%rdx
f2480f2d11|223344556677885f5f5f5f 64 intel cvtsd2si rdx, qword ptr [rcx]
-f2480f2d11|223344556677885f5f5f5f 64 plan9 REPNE CVTSD2SIQ 0(CX), DX
+f2480f2d11|223344556677885f5f5f5f 64 plan9 CVTSD2SIQ 0(CX), DX
f2480f38f011|223344556677885f5f5f 64 gnu crc32b (%rcx),%rdx
f2480f38f011|223344556677885f5f5f 64 intel crc32 rdx, byte ptr [rcx]
-f2480f38f011|223344556677885f5f5f 64 plan9 REPNE CRC32 0(CX), DX
+f2480f38f011|223344556677885f5f5f 64 plan9 CRC32 0(CX), DX
f2480f38f111|223344556677885f5f5f 64 gnu crc32q (%rcx),%rdx
f2480f38f111|223344556677885f5f5f 64 intel crc32 rdx, qword ptr [rcx]
-f2480f38f111|223344556677885f5f5f 64 plan9 REPNE CRC32 0(CX), DX
+f2480f38f111|223344556677885f5f5f 64 plan9 CRC32 0(CX), DX
f267f0663e360f38f111|223344556677 32 intel lock crc32 edx, word ptr ss:[bx+di*1]
-f267f0663e360f38f111|223344556677 32 plan9 SS CRC32 SS:0(BX)(DI*1), DX
+f267f0663e360f38f111|223344556677 32 plan9 DS CRC32 SS:0(BX)(DI*1), DX
f267f0663e360f38f111|223344556677 64 gnu lock crc32w %ds:%ss:(%ecx),%edx
f267f0663e360f38f111|223344556677 64 intel lock crc32 edx, word ptr [ecx]
f267f0663e360f38f111|223344556677 64 plan9 SS CRC32 0(CX), DX
f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 32 intel movntss dword ptr [ecx], xmm2
-f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 32 plan9 REP MOVNTSS X2, 0(CX)
+f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 32 plan9 REPNE; MOVNTSS X2, 0(CX)
f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 gnu repn movntss %xmm2,(%rcx)
f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 intel movntss dword ptr [rcx], xmm2
-f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 plan9 REP MOVNTSS X2, 0(CX)
+f2f30f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 plan9 REPNE; MOVNTSS X2, 0(CX)
f30f1011|223344556677885f5f5f5f5f 32 intel movss xmm2, dword ptr [ecx]
-f30f1011|223344556677885f5f5f5f5f 32 plan9 REP MOVSS 0(CX), X2
+f30f1011|223344556677885f5f5f5f5f 32 plan9 MOVSS 0(CX), X2
f30f1011|223344556677885f5f5f5f5f 64 gnu movss (%rcx),%xmm2
f30f1011|223344556677885f5f5f5f5f 64 intel movss xmm2, dword ptr [rcx]
-f30f1011|223344556677885f5f5f5f5f 64 plan9 REP MOVSS 0(CX), X2
+f30f1011|223344556677885f5f5f5f5f 64 plan9 MOVSS 0(CX), X2
f30f1122|3344556677885f5f5f5f5f5f 32 intel movss dword ptr [edx], xmm4
-f30f1122|3344556677885f5f5f5f5f5f 32 plan9 REP MOVSS X4, 0(DX)
+f30f1122|3344556677885f5f5f5f5f5f 32 plan9 MOVSS X4, 0(DX)
f30f1122|3344556677885f5f5f5f5f5f 64 gnu movss %xmm4,(%rdx)
f30f1122|3344556677885f5f5f5f5f5f 64 intel movss dword ptr [rdx], xmm4
-f30f1122|3344556677885f5f5f5f5f5f 64 plan9 REP MOVSS X4, 0(DX)
+f30f1122|3344556677885f5f5f5f5f5f 64 plan9 MOVSS X4, 0(DX)
f30f1211|223344556677885f5f5f5f5f 32 intel movsldup xmm2, xmmword ptr [ecx]
-f30f1211|223344556677885f5f5f5f5f 32 plan9 REP MOVSLDUP 0(CX), X2
+f30f1211|223344556677885f5f5f5f5f 32 plan9 MOVSLDUP 0(CX), X2
f30f1211|223344556677885f5f5f5f5f 64 gnu movsldup (%rcx),%xmm2
f30f1211|223344556677885f5f5f5f5f 64 intel movsldup xmm2, xmmword ptr [rcx]
-f30f1211|223344556677885f5f5f5f5f 64 plan9 REP MOVSLDUP 0(CX), X2
+f30f1211|223344556677885f5f5f5f5f 64 plan9 MOVSLDUP 0(CX), X2
f30f1611|223344556677885f5f5f5f5f 32 intel movshdup xmm2, xmmword ptr [ecx]
-f30f1611|223344556677885f5f5f5f5f 32 plan9 REP MOVSHDUP 0(CX), X2
+f30f1611|223344556677885f5f5f5f5f 32 plan9 MOVSHDUP 0(CX), X2
f30f1611|223344556677885f5f5f5f5f 64 gnu movshdup (%rcx),%xmm2
f30f1611|223344556677885f5f5f5f5f 64 intel movshdup xmm2, xmmword ptr [rcx]
-f30f1611|223344556677885f5f5f5f5f 64 plan9 REP MOVSHDUP 0(CX), X2
+f30f1611|223344556677885f5f5f5f5f 64 plan9 MOVSHDUP 0(CX), X2
f30f2a11|223344556677885f5f5f5f5f 32 intel cvtsi2ss xmm2, dword ptr [ecx]
-f30f2a11|223344556677885f5f5f5f5f 32 plan9 REP CVTSI2SSL 0(CX), X2
+f30f2a11|223344556677885f5f5f5f5f 32 plan9 CVTSI2SSL 0(CX), X2
f30f2a11|223344556677885f5f5f5f5f 64 gnu cvtsi2ssl (%rcx),%xmm2
f30f2a11|223344556677885f5f5f5f5f 64 intel cvtsi2ss xmm2, dword ptr [rcx]
-f30f2a11|223344556677885f5f5f5f5f 64 plan9 REP CVTSI2SSL 0(CX), X2
+f30f2a11|223344556677885f5f5f5f5f 64 plan9 CVTSI2SSL 0(CX), X2
f30f2c11|223344556677885f5f5f5f5f 32 intel cvttss2si edx, dword ptr [ecx]
-f30f2c11|223344556677885f5f5f5f5f 32 plan9 REP CVTTSS2SIL 0(CX), DX
+f30f2c11|223344556677885f5f5f5f5f 32 plan9 CVTTSS2SIL 0(CX), DX
f30f2c11|223344556677885f5f5f5f5f 64 gnu cvttss2si (%rcx),%edx
f30f2c11|223344556677885f5f5f5f5f 64 intel cvttss2si edx, dword ptr [rcx]
-f30f2c11|223344556677885f5f5f5f5f 64 plan9 REP CVTTSS2SIL 0(CX), DX
+f30f2c11|223344556677885f5f5f5f5f 64 plan9 CVTTSS2SIL 0(CX), DX
f30f2d11|223344556677885f5f5f5f5f 32 intel cvtss2si edx, dword ptr [ecx]
-f30f2d11|223344556677885f5f5f5f5f 32 plan9 REP CVTSS2SIL 0(CX), DX
+f30f2d11|223344556677885f5f5f5f5f 32 plan9 CVTSS2SIL 0(CX), DX
f30f2d11|223344556677885f5f5f5f5f 64 gnu cvtss2si (%rcx),%edx
f30f2d11|223344556677885f5f5f5f5f 64 intel cvtss2si edx, dword ptr [rcx]
-f30f2d11|223344556677885f5f5f5f5f 64 plan9 REP CVTSS2SIL 0(CX), DX
+f30f2d11|223344556677885f5f5f5f5f 64 plan9 CVTSS2SIL 0(CX), DX
f30f5111|223344556677885f5f5f5f5f 32 intel sqrtss xmm2, dword ptr [ecx]
-f30f5111|223344556677885f5f5f5f5f 32 plan9 REP SQRTSS 0(CX), X2
+f30f5111|223344556677885f5f5f5f5f 32 plan9 SQRTSS 0(CX), X2
f30f5111|223344556677885f5f5f5f5f 64 gnu sqrtss (%rcx),%xmm2
f30f5111|223344556677885f5f5f5f5f 64 intel sqrtss xmm2, dword ptr [rcx]
-f30f5111|223344556677885f5f5f5f5f 64 plan9 REP SQRTSS 0(CX), X2
+f30f5111|223344556677885f5f5f5f5f 64 plan9 SQRTSS 0(CX), X2
f30f5211|223344556677885f5f5f5f5f 32 intel rsqrtss xmm2, dword ptr [ecx]
-f30f5211|223344556677885f5f5f5f5f 32 plan9 REP RSQRTSS 0(CX), X2
+f30f5211|223344556677885f5f5f5f5f 32 plan9 RSQRTSS 0(CX), X2
f30f5211|223344556677885f5f5f5f5f 64 gnu rsqrtss (%rcx),%xmm2
f30f5211|223344556677885f5f5f5f5f 64 intel rsqrtss xmm2, dword ptr [rcx]
-f30f5211|223344556677885f5f5f5f5f 64 plan9 REP RSQRTSS 0(CX), X2
+f30f5211|223344556677885f5f5f5f5f 64 plan9 RSQRTSS 0(CX), X2
f30f5311|223344556677885f5f5f5f5f 32 intel rcpss xmm2, dword ptr [ecx]
-f30f5311|223344556677885f5f5f5f5f 32 plan9 REP RCPSS 0(CX), X2
+f30f5311|223344556677885f5f5f5f5f 32 plan9 RCPSS 0(CX), X2
f30f5311|223344556677885f5f5f5f5f 64 gnu rcpss (%rcx),%xmm2
f30f5311|223344556677885f5f5f5f5f 64 intel rcpss xmm2, dword ptr [rcx]
-f30f5311|223344556677885f5f5f5f5f 64 plan9 REP RCPSS 0(CX), X2
+f30f5311|223344556677885f5f5f5f5f 64 plan9 RCPSS 0(CX), X2
f30f5811|223344556677885f5f5f5f5f 32 intel addss xmm2, dword ptr [ecx]
-f30f5811|223344556677885f5f5f5f5f 32 plan9 REP ADDSS 0(CX), X2
+f30f5811|223344556677885f5f5f5f5f 32 plan9 ADDSS 0(CX), X2
f30f5811|223344556677885f5f5f5f5f 64 gnu addss (%rcx),%xmm2
f30f5811|223344556677885f5f5f5f5f 64 intel addss xmm2, dword ptr [rcx]
-f30f5811|223344556677885f5f5f5f5f 64 plan9 REP ADDSS 0(CX), X2
+f30f5811|223344556677885f5f5f5f5f 64 plan9 ADDSS 0(CX), X2
f30f5911|223344556677885f5f5f5f5f 32 intel mulss xmm2, dword ptr [ecx]
-f30f5911|223344556677885f5f5f5f5f 32 plan9 REP MULSS 0(CX), X2
+f30f5911|223344556677885f5f5f5f5f 32 plan9 MULSS 0(CX), X2
f30f5911|223344556677885f5f5f5f5f 64 gnu mulss (%rcx),%xmm2
f30f5911|223344556677885f5f5f5f5f 64 intel mulss xmm2, dword ptr [rcx]
-f30f5911|223344556677885f5f5f5f5f 64 plan9 REP MULSS 0(CX), X2
+f30f5911|223344556677885f5f5f5f5f 64 plan9 MULSS 0(CX), X2
f30f5a11|223344556677885f5f5f5f5f 32 intel cvtss2sd xmm2, dword ptr [ecx]
-f30f5a11|223344556677885f5f5f5f5f 32 plan9 REP CVTSS2SD 0(CX), X2
+f30f5a11|223344556677885f5f5f5f5f 32 plan9 CVTSS2SD 0(CX), X2
f30f5a11|223344556677885f5f5f5f5f 64 gnu cvtss2sd (%rcx),%xmm2
f30f5a11|223344556677885f5f5f5f5f 64 intel cvtss2sd xmm2, dword ptr [rcx]
-f30f5a11|223344556677885f5f5f5f5f 64 plan9 REP CVTSS2SD 0(CX), X2
+f30f5a11|223344556677885f5f5f5f5f 64 plan9 CVTSS2SD 0(CX), X2
f30f5b11|223344556677885f5f5f5f5f 32 intel cvttps2dq xmm2, xmmword ptr [ecx]
-f30f5b11|223344556677885f5f5f5f5f 32 plan9 REP CVTTPS2DQ 0(CX), X2
+f30f5b11|223344556677885f5f5f5f5f 32 plan9 CVTTPS2DQ 0(CX), X2
f30f5b11|223344556677885f5f5f5f5f 64 gnu cvttps2dq (%rcx),%xmm2
f30f5b11|223344556677885f5f5f5f5f 64 intel cvttps2dq xmm2, xmmword ptr [rcx]
-f30f5b11|223344556677885f5f5f5f5f 64 plan9 REP CVTTPS2DQ 0(CX), X2
+f30f5b11|223344556677885f5f5f5f5f 64 plan9 CVTTPS2DQ 0(CX), X2
f30f5c11|223344556677885f5f5f5f5f 32 intel subss xmm2, dword ptr [ecx]
-f30f5c11|223344556677885f5f5f5f5f 32 plan9 REP SUBSS 0(CX), X2
+f30f5c11|223344556677885f5f5f5f5f 32 plan9 SUBSS 0(CX), X2
f30f5c11|223344556677885f5f5f5f5f 64 gnu subss (%rcx),%xmm2
f30f5c11|223344556677885f5f5f5f5f 64 intel subss xmm2, dword ptr [rcx]
-f30f5c11|223344556677885f5f5f5f5f 64 plan9 REP SUBSS 0(CX), X2
+f30f5c11|223344556677885f5f5f5f5f 64 plan9 SUBSS 0(CX), X2
f30f5d11|223344556677885f5f5f5f5f 32 intel minss xmm2, dword ptr [ecx]
-f30f5d11|223344556677885f5f5f5f5f 32 plan9 REP MINSS 0(CX), X2
+f30f5d11|223344556677885f5f5f5f5f 32 plan9 MINSS 0(CX), X2
f30f5d11|223344556677885f5f5f5f5f 64 gnu minss (%rcx),%xmm2
f30f5d11|223344556677885f5f5f5f5f 64 intel minss xmm2, dword ptr [rcx]
-f30f5d11|223344556677885f5f5f5f5f 64 plan9 REP MINSS 0(CX), X2
+f30f5d11|223344556677885f5f5f5f5f 64 plan9 MINSS 0(CX), X2
f30f5e11|223344556677885f5f5f5f5f 32 intel divss xmm2, dword ptr [ecx]
-f30f5e11|223344556677885f5f5f5f5f 32 plan9 REP DIVSS 0(CX), X2
+f30f5e11|223344556677885f5f5f5f5f 32 plan9 DIVSS 0(CX), X2
f30f5e11|223344556677885f5f5f5f5f 64 gnu divss (%rcx),%xmm2
f30f5e11|223344556677885f5f5f5f5f 64 intel divss xmm2, dword ptr [rcx]
-f30f5e11|223344556677885f5f5f5f5f 64 plan9 REP DIVSS 0(CX), X2
+f30f5e11|223344556677885f5f5f5f5f 64 plan9 DIVSS 0(CX), X2
f30f5f11|223344556677885f5f5f5f5f 32 intel maxss xmm2, dword ptr [ecx]
-f30f5f11|223344556677885f5f5f5f5f 32 plan9 REP MAXSS 0(CX), X2
+f30f5f11|223344556677885f5f5f5f5f 32 plan9 MAXSS 0(CX), X2
f30f5f11|223344556677885f5f5f5f5f 64 gnu maxss (%rcx),%xmm2
f30f5f11|223344556677885f5f5f5f5f 64 intel maxss xmm2, dword ptr [rcx]
-f30f5f11|223344556677885f5f5f5f5f 64 plan9 REP MAXSS 0(CX), X2
+f30f5f11|223344556677885f5f5f5f5f 64 plan9 MAXSS 0(CX), X2
f30f6f11|223344556677885f5f5f5f5f 32 intel movdqu xmm2, xmmword ptr [ecx]
-f30f6f11|223344556677885f5f5f5f5f 32 plan9 REP MOVDQU 0(CX), X2
+f30f6f11|223344556677885f5f5f5f5f 32 plan9 MOVDQU 0(CX), X2
f30f6f11|223344556677885f5f5f5f5f 64 gnu movdqu (%rcx),%xmm2
f30f6f11|223344556677885f5f5f5f5f 64 intel movdqu xmm2, xmmword ptr [rcx]
-f30f6f11|223344556677885f5f5f5f5f 64 plan9 REP MOVDQU 0(CX), X2
+f30f6f11|223344556677885f5f5f5f5f 64 plan9 MOVDQU 0(CX), X2
f30f701122|3344556677885f5f5f5f5f 32 intel pshufhw xmm2, xmmword ptr [ecx], 0x22
-f30f701122|3344556677885f5f5f5f5f 32 plan9 REP PSHUFHW $0x22, 0(CX), X2
+f30f701122|3344556677885f5f5f5f5f 32 plan9 PSHUFHW $0x22, 0(CX), X2
f30f701122|3344556677885f5f5f5f5f 64 gnu pshufhw $0x22,(%rcx),%xmm2
f30f701122|3344556677885f5f5f5f5f 64 intel pshufhw xmm2, xmmword ptr [rcx], 0x22
-f30f701122|3344556677885f5f5f5f5f 64 plan9 REP PSHUFHW $0x22, 0(CX), X2
+f30f701122|3344556677885f5f5f5f5f 64 plan9 PSHUFHW $0x22, 0(CX), X2
f30f7e11|223344556677885f5f5f5f5f 32 intel movq xmm2, qword ptr [ecx]
-f30f7e11|223344556677885f5f5f5f5f 32 plan9 REP MOVQ 0(CX), X2
+f30f7e11|223344556677885f5f5f5f5f 32 plan9 MOVQ 0(CX), X2
f30f7e11|223344556677885f5f5f5f5f 64 gnu movq (%rcx),%xmm2
f30f7e11|223344556677885f5f5f5f5f 64 intel movq xmm2, qword ptr [rcx]
-f30f7e11|223344556677885f5f5f5f5f 64 plan9 REP MOVQ 0(CX), X2
+f30f7e11|223344556677885f5f5f5f5f 64 plan9 MOVQ 0(CX), X2
f30f7f11|223344556677885f5f5f5f5f 32 intel movdqu xmmword ptr [ecx], xmm2
-f30f7f11|223344556677885f5f5f5f5f 32 plan9 REP MOVDQU X2, 0(CX)
+f30f7f11|223344556677885f5f5f5f5f 32 plan9 MOVDQU X2, 0(CX)
f30f7f11|223344556677885f5f5f5f5f 64 gnu movdqu %xmm2,(%rcx)
f30f7f11|223344556677885f5f5f5f5f 64 intel movdqu xmmword ptr [rcx], xmm2
-f30f7f11|223344556677885f5f5f5f5f 64 plan9 REP MOVDQU X2, 0(CX)
+f30f7f11|223344556677885f5f5f5f5f 64 plan9 MOVDQU X2, 0(CX)
f30fae11|223344556677885f5f5f5f5f 64 gnu wrfsbasel (%rcx)
f30fae11|223344556677885f5f5f5f5f 64 intel wrfsbase dword ptr [rcx]
-f30fae11|223344556677885f5f5f5f5f 64 plan9 REP WRFSBASE 0(CX)
+f30fae11|223344556677885f5f5f5f5f 64 plan9 WRFSBASE 0(CX)
f30fae18|11223344556677885f5f5f5f 64 gnu wrgsbasel (%rax)
f30fae18|11223344556677885f5f5f5f 64 intel wrgsbase dword ptr [rax]
-f30fae18|11223344556677885f5f5f5f 64 plan9 REP WRGSBASE 0(AX)
+f30fae18|11223344556677885f5f5f5f 64 plan9 WRGSBASE 0(AX)
f30faec0|11223344556677885f5f5f5f 64 gnu rdfsbase %eax
f30faec0|11223344556677885f5f5f5f 64 intel rdfsbase eax
-f30faec0|11223344556677885f5f5f5f 64 plan9 REP RDFSBASE AX
+f30faec0|11223344556677885f5f5f5f 64 plan9 RDFSBASE AX
f30faec8|11223344556677885f5f5f5f 64 gnu rdgsbase %eax
f30faec8|11223344556677885f5f5f5f 64 intel rdgsbase eax
-f30faec8|11223344556677885f5f5f5f 64 plan9 REP RDGSBASE AX
+f30faec8|11223344556677885f5f5f5f 64 plan9 RDGSBASE AX
f30fb811|223344556677885f5f5f5f5f 32 intel popcnt edx, dword ptr [ecx]
-f30fb811|223344556677885f5f5f5f5f 32 plan9 REP POPCNT 0(CX), DX
+f30fb811|223344556677885f5f5f5f5f 32 plan9 POPCNT 0(CX), DX
f30fb811|223344556677885f5f5f5f5f 64 gnu popcnt (%rcx),%edx
f30fb811|223344556677885f5f5f5f5f 64 intel popcnt edx, dword ptr [rcx]
-f30fb811|223344556677885f5f5f5f5f 64 plan9 REP POPCNT 0(CX), DX
+f30fb811|223344556677885f5f5f5f5f 64 plan9 POPCNT 0(CX), DX
f30fbc11|223344556677885f5f5f5f5f 32 intel tzcnt edx, dword ptr [ecx]
-f30fbc11|223344556677885f5f5f5f5f 32 plan9 REP TZCNT 0(CX), DX
+f30fbc11|223344556677885f5f5f5f5f 32 plan9 TZCNT 0(CX), DX
f30fbc11|223344556677885f5f5f5f5f 64 gnu tzcnt (%rcx),%edx
f30fbc11|223344556677885f5f5f5f5f 64 intel tzcnt edx, dword ptr [rcx]
-f30fbc11|223344556677885f5f5f5f5f 64 plan9 REP TZCNT 0(CX), DX
+f30fbc11|223344556677885f5f5f5f5f 64 plan9 TZCNT 0(CX), DX
f30fbd11|223344556677885f5f5f5f5f 32 intel lzcnt edx, dword ptr [ecx]
-f30fbd11|223344556677885f5f5f5f5f 32 plan9 REP LZCNT 0(CX), DX
+f30fbd11|223344556677885f5f5f5f5f 32 plan9 LZCNT 0(CX), DX
f30fbd11|223344556677885f5f5f5f5f 64 gnu lzcnt (%rcx),%edx
f30fbd11|223344556677885f5f5f5f5f 64 intel lzcnt edx, dword ptr [rcx]
-f30fbd11|223344556677885f5f5f5f5f 64 plan9 REP LZCNT 0(CX), DX
+f30fbd11|223344556677885f5f5f5f5f 64 plan9 LZCNT 0(CX), DX
f30fc21122|3344556677885f5f5f5f5f 32 intel cmpss xmm2, dword ptr [ecx], 0x22
-f30fc21122|3344556677885f5f5f5f5f 32 plan9 REP CMPSS $0x22, 0(CX), X2
+f30fc21122|3344556677885f5f5f5f5f 32 plan9 CMPSS $0x22, 0(CX), X2
f30fc21122|3344556677885f5f5f5f5f 64 gnu cmpss $0x22,(%rcx),%xmm2
f30fc21122|3344556677885f5f5f5f5f 64 intel cmpss xmm2, dword ptr [rcx], 0x22
-f30fc21122|3344556677885f5f5f5f5f 64 plan9 REP CMPSS $0x22, 0(CX), X2
+f30fc21122|3344556677885f5f5f5f5f 64 plan9 CMPSS $0x22, 0(CX), X2
f30fe611|223344556677885f5f5f5f5f 32 intel cvtdq2pd xmm2, qword ptr [ecx]
-f30fe611|223344556677885f5f5f5f5f 32 plan9 REP CVTDQ2PD 0(CX), X2
+f30fe611|223344556677885f5f5f5f5f 32 plan9 CVTDQ2PD 0(CX), X2
f30fe611|223344556677885f5f5f5f5f 64 gnu cvtdq2pd (%rcx),%xmm2
f30fe611|223344556677885f5f5f5f5f 64 intel cvtdq2pd xmm2, qword ptr [rcx]
-f30fe611|223344556677885f5f5f5f5f 64 plan9 REP CVTDQ2PD 0(CX), X2
+f30fe611|223344556677885f5f5f5f5f 64 plan9 CVTDQ2PD 0(CX), X2
f3480f2a11|223344556677885f5f5f5f 64 gnu cvtsi2ssq (%rcx),%xmm2
f3480f2a11|223344556677885f5f5f5f 64 intel cvtsi2ss xmm2, qword ptr [rcx]
-f3480f2a11|223344556677885f5f5f5f 64 plan9 REP CVTSI2SSQ 0(CX), X2
+f3480f2a11|223344556677885f5f5f5f 64 plan9 CVTSI2SSQ 0(CX), X2
f3480f2c11|223344556677885f5f5f5f 64 gnu cvttss2si (%rcx),%rdx
f3480f2c11|223344556677885f5f5f5f 64 intel cvttss2si rdx, dword ptr [rcx]
-f3480f2c11|223344556677885f5f5f5f 64 plan9 REP CVTTSS2SIL 0(CX), DX
+f3480f2c11|223344556677885f5f5f5f 64 plan9 CVTTSS2SIL 0(CX), DX
f3480f2d11|223344556677885f5f5f5f 64 gnu cvtss2si (%rcx),%rdx
f3480f2d11|223344556677885f5f5f5f 64 intel cvtss2si rdx, dword ptr [rcx]
-f3480f2d11|223344556677885f5f5f5f 64 plan9 REP CVTSS2SIL 0(CX), DX
+f3480f2d11|223344556677885f5f5f5f 64 plan9 CVTSS2SIL 0(CX), DX
f3480fae11|223344556677885f5f5f5f 64 gnu wrfsbaseq (%rcx)
f3480fae11|223344556677885f5f5f5f 64 intel wrfsbase qword ptr [rcx]
-f3480fae11|223344556677885f5f5f5f 64 plan9 REP WRFSBASE 0(CX)
+f3480fae11|223344556677885f5f5f5f 64 plan9 WRFSBASE 0(CX)
f3480fae18|11223344556677885f5f5f 64 gnu wrgsbaseq (%rax)
f3480fae18|11223344556677885f5f5f 64 intel wrgsbase qword ptr [rax]
-f3480fae18|11223344556677885f5f5f 64 plan9 REP WRGSBASE 0(AX)
+f3480fae18|11223344556677885f5f5f 64 plan9 WRGSBASE 0(AX)
f3480faec0|11223344556677885f5f5f 64 gnu rdfsbase %rax
f3480faec0|11223344556677885f5f5f 64 intel rdfsbase rax
-f3480faec0|11223344556677885f5f5f 64 plan9 REP RDFSBASE AX
+f3480faec0|11223344556677885f5f5f 64 plan9 RDFSBASE AX
f3480faec8|11223344556677885f5f5f 64 gnu rdgsbase %rax
f3480faec8|11223344556677885f5f5f 64 intel rdgsbase rax
-f3480faec8|11223344556677885f5f5f 64 plan9 REP RDGSBASE AX
+f3480faec8|11223344556677885f5f5f 64 plan9 RDGSBASE AX
f3480fb811|223344556677885f5f5f5f 64 gnu popcnt (%rcx),%rdx
f3480fb811|223344556677885f5f5f5f 64 intel popcnt rdx, qword ptr [rcx]
-f3480fb811|223344556677885f5f5f5f 64 plan9 REP POPCNT 0(CX), DX
+f3480fb811|223344556677885f5f5f5f 64 plan9 POPCNT 0(CX), DX
f3480fbc11|223344556677885f5f5f5f 64 gnu tzcnt (%rcx),%rdx
f3480fbc11|223344556677885f5f5f5f 64 intel tzcnt rdx, qword ptr [rcx]
-f3480fbc11|223344556677885f5f5f5f 64 plan9 REP TZCNT 0(CX), DX
+f3480fbc11|223344556677885f5f5f5f 64 plan9 TZCNT 0(CX), DX
f3480fbd11|223344556677885f5f5f5f 64 gnu lzcnt (%rcx),%rdx
f3480fbd11|223344556677885f5f5f5f 64 intel lzcnt rdx, qword ptr [rcx]
-f3480fbd11|223344556677885f5f5f5f 64 plan9 REP LZCNT 0(CX), DX
+f3480fbd11|223344556677885f5f5f5f 64 plan9 LZCNT 0(CX), DX
f3660fb811|223344556677885f5f5f5f 32 intel popcnt dx, word ptr [ecx]
f3660fb811|223344556677885f5f5f5f 32 plan9 POPCNT 0(CX), DX
f3660fb811|223344556677885f5f5f5f 64 gnu popcnt (%rcx),%dx
@@ -6573,15 +6573,15 @@
f3660fbd11|223344556677885f5f5f5f 64 intel lzcnt dx, word ptr [rcx]
f3660fbd11|223344556677885f5f5f5f 64 plan9 LZCNT 0(CX), DX
f3f0673e660f38f111|22334455667788 32 intel lock movbe word ptr [bx+di*1], dx
-f3f0673e660f38f111|22334455667788 32 plan9 MOVBE DX, DS:0(BX)(DI*1)
+f3f0673e660f38f111|22334455667788 32 plan9 REP; MOVBE DX, DS:0(BX)(DI*1)
f3f0673e660f38f111|22334455667788 64 gnu rep lock movbe %dx,%ds:(%ecx)
f3f0673e660f38f111|22334455667788 64 intel lock movbe word ptr [ecx], dx
-f3f0673e660f38f111|22334455667788 64 plan9 MOVBE DX, 0(CX)
+f3f0673e660f38f111|22334455667788 64 plan9 REP; MOVBE DX, 0(CX)
f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 32 intel movntsd qword ptr [ecx], xmm2
-f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 32 plan9 REPNE MOVNTSD X2, 0(CX)
+f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 32 plan9 REP; MOVNTSD X2, 0(CX)
f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 gnu repn movntss %xmm2,(%rcx)
f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 intel movntsd qword ptr [rcx], xmm2
-f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 plan9 REPNE MOVNTSD X2, 0(CX)
+f3f20f2b11|5f5f5f5f5f5f5f5f5f5f5f 64 plan9 REP; MOVNTSD X2, 0(CX)
f4|11223344556677885f5f5f5f5f5f5f 32 intel hlt
f4|11223344556677885f5f5f5f5f5f5f 32 plan9 HLT
f4|11223344556677885f5f5f5f5f5f5f 64 gnu hlt
@@ -6740,3 +6740,32 @@
c57d7ff7|44556677885f5f5f5f5f5f5f 64 intel vmovdqa ymm7, ymm14
c57d7ff7|44556677885f5f5f5f5f5f5f 64 plan9 VMOVDQA X14, X7
c57d7ff7|44556677885f5f5f5f5f5f5f 64 gnu vmovdqa %ymm14,%ymm7
+66f3ab|223344556677885f5f5f5f5f5f 64 gnu rep stos %ax,%es:(%rdi)
+66f3ab|223344556677885f5f5f5f5f5f 64 intel rep stosw word ptr [rdi]
+66f3ab|223344556677885f5f5f5f5f5f 64 plan9 REP; STOSW AX, ES:0(DI)
+f348a5|223344556677885f5f5f5f5f5f 64 gnu rep movsq %ds:(%rsi),%es:(%rdi)
+f348a5|223344556677885f5f5f5f5f5f 64 intel rep movsq qword ptr [rdi], qword ptr [rsi]
+f348a5|223344556677885f5f5f5f5f5f 64 plan9 REP; MOVSQ DS:0(SI), ES:0(DI)
+f348ab|223344556677885f5f5f5f5f5f 64 gnu rep stos %rax,%es:(%rdi)
+f348ab|223344556677885f5f5f5f5f5f 64 intel rep stosq qword ptr [rdi]
+f348ab|223344556677885f5f5f5f5f5f 64 plan9 REP; STOSQ AX, ES:0(DI)
+f3a4|11223344556677885f5f5f5f5f5f 32 gnu rep movsb %ds:(%esi),%es:(%edi)
+f3a4|11223344556677885f5f5f5f5f5f 32 gnu rep movsb %ds:(%esi),%es:(%edi)
+f3a4|11223344556677885f5f5f5f5f5f 32 intel rep movsb byte ptr [edi], byte ptr [esi]
+f3a4|11223344556677885f5f5f5f5f5f 32 plan9 REP; MOVSB DS:0(SI), ES:0(DI)
+f3a4|11223344556677885f5f5f5f5f5f 64 gnu rep movsb %ds:(%rsi),%es:(%rdi)
+f3a4|11223344556677885f5f5f5f5f5f 64 intel rep movsb byte ptr [rdi], byte ptr [rsi]
+f3a4|11223344556677885f5f5f5f5f5f 64 plan9 REP; MOVSB DS:0(SI), ES:0(DI)
+f3a5|11223344556677885f5f5f5f5f5f 32 gnu rep movsl %ds:(%esi),%es:(%edi)
+f3a5|11223344556677885f5f5f5f5f5f 32 intel rep movsd dword ptr [edi], dword ptr [esi]
+f3a5|11223344556677885f5f5f5f5f5f 32 plan9 REP; MOVSD DS:0(SI), ES:0(DI)
+f3a5|11223344556677885f5f5f5f5f5f 64 gnu rep movsl %ds:(%rsi),%es:(%rdi)
+f3a5|11223344556677885f5f5f5f5f5f 64 intel rep movsd dword ptr [rdi], dword ptr [rsi]
+f3a5|11223344556677885f5f5f5f5f5f 64 plan9 REP; MOVSD DS:0(SI), ES:0(DI)
+f3a6|11223344556677885f5f5f5f5f5f 64 gnu rep cmpsb %es:(%rdi),%ds:(%rsi)
+f3a6|11223344556677885f5f5f5f5f5f 64 intel rep cmpsb byte ptr [rsi], byte ptr [rdi]
+f3a6|11223344556677885f5f5f5f5f5f 64 plan9 REP; CMPSB ES:0(DI), DS:0(SI)
+f3ab|11223344556677885f5f5f5f5f5f 32 gnu rep stos %eax,%es:(%edi)
+f3ab|11223344556677885f5f5f5f5f5f 32 intel rep stosd dword ptr [edi]
+f3ab|11223344556677885f5f5f5f5f5f 32 plan9 REP; STOSD AX, ES:0(DI)
+f201c1|223344556677885f5f5f5f5f5f 64 plan9 REPNE; ADDL AX, CX
