arm64/arm64asm/inst.json

[{"Name":"ADC","Bits":"0|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADC <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"ADC","Bits":"1|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADC <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"ADCS","Bits":"0|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADCS <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"ADCS","Bits":"1|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADCS <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"ADD (extended register)","Bits":"0|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":""},
{"Name":"ADD (extended register)","Bits":"1|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":""},
{"Name":"ADD (immediate)","Bits":"0|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."},
{"Name":"ADD (immediate)","Bits":"1|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."},
{"Name":"ADD (shifted register)","Bits":"0|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"ADD (shifted register)","Bits":"1|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"ADDS (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."},
{"Name":"ADDS (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."},
{"Name":"ADDS (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."},
{"Name":"ADDS (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."},
{"Name":"ADDS (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."},
{"Name":"ADDS (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."},
{"Name":"ADR","Bits":"0|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADR <Xd>, <label>","Code":"","Alias":""},
{"Name":"ADRP","Bits":"1|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADRP <Xd>, <label>","Code":"","Alias":""},
{"Name":"AND (immediate)","Bits":"0|0|0|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"AND <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":""},
{"Name":"AND (immediate)","Bits":"1|0|0|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"AND <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":""},
{"Name":"AND (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"AND (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"ANDS (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},
{"Name":"ANDS (immediate)","Bits":"1|1|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ANDS <Xd>, <Xn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},
{"Name":"ANDS (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias TST (shifted register)."},
{"Name":"ANDS (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias TST (shifted register)."},
{"Name":"ASR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the ASRV instruction."},
{"Name":"ASR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the ASRV instruction."},
{"Name":"ASR (immediate)","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|011111:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASR <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"ASR (immediate)","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|111111:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASR <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"ASRV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASRV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias ASR (register)."},
{"Name":"ASRV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASRV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias ASR (register)."},
{"Name":"AT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"AT <at_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
{"Name":"B.cond","Bits":"0|1|0|1|0|1|0|0|imm19:19|0|cond:4","Arch":"19-bit signed PC-relative branch offset variant","Syntax":"B.<cond> <label>","Code":"","Alias":""},
{"Name":"B","Bits":"0|0|0|1|0|1|imm26:26","Arch":"26-bit signed PC-relative branch offset variant","Syntax":"B <label>","Code":"","Alias":""},
{"Name":"BFI","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFI <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
{"Name":"BFI","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFI <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
{"Name":"BFM","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
{"Name":"BFM","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
{"Name":"BFXIL","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFXIL <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
{"Name":"BFXIL","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFXIL <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
{"Name":"BIC (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"BIC (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"BICS (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"BICS (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"BL","Bits":"1|0|0|1|0|1|imm26:26","Arch":"26-bit signed PC-relative branch offset variant","Syntax":"BL <label>","Code":"","Alias":""},
{"Name":"BLR","Bits":"1|1|0|1|0|1|1|0|0|0|1|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"BLR <Xn>","Code":"","Alias":""},
{"Name":"BR","Bits":"1|1|0|1|0|1|1|0|0|0|0|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"BR <Xn>","Code":"","Alias":""},
{"Name":"BRK","Bits":"1|1|0|1|0|1|0|0|0|0|1|imm16:16|0|0|0|0|0","Arch":"System variant","Syntax":"BRK #<imm>","Code":"","Alias":""},
{"Name":"CBNZ","Bits":"0|0|1|1|0|1|0|1|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"CBNZ <Wt>, <label>","Code":"","Alias":""},
{"Name":"CBNZ","Bits":"1|0|1|1|0|1|0|1|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"CBNZ <Xt>, <label>","Code":"","Alias":""},
{"Name":"CBZ","Bits":"0|0|1|1|0|1|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"CBZ <Wt>, <label>","Code":"","Alias":""},
{"Name":"CBZ","Bits":"1|0|1|1|0|1|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"CBZ <Xt>, <label>","Code":"","Alias":""},
{"Name":"CCMN (immediate)","Bits":"0|0|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMN <Wn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMN (immediate)","Bits":"1|0|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMN <Xn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMN (register)","Bits":"0|0|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMN <Wn>, <Wm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMN (register)","Bits":"1|0|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMN <Xn>, <Xm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMP (immediate)","Bits":"0|1|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMP <Wn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMP (immediate)","Bits":"1|1|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMP <Xn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMP (register)","Bits":"0|1|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMP <Wn>, <Wm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CCMP (register)","Bits":"1|1|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMP <Xn>, <Xm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"CINC","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CINC <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
{"Name":"CINC","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CINC <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
{"Name":"CINV","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CINV <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
{"Name":"CINV","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CINV <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
{"Name":"CLREX","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|0|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"CLREX {#<imm>}","Code":"","Alias":""},
{"Name":"CLS","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CLS <Wd>, <Wn>","Code":"","Alias":""},
{"Name":"CLS","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CLS <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"CLZ","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CLZ <Wd>, <Wn>","Code":"","Alias":""},
{"Name":"CLZ","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CLZ <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"CMN (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the ADDS (extended register) instruction."},
{"Name":"CMN (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the ADDS (extended register) instruction."},
{"Name":"CMN (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the ADDS (immediate) instruction."},
{"Name":"CMN (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the ADDS (immediate) instruction."},
{"Name":"CMN (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ADDS (shifted register) instruction."},
{"Name":"CMN (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ADDS (shifted register) instruction."},
{"Name":"CMP (extended register)","Bits":"0|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the SUBS (extended register) instruction."},
{"Name":"CMP (extended register)","Bits":"1|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the SUBS (extended register) instruction."},
{"Name":"CMP (immediate)","Bits":"0|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the SUBS (immediate) instruction."},
{"Name":"CMP (immediate)","Bits":"1|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the SUBS (immediate) instruction."},
{"Name":"CMP (shifted register)","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
{"Name":"CMP (shifted register)","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
{"Name":"CNEG","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CNEG <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSNEG instruction."},
{"Name":"CNEG","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CNEG <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSNEG instruction."},
{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|00:2|Rn:5|Rd:5","Arch":"CRC32B variant","Syntax":"CRC32B <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|01:2|Rn:5|Rd:5","Arch":"CRC32H variant","Syntax":"CRC32H <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|10:2|Rn:5|Rd:5","Arch":"CRC32W variant","Syntax":"CRC32W <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|11:2|Rn:5|Rd:5","Arch":"CRC32X variant","Syntax":"CRC32X <Wd>, <Wn>, <Xm>","Code":"","Alias":""},
{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|00:2|Rn:5|Rd:5","Arch":"CRC32CB variant","Syntax":"CRC32CB <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|01:2|Rn:5|Rd:5","Arch":"CRC32CH variant","Syntax":"CRC32CH <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|10:2|Rn:5|Rd:5","Arch":"CRC32CW variant","Syntax":"CRC32CW <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|11:2|Rn:5|Rd:5","Arch":"CRC32CX variant","Syntax":"CRC32CX <Wd>, <Wn>, <Xm>","Code":"","Alias":""},
{"Name":"CSEL","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSEL <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":""},
{"Name":"CSEL","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSEL <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":""},
{"Name":"CSET","Bits":"0|0|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|1|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"CSET <Wd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
{"Name":"CSET","Bits":"1|0|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|1|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"CSET <Xd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
{"Name":"CSETM","Bits":"0|1|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"CSETM <Wd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
{"Name":"CSETM","Bits":"1|1|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"CSETM <Xd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
{"Name":"CSINC","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSINC <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINC and CSET."},
{"Name":"CSINC","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSINC <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINC and CSET."},
{"Name":"CSINV","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSINV <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINV and CSETM."},
{"Name":"CSINV","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSINV <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINV and CSETM."},
{"Name":"CSNEG","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSNEG <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the alias CNEG."},
{"Name":"CSNEG","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSNEG <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the alias CNEG."},
{"Name":"DC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"DC <dc_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
{"Name":"DCPS1","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"DCPS1 {#<imm>}","Code":"","Alias":""},
{"Name":"DCPS2","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"DCPS2 {#<imm>}","Code":"","Alias":""},
{"Name":"DCPS3","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"DCPS3 {#<imm>}","Code":"","Alias":""},
{"Name":"DMB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"DMB <option>|#<imm>","Code":"","Alias":""},
{"Name":"DRPS","Bits":"1|1|0|1|0|1|1|0|1|0|1|1|1|1|1|1|0|0|0|0|0|0|1|1|1|1|1|0|0|0|0|0","Arch":"System variant","Syntax":"DRPS","Code":"","Alias":""},
{"Name":"DSB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"DSB <option>|#<imm>","Code":"","Alias":""},
{"Name":"EON (shifted register)","Bits":"0|1|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"EON (shifted register)","Bits":"1|1|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"EOR (immediate)","Bits":"0|1|0|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EOR <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":""},
{"Name":"EOR (immediate)","Bits":"1|1|0|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EOR <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":""},
{"Name":"EOR (shifted register)","Bits":"0|1|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"EOR (shifted register)","Bits":"1|1|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
{"Name":"ERET","Bits":"1|1|0|1|0|1|1|0|1|0|0|1|1|1|1|1|0|0|0|0|0|0|1|1|1|1|1|0|0|0|0|0","Arch":"System variant","Syntax":"ERET","Code":"","Alias":""},
{"Name":"EXTR","Bits":"0|0|0|1|0|0|1|1|1|0|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EXTR <Wd>, <Wn>, <Wm>, #<lsb>","Code":"","Alias":"This instruction is used by the alias ROR (immediate)."},
{"Name":"EXTR","Bits":"1|0|0|1|0|0|1|1|1|1|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EXTR <Xd>, <Xn>, <Xm>, #<lsb>","Code":"","Alias":"This instruction is used by the alias ROR (immediate)."},
{"Name":"HINT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0000:4|op2:3|1|1|1|1|1","Arch":"Hints 6 and 7 variant","Syntax":"HINT #<imm>","Code":"","Alias":""},
{"Name":"HINT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|CRm:4|op2:3|1|1|1|1|1","Arch":"Hints 8 to 127 variant","Syntax":"HINT #<imm>","Code":"","Alias":""},
{"Name":"HLT","Bits":"1|1|0|1|0|1|0|0|0|1|0|imm16:16|0|0|0|0|0","Arch":"System variant","Syntax":"HLT #<imm>","Code":"","Alias":""},
{"Name":"HVC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"HVC #<imm>","Code":"","Alias":""},
{"Name":"IC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"IC <ic_op>{, <Xt>}","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
{"Name":"ISB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"ISB {<option>|#<imm>}","Code":"","Alias":""},
{"Name":"LDAR","Bits":"10:2|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAR","Bits":"11:2|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDARB","Bits":"0|0|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDARB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDARH","Bits":"0|1|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDARH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAXP","Bits":"1|0|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|1|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAXP","Bits":"1|1|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|1|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAXR","Bits":"10:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAXR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAXR","Bits":"11:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAXR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAXRB","Bits":"0|0|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDAXRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDAXRH","Bits":"0|1|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDAXRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDNP","Bits":"00:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDNP","Bits":"10:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDP","Bits":"00:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"LDP","Bits":"10:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset Signed offset variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (literal)","Bits":"00:2|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"LDR <Wt>, <label>","Code":"","Alias":""},
{"Name":"LDR (literal)","Bits":"01:2|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Xt>, <label>","Code":"","Alias":""},
{"Name":"LDR (register)","Bits":"10:2|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDR (register)","Bits":"11:2|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
{"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRH (register)","Bits":"0|1|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit with extended register offset variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|11:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit with shifted register offset variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit with extended register offset variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|10:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit with shifted register offset variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRSH (register)","Bits":"0|1|1|1|1|0|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDRSH (register)","Bits":"0|1|1|1|1|0|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRSW <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRSW <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|1|1|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDRSW (literal)","Bits":"1|0|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"Literal variant","Syntax":"LDRSW <Xt>, <label>","Code":"","Alias":""},
{"Name":"LDRSW (register)","Bits":"1|0|1|1|1|0|0|0|1|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDTR","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTR","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRB","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRH","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRSB","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTRSB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRSB","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTRSB <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRSH","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTRSH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRSH","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTRSH <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDTRSW","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRSW <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDUR","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDUR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDUR","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDUR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURB","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURH","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURSB","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDURSB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURSB","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDURSB <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURSH","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDURSH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURSH","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDURSH <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDURSW","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURSW <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDXP","Bits":"1|0|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|0|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDXP","Bits":"1|1|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|0|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDXR","Bits":"10:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDXR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDXR","Bits":"11:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDXR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDXRB","Bits":"0|0|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDXRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LDXRH","Bits":"0|1|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDXRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"LSL (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSL <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSLV instruction."},
{"Name":"LSL (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSL <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the LSLV instruction."},
{"Name":"LSL (immediate)","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSL <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"LSL (immediate)","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSL <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"LSLV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSLV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias LSL (register)."},
{"Name":"LSLV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSLV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias LSL (register)."},
{"Name":"LSR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},
{"Name":"LSR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},
{"Name":"LSR (immediate)","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|011111:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"LSR (immediate)","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|111111:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSR <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"LSRV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSRV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias LSR (register)."},
{"Name":"LSRV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSRV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias LSR (register)."},
{"Name":"MADD","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MADD <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MUL."},
{"Name":"MADD","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MADD <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MUL."},
{"Name":"MNEG","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MNEG <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the MSUB instruction."},
{"Name":"MNEG","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MNEG <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the MSUB instruction."},
{"Name":"MOV (to/from SP)","Bits":"0|0|0|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd|WSP>, <Wn|WSP>","Code":"","Alias":"This instruction is an alias of the ADD (immediate) instruction."},
{"Name":"MOV (to/from SP)","Bits":"1|0|0|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd|SP>, <Xn|SP>","Code":"","Alias":"This instruction is an alias of the ADD (immediate) instruction."},
{"Name":"MOV (inverted wide immediate)","Bits":"0|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVN instruction."},
{"Name":"MOV (inverted wide immediate)","Bits":"1|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVN instruction."},
{"Name":"MOV (wide immediate)","Bits":"0|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVZ instruction."},
{"Name":"MOV (wide immediate)","Bits":"1|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVZ instruction."},
{"Name":"MOV (bitmask immediate)","Bits":"0|0|1|1|0|0|1|0|0|0|immr:6|imms:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd|WSP>, #<imm>","Code":"","Alias":"This instruction is an alias of the ORR (immediate) instruction."},
{"Name":"MOV (bitmask immediate)","Bits":"1|0|1|1|0|0|1|0|0|N|immr:6|imms:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd|SP>, #<imm>","Code":"","Alias":"This instruction is an alias of the ORR (immediate) instruction."},
{"Name":"MOV (register)","Bits":"0|0|1|0|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the ORR (shifted register) instruction."},
{"Name":"MOV (register)","Bits":"1|0|1|0|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the ORR (shifted register) instruction."},
{"Name":"MOVK","Bits":"0|1|1|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVK <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":""},
{"Name":"MOVK","Bits":"1|1|1|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVK <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":""},
{"Name":"MOVN","Bits":"0|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVN <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (inverted wide immediate)."},
{"Name":"MOVN","Bits":"1|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVN <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (inverted wide immediate)."},
{"Name":"MOVZ","Bits":"0|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVZ <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (wide immediate)."},
{"Name":"MOVZ","Bits":"1|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVZ <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (wide immediate)."},
{"Name":"MRS","Bits":"1|1|0|1|0|1|0|1|0|0|1|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MRS <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)","Code":"","Alias":""},
{"Name":"MSR (immediate)","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|op1:3|0|1|0|0|CRm:4|op2:3|1|1|1|1|1","Arch":"System variant","Syntax":"MSR <pstatefield>, #<imm>","Code":"","Alias":""},
{"Name":"MSR (register)","Bits":"1|1|0|1|0|1|0|1|0|0|0|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MSR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>","Code":"","Alias":""},
{"Name":"MSUB","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MSUB <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MNEG."},
{"Name":"MSUB","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MSUB <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MNEG."},
{"Name":"MUL","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MUL <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the MADD instruction."},
{"Name":"MUL","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MUL <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the MADD instruction."},
{"Name":"MVN","Bits":"0|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MVN <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ORN (shifted register) instruction."},
{"Name":"MVN","Bits":"1|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MVN <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ORN (shifted register) instruction."},
{"Name":"NEG (shifted register)","Bits":"0|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NEG <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUB (shifted register) instruction."},
{"Name":"NEG (shifted register)","Bits":"1|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NEG <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUB (shifted register) instruction."},
{"Name":"NEGS","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NEGS <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
{"Name":"NEGS","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NEGS <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
{"Name":"NGC","Bits":"0|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NGC <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the SBC instruction."},
{"Name":"NGC","Bits":"1|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NGC <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the SBC instruction."},
{"Name":"NGCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NGCS <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the SBCS instruction."},
{"Name":"NGCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NGCS <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the SBCS instruction."},
{"Name":"NOP","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"NOP","Code":"","Alias":""},
{"Name":"ORN (shifted register)","Bits":"0|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MVN."},
{"Name":"ORN (shifted register)","Bits":"1|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MVN."},
{"Name":"ORR (immediate)","Bits":"0|0|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias MOV (bitmask immediate)."},
{"Name":"ORR (immediate)","Bits":"1|0|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORR <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":"This instruction is used by the alias MOV (bitmask immediate)."},
{"Name":"ORR (shifted register)","Bits":"0|0|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MOV (register)."},
{"Name":"ORR (shifted register)","Bits":"1|0|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MOV (register)."},
{"Name":"PRFM (immediate)","Bits":"1|1|1|1|1|0|0|1|1|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset variant","Syntax":"PRFM (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"PRFM (literal)","Bits":"1|1|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"Literal variant","Syntax":"PRFM (<prfop>|#<imm5>), <label>","Code":"","Alias":""},
{"Name":"PRFM (register)","Bits":"1|1|1|1|1|0|0|0|1|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Integer variant","Syntax":"PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"PRFM (unscaled offset)","Bits":"1|1|1|1|1|0|0|0|1|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"PRFUM (<prfop>|#<imm5>), [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"RBIT","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"RBIT <Wd>, <Wn>","Code":"","Alias":""},
{"Name":"RBIT","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"RBIT <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"RET","Bits":"1|1|0|1|0|1|1|0|0|1|0|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"RET {<Xn>}","Code":"","Alias":""},
{"Name":"REV","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|10:2|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"REV <Wd>, <Wn>","Code":"","Alias":""},
{"Name":"REV","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|11:2|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"REV16","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"REV16 <Wd>, <Wn>","Code":"","Alias":""},
{"Name":"REV16","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV16 <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"REV32","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV32 <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"REV64","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV64 <Xd>, <Xn>","Code":"","Alias":""},
{"Name":"ROR (immediate)","Bits":"0|0|0|1|0|0|1|1|1|0|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ROR <Wd>, <Ws>, #<shift>","Code":"","Alias":"This instruction is an alias of the EXTR instruction."},
{"Name":"ROR (immediate)","Bits":"1|0|0|1|0|0|1|1|1|1|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ROR <Xd>, <Xs>, #<shift>","Code":"","Alias":"This instruction is an alias of the EXTR instruction."},
{"Name":"ROR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ROR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the RORV instruction."},
{"Name":"ROR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ROR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the RORV instruction."},
{"Name":"RORV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"RORV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias ROR (register)."},
{"Name":"RORV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"RORV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias ROR (register)."},
{"Name":"SBC","Bits":"0|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBC <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGC."},
{"Name":"SBC","Bits":"1|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBC <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGC."},
{"Name":"SBCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBCS <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
{"Name":"SBCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBCS <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
{"Name":"SBFIZ","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFIZ <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SBFIZ","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFIZ <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SBFM","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW."},
{"Name":"SBFM","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW."},
{"Name":"SBFX","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFX <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SBFX","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFX <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"SDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"SEV","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|1|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"SEV","Code":"","Alias":""},
{"Name":"SEVL","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|1|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"SEVL","Code":"","Alias":""},
{"Name":"SMADDL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMADDL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias SMULL."},
{"Name":"SMC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"SMC #<imm>","Code":"","Alias":""},
{"Name":"SMNEGL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the SMSUBL instruction."},
{"Name":"SMSUBL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias SMNEGL."},
{"Name":"SMULH","Bits":"1|0|0|1|1|0|1|1|0|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"SMULL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMULL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the SMADDL instruction."},
{"Name":"STLR","Bits":"10:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLR","Bits":"11:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLRB","Bits":"0|0|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLRH","Bits":"0|1|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXP","Bits":"1|0|0|0|1|0|0|0|0|0|1|Rs:5|1|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXP","Bits":"1|1|0|0|1|0|0|0|0|0|1|Rs:5|1|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXRB","Bits":"0|0|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXRH","Bits":"0|1|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STNP","Bits":"00:2|1|0|1|0|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STNP","Bits":"10:2|1|0|1|0|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STP","Bits":"00:2|1|0|1|0|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"STP","Bits":"10:2|1|0|1|0|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"STP","Bits":"00:2|1|0|1|0|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"STP","Bits":"10:2|1|0|1|0|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"STP","Bits":"00:2|1|0|1|0|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STP","Bits":"10:2|1|0|1|0|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (register)","Bits":"10:2|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STR (register)","Bits":"11:2|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"STRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"STRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"STRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STRB (register)","Bits":"0|0|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
{"Name":"STRB (register)","Bits":"0|0|1|1|1|0|0|0|0|0|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"STRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"STRH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"STRH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"STRH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STRH (register)","Bits":"0|1|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STTR","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STTR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STTR","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STTR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STTRB","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STTRB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STTRH","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STTRH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STUR","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STUR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STUR","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STUR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STURB","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STURB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STURH","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STURH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STXP","Bits":"1|0|0|0|1|0|0|0|0|0|1|Rs:5|0|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STXP","Bits":"1|1|0|0|1|0|0|0|0|0|1|Rs:5|0|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STXRB","Bits":"0|0|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STXRH","Bits":"0|1|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"SUB (extended register)","Bits":"0|1|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":""},
{"Name":"SUB (extended register)","Bits":"1|1|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":""},
{"Name":"SUB (immediate)","Bits":"0|1|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":""},
{"Name":"SUB (immediate)","Bits":"1|1|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":""},
{"Name":"SUB (shifted register)","Bits":"0|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias NEG (shifted register)."},
{"Name":"SUB (shifted register)","Bits":"1|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias NEG (shifted register)."},
{"Name":"SUBS (extended register)","Bits":"0|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMP (extended register)."},
{"Name":"SUBS (extended register)","Bits":"1|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMP (extended register)."},
{"Name":"SUBS (immediate)","Bits":"0|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMP (immediate)."},
{"Name":"SUBS (immediate)","Bits":"1|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMP (immediate)."},
{"Name":"SUBS (shifted register)","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the aliases CMP (shifted register) and NEGS."},
{"Name":"SUBS (shifted register)","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the aliases CMP (shifted register) and NEGS."},
{"Name":"SVC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"SVC #<imm>","Code":"","Alias":""},
{"Name":"SXTB","Bits":"0|0|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SXTB <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SXTB","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTB <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SXTH","Bits":"0|0|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SXTH <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SXTH","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTH <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SXTW","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTW <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
{"Name":"SYS","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}","Code":"","Alias":"This instruction is used by the aliases AT, DC, IC, and TLBI."},
{"Name":"SYSL","Bits":"1|1|0|1|0|1|0|1|0|0|1|0|1|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>","Code":"","Alias":""},
{"Name":"TBNZ","Bits":"b5|0|1|1|0|1|1|1|b40:5|imm14:14|Rt:5","Arch":"14-bit signed PC-relative branch offset variant","Syntax":"TBNZ <R><t>, #<imm>, <label>","Code":"","Alias":""},
{"Name":"TBZ","Bits":"b5|0|1|1|0|1|1|0|b40:5|imm14:14|Rt:5","Arch":"14-bit signed PC-relative branch offset variant","Syntax":"TBZ <R><t>, #<imm>, <label>","Code":"","Alias":""},
{"Name":"TLBI","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|1|0|0|0|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"TLBI <tlbi_op>{, <Xt>}","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
{"Name":"TST (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"TST <Wn>, #<imm>","Code":"","Alias":"This instruction is an alias of the ANDS (immediate) instruction."},
{"Name":"TST (immediate)","Bits":"1|1|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"TST <Xn>, #<imm>","Code":"","Alias":"This instruction is an alias of the ANDS (immediate) instruction."},
{"Name":"TST (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"TST <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ANDS (shifted register) instruction."},
{"Name":"TST (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"TST <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ANDS (shifted register) instruction."},
{"Name":"UBFIZ","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFIZ <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"UBFIZ","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFIZ <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"UBFM","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},
{"Name":"UBFM","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},
{"Name":"UBFX","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFX <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"UBFX","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFX <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"UDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"UDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"UMADDL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMADDL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMULL."},
{"Name":"UMNEGL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMSUBL instruction."},
{"Name":"UMSUBL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMNEGL."},
{"Name":"UMULH","Bits":"1|0|0|1|1|0|1|1|1|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"UMULL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMADDL instruction."},
{"Name":"UXTB","Bits":"0|1|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UXTB <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"UXTH","Bits":"0|1|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UXTH <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
{"Name":"WFE","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"WFE","Code":"","Alias":""},
{"Name":"WFI","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|1|1|1|1|1|1|1","Arch":"System variant","Syntax":"WFI","Code":"","Alias":""},
{"Name":"YIELD","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"YIELD","Code":"","Alias":""},
{"Name":"ABS","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"ABS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"ABS","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"ABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"ADD (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"ADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"ADD (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"ADDHN, ADDHN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"ADDHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"ADDHN, ADDHN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"ADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"ADDP (scalar)","Bits":"0|1|0|1|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDP <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"ADDP (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"ADDV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"AESD","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESD <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
{"Name":"AESE","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESE <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
{"Name":"AESIMC","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESIMC <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
{"Name":"AESMC","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESMC <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
{"Name":"AND (vector)","Bits":"0|Q|0|0|1|1|1|0|0|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"BIC (vector, immediate)","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit variant","Syntax":"BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"BIC (vector, immediate)","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"BIC (vector, register)","Bits":"0|Q|0|0|1|1|1|0|0|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"BIF","Bits":"0|Q|1|0|1|1|1|0|1|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"BIT","Bits":"0|Q|1|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"BSL","Bits":"0|Q|1|0|1|1|1|0|0|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CLS (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CLS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"CLZ (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CLZ <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"CMEQ (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMEQ <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"CMEQ (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CMEQ (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMEQ <V><d>, <V><n>, #0","Code":"","Alias":""},
{"Name":"CMEQ (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMEQ <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
{"Name":"CMGE (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"CMGE (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CMGE (zero)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGE <V><d>, <V><n>, #0","Code":"","Alias":""},
{"Name":"CMGE (zero)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGE <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
{"Name":"CMGT (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"CMGT (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CMGT (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGT <V><d>, <V><n>, #0","Code":"","Alias":""},
{"Name":"CMGT (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGT <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
{"Name":"CMHI (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMHI <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"CMHI (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CMHS (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMHS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"CMHS (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CMLE (zero)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMLE <V><d>, <V><n>, #0","Code":"","Alias":""},
{"Name":"CMLE (zero)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMLE <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
{"Name":"CMLT (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMLT <V><d>, <V><n>, #0","Code":"","Alias":""},
{"Name":"CMLT (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMLT <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
{"Name":"CMTST","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMTST <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"CMTST","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"CNT","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CNT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"DUP (element)","Bits":"0|1|0|1|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"DUP <V><d>, <Vn>.<T>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (scalar)."},
{"Name":"DUP (element)","Bits":"0|Q|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"DUP <Vd>.<T>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (scalar)."},
{"Name":"DUP (general)","Bits":"0|Q|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"DUP <Vd>.<T>, <R><n>","Code":"","Alias":""},
{"Name":"EOR (vector)","Bits":"0|Q|1|0|1|1|1|0|0|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"EXT","Bits":"0|Q|1|0|1|1|1|0|0|0|0|Rm:5|0|imm4:4|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>","Code":"","Alias":""},
{"Name":"FABD","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FABD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FABD","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FABS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FABS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FABS <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FABS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FABS <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FACGE","Bits":"0|1|1|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FACGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FACGE","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FACGT","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FACGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FACGT","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FADD (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FADD <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FADD <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FADDP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FADDP <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FADDP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FCCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|0|1|Rn:5|0|nzcv:4","Arch":"Single-precision variant","Syntax":"FCCMP <Sn>, <Sm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"FCCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|0|1|Rn:5|0|nzcv:4","Arch":"Double-precision variant","Syntax":"FCCMP <Dn>, <Dm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"FCCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|0|1|Rn:5|1|nzcv:4","Arch":"Single-precision variant","Syntax":"FCCMPE <Sn>, <Sm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"FCCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|0|1|Rn:5|1|nzcv:4","Arch":"Double-precision variant","Syntax":"FCCMPE <Dn>, <Dm>, #<nzcv>, <cond>","Code":"","Alias":""},
{"Name":"FCMEQ (register)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMEQ <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FCMEQ (register)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FCMEQ (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMEQ <V><d>, <V><n>, #0.0","Code":"","Alias":""},
{"Name":"FCMEQ (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
{"Name":"FCMGE (register)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FCMGE (register)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FCMGE (zero)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGE <V><d>, <V><n>, #0.0","Code":"","Alias":""},
{"Name":"FCMGE (zero)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGE <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
{"Name":"FCMGT (register)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FCMGT (register)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FCMGT (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGT <V><d>, <V><n>, #0.0","Code":"","Alias":""},
{"Name":"FCMGT (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGT <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
{"Name":"FCMLE (zero)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMLE <V><d>, <V><n>, #0.0","Code":"","Alias":""},
{"Name":"FCMLE (zero)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMLE <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
{"Name":"FCMLT (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMLT <V><d>, <V><n>, #0.0","Code":"","Alias":""},
{"Name":"FCMLT (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMLT <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|0|0|Rn:5|00:2|0|0|0","Arch":"Single-precision variant","Syntax":"FCMP <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|(00000):5|0|0|1|0|0|0|Rn:5|01:2|0|0|0","Arch":"Single-precision, zero variant","Syntax":"FCMP <Sn>, #0.0","Code":"","Alias":""},
{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|0|0|Rn:5|00:2|0|0|0","Arch":"Double-precision variant","Syntax":"FCMP <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|(00000):5|0|0|1|0|0|0|Rn:5|01:2|0|0|0","Arch":"Double-precision, zero variant","Syntax":"FCMP <Dn>, #0.0","Code":"","Alias":""},
{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|0|0|Rn:5|10:2|0|0|0","Arch":"Single-precision variant","Syntax":"FCMPE <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|(00000):5|0|0|1|0|0|0|Rn:5|11:2|0|0|0","Arch":"Single-precision, zero variant","Syntax":"FCMPE <Sn>, #0.0","Code":"","Alias":""},
{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|0|0|Rn:5|10:2|0|0|0","Arch":"Double-precision variant","Syntax":"FCMPE <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|(00000):5|0|0|1|0|0|0|Rn:5|11:2|0|0|0","Arch":"Double-precision, zero variant","Syntax":"FCMPE <Dn>, #0.0","Code":"","Alias":""},
{"Name":"FCSEL","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|1|1|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FCSEL <Sd>, <Sn>, <Sm>, <cond>","Code":"","Alias":""},
{"Name":"FCSEL","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|1|1|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FCSEL <Dd>, <Dn>, <Dm>, <cond>","Code":"","Alias":""},
{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|11:2|1|0|0|0|1|00:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Half-precision to single-precision variant","Syntax":"FCVT <Sd>, <Hn>","Code":"","Alias":""},
{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|11:2|1|0|0|0|1|01:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Half-precision to double-precision variant","Syntax":"FCVT <Dd>, <Hn>","Code":"","Alias":""},
{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|11:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to half-precision variant","Syntax":"FCVT <Hd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|01:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to double-precision variant","Syntax":"FCVT <Dd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|11:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to half-precision variant","Syntax":"FCVT <Hd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|00:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to single-precision variant","Syntax":"FCVT <Sd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTAS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTAS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTAS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTAS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTAS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTAS <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTAS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTAS <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTAS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTAS <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTAS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTAS <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTAU (vector)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTAU <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTAU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTAU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTAU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTAU <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTAU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTAU <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTAU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTAU <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTAU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTAU <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTL, FCVTL2","Bits":"0|0|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
{"Name":"FCVTL, FCVTL2","Bits":"0|1|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
{"Name":"FCVTMS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTMS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTMS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTMS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTMS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTMS <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTMS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTMS <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTMS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTMS <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTMS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTMS <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTMU (vector)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTMU <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTMU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTMU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTMU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTMU <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTMU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTMU <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTMU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTMU <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTMU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTMU <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTN, FCVTN2","Bits":"0|0|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"FCVTN, FCVTN2","Bits":"0|1|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FCVTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"FCVTNS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTNS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTNS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTNS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTNS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTNS <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTNS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTNS <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTNS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTNS <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTNS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTNS <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTNU (vector)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTNU <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTNU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTNU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTNU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTNU <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTNU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTNU <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTNU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTNU <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTNU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTNU <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTPS (vector)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTPS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTPS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTPS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTPS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTPS <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTPS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTPS <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTPS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTPS <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTPS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTPS <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTPU (vector)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTPU <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTPU (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTPU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTPU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTPU <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTPU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTPU <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTPU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTPU <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTPU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTPU <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTXN, FCVTXN2","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTXN <Vb><d>, <Va><n>","Code":"","Alias":""},
{"Name":"FCVTXN, FCVTXN2","Bits":"0|0|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTXN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"FCVTXN, FCVTXN2","Bits":"0|1|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTXN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"FCVTZS (vector, fixed-point)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZS <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZS (vector, fixed-point)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"FCVTZS (vector, integer)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTZS (vector, integer)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Sn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Dn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTZU (vector, fixed-point)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZU <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZU (vector, fixed-point)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"FCVTZU (vector, integer)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZU <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FCVTZU (vector, integer)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Sn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Sn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Dn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Sn>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Dn>","Code":"","Alias":""},
{"Name":"FCVTZU (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FDIV (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FDIV <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FDIV <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FMADD","Bits":"0|0|0|1|1|1|1|1|00:2|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMADD <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
{"Name":"FMADD","Bits":"0|0|0|1|1|1|1|1|01:2|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMADD <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
{"Name":"FMAX (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMAX (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMAX <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FMAX (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMAX <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FMAXNM (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMAXNM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMAXNM <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FMAXNM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMAXNM <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FMAXNMP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXNMP <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMAXNMP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMAXNMV","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXNMV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMAXP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXP <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMAXP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMAXV","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMIN (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMIN (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMIN <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FMIN (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMIN <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FMINNM (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMINNM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMINNM <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FMINNM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMINNM <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FMINNMP (scalar)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINNMP <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMINNMP (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMINNMV","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINNMV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMINP (scalar)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINP <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMINP (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMINV","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FMLA (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|0|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMLA (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|0|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMLA (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMLS (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|0|1|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMLS <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMLS (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|0|1|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMLS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMOV (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|1|1|1|1|0|1|d|e|f|g|h|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Vd>.<T>, #<imm>","Code":"","Alias":""},
{"Name":"FMOV (vector, immediate)","Bits":"0|1|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1|1|1|1|0|1|d|e|f|g|h|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Vd>.2D, #<imm>","Code":"","Alias":""},
{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"FMOV <Sd>, <Wn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FMOV <Wd>, <Sn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|01:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"FMOV <Dd>, <Xn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|10:2|1|01:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to top half of 128-bit variant","Syntax":"FMOV <Vd>.D[1], <Xn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|01:2|1|00:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FMOV <Xd>, <Dn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|10:2|1|01:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Top half of 128-bit to 64-bit variant","Syntax":"FMOV <Xd>, <Vn>.D[1]","Code":"","Alias":""},
{"Name":"FMOV (scalar, immediate)","Bits":"0|0|0|1|1|1|1|0|00:2|1|imm8:8|1|0|0|0|0|0|0|0|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Sd>, #<imm>","Code":"","Alias":""},
{"Name":"FMOV (scalar, immediate)","Bits":"0|0|0|1|1|1|1|0|01:2|1|imm8:8|1|0|0|0|0|0|0|0|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, #<imm>","Code":"","Alias":""},
{"Name":"FMSUB","Bits":"0|0|0|1|1|1|1|1|00:2|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMSUB <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
{"Name":"FMSUB","Bits":"0|0|0|1|1|1|1|1|01:2|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMSUB <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
{"Name":"FMUL (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMUL (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMUL (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMUL <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMUL <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FMULX (by element)","Bits":"0|1|1|1|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMULX <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMULX (by element)","Bits":"0|Q|1|0|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"FMULX","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMULX <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FMULX","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FNEG (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FNEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FNEG (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNEG <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FNEG (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNEG <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FNMADD","Bits":"0|0|0|1|1|1|1|1|00:2|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMADD <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
{"Name":"FNMADD","Bits":"0|0|0|1|1|1|1|1|01:2|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMADD <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
{"Name":"FNMSUB","Bits":"0|0|0|1|1|1|1|1|00:2|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMSUB <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
{"Name":"FNMSUB","Bits":"0|0|0|1|1|1|1|1|01:2|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMSUB <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
{"Name":"FNMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMUL <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FNMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMUL <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"FRECPE","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRECPE <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FRECPE","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRECPE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRECPS","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRECPS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FRECPS","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FRECPX","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar single-precision and double-precision variant","Syntax":"FRECPX <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FRINTA (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTA <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTA (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTA <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTA (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTA <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRINTI (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTI <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTI (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTI <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTI (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTI <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRINTM (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTM <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTM <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTM <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRINTN (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTN <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTN (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTN <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTN (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTN <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRINTP (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTP <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTP (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTP <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTP (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTP <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRINTX (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTX <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTX (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTX <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTX (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTX <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRINTZ (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTZ <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRINTZ (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTZ <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FRINTZ (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTZ <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FRSQRTE","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRSQRTE <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"FRSQRTE","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRSQRTE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FRSQRTS","Bits":"0|1|0|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRSQRTS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"FRSQRTS","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FSQRT (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSQRT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"FSQRT (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSQRT <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"FSQRT (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FSQRT <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FSUB (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSUB <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FSUB <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
{"Name":"INS (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is used by the alias MOV (element)."},
{"Name":"INS (general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index>], <R><n>","Code":"","Alias":"This instruction is used by the alias MOV (from general)."},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0111:4|size:2|Rn:5|Rt:5","Arch":"No offset One register variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|1010:4|size:2|Rn:5|Rt:5","Arch":"No offset Two registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0110:4|size:2|Rn:5|Rt:5","Arch":"No offset Three registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0010:4|size:2|Rn:5|Rt:5","Arch":"No offset Four registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, immediate offset variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, register offset variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>], #1","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32","Code":"","Alias":""},
{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LDNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDNP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"LDR (literal, SIMD&FP)","Bits":"00:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"LDR <St>, <label>","Code":"","Alias":""},
{"Name":"LDR (literal, SIMD&FP)","Bits":"01:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Dt>, <label>","Code":"","Alias":""},
{"Name":"LDR (literal, SIMD&FP)","Bits":"10:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"128-bit variant","Syntax":"LDR <Qt>, <label>","Code":"","Alias":""},
{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
{"Name":"LDR (register, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDR (register, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDR (register, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"LDUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDUR <Bt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDUR (SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"LDUR <Ht>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDUR (SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDUR <St>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDUR (SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDUR <Dt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"LDUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDUR <Qt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"MLA (by element)","Bits":"0|Q|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"MLA (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"MLS (by element)","Bits":"0|Q|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"MLS (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"MOV (scalar)","Bits":"0|1|0|1|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar variant","Syntax":"MOV <V><d>, <Vn>.<T>[<index>]","Code":"","Alias":"This instruction is an alias of the DUP (element) instruction."},
{"Name":"MOV (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is an alias of the INS (element) instruction."},
{"Name":"MOV (from general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"MOV <Vd>.<Ts>[<index>], <R><n>","Code":"","Alias":"This instruction is an alias of the INS (general) instruction."},
{"Name":"MOV (vector)","Bits":"0|Q|0|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MOV <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is an alias of the ORR (vector, register) instruction."},
{"Name":"MOV (to general)","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, <Vn>.S[<index>]","Code":"","Alias":"This instruction is an alias of the UMOV instruction."},
{"Name":"MOV (to general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, <Vn>.D[<index>]","Code":"","Alias":"This instruction is an alias of the UMOV instruction."},
{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"8-bit variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #0}","Code":"","Alias":""},
{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit shifted immediate variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifted immediate variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifting ones variant","Syntax":"MOVI <Vd>.<T>, #<imm8>, MSL #<amount>","Code":"","Alias":""},
{"Name":"MOVI","Bits":"0|0|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"64-bit scalar variant","Syntax":"MOVI <Dd>, #<imm>","Code":"","Alias":""},
{"Name":"MOVI","Bits":"0|1|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"64-bit vector variant","Syntax":"MOVI <Vd>.2D, #<imm>","Code":"","Alias":""},
{"Name":"MUL (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"MUL (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"MVN","Bits":"0|Q|1|0|1|1|1|0|0|0|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MVN <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is an alias of the NOT instruction."},
{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit shifted immediate variant","Syntax":"MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifted immediate variant","Syntax":"MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifting ones variant","Syntax":"MVNI <Vd>.<T>, #<imm8>, MSL #<amount>","Code":"","Alias":""},
{"Name":"NEG (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"NEG <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"NEG (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"NEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"NOT","Bits":"0|Q|1|0|1|1|1|0|0|0|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"NOT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is used by the alias MVN."},
{"Name":"ORN (vector)","Bits":"0|Q|0|0|1|1|1|0|1|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"ORR (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit variant","Syntax":"ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"ORR (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
{"Name":"ORR (vector, register)","Bits":"0|Q|0|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":"This instruction is used by the alias MOV (vector)."},
{"Name":"PMUL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"PMULL, PMULL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"PMULL, PMULL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"RADDHN, RADDHN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RADDHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"RADDHN, RADDHN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"RBIT (vector)","Bits":"0|Q|1|0|1|1|1|0|0|1|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RBIT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"REV16 (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV16 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"REV32 (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV32 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"REV64","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV64 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"RSHRN, RSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"RSHRN, RSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"RSUBHN, RSUBHN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RSUBHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"RSUBHN, RSUBHN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RSUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"SABA","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SABAL, SABAL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SABAL, SABAL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SABD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SABDL, SABDL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SABDL, SABDL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SADALP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SADALP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
{"Name":"SADDL, SADDL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SADDL, SADDL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SADDLP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SADDLP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
{"Name":"SADDLV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SADDLV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SADDW, SADDW2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SADDW, SADDW2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SCVTF (vector, fixed-point)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SCVTF <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
{"Name":"SCVTF (vector, fixed-point)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SCVTF (vector, integer)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SCVTF <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"SCVTF (vector, integer)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SCVTF <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Wn>, #<fbits>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Wn>, #<fbits>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Xn>, #<fbits>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Xn>, #<fbits>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Wn>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Wn>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Xn>","Code":"","Alias":""},
{"Name":"SCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Xn>","Code":"","Alias":""},
{"Name":"SHA1C","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1C <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHA1H","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1H <Sd>, <Sn>","Code":"","Alias":""},
{"Name":"SHA1M","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1M <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHA1P","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1P <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHA1SU0","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHA1SU1","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1SU1 <Vd>.4S, <Vn>.4S","Code":"","Alias":""},
{"Name":"SHA256H2","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256H2 <Qd>, <Qn>, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHA256H","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256H <Qd>, <Qn>, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHA256SU0","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256SU0 <Vd>.4S, <Vn>.4S","Code":"","Alias":""},
{"Name":"SHA256SU1","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S","Code":"","Alias":""},
{"Name":"SHADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SHL","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SHL","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SHLL, SHLL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"","Alias":""},
{"Name":"SHLL, SHLL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"","Alias":""},
{"Name":"SHRN, SHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SHRN, SHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SHSUB","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SLI","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SLI <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SLI","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SLI <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SMAX","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SMAXP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SMAXV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SMIN","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SMINP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SMINV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SMLAL, SMLAL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMLAL, SMLAL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMLAL, SMLAL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SMLAL, SMLAL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SMLSL, SMLSL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMLSL, SMLSL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMLSL, SMLSL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SMLSL, SMLSL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SMOV","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SMOV <Wd>, <Vn>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMOV","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMOV <Xd>, <Vn>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMULL, SMULL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMULL, SMULL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SMULL, SMULL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SMULL, SMULL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQABS","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQABS <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"SQABS","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SQADD","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SQADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLAL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLSL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLSL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQDMULH (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|1|0|0|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMULH (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|1|0|0|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMULH (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULH <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SQDMULH (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SQNEG","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQNEG <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"SQNEG","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQNEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SQRDMULH (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|1|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQRDMULH (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|1|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"SQRDMULH (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRDMULH <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SQRDMULH (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SQRSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SQRSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHRUN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRUN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSHL (immediate)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SQSHL (immediate)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSHL (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SQSHL (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SQSHLU","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHLU <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SQSHLU","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHLU <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSHRN, SQSHRN2","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
{"Name":"SQSHRN, SQSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSHRN, SQSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHRUN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRUN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SQSUB","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SQSUB","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SQXTN, SQXTN2","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQXTN <Vb><d>, <Va><n>","Code":"","Alias":""},
{"Name":"SQXTN, SQXTN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"SQXTN, SQXTN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"SQXTUN, SQXTUN2","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQXTUN <Vb><d>, <Va><n>","Code":"","Alias":""},
{"Name":"SQXTUN, SQXTUN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTUN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"SQXTUN, SQXTUN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTUN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"SRHADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SRI","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRI <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SRI","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRI <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SRSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SRSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SRSHR","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SRSHR","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SRSRA","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SRSRA","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SSHLL, SSHLL2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SSHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias SXTL, SXTL2."},
{"Name":"SSHLL, SSHLL2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SSHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias SXTL, SXTL2."},
{"Name":"SSHR","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SSHR","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SSRA","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"SSRA","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"SSUBL, SSUBL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SSUBL, SSUBL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SSUBW, SSUBW2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"SSUBW, SSUBW2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0111:4|size:2|Rn:5|Rt:5","Arch":"No offset One register variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1010:4|size:2|Rn:5|Rt:5","Arch":"No offset Two registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0110:4|size:2|Rn:5|Rt:5","Arch":"No offset Three registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0010:4|size:2|Rn:5|Rt:5","Arch":"No offset Four registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, immediate offset variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, register offset variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>], #1","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24","Code":"","Alias":""},
{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32","Code":"","Alias":""},
{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"STNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STNP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STR <St>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STR <St>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"STR <St>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
{"Name":"STR (register, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STR (register, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STR (register, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
{"Name":"STUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STUR <Bt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STUR (SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"STUR <Ht>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STUR (SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STUR <St>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STUR (SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STUR <Dt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"STUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STUR <Qt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
{"Name":"SUB (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"SUB (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"SUBHN, SUBHN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SUBHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"SUBHN, SUBHN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"SUQADD","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SUQADD <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"SUQADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SUQADD <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"SXTL, SXTL2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SXTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the SSHLL, SSHLL2 instruction."},
{"Name":"SXTL, SXTL2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SXTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the SSHLL, SSHLL2 instruction."},
{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|01:2|0|0|0|Rn:5|Rd:5","Arch":"Two register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|10:2|0|0|0|Rn:5|Rd:5","Arch":"Three register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|11:2|0|0|0|Rn:5|Rd:5","Arch":"Four register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|00:2|0|0|0|Rn:5|Rd:5","Arch":"Single register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|01:2|1|0|0|Rn:5|Rd:5","Arch":"Two register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|10:2|1|0|0|Rn:5|Rd:5","Arch":"Three register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|11:2|1|0|0|Rn:5|Rd:5","Arch":"Four register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|00:2|1|0|0|Rn:5|Rd:5","Arch":"Single register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
{"Name":"TRN1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"TRN2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UABA","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UABAL, UABAL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UABAL, UABAL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UABD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UABDL, UABDL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UABDL, UABDL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UADALP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UADALP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
{"Name":"UADDL, UADDL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UADDL, UADDL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UADDLP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UADDLP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
{"Name":"UADDLV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UADDLV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"UADDW, UADDW2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UADDW, UADDW2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UCVTF (vector, fixed-point)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UCVTF <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
{"Name":"UCVTF (vector, fixed-point)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"UCVTF (vector, integer)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UCVTF <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"UCVTF (vector, integer)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UCVTF <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Wn>, #<fbits>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Wn>, #<fbits>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Xn>, #<fbits>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Xn>, #<fbits>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Wn>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Wn>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Xn>","Code":"","Alias":""},
{"Name":"UCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Xn>","Code":"","Alias":""},
{"Name":"UHADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UHSUB","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UMAX","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UMAXP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UMAXV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"UMIN","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UMINP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UMINV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"UMLAL, UMLAL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"UMLAL, UMLAL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"UMLAL, UMLAL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UMLAL, UMLAL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UMLSL, UMLSL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"UMLSL, UMLSL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"UMLSL, UMLSL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UMLSL, UMLSL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UMOV","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UMOV <Wd>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (to general)."},
{"Name":"UMOV","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMOV <Xd>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (to general)."},
{"Name":"UMULL, UMULL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"UMULL, UMULL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
{"Name":"UMULL, UMULL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UMULL, UMULL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UQADD","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"UQADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UQRSHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"UQRSHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQRSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"UQSHL (immediate)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"UQSHL (immediate)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"UQSHL (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"UQSHL (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UQSHRN, UQSHRN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
{"Name":"UQSHRN, UQSHRN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"UQSHRN, UQSHRN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"UQSUB","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"UQSUB","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UQXTN, UQXTN2","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQXTN <Vb><d>, <Va><n>","Code":"","Alias":""},
{"Name":"UQXTN, UQXTN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQXTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"UQXTN, UQXTN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQXTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"URECPE","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"URECPE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"URHADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"URSHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"URSHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"URSHR","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"URSHR","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"URSQRTE","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"URSQRTE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"URSRA","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"URSRA","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"USHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
{"Name":"USHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"USHLL, USHLL2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"USHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias UXTL, UXTL2."},
{"Name":"USHLL, USHLL2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"USHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias UXTL, UXTL2."},
{"Name":"USHR","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"USHR","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"USQADD","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USQADD <V><d>, <V><n>","Code":"","Alias":""},
{"Name":"USQADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USQADD <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
{"Name":"USRA","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
{"Name":"USRA","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
{"Name":"USUBL, USUBL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"USUBL, USUBL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"USUBW, USUBW2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"USUBW, USUBW2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
{"Name":"UXTL, UXTL2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UXTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the USHLL, USHLL2 instruction."},
{"Name":"UXTL, UXTL2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UXTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the USHLL, USHLL2 instruction."},
{"Name":"UZP1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"UZP2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"XTN, XTN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"XTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"XTN, XTN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"XTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
{"Name":"ZIP1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"ZIP2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""}
]