x86avxgen/testdata/xedpath: replace "INTEL CONFIDENTIAL" files
These files are not really confidential - they were released in
github.com/intelxed/xed with incorrect copyright notices.
The copyright notices were updated in
https://github.com/intelxed/xed/commit/5c538047876feecf080d9441110f81d0e67b5de8
but the files had also changed a bit by then.
Replace the two mislabeled files with the latest versions,
bringing in the updated Apache license as well as assorted other changes.
The tests still pass, so these changes must not matter too much.
Fixes golang/go#64315.
[git-generate]
cd x86/x86avxgen/testdata/xedpath
rm -rf _xed
git clone https://github.com/intelxed/xed _xed
cd _xed
git checkout d41e876 # "2019 copyright"
cd ..
echo '
e all-dec-instructions.txt
/^###FILE:.*avx512-foundation-isa.xed.txt/+1;/^###FILE/-3 d
/^###FILE:.*avx512-foundation-isa.xed.txt/+1r _xed/datafiles/avx512f/avx512-foundation-isa.xed.txt
/^###FILE:.*skx-isa.xed.txt/+1;/^###FILE/-3 d
/^###FILE:.*skx-isa.xed.txt/+1r _xed/datafiles/avx512-skx/skx-isa.xed.txt
,s/ +$//g
w
q
' | sam -d
Change-Id: I60fb4b9a420b8962fbbdd026cb6229d55144908d
Reviewed-on: https://go-review.googlesource.com/c/arch/+/547775
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
diff --git a/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt b/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt
index 07cbc41..aad0b81 100644
--- a/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt
+++ b/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt
@@ -11873,29 +11873,22 @@
###FILE: ./datafiles/avx512f/avx512-foundation-isa.xed.txt
-
#BEGIN_LEGAL
-#INTEL CONFIDENTIAL
#
-#Copyright (c) 2017, Intel Corporation. All rights reserved.
+#Copyright (c) 2019 Intel Corporation
#
-#The source code contained or described herein and all documents
-#related to the source code ("Material") are owned by Intel Corporation
-#or its suppliers or licensors. Title to the Material remains with
-#Intel Corporation or its suppliers and licensors. The Material
-#contains trade secrets and proprietary and confidential information of
-#Intel or its suppliers and licensors. The Material is protected by
-#worldwide copyright and trade secret laws and treaty provisions. No
-#part of the Material may be used, copied, reproduced, modified,
-#published, uploaded, posted, transmitted, distributed, or disclosed in
-#any way without Intel's prior express written permission.
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
#
-#No license under any patent, copyright, trade secret or other
-#intellectual property right is granted to or conferred upon you by
-#disclosure or delivery of the Materials, either expressly, by
-#implication, inducement, estoppel or otherwise. Any license under such
-#intellectual property rights must be express and approved by Intel in
-#writing.
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
#END_LEGAL
#
#
@@ -13103,7 +13096,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
+IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
}
@@ -13117,7 +13113,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
+IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
}
@@ -13131,7 +13130,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
+IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512
+PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512
}
@@ -13147,7 +13149,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512
}
@@ -13161,7 +13163,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512
}
@@ -13175,7 +13177,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512
}
@@ -13235,7 +13237,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
+IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
}
@@ -13249,7 +13254,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
+IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
}
@@ -13263,7 +13271,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
+IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512
+PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512
}
@@ -13279,7 +13290,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512
}
@@ -13293,7 +13304,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512
}
@@ -13307,7 +13318,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512
}
@@ -13323,7 +13334,11 @@
EXCEPTIONS: AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES: SIMD_SCALAR
-PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0
+COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding
+PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
+IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
+PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
}
@@ -13337,7 +13352,10 @@
EXCEPTIONS: AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
+IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
+PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
}
@@ -13353,7 +13371,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
}
@@ -13367,7 +13385,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
}
@@ -13381,7 +13399,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64
IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512
}
@@ -13397,7 +13415,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0
+PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
+IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
+PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
}
@@ -13411,7 +13432,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0
+PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
+IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
+PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
}
@@ -13425,7 +13449,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
+IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
+PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
}
@@ -13441,7 +13468,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
}
@@ -13455,7 +13482,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
}
@@ -13469,12 +13496,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64
IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512
}
-
-
# EMITTING VCVTSS2SD (VCVTSS2SD-128-1)
{
ICLASS: VCVTSS2SD
@@ -13529,7 +13554,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
+IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
}
@@ -13543,7 +13571,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
+IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
}
@@ -13557,7 +13588,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
+IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512
+PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512
}
@@ -13573,7 +13607,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512
}
@@ -13587,7 +13621,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512
}
@@ -13601,7 +13635,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512
}
@@ -13617,7 +13651,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
+IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
}
@@ -13631,7 +13668,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
+IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
}
@@ -13645,7 +13685,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
+IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512
+PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512
}
@@ -13661,7 +13704,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512
}
@@ -13675,7 +13718,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512
}
@@ -13689,7 +13732,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512
}
@@ -13881,7 +13924,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
+IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
}
@@ -13895,7 +13941,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
+IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
+PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
}
@@ -13909,7 +13958,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
+IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512
+PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512
}
@@ -13925,7 +13977,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512
}
@@ -13939,7 +13991,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512
}
@@ -13953,7 +14005,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512
}
@@ -13969,7 +14021,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
+IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
}
@@ -13983,7 +14038,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
+IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
+PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
}
@@ -13997,7 +14055,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
+IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512
+PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512
}
@@ -14013,7 +14074,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512
}
@@ -14027,7 +14088,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512
}
@@ -14041,7 +14102,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
-PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q()
+PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512
}
@@ -14057,7 +14118,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
+IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
}
@@ -14071,7 +14135,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
+IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
+PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
}
@@ -14085,7 +14152,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
+IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512
+PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512
}
@@ -14101,7 +14171,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512
}
@@ -14115,7 +14185,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512
}
@@ -14129,7 +14199,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512
}
@@ -14145,7 +14215,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
+IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
}
@@ -14159,7 +14232,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
+IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
+PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
}
@@ -14173,7 +14249,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
+IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512
+PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512
}
@@ -14189,7 +14268,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512
}
@@ -14203,7 +14282,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512
}
@@ -14217,7 +14296,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
-PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D()
+PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512
}
@@ -14307,7 +14386,10 @@
EXCEPTIONS: AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES: SIMD_SCALAR
-PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
+IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
+PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
}
@@ -14321,7 +14403,10 @@
EXCEPTIONS: AVX512-E10NF
REAL_OPCODE: Y
ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
+IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
+PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
}
@@ -14337,7 +14422,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
}
@@ -14351,7 +14436,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
}
@@ -14365,7 +14450,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64
IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512
}
@@ -14381,7 +14466,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
+IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
+PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
}
@@ -14395,7 +14483,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
+IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
+PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
}
@@ -14409,7 +14500,10 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
+IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
+PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
}
@@ -14425,7 +14519,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
}
@@ -14439,7 +14533,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR
-PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0
+PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
}
@@ -14453,7 +14547,7 @@
EXCEPTIONS: AVX512-E3NF
REAL_OPCODE: Y
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
-PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64
IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512
}
@@ -18722,7 +18816,10 @@
ISA_SET: AVX512F_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
+IFORM: VMOVD_XMMu32_GPR32u32_AVX512
+PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
IFORM: VMOVD_XMMu32_GPR32u32_AVX512
}
@@ -18736,7 +18833,10 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_READER
-PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
+IFORM: VMOVD_XMMu32_MEMu32_AVX512
+PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
IFORM: VMOVD_XMMu32_MEMu32_AVX512
}
@@ -18751,7 +18851,10 @@
ISA_SET: AVX512F_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0
+OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
+IFORM: VMOVD_GPR32u32_XMMu32_AVX512
+PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
IFORM: VMOVD_GPR32u32_XMMu32_AVX512
}
@@ -18765,7 +18868,10 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_STORE
-PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
+IFORM: VMOVD_MEMu32_XMMu32_AVX512
+PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
IFORM: VMOVD_MEMu32_XMMu32_AVX512
}
@@ -19074,7 +19180,7 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_SCALAR
-PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64
IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512
}
@@ -19090,7 +19196,7 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_SCALAR
-PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64
IFORM: VMOVHPD_MEMf64_XMMf64_AVX512
}
@@ -19153,7 +19259,7 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_SCALAR
-PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64
IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512
}
@@ -19169,7 +19275,7 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_SCALAR
-PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64
IFORM: VMOVLPD_MEMf64_XMMf64_AVX512
}
@@ -19338,7 +19444,7 @@
ISA_SET: AVX512F_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64
IFORM: VMOVQ_XMMu64_XMMu64_AVX512
}
@@ -19352,7 +19458,7 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_SCALAR
-PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
IFORM: VMOVQ_XMMu64_MEMu64_AVX512
}
@@ -19367,7 +19473,7 @@
ISA_SET: AVX512F_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0
+PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64
IFORM: VMOVQ_XMMu64_XMMu64_AVX512
}
@@ -19381,7 +19487,7 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_SCALAR
-PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
+PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
IFORM: VMOVQ_MEMu64_XMMu64_AVX512
}
@@ -20217,7 +20323,10 @@
EXCEPTIONS: AVX512-E7NM
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
-PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
+IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
}
@@ -20265,7 +20374,7 @@
EXCEPTIONS: AVX512-E7NM
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
-PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 mode64 NOEVSR
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64
IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512
}
@@ -22272,9 +22381,10 @@
ISA_SET: AVX512F_512
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
-OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
+OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512
}
@@ -22286,9 +22396,10 @@
ISA_SET: AVX512F_512
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
+OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512
}
@@ -22332,9 +22443,10 @@
ISA_SET: AVX512F_512
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
-OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512
}
@@ -22346,9 +22458,10 @@
ISA_SET: AVX512F_512
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512
}
@@ -25350,7 +25463,6 @@
-
###FILE: ./datafiles/avx512cd/vconflict-isa.xed.txt
#BEGIN_LEGAL
@@ -25533,29 +25645,22 @@
###FILE: ./datafiles/avx512-skx/skx-isa.xed.txt
-
#BEGIN_LEGAL
-#INTEL CONFIDENTIAL
#
-#Copyright (c) 2017, Intel Corporation. All rights reserved.
+#Copyright (c) 2019 Intel Corporation
#
-#The source code contained or described herein and all documents
-#related to the source code ("Material") are owned by Intel Corporation
-#or its suppliers or licensors. Title to the Material remains with
-#Intel Corporation or its suppliers and licensors. The Material
-#contains trade secrets and proprietary and confidential information of
-#Intel or its suppliers and licensors. The Material is protected by
-#worldwide copyright and trade secret laws and treaty provisions. No
-#part of the Material may be used, copied, reproduced, modified,
-#published, uploaded, posted, transmitted, distributed, or disclosed in
-#any way without Intel's prior express written permission.
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
#
-#No license under any patent, copyright, trade secret or other
-#intellectual property right is granted to or conferred upon you by
-#disclosure or delivery of the Materials, either expressly, by
-#implication, inducement, estoppel or otherwise. Any license under such
-#intellectual property rights must be express and approved by Intel in
-#writing.
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
#END_LEGAL
#
#
@@ -25818,8 +25923,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}
{
@@ -25832,8 +25937,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}
@@ -25848,8 +25953,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}
{
@@ -25862,8 +25967,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}
@@ -25878,8 +25983,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}
{
@@ -25892,8 +25997,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}
@@ -25908,8 +26013,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
}
{
@@ -25922,8 +26027,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
}
@@ -25938,8 +26043,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
}
{
@@ -25952,8 +26057,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
}
@@ -25968,8 +26073,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}
{
@@ -25982,8 +26087,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}
@@ -25998,8 +26103,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}
{
@@ -26012,8 +26117,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}
@@ -26028,8 +26133,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}
{
@@ -26042,8 +26147,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}
@@ -26058,8 +26163,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}
{
@@ -26072,8 +26177,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}
@@ -26088,8 +26193,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
}
{
@@ -26102,8 +26207,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
}
@@ -26118,8 +26223,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
}
{
@@ -26132,8 +26237,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
}
@@ -26148,8 +26253,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}
{
@@ -26162,8 +26267,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}
@@ -34886,8 +34991,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM: VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}
{
@@ -34900,8 +35005,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}
@@ -34916,8 +35021,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM: VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}
{
@@ -34930,8 +35035,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}
@@ -34946,8 +35051,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}
{
@@ -34960,8 +35065,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}
@@ -34976,8 +35081,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM: VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
}
{
@@ -34990,8 +35095,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
}
@@ -35006,8 +35111,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM: VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
}
{
@@ -35020,8 +35125,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
}
@@ -35036,8 +35141,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}
{
@@ -35050,8 +35155,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}
@@ -37365,7 +37470,10 @@
EXCEPTIONS: AVX512-E7NM
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
-PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
+IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
}
@@ -37413,7 +37521,10 @@
EXCEPTIONS: AVX512-E7NM
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
-PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
+IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
+PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
}
@@ -40497,7 +40608,10 @@
ISA_SET: AVX512DQ_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8()
+PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8()
+OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
+IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
+PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8()
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
}
@@ -40511,7 +40625,10 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_WRITER_STORE
-PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
+OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
+IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
+PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
}
@@ -40577,16 +40694,22 @@
# EMITTING VPEXTRW (VPEXTRW-128-2)
{
-ICLASS: VPEXTRW
+ICLASS: VPEXTRW_C5
+DISASM: vpextrw
CPL: 3
CATEGORY: AVX512
EXTENSION: AVX512EVEX
ISA_SET: AVX512BW_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
+
+PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64
OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
-IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512
+IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
+
+PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE
+OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
+IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
}
@@ -40756,7 +40879,10 @@
ISA_SET: AVX512DQ_128N
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
-PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8()
+PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8()
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
+IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
+PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8()
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
}
@@ -40770,7 +40896,10 @@
EXCEPTIONS: AVX512-E9NF
REAL_OPCODE: Y
ATTRIBUTES: DISP8_GPR_READER
-PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()
+PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
+IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
+PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
}
@@ -44731,9 +44860,10 @@
ISA_SET: AVX512F_128
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
-OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
+OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512
}
@@ -44745,9 +44875,10 @@
ISA_SET: AVX512F_128
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
+OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512
}
@@ -44761,9 +44892,10 @@
ISA_SET: AVX512F_256
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
-OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
+OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512
}
@@ -44775,9 +44907,10 @@
ISA_SET: AVX512F_256
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
+OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512
}
@@ -45301,9 +45434,10 @@
ISA_SET: AVX512F_128
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
-OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512
}
@@ -45315,9 +45449,10 @@
ISA_SET: AVX512F_128
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512
}
@@ -45331,9 +45466,10 @@
ISA_SET: AVX512F_256
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
-OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512
}
@@ -45345,9 +45481,10 @@
ISA_SET: AVX512F_256
EXCEPTIONS: AVX512-E4
REAL_OPCODE: Y
+COMMENT: Strange instruction that uses 32b of each 64b input element
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512
}
@@ -52592,8 +52729,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
-IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
+IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
}
{
@@ -52606,8 +52743,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
}
@@ -52622,8 +52759,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
-IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
+IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
}
{
@@ -52636,8 +52773,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
}
@@ -52652,8 +52789,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
-IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
+IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
}
{
@@ -52666,8 +52803,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
-IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
+IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
}
@@ -52682,8 +52819,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
-IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
+IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
}
{
@@ -52696,8 +52833,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
+OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
}
@@ -52712,8 +52849,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
-IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
+IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
}
{
@@ -52726,8 +52863,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
+OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
}
@@ -52742,8 +52879,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MASKOP_EVEX
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
-IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
+IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
}
{
@@ -52756,8 +52893,8 @@
REAL_OPCODE: Y
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
-OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
-IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
+OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
+IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
}
@@ -53606,7 +53743,6 @@
-
###FILE: ./datafiles/avx512ifma/ifma-isa.xed.txt
#BEGIN_LEGAL
