internal/simdgen: make bitwise logic avaialble to all u?int vectors

This CL generates CL 692356.

Change-Id: I4d5da85d4ff7f83df52f4e2e1e082e8ccd6a5883
Reviewed-on: https://go-review.googlesource.com/c/arch/+/692555
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>

internal/simdgen/go.yaml

diff --git a/internal/simdgen/go.yaml b/internal/simdgen/go.yaml
index eb43540..ddab9c3 100644
--- a/internal/simdgen/go.yaml
+++ b/internal/simdgen/go.yaml
@@ -118,6 +118,28 @@
   out:
   - *any
 
+- go: And
+  asm: "VPANDD" # Fill in the gap, And is missing for Uint8x64 and Int8x64
+  inVariant: []
+  in: &twoI8x64
+  - &i8x64
+    go: $t
+    overwriteElementBits: 8
+  - *i8x64
+  out: &oneI8x64
+  - *i8x64
+
+- go: And
+  asm: "VPANDD" # Fill in the gap, And is missing for Uint16x32 and Int16x32
+  inVariant: []
+  in: &twoI16x32
+  - &i16x32
+    go: $t
+    overwriteElementBits: 16
+  - *i16x32
+  out: &oneI16x32
+  - *i16x32
+
 - go: AndNot
   asm: "VPANDN[DQ]?"
   operandOrder: "21" # switch the arg order
@@ -127,6 +149,20 @@
   out:
   - *any
 
+- go: AndNot
+  asm: "VPANDND" # Fill in the gap, AndNot is missing for Uint8x64 and Int8x64
+  operandOrder: "21" # switch the arg order
+  inVariant: []
+  in: *twoI8x64
+  out: *oneI8x64
+
+- go: AndNot
+  asm: "VPANDND" # Fill in the gap, AndNot is missing for Uint16x32 and Int16x32
+  operandOrder: "21" # switch the arg order
+  inVariant: []
+  in: *twoI16x32
+  out: *oneI16x32
+
 - go: Or
   asm: "VPOR[DQ]?"
   in:
@@ -135,6 +171,18 @@
   out:
   - *any
 
+- go: Or
+  asm: "VPORD" # Fill in the gap, Or is missing for Uint8x64 and Int8x64
+  inVariant: []
+  in: *twoI8x64
+  out: *oneI8x64
+
+- go: Or
+  asm: "VPORD" # Fill in the gap, Or is missing for Uint16x32 and Int16x32
+  inVariant: []
+  in: *twoI16x32
+  out: *oneI16x32
+
 - go: Xor
   asm: "VPXOR[DQ]?"
   in:
@@ -142,6 +190,18 @@
   - *any
   out:
   - *any
+
+- go: Xor
+  asm: "VPXORD" # Fill in the gap, Or is missing for Uint8x64 and Int8x64
+  inVariant: []
+  in: *twoI8x64
+  out: *oneI8x64
+
+- go: Xor
+  asm: "VPXORD" # Fill in the gap, Or is missing for Uint16x32 and Int16x32
+  inVariant: []
+  in: *twoI16x32
+  out: *oneI16x32
 # Ints
 - go: Equal
   asm: "V?PCMPEQ[BWDQ]"

internal/simdgen/ops/BitwiseLogic/go.yaml

diff --git a/internal/simdgen/ops/BitwiseLogic/go.yaml b/internal/simdgen/ops/BitwiseLogic/go.yaml
index 0d0f1c8..ab34443 100644
--- a/internal/simdgen/ops/BitwiseLogic/go.yaml
+++ b/internal/simdgen/ops/BitwiseLogic/go.yaml
@@ -42,6 +42,28 @@
   out:
   - *any
 
+- go: And
+  asm: "VPANDD" # Fill in the gap, And is missing for Uint8x64 and Int8x64
+  inVariant: []
+  in: &twoI8x64
+  - &i8x64
+    go: $t
+    overwriteElementBits: 8
+  - *i8x64
+  out: &oneI8x64
+  - *i8x64
+
+- go: And
+  asm: "VPANDD" # Fill in the gap, And is missing for Uint16x32 and Int16x32
+  inVariant: []
+  in: &twoI16x32
+  - &i16x32
+    go: $t
+    overwriteElementBits: 16
+  - *i16x32
+  out: &oneI16x32
+  - *i16x32
+
 - go: AndNot
   asm: "VPANDN[DQ]?"
   operandOrder: "21" # switch the arg order
@@ -51,6 +73,20 @@
   out:
   - *any
 
+- go: AndNot
+  asm: "VPANDND" # Fill in the gap, AndNot is missing for Uint8x64 and Int8x64
+  operandOrder: "21" # switch the arg order
+  inVariant: []
+  in: *twoI8x64
+  out: *oneI8x64
+
+- go: AndNot
+  asm: "VPANDND" # Fill in the gap, AndNot is missing for Uint16x32 and Int16x32
+  operandOrder: "21" # switch the arg order
+  inVariant: []
+  in: *twoI16x32
+  out: *oneI16x32
+
 - go: Or
   asm: "VPOR[DQ]?"
   in:
@@ -59,6 +95,18 @@
   out:
   - *any
 
+- go: Or
+  asm: "VPORD" # Fill in the gap, Or is missing for Uint8x64 and Int8x64
+  inVariant: []
+  in: *twoI8x64
+  out: *oneI8x64
+
+- go: Or
+  asm: "VPORD" # Fill in the gap, Or is missing for Uint16x32 and Int16x32
+  inVariant: []
+  in: *twoI16x32
+  out: *oneI16x32
+
 - go: Xor
   asm: "VPXOR[DQ]?"
   in:
@@ -66,3 +114,15 @@
   - *any
   out:
   - *any
+
+- go: Xor
+  asm: "VPXORD" # Fill in the gap, Or is missing for Uint8x64 and Int8x64
+  inVariant: []
+  in: *twoI8x64
+  out: *oneI8x64
+
+- go: Xor
+  asm: "VPXORD" # Fill in the gap, Or is missing for Uint16x32 and Int16x32
+  inVariant: []
+  in: *twoI16x32
+  out: *oneI16x32
\ No newline at end of file