ppc64/pp64.csv

# POWER ISA 3.1B instruction description.
#
# This file contains comment lines, each beginning with #,
# followed by entries in CSV format.
#
# Each line in the CSV section contains 4 fields:
#
#	instruction mnemonic encoding isa-level
#
# The instruction is the headline from the manual.
# The mnemonic is the instruction mnemonics, separated by | characters.
# The encoding is the encoding, a sequence of name@startbit| describing each bit field in turn or
#    a list of sequences of the form (,sequence)+. A leading comma is used to signify an
#    instruction encoding requiring multiple instruction words.
# The fourth field represents the ISA version where the instruction was introduced as
# stated in Appendix F. of ISA 3.1B
#
"Hash Check X-form","hashchk RB,offset(RA)","31@0|D@6|RA@11|RB@16|754@21|DX@31|","v3.1B"
"Hash Check Privileged X-form","hashchkp RB,offset(RA)","31@0|D@6|RA@11|RB@16|690@21|DX@31|","v3.1B"
"Hash Store X-form","hashst RB,offset(RA)","31@0|D@6|RA@11|RB@16|722@21|DX@31|","v3.1B"
"Hash Store Privileged X-form","hashstp RB,offset(RA)","31@0|D@6|RA@11|RB@16|658@21|DX@31|","v3.1B"
"Byte-Reverse Doubleword X-form","brd RA,RS","31@0|RS@6|RA@11|///@16|187@21|/@31|","v3.1"
"Byte-Reverse Halfword X-form","brh RA,RS","31@0|RS@6|RA@11|///@16|219@21|/@31|","v3.1"
"Byte-Reverse Word X-form","brw RA,RS","31@0|RS@6|RA@11|///@16|155@21|/@31|","v3.1"
"Centrifuge Doubleword X-form","cfuged RA,RS,RB","31@0|RS@6|RA@11|RB@16|220@21|/@31|","v3.1"
"Count Leading Zeros Doubleword under bit Mask X-form","cntlzdm RA,RS,RB","31@0|RS@6|RA@11|RB@16|59@21|/@31|","v3.1"
"Count Trailing Zeros Doubleword under bit Mask X-form","cnttzdm RA,RS,RB","31@0|RS@6|RA@11|RB@16|571@21|/@31|","v3.1"
"DFP Convert From Fixed Quadword Quad X-form","dcffixqq FRTp,VRB","63@0|FRTp@6|0@11|VRB@16|994@21|/@31|","v3.1"
"DFP Convert To Fixed Quadword Quad X-form","dctfixqq VRT,FRBp","63@0|VRT@6|1@11|FRBp@16|994@21|/@31|","v3.1"
"Load VSX Vector Special Value Quadword X-form","lxvkq XT,UIM","60@0|T@6|31@11|UIM@16|360@21|TX@31|","v3.1"
"Load VSX Vector Paired DQ-form","lxvp XTp,DQ(RA)","6@0|Tp@6|TX@10|RA@11|DQ@16|0@28|","v3.1"
"Load VSX Vector Paired Indexed X-form","lxvpx XTp,RA,RB","31@0|Tp@6|TX@10|RA@11|RB@16|333@21|/@31|","v3.1"
"Load VSX Vector Rightmost Byte Indexed X-form","lxvrbx XT,RA,RB","31@0|T@6|RA@11|RB@16|13@21|TX@31|","v3.1"
"Load VSX Vector Rightmost Doubleword Indexed X-form","lxvrdx XT,RA,RB","31@0|T@6|RA@11|RB@16|109@21|TX@31|","v3.1"
"Load VSX Vector Rightmost Halfword Indexed X-form","lxvrhx XT,RA,RB","31@0|T@6|RA@11|RB@16|45@21|TX@31|","v3.1"
"Load VSX Vector Rightmost Word Indexed X-form","lxvrwx XT,RA,RB","31@0|T@6|RA@11|RB@16|77@21|TX@31|","v3.1"
"Move to VSR Byte Mask VX-form","mtvsrbm VRT,RB","4@0|VRT@6|16@11|RB@16|1602@21|","v3.1"
"Move To VSR Byte Mask Immediate DX-form","mtvsrbmi VRT,bm","4@0|VRT@6|b1@11|b0@16|10@26|b2@31|","v3.1"
"Move to VSR Doubleword Mask VX-form","mtvsrdm VRT,RB","4@0|VRT@6|19@11|RB@16|1602@21|","v3.1"
"Move to VSR Halfword Mask VX-form","mtvsrhm VRT,RB","4@0|VRT@6|17@11|RB@16|1602@21|","v3.1"
"Move to VSR Quadword Mask VX-form","mtvsrqm VRT,RB","4@0|VRT@6|20@11|RB@16|1602@21|","v3.1"
"Move to VSR Word Mask VX-form","mtvsrwm VRT,RB","4@0|VRT@6|18@11|RB@16|1602@21|","v3.1"
"Prefixed Add Immediate MLS:D-form","paddi RT,RA,SI,R",",1@0|2@6|0@8|//@9|R@11|//@12|si0@14|,14@0|RT@6|RA@11|si1@16|","v3.1"
"Parallel Bits Deposit Doubleword X-form","pdepd RA,RS,RB","31@0|RS@6|RA@11|RB@16|156@21|/@31|","v3.1"
"Parallel Bits Extract Doubleword X-form","pextd RA,RS,RB","31@0|RS@6|RA@11|RB@16|188@21|/@31|","v3.1"
"Prefixed Load Byte and Zero MLS:D-form","plbz RT,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,34@0|RT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Doubleword 8LS:D-form","pld RT,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,57@0|RT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Floating-Point Double MLS:D-form","plfd FRT,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,50@0|FRT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Floating-Point Single MLS:D-form","plfs FRT,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,48@0|FRT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Halfword Algebraic MLS:D-form","plha RT,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,42@0|RT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Halfword and Zero MLS:D-form","plhz RT,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,40@0|RT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Quadword 8LS:D-form","plq RTp,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,56@0|RTp@6|RA@11|d1@16|","v3.1"
"Prefixed Load Word Algebraic 8LS:D-form","plwa RT,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,41@0|RT@6|RA@11|d1@16|","v3.1"
"Prefixed Load Word and Zero MLS:D-form","plwz RT,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,32@0|RT@6|RA@11|d1@16|","v3.1"
"Prefixed Load VSX Scalar Doubleword 8LS:D-form","plxsd VRT,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,42@0|VRT@6|RA@11|d1@16|","v3.1"
"Prefixed Load VSX Scalar Single-Precision 8LS:D-form","plxssp VRT,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,43@0|VRT@6|RA@11|d1@16|","v3.1"
"Prefixed Load VSX Vector 8LS:D-form","plxv XT,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,25@0|TX@5|T@6|RA@11|d1@16|","v3.1"
"Prefixed Load VSX Vector Paired 8LS:D-form","plxvp XTp,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,58@0|Tp@6|TX@10|RA@11|d1@16|","v3.1"
"Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) MMIRR:XX3-form","pmxvbf16ger2 AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|51@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate MMIRR:XX3-form","pmxvbf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|242@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate MMIRR:XX3-form","pmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|114@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate MMIRR:XX3-form","pmxvbf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|178@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvbf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|50@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) MMIRR:XX3-form","pmxvf16ger2 AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|19@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate MMIRR:XX3-form","pmxvf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|210@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate MMIRR:XX3-form","pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|82@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate MMIRR:XX3-form","pmxvf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|146@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|18@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form","pmxvf32ger AT,XA,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|27@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form","pmxvf32gernn AT,XA,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|218@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form","pmxvf32gernp AT,XA,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|90@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form","pmxvf32gerpn AT,XA,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|154@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvf32gerpp AT,XA,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|26@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form","pmxvf64ger AT,XAp,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|59@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form","pmxvf64gernn AT,XAp,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|250@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form","pmxvf64gernp AT,XAp,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|122@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form","pmxvf64gerpn AT,XAp,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|186@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvf64gerpp AT,XAp,XB,XMSK,YMSK",",1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|58@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) MMIRR:XX3-form","pmxvi16ger2 AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|75@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvi16ger2pp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|107@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation MMIRR:XX3-form","pmxvi16ger2s AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvi16ger2spp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|42@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) MMIRR:XX3-form","pmxvi4ger8 AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvi4ger8pp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|34@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) MMIRR:XX3-form","pmxvi8ger4 AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@20|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|3@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@20|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|2@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate MMIRR:XX3-form","pmxvi8ger4spp AT,XA,XB,XMSK,YMSK,PMSK",",1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@20|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|99@21|AX@29|BX@30|/@31|","v3.1"
"Prefixed Nop MRR:*-form","pnop",",1@0|3@6|0@8|///@12|0@14|//@31|,///@0|","v3.1"
"Prefixed Store Byte MLS:D-form","pstb RS,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,38@0|RS@6|RA@11|d1@16|","v3.1"
"Prefixed Store Doubleword 8LS:D-form","pstd RS,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,61@0|RS@6|RA@11|d1@16|","v3.1"
"Prefixed Store Floating-Point Double MLS:D-form","pstfd FRS,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,54@0|FRS@6|RA@11|d1@16|","v3.1"
"Prefixed Store Floating-Point Single MLS:D-form","pstfs FRS,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,52@0|FRS@6|RA@11|d1@16|","v3.1"
"Prefixed Store Halfword MLS:D-form","psth RS,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,44@0|RS@6|RA@11|d1@16|","v3.1"
"Prefixed Store Quadword 8LS:D-form","pstq RSp,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,60@0|RSp@6|RA@11|d1@16|","v3.1"
"Prefixed Store Word MLS:D-form","pstw RS,D(RA),R",",1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,36@0|RS@6|RA@11|d1@16|","v3.1"
"Prefixed Store VSX Scalar Doubleword 8LS:D-form","pstxsd VRS,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,46@0|VRS@6|RA@11|d1@16|","v3.1"
"Prefixed Store VSX Scalar Single-Precision 8LS:D-form","pstxssp VRS,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,47@0|VRS@6|RA@11|d1@16|","v3.1"
"Prefixed Store VSX Vector 8LS:D-form","pstxv XS,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,27@0|SX@5|S@6|RA@11|d1@16|","v3.1"
"Prefixed Store VSX Vector Paired 8LS:D-form","pstxvp XSp,D(RA),R",",1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,62@0|Sp@6|SX@10|RA@11|d1@16|","v3.1"
"Set Boolean Condition X-form","setbc RT,BI","31@0|RT@6|BI@11|///@16|384@21|/@31|","v3.1"
"Set Boolean Condition Reverse X-form","setbcr RT,BI","31@0|RT@6|BI@11|///@16|416@21|/@31|","v3.1"
"Set Negative Boolean Condition X-form","setnbc RT,BI","31@0|RT@6|BI@11|///@16|448@21|/@31|","v3.1"
"Set Negative Boolean Condition Reverse X-form","setnbcr RT,BI","31@0|RT@6|BI@11|///@16|480@21|/@31|","v3.1"
"Store VSX Vector Paired DQ-form","stxvp XSp,DQ(RA)","6@0|Sp@6|SX@10|RA@11|DQ@16|1@28|","v3.1"
"Store VSX Vector Paired Indexed X-form","stxvpx XSp,RA,RB","31@0|Sp@6|SX@10|RA@11|RB@16|461@21|/@31|","v3.1"
"Store VSX Vector Rightmost Byte Indexed X-form","stxvrbx XS,RA,RB","31@0|S@6|RA@11|RB@16|141@21|SX@31|","v3.1"
"Store VSX Vector Rightmost Doubleword Indexed X-form","stxvrdx XS,RA,RB","31@0|S@6|RA@11|RB@16|237@21|SX@31|","v3.1"
"Store VSX Vector Rightmost Halfword Indexed X-form","stxvrhx XS,RA,RB","31@0|S@6|RA@11|RB@16|173@21|SX@31|","v3.1"
"Store VSX Vector Rightmost Word Indexed X-form","stxvrwx XS,RA,RB","31@0|S@6|RA@11|RB@16|205@21|SX@31|","v3.1"
"Vector Centrifuge Doubleword VX-form","vcfuged VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1357@21|","v3.1"
"Vector Clear Leftmost Bytes VX-form","vclrlb VRT,VRA,RB","4@0|VRT@6|VRA@11|RB@16|397@21|","v3.1"
"Vector Clear Rightmost Bytes VX-form","vclrrb VRT,VRA,RB","4@0|VRT@6|VRA@11|RB@16|461@21|","v3.1"
"Vector Count Leading Zeros Doubleword under bit Mask VX-form","vclzdm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1924@21|","v3.1"
"Vector Compare Equal Quadword VC-form","vcmpequq VRT,VRA,VRB (Rc=0)|vcmpequq. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|455@22|","v3.1"
"Vector Compare Greater Than Signed Quadword VC-form","vcmpgtsq VRT,VRA,VRB (Rc=0)|vcmpgtsq. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|903@22|","v3.1"
"Vector Compare Greater Than Unsigned Quadword VC-form","vcmpgtuq VRT,VRA,VRB (Rc=0)|vcmpgtuq. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|647@22|","v3.1"
"Vector Compare Signed Quadword VX-form","vcmpsq BF,VRA,VRB","4@0|BF@6|//@9|VRA@11|VRB@16|321@21|","v3.1"
"Vector Compare Unsigned Quadword VX-form","vcmpuq BF,VRA,VRB","4@0|BF@6|//@9|VRA@11|VRB@16|257@21|","v3.1"
"Vector Count Mask Bits Byte VX-form","vcntmbb RT,VRB,MP","4@0|RT@6|12@11|MP@15|VRB@16|1602@21|","v3.1"
"Vector Count Mask Bits Doubleword VX-form","vcntmbd RT,VRB,MP","4@0|RT@6|15@11|MP@15|VRB@16|1602@21|","v3.1"
"Vector Count Mask Bits Halfword VX-form","vcntmbh RT,VRB,MP","4@0|RT@6|13@11|MP@15|VRB@16|1602@21|","v3.1"
"Vector Count Mask Bits Word VX-form","vcntmbw RT,VRB,MP","4@0|RT@6|14@11|MP@15|VRB@16|1602@21|","v3.1"
"Vector Count Trailing Zeros Doubleword under bit Mask VX-form","vctzdm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1988@21|","v3.1"
"Vector Divide Extended Signed Doubleword VX-form","vdivesd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|971@21|","v3.1"
"Vector Divide Extended Signed Quadword VX-form","vdivesq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|779@21|","v3.1"
"Vector Divide Extended Signed Word VX-form","vdivesw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|907@21|","v3.1"
"Vector Divide Extended Unsigned Doubleword VX-form","vdiveud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|715@21|","v3.1"
"Vector Divide Extended Unsigned Quadword VX-form","vdiveuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|523@21|","v3.1"
"Vector Divide Extended Unsigned Word VX-form","vdiveuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|651@21|","v3.1"
"Vector Divide Signed Doubleword VX-form","vdivsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|459@21|","v3.1"
"Vector Divide Signed Quadword VX-form","vdivsq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|267@21|","v3.1"
"Vector Divide Signed Word VX-form","vdivsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|395@21|","v3.1"
"Vector Divide Unsigned Doubleword VX-form","vdivud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|203@21|","v3.1"
"Vector Divide Unsigned Quadword VX-form","vdivuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|11@21|","v3.1"
"Vector Divide Unsigned Word VX-form","vdivuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|139@21|","v3.1"
"Vector Expand Byte Mask VX-form","vexpandbm VRT,VRB","4@0|VRT@6|0@11|VRB@16|1602@21|","v3.1"
"Vector Expand Doubleword Mask VX-form","vexpanddm VRT,VRB","4@0|VRT@6|3@11|VRB@16|1602@21|","v3.1"
"Vector Expand Halfword Mask VX-form","vexpandhm VRT,VRB","4@0|VRT@6|1@11|VRB@16|1602@21|","v3.1"
"Vector Expand Quadword Mask VX-form","vexpandqm VRT,VRB","4@0|VRT@6|4@11|VRB@16|1602@21|","v3.1"
"Vector Expand Word Mask VX-form","vexpandwm VRT,VRB","4@0|VRT@6|2@11|VRB@16|1602@21|","v3.1"
"Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form","vextddvlx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|30@26|","v3.1"
"Vector Extract Double Doubleword to VSR using GPR-specified Right-Index VA-form","vextddvrx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|31@26|","v3.1"
"Vector Extract Double Unsigned Byte to VSR using GPR-specified Left-Index VA-form","vextdubvlx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|24@26|","v3.1"
"Vector Extract Double Unsigned Byte to VSR using GPR-specified Right-Index VA-form","vextdubvrx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|25@26|","v3.1"
"Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form","vextduhvlx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|26@26|","v3.1"
"Vector Extract Double Unsigned Halfword to VSR using GPR-specified Right-Index VA-form","vextduhvrx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|27@26|","v3.1"
"Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form","vextduwvlx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|28@26|","v3.1"
"Vector Extract Double Unsigned Word to VSR using GPR-specified Right-Index VA-form","vextduwvrx VRT,VRA,VRB,RC","4@0|VRT@6|VRA@11|VRB@16|RC@21|29@26|","v3.1"
"Vector Extract Byte Mask VX-form","vextractbm RT,VRB","4@0|RT@6|8@11|VRB@16|1602@21|","v3.1"
"Vector Extract Doubleword Mask VX-form","vextractdm RT,VRB","4@0|RT@6|11@11|VRB@16|1602@21|","v3.1"
"Vector Extract Halfword Mask VX-form","vextracthm RT,VRB","4@0|RT@6|9@11|VRB@16|1602@21|","v3.1"
"Vector Extract Quadword Mask VX-form","vextractqm RT,VRB","4@0|RT@6|12@11|VRB@16|1602@21|","v3.1"
"Vector Extract Word Mask VX-form","vextractwm RT,VRB","4@0|RT@6|10@11|VRB@16|1602@21|","v3.1"
"Vector Extend Sign Doubleword to Quadword VX-form","vextsd2q VRT,VRB","4@0|VRT@6|27@11|VRB@16|1538@21|","v3.1"
"Vector Gather every Nth Bit VX-form","vgnb RT,VRB,N","4@0|RT@6|//@11|N@13|VRB@16|1228@21|","v3.1"
"Vector Insert Byte from GPR using GPR-specified Left-Index VX-form","vinsblx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|527@21|","v3.1"
"Vector Insert Byte from GPR using GPR-specified Right-Index VX-form","vinsbrx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|783@21|","v3.1"
"Vector Insert Byte from VSR using GPR-specified Left-Index VX-form","vinsbvlx VRT,RA,VRB","4@0|VRT@6|RA@11|VRB@16|15@21|","v3.1"
"Vector Insert Byte from VSR using GPR-specified Right-Index VX-form","vinsbvrx VRT,RA,VRB","4@0|VRT@6|RA@11|VRB@16|271@21|","v3.1"
"Vector Insert Doubleword from GPR using immediate-specified index VX-form","vinsd VRT,RB,UIM","4@0|VRT@6|/@11|UIM@12|RB@16|463@21|","v3.1"
"Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-form","vinsdlx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|719@21|","v3.1"
"Vector Insert Doubleword from GPR using GPR-specified Right-Index VX-form","vinsdrx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|975@21|","v3.1"
"Vector Insert Halfword from GPR using GPR-specified Left-Index VX-form","vinshlx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|591@21|","v3.1"
"Vector Insert Halfword from GPR using GPR-specified Right-Index VX-form","vinshrx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|847@21|","v3.1"
"Vector Insert Halfword from VSR using GPR-specified Left-Index VX-form","vinshvlx VRT,RA,VRB","4@0|VRT@6|RA@11|VRB@16|79@21|","v3.1"
"Vector Insert Halfword from VSR using GPR-specified Right-Index VX-form","vinshvrx VRT,RA,VRB","4@0|VRT@6|RA@11|VRB@16|335@21|","v3.1"
"Vector Insert Word from GPR using immediate-specified index VX-form","vinsw VRT,RB,UIM","4@0|VRT@6|/@11|UIM@12|RB@16|207@21|","v3.1"
"Vector Insert Word from GPR using GPR-specified Left-Index VX-form","vinswlx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|655@21|","v3.1"
"Vector Insert Word from GPR using GPR-specified Right-Index VX-form","vinswrx VRT,RA,RB","4@0|VRT@6|RA@11|RB@16|911@21|","v3.1"
"Vector Insert Word from VSR using GPR-specified Left-Index VX-form","vinswvlx VRT,RA,VRB","4@0|VRT@6|RA@11|VRB@16|143@21|","v3.1"
"Vector Insert Word from VSR using GPR-specified Left-Index VX-form","vinswvrx VRT,RA,VRB","4@0|VRT@6|RA@11|VRB@16|399@21|","v3.1"
"Vector Modulo Signed Doubleword VX-form","vmodsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1995@21|","v3.1"
"Vector Modulo Signed Quadword VX-form","vmodsq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1803@21|","v3.1"
"Vector Modulo Signed Word VX-form","vmodsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1931@21|","v3.1"
"Vector Modulo Unsigned Doubleword VX-form","vmodud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1739@21|","v3.1"
"Vector Modulo Unsigned Quadword VX-form","vmoduq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1547@21|","v3.1"
"Vector Modulo Unsigned Word VX-form","vmoduw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1675@21|","v3.1"
"Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form","vmsumcud VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|23@26|","v3.1"
"Vector Multiply Even Signed Doubleword VX-form","vmulesd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|968@21|","v3.1"
"Vector Multiply Even Unsigned Doubleword VX-form","vmuleud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|712@21|","v3.1"
"Vector Multiply High Signed Doubleword VX-form","vmulhsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|969@21|","v3.1"
"Vector Multiply High Signed Word VX-form","vmulhsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|905@21|","v3.1"
"Vector Multiply High Unsigned Doubleword VX-form","vmulhud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|713@21|","v3.1"
"Vector Multiply High Unsigned Word VX-form","vmulhuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|649@21|","v3.1"
"Vector Multiply Low Doubleword VX-form","vmulld VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|457@21|","v3.1"
"Vector Multiply Odd Signed Doubleword VX-form","vmulosd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|456@21|","v3.1"
"Vector Multiply Odd Unsigned Doubleword VX-form","vmuloud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|200@21|","v3.1"
"Vector Parallel Bits Deposit Doubleword VX-form","vpdepd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1485@21|","v3.1"
"Vector Parallel Bits Extract Doubleword VX-form","vpextd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1421@21|","v3.1"
"Vector Rotate Left Quadword VX-form","vrlq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|5@21|","v3.1"
"Vector Rotate Left Quadword then Mask Insert VX-form","vrlqmi VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|69@21|","v3.1"
"Vector Rotate Left Quadword then AND with Mask VX-form","vrlqnm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|325@21|","v3.1"
"Vector Shift Left Double by Bit Immediate VN-form","vsldbi VRT,VRA,VRB,SH","4@0|VRT@6|VRA@11|VRB@16|0@21|SH@23|22@26|","v3.1"
"Vector Shift Left Quadword VX-form","vslq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|261@21|","v3.1"
"Vector Shift Right Algebraic Quadword VX-form","vsraq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|773@21|","v3.1"
"Vector Shift Right Double by Bit Immediate VN-form","vsrdbi VRT,VRA,VRB,SH","4@0|VRT@6|VRA@11|VRB@16|1@21|SH@23|22@26|","v3.1"
"Vector Shift Right Quadword VX-form","vsrq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|517@21|","v3.1"
"Vector String Isolate Byte Left-justified VX-form","vstribl VRT,VRB (Rc=0)|vstribl. VRT,VRB (Rc=1)","4@0|VRT@6|0@11|VRB@16|Rc@21|13@22|","v3.1"
"Vector String Isolate Byte Right-justified VX-form","vstribr VRT,VRB (Rc=0)|vstribr. VRT,VRB (Rc=1)","4@0|VRT@6|1@11|VRB@16|Rc@21|13@22|","v3.1"
"Vector String Isolate Halfword Left-justified VX-form","vstrihl VRT,VRB (Rc=0)|vstrihl. VRT,VRB (Rc=1)","4@0|VRT@6|2@11|VRB@16|Rc@21|13@22|","v3.1"
"Vector String Isolate Halfword Right-justified VX-form","vstrihr VRT,VRB (Rc=0)|vstrihr. VRT,VRB (Rc=1)","4@0|VRT@6|3@11|VRB@16|Rc@21|13@22|","v3.1"
"VSX Scalar Compare Equal Quad-Precision X-form","xscmpeqqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|68@21|/@31|","v3.1"
"VSX Scalar Compare Greater Than or Equal Quad-Precision X-form","xscmpgeqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|196@21|/@31|","v3.1"
"VSX Scalar Compare Greater Than Quad-Precision X-form","xscmpgtqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|228@21|/@31|","v3.1"
"VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword X-form","xscvqpsqz VRT,VRB","63@0|VRT@6|8@11|VRB@16|836@21|/@31|","v3.1"
"VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword X-form","xscvqpuqz VRT,VRB","63@0|VRT@6|0@11|VRB@16|836@21|/@31|","v3.1"
"VSX Scalar Convert with round Signed Quadword to Quad-Precision X-form","xscvsqqp VRT,VRB","63@0|VRT@6|11@11|VRB@16|836@21|/@31|","v3.1"
"VSX Scalar Convert with round Unsigned Quadword to Quad-Precision X-form","xscvuqqp VRT,VRB","63@0|VRT@6|3@11|VRB@16|836@21|/@31|","v3.1"
"VSX Scalar Maximum Type-C Quad-Precision X-form","xsmaxcqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|676@21|/@31|","v3.1"
"VSX Scalar Minimum Type-C Quad-Precision X-form","xsmincqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|740@21|/@31|","v3.1"
"VSX Vector bfloat16 GER (Rank-2 Update) XX3-form","xvbf16ger2 AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|51@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate XX3-form","xvbf16ger2nn AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|242@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate XX3-form","xvbf16ger2np AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|114@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate XX3-form","xvbf16ger2pn AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|178@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate XX3-form","xvbf16ger2pp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|50@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector Convert bfloat16 to Single-Precision format Non-signaling XX2-form","xvcvbf16spn XT,XB","60@0|T@6|16@11|B@16|475@21|BX@30|TX@31|","v3.1"
"VSX Vector Convert with round Single-Precision to bfloat16 format XX2-form","xvcvspbf16 XT,XB","60@0|T@6|17@11|B@16|475@21|BX@30|TX@31|","v3.1"
"VSX Vector 16-bit Floating-Point GER (rank-2 update) XX3-form","xvf16ger2 AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|19@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate XX3-form","xvf16ger2nn AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|210@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate XX3-form","xvf16ger2np AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|82@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate XX3-form","xvf16ger2pn AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|146@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate XX3-form","xvf16ger2pp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|18@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 32-bit Floating-Point GER (rank-1 update) XX3-form","xvf32ger AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|27@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form","xvf32gernn AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|218@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form","xvf32gernp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|90@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form","xvf32gerpn AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|154@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form","xvf32gerpp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|26@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 64-bit Floating-Point GER (rank-1 update) XX3-form","xvf64ger AT,XAp,XB","59@0|AT@6|//@9|Ap@11|B@16|59@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form","xvf64gernn AT,XAp,XB","59@0|AT@6|//@9|Ap@11|B@16|250@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form","xvf64gernp AT,XAp,XB","59@0|AT@6|//@9|Ap@11|B@16|122@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form","xvf64gerpn AT,XAp,XB","59@0|AT@6|//@9|Ap@11|B@16|186@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form","xvf64gerpp AT,XAp,XB","59@0|AT@6|//@9|Ap@11|B@16|58@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Signed Integer GER (rank-2 update) XX3-form","xvi16ger2 AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|75@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate XX3-form","xvi16ger2pp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|107@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation XX3-form","xvi16ger2s AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate XX3-form","xvi16ger2spp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|42@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 4-bit Signed Integer GER (rank-8 update) XX3-form","xvi4ger8 AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate XX3-form","xvi4ger8pp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|34@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) XX3-form","xvi8ger4 AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|3@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate XX3-form","xvi8ger4pp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|2@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate XX3-form","xvi8ger4spp AT,XA,XB","59@0|AT@6|//@9|A@11|B@16|99@21|AX@29|BX@30|/@31|","v3.1"
"VSX Vector Test Least-Significant Bit by Byte XX2-form","xvtlsbb BF,XB","60@0|BF@6|//@9|2@11|B@16|475@21|BX@30|/@31|","v3.1"
"VSX Vector Blend Variable Byte 8RR:XX4-form","xxblendvb XT,XA,XB,XC",",1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|0@26|CX@28|AX@29|BX@30|TX@31|","v3.1"
"VSX Vector Blend Variable Doubleword 8RR:XX4-form","xxblendvd XT,XA,XB,XC",",1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|","v3.1"
"VSX Vector Blend Variable Halfword 8RR:XX4-form","xxblendvh XT,XA,XB,XC",",1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|1@26|CX@28|AX@29|BX@30|TX@31|","v3.1"
"VSX Vector Blend Variable Word 8RR:XX4-form","xxblendvw XT,XA,XB,XC",",1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|2@26|CX@28|AX@29|BX@30|TX@31|","v3.1"
"VSX Vector Evaluate 8RR-XX4-form","xxeval XT,XA,XB,XC,IMM",",1@0|1@6|0@8|//@12|///@14|IMM@24|,34@0|T@6|A@11|B@16|C@21|1@26|CX@28|AX@29|BX@30|TX@31|","v3.1"
"VSX Vector Generate PCV from Byte Mask X-form","xxgenpcvbm XT,VRB,IMM","60@0|T@6|IMM@11|VRB@16|916@21|TX@31|","v3.1"
"VSX Vector Generate PCV from Doubleword Mask X-form","xxgenpcvdm XT,VRB,IMM","60@0|T@6|IMM@11|VRB@16|949@21|TX@31|","v3.1"
"VSX Vector Generate PCV from Halfword Mask X-form","xxgenpcvhm XT,VRB,IMM","60@0|T@6|IMM@11|VRB@16|917@21|TX@31|","v3.1"
"VSX Vector Generate PCV from Word Mask X-form","xxgenpcvwm XT,VRB,IMM","60@0|T@6|IMM@11|VRB@16|948@21|TX@31|","v3.1"
"VSX Move From Accumulator X-form","xxmfacc AS","31@0|AS@6|//@9|0@11|///@16|177@21|/@31|","v3.1"
"VSX Move To Accumulator X-form","xxmtacc AT","31@0|AT@6|//@9|1@11|///@16|177@21|/@31|","v3.1"
"VSX Vector Permute Extended 8RR:XX4-form","xxpermx XT,XA,XB,XC,UIM",",1@0|1@6|0@8|//@12|///@14|UIM@29|,34@0|T@6|A@11|B@16|C@21|0@26|CX@28|AX@29|BX@30|TX@31|","v3.1"
"VSX Set Accumulator to Zero X-form","xxsetaccz AT","31@0|AT@6|//@9|3@11|///@16|177@21|/@31|","v3.1"
"VSX Vector Splat Immediate32 Doubleword Indexed 8RR:D-form","xxsplti32dx XT,IX,IMM32",",1@0|1@6|0@8|//@12|//@14|imm0@16|,32@0|T@6|0@11|IX@14|TX@15|imm1@16|","v3.1"
"VSX Vector Splat Immediate Double-Precision 8RR:D-form","xxspltidp XT,IMM32",",1@0|1@6|0@8|//@12|//@14|imm0@16|,32@0|T@6|2@11|TX@15|imm1@16|","v3.1"
"VSX Vector Splat Immediate Word 8RR:D-form","xxspltiw XT,IMM32",",1@0|1@6|0@8|//@12|//@14|imm0@16|,32@0|T@6|3@11|TX@15|imm1@16|","v3.1"
"Ultravisor Message Clear X-form","msgclru RB","31@0|///@6|///@11|RB@16|110@21|/@31|","v3.0C"
"Ultravisor Message SendX-form","msgsndu RB","31@0|///@6|///@11|RB@16|78@21|/@31|","v3.0C"
"Ultravisor Return From Interrupt Doubleword XL-form","urfid","19@0|///@6|///@11|///@16|306@21|/@31|","v3.0C"
"Add Extended using alternate carry bit Z23-form","addex RT,RA,RB,CY","31@0|RT@6|RA@11|RB@16|CY@21|170@23|/@31|","v3.0B"
"Move From FPSCR Control & Set DRN X-form","mffscdrn FRT,FRB","63@0|FRT@6|20@11|FRB@16|583@21|/@31|","v3.0B"
"Move From FPSCR Control & Set DRN Immediate X-form","mffscdrni FRT,DRM","63@0|FRT@6|21@11|//@16|DRM@18|583@21|/@31|","v3.0B"
"Move From FPSCR & Clear Enables X-form","mffsce FRT","63@0|FRT@6|1@11|///@16|583@21|/@31|","v3.0B"
"Move From FPSCR Control & Set RN X-form","mffscrn FRT,FRB","63@0|FRT@6|22@11|FRB@16|583@21|/@31|","v3.0B"
"Move From FPSCR Control & Set RN Immediate X-form","mffscrni FRT,RM","63@0|FRT@6|23@11|///@16|RM@19|583@21|/@31|","v3.0B"
"Move From FPSCR Lightweight X-form","mffsl FRT","63@0|FRT@6|24@11|///@16|583@21|/@31|","v3.0B"
"SLB Invalidate All Global X-form","slbiag RS, L","31@0|RS@6|///@11|L@15|///@16|850@21|/@31|","v3.0B"
"Vector Multiply-Sum Unsigned Doubleword Modulo VA-form","vmsumudm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|35@26|","v3.0B"
"Add PC Immediate Shifted DX-form","addpcis RT,D","19@0|RT@6|d1@11|d0@16|2@26|d2@31|","v3.0"
"Decimal Convert From National VX-form","bcdcfn. VRT,VRB,PS","4@0|VRT@6|7@11|VRB@16|1@21|PS@22|385@23|","v3.0"
"Decimal Convert From Signed Quadword VX-form","bcdcfsq. VRT,VRB,PS","4@0|VRT@6|2@11|VRB@16|1@21|PS@22|385@23|","v3.0"
"Decimal Convert From Zoned VX-form","bcdcfz. VRT,VRB,PS","4@0|VRT@6|6@11|VRB@16|1@21|PS@22|385@23|","v3.0"
"Decimal Copy Sign VX-form","bcdcpsgn. VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|833@21|","v3.0"
"Decimal Convert To National VX-form","bcdctn. VRT,VRB","4@0|VRT@6|5@11|VRB@16|1@21|/@22|385@23|","v3.0"
"Decimal Convert To Signed Quadword VX-form","bcdctsq. VRT,VRB","4@0|VRT@6|0@11|VRB@16|1@21|/@22|385@23|","v3.0"
"Decimal Convert To Zoned VX-form","bcdctz. VRT,VRB,PS","4@0|VRT@6|4@11|VRB@16|1@21|PS@22|385@23|","v3.0"
"Decimal Shift VX-form","bcds. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|193@23|","v3.0"
"Decimal Set Sign VX-form","bcdsetsgn. VRT,VRB,PS","4@0|VRT@6|31@11|VRB@16|1@21|PS@22|385@23|","v3.0"
"Decimal Shift and Round VX-form","bcdsr. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|449@23|","v3.0"
"Decimal Truncate VX-form","bcdtrunc. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|257@23|","v3.0"
"Decimal Unsigned Shift VX-form","bcdus. VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1@21|/@22|129@23|","v3.0"
"Decimal Unsigned Truncate VX-form","bcdutrunc. VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1@21|/@22|321@23|","v3.0"
"Compare Equal Byte X-form","cmpeqb BF,RA,RB","31@0|BF@6|//@9|RA@11|RB@16|224@21|/@31|","v3.0"
"Compare Ranged Byte X-form","cmprb BF,L,RA,RB","31@0|BF@6|/@9|L@10|RA@11|RB@16|192@21|/@31|","v3.0"
"Count Trailing Zeros Doubleword X-form","cnttzd RA,RS (Rc=0)|cnttzd. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|570@21|Rc@31|","v3.0"
"Count Trailing Zeros Word X-form","cnttzw RA,RS (Rc=0)|cnttzw. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|538@21|Rc@31|","v3.0"
"Copy X-form","copy RA,RB","31@0|///@6|1@10|RA@11|RB@16|774@21|/@31|","v3.0"
"Copy-Paste Abort X-form","cpabort","31@0|///@6|///@11|///@16|838@21|/@31|","v3.0"
"Deliver A Random Number X-form","darn RT,L","31@0|RT@6|///@11|L@14|///@16|755@21|/@31|","v3.0"
"DFP Test Significance Immediate X-form","dtstsfi BF,UIM,FRB","59@0|BF@6|/@9|UIM@10|FRB@16|675@21|/@31|","v3.0"
"DFP Test Significance Immediate Quad X-form","dtstsfiq BF,UIM,FRBp","63@0|BF@6|/@9|UIM@10|FRBp@16|675@21|/@31|","v3.0"
"Extend Sign Word and Shift Left Immediate XS-form","extswsli RA,RS,SH (Rc=0)|extswsli. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|sh@16|445@21|sh@30|Rc@31|","v3.0"
"Load Doubleword ATomic X-form","ldat RT,RA,FC","31@0|RT@6|RA@11|FC@16|614@21|/@31|","v3.0"
"Load Word ATomic X-form","lwat RT,RA,FC","31@0|RT@6|RA@11|FC@16|582@21|/@31|","v3.0"
"Load VSX Scalar Doubleword DS-form","lxsd VRT,DS(RA)","57@0|VRT@6|RA@11|DS@16|2@30|","v3.0"
"Load VSX Scalar as Integer Byte & Zero Indexed X-form","lxsibzx XT,RA,RB","31@0|T@6|RA@11|RB@16|781@21|TX@31|","v3.0"
"Load VSX Scalar as Integer Halfword & Zero Indexed X-form","lxsihzx XT,RA,RB","31@0|T@6|RA@11|RB@16|813@21|TX@31|","v3.0"
"Load VSX Scalar Single-Precision DS-form","lxssp VRT,DS(RA)","57@0|VRT@6|RA@11|DS@16|3@30|","v3.0"
"Load VSX Vector DQ-form","lxv XT,DQ(RA)","61@0|T@6|RA@11|DQ@16|TX@28|1@29|","v3.0"
"Load VSX Vector Byte*16 Indexed X-form","lxvb16x XT,RA,RB","31@0|T@6|RA@11|RB@16|876@21|TX@31|","v3.0"
"Load VSX Vector Halfword*8 Indexed X-form","lxvh8x XT,RA,RB","31@0|T@6|RA@11|RB@16|812@21|TX@31|","v3.0"
"Load VSX Vector with Length X-form","lxvl XT,RA,RB","31@0|T@6|RA@11|RB@16|269@21|TX@31|","v3.0"
"Load VSX Vector with Length Left-justified X-form","lxvll XT,RA,RB","31@0|T@6|RA@11|RB@16|301@21|TX@31|","v3.0"
"Load VSX Vector Word & Splat Indexed X-form","lxvwsx XT,RA,RB","31@0|T@6|RA@11|RB@16|364@21|TX@31|","v3.0"
"Load VSX Vector Indexed X-form","lxvx XT,RA,RB","31@0|T@6|RA@11|RB@16|4@21|/@25|12@26|TX@31|","v3.0"
"Multiply-Add High Doubleword VA-form","maddhd RT,RA,RB,RC","4@0|RT@6|RA@11|RB@16|RC@21|48@26|","v3.0"
"Multiply-Add High Doubleword Unsigned VA-form","maddhdu RT,RA,RB,RC","4@0|RT@6|RA@11|RB@16|RC@21|49@26|","v3.0"
"Multiply-Add Low Doubleword VA-form","maddld RT,RA,RB,RC","4@0|RT@6|RA@11|RB@16|RC@21|51@26|","v3.0"
"Move to CR from XER Extended X-form","mcrxrx BF","31@0|BF@6|//@9|///@11|///@16|576@21|/@31|","v3.0"
"Move From VSR Lower Doubleword X-form","mfvsrld RA,XS","31@0|S@6|RA@11|///@16|307@21|SX@31|","v3.0"
"Modulo Signed Doubleword X-form","modsd RT,RA,RB","31@0|RT@6|RA@11|RB@16|777@21|/@31|","v3.0"
"Modulo Signed Word X-form","modsw RT,RA,RB","31@0|RT@6|RA@11|RB@16|779@21|/@31|","v3.0"
"Modulo Unsigned Doubleword X-form","modud RT,RA,RB","31@0|RT@6|RA@11|RB@16|265@21|/@31|","v3.0"
"Modulo Unsigned Word X-form","moduw RT,RA,RB","31@0|RT@6|RA@11|RB@16|267@21|/@31|","v3.0"
"Message Synchronize X-form","msgsync","31@0|///@6|///@11|///@16|886@21|/@31|","v3.0"
"Move To VSR Double Doubleword X-form","mtvsrdd XT,RA,RB","31@0|T@6|RA@11|RB@16|435@21|TX@31|","v3.0"
"Move To VSR Word & Splat X-form","mtvsrws XT,RA","31@0|T@6|RA@11|///@16|403@21|TX@31|","v3.0"
"Paste X-form","paste. RA,RB,L","31@0|///@6|L@10|RA@11|RB@16|902@21|1@31|","v3.0"
"Set Boolean X-form","setb RT,BFA","31@0|RT@6|BFA@11|//@14|///@16|128@21|/@31|","v3.0"
"SLB Invalidate Entry Global X-form","slbieg RS,RB","31@0|RS@6|///@11|RB@16|466@21|/@31|","v3.0"
"SLB Synchronize X-form","slbsync","31@0|///@6|///@11|///@16|338@21|/@31|","v3.0"
"Store Doubleword ATomic X-form","stdat RS,RA,FC","31@0|RS@6|RA@11|FC@16|742@21|/@31|","v3.0"
"Stop XL-form","stop","19@0|///@6|///@11|///@16|370@21|/@31|","v3.0"
"Store Word ATomic X-form","stwat RS,RA,FC","31@0|RS@6|RA@11|FC@16|710@21|/@31|","v3.0"
"Store VSX Scalar Doubleword DS-form","stxsd VRS,DS(RA)","61@0|VRS@6|RA@11|DS@16|2@30|","v3.0"
"Store VSX Scalar as Integer Byte Indexed X-form","stxsibx XS,RA,RB","31@0|S@6|RA@11|RB@16|909@21|SX@31|","v3.0"
"Store VSX Scalar as Integer Halfword Indexed X-form","stxsihx XS,RA,RB","31@0|S@6|RA@11|RB@16|941@21|SX@31|","v3.0"
"Store VSX Scalar Single DS-form","stxssp VRS,DS(RA)","61@0|VRS@6|RA@11|DS@16|3@30|","v3.0"
"Store VSX Vector DQ-form","stxv XS,DQ(RA)","61@0|S@6|RA@11|DQ@16|SX@28|5@29|","v3.0"
"Store VSX Vector Byte*16 Indexed X-form","stxvb16x XS,RA,RB","31@0|S@6|RA@11|RB@16|1004@21|SX@31|","v3.0"
"Store VSX Vector Halfword*8 Indexed X-form","stxvh8x XS,RA,RB","31@0|S@6|RA@11|RB@16|940@21|SX@31|","v3.0"
"Store VSX Vector with Length X-form","stxvl XS,RA,RB","31@0|S@6|RA@11|RB@16|397@21|SX@31|","v3.0"
"Store VSX Vector with Length Left-justified X-form","stxvll XS,RA,RB","31@0|S@6|RA@11|RB@16|429@21|SX@31|","v3.0"
"Store VSX Vector Indexed X-form","stxvx XS,RA,RB","31@0|S@6|RA@11|RB@16|396@21|SX@31|","v3.0"
"Vector Absolute Difference Unsigned Byte VX-form","vabsdub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1027@21|","v3.0"
"Vector Absolute Difference Unsigned Halfword VX-form","vabsduh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1091@21|","v3.0"
"Vector Absolute Difference Unsigned Word VX-form","vabsduw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1155@21|","v3.0"
"Vector Bit Permute Doubleword VX-form","vbpermd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1484@21|","v3.0"
"Vector Count Leading Zero Least-Significant Bits Byte VX-form","vclzlsbb RT,VRB","4@0|RT@6|0@11|VRB@16|1538@21|","v3.0"
"Vector Compare Not Equal Byte VC-form","vcmpneb VRT,VRA,VRB (Rc=0)|vcmpneb. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|7@22|","v3.0"
"Vector Compare Not Equal Halfword VC-form","vcmpneh VRT,VRA,VRB (Rc=0)|vcmpneh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|71@22|","v3.0"
"Vector Compare Not Equal Word VC-form","vcmpnew VRT,VRA,VRB (Rc=0)|vcmpnew. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|135@22|","v3.0"
"Vector Compare Not Equal or Zero Byte VC-form","vcmpnezb VRT,VRA,VRB (Rc=0)|vcmpnezb. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|263@22|","v3.0"
"Vector Compare Not Equal or Zero Halfword VC-form","vcmpnezh VRT,VRA,VRB (Rc=0)|vcmpnezh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|327@22|","v3.0"
"Vector Compare Not Equal or Zero Word VC-form","vcmpnezw VRT,VRA,VRB (Rc=0)|vcmpnezw. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|391@22|","v3.0"
"Vector Count Trailing Zeros Byte VX-form","vctzb VRT,VRB","4@0|VRT@6|28@11|VRB@16|1538@21|","v3.0"
"Vector Count Trailing Zeros Doubleword VX-form","vctzd VRT,VRB","4@0|VRT@6|31@11|VRB@16|1538@21|","v3.0"
"Vector Count Trailing Zeros Halfword VX-form","vctzh VRT,VRB","4@0|VRT@6|29@11|VRB@16|1538@21|","v3.0"
"Vector Count Trailing Zero Least-Significant Bits Byte VX-form","vctzlsbb RT,VRB","4@0|RT@6|1@11|VRB@16|1538@21|","v3.0"
"Vector Count Trailing Zeros Word VX-form","vctzw VRT,VRB","4@0|VRT@6|30@11|VRB@16|1538@21|","v3.0"
"Vector Extract Doubleword to VSR using immediate-specified index VX-form","vextractd VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|717@21|","v3.0"
"Vector Extract Unsigned Byte to VSR using immediate-specified index VX-form","vextractub VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|525@21|","v3.0"
"Vector Extract Unsigned Halfword to VSR using immediate-specified index VX-form","vextractuh VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|589@21|","v3.0"
"Vector Extract Unsigned Word to VSR using immediate-specified index VX-form","vextractuw VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|653@21|","v3.0"
"Vector Extend Sign Byte To Doubleword VX-form","vextsb2d VRT,VRB","4@0|VRT@6|24@11|VRB@16|1538@21|","v3.0"
"Vector Extend Sign Byte To Word VX-form","vextsb2w VRT,VRB","4@0|VRT@6|16@11|VRB@16|1538@21|","v3.0"
"Vector Extend Sign Halfword To Doubleword VX-form","vextsh2d VRT,VRB","4@0|VRT@6|25@11|VRB@16|1538@21|","v3.0"
"Vector Extend Sign Halfword To Word VX-form","vextsh2w VRT,VRB","4@0|VRT@6|17@11|VRB@16|1538@21|","v3.0"
"Vector Extend Sign Word To Doubleword VX-form","vextsw2d VRT,VRB","4@0|VRT@6|26@11|VRB@16|1538@21|","v3.0"
"Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-form","vextublx RT,RA,VRB","4@0|RT@6|RA@11|VRB@16|1549@21|","v3.0"
"Vector Extract Unsigned Byte to GPR using GPR-specified Right-Index VX-form","vextubrx RT,RA,VRB","4@0|RT@6|RA@11|VRB@16|1805@21|","v3.0"
"Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index VX-form","vextuhlx RT,RA,VRB","4@0|RT@6|RA@11|VRB@16|1613@21|","v3.0"
"Vector Extract Unsigned Halfword to GPR using GPR-specified Right-Index VX-form","vextuhrx RT,RA,VRB","4@0|RT@6|RA@11|VRB@16|1869@21|","v3.0"
"Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-form","vextuwlx RT,RA,VRB","4@0|RT@6|RA@11|VRB@16|1677@21|","v3.0"
"Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-form","vextuwrx RT,RA,VRB","4@0|RT@6|RA@11|VRB@16|1933@21|","v3.0"
"Vector Insert Byte from VSR using immediate-specified index VX-form","vinsertb VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|781@21|","v3.0"
"Vector Insert Doubleword from VSR using immediate-specified index VX-form","vinsertd VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|973@21|","v3.0"
"Vector Insert Halfword from VSR using immediate-specified index VX-form","vinserth VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|845@21|","v3.0"
"Vector Insert Word from VSR using immediate-specified index VX-form","vinsertw VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|909@21|","v3.0"
"Vector Multiply-by-10 & write Carry-out Unsigned Quadword VX-form","vmul10cuq VRT,VRA","4@0|VRT@6|VRA@11|///@16|1@21|","v3.0"
"Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword VX-form","vmul10ecuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|65@21|","v3.0"
"Vector Multiply-by-10 Extended Unsigned Quadword VX-form","vmul10euq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|577@21|","v3.0"
"Vector Multiply-by-10 Unsigned Quadword VX-form","vmul10uq VRT,VRA","4@0|VRT@6|VRA@11|///@16|513@21|","v3.0"
"Vector Negate Doubleword VX-form","vnegd VRT,VRB","4@0|VRT@6|7@11|VRB@16|1538@21|","v3.0"
"Vector Negate Word VX-form","vnegw VRT,VRB","4@0|VRT@6|6@11|VRB@16|1538@21|","v3.0"
"Vector Permute Right-indexed VA-form","vpermr VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|59@26|","v3.0"
"Vector Parity Byte Doubleword VX-form","vprtybd VRT,VRB","4@0|VRT@6|9@11|VRB@16|1538@21|","v3.0"
"Vector Parity Byte Quadword VX-form","vprtybq VRT,VRB","4@0|VRT@6|10@11|VRB@16|1538@21|","v3.0"
"Vector Parity Byte Word VX-form","vprtybw VRT,VRB","4@0|VRT@6|8@11|VRB@16|1538@21|","v3.0"
"Vector Rotate Left Doubleword then Mask Insert VX-form","vrldmi VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|197@21|","v3.0"
"Vector Rotate Left Doubleword then AND with Mask VX-form","vrldnm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|453@21|","v3.0"
"Vector Rotate Left Word then Mask Insert VX-form","vrlwmi VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|133@21|","v3.0"
"Vector Rotate Left Word then AND with Mask VX-form","vrlwnm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|389@21|","v3.0"
"Vector Shift Left Variable VX-form","vslv VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1860@21|","v3.0"
"Vector Shift Right Variable VX-form","vsrv VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1796@21|","v3.0"
"Wait X-form","wait WC,PL","31@0|??@6|/@8|WC@9|///@11|PL@14|///@16|30@21|/@31|","v3.0"
"VSX Scalar Absolute Quad-Precision X-form","xsabsqp VRT,VRB","63@0|VRT@6|0@11|VRB@16|804@21|/@31|","v3.0"
"VSX Scalar Add Quad-Precision [using round to Odd] X-form","xsaddqp VRT,VRA,VRB (RO=0)|xsaddqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|4@21|RO@31|","v3.0"
"VSX Scalar Compare Equal Double-Precision XX3-form","xscmpeqdp XT,XA,XB","60@0|T@6|A@11|B@16|3@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Compare Exponents Double-Precision XX3-form","xscmpexpdp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|59@21|AX@29|BX@30|/@31|","v3.0"
"VSX Scalar Compare Exponents Quad-Precision X-form","xscmpexpqp BF,VRA,VRB","63@0|BF@6|//@9|VRA@11|VRB@16|164@21|/@31|","v3.0"
"VSX Scalar Compare Greater Than or Equal Double-Precision XX3-form","xscmpgedp XT,XA,XB","60@0|T@6|A@11|B@16|19@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Compare Greater Than Double-Precision XX3-form","xscmpgtdp XT,XA,XB","60@0|T@6|A@11|B@16|11@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Compare Ordered Quad-Precision X-form","xscmpoqp BF,VRA,VRB","63@0|BF@6|//@9|VRA@11|VRB@16|132@21|/@31|","v3.0"
"VSX Scalar Compare Unordered Quad-Precision X-form","xscmpuqp BF,VRA,VRB","63@0|BF@6|//@9|VRA@11|VRB@16|644@21|/@31|","v3.0"
"VSX Scalar Copy Sign Quad-Precision X-form","xscpsgnqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|100@21|/@31|","v3.0"
"VSX Scalar Convert with round Double-Precision to Half-Precision format XX2-form","xscvdphp XT,XB","60@0|T@6|17@11|B@16|347@21|BX@30|TX@31|","v3.0"
"VSX Scalar Convert Double-Precision to Quad-Precision format X-form","xscvdpqp VRT,VRB","63@0|VRT@6|22@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Convert Half-Precision to Double-Precision format XX2-form","xscvhpdp XT,XB","60@0|T@6|16@11|B@16|347@21|BX@30|TX@31|","v3.0"
"VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form","xscvqpdp VRT,VRB (RO=0)|xscvqpdpo VRT,VRB (RO=1)","63@0|VRT@6|20@11|VRB@16|836@21|RO@31|","v3.0"
"VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form","xscvqpsdz VRT,VRB","63@0|VRT@6|25@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Convert with round to zero Quad-Precision to Signed Word format X-form","xscvqpswz VRT,VRB","63@0|VRT@6|9@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form","xscvqpudz VRT,VRB","63@0|VRT@6|17@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format X-form","xscvqpuwz VRT,VRB","63@0|VRT@6|1@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Convert Signed Doubleword to Quad-Precision format X-form","xscvsdqp VRT,VRB","63@0|VRT@6|10@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Convert Unsigned Doubleword to Quad-Precision format X-form","xscvudqp VRT,VRB","63@0|VRT@6|2@11|VRB@16|836@21|/@31|","v3.0"
"VSX Scalar Divide Quad-Precision [using round to Odd] X-form","xsdivqp VRT,VRA,VRB (RO=0)|xsdivqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|548@21|RO@31|","v3.0"
"VSX Scalar Insert Exponent Double-Precision X-form","xsiexpdp XT,RA,RB","60@0|T@6|RA@11|RB@16|918@21|TX@31|","v3.0"
"VSX Scalar Insert Exponent Quad-Precision X-form","xsiexpqp VRT,VRA,VRB","63@0|VRT@6|VRA@11|VRB@16|868@21|/@31|","v3.0"
"VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form","xsmaddqp VRT,VRA,VRB (RO=0)|xsmaddqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|388@21|RO@31|","v3.0"
"VSX Scalar Maximum Type-C Double-Precision XX3-form","xsmaxcdp XT,XA,XB","60@0|T@6|A@11|B@16|128@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Maximum Type-J Double-Precision XX3-form","xsmaxjdp XT,XA,XB","60@0|T@6|A@11|B@16|144@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Minimum Type-C Double-Precision XX3-form","xsmincdp XT,XA,XB","60@0|T@6|A@11|B@16|136@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Minimum Type-J Double-Precision XX3-form","xsminjdp XT,XA,XB","60@0|T@6|A@11|B@16|152@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form","xsmsubqp VRT,VRA,VRB (RO=0)|xsmsubqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|420@21|RO@31|","v3.0"
"VSX Scalar Multiply Quad-Precision [using round to Odd] X-form","xsmulqp VRT,VRA,VRB (RO=0)|xsmulqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|36@21|RO@31|","v3.0"
"VSX Scalar Negative Absolute Quad-Precision X-form","xsnabsqp VRT,VRB","63@0|VRT@6|8@11|VRB@16|804@21|TX@31|","v3.0"
"VSX Scalar Negate Quad-Precision X-form","xsnegqp VRT,VRB","63@0|VRT@6|16@11|VRB@16|804@21|/@31|","v3.0"
"VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form","xsnmaddqp VRT,VRA,VRB (RO=0)|xsnmaddqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|452@21|RO@31|","v3.0"
"VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form","xsnmsubqp VRT,VRA,VRB (RO=0)|xsnmsubqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|484@21|RO@31|","v3.0"
"VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form","xsrqpi R,VRT,VRB,RMC (EX=0)|xsrqpix R,VRT,VRB,RMC (EX=1)","63@0|VRT@6|///@11|R@15|VRB@16|RMC@21|5@23|EX@31|","v3.0"
"VSX Scalar Round Quad-Precision to Double-Extended Precision Z23-form","xsrqpxp R,VRT,VRB,RMC","63@0|VRT@6|///@11|R@15|VRB@16|RMC@21|37@23|/@31|","v3.0"
"VSX Scalar Square Root Quad-Precision [using round to Odd] X-form","xssqrtqp VRT,VRB (RO=0)|xssqrtqpo VRT,VRB (RO=1)","63@0|VRT@6|27@11|VRB@16|804@21|RO@31|","v3.0"
"VSX Scalar Subtract Quad-Precision [using round to Odd] X-form","xssubqp VRT,VRA,VRB (RO=0)|xssubqpo VRT,VRA,VRB (RO=1)","63@0|VRT@6|VRA@11|VRB@16|516@21|RO@31|","v3.0"
"VSX Scalar Test Data Class Double-Precision XX2-form","xststdcdp BF,XB,DCMX","60@0|BF@6|DCMX@9|B@16|362@21|BX@30|/@31|","v3.0"
"VSX Scalar Test Data Class Quad-Precision X-form","xststdcqp BF,VRB,DCMX","63@0|BF@6|DCMX@9|VRB@16|708@21|/@31|","v3.0"
"VSX Scalar Test Data Class Single-Precision XX2-form","xststdcsp BF,XB,DCMX","60@0|BF@6|DCMX@9|B@16|298@21|BX@30|/@31|","v3.0"
"VSX Scalar Extract Exponent Double-Precision XX2-form","xsxexpdp RT,XB","60@0|RT@6|0@11|B@16|347@21|BX@30|/@31|","v3.0"
"VSX Scalar Extract Exponent Quad-Precision X-form","xsxexpqp VRT,VRB","63@0|VRT@6|2@11|VRB@16|804@21|/@31|","v3.0"
"VSX Scalar Extract Significand Double-Precision XX2-form","xsxsigdp RT,XB","60@0|RT@6|1@11|B@16|347@21|BX@30|/@31|","v3.0"
"VSX Scalar Extract Significand Quad-Precision X-form","xsxsigqp VRT,VRB","63@0|VRT@6|18@11|VRB@16|804@21|/@31|","v3.0"
"VSX Vector Convert Half-Precision to Single-Precision format XX2-form","xvcvhpsp XT,XB","60@0|T@6|24@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Convert with round Single-Precision to Half-Precision format XX2-form","xvcvsphp XT,XB","60@0|T@6|25@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Insert Exponent Double-Precision XX3-form","xviexpdp XT,XA,XB","60@0|T@6|A@11|B@16|248@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Vector Insert Exponent Single-Precision XX3-form","xviexpsp XT,XA,XB","60@0|T@6|A@11|B@16|216@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Vector Test Data Class Double-Precision XX2-form","xvtstdcdp XT,XB,DCMX","60@0|T@6|dx@11|B@16|15@21|dc@25|5@26|dm@29|BX@30|TX@31|","v3.0"
"VSX Vector Test Data Class Single-Precision XX2-form","xvtstdcsp XT,XB,DCMX","60@0|T@6|dx@11|B@16|13@21|dc@25|5@26|dm@29|BX@30|TX@31|","v3.0"
"VSX Vector Extract Exponent Double-Precision XX2-form","xvxexpdp XT,XB","60@0|T@6|0@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Extract Exponent Single-Precision XX2-form","xvxexpsp XT,XB","60@0|T@6|8@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Extract Significand Double-Precision XX2-form","xvxsigdp XT,XB","60@0|T@6|1@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Extract Significand Single-Precision XX2-form","xvxsigsp XT,XB","60@0|T@6|9@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Byte-Reverse Doubleword XX2-form","xxbrd XT,XB","60@0|T@6|23@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Byte-Reverse Halfword XX2-form","xxbrh XT,XB","60@0|T@6|7@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Byte-Reverse Quadword XX2-form","xxbrq XT,XB","60@0|T@6|31@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Byte-Reverse Word XX2-form","xxbrw XT,XB","60@0|T@6|15@11|B@16|475@21|BX@30|TX@31|","v3.0"
"VSX Vector Extract Unsigned Word XX2-form","xxextractuw XT,XB,UIM","60@0|T@6|/@11|UIM@12|B@16|165@21|BX@30|TX@31|","v3.0"
"VSX Vector Insert Word XX2-form","xxinsertw XT,XB,UIM","60@0|T@6|/@11|UIM@12|B@16|181@21|BX@30|TX@31|","v3.0"
"VSX Vector Permute XX3-form","xxperm XT,XA,XB","60@0|T@6|A@11|B@16|26@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Vector Permute Right-indexed XX3-form","xxpermr XT,XA,XB","60@0|T@6|A@11|B@16|58@21|AX@29|BX@30|TX@31|","v3.0"
"VSX Vector Splat Immediate Byte X-form","xxspltib XT,IMM8","60@0|T@6|0@11|IMM8@13|360@21|TX@31|","v3.0"
"Decimal Add Modulo VX-form","bcdadd. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|1@23|","v2.07"
"Decimal Subtract Modulo VX-form","bcdsub. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|65@23|","v2.07"
"Branch Conditional to Branch Target Address Register XL-form","bctar BO,BI,BH (LK=0)|bctarl BO,BI,BH (LK=1)","19@0|BO@6|BI@11|///@16|BH@19|560@21|LK@31|","v2.07"
"Clear BHRB X-form","clrbhrb","31@0|///@6|///@11|///@16|430@21|/@31|","v2.07"
"Floating Merge Even Word X-form","fmrgew FRT,FRA,FRB","63@0|FRT@6|FRA@11|FRB@16|966@21|/@31|","v2.07"
"Floating Merge Odd Word X-form","fmrgow FRT,FRA,FRB","63@0|FRT@6|FRA@11|FRB@16|838@21|/@31|","v2.07"
"Instruction Cache Block Touch X-form","icbt CT, RA, RB","31@0|/@6|CT@7|RA@11|RB@16|22@21|/@31|","v2.07"
"Load Quadword And Reserve Indexed X-form","lqarx RTp,RA,RB,EH","31@0|RTp@6|RA@11|RB@16|276@21|EH@31|","v2.07"
"Load VSX Scalar as Integer Word Algebraic Indexed X-form","lxsiwax XT,RA,RB","31@0|T@6|RA@11|RB@16|76@21|TX@31|","v2.07"
"Load VSX Scalar as Integer Word & Zero Indexed X-form","lxsiwzx XT,RA,RB","31@0|T@6|RA@11|RB@16|12@21|TX@31|","v2.07"
"Load VSX Scalar Single-Precision Indexed X-form","lxsspx XT,RA,RB","31@0|T@6|RA@11|RB@16|524@21|TX@31|","v2.07"
"Move From BHRB XFX-form","mfbhrbe RT,BHRBE","31@0|RT@6|BHRBE@11|302@21|/@31|","v2.07"
"Move From VSR Doubleword X-form","mfvsrd RA,XS","31@0|S@6|RA@11|///@16|51@21|SX@31|","v2.07"
"Move From VSR Word and Zero X-form","mfvsrwz RA,XS","31@0|S@6|RA@11|///@16|115@21|SX@31|","v2.07"
"Message Clear X-form","msgclr RB","31@0|///@6|///@11|RB@16|238@21|/@31|","v2.07"
"Message Clear Privileged X-form","msgclrp RB","31@0|///@6|///@11|RB@16|174@21|/@31|","v2.07"
"Message Send X-form","msgsnd RB","31@0|///@6|///@11|RB@16|206@21|/@31|","v2.07"
"Message Send Privileged X-form","msgsndp RB","31@0|///@6|///@11|RB@16|142@21|/@31|","v2.07"
"Move To VSR Doubleword X-form","mtvsrd XT,RA","31@0|T@6|RA@11|///@16|179@21|TX@31|","v2.07"
"Move To VSR Word Algebraic X-form","mtvsrwa XT,RA","31@0|T@6|RA@11|///@16|211@21|TX@31|","v2.07"
"Move To VSR Word and Zero X-form","mtvsrwz XT,RA","31@0|T@6|RA@11|///@16|243@21|TX@31|","v2.07"
"Return from Event Based Branch XL-form","rfebb S","19@0|///@6|///@11|///@16|S@20|146@21|/@31|","v2.07"
"Store Quadword Conditional Indexed X-form","stqcx. RSp,RA,RB","31@0|RSp@6|RA@11|RB@16|182@21|1@31|","v2.07"
"Store VSX Scalar as Integer Word Indexed X-form","stxsiwx XS,RA,RB","31@0|S@6|RA@11|RB@16|140@21|SX@31|","v2.07"
"Store VSX Scalar Single-Precision Indexed X-form","stxsspx XS,RA,RB","31@0|S@6|RA@11|RB@16|652@21|SX@31|","v2.07"
"Vector Add & write Carry Unsigned Quadword VX-form","vaddcuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|320@21|","v2.07"
"Vector Add Extended & write Carry Unsigned Quadword VA-form","vaddecuq VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|61@26|","v2.07"
"Vector Add Extended Unsigned Quadword Modulo VA-form","vaddeuqm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|60@26|","v2.07"
"Vector Add Unsigned Doubleword Modulo VX-form","vaddudm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|192@21|","v2.07"
"Vector Add Unsigned Quadword Modulo VX-form","vadduqm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|256@21|","v2.07"
"Vector Bit Permute Quadword VX-form","vbpermq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1356@21|","v2.07"
"Vector AES Cipher VX-form","vcipher VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1288@21|","v2.07"
"Vector AES Cipher Last VX-form","vcipherlast VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1289@21|","v2.07"
"Vector Count Leading Zeros Byte VX-form","vclzb VRT,VRB","4@0|VRT@6|///@11|VRB@16|1794@21|","v2.07"
"Vector Count Leading Zeros Doubleword VX-form","vclzd VRT,VRB","4@0|VRT@6|///@11|VRB@16|1986@21|","v2.07"
"Vector Count Leading Zeros Halfword VX-form","vclzh VRT,VRB","4@0|VRT@6|///@11|VRB@16|1858@21|","v2.07"
"Vector Count Leading Zeros Word VX-form","vclzw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1922@21|","v2.07"
"Vector Compare Equal Unsigned Doubleword VC-form","vcmpequd VRT,VRA,VRB (Rc=0)|vcmpequd. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|199@22|","v2.07"
"Vector Compare Greater Than Signed Doubleword VC-form","vcmpgtsd VRT,VRA,VRB (Rc=0)|vcmpgtsd. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|967@22|","v2.07"
"Vector Compare Greater Than Unsigned Doubleword VC-form","vcmpgtud VRT,VRA,VRB (Rc=0)|vcmpgtud. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|711@22|","v2.07"
"Vector Logical Equivalence VX-form","veqv VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1668@21|","v2.07"
"Vector Gather Bits by Bytes by Doubleword VX-form","vgbbd VRT,VRB","4@0|VRT@6|///@11|VRB@16|1292@21|","v2.07"
"Vector Maximum Signed Doubleword VX-form","vmaxsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|450@21|","v2.07"
"Vector Maximum Unsigned Doubleword VX-form","vmaxud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|194@21|","v2.07"
"Vector Minimum Signed Doubleword VX-form","vminsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|962@21|","v2.07"
"Vector Minimum Unsigned Doubleword VX-form","vminud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|706@21|","v2.07"
"Vector Merge Even Word VX-form","vmrgew VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1932@21|","v2.07"
"Vector Merge Odd Word VX-form","vmrgow VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1676@21|","v2.07"
"Vector Multiply Even Signed Word VX-form","vmulesw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|904@21|","v2.07"
"Vector Multiply Even Unsigned Word VX-form","vmuleuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|648@21|","v2.07"
"Vector Multiply Odd Signed Word VX-form","vmulosw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|392@21|","v2.07"
"Vector Multiply Odd Unsigned Word VX-form","vmulouw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|136@21|","v2.07"
"Vector Multiply Unsigned Word Modulo VX-form","vmuluwm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|137@21|","v2.07"
"Vector Logical NAND VX-form","vnand VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1412@21|","v2.07"
"Vector AES Inverse Cipher VX-form","vncipher VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1352@21|","v2.07"
"Vector AES Inverse Cipher Last VX-form","vncipherlast VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1353@21|","v2.07"
"Vector Logical OR with Complement VX-form","vorc VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1348@21|","v2.07"
"Vector Permute & Exclusive-OR VA-form","vpermxor VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|45@26|","v2.07"
"Vector Pack Signed Doubleword Signed Saturate VX-form","vpksdss VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1486@21|","v2.07"
"Vector Pack Signed Doubleword Unsigned Saturate VX-form","vpksdus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1358@21|","v2.07"
"Vector Pack Unsigned Doubleword Unsigned Modulo VX-form","vpkudum VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1102@21|","v2.07"
"Vector Pack Unsigned Doubleword Unsigned Saturate VX-form","vpkudus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1230@21|","v2.07"
"Vector Polynomial Multiply-Sum Byte VX-form","vpmsumb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1032@21|","v2.07"
"Vector Polynomial Multiply-Sum Doubleword VX-form","vpmsumd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1224@21|","v2.07"
"Vector Polynomial Multiply-Sum Halfword VX-form","vpmsumh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1096@21|","v2.07"
"Vector Polynomial Multiply-Sum Word VX-form","vpmsumw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1160@21|","v2.07"
"Vector Population Count Byte VX-form","vpopcntb VRT,VRB","4@0|VRT@6|///@11|VRB@16|1795@21|","v2.07"
"Vector Population Count Doubleword VX-form","vpopcntd VRT,VRB","4@0|VRT@6|///@11|VRB@16|1987@21|","v2.07"
"Vector Population Count Halfword VX-form","vpopcnth VRT,VRB","4@0|VRT@6|///@11|VRB@16|1859@21|","v2.07"
"Vector Population Count Word VX-form","vpopcntw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1923@21|","v2.07"
"Vector Rotate Left Doubleword VX-form","vrld VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|196@21|","v2.07"
"Vector AES SubBytes VX-form","vsbox VRT,VRA","4@0|VRT@6|VRA@11|///@16|1480@21|","v2.07"
"Vector SHA-512 Sigma Doubleword VX-form","vshasigmad VRT,VRA,ST,SIX","4@0|VRT@6|VRA@11|ST@16|SIX@17|1730@21|","v2.07"
"Vector SHA-256 Sigma Word VX-form","vshasigmaw VRT,VRA,ST,SIX","4@0|VRT@6|VRA@11|ST@16|SIX@17|1666@21|","v2.07"
"Vector Shift Left Doubleword VX-form","vsld VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1476@21|","v2.07"
"Vector Shift Right Algebraic Doubleword VX-form","vsrad VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|964@21|","v2.07"
"Vector Shift Right Doubleword VX-form","vsrd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1732@21|","v2.07"
"Vector Subtract & write Carry-out Unsigned Quadword VX-form","vsubcuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1344@21|","v2.07"
"Vector Subtract Extended & write Carry-out Unsigned Quadword VA-form","vsubecuq VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|63@26|","v2.07"
"Vector Subtract Extended Unsigned Quadword Modulo VA-form","vsubeuqm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|62@26|","v2.07"
"Vector Subtract Unsigned Doubleword Modulo VX-form","vsubudm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1216@21|","v2.07"
"Vector Subtract Unsigned Quadword Modulo VX-form","vsubuqm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1280@21|","v2.07"
"Vector Unpack High Signed Word VX-form","vupkhsw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1614@21|","v2.07"
"Vector Unpack Low Signed Word VX-form","vupklsw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1742@21|","v2.07"
"VSX Scalar Add Single-Precision XX3-form","xsaddsp XT,XA,XB","60@0|T@6|A@11|B@16|0@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form","xscvdpspn XT,XB","60@0|T@6|///@11|B@16|267@21|BX@30|TX@31|","v2.07"
"VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form","xscvspdpn XT,XB","60@0|T@6|///@11|B@16|331@21|BX@30|TX@31|","v2.07"
"VSX Scalar Convert with round Signed Doubleword to Single-Precision format XX2-form","xscvsxdsp XT,XB","60@0|T@6|///@11|B@16|312@21|BX@30|TX@31|","v2.07"
"VSX Scalar Convert with round Unsigned Doubleword to Single-Precision XX2-form","xscvuxdsp XT,XB","60@0|T@6|///@11|B@16|296@21|BX@30|TX@31|","v2.07"
"VSX Scalar Divide Single-Precision XX3-form","xsdivsp XT,XA,XB","60@0|T@6|A@11|B@16|24@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Multiply-Add Type-A Single-Precision XX3-form","xsmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|1@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Multiply-Add Type-M Single-Precision XX3-form","xsmaddmsp XT,XA,XB","60@0|T@6|A@11|B@16|9@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Multiply-Subtract Type-A Single-Precision XX3-form","xsmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|17@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Multiply-Subtract Type-M Single-Precision XX3-form","xsmsubmsp XT,XA,XB","60@0|T@6|A@11|B@16|25@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Multiply Single-Precision XX3-form","xsmulsp XT,XA,XB","60@0|T@6|A@11|B@16|16@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Negative Multiply-Add Type-A Single-Precision XX3-form","xsnmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|129@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Negative Multiply-Add Type-M Single-Precision XX3-form","xsnmaddmsp XT,XA,XB","60@0|T@6|A@11|B@16|137@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Negative Multiply-Subtract Type-A Single-Precision XX3-form","xsnmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|145@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Negative Multiply-Subtract Type-M Single-Precision XX3-form","xsnmsubmsp XT,XA,XB","60@0|T@6|A@11|B@16|153@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Scalar Reciprocal Estimate Single-Precision XX2-form","xsresp XT,XB","60@0|T@6|///@11|B@16|26@21|BX@30|TX@31|","v2.07"
"VSX Scalar Round to Single-Precision XX2-form","xsrsp XT,XB","60@0|T@6|///@11|B@16|281@21|BX@30|TX@31|","v2.07"
"VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form","xsrsqrtesp XT,XB","60@0|T@6|///@11|B@16|10@21|BX@30|TX@31|","v2.07"
"VSX Scalar Square Root Single-Precision XX2-form","xssqrtsp XT,XB","60@0|T@6|///@11|B@16|11@21|BX@30|TX@31|","v2.07"
"VSX Scalar Subtract Single-Precision XX3-form","xssubsp XT,XA,XB","60@0|T@6|A@11|B@16|8@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Vector Logical Equivalence XX3-form","xxleqv XT,XA,XB","60@0|T@6|A@11|B@16|186@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Vector Logical NAND XX3-form","xxlnand XT,XA,XB","60@0|T@6|A@11|B@16|178@21|AX@29|BX@30|TX@31|","v2.07"
"VSX Vector Logical OR with Complement XX3-form","xxlorc XT,XA,XB","60@0|T@6|A@11|B@16|170@21|AX@29|BX@30|TX@31|","v2.07"
"Add and Generate Sixes XO-form","addg6s RT,RA,RB","31@0|RT@6|RA@11|RB@16|/@21|74@22|/@31|","v2.06"
"Bit Permute Doubleword X-form","bpermd RA,RS,RB","31@0|RS@6|RA@11|RB@16|252@21|/@31|","v2.06"
"Convert Binary Coded Decimal To Declets X-form","cbcdtd RA, RS","31@0|RS@6|RA@11|///@16|314@21|/@31|","v2.06"
"Convert Declets To Binary Coded Decimal X-form","cdtbcd RA, RS","31@0|RS@6|RA@11|///@16|282@21|/@31|","v2.06"
"DFP Convert From Fixed X-form","dcffix FRT,FRB (Rc=0)|dcffix. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|802@21|Rc@31|","v2.06"
"Divide Doubleword Extended XO-form","divde RT,RA,RB (OE=0 Rc=0)|divde. RT,RA,RB (OE=0 Rc=1)|divdeo RT,RA,RB (OE=1 Rc=0)|divdeo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|425@22|Rc@31|","v2.06"
"Divide Doubleword Extended Unsigned XO-form","divdeu RT,RA,RB (OE=0 Rc=0)|divdeu. RT,RA,RB (OE=0 Rc=1)|divdeuo RT,RA,RB (OE=1 Rc=0)|divdeuo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|393@22|Rc@31|","v2.06"
"Divide Word Extended XO-form","divwe RT,RA,RB (OE=0 Rc=0)|divwe. RT,RA,RB (OE=0 Rc=1)|divweo RT,RA,RB (OE=1 Rc=0)|divweo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|427@22|Rc@31|","v2.06"
"Divide Word Extended Unsigned XO-form","divweu RT,RA,RB (OE=0 Rc=0)|divweu. RT,RA,RB (OE=0 Rc=1)|divweuo RT,RA,RB (OE=1 Rc=0)|divweuo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|395@22|Rc@31|","v2.06"
"Floating Convert with round Signed Doubleword to Single-Precision format X-form","fcfids FRT,FRB (Rc=0)|fcfids. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|846@21|Rc@31|","v2.06"
"Floating Convert with round Unsigned Doubleword to Double-Precision format X-form","fcfidu FRT,FRB (Rc=0)|fcfidu. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|974@21|Rc@31|","v2.06"
"Floating Convert with round Unsigned Doubleword to Single-Precision format X-form","fcfidus FRT,FRB (Rc=0)|fcfidus. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|974@21|Rc@31|","v2.06"
"Floating Convert with round Double-Precision To Unsigned Doubleword format X-form","fctidu FRT,FRB (Rc=0)|fctidu. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|942@21|Rc@31|","v2.06"
"Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form","fctiduz FRT,FRB (Rc=0)|fctiduz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|943@21|Rc@31|","v2.06"
"Floating Convert with round Double-Precision To Unsigned Word format X-form","fctiwu FRT,FRB (Rc=0)|fctiwu. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|142@21|Rc@31|","v2.06"
"Floating Convert with truncate Double-Precision To Unsigned Word format X-form","fctiwuz FRT,FRB (Rc=0)|fctiwuz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|143@21|Rc@31|","v2.06"
"Floating Test for software Divide X-form","ftdiv BF,FRA,FRB","63@0|BF@6|//@9|FRA@11|FRB@16|128@21|/@31|","v2.06"
"Floating Test for software Square Root X-form","ftsqrt BF,FRB","63@0|BF@6|//@9|///@11|FRB@16|160@21|/@31|","v2.06"
"Load Byte And Reserve Indexed X-form","lbarx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|52@21|EH@31|","v2.06"
"Load Doubleword Byte-Reverse Indexed X-form","ldbrx RT,RA,RB","31@0|RT@6|RA@11|RB@16|532@21|/@31|","v2.06"
"Load Floating-Point as Integer Word & Zero Indexed X-form","lfiwzx FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|887@21|/@31|","v2.06"
"Load Halfword And Reserve Indexed Xform","lharx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|116@21|EH@31|","v2.06"
"Load VSX Scalar Doubleword Indexed X-form","lxsdx XT,RA,RB","31@0|T@6|RA@11|RB@16|588@21|TX@31|","v2.06"
"Load VSX Vector Doubleword*2 Indexed X-form","lxvd2x XT,RA,RB","31@0|T@6|RA@11|RB@16|844@21|TX@31|","v2.06"
"Load VSX Vector Doubleword & Splat Indexed X-form","lxvdsx XT,RA,RB","31@0|T@6|RA@11|RB@16|332@21|TX@31|","v2.06"
"Load VSX Vector Word*4 Indexed X-form","lxvw4x XT,RA,RB","31@0|T@6|RA@11|RB@16|780@21|TX@31|","v2.06"
"Population Count Doubleword X-form","popcntd RA, RS","31@0|RS@6|RA@11|///@16|506@21|/@31|","v2.06"
"Population Count Words X-form","popcntw RA, RS","31@0|RS@6|RA@11|///@16|378@21|/@31|","v2.06"
"Store Byte Conditional Indexed X-form","stbcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|694@21|1@31|","v2.06"
"Store Doubleword Byte-Reverse Indexed X-form","stdbrx RS,RA,RB","31@0|RS@6|RA@11|RB@16|660@21|/@31|","v2.06"
"Store Halfword Conditional Indexed X-form","sthcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|726@21|1@31|","v2.06"
"Store VSX Scalar Doubleword Indexed X-form","stxsdx XS,RA,RB","31@0|S@6|RA@11|RB@16|716@21|SX@31|","v2.06"
"Store VSX Vector Doubleword*2 Indexed X-form","stxvd2x XS,RA,RB","31@0|S@6|RA@11|RB@16|972@21|SX@31|","v2.06"
"Store VSX Vector Word*4 Indexed X-form","stxvw4x XS,RA,RB","31@0|S@6|RA@11|RB@16|908@21|SX@31|","v2.06"
"VSX Scalar Absolute Double-Precision XX2-form","xsabsdp XT,XB","60@0|T@6|///@11|B@16|345@21|BX@30|TX@31|","v2.06"
"VSX Scalar Add Double-Precision XX3-form","xsadddp XT,XA,XB","60@0|T@6|A@11|B@16|32@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Compare Ordered Double-Precision XX3-form","xscmpodp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|","v2.06"
"VSX Scalar Compare Unordered Double-Precision XX3-form","xscmpudp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|","v2.06"
"VSX Scalar Copy Sign Double-Precision XX3-form","xscpsgndp XT,XA,XB","60@0|T@6|A@11|B@16|176@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round Double-Precision to Single-Precision format XX2-form","xscvdpsp XT,XB","60@0|T@6|///@11|B@16|265@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round to zero Double-Precision to Signed Doubleword format XX2-form","xscvdpsxds XT,XB","60@0|T@6|///@11|B@16|344@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round to zero Double-Precision to Signed Word format XX2-form","xscvdpsxws XT,XB","60@0|T@6|///@11|B@16|88@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form","xscvdpuxds XT,XB","60@0|T@6|///@11|B@16|328@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round to zero Double-Precision to Unsigned Word format XX2-form","xscvdpuxws XT,XB","60@0|T@6|///@11|B@16|72@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert Single-Precision to Double-Precision format XX2-form","xscvspdp XT,XB","60@0|T@6|///@11|B@16|329@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round Signed Doubleword to Double-Precision format XX2-form","xscvsxddp XT,XB","60@0|T@6|///@11|B@16|376@21|BX@30|TX@31|","v2.06"
"VSX Scalar Convert with round Unsigned Doubleword to Double-Precision format XX2-form","xscvuxddp XT,XB","60@0|T@6|///@11|B@16|360@21|BX@30|TX@31|","v2.06"
"VSX Scalar Divide Double-Precision XX3-form","xsdivdp XT,XA,XB","60@0|T@6|A@11|B@16|56@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Multiply-Add Type-A Double-Precision XX3-form","xsmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|33@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Multiply-Add Type-M Double-Precision XX3-form","xsmaddmdp XT,XA,XB","60@0|T@6|A@11|B@16|41@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Maximum Double-Precision XX3-form","xsmaxdp XT,XA,XB","60@0|T@6|A@11|B@16|160@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Minimum Double-Precision XX3-form","xsmindp XT,XA,XB","60@0|T@6|A@11|B@16|168@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Multiply-Subtract Type-A Double-Precision XX3-form","xsmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|49@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Multiply-Subtract Type-M Double-Precision XX3-form","xsmsubmdp XT,XA,XB","60@0|T@6|A@11|B@16|57@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Multiply Double-Precision XX3-form","xsmuldp XT,XA,XB","60@0|T@6|A@11|B@16|48@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Negative Absolute Double-Precision XX2-form","xsnabsdp XT,XB","60@0|T@6|///@11|B@16|361@21|BX@30|TX@31|","v2.06"
"VSX Scalar Negate Double-Precision XX2-form","xsnegdp XT,XB","60@0|T@6|///@11|B@16|377@21|BX@30|TX@31|","v2.06"
"VSX Scalar Negative Multiply-Add Type-A Double-Precision XX3-form","xsnmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|161@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Negative Multiply-Add Type-M Double-Precision XX3-form","xsnmaddmdp XT,XA,XB","60@0|T@6|A@11|B@16|169@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Negative Multiply-Subtract Type-A Double-Precision XX3-form","xsnmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|177@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Negative Multiply-Subtract Type-M Double-Precision XX3-form","xsnmsubmdp XT,XA,XB","60@0|T@6|A@11|B@16|185@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form","xsrdpi XT,XB","60@0|T@6|///@11|B@16|73@21|BX@30|TX@31|","v2.06"
"VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form","xsrdpic XT,XB","60@0|T@6|///@11|B@16|107@21|BX@30|TX@31|","v2.06"
"VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form","xsrdpim XT,XB","60@0|T@6|///@11|B@16|121@21|BX@30|TX@31|","v2.06"
"VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form","xsrdpip XT,XB","60@0|T@6|///@11|B@16|105@21|BX@30|TX@31|","v2.06"
"VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form","xsrdpiz XT,XB","60@0|T@6|///@11|B@16|89@21|BX@30|TX@31|","v2.06"
"VSX Scalar Reciprocal Estimate Double-Precision XX2-form","xsredp XT,XB","60@0|T@6|///@11|B@16|90@21|BX@30|TX@31|","v2.06"
"VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form","xsrsqrtedp XT,XB","60@0|T@6|///@11|B@16|74@21|BX@30|TX@31|","v2.06"
"VSX Scalar Square Root Double-Precision XX2-form","xssqrtdp XT,XB","60@0|T@6|///@11|B@16|75@21|BX@30|TX@31|","v2.06"
"VSX Scalar Subtract Double-Precision XX3-form","xssubdp XT,XA,XB","60@0|T@6|A@11|B@16|40@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Scalar Test for software Divide Double-Precision XX3-form","xstdivdp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|61@21|AX@29|BX@30|/@31|","v2.06"
"VSX Scalar Test for software Square Root Double-Precision XX2-form","xstsqrtdp BF,XB","60@0|BF@6|//@9|///@11|B@16|106@21|BX@30|/@31|","v2.06"
"VSX Vector Absolute Value Double-Precision XX2-form","xvabsdp XT,XB","60@0|T@6|///@11|B@16|473@21|BX@30|TX@31|","v2.06"
"VSX Vector Absolute Value Single-Precision XX2-form","xvabssp XT,XB","60@0|T@6|///@11|B@16|409@21|BX@30|TX@31|","v2.06"
"VSX Vector Add Double-Precision XX3-form","xvadddp XT,XA,XB","60@0|T@6|A@11|B@16|96@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Add Single-Precision XX3-form","xvaddsp XT,XA,XB","60@0|T@6|A@11|B@16|64@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Compare Equal To Double-Precision XX3-form","xvcmpeqdp XT,XA,XB (Rc=0)|xvcmpeqdp. XT,XA,XB (Rc=1)","60@0|T@6|A@11|B@16|Rc@21|99@22|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Compare Equal To Single-Precision XX3-form","xvcmpeqsp XT,XA,XB (Rc=0)|xvcmpeqsp. XT,XA,XB (Rc=1)","60@0|T@6|A@11|B@16|Rc@21|67@22|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form","xvcmpgedp XT,XA,XB (Rc=0)|xvcmpgedp. XT,XA,XB (Rc=1)","60@0|T@6|A@11|B@16|Rc@21|115@22|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form","xvcmpgesp XT,XA,XB (Rc=0)|xvcmpgesp. XT,XA,XB (Rc=1)","60@0|T@6|A@11|B@16|Rc@21|83@22|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Compare Greater Than Double-Precision XX3-form","xvcmpgtdp XT,XA,XB (Rc=0)|xvcmpgtdp. XT,XA,XB (Rc=1)","60@0|T@6|A@11|B@16|Rc@21|107@22|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Compare Greater Than Single-Precision XX3-form","xvcmpgtsp XT,XA,XB (Rc=0)|xvcmpgtsp. XT,XA,XB (Rc=1)","60@0|T@6|A@11|B@16|Rc@21|75@22|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Copy Sign Double-Precision XX3-form","xvcpsgndp XT,XA,XB","60@0|T@6|A@11|B@16|240@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Copy Sign Single-Precision XX3-form","xvcpsgnsp XT,XA,XB","60@0|T@6|A@11|B@16|208@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Double-Precision to Single-Precision format XX2-form","xvcvdpsp XT,XB","60@0|T@6|///@11|B@16|393@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Double-Precision to Signed Doubleword format XX2-form","xvcvdpsxds XT,XB","60@0|T@6|///@11|B@16|472@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Double-Precision to Signed Word format XX2-form","xvcvdpsxws XT,XB","60@0|T@6|///@11|B@16|216@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form","xvcvdpuxds XT,XB","60@0|T@6|///@11|B@16|456@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Double-Precision to Unsigned Word format XX2-form","xvcvdpuxws XT,XB","60@0|T@6|///@11|B@16|200@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert Single-Precision to Double-Precision format XX2-form","xvcvspdp XT,XB","60@0|T@6|///@11|B@16|457@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-form","xvcvspsxds XT,XB","60@0|T@6|///@11|B@16|408@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Single-Precision to Signed Word format XX2-form","xvcvspsxws XT,XB","60@0|T@6|///@11|B@16|152@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Single-Precision to Unsigned Doubleword format XX2-form","xvcvspuxds XT,XB","60@0|T@6|///@11|B@16|392@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round to zero Single-Precision to Unsigned Word format XX2-form","xvcvspuxws XT,XB","60@0|T@6|///@11|B@16|136@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Signed Doubleword to Double-Precision format XX2-form","xvcvsxddp XT,XB","60@0|T@6|///@11|B@16|504@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Signed Doubleword to Single-Precision format XX2-form","xvcvsxdsp XT,XB","60@0|T@6|///@11|B@16|440@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert Signed Word to Double-Precision format XX2-form","xvcvsxwdp XT,XB","60@0|T@6|///@11|B@16|248@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Signed Word to Single-Precision format XX2-form","xvcvsxwsp XT,XB","60@0|T@6|///@11|B@16|184@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Unsigned Doubleword to Double-Precision format XX2-form","xvcvuxddp XT,XB","60@0|T@6|///@11|B@16|488@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Unsigned Doubleword to Single-Precision format XX2-form","xvcvuxdsp XT,XB","60@0|T@6|///@11|B@16|424@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert Unsigned Word to Double-Precision format XX2-form","xvcvuxwdp XT,XB","60@0|T@6|///@11|B@16|232@21|BX@30|TX@31|","v2.06"
"VSX Vector Convert with round Unsigned Word to Single-Precision format XX2-form","xvcvuxwsp XT,XB","60@0|T@6|///@11|B@16|168@21|BX@30|TX@31|","v2.06"
"VSX Vector Divide Double-Precision XX3-form","xvdivdp XT,XA,XB","60@0|T@6|A@11|B@16|120@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Divide Single-Precision XX3-form","xvdivsp XT,XA,XB","60@0|T@6|A@11|B@16|88@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Add Type-A Double-Precision XX3-form","xvmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|97@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Add Type-A Single-Precision XX3-form","xvmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|65@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Add Type-M Double-Precision XX3-form","xvmaddmdp XT,XA,XB","60@0|T@6|A@11|B@16|105@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Add Type-M Single-Precision XX3-form","xvmaddmsp XT,XA,XB","60@0|T@6|A@11|B@16|73@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Maximum Double-Precision XX3-form","xvmaxdp XT,XA,XB","60@0|T@6|A@11|B@16|224@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Maximum Single-Precision XX3-form","xvmaxsp XT,XA,XB","60@0|T@6|A@11|B@16|192@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Minimum Double-Precision XX3-form","xvmindp XT,XA,XB","60@0|T@6|A@11|B@16|232@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Minimum Single-Precision XX3-form","xvminsp XT,XA,XB","60@0|T@6|A@11|B@16|200@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Subtract Type-A Double-Precision XX3-form","xvmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|113@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Subtract Type-A Single-Precision XX3-form","xvmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|81@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Subtract Type-M Double-Precision XX3-form","xvmsubmdp XT,XA,XB","60@0|T@6|A@11|B@16|121@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply-Subtract Type-M Single-Precision XX3-form","xvmsubmsp XT,XA,XB","60@0|T@6|A@11|B@16|89@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply Double-Precision XX3-form","xvmuldp XT,XA,XB","60@0|T@6|A@11|B@16|112@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Multiply Single-Precision XX3-form","xvmulsp XT,XA,XB","60@0|T@6|A@11|B@16|80@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Absolute Double-Precision XX2-form","xvnabsdp XT,XB","60@0|T@6|///@11|B@16|489@21|BX@30|TX@31|","v2.06"
"VSX Vector Negative Absolute Single-Precision XX2-form","xvnabssp XT,XB","60@0|T@6|///@11|B@16|425@21|BX@30|TX@31|","v2.06"
"VSX Vector Negate Double-Precision XX2-form","xvnegdp XT,XB","60@0|T@6|///@11|B@16|505@21|BX@30|TX@31|","v2.06"
"VSX Vector Negate Single-Precision XX2-form","xvnegsp XT,XB","60@0|T@6|///@11|B@16|441@21|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Add Type-A Double-Precision XX3-form","xvnmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|225@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Add Type-A Single-Precision XX3-form","xvnmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|193@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Add Type-M Double-Precision XX3-form","xvnmaddmdp XT,XA,XB","60@0|T@6|A@11|B@16|233@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Add Type-M Single-Precision XX3-form","xvnmaddmsp XT,XA,XB","60@0|T@6|A@11|B@16|201@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Subtract Type-A Double-Precision XX3-form","xvnmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|241@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Subtract Type-A Single-Precision XX3-form","xvnmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|209@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Subtract Type-M Double-Precision XX3-form","xvnmsubmdp XT,XA,XB","60@0|T@6|A@11|B@16|249@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Negative Multiply-Subtract Type-M Single-Precision XX3-form","xvnmsubmsp XT,XA,XB","60@0|T@6|A@11|B@16|217@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form","xvrdpi XT,XB","60@0|T@6|///@11|B@16|201@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form","xvrdpic XT,XB","60@0|T@6|///@11|B@16|235@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form","xvrdpim XT,XB","60@0|T@6|///@11|B@16|249@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form","xvrdpip XT,XB","60@0|T@6|///@11|B@16|233@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form","xvrdpiz XT,XB","60@0|T@6|///@11|B@16|217@21|BX@30|TX@31|","v2.06"
"VSX Vector Reciprocal Estimate Double-Precision XX2-form","xvredp XT,XB","60@0|T@6|///@11|B@16|218@21|BX@30|TX@31|","v2.06"
"VSX Vector Reciprocal Estimate Single-Precision XX2-form","xvresp XT,XB","60@0|T@6|///@11|B@16|154@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form","xvrspi XT,XB","60@0|T@6|///@11|B@16|137@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form","xvrspic XT,XB","60@0|T@6|///@11|B@16|171@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form","xvrspim XT,XB","60@0|T@6|///@11|B@16|185@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form","xvrspip XT,XB","60@0|T@6|///@11|B@16|169@21|BX@30|TX@31|","v2.06"
"VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form","xvrspiz XT,XB","60@0|T@6|///@11|B@16|153@21|BX@30|TX@31|","v2.06"
"VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form","xvrsqrtedp XT,XB","60@0|T@6|///@11|B@16|202@21|BX@30|TX@31|","v2.06"
"VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form","xvrsqrtesp XT,XB","60@0|T@6|///@11|B@16|138@21|BX@30|TX@31|","v2.06"
"VSX Vector Square Root Double-Precision XX2-form","xvsqrtdp XT,XB","60@0|T@6|///@11|B@16|203@21|BX@30|TX@31|","v2.06"
"VSX Vector Square Root Single-Precision XX2-form","xvsqrtsp XT,XB","60@0|T@6|///@11|B@16|139@21|BX@30|TX@31|","v2.06"
"VSX Vector Subtract Double-Precision XX3-form","xvsubdp XT,XA,XB","60@0|T@6|A@11|B@16|104@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Subtract Single-Precision XX3-form","xvsubsp XT,XA,XB","60@0|T@6|A@11|B@16|72@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Test for software Divide Double-Precision XX3-form","xvtdivdp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|125@21|AX@29|BX@30|/@31|","v2.06"
"VSX Vector Test for software Divide Single-Precision XX3-form","xvtdivsp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|93@21|AX@29|BX@30|/@31|","v2.06"
"VSX Vector Test for software Square Root Double-Precision XX2-form","xvtsqrtdp BF,XB","60@0|BF@6|//@9|///@11|B@16|234@21|BX@30|/@31|","v2.06"
"VSX Vector Test for software Square Root Single-Precision XX2-form","xvtsqrtsp BF,XB","60@0|BF@6|//@9|///@11|B@16|170@21|BX@30|/@31|","v2.06"
"VSX Vector Logical AND XX3-form","xxland XT,XA,XB","60@0|T@6|A@11|B@16|130@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Logical AND with Complement XX3-form","xxlandc XT,XA,XB","60@0|T@6|A@11|B@16|138@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Logical NOR XX3-form","xxlnor XT,XA,XB","60@0|T@6|A@11|B@16|162@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Logical OR XX3-form","xxlor XT,XA,XB","60@0|T@6|A@11|B@16|146@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Logical XOR XX3-form","xxlxor XT,XA,XB","60@0|T@6|A@11|B@16|154@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Merge High Word XX3-form","xxmrghw XT,XA,XB","60@0|T@6|A@11|B@16|18@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Merge Low Word XX3-form","xxmrglw XT,XA,XB","60@0|T@6|A@11|B@16|50@21|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Permute Doubleword Immediate XX3-form","xxpermdi XT,XA,XB,DM","60@0|T@6|A@11|B@16|0@21|DM@22|10@24|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Select XX4-form","xxsel XT,XA,XB,XC","60@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Shift Left Double by Word Immediate XX3-form","xxsldwi XT,XA,XB,SHW","60@0|T@6|A@11|B@16|0@21|SHW@22|2@24|AX@29|BX@30|TX@31|","v2.06"
"VSX Vector Splat Word XX2-form","xxspltw XT,XB,UIM","60@0|T@6|///@11|UIM@14|B@16|164@21|BX@30|TX@31|","v2.06"
"Compare Bytes X-form","cmpb RA,RS,RB","31@0|RS@6|RA@11|RB@16|508@21|/@31|","v2.05"
"DFP Add X-form","dadd FRT,FRA,FRB (Rc=0)|dadd. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|2@21|Rc@31|","v2.05"
"DFP Add Quad X-form","daddq FRTp,FRAp,FRBp (Rc=0)|daddq. FRTp,FRAp,FRBp (Rc=1)","63@0|FRTp@6|FRAp@11|FRBp@16|2@21|Rc@31|","v2.05"
"DFP Convert From Fixed Quad X-form","dcffixq FRTp,FRB (Rc=0)|dcffixq. FRTp,FRB (Rc=1)","63@0|FRTp@6|///@11|FRB@16|802@21|Rc@31|","v2.05"
"DFP Compare Ordered X-form","dcmpo BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|130@21|/@31|","v2.05"
"DFP Compare Ordered Quad X-form","dcmpoq BF,FRAp,FRBp","63@0|BF@6|//@9|FRAp@11|FRBp@16|130@21|/@31|","v2.05"
"DFP Compare Unordered X-form","dcmpu BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|642@21|/@31|","v2.05"
"DFP Compare Unordered Quad X-form","dcmpuq BF,FRAp,FRBp","63@0|BF@6|//@9|FRAp@11|FRBp@16|642@21|/@31|","v2.05"
"DFP Convert To DFP Long X-form","dctdp FRT,FRB (Rc=0)|dctdp. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|258@21|Rc@31|","v2.05"
"DFP Convert To Fixed X-form","dctfix FRT,FRB (Rc=0)|dctfix. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|290@21|Rc@31|","v2.05"
"DFP Convert To Fixed Quad X-form","dctfixq FRT,FRBp (Rc=0)|dctfixq. FRT,FRBp (Rc=1)","63@0|FRT@6|///@11|FRBp@16|290@21|Rc@31|","v2.05"
"DFP Convert To DFP Extended X-form","dctqpq FRTp,FRB (Rc=0)|dctqpq. FRTp,FRB (Rc=1)","63@0|FRTp@6|///@11|FRB@16|258@21|Rc@31|","v2.05"
"DFP Decode DPD To BCD X-form","ddedpd SP,FRT,FRB (Rc=0)|ddedpd. SP,FRT,FRB (Rc=1)","59@0|FRT@6|SP@11|///@13|FRB@16|322@21|Rc@31|","v2.05"
"DFP Decode DPD To BCD Quad X-form","ddedpdq SP,FRTp,FRBp (Rc=0)|ddedpdq. SP,FRTp,FRBp (Rc=1)","63@0|FRTp@6|SP@11|///@13|FRBp@16|322@21|Rc@31|","v2.05"
"DFP Divide X-form","ddiv FRT,FRA,FRB (Rc=0)|ddiv. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|546@21|Rc@31|","v2.05"
"DFP Divide Quad X-form","ddivq FRTp,FRAp,FRBp (Rc=0)|ddivq. FRTp,FRAp,FRBp (Rc=1)","63@0|FRTp@6|FRAp@11|FRBp@16|546@21|Rc@31|","v2.05"
"DFP Encode BCD To DPD X-form","denbcd S,FRT,FRB (Rc=0)|denbcd. S,FRT,FRB (Rc=1)","59@0|FRT@6|S@11|///@12|FRB@16|834@21|Rc@31|","v2.05"
"DFP Encode BCD To DPD Quad X-form","denbcdq S,FRTp,FRBp (Rc=0)|denbcdq. S,FRTp,FRBp (Rc=1)","63@0|FRTp@6|S@11|///@12|FRBp@16|834@21|Rc@31|","v2.05"
"DFP Insert Biased Exponent X-form","diex FRT,FRA,FRB (Rc=0)|diex. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|866@21|Rc@31|","v2.05"
"DFP Insert Biased Exponent Quad X-form","diexq FRTp,FRA,FRBp|diexq. FRTp,FRA,FRBp (Rc=1)","63@0|FRTp@6|FRA@11|FRBp@16|866@21|Rc@31|","v2.05"
"DFP Multiply X-form","dmul FRT,FRA,FRB (Rc=0)|dmul. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|34@21|Rc@31|","v2.05"
"DFP Multiply Quad X-form","dmulq FRTp,FRAp,FRBp (Rc=0)|dmulq. FRTp,FRAp,FRBp (Rc=1)","63@0|FRTp@6|FRAp@11|FRBp@16|34@21|Rc@31|","v2.05"
"DFP Quantize Z23-form","dqua FRT,FRA,FRB,RMC (Rc=0)|dqua. FRT,FRA,FRB,RMC (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|RMC@21|3@23|Rc@31|","v2.05"
"DFP Quantize Immediate Z23-form","dquai TE,FRT,FRB,RMC (Rc=0)|dquai. TE,FRT,FRB,RMC (Rc=1)","59@0|FRT@6|TE@11|FRB@16|RMC@21|67@23|Rc@31|","v2.05"
"DFP Quantize Immediate Quad Z23-form","dquaiq TE,FRTp,FRBp,RMC (Rc=0)|dquaiq. TE,FRTp,FRBp,RMC (Rc=1)","63@0|FRTp@6|TE@11|FRBp@16|RMC@21|67@23|Rc@31|","v2.05"
"DFP Quantize Quad Z23-form","dquaq FRTp,FRAp,FRBp,RMC (Rc=0)|dquaq. FRTp,FRAp,FRBp,RMC (Rc=1)","63@0|FRTp@6|FRAp@11|FRBp@16|RMC@21|3@23|Rc@31|","v2.05"
"DFP Round To DFP Long X-form","drdpq FRTp,FRBp (Rc=0)|drdpq. FRTp,FRBp (Rc=1)","63@0|FRTp@6|///@11|FRBp@16|770@21|Rc@31|","v2.05"
"DFP Round To FP Integer Without Inexact Z23-form","drintn R,FRT,FRB,RMC (Rc=0)|drintn. R,FRT,FRB,RMC (Rc=1)","59@0|FRT@6|///@11|R@15|FRB@16|RMC@21|227@23|Rc@31|","v2.05"
"DFP Round To FP Integer Without Inexact Quad Z23-form","drintnq R,FRTp,FRBp,RMC (Rc=0)|drintnq. R,FRTp,FRBp,RMC (Rc=1)","63@0|FRTp@6|///@11|R@15|FRBp@16|RMC@21|227@23|Rc@31|","v2.05"
"DFP Round To FP Integer With Inexact Z23-form","drintx R,FRT,FRB,RMC (Rc=0)|drintx. R,FRT,FRB,RMC (Rc=1)","59@0|FRT@6|///@11|R@15|FRB@16|RMC@21|99@23|Rc@31|","v2.05"
"DFP Round To FP Integer With Inexact Quad Z23-form","drintxq R,FRTp,FRBp,RMC (Rc=0)|drintxq. R,FRTp,FRBp,RMC (Rc=1)","63@0|FRTp@6|///@11|R@15|FRBp@16|RMC@21|99@23|Rc@31|","v2.05"
"DFP Reround Z23-form","drrnd FRT,FRA,FRB,RMC (Rc=0)|drrnd. FRT,FRA,FRB,RMC (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|RMC@21|35@23|Rc@31|","v2.05"
"DFP Reround Quad Z23-form","drrndq FRTp,FRA,FRBp,RMC (Rc=0)|drrndq. FRTp,FRA,FRBp,RMC (Rc=1)","63@0|FRTp@6|FRA@11|FRBp@16|RMC@21|35@23|Rc@31|","v2.05"
"DFP Round To DFP Short X-form","drsp FRT,FRB (Rc=0)|drsp. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|770@21|Rc@31|","v2.05"
"DFP Shift Significand Left Immediate Z22-form","dscli FRT,FRA,SH (Rc=0)|dscli. FRT,FRA,SH (Rc=1)","59@0|FRT@6|FRA@11|SH@16|66@22|Rc@31|","v2.05"
"DFP Shift Significand Left Immediate Quad Z22-form","dscliq FRTp,FRAp,SH (Rc=0)|dscliq. FRTp,FRAp,SH (Rc=1)","63@0|FRTp@6|FRAp@11|SH@16|66@22|Rc@31|","v2.05"
"DFP Shift Significand Right Immediate Z22-form","dscri FRT,FRA,SH (Rc=0)|dscri. FRT,FRA,SH (Rc=1)","59@0|FRT@6|FRA@11|SH@16|98@22|Rc@31|","v2.05"
"DFP Shift Significand Right Immediate Quad Z22-form","dscriq FRTp,FRAp,SH (Rc=0)|dscriq. FRTp,FRAp,SH (Rc=1)","63@0|FRTp@6|FRAp@11|SH@16|98@22|Rc@31|","v2.05"
"DFP Subtract X-form","dsub FRT,FRA,FRB (Rc=0)|dsub. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|514@21|Rc@31|","v2.05"
"DFP Subtract Quad X-form","dsubq FRTp,FRAp,FRBp (Rc=0)|dsubq. FRTp,FRAp,FRBp (Rc=1)","63@0|FRTp@6|FRAp@11|FRBp@16|514@21|Rc@31|","v2.05"
"DFP Test Data Class Z22-form","dtstdc BF,FRA,DCM","59@0|BF@6|//@9|FRA@11|DCM@16|194@22|/@31|","v2.05"
"DFP Test Data Class Quad Z22-form","dtstdcq BF,FRAp,DCM","63@0|BF@6|//@9|FRAp@11|DCM@16|194@22|/@31|","v2.05"
"DFP Test Data Group Z22-form","dtstdg BF,FRA,DGM","59@0|BF@6|//@9|FRA@11|DGM@16|226@22|/@31|","v2.05"
"DFP Test Data Group Quad Z22-form","dtstdgq BF,FRAp,DGM","63@0|BF@6|//@9|FRAp@11|DGM@16|226@22|/@31|","v2.05"
"DFP Test Exponent X-form","dtstex BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|162@21|/@31|","v2.05"
"DFP Test Exponent Quad X-form","dtstexq BF,FRAp,FRBp","63@0|BF@6|//@9|FRAp@11|FRBp@16|162@21|/@31|","v2.05"
"DFP Test Significance X-form","dtstsf BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|674@21|/@31|","v2.05"
"DFP Test Significance Quad X-form","dtstsfq BF,FRA,FRBp","63@0|BF@6|//@9|FRA@11|FRBp@16|674@21|/@31|","v2.05"
"DFP Extract Biased Exponent X-form","dxex FRT,FRB (Rc=0)|dxex. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|354@21|Rc@31|","v2.05"
"DFP Extract Biased Exponent Quad X-form","dxexq FRT,FRBp (Rc=0)|dxexq. FRT,FRBp (Rc=1)","63@0|FRT@6|///@11|FRBp@16|354@21|Rc@31|","v2.05"
"Floating Copy Sign X-form","fcpsgn FRT, FRA, FRB (Rc=0)|fcpsgn. FRT, FRA, FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|8@21|Rc@31|","v2.05"
"Load Byte & Zero Caching Inhibited Indexed X-form","lbzcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|853@21|/@31|","v2.05"
"Load Doubleword Caching Inhibited Indexed X-form","ldcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|885@21|/@31|","v2.05"
"Load Floating-Point Double Pair DS-form","lfdp FRTp,DS(RA)","57@0|FRTp@6|RA@11|DS@16|0@30|","v2.05"
"Load Floating-Point Double Pair Indexed X-form","lfdpx FRTp,RA,RB","31@0|FRTp@6|RA@11|RB@16|791@21|/@31|","v2.05"
"Load Floating-Point as Integer Word Algebraic Indexed X-form","lfiwax FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|855@21|/@31|","v2.05"
"Load Halfword & Zero Caching Inhibited Indexed X-form","lhzcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|821@21|/@31|","v2.05"
"Load Word & Zero Caching Inhibited Indexed X-form","lwzcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|789@21|/@31|","v2.05"
"Parity Doubleword X-form","prtyd RA,RS","31@0|RS@6|RA@11|///@16|186@21|/@31|","v2.05"
"Parity Word X-form","prtyw RA,RS","31@0|RS@6|RA@11|///@16|154@21|/@31|","v2.05"
"SLB Find Entry ESID X-form","slbfee. RT,RB","31@0|RT@6|///@11|RB@16|979@21|1@31|","v2.05"
"Store Byte Caching Inhibited Indexed X-form","stbcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|981@21|/@31|","v2.05"
"Store Doubleword Caching Inhibited Indexed X-form","stdcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|1013@21|/@31|","v2.05"
"Store Floating-Point Double Pair DS-form","stfdp FRSp,DS(RA)","61@0|FRSp@6|RA@11|DS@16|0@30|","v2.05"
"Store Floating-Point Double Pair Indexed X-form","stfdpx FRSp,RA,RB","31@0|FRSp@6|RA@11|RB@16|919@21|/@31|","v2.05"
"Store Halfword Caching Inhibited Indexed X-form","sthcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|949@21|/@31|","v2.05"
"Store Word Caching Inhibited Indexed X-form","stwcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|917@21|/@31|","v2.05"
"Integer Select A-form","isel RT,RA,RB,BC","31@0|RT@6|RA@11|RB@16|BC@21|15@26|/@31|","v2.03"
"Load Vector Element Byte Indexed X-form","lvebx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|7@21|/@31|","v2.03"
"Load Vector Element Halfword Indexed X-form","lvehx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|39@21|/@31|","v2.03"
"Load Vector Element Word Indexed X-form","lvewx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|71@21|/@31|","v2.03"
"Load Vector for Shift Left Indexed X-form","lvsl VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|6@21|/@31|","v2.03"
"Load Vector for Shift Right Indexed X-form","lvsr VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|38@21|/@31|","v2.03"
"Load Vector Indexed X-form","lvx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|103@21|/@31|","v2.03"
"Load Vector Indexed Last X-form","lvxl VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|359@21|/@31|","v2.03"
"Move From Vector Status and Control Register VX-form","mfvscr VRT","4@0|VRT@6|///@11|///@16|1540@21|","v2.03"
"Move To Vector Status and Control Register VX-form","mtvscr VRB","4@0|///@6|///@11|VRB@16|1604@21|","v2.03"
"Store Vector Element Byte Indexed X-form","stvebx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|135@21|/@31|","v2.03"
"Store Vector Element Halfword Indexed X-form","stvehx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|167@21|/@31|","v2.03"
"Store Vector Element Word Indexed X-form","stvewx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|199@21|/@31|","v2.03"
"Store Vector Indexed X-form","stvx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|231@21|/@31|","v2.03"
"Store Vector Indexed Last X-form","stvxl VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|487@21|/@31|","v2.03"
"TLB Invalidate Entry Local X-form","tlbiel RB,RS,RIC,PRS,R","31@0|RS@6|/@11|RIC@12|PRS@14|R@15|RB@16|274@21|/@31|","v2.03"
"Vector Add & write Carry Unsigned Word VX-form","vaddcuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|384@21|","v2.03"
"Vector Add Floating-Point VX-form","vaddfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|10@21|","v2.03"
"Vector Add Signed Byte Saturate VX-form","vaddsbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|768@21|","v2.03"
"Vector Add Signed Halfword Saturate VX-form","vaddshs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|832@21|","v2.03"
"Vector Add Signed Word Saturate VX-form","vaddsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|896@21|","v2.03"
"Vector Add Unsigned Byte Modulo VX-form","vaddubm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|0@21|","v2.03"
"Vector Add Unsigned Byte Saturate VX-form","vaddubs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|512@21|","v2.03"
"Vector Add Unsigned Halfword Modulo VX-form","vadduhm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|64@21|","v2.03"
"Vector Add Unsigned Halfword Saturate VX-form","vadduhs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|576@21|","v2.03"
"Vector Add Unsigned Word Modulo VX-form","vadduwm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|128@21|","v2.03"
"Vector Add Unsigned Word Saturate VX-form","vadduws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|640@21|","v2.03"
"Vector Logical AND VX-form","vand VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1028@21|","v2.03"
"Vector Logical AND with Complement VX-form","vandc VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1092@21|","v2.03"
"Vector Average Signed Byte VX-form","vavgsb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1282@21|","v2.03"
"Vector Average Signed Halfword VX-form","vavgsh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1346@21|","v2.03"
"Vector Average Signed Word VX-form","vavgsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1410@21|","v2.03"
"Vector Average Unsigned Byte VX-form","vavgub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1026@21|","v2.03"
"Vector Average Unsigned Halfword VX-form","vavguh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1090@21|","v2.03"
"Vector Average Unsigned Word VX-form","vavguw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1154@21|","v2.03"
"Vector Convert with round to nearest From Signed Word to floating-point format VX-form","vcfsx VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|842@21|","v2.03"
"Vector Convert with round to nearest From Unsigned Word to floating-point format VX-form","vcfux VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|778@21|","v2.03"
"Vector Compare Bounds Floating-Point VC-form","vcmpbfp VRT,VRA,VRB (Rc=0)|vcmpbfp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|966@22|","v2.03"
"Vector Compare Equal Floating-Point VC-form","vcmpeqfp VRT,VRA,VRB (Rc=0)|vcmpeqfp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|198@22|","v2.03"
"Vector Compare Equal Unsigned Byte VC-form","vcmpequb VRT,VRA,VRB (Rc=0)|vcmpequb. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|6@22|","v2.03"
"Vector Compare Equal Unsigned Halfword VC-form","vcmpequh VRT,VRA,VRB (Rc=0)|vcmpequh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|70@22|","v2.03"
"Vector Compare Equal Unsigned Word VC-form","vcmpequw VRT,VRA,VRB (Rc=0)|vcmpequw. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|134@22|","v2.03"
"Vector Compare Greater Than or Equal Floating-Point VC-form","vcmpgefp VRT,VRA,VRB (Rc=0)|vcmpgefp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|454@22|","v2.03"
"Vector Compare Greater Than Floating-Point VC-form","vcmpgtfp VRT,VRA,VRB (Rc=0)|vcmpgtfp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|710@22|","v2.03"
"Vector Compare Greater Than Signed Byte VC-form","vcmpgtsb VRT,VRA,VRB (Rc=0)|vcmpgtsb. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|774@22|","v2.03"
"Vector Compare Greater Than Signed Halfword VC-form","vcmpgtsh VRT,VRA,VRB (Rc=0)|vcmpgtsh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|838@22|","v2.03"
"Vector Compare Greater Than Signed Word VC-form","vcmpgtsw VRT,VRA,VRB (Rc=0)|vcmpgtsw. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|902@22|","v2.03"
"Vector Compare Greater Than Unsigned Byte VC-form","vcmpgtub VRT,VRA,VRB (Rc=0)|vcmpgtub. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|518@22|","v2.03"
"Vector Compare Greater Than Unsigned Halfword VC-form","vcmpgtuh VRT,VRA,VRB (Rc=0)|vcmpgtuh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|582@22|","v2.03"
"Vector Compare Greater Than Unsigned Word VC-form","vcmpgtuw VRT,VRA,VRB (Rc=0)|vcmpgtuw. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|646@22|","v2.03"
"Vector Convert with round to zero from floating-point To Signed Word format Saturate VX-form","vctsxs VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|970@21|","v2.03"
"Vector Convert with round to zero from floating-point To Unsigned Word format Saturate VX-form","vctuxs VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|906@21|","v2.03"
"Vector 2 Raised to the Exponent Estimate Floating-Point VX-form","vexptefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|394@21|","v2.03"
"Vector Log Base 2 Estimate Floating-Point VX-form","vlogefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|458@21|","v2.03"
"Vector Multiply-Add Floating-Point VA-form","vmaddfp VRT,VRA,VRC,VRB","4@0|VRT@6|VRA@11|VRB@16|VRC@21|46@26|","v2.03"
"Vector Maximum Floating-Point VX-form","vmaxfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1034@21|","v2.03"
"Vector Maximum Signed Byte VX-form","vmaxsb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|258@21|","v2.03"
"Vector Maximum Signed Halfword VX-form","vmaxsh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|322@21|","v2.03"
"Vector Maximum Signed Word VX-form","vmaxsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|386@21|","v2.03"
"Vector Maximum Unsigned Byte VX-form","vmaxub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|2@21|","v2.03"
"Vector Maximum Unsigned Halfword VX-form","vmaxuh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|66@21|","v2.03"
"Vector Maximum Unsigned Word VX-form","vmaxuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|130@21|","v2.03"
"Vector Multiply-High-Add Signed Halfword Saturate VA-form","vmhaddshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|32@26|","v2.03"
"Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form","vmhraddshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|33@26|","v2.03"
"Vector Minimum Floating-Point VX-form","vminfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1098@21|","v2.03"
"Vector Minimum Signed Byte VX-form","vminsb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|770@21|","v2.03"
"Vector Minimum Signed Halfword VX-form","vminsh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|834@21|","v2.03"
"Vector Minimum Signed Word VX-form","vminsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|898@21|","v2.03"
"Vector Minimum Unsigned Byte VX-form","vminub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|514@21|","v2.03"
"Vector Minimum Unsigned Halfword VX-form","vminuh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|578@21|","v2.03"
"Vector Minimum Unsigned Word VX-form","vminuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|642@21|","v2.03"
"Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form","vmladduhm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|34@26|","v2.03"
"Vector Merge High Byte VX-form","vmrghb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|12@21|","v2.03"
"Vector Merge High Halfword VX-form","vmrghh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|76@21|","v2.03"
"Vector Merge High Word VX-form","vmrghw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|140@21|","v2.03"
"Vector Merge Low Byte VX-form","vmrglb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|268@21|","v2.03"
"Vector Merge Low Halfword VX-form","vmrglh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|332@21|","v2.03"
"Vector Merge Low Word VX-form","vmrglw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|396@21|","v2.03"
"Vector Multiply-Sum Mixed Byte Modulo VA-form","vmsummbm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|37@26|","v2.03"
"Vector Multiply-Sum Signed Halfword Modulo VA-form","vmsumshm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|40@26|","v2.03"
"Vector Multiply-Sum Signed Halfword Saturate VA-form","vmsumshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|41@26|","v2.03"
"Vector Multiply-Sum Unsigned Byte Modulo VA-form","vmsumubm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|36@26|","v2.03"
"Vector Multiply-Sum Unsigned Halfword Modulo VA-form","vmsumuhm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|38@26|","v2.03"
"Vector Multiply-Sum Unsigned Halfword Saturate VA-form","vmsumuhs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|39@26|","v2.03"
"Vector Multiply Even Signed Byte VX-form","vmulesb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|776@21|","v2.03"
"Vector Multiply Even Signed Halfword VX-form","vmulesh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|840@21|","v2.03"
"Vector Multiply Even Unsigned Byte VX-form","vmuleub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|520@21|","v2.03"
"Vector Multiply Even Unsigned Halfword VX-form","vmuleuh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|584@21|","v2.03"
"Vector Multiply Odd Signed Byte VX-form","vmulosb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|264@21|","v2.03"
"Vector Multiply Odd Signed Halfword VX-form","vmulosh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|328@21|","v2.03"
"Vector Multiply Odd Unsigned Byte VX-form","vmuloub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|8@21|","v2.03"
"Vector Multiply Odd Unsigned Halfword VX-form","vmulouh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|72@21|","v2.03"
"Vector Negative Multiply-Subtract Floating-Point VA-form","vnmsubfp VRT,VRA,VRC,VRB","4@0|VRT@6|VRA@11|VRB@16|VRC@21|47@26|","v2.03"
"Vector Logical NOR VX-form","vnor VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1284@21|","v2.03"
"Vector Logical OR VX-form","vor VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1156@21|","v2.03"
"Vector Permute VA-form","vperm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|43@26|","v2.03"
"Vector Pack Pixel VX-form","vpkpx VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|782@21|","v2.03"
"Vector Pack Signed Halfword Signed Saturate VX-form","vpkshss VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|398@21|","v2.03"
"Vector Pack Signed Halfword Unsigned Saturate VX-form","vpkshus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|270@21|","v2.03"
"Vector Pack Signed Word Signed Saturate VX-form","vpkswss VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|462@21|","v2.03"
"Vector Pack Signed Word Unsigned Saturate VX-form","vpkswus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|334@21|","v2.03"
"Vector Pack Unsigned Halfword Unsigned Modulo VX-form","vpkuhum VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|14@21|","v2.03"
"Vector Pack Unsigned Halfword Unsigned Saturate VX-form","vpkuhus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|142@21|","v2.03"
"Vector Pack Unsigned Word Unsigned Modulo VX-form","vpkuwum VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|78@21|","v2.03"
"Vector Pack Unsigned Word Unsigned Saturate VX-form","vpkuwus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|206@21|","v2.03"
"Vector Reciprocal Estimate Floating-Point VX-form","vrefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|266@21|","v2.03"
"Vector Round to Floating-Point Integer toward -Infinity VX-form","vrfim VRT,VRB","4@0|VRT@6|///@11|VRB@16|714@21|","v2.03"
"Vector Round to Floating-Point Integer Nearest VX-form","vrfin VRT,VRB","4@0|VRT@6|///@11|VRB@16|522@21|","v2.03"
"Vector Round to Floating-Point Integer toward +Infinity VX-form","vrfip VRT,VRB","4@0|VRT@6|///@11|VRB@16|650@21|","v2.03"
"Vector Round to Floating-Point Integer toward Zero VX-form","vrfiz VRT,VRB","4@0|VRT@6|///@11|VRB@16|586@21|","v2.03"
"Vector Rotate Left Byte VX-form","vrlb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|4@21|","v2.03"
"Vector Rotate Left Halfword VX-form","vrlh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|68@21|","v2.03"
"Vector Rotate Left Word VX-form","vrlw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|132@21|","v2.03"
"Vector Reciprocal Square Root Estimate Floating-Point VX-form","vrsqrtefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|330@21|","v2.03"
"Vector Select VA-form","vsel VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|42@26|","v2.03"
"Vector Shift Left VX-form","vsl VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|452@21|","v2.03"
"Vector Shift Left Byte VX-form","vslb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|260@21|","v2.03"
"Vector Shift Left Double by Octet Immediate VA-form","vsldoi VRT,VRA,VRB,SHB","4@0|VRT@6|VRA@11|VRB@16|/@21|SHB@22|44@26|","v2.03"
"Vector Shift Left Halfword VX-form","vslh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|324@21|","v2.03"
"Vector Shift Left by Octet VX-form","vslo VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1036@21|","v2.03"
"Vector Shift Left Word VX-form","vslw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|388@21|","v2.03"
"Vector Splat Byte VX-form","vspltb VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|524@21|","v2.03"
"Vector Splat Halfword VX-form","vsplth VRT,VRB,UIM","4@0|VRT@6|//@11|UIM@13|VRB@16|588@21|","v2.03"
"Vector Splat Immediate Signed Byte VX-form","vspltisb VRT,SIM","4@0|VRT@6|SIM@11|///@16|780@21|","v2.03"
"Vector Splat Immediate Signed Halfword VX-form","vspltish VRT,SIM","4@0|VRT@6|SIM@11|///@16|844@21|","v2.03"
"Vector Splat Immediate Signed Word VX-form","vspltisw VRT,SIM","4@0|VRT@6|SIM@11|///@16|908@21|","v2.03"
"Vector Splat Word VX-form","vspltw VRT,VRB,UIM","4@0|VRT@6|///@11|UIM@14|VRB@16|652@21|","v2.03"
"Vector Shift Right VX-form","vsr VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|708@21|","v2.03"
"Vector Shift Right Algebraic Byte VX-form","vsrab VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|772@21|","v2.03"
"Vector Shift Right Algebraic Halfword VX-form","vsrah VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|836@21|","v2.03"
"Vector Shift Right Algebraic Word VX-form","vsraw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|900@21|","v2.03"
"Vector Shift Right Byte VX-form","vsrb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|516@21|","v2.03"
"Vector Shift Right Halfword VX-form","vsrh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|580@21|","v2.03"
"Vector Shift Right by Octet VX-form","vsro VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1100@21|","v2.03"
"Vector Shift Right Word VX-form","vsrw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|644@21|","v2.03"
"Vector Subtract & Write Carry-out Unsigned Word VX-form","vsubcuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1408@21|","v2.03"
"Vector Subtract Floating-Point VX-form","vsubfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|74@21|","v2.03"
"Vector Subtract Signed Byte Saturate VX-form","vsubsbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1792@21|","v2.03"
"Vector Subtract Signed Halfword Saturate VX-form","vsubshs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1856@21|","v2.03"
"Vector Subtract Signed Word Saturate VX-form","vsubsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1920@21|","v2.03"
"Vector Subtract Unsigned Byte Modulo VX-form","vsububm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1024@21|","v2.03"
"Vector Subtract Unsigned Byte Saturate VX-form","vsububs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1536@21|","v2.03"
"Vector Subtract Unsigned Halfword Modulo VX-form","vsubuhm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1088@21|","v2.03"
"Vector Subtract Unsigned Halfword Saturate VX-form","vsubuhs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1600@21|","v2.03"
"Vector Subtract Unsigned Word Modulo VX-form","vsubuwm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1152@21|","v2.03"
"Vector Subtract Unsigned Word Saturate VX-form","vsubuws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1664@21|","v2.03"
"Vector Sum across Half Signed Word Saturate VX-form","vsum2sws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1672@21|","v2.03"
"Vector Sum across Quarter Signed Byte Saturate VX-form","vsum4sbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1800@21|","v2.03"
"Vector Sum across Quarter Signed Halfword Saturate VX-form","vsum4shs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1608@21|","v2.03"
"Vector Sum across Quarter Unsigned Byte Saturate VX-form","vsum4ubs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1544@21|","v2.03"
"Vector Sum across Signed Word Saturate VX-form","vsumsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1928@21|","v2.03"
"Vector Unpack High Pixel VX-form","vupkhpx VRT,VRB","4@0|VRT@6|///@11|VRB@16|846@21|","v2.03"
"Vector Unpack High Signed Byte VX-form","vupkhsb VRT,VRB","4@0|VRT@6|///@11|VRB@16|526@21|","v2.03"
"Vector Unpack High Signed Halfword VX-form","vupkhsh VRT,VRB","4@0|VRT@6|///@11|VRB@16|590@21|","v2.03"
"Vector Unpack Low Pixel VX-form","vupklpx VRT,VRB","4@0|VRT@6|///@11|VRB@16|974@21|","v2.03"
"Vector Unpack Low Signed Byte VX-form","vupklsb VRT,VRB","4@0|VRT@6|///@11|VRB@16|654@21|","v2.03"
"Vector Unpack Low Signed Halfword VX-form","vupklsh VRT,VRB","4@0|VRT@6|///@11|VRB@16|718@21|","v2.03"
"Vector Logical XOR VX-form","vxor VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1220@21|","v2.03"
"Floating Reciprocal Estimate A-form","fre FRT,FRB (Rc=0)|fre. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|///@21|24@26|Rc@31|","v2.02"
"Floating Round to Integer Minus X-form","frim FRT,FRB (Rc=0)|frim. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|488@21|Rc@31|","v2.02"
"Floating Round to Integer Nearest X-form","frin FRT,FRB (Rc=0)|frin. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|392@21|Rc@31|","v2.02"
"Floating Round to Integer Plus X-form","frip FRT,FRB (Rc=0)|frip. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|456@21|Rc@31|","v2.02"
"Floating Round to Integer Toward Zero X-form","friz FRT,FRB (Rc=0)|friz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|424@21|Rc@31|","v2.02"
"Floating Reciprocal Square Root Estimate Single A-form","frsqrtes FRT,FRB (Rc=0)|frsqrtes. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|///@21|26@26|Rc@31|","v2.02"
"Return From Interrupt Doubleword Hypervisor XL-form","hrfid","19@0|///@6|///@11|///@16|274@21|/@31|","v2.02"
"Population Count Bytes X-form","popcntb RA, RS","31@0|RS@6|RA@11|///@16|122@21|/@31|","v2.02"
"Move From One Condition Register Field XFX-form","mfocrf RT,FXM","31@0|RT@6|1@11|FXM@12|/@20|19@21|/@31|","v2.01"
"Move To One Condition Register Field XFX-form","mtocrf FXM,RS","31@0|RS@6|1@11|FXM@12|/@20|144@21|/@31|","v2.01"
"SLB Move From Entry ESID X-form","slbmfee RT,RB","31@0|RT@6|///@11|L@15|RB@16|915@21|/@31|","v2.00"
"SLB Move From Entry VSID X-form","slbmfev RT,RB","31@0|RT@6|///@11|L@15|RB@16|851@21|/@31|","v2.00"
"SLB Move To Entry X-form","slbmte RS,RB","31@0|RS@6|///@11|RB@16|402@21|/@31|","v2.00"
"Return From System Call Vectored XL-form","rfscv","19@0|///@6|///@11|///@16|82@21|/@31|","v3.0"
"System Call Vectored SC-form","scv LEV","17@0|///@6|///@11|///@16|LEV@20|///@27|0@30|1@31|","v3.0"
"Load Quadword DQ-form","lq RTp,DQ(RA)","56@0|RTp@6|RA@11|DQ@16|///@28|","v2.03"
"Store Quadword DS-form","stq RSp,DS(RA)","62@0|RSp@6|RA@11|DS@16|2@30|","v2.03"
"Count Leading Zeros Doubleword X-form","cntlzd RA,RS (Rc=0)|cntlzd. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|58@21|Rc@31|","PPC"
"Data Cache Block Flush X-form","dcbf RA,RB,L","31@0|//@6|L@8|RA@11|RB@16|86@21|/@31|","PPC"
"Data Cache Block Store X-form","dcbst RA,RB","31@0|///@6|RA@11|RB@16|54@21|/@31|","PPC"
"Data Cache Block Touch X-form","dcbt RA,RB,TH","31@0|TH@6|RA@11|RB@16|278@21|/@31|","PPC"
"Data Cache Block Touch for Store X-form","dcbtst RA,RB,TH","31@0|TH@6|RA@11|RB@16|246@21|/@31|","PPC"
"Divide Doubleword XO-form","divd RT,RA,RB (OE=0 Rc=0)|divd. RT,RA,RB (OE=0 Rc=1)|divdo RT,RA,RB (OE=1 Rc=0)|divdo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|489@22|Rc@31|","PPC"
"Divide Doubleword Unsigned XO-form","divdu RT,RA,RB (OE=0 Rc=0)|divdu. RT,RA,RB (OE=0 Rc=1)|divduo RT,RA,RB (OE=1 Rc=0)|divduo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|457@22|Rc@31|","PPC"
"Divide Word XO-form","divw RT,RA,RB (OE=0 Rc=0)|divw. RT,RA,RB (OE=0 Rc=1)|divwo RT,RA,RB (OE=1 Rc=0)|divwo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|491@22|Rc@31|","PPC"
"Divide Word Unsigned XO-form","divwu RT,RA,RB (OE=0 Rc=0)|divwu. RT,RA,RB (OE=0 Rc=1)|divwuo RT,RA,RB (OE=1 Rc=0)|divwuo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|459@22|Rc@31|","PPC"
"Enforce In-order Execution of I/O X-form","eieio","31@0|///@6|///@11|///@16|854@21|/@31|","PPC"
"Extend Sign Byte X-form","extsb RA,RS (Rc=0)|extsb. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|954@21|Rc@31|","PPC"
"Extend Sign Word X-form","extsw RA,RS (Rc=0)|extsw. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|986@21|Rc@31|","PPC"
"Floating Add Single A-form","fadds FRT,FRA,FRB (Rc=0)|fadds. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|///@21|21@26|Rc@31|","PPC"
"Floating Convert with round Signed Doubleword to Double-Precision format X-form","fcfid FRT,FRB (Rc=0)|fcfid. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|846@21|Rc@31|","PPC"
"Floating Convert with round Double-Precision To Signed Doubleword format X-form","fctid FRT,FRB (Rc=0)|fctid. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|814@21|Rc@31|","PPC"
"Floating Convert with truncate Double-Precision To Signed Doubleword format X-form","fctidz FRT,FRB (Rc=0)|fctidz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|815@21|Rc@31|","PPC"
"Floating Divide Single A-form","fdivs FRT,FRA,FRB (Rc=0)|fdivs. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|///@21|18@26|Rc@31|","PPC"
"Floating Multiply-Add Single A-form","fmadds FRT,FRA,FRC,FRB (Rc=0)|fmadds. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|29@26|Rc@31|","PPC"
"Floating Multiply-Subtract Single A-form","fmsubs FRT,FRA,FRC,FRB (Rc=0)|fmsubs. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|28@26|Rc@31|","PPC"
"Floating Multiply Single A-form","fmuls FRT,FRA,FRC (Rc=0)|fmuls. FRT,FRA,FRC (Rc=1)","59@0|FRT@6|FRA@11|///@16|FRC@21|25@26|Rc@31|","PPC"
"Floating Negative Multiply-Add Single A-form","fnmadds FRT,FRA,FRC,FRB (Rc=0)|fnmadds. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|31@26|Rc@31|","PPC"
"Floating Negative Multiply-Subtract Single A-form","fnmsubs FRT,FRA,FRC,FRB (Rc=0)|fnmsubs. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|30@26|Rc@31|","PPC"
"Floating Reciprocal Estimate Single A-form","fres FRT,FRB (Rc=0)|fres. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|///@21|24@26|Rc@31|","PPC"
"Floating Reciprocal Square Root Estimate A-form","frsqrte FRT,FRB (Rc=0)|frsqrte. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|///@21|26@26|Rc@31|","PPC"
"Floating Select A-form","fsel FRT,FRA,FRC,FRB (Rc=0)|fsel. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|23@26|Rc@31|","PPC"
"Floating Square Root Single A-form","fsqrts FRT,FRB (Rc=0)|fsqrts. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|///@21|22@26|Rc@31|","PPC"
"Floating Subtract Single A-form","fsubs FRT,FRA,FRB (Rc=0)|fsubs. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|///@21|20@26|Rc@31|","PPC"
"Instruction Cache Block Invalidate X-form","icbi RA,RB","31@0|///@6|RA@11|RB@16|982@21|/@31|","PPC"
"Load Doubleword DS-form","ld RT,DS(RA)","58@0|RT@6|RA@11|DS@16|0@30|","PPC"
"Load Doubleword And Reserve Indexed X-form","ldarx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|84@21|EH@31|","PPC"
"Load Doubleword with Update DS-form","ldu RT,DS(RA)","58@0|RT@6|RA@11|DS@16|1@30|","PPC"
"Load Doubleword with Update Indexed X-form","ldux RT,RA,RB","31@0|RT@6|RA@11|RB@16|53@21|/@31|","PPC"
"Load Doubleword Indexed X-form","ldx RT,RA,RB","31@0|RT@6|RA@11|RB@16|21@21|/@31|","PPC"
"Load Word Algebraic DS-form","lwa RT,DS(RA)","58@0|RT@6|RA@11|DS@16|2@30|","PPC"
"Load Word & Reserve Indexed X-form","lwarx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|20@21|EH@31|","PPC"
"Load Word Algebraic with Update Indexed X-form","lwaux RT,RA,RB","31@0|RT@6|RA@11|RB@16|373@21|/@31|","PPC"
"Load Word Algebraic Indexed X-form","lwax RT,RA,RB","31@0|RT@6|RA@11|RB@16|341@21|/@31|","PPC"
"Move From Time Base XFX-form","mftb RT,TBR","31@0|RT@6|tbr@11|371@21|/@31|","PPC"
"Move To MSR Doubleword X-form","mtmsrd RS,L","31@0|RS@6|///@11|L@15|///@16|178@21|/@31|","PPC"
"Multiply High Doubleword XO-form","mulhd RT,RA,RB (Rc=0)|mulhd. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|73@22|Rc@31|","PPC"
"Multiply High Doubleword Unsigned XO-form","mulhdu RT,RA,RB (Rc=0)|mulhdu. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|9@22|Rc@31|","PPC"
"Multiply High Word XO-form","mulhw RT,RA,RB (Rc=0)|mulhw. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|75@22|Rc@31|","PPC"
"Multiply High Word Unsigned XO-form","mulhwu RT,RA,RB (Rc=0)|mulhwu. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|11@22|Rc@31|","PPC"
"Multiply Low Doubleword XO-form","mulld RT,RA,RB (OE=0 Rc=0)|mulld. RT,RA,RB (OE=0 Rc=1)|mulldo RT,RA,RB (OE=1 Rc=0)|mulldo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|233@22|Rc@31|","PPC"
"Return from Interrupt Doubleword XL-form","rfid","19@0|///@6|///@11|///@16|18@21|/@31|","PPC"
"Rotate Left Doubleword then Clear Left MDS-form","rldcl RA,RS,RB,MB (Rc=0)|rldcl. RA,RS,RB,MB (Rc=1)","30@0|RS@6|RA@11|RB@16|mb@21|8@27|Rc@31|","PPC"
"Rotate Left Doubleword then Clear Right MDS-form","rldcr RA,RS,RB,ME (Rc=0)|rldcr. RA,RS,RB,ME (Rc=1)","30@0|RS@6|RA@11|RB@16|me@21|9@27|Rc@31|","PPC"
"Rotate Left Doubleword Immediate then Clear MD-form","rldic RA,RS,SH,MB (Rc=0)|rldic. RA,RS,SH,MB (Rc=1)","30@0|RS@6|RA@11|sh@16|mb@21|2@27|sh@30|Rc@31|","PPC"
"Rotate Left Doubleword Immediate then Clear Left MD-form","rldicl RA,RS,SH,MB (Rc=0)|rldicl. RA,RS,SH,MB (Rc=1)","30@0|RS@6|RA@11|sh@16|mb@21|0@27|sh@30|Rc@31|","PPC"
"Rotate Left Doubleword Immediate then Clear Right MD-form","rldicr RA,RS,SH,ME (Rc=0)|rldicr. RA,RS,SH,ME (Rc=1)","30@0|RS@6|RA@11|sh@16|me@21|1@27|sh@30|Rc@31|","PPC"
"Rotate Left Doubleword Immediate then Mask Insert MD-form","rldimi RA,RS,SH,MB (Rc=0)|rldimi. RA,RS,SH,MB (Rc=1)","30@0|RS@6|RA@11|sh@16|mb@21|3@27|sh@30|Rc@31|","PPC"
"System Call SC-form","sc LEV","17@0|///@6|///@11|///@16|LEV@20|///@27|1@30|/@31|","PPC"
"SLB Invalidate All X-form","slbia IH","31@0|//@6|IH@8|///@11|///@16|498@21|/@31|","PPC"
"SLB Invalidate Entry X-form","slbie RB","31@0|///@6|///@11|RB@16|434@21|/@31|","PPC"
"Shift Left Doubleword X-form","sld RA,RS,RB (Rc=0)|sld. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|27@21|Rc@31|","PPC"
"Shift Right Algebraic Doubleword X-form","srad RA,RS,RB (Rc=0)|srad. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|794@21|Rc@31|","PPC"
"Shift Right Algebraic Doubleword Immediate XS-form","sradi RA,RS,SH (Rc=0)|sradi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|sh@16|413@21|sh@30|Rc@31|","PPC"
"Shift Right Doubleword X-form","srd RA,RS,RB (Rc=0)|srd. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|539@21|Rc@31|","PPC"
"Store Doubleword DS-form","std RS,DS(RA)","62@0|RS@6|RA@11|DS@16|0@30|","PPC"
"Store Doubleword Conditional Indexed X-form","stdcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|214@21|1@31|","PPC"
"Store Doubleword with Update DS-form","stdu RS,DS(RA)","62@0|RS@6|RA@11|DS@16|1@30|","PPC"
"Store Doubleword with Update Indexed X-form","stdux RS,RA,RB","31@0|RS@6|RA@11|RB@16|181@21|/@31|","PPC"
"Store Doubleword Indexed X-form","stdx RS,RA,RB","31@0|RS@6|RA@11|RB@16|149@21|/@31|","PPC"
"Store Floating-Point as Integer Word Indexed X-form","stfiwx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|983@21|/@31|","PPC"
"Store Word Conditional Indexed X-form","stwcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|150@21|1@31|","PPC"
"Subtract From XO-form","subf RT,RA,RB (OE=0 Rc=0)|subf. RT,RA,RB (OE=0 Rc=1)|subfo RT,RA,RB (OE=1 Rc=0)|subfo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|40@22|Rc@31|","PPC"
"Trap Doubleword X-form","td TO,RA,RB","31@0|TO@6|RA@11|RB@16|68@21|/@31|","PPC"
"Trap Doubleword Immediate D-form","tdi TO,RA,SI","2@0|TO@6|RA@11|SI@16|","PPC"
"TLB Synchronize X-form","tlbsync","31@0|///@6|///@11|///@16|566@21|/@31|","PPC"
"Floating Convert with round Double-Precision To Signed Word format X-form","fctiw FRT,FRB (Rc=0)|fctiw. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|14@21|Rc@31|","P2"
"Floating Convert with truncate Double-Precision To Signed Word fomat X-form","fctiwz FRT,FRB (Rc=0)|fctiwz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|15@21|Rc@31|","P2"
"Floating Square Root A-form","fsqrt FRT,FRB (Rc=0)|fsqrt. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|///@21|22@26|Rc@31|","P2"
"Add XO-form","add RT,RA,RB (OE=0 Rc=0)|add. RT,RA,RB (OE=0 Rc=1)|addo RT,RA,RB (OE=1 Rc=0)|addo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|266@22|Rc@31|","P1"
"Add Carrying XO-form","addc RT,RA,RB (OE=0 Rc=0)|addc. RT,RA,RB (OE=0 Rc=1)|addco RT,RA,RB (OE=1 Rc=0)|addco. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|10@22|Rc@31|","P1"
"Add Extended XO-form","adde RT,RA,RB (OE=0 Rc=0)|adde. RT,RA,RB (OE=0 Rc=1)|addeo RT,RA,RB (OE=1 Rc=0)|addeo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|138@22|Rc@31|","P1"
"Add Immediate D-form","addi RT,RA,SI|li RT,SI (RA=0)","14@0|RT@6|RA@11|SI@16|","P1"
"Add Immediate Carrying D-form","addic RT,RA,SI","12@0|RT@6|RA@11|SI@16|","P1"
"Add Immediate Carrying and Record D-form","addic. RT,RA,SI","13@0|RT@6|RA@11|SI@16|","P1"
"Add Immediate Shifted D-form","addis RT,RA,SI|lis RT,SI (RA=0)","15@0|RT@6|RA@11|SI@16|","P1"
"Add to Minus One Extended XO-form","addme RT,RA (OE=0 Rc=0)|addme. RT,RA (OE=0 Rc=1)|addmeo RT,RA (OE=1 Rc=0)|addmeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|234@22|Rc@31|","P1"
"Add to Zero Extended XO-form","addze RT,RA (OE=0 Rc=0)|addze. RT,RA (OE=0 Rc=1)|addzeo RT,RA (OE=1 Rc=0)|addzeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|202@22|Rc@31|","P1"
"AND X-form","and RA,RS,RB (Rc=0)|and. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|28@21|Rc@31|","P1"
"AND with Complement X-form","andc RA,RS,RB (Rc=0)|andc. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|60@21|Rc@31|","P1"
"AND Immediate D-form","andi. RA,RS,UI","28@0|RS@6|RA@11|UI@16|","P1"
"AND Immediate Shifted D-form","andis. RA,RS,UI","29@0|RS@6|RA@11|UI@16|","P1"
"Branch I-form","b target_addr (AA=0 LK=0)|ba target_addr (AA=1 LK=0)|bl target_addr (AA=0 LK=1)|bla target_addr (AA=1 LK=1)","18@0|LI@6|AA@30|LK@31|","P1"
"Branch Conditional B-form","bc BO,BI,target_addr (AA=0 LK=0)|bca BO,BI,target_addr (AA=1 LK=0)|bcl BO,BI,target_addr (AA=0 LK=1)|bcla BO,BI,target_addr (AA=1 LK=1)","16@0|BO@6|BI@11|BD@16|AA@30|LK@31|","P1"
"Branch Conditional to Count Register XL-form","bcctr BO,BI,BH (LK=0)|bcctrl BO,BI,BH (LK=1)","19@0|BO@6|BI@11|///@16|BH@19|528@21|LK@31|","P1"
"Branch Conditional to Link Register XL-form","bclr BO,BI,BH (LK=0)|bclrl BO,BI,BH (LK=1)","19@0|BO@6|BI@11|///@16|BH@19|16@21|LK@31|","P1"
"Compare X-form","cmp BF,L,RA,RB|cmpw BF,RA,RB (L=0)|cmpd BF,RA,RB (L=1)","31@0|BF@6|/@9|L@10|RA@11|RB@16|0@21|/@31|","P1"
"Compare Immediate D-form","cmpi BF,L,RA,SI|cmpwi BF,RA,SI (L=0)|cmpdi BF,RA,SI (L=1)","11@0|BF@6|/@9|L@10|RA@11|SI@16|","P1"
"Compare Logical X-form","cmpl BF,L,RA,RB|cmplw BF,RA,RB (L=0)|cmpld BF,RA,RB (L=1)","31@0|BF@6|/@9|L@10|RA@11|RB@16|32@21|/@31|","P1"
"Compare Logical Immediate D-form","cmpli BF,L,RA,UI|cmplwi BF,RA,UI (L=0)|cmpldi BF,RA,UI (L=1)","10@0|BF@6|/@9|L@10|RA@11|UI@16|","P1"
"Count Leading Zeros Word X-form","cntlzw RA,RS (Rc=0)|cntlzw. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|26@21|Rc@31|","P1"
"Condition Register AND XL-form","crand BT,BA,BB","19@0|BT@6|BA@11|BB@16|257@21|/@31|","P1"
"Condition Register AND with Complement XL-form","crandc BT,BA,BB","19@0|BT@6|BA@11|BB@16|129@21|/@31|","P1"
"Condition Register Equivalent XL-form","creqv BT,BA,BB","19@0|BT@6|BA@11|BB@16|289@21|/@31|","P1"
"Condition Register NAND XL-form","crnand BT,BA,BB","19@0|BT@6|BA@11|BB@16|225@21|/@31|","P1"
"Condition Register NOR XL-form","crnor BT,BA,BB","19@0|BT@6|BA@11|BB@16|33@21|/@31|","P1"
"Condition Register OR XL-form","cror BT,BA,BB","19@0|BT@6|BA@11|BB@16|449@21|/@31|","P1"
"Condition Register OR with Complement XL-form","crorc BT,BA,BB","19@0|BT@6|BA@11|BB@16|417@21|/@31|","P1"
"Condition Register XOR XL-form","crxor BT,BA,BB","19@0|BT@6|BA@11|BB@16|193@21|/@31|","P1"
"Data Cache Block set to Zero X-form","dcbz RA,RB","31@0|///@6|RA@11|RB@16|1014@21|/@31|","P1"
"Equivalent X-form","eqv RA,RS,RB (Rc=0)|eqv. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|284@21|Rc@31|","P1"
"Extend Sign Halfword X-form","extsh RA,RS (Rc=0)|extsh. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|922@21|Rc@31|","P1"
"Floating Absolute Value X-form","fabs FRT,FRB (Rc=0)|fabs. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|264@21|Rc@31|","P1"
"Floating Add A-form","fadd FRT,FRA,FRB (Rc=0)|fadd. FRT,FRA,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|///@21|21@26|Rc@31|","P1"
"Floating Compare Ordered X-form","fcmpo BF,FRA,FRB","63@0|BF@6|//@9|FRA@11|FRB@16|32@21|/@31|","P1"
"Floating Compare Unordered X-form","fcmpu BF,FRA,FRB","63@0|BF@6|//@9|FRA@11|FRB@16|0@21|/@31|","P1"
"Floating Divide A-form","fdiv FRT,FRA,FRB (Rc=0)|fdiv. FRT,FRA,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|///@21|18@26|Rc@31|","P1"
"Floating Multiply-Add A-form","fmadd FRT,FRA,FRC,FRB (Rc=0)|fmadd. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|29@26|Rc@31|","P1"
"Floating Move Register X-form","fmr FRT,FRB (Rc=0)|fmr. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|72@21|Rc@31|","P1"
"Floating Multiply-Subtract A-form","fmsub FRT,FRA,FRC,FRB (Rc=0)|fmsub. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|28@26|Rc@31|","P1"
"Floating Multiply A-form","fmul FRT,FRA,FRC (Rc=0)|fmul. FRT,FRA,FRC (Rc=1)","63@0|FRT@6|FRA@11|///@16|FRC@21|25@26|Rc@31|","P1"
"Floating Negative Absolute Value X-form","fnabs FRT,FRB (Rc=0)|fnabs. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|136@21|Rc@31|","P1"
"Floating Negate X-form","fneg FRT,FRB (Rc=0)|fneg. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|40@21|Rc@31|","P1"
"Floating Negative Multiply-Add A-form","fnmadd FRT,FRA,FRC,FRB (Rc=0)|fnmadd. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|31@26|Rc@31|","P1"
"Floating Negative Multiply-Subtract A-form","fnmsub FRT,FRA,FRC,FRB (Rc=0)|fnmsub. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|30@26|Rc@31|","P1"
"Floating Round to Single-Precision X-form","frsp FRT,FRB (Rc=0)|frsp. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|12@21|Rc@31|","P1"
"Floating Subtract A-form","fsub FRT,FRA,FRB (Rc=0)|fsub. FRT,FRA,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|///@21|20@26|Rc@31|","P1"
"Instruction Synchronize XL-form","isync","19@0|///@6|///@11|///@16|150@21|/@31|","P1"
"Load Byte and Zero D-form","lbz RT,D(RA)","34@0|RT@6|RA@11|D@16|","P1"
"Load Byte and Zero with Update D-form","lbzu RT,D(RA)","35@0|RT@6|RA@11|D@16|","P1"
"Load Byte and Zero with Update Indexed X-form","lbzux RT,RA,RB","31@0|RT@6|RA@11|RB@16|119@21|/@31|","P1"
"Load Byte and Zero Indexed X-form","lbzx RT,RA,RB","31@0|RT@6|RA@11|RB@16|87@21|/@31|","P1"
"Load Floating-Point Double D-form","lfd FRT,D(RA)","50@0|FRT@6|RA@11|D@16|","P1"
"Load Floating-Point Double with Update D-form","lfdu FRT,D(RA)","51@0|FRT@6|RA@11|D@16|","P1"
"Load Floating-Point Double with Update Indexed X-form","lfdux FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|631@21|/@31|","P1"
"Load Floating-Point Double Indexed X-form","lfdx FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|599@21|/@31|","P1"
"Load Floating-Point Single D-form","lfs FRT,D(RA)","48@0|FRT@6|RA@11|D@16|","P1"
"Load Floating-Point Single with Update D-form","lfsu FRT,D(RA)","49@0|FRT@6|RA@11|D@16|","P1"
"Load Floating-Point Single with Update Indexed X-form","lfsux FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|567@21|/@31|","P1"
"Load Floating-Point Single Indexed X-form","lfsx FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|535@21|/@31|","P1"
"Load Halfword Algebraic D-form","lha RT,D(RA)","42@0|RT@6|RA@11|D@16|","P1"
"Load Halfword Algebraic with Update D-form","lhau RT,D(RA)","43@0|RT@6|RA@11|D@16|","P1"
"Load Halfword Algebraic with Update Indexed X-form","lhaux RT,RA,RB","31@0|RT@6|RA@11|RB@16|375@21|/@31|","P1"
"Load Halfword Algebraic Indexed X-form","lhax RT,RA,RB","31@0|RT@6|RA@11|RB@16|343@21|/@31|","P1"
"Load Halfword Byte-Reverse Indexed X-form","lhbrx RT,RA,RB","31@0|RT@6|RA@11|RB@16|790@21|/@31|","P1"
"Load Halfword and Zero D-form","lhz RT,D(RA)","40@0|RT@6|RA@11|D@16|","P1"
"Load Halfword and Zero with Update D-form","lhzu RT,D(RA)","41@0|RT@6|RA@11|D@16|","P1"
"Load Halfword and Zero with Update Indexed X-form","lhzux RT,RA,RB","31@0|RT@6|RA@11|RB@16|311@21|/@31|","P1"
"Load Halfword and Zero Indexed X-form","lhzx RT,RA,RB","31@0|RT@6|RA@11|RB@16|279@21|/@31|","P1"
"Load Multiple Word D-form","lmw RT,D(RA)","46@0|RT@6|RA@11|D@16|","P1"
"Load String Word Immediate X-form","lswi RT,RA,NB","31@0|RT@6|RA@11|NB@16|597@21|/@31|","P1"
"Load String Word Indexed X-form","lswx RT,RA,RB","31@0|RT@6|RA@11|RB@16|533@21|/@31|","P1"
"Load Word Byte-Reverse Indexed X-form","lwbrx RT,RA,RB","31@0|RT@6|RA@11|RB@16|534@21|/@31|","P1"
"Load Word and Zero D-form","lwz RT,D(RA)","32@0|RT@6|RA@11|D@16|","P1"
"Load Word and Zero with Update D-form","lwzu RT,D(RA)","33@0|RT@6|RA@11|D@16|","P1"
"Load Word and Zero with Update Indexed X-form","lwzux RT,RA,RB","31@0|RT@6|RA@11|RB@16|55@21|/@31|","P1"
"Load Word and Zero Indexed X-form","lwzx RT,RA,RB","31@0|RT@6|RA@11|RB@16|23@21|/@31|","P1"
"Move Condition Register Field XL-form","mcrf BF,BFA","19@0|BF@6|//@9|BFA@11|//@14|///@16|0@21|/@31|","P1"
"Move to Condition Register from FPSCR X-form","mcrfs BF,BFA","63@0|BF@6|//@9|BFA@11|//@14|///@16|64@21|/@31|","P1"
"Move From Condition Register XFX-form","mfcr RT","31@0|RT@6|0@11|///@12|/@20|19@21|/@31|","P1"
"Move From FPSCR X-form","mffs FRT (Rc=0)|mffs. FRT (Rc=1)","63@0|FRT@6|0@11|///@16|583@21|Rc@31|","P1"
"Move From MSR X-form","mfmsr RT","31@0|RT@6|///@11|///@16|83@21|/@31|","P1"
"Move From Special Purpose Register XFX-form","mfspr RT,SPR","31@0|RT@6|spr@11|339@21|/@31|","P1"
"Move To Condition Register Fields XFX-form","mtcrf FXM,RS","31@0|RS@6|0@11|FXM@12|/@20|144@21|/@31|","P1"
"Move To FPSCR Bit 0 X-form","mtfsb0 BT (Rc=0)|mtfsb0. BT (Rc=1)","63@0|BT@6|///@11|///@16|70@21|Rc@31|","P1"
"Move To FPSCR Bit 1 X-form","mtfsb1 BT (Rc=0)|mtfsb1. BT (Rc=1)","63@0|BT@6|///@11|///@16|38@21|Rc@31|","P1"
"Move To FPSCR Fields XFL-form","mtfsf FLM,FRB,L,W (Rc=0)|mtfsf. FLM,FRB,L,W (Rc=1)","63@0|L@6|FLM@7|W@15|FRB@16|711@21|Rc@31|","P1"
"Move To FPSCR Field Immediate X-form","mtfsfi BF,U,W (Rc=0)|mtfsfi. BF,U,W (Rc=1)","63@0|BF@6|//@9|///@11|W@15|U@16|/@20|134@21|Rc@31|","P1"
"Move To MSR X-form","mtmsr RS,L","31@0|RS@6|///@11|L@15|///@16|146@21|/@31|","P1"
"Move To Special Purpose Register XFX-form","mtspr SPR,RS","31@0|RS@6|spr@11|467@21|/@31|","P1"
"Multiply Low Immediate D-form","mulli RT,RA,SI","7@0|RT@6|RA@11|SI@16|","P1"
"Multiply Low Word XO-form","mullw RT,RA,RB (OE=0 Rc=0)|mullw. RT,RA,RB (OE=0 Rc=1)|mullwo RT,RA,RB (OE=1 Rc=0)|mullwo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|235@22|Rc@31|","P1"
"NAND X-form","nand RA,RS,RB (Rc=0)|nand. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|476@21|Rc@31|","P1"
"Negate XO-form","neg RT,RA (OE=0 Rc=0)|neg. RT,RA (OE=0 Rc=1)|nego RT,RA (OE=1 Rc=0)|nego. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|104@22|Rc@31|","P1"
"NOR X-form","nor RA,RS,RB (Rc=0)|nor. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|124@21|Rc@31|","P1"
"OR X-form","or RA,RS,RB (Rc=0)|or. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|444@21|Rc@31|","P1"
"OR with Complement X-form","orc RA,RS,RB (Rc=0)|orc. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|412@21|Rc@31|","P1"
"OR Immediate D-form","ori RA,RS,UI|nop (RA=0 RS=0 UI=0)","24@0|RS@6|RA@11|UI@16|","P1"
"OR Immediate Shifted D-form","oris RA,RS,UI","25@0|RS@6|RA@11|UI@16|","P1"
"Rotate Left Word Immediate then Mask Insert M-form","rlwimi RA,RS,SH,MB,ME (Rc=0)|rlwimi. RA,RS,SH,MB,ME (Rc=1)","20@0|RS@6|RA@11|SH@16|MB@21|ME@26|Rc@31|","P1"
"Rotate Left Word Immediate then AND with Mask M-form","rlwinm RA,RS,SH,MB,ME (Rc=0)|rlwinm. RA,RS,SH,MB,ME (Rc=1)","21@0|RS@6|RA@11|SH@16|MB@21|ME@26|Rc@31|","P1"
"Rotate Left Word then AND with Mask M-form","rlwnm RA,RS,RB,MB,ME (Rc=0)|rlwnm. RA,RS,RB,MB,ME (Rc=1)","23@0|RS@6|RA@11|RB@16|MB@21|ME@26|Rc@31|","P1"
"Shift Left Word X-form","slw RA,RS,RB (Rc=0)|slw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|24@21|Rc@31|","P1"
"Shift Right Algebraic Word X-form","sraw RA,RS,RB (Rc=0)|sraw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|792@21|Rc@31|","P1"
"Shift Right Algebraic Word Immediate X-form","srawi RA,RS,SH (Rc=0)|srawi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|SH@16|824@21|Rc@31|","P1"
"Shift Right Word X-form","srw RA,RS,RB (Rc=0)|srw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|536@21|Rc@31|","P1"
"Store Byte D-form","stb RS,D(RA)","38@0|RS@6|RA@11|D@16|","P1"
"Store Byte with Update D-form","stbu RS,D(RA)","39@0|RS@6|RA@11|D@16|","P1"
"Store Byte with Update Indexed X-form","stbux RS,RA,RB","31@0|RS@6|RA@11|RB@16|247@21|/@31|","P1"
"Store Byte Indexed X-form","stbx RS,RA,RB","31@0|RS@6|RA@11|RB@16|215@21|/@31|","P1"
"Store Floating-Point Double D-form","stfd FRS,D(RA)","54@0|FRS@6|RA@11|D@16|","P1"
"Store Floating-Point Double with Update D-form","stfdu FRS,D(RA)","55@0|FRS@6|RA@11|D@16|","P1"
"Store Floating-Point Double with Update Indexed X-form","stfdux FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|759@21|/@31|","P1"
"Store Floating-Point Double Indexed X-form","stfdx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|727@21|/@31|","P1"
"Store Floating-Point Single D-form","stfs FRS,D(RA)","52@0|FRS@6|RA@11|D@16|","P1"
"Store Floating-Point Single with Update D-form","stfsu FRS,D(RA)","53@0|FRS@6|RA@11|D@16|","P1"
"Store Floating-Point Single with Update Indexed X-form","stfsux FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|695@21|/@31|","P1"
"Store Floating-Point Single Indexed X-form","stfsx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|663@21|/@31|","P1"
"Store Halfword D-form","sth RS,D(RA)","44@0|RS@6|RA@11|D@16|","P1"
"Store Halfword Byte-Reverse Indexed X-form","sthbrx RS,RA,RB","31@0|RS@6|RA@11|RB@16|918@21|/@31|","P1"
"Store Halfword with Update D-form","sthu RS,D(RA)","45@0|RS@6|RA@11|D@16|","P1"
"Store Halfword with Update Indexed X-form","sthux RS,RA,RB","31@0|RS@6|RA@11|RB@16|439@21|/@31|","P1"
"Store Halfword Indexed X-form","sthx RS,RA,RB","31@0|RS@6|RA@11|RB@16|407@21|/@31|","P1"
"Store Multiple Word D-form","stmw RS,D(RA)","47@0|RS@6|RA@11|D@16|","P1"
"Store String Word Immediate X-form","stswi RS,RA,NB","31@0|RS@6|RA@11|NB@16|725@21|/@31|","P1"
"Store String Word Indexed X-form","stswx RS,RA,RB","31@0|RS@6|RA@11|RB@16|661@21|/@31|","P1"
"Store Word D-form","stw RS,D(RA)","36@0|RS@6|RA@11|D@16|","P1"
"Store Word Byte-Reverse Indexed X-form","stwbrx RS,RA,RB","31@0|RS@6|RA@11|RB@16|662@21|/@31|","P1"
"Store Word with Update D-form","stwu RS,D(RA)","37@0|RS@6|RA@11|D@16|","P1"
"Store Word with Update Indexed X-form","stwux RS,RA,RB","31@0|RS@6|RA@11|RB@16|183@21|/@31|","P1"
"Store Word Indexed X-form","stwx RS,RA,RB","31@0|RS@6|RA@11|RB@16|151@21|/@31|","P1"
"Subtract From Carrying XO-form","subfc RT,RA,RB (OE=0 Rc=0)|subfc. RT,RA,RB (OE=0 Rc=1)|subfco RT,RA,RB (OE=1 Rc=0)|subfco. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|8@22|Rc@31|","P1"
"Subtract From Extended XO-form","subfe RT,RA,RB (OE=0 Rc=0)|subfe. RT,RA,RB (OE=0 Rc=1)|subfeo RT,RA,RB (OE=1 Rc=0)|subfeo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|136@22|Rc@31|","P1"
"Subtract From Immediate Carrying D-form","subfic RT,RA,SI","8@0|RT@6|RA@11|SI@16|","P1"
"Subtract From Minus One Extended XO-form","subfme RT,RA (OE=0 Rc=0)|subfme. RT,RA (OE=0 Rc=1)|subfmeo RT,RA (OE=1 Rc=0)|subfmeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|232@22|Rc@31|","P1"
"Subtract From Zero Extended XO-form","subfze RT,RA (OE=0 Rc=0)|subfze. RT,RA (OE=0 Rc=1)|subfzeo RT,RA (OE=1 Rc=0)|subfzeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|200@22|Rc@31|","P1"
"Synchronize X-form","sync L,SC","31@0|//@6|L@8|///@11|SC@14|///@16|598@21|/@31|","P1"
"TLB Invalidate Entry X-form","tlbie RB,RS,RIC,PRS,R","31@0|RS@6|/@11|RIC@12|PRS@14|R@15|RB@16|306@21|/@31|","P1"
"Trap Word X-form","tw TO,RA,RB","31@0|TO@6|RA@11|RB@16|4@21|/@31|","P1"
"Trap Word Immediate D-form","twi TO,RA,SI","3@0|TO@6|RA@11|SI@16|","P1"
"XOR X-form","xor RA,RS,RB (Rc=0)|xor. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|316@21|Rc@31|","P1"
"XOR Immediate D-form","xori RA,RS,UI","26@0|RS@6|RA@11|UI@16|","P1"
"XOR Immediate Shifted D-form","xoris RA,RS,UI","27@0|RS@6|RA@11|UI@16|","P1"