commit 21375ab36ac3450884ce73b7b4bc00cb75416f7f
author Russ Cox <rsc@golang.org> Wed Oct 12 12:35:10 2016 -0400
committer Russ Cox <rsc@golang.org> Wed Oct 12 18:28:02 2016 +0000
tree 32654de132591c70a7a349b4d61af1e0dfc9f520
parent bebde3aee3712c6e3a456f71fda164affc5be532

ppc64: add, from github.com/minux/power64

This is a direct copy of github.com/minux/power64,
which in turn was forked from rsc.io/power64,
which was using Mercurial and is gone.
The code in those places was reviewed via code review
and is by Minux and me under the usual Go CLA.

I've done a global search and replace of power64 to ppc64
and checked that everything still builds. Any further fixes
will be in followup CLs.

(The arch subrepo did not exist when this code was written.)

Change-Id: I80ea16ca689c9fc51a7501c3492099f19aa30873
Reviewed-on: https://go-review.googlesource.com/30932
Run-TryBot: Russ Cox <rsc@golang.org>
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>

ppc64/pp64.csv

diff --git a/ppc64/pp64.csv b/ppc64/pp64.csv
new file mode 100644
index 0000000..bd7bdf6
--- /dev/null
+++ b/ppc64/pp64.csv
@@ -0,0 +1,1200 @@
+# power64 instruction description version 0.01. http://rsc.io/power64/
+#
+# This file contains a block of comment lines, each beginning with #,
+# followed by entries in CSV format. All the # comments are at the top
+# of the file, so a reader can skip past the comments and hand the
+# rest of the file to a standard CSV reader.
+#
+# Each line in the CSV section contains 4 fields:
+#
+#	instruction mnemonic encoding tags
+#
+# The instruction is the headline from the manual.
+# The mnemonic is the instruction mnemonics, separated by | characters.
+# The encoding is the encoding, a sequence of name@startbit| describing each bit field in turn.
+# The tags are additional metadata, currently always empty.
+#
+"Count Leading Zeros Word X-form","cntlzw RA, RS (Rc=0)|cntlzw. RA, RS (Rc=1)","31@0|RS@6|RA@11|///@16|26@21|Rc@31|",""
+"Branch I-form","b target_addr (AA=0 LK=0)|ba target_addr (AA=1 LK=0)|bl target_addr (AA=0 LK=1)|bla target_addr (AA=1 LK=1)","18@0|LI@6|AA@30|LK@31|",""
+"Branch Conditional B-form","bc BO,BI,target_addr (AA=0 LK=0)|bca BO,BI,target_addr (AA=1 LK=0)|bcl BO,BI,target_addr (AA=0 LK=1)|bcla BO,BI,target_addr (AA=1 LK=1)","16@0|BO@6|BI@11|BD@16|AA@30|LK@31|",""
+"Branch Conditional to Link Register XL-form","bclr BO,BI,BH (LK=0)|bclrl BO,BI,BH (LK=1)","19@0|BO@6|BI@11|///@16|BH@19|16@21|LK@31|",""
+"Branch Conditional to Count Register XL-form","bcctr BO,BI,BH (LK=0)|bcctrl BO,BI,BH (LK=1)","19@0|BO@6|BI@11|///@16|BH@19|528@21|LK@31|",""
+"Branch Conditional to Branch Target Address Register XL-form","bctar BO,BI,BH (LK=0)|bctarl BO,BI,BH (LK=1)","19@0|BO@6|BI@11|///@16|BH@19|560@21|LK@31|",""
+"Condition Register AND XL-form","crand BT,BA,BB","19@0|BT@6|BA@11|BB@16|257@21|/@31|",""
+"Condition Register OR XL-form","cror BT,BA,BB","19@0|BT@6|BA@11|BB@16|449@21|/@31|",""
+"Condition Register NAND XL-form","crnand BT,BA,BB","19@0|BT@6|BA@11|BB@16|225@21|/@31|",""
+"Condition Register XOR XL-form","crxor BT,BA,BB","19@0|BT@6|BA@11|BB@16|193@21|/@31|",""
+"Condition Register NOR XL-form","crnor BT,BA,BB","19@0|BT@6|BA@11|BB@16|33@21|/@31|",""
+"Condition Register AND with Complement XL-form","crandc BT,BA,BB","19@0|BT@6|BA@11|BB@16|129@21|/@31|",""
+"Move Condition Register Field XL-form","mcrf BF,BFA","19@0|BF@6|//@9|BFA@11|//@14|///@16|0@21|/@31|",""
+"Condition Register Equivalent XL-form","creqv BT,BA,BB","19@0|BT@6|BA@11|BB@16|289@21|/@31|",""
+"Condition Register OR with Complement XL-form","crorc BT,BA,BB","19@0|BT@6|BA@11|BB@16|417@21|/@31|",""
+"System Call SC-form","sc LEV","17@0|///@6|///@11|//@16|LEV@20|//@27|1@30|/@31|",""
+"Clear BHRB X-form","clrbhrb","31@0|///@6|430@21|/@31|",""
+"Move From Branch History Rolling Buffer XFX-form","mfbhrbe RT,BHRBE","31@0|RT@6|bhrbe@11|302@21|/@31|",""
+"Load Byte and Zero D-form","lbz RT,D(RA)","34@0|RT@6|RA@11|D@16|",""
+"Load Byte and Zero with Update D-form","lbzu RT,D(RA)","35@0|RT@6|RA@11|D@16|",""
+"Load Byte and Zero Indexed X-form","lbzx RT,RA,RB","31@0|RT@6|RA@11|RB@16|87@21|/@31|",""
+"Load Byte and Zero with Update Indexed X-form","lbzux RT,RA,RB","31@0|RT@6|RA@11|RB@16|119@21|/@31|",""
+"Load Halfword and Zero D-form","lhz RT,D(RA)","40@0|RT@6|RA@11|D@16|",""
+"Load Halfword and Zero with Update D-form","lhzu RT,D(RA)","41@0|RT@6|RA@11|D@16|",""
+"Load Halfword and Zero Indexed X-form","lhzx RT,RA,RB","31@0|RT@6|RA@11|RB@16|279@21|/@31|",""
+"Load Halfword and Zero with Update Indexed X-form","lhzux RT,RA,RB","31@0|RT@6|RA@11|RB@16|311@21|/@31|",""
+"Load Halfword Algebraic D-form","lha RT,D(RA)","42@0|RT@6|RA@11|D@16|",""
+"Load Halfword Algebraic with Update D-form","lhau RT,D(RA)","43@0|RT@6|RA@11|D@16|",""
+"Load Halfword Algebraic Indexed X-form","lhax RT,RA,RB","31@0|RT@6|RA@11|RB@16|343@21|/@31|",""
+"Load Halfword Algebraic with Update Indexed X-form","lhaux RT,RA,RB","31@0|RT@6|RA@11|RB@16|375@21|/@31|",""
+"Load Word and Zero D-form","lwz RT,D(RA)","32@0|RT@6|RA@11|D@16|",""
+"Load Word and Zero with Update D-form","lwzu RT,D(RA)","33@0|RT@6|RA@11|D@16|",""
+"Load Word and Zero Indexed X-form","lwzx RT,RA,RB","31@0|RT@6|RA@11|RB@16|23@21|/@31|",""
+"Load Word and Zero with Update Indexed X-form","lwzux RT,RA,RB","31@0|RT@6|RA@11|RB@16|55@21|/@31|",""
+"Load Word Algebraic DS-form","lwa RT,DS(RA)","58@0|RT@6|RA@11|DS@16|2@30|",""
+"Load Word Algebraic Indexed X-form","lwax RT,RA,RB","31@0|RT@6|RA@11|RB@16|341@21|/@31|",""
+"Load Word Algebraic with Update Indexed X-form","lwaux RT,RA,RB","31@0|RT@6|RA@11|RB@16|373@21|/@31|",""
+"Load Doubleword DS-form","ld RT,DS(RA)","58@0|RT@6|RA@11|DS@16|0@30|",""
+"Load Doubleword with Update DS-form","ldu RT,DS(RA)","58@0|RT@6|RA@11|DS@16|1@30|",""
+"Load Doubleword Indexed X-form","ldx RT,RA,RB","31@0|RT@6|RA@11|RB@16|21@21|/@31|",""
+"Load Doubleword with Update Indexed X-form","ldux RT,RA,RB","31@0|RT@6|RA@11|RB@16|53@21|/@31|",""
+"Store Byte D-form","stb RS,D(RA)","38@0|RS@6|RA@11|D@16|",""
+"Store Byte with Update D-form","stbu RS,D(RA)","39@0|RS@6|RA@11|D@16|",""
+"Store Byte Indexed X-form","stbx RS,RA,RB","31@0|RS@6|RA@11|RB@16|215@21|/@31|",""
+"Store Byte with Update Indexed X-form","stbux RS,RA,RB","31@0|RS@6|RA@11|RB@16|247@21|/@31|",""
+"Store Halfword D-form","sth RS,D(RA)","44@0|RS@6|RA@11|D@16|",""
+"Store Halfword with Update D-form","sthu RS,D(RA)","45@0|RS@6|RA@11|D@16|",""
+"Store Halfword Indexed X-form","sthx RS,RA,RB","31@0|RS@6|RA@11|RB@16|407@21|/@31|",""
+"Store Halfword with Update Indexed X-form","sthux RS,RA,RB","31@0|RS@6|RA@11|RB@16|439@21|/@31|",""
+"Store Word D-form","stw RS,D(RA)","36@0|RS@6|RA@11|D@16|",""
+"Store Word with Update D-form","stwu RS,D(RA)","37@0|RS@6|RA@11|D@16|",""
+"Store Word Indexed X-form","stwx RS,RA,RB","31@0|RS@6|RA@11|RB@16|151@21|/@31|",""
+"Store Word with Update Indexed X-form","stwux RS,RA,RB","31@0|RS@6|RA@11|RB@16|183@21|/@31|",""
+"Store Doubleword DS-form","std RS,DS(RA)","62@0|RS@6|RA@11|DS@16|0@30|",""
+"Store Doubleword with Update DS-form","stdu RS,DS(RA)","62@0|RS@6|RA@11|DS@16|1@30|",""
+"Store Doubleword Indexed X-form","stdx RS,RA,RB","31@0|RS@6|RA@11|RB@16|149@21|/@31|",""
+"Store Doubleword with Update Indexed X-form","stdux RS,RA,RB","31@0|RS@6|RA@11|RB@16|181@21|/@31|",""
+"Load Quadword DQ-form","lq RTp,DQ(RA)","56@0|RTp@6|RA@11|DQ@16|///@28|",""
+"Store Quadword DS-form","stq RSp,DS(RA)","62@0|RSp@6|RA@11|DS@16|2@30|",""
+"Load Halfword Byte-Reverse Indexed X-form","lhbrx RT,RA,RB","31@0|RT@6|RA@11|RB@16|790@21|/@31|",""
+"Load Word Byte-Reverse Indexed X-form","lwbrx RT,RA,RB","31@0|RT@6|RA@11|RB@16|534@21|/@31|",""
+"Store Halfword Byte-Reverse Indexed X-form","sthbrx RS,RA,RB","31@0|RS@6|RA@11|RB@16|918@21|/@31|",""
+"Store Word Byte-Reverse Indexed X-form","stwbrx RS,RA,RB","31@0|RS@6|RA@11|RB@16|662@21|/@31|",""
+"Load Doubleword Byte-Reverse Indexed X-form","ldbrx RT,RA,RB","31@0|RT@6|RA@11|RB@16|532@21|/@31|",""
+"Store Doubleword Byte-Reverse Indexed X-form","stdbrx RS,RA,RB","31@0|RS@6|RA@11|RB@16|660@21|/@31|",""
+"Load Multiple Word D-form","lmw RT,D(RA)","46@0|RT@6|RA@11|D@16|",""
+"Store Multiple Word D-form","stmw RS,D(RA)","47@0|RS@6|RA@11|D@16|",""
+"Load String Word Immediate X-form","lswi RT,RA,NB","31@0|RT@6|RA@11|NB@16|597@21|/@31|",""
+"Load String Word Indexed X-form","lswx RT,RA,RB","31@0|RT@6|RA@11|RB@16|533@21|/@31|",""
+"Store String Word Immediate X-form","stswi RS,RA,NB","31@0|RS@6|RA@11|NB@16|725@21|/@31|",""
+"Store String Word Indexed X-form","stswx RS,RA,RB","31@0|RS@6|RA@11|RB@16|661@21|/@31|",""
+"Add Immediate D-form","li RT,SI (RA=0)|addi RT,RA,SI","14@0|RT@6|RA@11|SI@16|",""
+"Add Immediate Shifted D-form","lis RT, SI (RA=0)|addis RT,RA,SI","15@0|RT@6|RA@11|SI@16|",""
+"Add XO-form","add RT,RA,RB (OE=0 Rc=0)|add. RT,RA,RB (OE=0 Rc=1)|addo RT,RA,RB (OE=1 Rc=0)|addo. RT,RA,RB (OE=1Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|266@22|Rc@31|",""
+"Add Immediate Carrying D-form","addic RT,RA,SI","12@0|RT@6|RA@11|SI@16|",""
+"Subtract From XO-form","subf RT,RA,RB (OE=0 Rc=0)|subf. RT,RA,RB (OE=0 Rc=1)|subfo RT,RA,RB (OE=1 Rc=0)|subfo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|40@22|Rc@31|",""
+"Add Immediate Carrying and Record D-form","addic. RT,RA,SI","13@0|RT@6|RA@11|SI@16|",""
+"Subtract From Immediate Carrying D-form","subfic RT,RA,SI","8@0|RT@6|RA@11|SI@16|",""
+"Add Carrying XO-form","addc RT,RA,RB (OE=0 Rc=0)|addc. RT,RA,RB (OE=0 Rc=1)|addco RT,RA,RB (OE=1 Rc=0)|addco. RT,RA,RB (OE=1Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|10@22|Rc@31|",""
+"Subtract From Carrying XO-form","subfc RT,RA,RB (OE=0 Rc=0)|subfc. RT,RA,RB (OE=0 Rc=1)|subfco RT,RA,RB (OE=1 Rc=0)|subfco. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|8@22|Rc@31|",""
+"Add Extended XO-form","adde RT,RA,RB (OE=0 Rc=0)|adde. RT,RA,RB (OE=0 Rc=1)|addeo RT,RA,RB (OE=1 Rc=0)|addeo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|138@22|Rc@31|",""
+"Add to Minus One Extended XO-form","addme RT,RA (OE=0 Rc=0)|addme. RT,RA (OE=0 Rc=1)|addmeo RT,RA (OE=1 Rc=0)|addmeo. RT,RA (OE=1Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|234@22|Rc@31|",""
+"Subtract From Extended XO-form","subfe RT,RA,RB (OE=0 Rc=0)|subfe. RT,RA,RB (OE=0 Rc=1)|subfeo RT,RA,RB (OE=1 Rc=0)|subfeo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|136@22|Rc@31|",""
+"Subtract From Minus One Extended XO-form","subfme RT,RA (OE=0 Rc=0)|subfme. RT,RA (OE=0 Rc=1)|subfmeo RT,RA (OE=1 Rc=0)|subfmeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|232@22|Rc@31|",""
+"Add to Zero Extended XO-form","addze RT,RA (OE=0 Rc=0)|addze. RT,RA (OE=0 Rc=1)|addzeo RT,RA (OE=1 Rc=0)|addzeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|202@22|Rc@31|",""
+"Subtract From Zero Extended XO-form","subfze RT,RA (OE=0 Rc=0)|subfze. RT,RA (OE=0 Rc=1)|subfzeo RT,RA (OE=1 Rc=0)|subfzeo. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|200@22|Rc@31|",""
+"Negate XO-form","neg RT,RA (OE=0 Rc=0)|neg. RT,RA (OE=0 Rc=1)|nego RT,RA (OE=1 Rc=0)|nego. RT,RA (OE=1 Rc=1)","31@0|RT@6|RA@11|///@16|OE@21|104@22|Rc@31|",""
+"Multiply Low Immediate D-form","mulli RT,RA,SI","7@0|RT@6|RA@11|SI@16|",""
+"Multiply Low Word XO-form","mullw RT,RA,RB (OE=0 Rc=0)|mullw. RT,RA,RB (OE=0 Rc=1)|mullwo RT,RA,RB (OE=1 Rc=0)|mullwo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|235@22|Rc@31|",""
+"Multiply High Word XO-form","mulhw RT,RA,RB (Rc=0)|mulhw. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|75@22|Rc@31|",""
+"Multiply High Word Unsigned XO-form","mulhwu RT,RA,RB (Rc=0)|mulhwu. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|11@22|Rc@31|",""
+"Divide Word XO-form","divw RT,RA,RB (OE=0 Rc=0)|divw. RT,RA,RB (OE=0 Rc=1)|divwo RT,RA,RB (OE=1 Rc=0)|divwo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|491@22|Rc@31|",""
+"Divide Word Unsigned XO-form","divwu RT,RA,RB (OE=0 Rc=0)|divwu. RT,RA,RB (OE=0 Rc=1)|divwuo RT,RA,RB (OE=1 Rc=0)|divwuo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|459@22|Rc@31|",""
+"Divide Word Extended XO-form","divwe RT,RA,RB (OE=0 Rc=0)|divwe. RT,RA,RB (OE=0 Rc=1)|divweo RT,RA,RB (OE=1 Rc=0)|divweo. RT,RA,RB (OE=1 Rc=1)|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RT@6|RA@11|RB@16|OE@21|427@22|Rc@31|",""
+"Divide Word Extended Unsigned XO-form","divweu RT,RA,RB (OE=0 Rc=0)|divweu. RT,RA,RB (OE=0 Rc=1)|divweuo RT,RA,RB (OE=1 Rc=0)|divweuo. RT,RA,RB (OE=1 Rc=1)|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RT@6|RA@11|RB@16|OE@21|395@22|Rc@31|",""
+"Multiply Low Doubleword XO-form","mulld RT,RA,RB (OE=0 Rc=0)|mulld. RT,RA,RB (OE=0 Rc=1)|mulldo RT,RA,RB (OE=1 Rc=0)|mulldo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|233@22|Rc@31|",""
+"Multiply High Doubleword Unsigned XO-form","mulhdu RT,RA,RB (Rc=0)|mulhdu. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|9@22|Rc@31|",""
+"Multiply High Doubleword XO-form","mulhd RT,RA,RB (Rc=0)|mulhd. RT,RA,RB (Rc=1)","31@0|RT@6|RA@11|RB@16|/@21|73@22|Rc@31|",""
+"Divide Doubleword XO-form","divd RT,RA,RB (OE=0 Rc=0)|divd. RT,RA,RB (OE=0 Rc=1)|divdo RT,RA,RB (OE=1 Rc=0)|divdo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|489@22|Rc@31|",""
+"Divide Doubleword Unsigned XO-form","divdu RT,RA,RB (OE=0 Rc=0)|divdu. RT,RA,RB (OE=0 Rc=1)|divduo RT,RA,RB (OE=1 Rc=0)|divduo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|457@22|Rc@31|",""
+"Divide Doubleword Extended XO-form","divde RT,RA,RB (OE=0 Rc=0)|divde. RT,RA,RB (OE=0 Rc=1)|divdeo RT,RA,RB (OE=1 Rc=0)|divdeo. RT,RA,RB (OE=1 Rc=1)|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RT@6|RA@11|RB@16|OE@21|425@22|Rc@31|",""
+"Divide Doubleword Extended Unsigned XO-form","divdeu RT,RA,RB (OE=0 Rc=0)|divdeu. RT,RA,RB (OE=0 Rc=1)|divdeuo RT,RA,RB (OE=1 Rc=0)|divdeuo. RT,RA,RB (OE=1 Rc=1)|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RT@6|RA@11|RB@16|OE@21|393@22|Rc@31|",""
+"Compare Immediate D-form","cmpwi BF,RA,SI (L=0)|cmpdi BF,RA,SI (L=1)","11@0|BF@6|/@9|L@10|RA@11|SI@16|",""
+"Compare X-form","cmpw BF,RA,RB (L=0)|cmpd BF,RA,RB (L=1)","31@0|BF@6|/@9|L@10|RA@11|RB@16|0@21|/@31|",""
+"Compare Logical Immediate D-form","cmplwi BF,RA,UI (L=0)|cmpldi BF,RA,UI (L=1)","10@0|BF@6|/@9|L@10|RA@11|UI@16|",""
+"Compare Logical X-form","cmplw BF,RA,RB (L=0)|cmpld BF,RA,RB (L=1)","31@0|BF@6|/@9|L@10|RA@11|RB@16|32@21|/@31|",""
+"Trap Word Immediate D-form","twi TO,RA,SI","3@0|TO@6|RA@11|SI@16|",""
+"Trap Word X-form","tw TO,RA,RB","31@0|TO@6|RA@11|RB@16|4@21|/@31|",""
+"Trap Doubleword Immediate D-form","tdi TO,RA,SI","2@0|TO@6|RA@11|SI@16|",""
+"Integer Select A-form","isel RT,RA,RB,BC","31@0|RT@6|RA@11|RB@16|BC@21|15@26|/@31|",""
+"Trap Doubleword X-form","td TO,RA,RB","31@0|TO@6|RA@11|RB@16|68@21|/@31|",""
+"AND Immediate D-form","andi. RA,RS,UI","28@0|RS@6|RA@11|UI@16|",""
+"AND Immediate Shifted D-form","andis. RA,RS,UI","29@0|RS@6|RA@11|UI@16|",""
+"OR Immediate D-form","ori RA,RS,UI","24@0|RS@6|RA@11|UI@16|",""
+"OR Immediate Shifted D-form","oris RA,RS,UI","25@0|RS@6|RA@11|UI@16|",""
+"XOR Immediate D-form","xori RA,RS,UI","26@0|RS@6|RA@11|UI@16|",""
+"XOR Immediate Shifted D-form","xoris RA,RS,UI","27@0|RS@6|RA@11|UI@16|",""
+"AND X-form","and RA,RS,RB (Rc=0)|and. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|28@21|Rc@31|",""
+"XOR X-form","xor RA,RS,RB (Rc=0)|xor. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|316@21|Rc@31|",""
+"NAND X-form","nand RA,RS,RB (Rc=0)|nand. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|476@21|Rc@31|",""
+"OR X-form","or RA,RS,RB (Rc=0)|or. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|444@21|Rc@31|",""
+"NOR X-form","nor RA,RS,RB (Rc=0)|nor. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|124@21|Rc@31|",""
+"AND with Complement X-form","andc RA,RS,RB (Rc=0)|andc. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|60@21|Rc@31|",""
+"Extend Sign Byte X-form","extsb RA,RS (Rc=0)|extsb. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|954@21|Rc@31|",""
+"Equivalent X-form","eqv RA,RS,RB (Rc=0)|eqv. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|284@21|Rc@31|",""
+"OR with Complement X-form","orc RA,RS,RB (Rc=0)|orc. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|412@21|Rc@31|",""
+"Extend Sign Halfword X-form","extsh RA,RS (Rc=0)|extsh. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|922@21|Rc@31|",""
+"Compare Bytes X-form","cmpb RA,RS,RB","31@0|RS@6|RA@11|RB@16|508@21|/@31|",""
+"Population Count Bytes X-form","popcntb RA, RS","31@0|RS@6|RA@11|///@16|122@21|/@31|",""
+"Population Count Words X-form","popcntw RA, RS|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RS@6|RA@11|///@16|378@21|/@31|",""
+"Parity Doubleword X-form","prtyd RA,RS|[Category: 64-bit]","31@0|RS@6|RA@11|///@16|186@21|/@31|",""
+"Parity Word X-form","prtyw RA,RS","31@0|RS@6|RA@11|///@16|154@21|/@31|",""
+"Extend Sign Word X-form","extsw RA,RS (Rc=0)|extsw. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|986@21|Rc@31|",""
+"Count Leading Zeros Doubleword X-form","cntlzd RA,RS (Rc=0)|cntlzd. RA,RS (Rc=1)","31@0|RS@6|RA@11|///@16|58@21|Rc@31|",""
+"Population Count Doubleword X-form","popcntd RA, RS|[Category: Server.64-bit]|[Category: Embedded.64-bit.Phased-In]","31@0|RS@6|RA@11|///@16|506@21|/@31|",""
+"Bit Permute Doubleword X-form","bpermd RA,RS,RB|[Category: Embedded.Phased-in, Server]","31@0|RS@6|RA@11|RB@16|252@21|/@31|",""
+"Rotate Left Word Immediate then AND with Mask M-form","rlwinm RA,RS,SH,MB,ME (Rc=0)|rlwinm. RA,RS,SH,MB,ME (Rc=1)","21@0|RS@6|RA@11|SH@16|MB@21|ME@26|Rc@31|",""
+"Rotate Left Word then AND with Mask M-form","rlwnm RA,RS,RB,MB,ME (Rc=0)|rlwnm. RA,RS,RB,MB,ME (Rc=1)","23@0|RS@6|RA@11|RB@16|MB@21|ME@26|Rc@31|",""
+"Rotate Left Word Immediate then Mask Insert M-form","rlwimi RA,RS,SH,MB,ME (Rc=0)|rlwimi. RA,RS,SH,MB,ME (Rc=1)","20@0|RS@6|RA@11|SH@16|MB@21|ME@26|Rc@31|",""
+"Rotate Left Doubleword Immediate then Clear Left MD-form","rldicl RA,RS,SH,MB (Rc=0)|rldicl. RA,RS,SH,MB (Rc=1)","30@0|RS@6|RA@11|sh@16|mb@21|0@27|sh@30|Rc@31|",""
+"Rotate Left Doubleword Immediate then Clear Right MD-form","rldicr RA,RS,SH,ME (Rc=0)|rldicr. RA,RS,SH,ME (Rc=1)","30@0|RS@6|RA@11|sh@16|me@21|1@27|sh@30|Rc@31|",""
+"Rotate Left Doubleword Immediate then Clear MD-form","rldic RA,RS,SH,MB (Rc=0)|rldic. RA,RS,SH,MB (Rc=1)","30@0|RS@6|RA@11|sh@16|mb@21|2@27|sh@30|Rc@31|",""
+"Rotate Left Doubleword then Clear Left MDS-form","rldcl RA,RS,RB,MB (Rc=0)|rldcl. RA,RS,RB,MB (Rc=1)","30@0|RS@6|RA@11|RB@16|mb@21|8@27|Rc@31|",""
+"Rotate Left Doubleword then Clear Right MDS-form","rldcr RA,RS,RB,ME (Rc=0)|rldcr. RA,RS,RB,ME (Rc=1)","30@0|RS@6|RA@11|RB@16|me@21|9@27|Rc@31|",""
+"Rotate Left Doubleword Immediate then Mask Insert MD-form","rldimi RA,RS,SH,MB (Rc=0)|rldimi. RA,RS,SH,MB (Rc=1)","30@0|RS@6|RA@11|sh@16|mb@21|3@27|sh@30|Rc@31|",""
+"Shift Left Word X-form","slw RA,RS,RB (Rc=0)|slw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|24@21|Rc@31|",""
+"Shift Right Word X-form","srw RA,RS,RB (Rc=0)|srw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|536@21|Rc@31|",""
+"Shift Right Algebraic Word Immediate X-form","srawi RA,RS,SH (Rc=0)|srawi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|SH@16|824@21|Rc@31|",""
+"Shift Right Algebraic Word X-form","sraw RA,RS,RB (Rc=0)|sraw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|792@21|Rc@31|",""
+"Shift Left Doubleword X-form","sld RA,RS,RB (Rc=0)|sld. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|27@21|Rc@31|",""
+"Shift Right Doubleword X-form","srd RA,RS,RB (Rc=0)|srd. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|539@21|Rc@31|",""
+"Shift Right Algebraic Doubleword Immediate XS-form","sradi RA,RS,SH (Rc=0)|sradi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|sh@16|413@21|sh@30|Rc@31|",""
+"Shift Right Algebraic Doubleword X-form","srad RA,RS,RB (Rc=0)|srad. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|794@21|Rc@31|",""
+"Convert Declets To Binary Coded Decimal X-form","cdtbcd RA, RS","31@0|RS@6|RA@11|///@16|282@21|/@31|",""
+"Convert Binary Coded Decimal To Declets X-form","cbcdtd RA, RS","31@0|RS@6|RA@11|///@16|314@21|/@31|",""
+"Add and Generate Sixes XO-form","addg6s RT,RA,RB","31@0|RT@6|RA@11|RB@16|/@21|74@22|/@31|",""
+"Move To Special Purpose Register XFX-form","mtspr SPR,RS","31@0|RS@6|spr@11|467@21|/@31|",""
+"Move From Special Purpose Register XFX-form","mfspr RT,SPR","31@0|RT@6|spr@11|339@21|/@31|",""
+"Move To Condition Register Fields XFX-form","mtcrf FXM,RS","31@0|RS@6|0@11|FXM@12|/@20|144@21|/@31|",""
+"Move From Condition Register XFX-form","mfcr RT","31@0|RT@6|0@11|///@12|19@21|/@31|",""
+"Move To Split Little Endian X-form","mtsle L|[Category: Server]","31@0|///@6|L@10|///@11|///@16|147@21|/@31|",""
+"Move From VSR Doubleword XX1-form","[Category: Vector-Scalar]|mfvsrd RA,XS","31@0|S@6|RA@11|///@16|51@21|SX@31|",""
+"Move From VSR Word and Zero XX1-form","[Category: Vector-Scalar]|mfvsrwz RA,XS ( 0x7C00_00E6 )","31@0|S@6|RA@11|///@16|115@21|SX@31|",""
+"Move To VSR Doubleword XX1-form","[Category: Vector-Scalar]|mtvsrd XT,RA","31@0|T@6|RA@11|///@16|179@21|TX@31|",""
+"Move To VSR Word Algebraic XX1-form","[Category: Vector-Scalar]|mtvsrwa XT,RA","31@0|T@6|RA@11|///@16|211@21|TX@31|",""
+"Move To VSR Word and Zero XX1-form","[Category: Vector-Scalar]|mtvsrwz XT,RA","31@0|T@6|RA@11|///@16|243@21|TX@31|",""
+"Move To One Condition Register Field XFX-form","mtocrf FXM,RS","31@0|RS@6|1@11|FXM@12|/@20|144@21|/@31|",""
+"Move From One Condition Register Field XFX-form","mfocrf RT,FXM","31@0|RT@6|1@11|FXM@12|/@20|19@21|/@31|",""
+"Move to Condition Register from XER X-form","mcrxr BF","31@0|BF@6|//@9|///@11|///@16|512@21|/@31|",""
+"Move To Device Control Register User-mode Indexed X-form","mtdcrux RS,RA|[Category: Embedded.Device Control]","31@0|RS@6|RA@11|///@16|419@21|/@31|",""
+"Move From Device Control Register User-mode Indexed X-form","mfdcrux RT,RA|[Category: Embedded.Device Control]","31@0|RT@6|RA@11|///@16|291@21|/@31|",""
+"Load Floating-Point Single D-form","lfs FRT,D(RA)","48@0|FRT@6|RA@11|D@16|",""
+"Load Floating-Point Single with Update D-form","lfsu FRT,D(RA)","49@0|FRT@6|RA@11|D@16|",""
+"Load Floating-Point Single Indexed X-form","lfsx FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|535@21|/@31|",""
+"Load Floating-Point Single with Update Indexed X-form","lfsux FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|567@21|/@31|",""
+"Load Floating-Point Double D-form","lfd FRT,D(RA)","50@0|FRT@6|RA@11|D@16|",""
+"Load Floating-Point Double with Update D-form","lfdu FRT,D(RA)","51@0|FRT@6|RA@11|D@16|",""
+"Load Floating-Point Double Indexed X-form","lfdx FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|599@21|/@31|",""
+"Load Floating-Point Double with Update Indexed X-form","lfdux FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|631@21|/@31|",""
+"Load Floating-Point as Integer Word Algebraic Indexed X-form","lfiwax FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|855@21|/@31|",""
+"Load Floating-Point as Integer Word and Zero Indexed X-form","lfiwzx FRT,RA,RB|[Category: Floating-Point.Phased-in]","31@0|FRT@6|RA@11|RB@16|887@21|/@31|",""
+"Store Floating-Point Single D-form","stfs FRS,D(RA)","52@0|FRS@6|RA@11|D@16|",""
+"Store Floating-Point Single with Update D-form","stfsu FRS,D(RA)","53@0|FRS@6|RA@11|D@16|",""
+"Store Floating-Point Single Indexed X-form","stfsx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|663@21|/@31|",""
+"Store Floating-Point Single with Update Indexed X-form","stfsux FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|695@21|/@31|",""
+"Store Floating-Point Double D-form","stfd FRS,D(RA)","54@0|FRS@6|RA@11|D@16|",""
+"Store Floating-Point Double with Update D-form","stfdu FRS,D(RA)","55@0|FRS@6|RA@11|D@16|",""
+"Store Floating-Point Double Indexed X-form","stfdx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|727@21|/@31|",""
+"Store Floating-Point Double with Update Indexed X-form","stfdux FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|759@21|/@31|",""
+"Store Floating-Point as Integer Word Indexed X-form","stfiwx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|983@21|/@31|",""
+"Load Floating-Point Double Pair DS-form","lfdp FRTp,DS(RA)","57@0|FRTp@6|RA@11|DS@16|00@30|",""
+"Load Floating-Point Double Pair Indexed X-form","lfdpx FRTp,RA,RB","31@0|FRTp@6|RA@11|RB@16|791@21|/@31|",""
+"Store Floating-Point Double Pair DS-form","stfdp FRSp,DS(RA)","61@0|FRSp@6|RA@11|DS@16|00@30|",""
+"Store Floating-Point Double Pair Indexed X-form","stfdpx FRSp,RA,RB","31@0|FRSp@6|RA@11|RB@16|919@21|/@31|",""
+"Floating Move Register X-form","fmr FRT,FRB (Rc=0)|fmr. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|72@21|Rc@31|",""
+"Floating Absolute Value X-form","fabs FRT,FRB (Rc=0)|fabs. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|264@21|Rc@31|",""
+"Floating Negative Absolute Value X-form","fnabs FRT,FRB (Rc=0)|fnabs. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|136@21|Rc@31|",""
+"Floating Negate X-form","fneg FRT,FRB (Rc=0)|fneg. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|40@21|Rc@31|",""
+"Floating Copy Sign X-form","fcpsgn FRT, FRA, FRB (Rc=0)|fcpsgn. FRT, FRA, FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|8@21|Rc@31|",""
+"Floating Merge Even Word X-form","[Category: Vector-Scalar]|fmrgew FRT,FRA,FRB","63@0|FRT@6|FRA@11|FRB@16|966@21|/@31|",""
+"Floating Merge Odd Word X-form","[Category: Vector-Scalar]|fmrgow FRT,FRA,FRB","63@0|FRT@6|FRA@11|FRB@16|838@21|/@31|",""
+"Floating Add [Single] A-form","fadd FRT,FRA,FRB (Rc=0)|fadd. FRT,FRA,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|///@21|21@26|Rc@31|",""
+"Floating Add [Single] A-form","fadds FRT,FRA,FRB (Rc=0)|fadds. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|///@21|21@26|Rc@31|",""
+"Floating Subtract [Single] A-form","fsub FRT,FRA,FRB (Rc=0)|fsub. FRT,FRA,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|///@21|20@26|Rc@31|",""
+"Floating Subtract [Single] A-form","fsubs FRT,FRA,FRB (Rc=0)|fsubs. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|///@21|20@26|Rc@31|",""
+"Floating Multiply [Single] A-form","fmul FRT,FRA,FRC (Rc=0)|fmul. FRT,FRA,FRC (Rc=1)","63@0|FRT@6|FRA@11|///@16|FRC@21|25@26|Rc@31|",""
+"Floating Multiply [Single] A-form","fmuls FRT,FRA,FRC (Rc=0)|fmuls. FRT,FRA,FRC (Rc=1)","59@0|FRT@6|FRA@11|///@16|FRC@21|25@26|Rc@31|",""
+"Floating Divide [Single] A-form","fdiv FRT,FRA,FRB (Rc=0)|fdiv. FRT,FRA,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|///@21|18@26|Rc@31|",""
+"Floating Divide [Single] A-form","fdivs FRT,FRA,FRB (Rc=0)|fdivs. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|///@21|18@26|Rc@31|",""
+"Floating Square Root [Single] A-form","fsqrt FRT,FRB (Rc=0)|fsqrt. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|///@21|22@26|Rc@31|",""
+"Floating Square Root [Single] A-form","fsqrts FRT,FRB (Rc=0)|fsqrts. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|///@21|22@26|Rc@31|",""
+"Floating Reciprocal Estimate [Single] A-form","fre FRT,FRB (Rc=0)|fre. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|///@21|24@26|Rc@31|",""
+"Floating Reciprocal Estimate [Single] A-form","fres FRT,FRB (Rc=0)|fres. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|///@21|24@26|Rc@31|",""
+"Floating Reciprocal Square Root Estimate [Single] A-form","frsqrte FRT,FRB (Rc=0)|frsqrte. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|///@21|26@26|Rc@31|",""
+"Floating Reciprocal Square Root Estimate [Single] A-form","frsqrtes FRT,FRB (Rc=0)|frsqrtes. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|///@21|26@26|Rc@31|",""
+"Floating Test for software Divide X-form","[Category: Floating Point.Phased-In]|ftdiv BF,FRA,FRB","63@0|BF@6|//@9|FRA@11|FRB@16|128@21|/@31|",""
+"Floating Test for software Square Root X-form","[Category: Floating Point.Phased-In]|ftsqrt BF,FRB","63@0|BF@6|//@9|///@11|FRB@16|160@21|/@31|",""
+"Floating Multiply-Add [Single] A-form","fmadd FRT,FRA,FRC,FRB (Rc=0)|fmadd. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|29@26|Rc@31|",""
+"Floating Multiply-Add [Single] A-form","fmadds FRT,FRA,FRC,FRB (Rc=0)|fmadds. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|29@26|Rc@31|",""
+"Floating Multiply-Subtract [Single] A-form","fmsub FRT,FRA,FRC,FRB (Rc=0)|fmsub. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|28@26|Rc@31|",""
+"Floating Multiply-Subtract [Single] A-form","fmsubs FRT,FRA,FRC,FRB (Rc=0)|fmsubs. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|28@26|Rc@31|",""
+"Floating Negative Multiply-Add [Single] A-form","fnmadd FRT,FRA,FRC,FRB (Rc=0)|fnmadd. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|31@26|Rc@31|",""
+"Floating Negative Multiply-Add [Single] A-form","fnmadds FRT,FRA,FRC,FRB (Rc=0)|fnmadds. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|31@26|Rc@31|",""
+"Floating Negative Multiply-Subtract [Single] A-form","fnmsub FRT,FRA,FRC,FRB (Rc=0)|fnmsub. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|30@26|Rc@31|",""
+"Floating Negative Multiply-Subtract [Single] A-form","fnmsubs FRT,FRA,FRC,FRB (Rc=0)|fnmsubs. FRT,FRA,FRC,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|FRC@21|30@26|Rc@31|",""
+"Floating Round to Single-Precision X-form","frsp FRT,FRB (Rc=0)|frsp. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|12@21|Rc@31|",""
+"Floating Convert To Integer Doubleword X-form","fctid FRT,FRB (Rc=0)|fctid. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|814@21|Rc@31|",""
+"Floating Convert To Integer Doubleword with round toward Zero X-form","fctidz FRT,FRB (Rc=0)|fctidz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|815@21|Rc@31|",""
+"Floating Convert To Integer Doubleword Unsigned X-form","[Category: Floating-Point.Phased-In]|fctidu FRT,FRB (Rc=0)|fctidu. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|942@21|Rc@31|",""
+"Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form","[Category: Floating-Point.Phased-In]|fctiduz FRT,FRB (Rc=0)|fctiduz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|943@21|Rc@31|",""
+"Floating Convert To Integer Word X-form","fctiw FRT,FRB (Rc=0)|fctiw. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|14@21|Rc@31|",""
+"Floating Convert To Integer Word with round toward Zero X-form","fctiwz FRT,FRB (Rc=0)|fctiwz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|15@21|Rc@31|",""
+"Floating Convert To Integer Word Unsigned X-form","[Category: Floating-Point.Phased-In]|fctiwu FRT,FRB (Rc=0)|fctiwu. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|142@21|Rc@31|",""
+"Floating Convert To Integer Word Unsigned with round toward Zero X-form","[Category: Floating-Point.Phased-In]|fctiwuz FRT,FRB (Rc=0)|fctiwuz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|143@21|Rc@31|",""
+"Floating Convert From Integer Doubleword X-form","fcfid FRT,FRB (Rc=0)|fcfid. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|846@21|Rc@31|",""
+"Floating Convert From Integer Doubleword Unsigned X-form","[Category: Floating-Point.Phased-In]|fcfidu FRT,FRB (Rc=0)|fcfidu. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|974@21|Rc@31|",""
+"Floating Convert From Integer Doubleword Single X-form","[Category: Floating-Point.Phased-In]|fcfids FRT,FRB (Rc=0)|fcfids. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|846@21|Rc@31|",""
+"Floating Convert From Integer Doubleword Unsigned Single X-form","[Category: Floating-Point.Phased-In]|fcfidus FRT,FRB (Rc=0)|fcfidus. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|974@21|Rc@31|",""
+"Floating Round to Integer Nearest X-form","frin FRT,FRB (Rc=0)|frin. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|392@21|Rc@31|",""
+"Floating Round to Integer Toward Zero X-form","friz FRT,FRB (Rc=0)|friz. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|424@21|Rc@31|",""
+"Floating Round to Integer Plus X-form","frip FRT,FRB (Rc=0)|frip. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|456@21|Rc@31|",""
+"Floating Round to Integer Minus X-form","frim FRT,FRB (Rc=0)|frim. FRT,FRB (Rc=1)","63@0|FRT@6|///@11|FRB@16|488@21|Rc@31|",""
+"Floating Compare Unordered X-form","fcmpu BF,FRA,FRB","63@0|BF@6|//@9|FRA@11|FRB@16|0@21|/@31|",""
+"Floating Compare Ordered X-form","fcmpo BF,FRA,FRB","63@0|BF@6|//@9|FRA@11|FRB@16|32@21|/@31|",""
+"Floating Select A-form","fsel FRT,FRA,FRC,FRB (Rc=0)|fsel. FRT,FRA,FRC,FRB (Rc=1)","63@0|FRT@6|FRA@11|FRB@16|FRC@21|23@26|Rc@31|",""
+"Move From FPSCR X-form","mffs FRT (Rc=0)|mffs. FRT (Rc=1)","63@0|FRT@6|///@11|///@16|583@21|Rc@31|",""
+"Move to Condition Register from FPSCR X-form","mcrfs BF,BFA","63@0|BF@6|//@9|BFA@11|//@14|///@16|64@21|/@31|",""
+"Move To FPSCR Field Immediate X-form","mtfsfi BF,U,W (Rc=0)|mtfsfi. BF,U,W (Rc=1)","63@0|BF@6|//@9|///@11|W@15|U@16|/@20|134@21|Rc@31|",""
+"Move To FPSCR Fields XFL-form","mtfsf FLM,FRB,L,W (Rc=0)|mtfsf. FLM,FRB,L,W (Rc=1)","63@0|L@6|FLM@7|W@15|FRB@16|711@21|Rc@31|",""
+"Move To FPSCR Bit 0 X-form","mtfsb0 BT (Rc=0)|mtfsb0. BT (Rc=1)","63@0|BT@6|///@11|///@16|70@21|Rc@31|",""
+"Move To FPSCR Bit 1 X-form","mtfsb1 BT (Rc=0)|mtfsb1. BT (Rc=1)","63@0|BT@6|///@11|///@16|38@21|Rc@31|",""
+"Load Vector Element Byte Indexed X-form","lvebx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|7@21|/@31|",""
+"Load Vector Element Halfword Indexed X-form","lvehx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|39@21|/@31|",""
+"Load Vector Element Word Indexed X-form","lvewx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|71@21|/@31|",""
+"Load Vector Indexed X-form","lvx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|103@21|/@31|",""
+"Load Vector Indexed LRU X-form","lvxl VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|359@21|/@31|",""
+"Store Vector Element Byte Indexed X-form","stvebx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|135@21|/@31|",""
+"Store Vector Element Halfword Indexed X-form","stvehx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|167@21|/@31|",""
+"Store Vector Element Word Indexed X-form","stvewx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|199@21|/@31|",""
+"Store Vector Indexed X-form","stvx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|231@21|/@31|",""
+"Store Vector Indexed LRU X-form","stvxl VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|487@21|/@31|",""
+"Load Vector for Shift Left Indexed X-form","lvsl VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|6@21|/@31|",""
+"Load Vector for Shift Right Indexed X-form","lvsr VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|38@21|/@31|",""
+"Vector Pack Pixel VX-form","vpkpx VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|782@21|",""
+"Vector Pack Signed Doubleword Signed Saturate VX-form","vpksdss VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1486@21|",""
+"Vector Pack Signed Doubleword Unsigned Saturate VX-form","vpksdus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1358@21|",""
+"Vector Pack Signed Halfword Signed Saturate VX-form","vpkshss VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|398@21|",""
+"Vector Pack Signed Halfword Unsigned Saturate VX-form","vpkshus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|270@21|",""
+"Vector Pack Signed Word Signed Saturate VX-form","vpkswss VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|462@21|",""
+"Vector Pack Signed Word Unsigned Saturate VX-form","vpkswus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|334@21|",""
+"Vector Pack Unsigned Doubleword Unsigned Modulo VX-form","vpkudum VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1102@21|",""
+"Vector Pack Unsigned Doubleword Unsigned Saturate VX-form","vpkudus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1230@21|",""
+"Vector Pack Unsigned Halfword Unsigned Modulo VX-form","vpkuhum VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|14@21|",""
+"Vector Pack Unsigned Halfword Unsigned Saturate VX-form","vpkuhus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|142@21|",""
+"Vector Pack Unsigned Word Unsigned Modulo VX-form","vpkuwum VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|78@21|",""
+"Vector Pack Unsigned Word Unsigned Saturate VX-form","vpkuwus VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|206@21|",""
+"Vector Unpack High Pixel VX-form","vupkhpx VRT,VRB","4@0|VRT@6|///@11|VRB@16|846@21|",""
+"Vector Unpack Low Pixel VX-form","vupklpx VRT,VRB","4@0|VRT@6|///@11|VRB@16|974@21|",""
+"Vector Unpack High Signed Byte VX-form","vupkhsb VRT,VRB","4@0|VRT@6|///@11|VRB@16|526@21|",""
+"Vector Unpack High Signed Halfword VX-form","vupkhsh VRT,VRB","4@0|VRT@6|///@11|VRB@16|590@21|",""
+"Vector Unpack High Signed Word VX-form","vupkhsw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1614@21|",""
+"Vector Unpack Low Signed Byte VX-form","vupklsb VRT,VRB","4@0|VRT@6|///@11|VRB@16|654@21|",""
+"Vector Unpack Low Signed Halfword VX-form","vupklsh VRT,VRB","4@0|VRT@6|///@11|VRB@16|718@21|",""
+"Vector Unpack Low Signed Word VX-form","vupklsw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1742@21|",""
+"Vector Merge High Byte VX-form","vmrghb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|12@21|",""
+"Vector Merge High Halfword VX-form","vmrghh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|76@21|",""
+"Vector Merge Low Byte VX-form","vmrglb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|268@21|",""
+"Vector Merge Low Halfword VX-form","vmrglh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|332@21|",""
+"Vector Merge High Word VX-form","vmrghw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|140@21|",""
+"Vector Merge Low Word VX-form","vmrglw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|396@21|",""
+"Vector Merge Even Word VX-form","[Category: Vector-Scalar]|vmrgew VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1932@21|",""
+"Vector Merge Odd Word VX-form","[Category: Vector-Scalar]|vmrgow VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1676@21|",""
+"Vector Splat Byte VX-form","vspltb VRT,VRB,UIM","4@0|VRT@6|/@11|UIM@12|VRB@16|524@21|",""
+"Vector Splat Halfword VX-form","vsplth VRT,VRB,UIM","4@0|VRT@6|//@11|UIM@13|VRB@16|588@21|",""
+"Vector Splat Word VX-form","vspltw VRT,VRB,UIM","4@0|VRT@6|///@11|UIM@14|VRB@16|652@21|",""
+"Vector Splat Immediate Signed Byte VX-form","vspltisb VRT,SIM","4@0|VRT@6|SIM@11|///@16|780@21|",""
+"Vector Splat Immediate Signed Halfword VX-form","vspltish VRT,SIM","4@0|VRT@6|SIM@11|///@16|844@21|",""
+"Vector Splat Immediate Signed Word VX-form","vspltisw VRT,SIM","4@0|VRT@6|SIM@11|///@16|908@21|",""
+"Vector Permute VA-form","vperm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|43@26|",""
+"Vector Select VA-form","vsel VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|42@26|",""
+"Vector Shift Left VX-form","vsl VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|452@21|",""
+"Vector Shift Left Double by Octet Immediate VA-form","vsldoi VRT,VRA,VRB,SHB","4@0|VRT@6|VRA@11|VRB@16|/@21|SHB@22|44@26|",""
+"Vector Shift Left by Octet VX-form","vslo VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1036@21|",""
+"Vector Shift Right VX-form","vsr VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|708@21|",""
+"Vector Shift Right by Octet VX-form","vsro VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1100@21|",""
+"Vector Add and Write Carry-Out Unsigned Word VX-form","vaddcuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|384@21|",""
+"Vector Add Signed Byte Saturate VX-form","vaddsbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|768@21|",""
+"Vector Add Signed Halfword Saturate VX-form","vaddshs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|832@21|",""
+"Vector Add Signed Word Saturate VX-form","vaddsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|896@21|",""
+"Vector Add Unsigned Byte Modulo VX-form","vaddubm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|0@21|",""
+"Vector Add Unsigned Doubleword Modulo VX-form","vaddudm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|192@21|",""
+"Vector Add Unsigned Halfword Modulo VX-form","vadduhm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|64@21|",""
+"Vector Add Unsigned Word Modulo VX-form","vadduwm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|128@21|",""
+"Vector Add Unsigned Byte Saturate VX-form","vaddubs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|512@21|",""
+"Vector Add Unsigned Halfword Saturate VX-form","vadduhs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|576@21|",""
+"Vector Add Unsigned Word Saturate VX-form","vadduws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|640@21|",""
+"Vector Add Unsigned Quadword Modulo VX-form","vadduqm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|256@21|",""
+"Vector Add Extended Unsigned Quadword Modulo VA-form","vaddeuqm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|60@26|",""
+"Vector Add & write Carry Unsigned Quadword VX-form","vaddcuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|320@21|",""
+"Vector Add Extended & write Carry Unsigned Quadword VA-form","vaddecuq VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|61@26|",""
+"Vector Subtract and Write Carry-Out Unsigned Word VX-form","vsubcuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1408@21|",""
+"Vector Subtract Signed Byte Saturate VX-form","vsubsbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1792@21|",""
+"Vector Subtract Signed Halfword Saturate VX-form","vsubshs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1856@21|",""
+"Vector Subtract Signed Word Saturate VX-form","vsubsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1920@21|",""
+"Vector Subtract Unsigned Byte Modulo VX-form","vsububm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1024@21|",""
+"Vector Subtract Unsigned Doubleword Modulo VX-form","vsubudm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1216@21|",""
+"Vector Subtract Unsigned Halfword Modulo VX-form","vsubuhm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1088@21|",""
+"Vector Subtract Unsigned Word Modulo VX-form","vsubuwm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1152@21|",""
+"Vector Subtract Unsigned Byte Saturate VX-form","vsububs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1536@21|",""
+"Vector Subtract Unsigned Halfword Saturate VX-form","vsubuhs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1600@21|",""
+"Vector Subtract Unsigned Word Saturate VX-form","vsubuws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1664@21|",""
+"Vector Subtract Unsigned Quadword Modulo VX-form","vsubuqm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1280@21|",""
+"Vector Subtract Extended Unsigned Quadword Modulo VA-form","vsubeuqm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|62@26|",""
+"Vector Subtract & write Carry Unsigned Quadword VX-form","vsubcuq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1344@21|",""
+"Vector Subtract Extended & write Carry Unsigned Quadword VA-form","vsubecuq VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|63@26|",""
+"Vector Multiply Even Signed Byte VX-form","vmulesb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|776@21|",""
+"Vector Multiply Even Unsigned Byte VX-form","vmuleub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|520@21|",""
+"Vector Multiply Odd Signed Byte VX-form","vmulosb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|264@21|",""
+"Vector Multiply Odd Unsigned Byte VX-form","vmuloub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|8@21|",""
+"Vector Multiply Even Signed Halfword VX-form","vmulesh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|840@21|",""
+"Vector Multiply Even Unsigned Halfword VX-form","vmuleuh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|584@21|",""
+"Vector Multiply Odd Signed Halfword VX-form","vmulosh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|328@21|",""
+"Vector Multiply Odd Unsigned Halfword VX-form","vmulouh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|72@21|",""
+"Vector Multiply Even Signed Word VX-form","vmulesw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|904@21|",""
+"Vector Multiply Even Unsigned Word VX-form","vmuleuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|648@21|",""
+"Vector Multiply Odd Signed Word VX-form","vmulosw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|392@21|",""
+"Vector Multiply Odd Unsigned Word VX-form","vmulouw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|136@21|",""
+"Vector Multiply Unsigned Word Modulo VX-form","vmuluwm VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|137@21|",""
+"Vector Multiply-High-Add Signed Halfword Saturate VA-form","vmhaddshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|32@26|",""
+"Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form","vmhraddshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|33@26|",""
+"Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form","vmladduhm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|34@26|",""
+"Vector Multiply-Sum Unsigned Byte Modulo VA-form","vmsumubm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|36@26|",""
+"Vector Multiply-Sum Mixed Byte Modulo VA-form","vmsummbm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|37@26|",""
+"Vector Multiply-Sum Signed Halfword Modulo VA-form","vmsumshm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|40@26|",""
+"Vector Multiply-Sum Signed Halfword Saturate VA-form","vmsumshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|41@26|",""
+"Vector Multiply-Sum Unsigned Halfword Modulo VA-form","vmsumuhm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|38@26|",""
+"Vector Multiply-Sum Unsigned Halfword Saturate VA-form","vmsumuhs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|39@26|",""
+"Vector Sum across Signed Word Saturate VX-form","vsumsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1928@21|",""
+"Vector Sum across Half Signed Word Saturate VX-form","vsum2sws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1672@21|",""
+"Vector Sum across Quarter Signed Byte Saturate VX-form","vsum4sbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1800@21|",""
+"Vector Sum across Quarter Signed Halfword Saturate VX-form","vsum4shs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1608@21|",""
+"Vector Sum across Quarter Unsigned Byte Saturate VX-form","vsum4ubs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1544@21|",""
+"Vector Average Signed Byte VX-form","vavgsb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1282@21|",""
+"Vector Average Signed Halfword VX-form","vavgsh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1346@21|",""
+"Vector Average Signed Word VX-form","vavgsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1410@21|",""
+"Vector Average Unsigned Byte VX-form","vavgub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1026@21|",""
+"Vector Average Unsigned Word VX-form","vavguw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1154@21|",""
+"Vector Average Unsigned Halfword VX-form","vavguh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1090@21|",""
+"Vector Maximum Signed Byte VX-form","vmaxsb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|258@21|",""
+"Vector Maximum Signed Doubleword VX-form","vmaxsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|450@21|",""
+"Vector Maximum Unsigned Byte VX-form","vmaxub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|2@21|",""
+"Vector Maximum Unsigned Doubleword VX-form","vmaxud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|194@21|",""
+"Vector Maximum Signed Halfword VX-form","vmaxsh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|322@21|",""
+"Vector Maximum Signed Word VX-form","vmaxsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|386@21|",""
+"Vector Maximum Unsigned Halfword VX-form","vmaxuh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|66@21|",""
+"Vector Maximum Unsigned Word VX-form","vmaxuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|130@21|",""
+"Vector Minimum Signed Byte VX-form","vminsb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|770@21|",""
+"Vector Minimum Signed Doubleword VX-form","vminsd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|962@21|",""
+"Vector Minimum Unsigned Byte VX-form","vminub VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|514@21|",""
+"Vector Minimum Unsigned Doubleword VX-form","vminud VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|706@21|",""
+"Vector Minimum Signed Halfword VX-form","vminsh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|834@21|",""
+"Vector Minimum Signed Word VX-form","vminsw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|898@21|",""
+"Vector Minimum Unsigned Halfword VX-form","vminuh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|578@21|",""
+"Vector Minimum Unsigned Word VX-form","vminuw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|642@21|",""
+"Vector Compare Equal To Unsigned Byte VC-form","vcmpequb VRT,VRA,VRB (Rc=0)|vcmpequb. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|6@22|",""
+"Vector Compare Equal To Unsigned Halfword VC-form","vcmpequh VRT,VRA,VRB (Rc=0)|vcmpequh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|70@22|",""
+"Vector Compare Equal To Unsigned Word VC-form","vcmpequw VRT,VRA,VRB ( Rc=0 )|vcmpequw. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|134@22|",""
+"Vector Compare Equal To Unsigned Doubleword VX-form","vcmpequd VRT,VRA,VRB ( Rc=0 )|vcmpequd. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|199@22|",""
+"Vector Compare Greater Than Signed Byte VC-form","vcmpgtsb VRT,VRA,VRB ( Rc=0 )|vcmpgtsb. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|774@22|",""
+"Vector Compare Greater Than Signed Doubleword VX-form","vcmpgtsd VRT,VRA,VRB ( Rc=0 )|vcmpgtsd. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|967@22|",""
+"Vector Compare Greater Than Signed Halfword VC-form","vcmpgtsh VRT,VRA,VRB (Rc=0)|vcmpgtsh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|838@22|",""
+"Vector Compare Greater Than Signed Word VC-form","vcmpgtsw VRT,VRA,VRB (Rc=0)|vcmpgtsw. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|902@22|",""
+"Vector Compare Greater Than Unsigned Byte VC-form","vcmpgtub VRT,VRA,VRB (Rc=0)|vcmpgtub. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|518@22|",""
+"Vector Compare Greater Than Unsigned Doubleword VX-form","vcmpgtud VRT,VRA,VRB ( Rc=0 )|vcmpgtud. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|711@22|",""
+"Vector Compare Greater Than Unsigned Halfword VC-form","vcmpgtuh VRT,VRA,VRB (Rc=0)|vcmpgtuh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|582@22|",""
+"Vector Compare Greater Than Unsigned Word VC-form","vcmpgtuw VRT,VRA,VRB (Rc=0)|vcmpgtuw. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|646@22|",""
+"Vector Logical AND VX-form","vand VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1028@21|",""
+"Vector Logical AND with Complement VX-form","vandc VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1092@21|",""
+"Vector Logical Equivalent VX-form","veqv VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1668@21|",""
+"Vector Logical NAND VX-form","vnand VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1412@21|",""
+"Vector Logical OR with Complement VX-form","vorc VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1348@21|",""
+"Vector Logical NOR VX-form","vnor VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1284@21|",""
+"Vector Logical OR VX-form","vor VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1156@21|",""
+"Vector Logical XOR VX-form","vxor VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1220@21|",""
+"Vector Rotate Left Byte VX-form","vrlb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|4@21|",""
+"Vector Rotate Left Halfword VX-form","vrlh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|68@21|",""
+"Vector Rotate Left Word VX-form","vrlw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|132@21|",""
+"Vector Rotate Left Doubleword VX-form","vrld VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|196@21|",""
+"Vector Shift Left Byte VX-form","vslb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|260@21|",""
+"Vector Shift Left Halfword VX-form","vslh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|324@21|",""
+"Vector Shift Left Word VX-form","vslw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|388@21|",""
+"Vector Shift Left Doubleword VX-form","vsld VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1476@21|",""
+"Vector Shift Right Byte VX-form","vsrb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|516@21|",""
+"Vector Shift Right Halfword VX-form","vsrh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|580@21|",""
+"Vector Shift Right Word VX-form","vsrw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|644@21|",""
+"Vector Shift Right Doubleword VX-form","vsrd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1732@21|",""
+"Vector Shift Right Algebraic Byte VX-form","vsrab VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|772@21|",""
+"Vector Shift Right Algebraic Halfword VX-form","vsrah VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|836@21|",""
+"Vector Shift Right Algebraic Word VX-form","vsraw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|900@21|",""
+"Vector Shift Right Algebraic Doubleword VX-form","vsrad VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|964@21|",""
+"Vector Add Single-Precision VX-form","vaddfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|10@21|",""
+"Vector Subtract Single-Precision VX-form","vsubfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|74@21|",""
+"Vector Multiply-Add Single-Precision VA-form","vmaddfp VRT,VRA,VRC,VRB","4@0|VRT@6|VRA@11|VRB@16|VRC@21|46@26|",""
+"Vector Negative Multiply-Subtract Single-Precision VA-form","vnmsubfp VRT,VRA,VRC,VRB","4@0|VRT@6|VRA@11|VRB@16|VRC@21|47@26|",""
+"Vector Maximum Single-Precision VX-form","vmaxfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1034@21|",""
+"Vector Minimum Single-Precision VX-form","vminfp VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1098@21|",""
+"Vector Convert To Signed Fixed-Point Word Saturate VX-form","vctsxs VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|970@21|",""
+"Vector Convert To Unsigned Fixed-Point Word Saturate VX-form","vctuxs VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|906@21|",""
+"Vector Convert From Signed Fixed-Point Word VX-form","vcfsx VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|842@21|",""
+"Vector Convert From Unsigned Fixed-Point Word VX-form","vcfux VRT,VRB,UIM","4@0|VRT@6|UIM@11|VRB@16|778@21|",""
+"Vector Round to Single-Precision Integer toward -Infinity VX-form","vrfim VRT,VRB","4@0|VRT@6|///@11|VRB@16|714@21|",""
+"Vector Round to Single-Precision Integer Nearest VX-form","vrfin VRT,VRB","4@0|VRT@6|///@11|VRB@16|522@21|",""
+"Vector Round to Single-Precision Integer toward +Infinity VX-form","vrfip VRT,VRB","4@0|VRT@6|///@11|VRB@16|650@21|",""
+"Vector Round to Single-Precision Integer toward Zero VX-form","vrfiz VRT,VRB","4@0|VRT@6|///@11|VRB@16|586@21|",""
+"Vector Compare Bounds Single-Precision VC-form","vcmpbfp VRT,VRA,VRB (Rc=0)|vcmpbfp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|966@22|",""
+"Vector Compare Equal To Single-Precision VC-form","vcmpeqfp VRT,VRA,VRB (Rc=0)|vcmpeqfp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|198@22|",""
+"Vector Compare Greater Than or Equal To Single-Precision VC-form","vcmpgefp VRT,VRA,VRB (Rc=0)|vcmpgefp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|454@22|",""
+"Vector Compare Greater Than Single-Precision VC-form","vcmpgtfp VRT,VRA,VRB (Rc=0)|vcmpgtfp. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|710@22|",""
+"Vector 2 Raised to the Exponent Estimate Floating-Point VX-form","vexptefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|394@21|",""
+"Vector Log Base 2 Estimate Floating-Point VX-form","vlogefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|458@21|",""
+"Vector Reciprocal Estimate Single-Precision VX-form","vrefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|266@21|",""
+"Vector Reciprocal Square Root Estimate Single-Precision VX-form","vrsqrtefp VRT,VRB","4@0|VRT@6|///@11|VRB@16|330@21|",""
+"Vector AES Cipher VX-form","[Category:Vector.Crypto]|vcipher VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1288@21|",""
+"Vector AES Cipher Last VX-form","[Category:Vector.Crypto]|vcipherlast VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1289@21|",""
+"Vector AES Inverse Cipher VX-form","[Category:Vector.Crypto]|vncipher VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1352@21|",""
+"Vector AES Inverse Cipher Last VX-form","[Category:Vector.Crypto]|vncipherlast VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1353@21|",""
+"Vector AES SubBytes VX-form","[Category:Vector.Crypto]|vsbox VRT,VRA","4@0|VRT@6|VRA@11|///@16|1480@21|",""
+"Vector SHA-512 Sigma Doubleword VX-form","[Category:Vector.Crypto]|vshasigmad VRT,VRA,ST,SIX","4@0|VRT@6|VRA@11|ST@16|SIX@17|1730@21|",""
+"Vector SHA-256 Sigma Word VX-form","[Category:Vector.Crypto]|vshasigmaw VRT,VRA,ST,SIX","4@0|VRT@6|VRA@11|ST@16|SIX@17|1666@21|",""
+"Vector Polynomial Multiply-Sum Byte VX-form","vpmsumb VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1032@21|",""
+"Vector Polynomial Multiply-Sum Doubleword VX-form","vpmsumd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1224@21|",""
+"Vector Polynomial Multiply-Sum Halfword VX-form","vpmsumh VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1096@21|",""
+"Vector Polynomial Multiply-Sum Word VX-form","vpmsumw VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1160@21|",""
+"Vector Permute and Exclusive-OR VA-form","[Category:Vector.RAID]|vpermxor VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|45@26|",""
+"Vector Gather Bits by Bytes by Doubleword VX-form","vgbbd VRT,VRB","4@0|VRT@6|///@11|VRB@16|1292@21|",""
+"Vector Count Leading Zeros Byte VX-form","vclzb VRT,VRB","4@0|VRT@6|///@11|VRB@16|1794@21|",""
+"Vector Count Leading Zeros Halfword VX-form","vclzh VRT,VRB","4@0|VRT@6|///@11|VRB@16|1858@21|",""
+"Vector Count Leading Zeros Word VX-form","vclzw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1922@21|",""
+"Vector Count Leading Zeros Doubleword","vclzd VRT,VRB","4@0|VRT@6|///@11|VRB@16|1986@21|",""
+"Vector Population Count Byte","vpopcntb VRT,VRB","4@0|VRT@6|///@11|VRB@16|1795@21|",""
+"Vector Population Count Doubleword","vpopcntd VRT,VRB","4@0|VRT@6|///@11|VRB@16|1987@21|",""
+"Vector Population Count Halfword","vpopcnth VRT,VRB","4@0|VRT@6|///@11|VRB@16|1859@21|",""
+"Vector Population Count Word","vpopcntw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1923@21|",""
+"Vector Bit Permute Quadword VX-form","vbpermq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1356@21|",""
+"Decimal Add Modulo VX-form","bcdadd. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|1@23|",""
+"Decimal Subtract Modulo VX-form","bcdsub. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|65@23|",""
+"Move To Vector Status and Control Register VX-form","mtvscr VRB","4@0|///@6|///@11|VRB@16|1604@21|",""
+"Move From Vector Status and Control Register VX-form","mfvscr VRT","4@0|VRT@6|///@11|///@16|1540@21|",""
+"DFP Add [Quad] X-form","dadd FRT,FRA,FRB (Rc=0)|dadd. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|2@21|Rc@31|",""
+"DFP Subtract [Quad] X-form","dsub FRT,FRA,FRB (Rc=0)|dsub. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|514@21|Rc@31|",""
+"DFP Multiply [Quad] X-form","dmul FRT,FRA,FRB (Rc=0)|dmul. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|34@21|Rc@31|",""
+"DFP Divide [Quad] X-form","ddiv FRT,FRA,FRB (Rc=0)|ddiv. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|546@21|Rc@31|",""
+"DFP Compare Unordered [Quad] X-form","dcmpu BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|642@21|/@31|",""
+"DFP Compare Ordered [Quad] X-form","dcmpo BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|130@21|/@31|",""
+"DFP Test Data Class [Quad] Z22-form","dtstdc BF,FRA,DCM","59@0|BF@6|//@9|FRA@11|DCM@16|194@22|/@31|",""
+"DFP Test Data Group [Quad] Z22-form","dtstdg BF,FRA,DGM","59@0|BF@6|//@9|FRA@11|DGM@16|226@22|/@31|",""
+"DFP Test Exponent [Quad] X-form","dtstex BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|162@21|/@31|",""
+"DFP Test Significance [Quad] X-form","dtstsf BF,FRA,FRB","59@0|BF@6|//@9|FRA@11|FRB@16|674@21|/@31|",""
+"DFP Quantize Immediate [Quad] Z23-form","dquai TE,FRT,FRB,RMC (Rc=0)|dquai. TE,FRT,FRB,RMC (Rc=1)","59@0|FRT@6|TE@11|FRB@16|RMC@21|67@23|Rc@31|",""
+"DFP Quantize [Quad] Z23-form","dqua FRT,FRA,FRB,RMC (Rc=0)|dqua. FRT,FRA,FRB,RMC (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|RMC@21|3@23|Rc@31|",""
+"DFP Reround [Quad] Z23-form","drrnd FRT,FRA,FRB,RMC (Rc=0)|drrnd. FRT,FRA,FRB,RMC (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|RMC@21|35@23|Rc@31|",""
+"DFP Round To FP Integer With Inexact [Quad] Z23-form","drintx R,FRT,FRB,RMC (Rc=0)|drintx. R,FRT,FRB,RMC (Rc=1)","59@0|FRT@6|///@11|R@15|FRB@16|RMC@21|99@23|Rc@31|",""
+"DFP Round To FP Integer Without Inexact [Quad] Z23-form","drintn R,FRT,FRB,RMC (Rc=0)|drintn. R,FRT,FRB,RMC (Rc=1)","59@0|FRT@6|///@11|R@15|FRB@16|RMC@21|227@23|Rc@31|",""
+"DFP Convert To DFP Long X-form","dctdp FRT,FRB (Rc=0)|dctdp. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|258@21|Rc@31|",""
+"DFP Convert To DFP Extended X-form","dctqpq FRTp,FRB (Rc=0)|dctqpq. FRTp,FRB (Rc=1)","63@0|FRTp@6|///@11|FRB@16|258@21|Rc@31|",""
+"DFP Round To DFP Short X-form","drsp FRT,FRB (Rc=0)|drsp. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|770@21|Rc@31|",""
+"DFP Round To DFP Long X-form","drdpq FRTp,FRBp (Rc=0)|drdpq. FRTp,FRBp (Rc=1)","63@0|FRTp@6|///@11|FRBp@16|770@21|Rc@31|",""
+"DFP Convert From Fixed X-form","dcffix FRT,FRB (Rc=0)|dcffix. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|802@21|Rc@31|",""
+"DFP Convert From Fixed Quad X-form","dcffixq FRTp,FRB (Rc=0)|dcffixq. FRTp,FRB (Rc=1)","63@0|FRTp@6|///@11|FRB@16|802@21|Rc@31|",""
+"DFP Convert To Fixed [Quad] X-form","dctfix FRT,FRB (Rc=0)|dctfix. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|290@21|Rc@31|",""
+"DFP Decode DPD To BCD [Quad] X-form","ddedpd SP,FRT,FRB (Rc=0)|ddedpd. SP,FRT,FRB (Rc=1)","59@0|FRT@6|SP@11|///@13|FRB@16|322@21|Rc@31|",""
+"DFP Encode BCD To DPD [Quad] X-form","denbcd S,FRT,FRB (Rc=0)|denbcd. S,FRT,FRB (Rc=1)","59@0|FRT@6|S@11|///@12|FRB@16|834@21|Rc@31|",""
+"DFP Extract Biased Exponent [Quad] X-form","dxex FRT,FRB (Rc=0)|dxex. FRT,FRB (Rc=1)","59@0|FRT@6|///@11|FRB@16|354@21|Rc@31|",""
+"DFP Insert Biased Exponent [Quad] X-form","diex FRT,FRA,FRB (Rc=0)|diex. FRT,FRA,FRB (Rc=1)","59@0|FRT@6|FRA@11|FRB@16|866@21|Rc@31|",""
+"DFP Shift Significand Left Immediate [Quad] Z22-form","dscli FRT,FRA,SH (Rc=0)|dscli. FRT,FRA,SH (Rc=1)","59@0|FRT@6|FRA@11|SH@16|66@22|Rc@31|",""
+"DFP Shift Significand Right Immediate [Quad] Z22-form","dscri FRT,FRA,SH (Rc=0)|dscri. FRT,FRA,SH (Rc=1)","59@0|FRT@6|FRA@11|SH@16|98@22|Rc@31|",""
+"Load VSX Scalar Doubleword Indexed XX1-form","lxsdx XT,RA,RB","31@0|T@6|RA@11|RB@16|588@21|TX@31|",""
+"Load VSX Scalar as Integer Word Algebraic Indexed XX1-form","lxsiwax XT,RA,RB","31@0|T@6|RA@11|RB@16|76@21|TX@31|",""
+"Load VSX Scalar as Integer Word and Zero Indexed XX1-form","lxsiwzx XT,RA,RB","31@0|T@6|RA@11|RB@16|12@21|TX@31|",""
+"Load VSX Scalar Single-Precision Indexed XX1-form","lxsspx XT,RA,RB","31@0|T@6|RA@11|RB@16|524@21|TX@31|",""
+"Load VSX Vector Doubleword*2 Indexed XX1-form","lxvd2x XT,RA,RB","31@0|T@6|RA@11|RB@16|844@21|TX@31|",""
+"Load VSX Vector Doubleword & Splat Indexed XX1-form","lxvdsx XT,RA,RB ( 0x7C00_0298 )","31@0|T@6|RA@11|RB@16|332@21|TX@31|",""
+"Load VSX Vector Word*4 Indexed XX1-form","lxvw4x XT,RA,RB","31@0|T@6|RA@11|RB@16|780@21|TX@31|",""
+"Store VSX Scalar Doubleword Indexed XX1-form","stxsdx XS,RA,RB","31@0|S@6|RA@11|RB@16|716@21|SX@31|",""
+"Store VSX Scalar as Integer Word Indexed XX1-form","stxsiwx XS,RA,RB","31@0|S@6|RA@11|RB@16|140@21|SX@31|",""
+"Store VSX Scalar Single-Precision Indexed XX1-form","stxsspx XS,RA,RB","31@0|S@6|RA@11|RB@16|652@21|SX@31|",""
+"Store VSX Vector Doubleword*2 Indexed XX1-form","stxvd2x XS,RA,RB","31@0|S@6|RA@11|RB@16|972@21|SX@31|",""
+"Store VSX Vector Word*4 Indexed XX1-form","stxvw4x XS,RA,RB","31@0|S@6|RA@11|RB@16|908@21|SX@31|",""
+"VSX Scalar Absolute Value Double-Precision XX2-form","xsabsdp XT,XB","60@0|T@6|///@11|B@16|345@21|BX@30|TX@31|",""
+"VSX Scalar Add Double-Precision XX3-form","xsadddp XT,XA,XB","60@0|T@6|A@11|B@16|32@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Add Single-Precision XX3-form","xsaddsp XT,XA,XB","60@0|T@6|A@11|B@16|0@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Compare Ordered Double-Precision XX3-form","xscmpodp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|",""
+"VSX Scalar Compare Unordered Double-Precision XX3-form","xscmpudp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|",""
+"VSX Scalar Copy Sign Double-Precision XX3-form","xscpsgndp XT,XA,XB","60@0|T@6|A@11|B@16|176@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar round Double-Precision to single-precision and Convert to Single-Precision format XX2-form","xscvdpsp XT,XB","60@0|T@6|///@11|B@16|265@21|BX@30|TX@31|",""
+"VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form","xscvdpspn XT,XB","60@0|T@6|///@11|B@16|267@21|BX@30|TX@31|",""
+"VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form","xscvdpsxds XT,XB","60@0|T@6|///@11|B@16|344@21|BX@30|TX@31|",""
+"VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form","xscvdpsxws XT,XB","60@0|T@6|///@11|B@16|88@21|BX@30|TX@31|",""
+"VSX Scalar truncate Double-Precision integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form","xscvdpuxds XT,XB","60@0|T@6|///@11|B@16|328@21|BX@30|TX@31|",""
+"VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form","xscvdpuxws XT,XB","60@0|T@6|///@11|B@16|72@21|BX@30|TX@31|",""
+"VSX Scalar Convert Single-Precision to Double-Precision format XX2-form","xscvspdp XT,XB","60@0|T@6|///@11|B@16|329@21|BX@30|TX@31|",""
+"VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form","xscvspdpn XT,XB","60@0|T@6|///@11|B@16|331@21|BX@30|TX@31|",""
+"VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Double-Precision format XX2-form","xscvsxddp XT,XB","60@0|T@6|///@11|B@16|376@21|BX@30|TX@31|",""
+"VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Single-Precision XX2-form","xscvsxdsp XT,XB","60@0|T@6|///@11|B@16|312@21|BX@30|TX@31|",""
+"VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Double-Precision format XX2-form","xscvuxddp XT,XB","60@0|T@6|///@11|B@16|360@21|BX@30|TX@31|",""
+"VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Single-Precision XX2-form","xscvuxdsp XT,XB","60@0|T@6|///@11|B@16|296@21|BX@30|TX@31|",""
+"VSX Scalar Divide Double-Precision XX3-form","xsdivdp XT,XA,XB","60@0|T@6|A@11|B@16|56@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Divide Single-Precision XX3-form","xsdivsp XT,XA,XB","60@0|T@6|A@11|B@16|24@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Multiply-Add Double-Precision XX3-form","xsmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|33@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Multiply-Add Single-Precision XX3-form","xsmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|1@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Maximum Double-Precision XX3-form","xsmaxdp XT,XA,XB","60@0|T@6|A@11|B@16|160@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Minimum Double-Precision XX3-form","xsmindp XT,XA,XB","60@0|T@6|A@11|B@16|168@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Multiply-Subtract Double-Precision XX3-form","xsmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|49@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Multiply-Subtract Single-Precision XX3-form","xsmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|17@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Multiply Double-Precision XX3-form","xsmuldp XT,XA,XB","60@0|T@6|A@11|B@16|48@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Multiply Single-Precision XX3-form","xsmulsp XT,XA,XB","60@0|T@6|A@11|B@16|16@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Negative Absolute Value Double-Precision XX2-form","xsnabsdp XT,XB","60@0|T@6|///@11|B@16|361@21|BX@30|TX@31|",""
+"VSX Scalar Negate Double-Precision XX2-form","xsnegdp XT,XB","60@0|T@6|///@11|B@16|377@21|BX@30|TX@31|",""
+"VSX Scalar Negative Multiply-Add Double-Precision XX3-form","xsnmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|161@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Negative Multiply-Add Single-Precision XX3-form","xsnmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|129@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Negative Multiply-Subtract Double-Precision XX3-form","xsnmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|177@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Negative Multiply-Subtract Single-Precision XX3-form","xsnmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|145@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form","xsrdpi XT,XB","60@0|T@6|///@11|B@16|73@21|BX@30|TX@31|",""
+"VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form","xsrdpic XT,XB","60@0|T@6|///@11|B@16|107@21|BX@30|TX@31|",""
+"VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form","xsrdpim XT,XB","60@0|T@6|///@11|B@16|121@21|BX@30|TX@31|",""
+"VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form","xsrdpip XT,XB","60@0|T@6|///@11|B@16|105@21|BX@30|TX@31|",""
+"VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form","xsrdpiz XT,XB","60@0|T@6|///@11|B@16|89@21|BX@30|TX@31|",""
+"VSX Scalar Reciprocal Estimate Double-Precision XX2-form","xsredp XT,XB","60@0|T@6|///@11|B@16|90@21|BX@30|TX@31|",""
+"VSX Scalar Reciprocal Estimate Single-Precision XX2-form","xsresp XT,XB","60@0|T@6|///@11|B@16|26@21|BX@30|TX@31|",""
+"VSX Scalar Round to Single-Precision XX2-form","xsrsp XT,XB","60@0|T@6|///@11|B@16|281@21|BX@30|TX@31|",""
+"VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form","xsrsqrtedp XT,XB","60@0|T@6|///@11|B@16|74@21|BX@30|TX@31|",""
+"VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form","xsrsqrtesp XT,XB","60@0|T@6|///@11|B@16|10@21|BX@30|TX@31|",""
+"VSX Scalar Square Root Double-Precision XX2-form","xssqrtdp XT,XB","60@0|T@6|///@11|B@16|75@21|BX@30|TX@31|",""
+"VSX Scalar Square Root Single-Precision XX-form","xssqrtsp XT,XB","60@0|T@6|///@11|B@16|11@21|BX@30|TX@31|",""
+"VSX Scalar Subtract Double-Precision XX3-form","xssubdp XT,XA,XB","60@0|T@6|A@11|B@16|40@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Subtract Single-Precision XX3-form","xssubsp XT,XA,XB","60@0|T@6|A@11|B@16|8@21|AX@29|BX@30|TX@31|",""
+"VSX Scalar Test for software Divide Double-Precision XX3-form","xstdivdp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|61@21|AX@29|BX@30|/@31|",""
+"VSX Scalar Test for software Square Root Double-Precision XX2-form","xstsqrtdp BF,XB","60@0|BF@6|//@9|///@11|B@16|106@21|BX@30|/@31|",""
+"VSX Vector Absolute Value Double-Precision XX2-form","xvabsdp XT,XB","60@0|T@6|///@11|B@16|473@21|BX@30|TX@31|",""
+"VSX Vector Absolute Value Single-Precision XX2-form","xvabssp XT,XB","60@0|T@6|///@11|B@16|409@21|BX@30|TX@31|",""
+"VSX Vector Add Double-Precision XX3-form","xvadddp XT,XA,XB","60@0|T@6|A@11|B@16|96@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Add Single-Precision XX3-form","xvaddsp XT,XA,XB","60@0|T@6|A@11|B@16|64@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form","xvcmpeqdp XT,XA,XB ( Rc=0 )|xvcmpeqdp. XT,XA,XB ( Rc=1 )","60@0|T@6|A@11|B@16|Rc@21|99@22|AX@29|BX@30|TX@31|",""
+"VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form","xvcmpeqsp XT,XA,XB ( Rc=0 )|xvcmpeqsp. XT,XA,XB ( Rc=1 )","60@0|T@6|A@11|B@16|Rc@21|67@22|AX@29|BX@30|TX@31|",""
+"VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form","xvcmpgedp XT,XA,XB ( Rc=0 )|xvcmpgedp. XT,XA,XB ( Rc=1 )","60@0|T@6|A@11|B@16|Rc@21|115@22|AX@29|BX@30|TX@31|",""
+"VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form","xvcmpgesp XT,XA,XB ( Rc=0 )|xvcmpgesp. XT,XA,XB ( Rc=1 )","60@0|T@6|A@11|B@16|Rc@21|83@22|AX@29|BX@30|TX@31|",""
+"VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form","xvcmpgtdp XT,XA,XB ( Rc=0 )|xvcmpgtdp. XT,XA,XB ( Rc=1 )","60@0|T@6|A@11|B@16|Rc@21|107@22|AX@29|BX@30|TX@31|",""
+"VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form","xvcmpgtsp XT,XA,XB ( Rc=0 )|xvcmpgtsp. XT,XA,XB ( Rc=1 )","60@0|T@6|A@11|B@16|Rc@21|75@22|AX@29|BX@30|TX@31|",""
+"VSX Vector Copy Sign Double-Precision XX3-form","xvcpsgndp XT,XA,XB","60@0|T@6|A@11|B@16|240@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Copy Sign Single-Precision XX3-form","xvcpsgnsp XT,XA,XB","60@0|T@6|A@11|B@16|208@21|AX@29|BX@30|TX@31|",""
+"VSX Vector round Double-Precision to single-precision and Convert to Single-Precision format XX2-form","xvcvdpsp XT,XB","60@0|T@6|///@11|B@16|393@21|BX@30|TX@31|",""
+"VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form","xvcvdpsxds XT,XB","60@0|T@6|///@11|B@16|472@21|BX@30|TX@31|",""
+"VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form","xvcvdpsxws XT,XB","60@0|T@6|///@11|B@16|216@21|BX@30|TX@31|",""
+"VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form","xvcvdpuxds XT,XB","60@0|T@6|///@11|B@16|456@21|BX@30|TX@31|",""
+"VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form","xvcvdpuxws XT,XB","60@0|T@6|///@11|B@16|200@21|BX@30|TX@31|",""
+"VSX Vector Convert Single-Precision to Double-Precision format XX2-form","xvcvspdp XT,XB","60@0|T@6|///@11|B@16|457@21|BX@30|TX@31|",""
+"VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form","xvcvspsxds XT,XB","60@0|T@6|///@11|B@16|408@21|BX@30|TX@31|",""
+"VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form","xvcvspsxws XT,XB","60@0|T@6|///@11|B@16|152@21|BX@30|TX@31|",""
+"VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form","xvcvspuxds XT,XB","60@0|T@6|///@11|B@16|392@21|BX@30|TX@31|",""
+"VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form","xvcvspuxws XT,XB","60@0|T@6|///@11|B@16|136@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Signed Integer Doubleword to Double-Precision format XX2-form","xvcvsxddp XT,XB","60@0|T@6|///@11|B@16|504@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Signed Integer Doubleword to Single-Precision format XX2-form","xvcvsxdsp XT,XB","60@0|T@6|///@11|B@16|440@21|BX@30|TX@31|",""
+"VSX Vector Convert Signed Integer Word to Double-Precision format XX2-form","xvcvsxwdp XT,XB","60@0|T@6|///@11|B@16|248@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Signed Integer Word to Single-Precision format XX2-form","xvcvsxwsp XT,XB","60@0|T@6|///@11|B@16|184@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Unsigned Integer Doubleword to Double-Precision format XX2-form","xvcvuxddp XT,XB","60@0|T@6|///@11|B@16|488@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Unsigned Integer Doubleword to Single-Precision format XX2-form","xvcvuxdsp XT,XB","60@0|T@6|///@11|B@16|424@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Unsigned Integer Word to Double-Precision format XX2-form","xvcvuxwdp XT,XB","60@0|T@6|///@11|B@16|232@21|BX@30|TX@31|",""
+"VSX Vector Convert and round Unsigned Integer Word to Single-Precision format XX2-form","xvcvuxwsp XT,XB","60@0|T@6|///@11|B@16|168@21|BX@30|TX@31|",""
+"VSX Vector Divide Double-Precision XX3-form","xvdivdp XT,XA,XB","60@0|T@6|A@11|B@16|120@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Divide Single-Precision XX3-form","xvdivsp XT,XA,XB","60@0|T@6|A@11|B@16|88@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Multiply-Add Double-Precision XX3-form","xvmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|97@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Multiply-Add Single-Precision XX3-form","xvmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|65@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Maximum Double-Precision XX3-form","xvmaxdp XT,XA,XB","60@0|T@6|A@11|B@16|224@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Maximum Single-Precision XX3-form","xvmaxsp XT,XA,XB","60@0|T@6|A@11|B@16|192@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Minimum Double-Precision XX3-form","xvmindp XT,XA,XB","60@0|T@6|A@11|B@16|232@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Minimum Single-Precision XX3-form","xvminsp XT,XA,XB","60@0|T@6|A@11|B@16|200@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Multiply-Subtract Double-Precision XX3-form","xvmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|113@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Multiply-Subtract Single-Precision XX3-form","xvmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|81@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Multiply Double-Precision XX3-form","xvmuldp XT,XA,XB","60@0|T@6|A@11|B@16|112@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Multiply Single-Precision XX3-form","xvmulsp XT,XA,XB","60@0|T@6|A@11|B@16|80@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Negative Absolute Value Double-Precision XX2-form","xvnabsdp XT,XB","60@0|T@6|///@11|B@16|489@21|BX@30|TX@31|",""
+"VSX Vector Negative Absolute Value Single-Precision XX2-form","xvnabssp XT,XB","60@0|T@6|///@11|B@16|425@21|BX@30|TX@31|",""
+"VSX Vector Negate Double-Precision XX2-form","xvnegdp XT,XB","60@0|T@6|///@11|B@16|505@21|BX@30|TX@31|",""
+"VSX Vector Negate Single-Precision XX2-form","xvnegsp XT,XB","60@0|T@6|///@11|B@16|441@21|BX@30|TX@31|",""
+"VSX Vector Negative Multiply-Add Double-Precision XX3-form","xvnmaddadp XT,XA,XB","60@0|T@6|A@11|B@16|225@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Negative Multiply-Add Single-Precision XX3-form","xvnmaddasp XT,XA,XB","60@0|T@6|A@11|B@16|193@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Negative Multiply-Subtract Double-Precision XX3-form","xvnmsubadp XT,XA,XB","60@0|T@6|A@11|B@16|241@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Negative Multiply-Subtract Single-Precision XX3-form","xvnmsubasp XT,XA,XB","60@0|T@6|A@11|B@16|209@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form","xvrdpi XT,XB","60@0|T@6|///@11|B@16|201@21|BX@30|TX@31|",""
+"VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form","xvrdpic XT,XB","60@0|T@6|///@11|B@16|235@21|BX@30|TX@31|",""
+"VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form","xvrdpim XT,XB","60@0|T@6|///@11|B@16|249@21|BX@30|TX@31|",""
+"VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form","xvrdpip XT,XB","60@0|T@6|///@11|B@16|233@21|BX@30|TX@31|",""
+"VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form","xvrdpiz XT,XB","60@0|T@6|///@11|B@16|217@21|BX@30|TX@31|",""
+"VSX Vector Reciprocal Estimate Double-Precision XX2-form","xvredp XT,XB","60@0|T@6|///@11|B@16|218@21|BX@30|TX@31|",""
+"VSX Vector Reciprocal Estimate Single-Precision XX2-form","xvresp XT,XB","60@0|T@6|///@11|B@16|154@21|BX@30|TX@31|",""
+"VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form","xvrspi XT,XB","60@0|T@6|///@11|B@16|137@21|BX@30|TX@31|",""
+"VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form","xvrspic XT,XB","60@0|T@6|///@11|B@16|171@21|BX@30|TX@31|",""
+"VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form","xvrspim XT,XB","60@0|T@6|///@11|B@16|185@21|BX@30|TX@31|",""
+"VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form","xvrspip XT,XB","60@0|T@6|///@11|B@16|169@21|BX@30|TX@31|",""
+"VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form","xvrspiz XT,XB","60@0|T@6|///@11|B@16|153@21|BX@30|TX@31|",""
+"VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form","xvrsqrtedp XT,XB","60@0|T@6|///@11|B@16|202@21|BX@30|TX@31|",""
+"VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form","xvrsqrtesp XT,XB","60@0|T@6|///@11|B@16|138@21|BX@30|TX@31|",""
+"VSX Vector Square Root Double-Precision XX2-form","xvsqrtdp XT,XB","60@0|T@6|///@11|B@16|203@21|BX@30|TX@31|",""
+"VSX Vector Square Root Single-Precision XX2-form","xvsqrtsp XT,XB","60@0|T@6|///@11|B@16|139@21|BX@30|TX@31|",""
+"VSX Vector Subtract Double-Precision XX3-form","xvsubdp XT,XA,XB","60@0|T@6|A@11|B@16|104@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Subtract Single-Precision XX3-form","xvsubsp XT,XA,XB","60@0|T@6|A@11|B@16|72@21|AX@29|BX@30|TX@31|",""
+"VSX Vector Test for software Divide Double-Precision XX3-form","xvtdivdp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|125@21|AX@29|BX@30|/@31|",""
+"VSX Vector Test for software Divide Single-Precision XX3-form","xvtdivsp BF,XA,XB","60@0|BF@6|//@9|A@11|B@16|93@21|AX@29|BX@30|/@31|",""
+"VSX Vector Test for software Square Root Double-Precision XX2-form","xvtsqrtdp BF,XB","60@0|BF@6|//@9|///@11|B@16|234@21|BX@30|/@31|",""
+"VSX Vector Test for software Square Root Single-Precision XX2-form","xvtsqrtsp BF,XB","60@0|BF@6|//@9|///@11|B@16|170@21|BX@30|/@31|",""
+"VSX Logical AND XX3-form","xxland XT,XA,XB","60@0|T@6|A@11|B@16|130@21|AX@29|BX@30|TX@31|",""
+"VSX Logical AND with Complement XX3-form","xxlandc XT,XA,XB","60@0|T@6|A@11|B@16|138@21|AX@29|BX@30|TX@31|",""
+"VSX Logical Equivalence XX3-form","xxleqv XT,XA,XB","60@0|T@6|A@11|B@16|186@21|AX@29|BX@30|TX@31|",""
+"VSX Logical NAND XX3-form","xxlnand XT,XA,XB","60@0|T@6|A@11|B@16|178@21|AX@29|BX@30|TX@31|",""
+"VSX Logical OR with Complement XX3-form","xxlorc XT,XA,XB","60@0|T@6|A@11|B@16|170@21|AX@29|BX@30|TX@31|",""
+"VSX Logical NOR XX3-form","xxlnor XT,XA,XB","60@0|T@6|A@11|B@16|162@21|AX@29|BX@30|TX@31|",""
+"VSX Logical OR XX3-form","xxlor XT,XA,XB","60@0|T@6|A@11|B@16|146@21|AX@29|BX@30|TX@31|",""
+"VSX Logical XOR XX3-form","xxlxor XT,XA,XB","60@0|T@6|A@11|B@16|154@21|AX@29|BX@30|TX@31|",""
+"VSX Merge High Word XX3-form","xxmrghw XT,XA,XB","60@0|T@6|A@11|B@16|18@21|AX@29|BX@30|TX@31|",""
+"VSX Merge Low Word XX3-form","xxmrglw XT,XA,XB","60@0|T@6|A@11|B@16|50@21|AX@29|BX@30|TX@31|",""
+"VSX Permute Doubleword Immediate XX3-form","xxpermdi XT,XA,XB,DM","60@0|T@6|A@11|B@16|0@21|DM@22|10@24|AX@29|BX@30|TX@31|",""
+"VSX Select XX4-form","xxsel XT,XA,XB,XC","60@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|",""
+"VSX Shift Left Double by Word Immediate XX3-form","xxsldwi XT,XA,XB,SHW","60@0|T@6|A@11|B@16|0@21|SHW@22|2@24|AX@29|BX@30|TX@31|",""
+"VSX Splat Word XX2-form","xxspltw XT,XB,UIM","60@0|T@6|///@11|UIM@14|B@16|164@21|BX@30|TX@31|",""
+"Bit Reversed Increment EVX-form","brinc RT,RA,RB","4@0|RT@6|RA@11|RB@16|527@21|",""
+"Vector Absolute Value EVX-form","evabs RT,RA","4@0|RT@6|RA@11|///@16|520@21|",""
+"Vector Add Immediate Word EVX-form","evaddiw RT,RB,UI","4@0|RT@6|UI@11|RB@16|514@21|",""
+"Vector Add Signed, Modulo, Integer to Accumulator Word EVX-form","evaddsmiaaw RT,RA","4@0|RT@6|RA@11|///@16|1225@21|",""
+"Vector Add Signed, Saturate, Integer to Accumulator Word EVX-form","evaddssiaaw RT,RA","4@0|RT@6|RA@11|///@16|1217@21|",""
+"Vector Add Unsigned, Modulo, Integer to Accumulator Word EVX-form","evaddumiaaw RT,RA","4@0|RT@6|RA@11|///@16|1224@21|",""
+"Vector Add Unsigned, Saturate, Integer to Accumulator Word EVX-form","evaddusiaaw RT,RA","4@0|RT@6|RA@11|///@16|1216@21|",""
+"Vector Add Word EVX-form","evaddw RT,RA,RB","4@0|RT@6|RA@11|RB@16|512@21|",""
+"Vector AND EVX-form","evand RT,RA,RB","4@0|RT@6|RA@11|RB@16|529@21|",""
+"Vector Compare Equal EVX-form","evcmpeq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|564@21|",""
+"Vector AND with Complement EVX-form","evandc RT,RA,RB","4@0|RT@6|RA@11|RB@16|530@21|",""
+"Vector Compare Greater Than Signed EVX-form","evcmpgts BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|561@21|",""
+"Vector Compare Greater Than Unsigned EVX-form","evcmpgtu BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|560@21|",""
+"Vector Compare Less Than Unsigned EVX-form","evcmpltu BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|562@21|",""
+"Vector Compare Less Than Signed EVX-form","evcmplts BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|563@21|",""
+"Vector Count Leading Signed Bits Word EVX-form","evcntlsw RT,RA","4@0|RT@6|RA@11|///@16|526@21|",""
+"Vector Count Leading Zeros Word EVX-form","evcntlzw RT,RA","4@0|RT@6|RA@11|///@16|525@21|",""
+"Vector Divide Word Signed EVX-form","evdivws RT,RA,RB","4@0|RT@6|RA@11|RB@16|1222@21|",""
+"Vector Divide Word Unsigned EVX-form","evdivwu RT,RA,RB","4@0|RT@6|RA@11|RB@16|1223@21|",""
+"Vector Equivalent EVX-form","eveqv RT,RA,RB","4@0|RT@6|RA@11|RB@16|537@21|",""
+"Vector Extend Sign Byte EVX-form","evextsb RT,RA","4@0|RT@6|RA@11|///@16|522@21|",""
+"Vector Extend Sign Halfword EVX-form","evextsh RT,RA","4@0|RT@6|RA@11|///@16|523@21|",""
+"Vector Load Double Word into Double Word EVX-form","evldd RT,D(RA)","4@0|RT@6|RA@11|UI@16|769@21|",""
+"Vector Load Double into Four Halfwords EVX-form","evldh RT,D(RA)","4@0|RT@6|RA@11|UI@16|773@21|",""
+"Vector Load Double Word into Double Word Indexed EVX-form","evlddx RT,RA,RB","4@0|RT@6|RA@11|RB@16|768@21|",""
+"Vector Load Double into Four Halfwords Indexed EVX-form","evldhx RT,RA,RB","4@0|RT@6|RA@11|RB@16|772@21|",""
+"Vector Load Double into Two Words EVX-form","evldw RT,D(RA)","4@0|RT@6|RA@11|UI@16|771@21|",""
+"Vector Load Halfword into Halfwords Even and Splat EVX-form","evlhhesplat RT,D(RA)","4@0|RT@6|RA@11|UI@16|777@21|",""
+"Vector Load Double into Two Words Indexed EVX-form","evldwx RT,RA,RB","4@0|RT@6|RA@11|RB@16|770@21|",""
+"Vector Load Halfword into Halfwords Even and Splat Indexed EVX-form","evlhhesplatx RT,RA,RB","4@0|RT@6|RA@11|RB@16|776@21|",""
+"Vector Load Halfword into Halfword Odd Signed and Splat EVX-form","evlhhossplat RT,D(RA)","4@0|RT@6|RA@11|UI@16|783@21|",""
+"Vector Load Halfword into Halfword Odd Unsigned and Splat EVX-form","evlhhousplat RT,D(RA)","4@0|RT@6|RA@11|UI@16|781@21|",""
+"Vector Load Halfword into Halfword Odd Signed and Splat Indexed EVX-form","evlhhossplatx RT,RA,RB","4@0|RT@6|RA@11|RB@16|782@21|",""
+"Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed EVX-form","evlhhousplatx RT,RA,RB","4@0|RT@6|RA@11|RB@16|780@21|",""
+"Vector Load Word into Two Halfwords Even EVX-form","evlwhe RT,D(RA)","4@0|RT@6|RA@11|UI@16|785@21|",""
+"Vector Load Word into Two Halfwords Odd Signed (with sign extension) EVX-form","evlwhos RT,D(RA)","4@0|RT@6|RA@11|UI@16|791@21|",""
+"Vector Load Word into Two Halfwords Even Indexed EVX-form","evlwhex RT,RA,RB","4@0|RT@6|RA@11|RB@16|784@21|",""
+"Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) EVX-form","evlwhosx RT,RA,RB","4@0|RT@6|RA@11|RB@16|790@21|",""
+"Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) EVX-form","evlwhou RT,D(RA)","4@0|RT@6|RA@11|UI@16|789@21|",""
+"Vector Load Word into Two Halfwords and Splat EVX-form","evlwhsplat RT,D(RA)","4@0|RT@6|RA@11|UI@16|797@21|",""
+"Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) EVX-form","evlwhoux RT,RA,RB","4@0|RT@6|RA@11|RB@16|788@21|",""
+"Vector Load Word into Two Halfwords and Splat Indexed EVX-form","evlwhsplatx RT,RA,RB","4@0|RT@6|RA@11|RB@16|796@21|",""
+"Vector Load Word into Word and Splat EVX-form","evlwwsplat RT,D(RA)","4@0|RT@6|RA@11|UI@16|793@21|",""
+"Vector Merge High EVX-form","evmergehi RT,RA,RB","4@0|RT@6|RA@11|RB@16|556@21|",""
+"Vector Load Word into Word and Splat Indexed EVX-form","evlwwsplatx RT,RA,RB","4@0|RT@6|RA@11|RB@16|792@21|",""
+"Vector Merge Low EVX-form","evmergelo RT,RA,RB","4@0|RT@6|RA@11|RB@16|557@21|",""
+"Vector Merge High/Low EVX-form","evmergehilo RT,RA,RB","4@0|RT@6|RA@11|RB@16|558@21|",""
+"Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form","evmhegsmfaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1323@21|",""
+"Vector Merge Low/High EVX-form","evmergelohi RT,RA,RB","4@0|RT@6|RA@11|RB@16|559@21|",""
+"Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form","evmhegsmfan RT,RA,RB","4@0|RT@6|RA@11|RB@16|1451@21|",""
+"Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate EVX-form","evmhegsmiaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1321@21|",""
+"Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form","evmhegumiaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1320@21|",""
+"Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form","evmhegsmian RT,RA,RB","4@0|RT@6|RA@11|RB@16|1449@21|",""
+"Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form","evmhegumian RT,RA,RB","4@0|RT@6|RA@11|RB@16|1448@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Fractional EVX-form","evmhesmf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1035@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words EVX-form","evmhesmfaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1291@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator EVX-form","evmhesmfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1067@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form","evmhesmfanw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1419@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Integer EVX-form","evmhesmi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1033@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words EVX-form","evmhesmiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1289@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator EVX-form","evmhesmia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1065@21|",""
+"Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form","evmhesmianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1417@21|",""
+"Vector Multiply Halfwords, Even, Signed, Saturate, Fractional EVX-form","evmhessf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1027@21|",""
+"Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator EVX-form","evmhessfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1059@21|",""
+"Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words EVX-form","evmhessfaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1283@21|",""
+"Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form","evmhessfanw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1411@21|",""
+"Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words EVX-form","evmhessiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1281@21|",""
+"Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form","evmhessianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1409@21|",""
+"Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer EVX-form","evmheumi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1032@21|",""
+"Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words EVX-form","evmheumiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1288@21|",""
+"Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator EVX-form","evmheumia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1064@21|",""
+"Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form","evmheumianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1416@21|",""
+"Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words EVX-form","evmheusiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1280@21|",""
+"Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form","evmheusianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1408@21|",""
+"Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form","evmhogsmfaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1327@21|",""
+"Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate EVX-form","evmhogsmiaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1325@21|",""
+"Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form","evmhogsmfan RT,RA,RB","4@0|RT@6|RA@11|RB@16|1455@21|",""
+"Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form","evmhogsmian RT,RA,RB","4@0|RT@6|RA@11|RB@16|1453@21|",""
+"Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form","evmhogumiaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1324@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional EVX-form","evmhosmf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1039@21|",""
+"Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form","evmhogumian RT,RA,RB","4@0|RT@6|RA@11|RB@16|1452@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator EVX-form","evmhosmfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1071@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words EVX-form","evmhosmfaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1295@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Integer EVX-form","evmhosmi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1037@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form","evmhosmfanw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1423@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator EVX-form","evmhosmia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1069@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words EVX-form","evmhosmiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1293@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form","evmhosmianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1421@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional EVX-form","evmhossf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1031@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator EVX-form","evmhossfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1063@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words EVX-form","evmhossfaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1287@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form","evmhossfanw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1415@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words EVX-form","evmhossiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1285@21|",""
+"Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer EVX-form","evmhoumi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1036@21|",""
+"Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form","evmhossianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1413@21|",""
+"Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator EVX-form","evmhoumia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1068@21|",""
+"Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words EVX-form","evmhoumiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1292@21|",""
+"Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words EVX-form","evmhousiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1284@21|",""
+"Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form","evmhoumianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1420@21|",""
+"Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form","evmhousianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1412@21|",""
+"Initialize Accumulator EVX-form","evmra RT,RA","4@0|RT@6|RA@11|///@16|1220@21|",""
+"Vector Multiply Word High Signed, Modulo, Fractional EVX-form","evmwhsmf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1103@21|",""
+"Vector Multiply Word High Signed, Modulo, Integer EVX-form","evmwhsmi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1101@21|",""
+"Vector Multiply Word High Signed, Modulo, Fractional to Accumulator EVX-form","evmwhsmfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1135@21|",""
+"Vector Multiply Word High Signed, Modulo, Integer to Accumulator EVX-form","evmwhsmia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1133@21|",""
+"Vector Multiply Word High Signed, Saturate, Fractional EVX-form","evmwhssf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1095@21|",""
+"Vector Multiply Word High Unsigned, Modulo, Integer EVX-form","evmwhumi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1100@21|",""
+"Vector Multiply Word High Signed, Saturate, Fractional to Accumulator EVX-form","evmwhssfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1127@21|",""
+"Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator EVX-form","evmwhumia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1132@21|",""
+"Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words EVX-form","evmwlsmiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1353@21|",""
+"Vector Multiply Word Low Signed, Saturate, Integer and Accumulate into Words EVX-form","evmwlssiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1345@21|",""
+"Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words EVX-form","evmwlsmianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1481@21|",""
+"Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words EVX-form","evmwlssianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1473@21|",""
+"Vector Multiply Word Low Unsigned, Modulo, Integer EVX-form","evmwlumi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1096@21|",""
+"Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words EVX-form","evmwlumiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1352@21|",""
+"Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator EVX-form","evmwlumia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1128@21|",""
+"Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words EVX-form","evmwlumianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1480@21|",""
+"Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words EVX-form","evmwlusiaaw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1344@21|",""
+"Vector Multiply Word Signed, Modulo, Fractional EVX-form","evmwsmf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1115@21|",""
+"Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words EVX-form","evmwlusianw RT,RA,RB","4@0|RT@6|RA@11|RB@16|1472@21|",""
+"Vector Multiply Word Signed, Modulo, Fractional to Accumulator EVX-form","evmwsmfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1147@21|",""
+"Vector Multiply Word Signed, Modulo, Fractional and Accumulate EVX-form","evmwsmfaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1371@21|",""
+"Vector Multiply Word Signed, Modulo, Integer EVX-form","evmwsmi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1113@21|",""
+"Vector Multiply Word Signed, Modulo, Integer and Accumulate EVX-form","evmwsmiaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1369@21|",""
+"Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative EVX-form","evmwsmfan RT,RA,RB","4@0|RT@6|RA@11|RB@16|1499@21|",""
+"Vector Multiply Word Signed, Modulo, Integer to Accumulator EVX-form","evmwsmia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1145@21|",""
+"Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative EVX-form","evmwsmian RT,RA,RB","4@0|RT@6|RA@11|RB@16|1497@21|",""
+"Vector Multiply Word Signed, Saturate, Fractional EVX-form","evmwssf RT,RA,RB","4@0|RT@6|RA@11|RB@16|1107@21|",""
+"Vector Multiply Word Signed, Saturate, Fractional to Accumulator EVX-form","evmwssfa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1139@21|",""
+"Vector Multiply Word Signed, Saturate, Fractional and Accumulate EVX-form","evmwssfaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1363@21|",""
+"Vector Multiply Word Unsigned, Modulo, Integer EVX-form","evmwumi RT,RA,RB","4@0|RT@6|RA@11|RB@16|1112@21|",""
+"Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative EVX-form","evmwssfan RT,RA,RB","4@0|RT@6|RA@11|RB@16|1491@21|",""
+"Vector Multiply Word Unsigned, Modulo, Integer to Accumulator EVX-form","evmwumia RT,RA,RB","4@0|RT@6|RA@11|RB@16|1144@21|",""
+"Vector Multiply Word Unsigned, Modulo, Integer and Accumulate EVX-form","evmwumiaa RT,RA,RB","4@0|RT@6|RA@11|RB@16|1368@21|",""
+"Vector NAND EVX-form","evnand RT,RA,RB","4@0|RT@6|RA@11|RB@16|542@21|",""
+"Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative EVX-form","evmwumian RT,RA,RB","4@0|RT@6|RA@11|RB@16|1496@21|",""
+"Vector Negate EVX-form","evneg RT,RA","4@0|RT@6|RA@11|///@16|521@21|",""
+"Vector NOR EVX-form","evnor RT,RA,RB","4@0|RT@6|RA@11|RB@16|536@21|",""
+"Vector OR with Complement EVX-form","evorc RT,RA,RB","4@0|RT@6|RA@11|RB@16|539@21|",""
+"Vector OR EVX-form","evor RT,RA,RB","4@0|RT@6|RA@11|RB@16|535@21|",""
+"Vector Rotate Left Word EVX-form","evrlw RT,RA,RB","4@0|RT@6|RA@11|RB@16|552@21|",""
+"Vector Rotate Left Word Immediate EVX-form","evrlwi RT,RA,UI","4@0|RT@6|RA@11|UI@16|554@21|",""
+"Vector Select EVS-form","evsel RT,RA,RB,BFA","4@0|RT@6|RA@11|RB@16|79@21|BFA@29|",""
+"Vector Round Word EVX-form","evrndw RT,RA","4@0|RT@6|RA@11|///@16|524@21|",""
+"Vector Shift Left Word EVX-form","evslw RT,RA,RB","4@0|RT@6|RA@11|RB@16|548@21|",""
+"Vector Splat Fractional Immediate EVX-form","evsplatfi RT,SI","4@0|RT@6|SI@11|///@16|555@21|",""
+"Vector Shift Right Word Immediate Signed EVX-form","evsrwis RT,RA,UI","4@0|RT@6|RA@11|UI@16|547@21|",""
+"Vector Shift Left Word Immediate EVX-form","evslwi RT,RA,UI","4@0|RT@6|RA@11|UI@16|550@21|",""
+"Vector Splat Immediate EVX-form","evsplati RT,SI","4@0|RT@6|SI@11|///@16|553@21|",""
+"Vector Shift Right Word Immediate Unsigned EVX-form","evsrwiu RT,RA,UI","4@0|RT@6|RA@11|UI@16|546@21|",""
+"Vector Shift Right Word Signed EVX-form","evsrws RT,RA,RB","4@0|RT@6|RA@11|RB@16|545@21|",""
+"Vector Store Double of Double EVX-form","evstdd RS,D(RA)","4@0|RS@6|RA@11|UI@16|801@21|",""
+"Vector Shift Right Word Unsigned EVX-form","evsrwu RT,RA,RB","4@0|RT@6|RA@11|RB@16|544@21|",""
+"Vector Store Double of Double Indexed EVX-form","evstddx RS,RA,RB","4@0|RS@6|RA@11|RB@16|800@21|",""
+"Vector Store Double of Four Halfwords EVX-form","evstdh RS,D(RA)","4@0|RS@6|RA@11|UI@16|805@21|",""
+"Vector Store Double of Two Words EVX-form","evstdw RS,D(RA)","4@0|RS@6|RA@11|UI@16|803@21|",""
+"Vector Store Double of Four Halfwords Indexed EVX-form","evstdhx RS,RA,RB","4@0|RS@6|RA@11|RB@16|804@21|",""
+"Vector Store Double of Two Words Indexed EVX-form","evstdwx RS,RA,RB","4@0|RS@6|RA@11|RB@16|802@21|",""
+"Vector Store Word of Two Halfwords from Even EVX-form","evstwhe RS,D(RA)","4@0|RS@6|RA@11|UI@16|817@21|",""
+"Vector Store Word of Two Halfwords from Odd EVX-form","evstwho RS,D(RA)","4@0|RS@6|RA@11|UI@16|821@21|",""
+"Vector Store Word of Word from Even EVX-form","evstwwe RS,D(RA)","4@0|RS@6|RA@11|UI@16|825@21|",""
+"Vector Store Word of Two Halfwords from Even Indexed EVX-form","evstwhex RS,RA,RB","4@0|RS@6|RA@11|RB@16|816@21|",""
+"Vector Store Word of Two Halfwords from Odd Indexed EVX-form","evstwhox RS,RA,RB","4@0|RS@6|RA@11|RB@16|820@21|",""
+"Vector Store Word of Word from Even Indexed EVX-form","evstwwex RS,RA,RB","4@0|RS@6|RA@11|RB@16|824@21|",""
+"Vector Store Word of Word from Odd EVX-form","evstwwo RS,D(RA)","4@0|RS@6|RA@11|UI@16|829@21|",""
+"Vector Subtract Signed, Modulo, Integer to Accumulator Word EVX-form","evsubfsmiaaw RT,RA","4@0|RT@6|RA@11|///@16|1227@21|",""
+"Vector Store Word of Word from Odd Indexed EVX-form","evstwwox RS,RA,RB","4@0|RS@6|RA@11|RB@16|828@21|",""
+"Vector Subtract Signed, Saturate, Integer to Accumulator Word EVX-form","evsubfssiaaw RT,RA","4@0|RT@6|RA@11|///@16|1219@21|",""
+"Vector Subtract Unsigned, Modulo, Integer to Accumulator Word EVX-form","evsubfumiaaw RT,RA","4@0|RT@6|RA@11|///@16|1226@21|",""
+"Vector Subtract Unsigned, Saturate, Integer to Accumulator Word EVX-form","evsubfusiaaw RT,RA","4@0|RT@6|RA@11|///@16|1218@21|",""
+"Vector Subtract from Word EVX-form","evsubfw RT,RA,RB","4@0|RT@6|RA@11|RB@16|516@21|",""
+"Vector Subtract Immediate from Word EVX-form","evsubifw RT,UI,RB","4@0|RT@6|UI@11|RB@16|518@21|",""
+"Vector XOR EVX-form","evxor RT,RA,RB","4@0|RT@6|RA@11|RB@16|534@21|",""
+"Vector Floating-Point Single-Precision Absolute Value EVX-form","evfsabs RT,RA","4@0|RT@6|RA@11|///@16|644@21|",""
+"Vector Floating-Point Single-Precision Negative Absolute Value EVX-form","evfsnabs RT,RA","4@0|RT@6|RA@11|///@16|645@21|",""
+"Vector Floating-Point Single-Precision Negate EVX-form","evfsneg RT,RA","4@0|RT@6|RA@11|///@16|646@21|",""
+"Vector Floating-Point Single-Precision Add EVX-form","evfsadd RT,RA,RB","4@0|RT@6|RA@11|RB@16|640@21|",""
+"Vector Floating-Point Single-Precision Multiply EVX-form","evfsmul RT,RA,RB","4@0|RT@6|RA@11|RB@16|648@21|",""
+"Vector Floating-Point Single-Precision Subtract EVX-form","evfssub RT,RA,RB","4@0|RT@6|RA@11|RB@16|641@21|",""
+"Vector Floating-Point Single-Precision Divide EVX-form","evfsdiv RT,RA,RB","4@0|RT@6|RA@11|RB@16|649@21|",""
+"Vector Floating-Point Single-Precision Compare Greater Than EVX-form","evfscmpgt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|652@21|",""
+"Vector Floating-Point Single-Precision Compare Less Than EVX-form","evfscmplt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|653@21|",""
+"Vector Floating-Point Single-Precision Compare Equal EVX-form","evfscmpeq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|654@21|",""
+"Vector Floating-Point Single-Precision Test Greater Than EVX-form","evfststgt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|668@21|",""
+"Vector Floating-Point Single-Precision Test Less Than EVX-form","evfststlt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|669@21|",""
+"Vector Floating-Point Single-Precision Test Equal EVX-form","evfststeq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|670@21|",""
+"Vector Convert Floating-Point Single-Precision from Signed Integer EVX-form","evfscfsi RT,RB","4@0|RT@6|///@11|RB@16|657@21|",""
+"Vector Convert Floating-Point Single-Precision from Signed Fraction EVX-form","evfscfsf RT,RB","4@0|RT@6|///@11|RB@16|659@21|",""
+"Vector Convert Floating-Point Single-Precision from Unsigned Integer EVX-form","evfscfui RT,RB","4@0|RT@6|///@11|RB@16|656@21|",""
+"Vector Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form","evfscfuf RT,RB","4@0|RT@6|///@11|RB@16|658@21|",""
+"Vector Convert Floating-Point Single-Precision to Signed Integer EVX-form","evfsctsi RT,RB","4@0|RT@6|///@11|RB@16|661@21|",""
+"Vector Convert Floating-Point Single-Precision to Unsigned Integer EVX-form","evfsctui RT,RB","4@0|RT@6|///@11|RB@16|660@21|",""
+"Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form","evfsctsiz RT,RB","4@0|RT@6|///@11|RB@16|666@21|",""
+"Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form","evfsctuiz RT,RB","4@0|RT@6|///@11|RB@16|664@21|",""
+"Vector Convert Floating-Point Single-Precision to Signed Fraction EVX-form","evfsctsf RT,RB","4@0|RT@6|///@11|RB@16|663@21|",""
+"Vector Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form","evfsctuf RT,RB","4@0|RT@6|///@11|RB@16|662@21|",""
+"Floating-Point Single-Precision Absolute Value EVX-form","efsabs RT,RA","4@0|RT@6|RA@11|///@16|708@21|",""
+"Floating-Point Single-Precision Negate EVX-form","efsneg RT,RA","4@0|RT@6|RA@11|///@16|710@21|",""
+"Floating-Point Single-Precision Negative Absolute Value EVX-form","efsnabs RT,RA","4@0|RT@6|RA@11|///@16|709@21|",""
+"Floating-Point Single-Precision Add EVX-form","efsadd RT,RA,RB","4@0|RT@6|RA@11|RB@16|704@21|",""
+"Floating-Point Single-Precision Multiply EVX-form","efsmul RT,RA,RB","4@0|RT@6|RA@11|RB@16|712@21|",""
+"Floating-Point Single-Precision Subtract EVX-form","efssub RT,RA,RB","4@0|RT@6|RA@11|RB@16|705@21|",""
+"Floating-Point Single-Precision Divide EVX-form","efsdiv RT,RA,RB","4@0|RT@6|RA@11|RB@16|713@21|",""
+"Floating-Point Single-Precision Compare Greater Than EVX-form","efscmpgt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|716@21|",""
+"Floating-Point Single-Precision Compare Less Than EVX-form","efscmplt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|717@21|",""
+"Floating-Point Single-Precision Compare Equal EVX-form","efscmpeq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|718@21|",""
+"Floating-Point Single-Precision Test Greater Than EVX-form","efststgt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|732@21|",""
+"Floating-Point Single-Precision Test Less Than EVX-form","efststlt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|733@21|",""
+"Floating-Point Single-Precision Test Equal EVX-form","efststeq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|734@21|",""
+"Convert Floating-Point Single-Precision from Signed Integer EVX-form","efscfsi RT,RB","4@0|RT@6|///@11|RB@16|721@21|",""
+"Convert Floating-Point Single-Precision from Signed Fraction EVX-form","efscfsf RT,RB","4@0|RT@6|///@11|RB@16|723@21|",""
+"Convert Floating-Point Single-Precision to Signed Integer EVX-form","efsctsi RT,RB","4@0|RT@6|///@11|RB@16|725@21|",""
+"Convert Floating-Point Single-Precision from Unsigned Integer EVX-form","efscfui RT,RB","4@0|RT@6|///@11|RB@16|720@21|",""
+"Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form","efscfuf RT,RB","4@0|RT@6|///@11|RB@16|722@21|",""
+"Convert Floating-Point Single-Precision to Unsigned Integer EVX-form","efsctui RT,RB","4@0|RT@6|///@11|RB@16|724@21|",""
+"Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form","efsctsiz RT,RB","4@0|RT@6|///@11|RB@16|730@21|",""
+"Convert Floating-Point Single-Precision to Signed Fraction EVX-form","efsctsf RT,RB","4@0|RT@6|///@11|RB@16|727@21|",""
+"Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form","efsctuiz RT,RB","4@0|RT@6|///@11|RB@16|728@21|",""
+"Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form","efsctuf RT,RB","4@0|RT@6|///@11|RB@16|726@21|",""
+"Floating-Point Double-Precision Absolute Value EVX-form","efdabs RT,RA","4@0|RT@6|RA@11|///@16|740@21|",""
+"Floating-Point Double-Precision Negate EVX-form","efdneg RT,RA","4@0|RT@6|RA@11|///@16|742@21|",""
+"Floating-Point Double-Precision Negative Absolute Value EVX-form","efdnabs RT,RA","4@0|RT@6|RA@11|///@16|741@21|",""
+"Floating-Point Double-Precision Add EVX-form","efdadd RT,RA,RB","4@0|RT@6|RA@11|RB@16|736@21|",""
+"Floating-Point Double-Precision Multiply EVX-form","efdmul RT,RA,RB","4@0|RT@6|RA@11|RB@16|744@21|",""
+"Floating-Point Double-Precision Subtract EVX-form","efdsub RT,RA,RB","4@0|RT@6|RA@11|RB@16|737@21|",""
+"Floating-Point Double-Precision Divide EVX-form","efddiv RT,RA,RB","4@0|RT@6|RA@11|RB@16|745@21|",""
+"Floating-Point Double-Precision Compare Greater Than EVX-form","efdcmpgt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|748@21|",""
+"Floating-Point Double-Precision Compare Equal EVX-form","efdcmpeq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|750@21|",""
+"Floating-Point Double-Precision Compare Less Than EVX-form","efdcmplt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|749@21|",""
+"Floating-Point Double-Precision Test Greater Than EVX-form","efdtstgt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|764@21|",""
+"Floating-Point Double-Precision Test Less Than EVX-form","efdtstlt BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|765@21|",""
+"Convert Floating-Point Double-Precision from Signed Integer EVX-form","efdcfsi RT,RB","4@0|RT@6|///@11|RB@16|753@21|",""
+"Floating-Point Double-Precision Test Equal EVX-form","efdtsteq BF,RA,RB","4@0|BF@6|//@9|RA@11|RB@16|766@21|",""
+"Convert Floating-Point Double-Precision from Unsigned Integer EVX-form","efdcfui RT,RB","4@0|RT@6|///@11|RB@16|752@21|",""
+"Convert Floating-Point Double-Precision from Signed Integer Doubleword EVX-form","efdcfsid RT,RB","4@0|RT@6|///@11|RB@16|739@21|",""
+"Convert Floating-Point Double-Precision from Signed Fraction EVX-form","efdcfsf RT,RB","4@0|RT@6|///@11|RB@16|755@21|",""
+"Convert Floating-Point Double-Precision from Unsigned Fraction EVX-form","efdcfuf RT,RB","4@0|RT@6|///@11|RB@16|754@21|",""
+"Convert Floating-Point Double-Precision from Unsigned Integer Doubleword EVX-form","efdcfuid RT,RB","4@0|RT@6|///@11|RB@16|738@21|",""
+"Convert Floating-Point Double-Precision to Signed Integer EVX-form","efdctsi RT,RB","4@0|RT@6|///@11|RB@16|757@21|",""
+"Convert Floating-Point Double-Precision to Unsigned Integer EVX-form","efdctui RT,RB","4@0|RT@6|///@11|RB@16|756@21|",""
+"Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero EVX-form","efdctsidz RT,RB","4@0|RT@6|///@11|RB@16|747@21|",""
+"Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero EVX-form","efdctuidz RT,RB","4@0|RT@6|///@11|RB@16|746@21|",""
+"Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero EVX-form","efdctsiz RT,RB","4@0|RT@6|///@11|RB@16|762@21|",""
+"Convert Floating-Point Double-Precision to Signed Fraction EVX-form","efdctsf RT,RB","4@0|RT@6|///@11|RB@16|759@21|",""
+"Convert Floating-Point Double-Precision to Unsigned Fraction EVX-form","efdctuf RT,RB","4@0|RT@6|///@11|RB@16|758@21|",""
+"Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero EVX-form","efdctuiz RT,RB","4@0|RT@6|///@11|RB@16|760@21|",""
+"Floating-Point Double-Precision Convert from Single-Precision EVX-form","efdcfs RT,RB","4@0|RT@6|///@11|RB@16|751@21|",""
+"Floating-Point Single-Precision Convert from Double-Precision EVX-form","efscfd RT,RB","4@0|RT@6|///@11|RB@16|719@21|",""
+"Determine Leftmost Zero Byte X-form","dlmzb RA,RS,RB (Rc=0)|dlmzb. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|78@21|Rc@31|",""
+"Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form","macchw RT,RA,RB (OE=0 Rc=0)|macchw. RT,RA,RB (OE=0 Rc=1)|macchwo RT,RA,RB (OE=1 Rc=0)|macchwo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|172@22|Rc@31|",""
+"Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form","macchws RT,RA,RB (OE=0 Rc=0)|macchws. RT,RA,RB (OE=0 Rc=1)|macchwso RT,RA,RB (OE=1 Rc=0)|macchwso. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|236@22|Rc@31|",""
+"Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form","macchwu RT,RA,RB (OE=0 Rc=0)|macchwu. RT,RA,RB (OE=0 Rc=1)|macchwuo RT,RA,RB (OE=1 Rc=0)|macchwuo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|140@22|Rc@31|",""
+"Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form","macchwsu RT,RA,RB (OE=0 Rc=0)|macchwsu. RT,RA,RB (OE=0 Rc=1)|macchwsuo RT,RA,RB (OE=1 Rc=0)|macchwsuo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|204@22|Rc@31|",""
+"Multiply Accumulate High Halfword to Word Modulo Signed XO-form","machhw RT,RA,RB (OE=0 Rc=0)|machhw. RT,RA,RB (OE=0 Rc=1)|machhwo RT,RA,RB (OE=1 Rc=0)|machhwo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|44@22|Rc@31|",""
+"Multiply Accumulate High Halfword to Word Saturate Signed XO-form","machhws RT,RA,RB (OE=0 Rc=0)|machhws. RT,RA,RB (OE=0 Rc=1)|machhwso RT,RA,RB (OE=1 Rc=0)|machhwso. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|108@22|Rc@31|",""
+"Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form","machhwu RT,RA,RB (OE=0 Rc=0)|machhwu. RT,RA,RB (OE=0 Rc=1)|machhwuo RT,RA,RB (OE=1 Rc=0)|machhwuo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|12@22|Rc@31|",""
+"Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form","machhwsu RT,RA,RB (OE=0 Rc=0)|machhwsu. RT,RA,RB (OE=0 Rc=1)|machhwsuo RT,RA,RB (OE=1 Rc=0)|machhwsuo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|76@22|Rc@31|",""
+"Multiply Accumulate Low Halfword to Word Modulo Signed XO-form","maclhw RT,RA,RB (OE=0 Rc=0)|maclhw. RT,RA,RB (OE=0 Rc=1)|maclhwo RT,RA,RB (OE=1 Rc=0)|maclhwo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|428@22|Rc@31|",""
+"Multiply Accumulate Low Halfword to Word Saturate Signed XO-form","maclhws RT,RA,RB (OE=0 Rc=0)|maclhws. RT,RA,RB (OE=0 Rc=1)|maclhwso RT,RA,RB (OE=1 Rc=0)|maclhwso. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|492@22|Rc@31|",""
+"Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form","maclhwu RT,RA,RB (OE=0 Rc=0)|maclhwu. RT,RA,RB (OE=0 Rc=1)|maclhwuo RT,RA,RB (OE=1 Rc=0)|maclhwuo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|396@22|Rc@31|",""
+"Multiply Cross Halfword to Word Signed X-form","mulchw RT,RA,RB (Rc=0)|mulchw. RT,RA,RB (Rc=1)","4@0|RT@6|RA@11|RB@16|168@21|Rc@31|",""
+"Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form","maclhwsu RT,RA,RB (OE=0 Rc=0)|maclhwsu. RT,RA,RB (OE=0 Rc=1)|maclhwsuo RT,RA,RB (OE=1 Rc=0)|maclhwsuo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|460@22|Rc@31|",""
+"Multiply Cross Halfword to Word Unsigned X-form","mulchwu RT,RA,RB (Rc=0)|mulchwu. RT,RA,RB (Rc=1)","4@0|RT@6|RA@11|RB@16|136@21|Rc@31|",""
+"Multiply High Halfword to Word Signed X-form","mulhhw RT,RA,RB (Rc=0)|mulhhw. RT,RA,RB (Rc=1)","4@0|RT@6|RA@11|RB@16|40@21|Rc@31|",""
+"Multiply Low Halfword to Word Signed X-form","mullhw RT,RA,RB (Rc=0)|mullhw. RT,RA,RB (Rc=1)","4@0|RT@6|RA@11|RB@16|424@21|Rc@31|",""
+"Multiply High Halfword to Word Unsigned X-form","mulhhwu RT,RA,RB (Rc=0)|mulhhwu. RT,RA,RB (Rc=1)","4@0|RT@6|RA@11|RB@16|8@21|Rc@31|",""
+"Multiply Low Halfword to Word Unsigned X-form","mullhwu RT,RA,RB (Rc=0)|mullhwu. RT,RA,RB (Rc=1)","4@0|RT@6|RA@11|RB@16|392@21|Rc@31|",""
+"Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form","nmacchw RT,RA,RB (OE=0 Rc=0)|nmacchw. RT,RA,RB (OE=0 Rc=1)|nmacchwo RT,RA,RB (OE=1 Rc=0)|nmacchwo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|174@22|Rc@31|",""
+"Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form","nmacchws RT,RA,RB (OE=0 Rc=0)|nmacchws. RT,RA,RB (OE=0 Rc=1)|nmacchwso RT,RA,RB (OE=1 Rc=0)|nmacchwso. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|238@22|Rc@31|",""
+"Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form","nmachhw RT,RA,RB (OE=0 Rc=0)|nmachhw. RT,RA,RB (OE=0 Rc=1)|nmachhwo RT,RA,RB (OE=1 Rc=0)|nmachhwo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|46@22|Rc@31|",""
+"Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form","nmachhws RT,RA,RB (OE=0 Rc=0)|nmachhws. RT,RA,RB (OE=0 Rc=1)|nmachhwso RT,RA,RB (OE=1 Rc=0)|nmachhwso. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|110@22|Rc@31|",""
+"Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form","nmaclhw RT,RA,RB (OE=0 Rc=0)|nmaclhw. RT,RA,RB (OE=0 Rc=1)|nmaclhwo RT,RA,RB (OE=1 Rc=0)|nmaclhwo. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|430@22|Rc@31|",""
+"Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form","nmaclhws RT,RA,RB (OE=0 Rc=0)|nmaclhws. RT,RA,RB (OE=0 Rc=1)|nmaclhwso RT,RA,RB (OE=1 Rc=0)|nmaclhwso. RT,RA,RB (OE=1 Rc=1)","4@0|RT@6|RA@11|RB@16|OE@21|494@22|Rc@31|",""
+"Instruction Cache Block Invalidate X-form","icbi RA,RB","31@0|///@6|RA@11|RB@16|982@21|/@31|",""
+"Instruction Cache Block Touch X-form","icbt CT, RA, RB","31@0|/@6|CT@7|RA@11|RB@16|22@21|/@31|",""
+"Data Cache Block Allocate X-form","dcba RA,RB|[Category: Embedded]","31@0|///@6|RA@11|RB@16|758@21|/@31|",""
+"Data Cache Block Touch X-form","dcbt RA,RB,TH [Category: Server]|dcbt TH,RA,RB [Category: Embedded]","31@0|TH@6|RA@11|RB@16|278@21|/@31|",""
+"Data Cache Block Touch for Store X-form","dcbtst RA,RB,TH [Category: Server]|dcbtst TH,RA,RB [Category: Embedded]","31@0|TH@6|RA@11|RB@16|246@21|/@31|",""
+"Data Cache Block set to Zero X-form","dcbz RA,RB","31@0|///@6|RA@11|RB@16|1014@21|/@31|",""
+"Data Cache Block Store X-form","dcbst RA,RB","31@0|///@6|RA@11|RB@16|54@21|/@31|",""
+"Data Cache Block Flush X-form","dcbf RA,RB,L","31@0|///@6|L@9|RA@11|RB@16|86@21|/@31|",""
+"Instruction Synchronize XL-form","isync","19@0|///@6|///@11|///@16|150@21|/@31|",""
+"Load Byte And Reserve Indexed X-form [Category: Phased-In]","lbarx RT,RA,RB (EH=0)|lbarx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|52@21|EH@31|",""
+"Load Halfword And Reserve Indexed X-form [Category: Phased-In]","lharx RT,RA,RB (EH=0)|lharx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|116@21|EH@31|",""
+"Load Word And Reserve Indexed X-form","lwarx RT,RA,RB (EH=0)|lwarx RT,RA,RB (EH=0)|lwarx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|20@21|EH@31|",""
+"Store Byte Conditional Indexed X-form [Category: Phased-In]","stbcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|694@21|1@31|",""
+"Store Halfword Conditional Indexed X-form [Category: Phased-In]","sthcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|726@21|1@31|",""
+"Store Word Conditional Indexed X-form","stwcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|150@21|1@31|",""
+"Load Doubleword And Reserve Indexed X-form","ldarx RT,RA,RB (EH=0)|ldarx RT,RA,RB,EH","31@0|RT@6|RA@11|RB@16|84@21|EH@31|",""
+"Store Doubleword Conditional Indexed X-form","stdcx. RS,RA,RB","31@0|RS@6|RA@11|RB@16|214@21|1@31|",""
+"Load Quadword And Reserve Indexed X-form","lqarx RTp,RA,RB (EH=0)|lqarx RTp,RA,RB,EH","31@0|RTp@6|RA@11|RB@16|276@21|EH@31|",""
+"Store Quadword Conditional Indexed X-form","stqcx. RSp,RA,RB","31@0|RSp@6|RA@11|RB@16|182@21|1@31|",""
+"Synchronize X-form","sync L, E [Category: Elemental Memory Barri-|ers]","31@0|///@6|L@9|/@11|E@12|///@16|598@21|/@31|",""
+"Enforce In-order Execution of I/O X-form","eieio|[Category: Server]","31@0|///@6|///@11|///@16|854@21|/@31|",""
+"Memory Barrier X-form","mbar MO|[Category: Embedded]","31@0|MO@6|///@11|///@16|854@21|/@31|",""
+"Wait X-form","wait WC|[Category: Wait.Phased-In]","31@0|///@6|WC@9|///@11|///@16|62@21|/@31|",""
+"Transaction Begin X-form","tbegin. R","31@0|A@6|//@7|R@10|///@11|///@16|654@21|1@31|",""
+"Transaction End X-form","tend. A","31@0|A@6|//@7|/@10|///@11|///@16|686@21|1@31|",""
+"Transaction Abort X-form","tabort. RA","31@0|///@6|RA@11|///@16|910@21|1@31|",""
+"Transaction Abort Word Conditional X-form","tabortwc. TO,RA,RB","31@0|TO@6|RA@11|RB@16|782@21|1@31|",""
+"Transaction Abort Word Conditional Immediate X-form","tabortwci. TO,RA,SI","31@0|TO@6|RA@11|SI@16|846@21|1@31|",""
+"Transaction Abort Doubleword Conditional X-form","tabortdc. TO,RA,RB","31@0|TO@6|RA@11|RB@16|814@21|1@31|",""
+"Transaction Abort Doubleword Conditional Immediate X-form","tabortdci. TO,RA, SI","31@0|TO@6|RA@11|SI@16|878@21|1@31|",""
+"Transaction Suspend or Resume X-form","tsr. L","31@0|///@6|L@10|///@11|///@16|750@21|1@31|",""
+"Transaction Check X-form","tcheck BF","31@0|BF@6|//@9|///@11|///@16|718@21|/@31|",""
+"Move From Time Base XFX-form","mftb RT,TBR|[Category: Phased-Out]","31@0|RT@6|tbr@11|371@21|/@31|",""
+"Return from Event-Based Branch XL-form","rfebb S","19@0|///@6|///@11|///@16|S@20|146@21|/@31|",""
+"Load Byte with Decoration Indexed X-form","lbdx RT,RA,RB","31@0|RT@6|RA@11|RB@16|515@21|/@31|",""
+"Load Halfword with Decoration Indexed X-form","lhdx RT,RA,RB","31@0|RT@6|RA@11|RB@16|547@21|/@31|",""
+"Load Word with Decoration Indexed X-form","lwdx RT,RA,RB","31@0|RT@6|RA@11|RB@16|579@21|/@31|",""
+"Load Doubleword with Decoration Indexed X-form","lddx RT,RA,RB [Co-requisite category: 64-Bit]","31@0|RT@6|RA@11|RB@16|611@21|/@31|",""
+"Load Floating Doubleword with Decoration Indexed X-form","lfddx FRT,RA,RB [Co-requisite category: FP]","31@0|FRT@6|RA@11|RB@16|803@21|/@31|",""
+"Store Byte with Decoration Indexed X-form","stbdx RS,RA,RB","31@0|RS@6|RA@11|RB@16|643@21|/@31|",""
+"Store Halfword with Decoration Indexed X-form","sthdx RS,RA,RB","31@0|RS@6|RA@11|RB@16|675@21|/@31|",""
+"Store Word with Decoration Indexed X-form","stwdx RS,RA,RB","31@0|RS@6|RA@11|RB@16|707@21|/@31|",""
+"Store Doubleword with Decoration Indexed X-form","stddx RS,RA,RB [Co-requisite category: 64-Bit]","31@0|RS@6|RA@11|RB@16|739@21|/@31|",""
+"Store Floating Doubleword with Decoration Indexed X-form","stfddx FRS,RA,RB [Co-requisite category: FP]","31@0|FRS@6|RA@11|RB@16|931@21|/@31|",""
+"Decorated Storage Notify X-form","dsn RA,RB","31@0|///@6|RA@11|RB@16|483@21|/@31|",""
+"External Control In Word Indexed X-form","eciwx RT,RA,RB","31@0|RT@6|RA@11|RB@16|310@21|/@31|",""
+"External Control Out Word Indexed X-form","ecowx RS,RA,RB","31@0|RS@6|RA@11|RB@16|438@21|/@31|",""
+"System Call SC-form","sc LEV","17@0|///@6|///@11|//@16|LEV@20|//@27|1@30|/@31|",""
+"Return From Interrupt Doubleword XL-form","rfid","19@0|///@6|///@11|///@16|18@21|/@31|",""
+"Hypervisor Return From Interrupt Doubleword XL-form","hrfid","19@0|///@6|///@11|///@16|274@21|/@31|",""
+"Doze XL-form","doze","19@0|///@6|///@11|///@16|402@21|/@31|",""
+"Nap XL-form","nap","19@0|///@6|///@11|///@16|434@21|/@31|",""
+"Sleep XL-form","sleep","19@0|///@6|///@11|///@16|466@21|/@31|",""
+"Rip Van Winkle XL-form","rvwinkle","19@0|///@6|///@11|///@16|498@21|/@31|",""
+"Load Byte and Zero Caching Inhibited Indexed X-form","lbzcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|853@21|/@31|",""
+"Load Word and Zero Caching Inhibited Indexed X-form","lwzcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|789@21|/@31|",""
+"Load Halfword and Zero Caching Inhibited Indexed X-form","lhzcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|821@21|/@31|",""
+"Load Doubleword Caching Inhibited Indexed X-form","ldcix RT,RA,RB","31@0|RT@6|RA@11|RB@16|885@21|/@31|",""
+"Store Byte Caching Inhibited Indexed X-form","stbcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|981@21|/@31|",""
+"Store Word Caching Inhibited Indexed X-form","stwcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|917@21|/@31|",""
+"Store Halfword Caching Inhibited Indexed X-form","sthcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|949@21|/@31|",""
+"Store Doubleword Caching Inhibited Indexed X-form","stdcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|1013@21|/@31|",""
+"Transaction Reclaim X-form","treclaim. RA","31@0|///@6|RA@11|///@16|942@21|1@31|",""
+"Transaction Recheckpoint X-form","trechkpt.","31@0|///@6|///@11|///@16|1006@21|1@31|",""
+"Move To Special Purpose Register XFX-form","mtspr SPR,RS","31@0|RS@6|spr@11|467@21|/@31|",""
+"Move From Special Purpose Register XFX-form","mfspr RT,SPR","31@0|RT@6|spr@11|339@21|/@31|",""
+"Move To Machine State Register X-form","mtmsr RS,L","31@0|RS@6|///@11|L@15|///@16|146@21|/@31|",""
+"Move To Machine State Register Doubleword X-form","mtmsrd RS,L","31@0|RS@6|///@11|L@15|///@16|178@21|/@31|",""
+"Move From Machine State Register X-form","mfmsr RT","31@0|RT@6|///@11|///@16|83@21|/@31|",""
+"SLB Invalidate Entry X-form","slbie RB","31@0|///@6|///@11|RB@16|434@21|/@31|",""
+"SLB Invalidate All X-form","slbia IH","31@0|//@6|IH@8|///@11|///@16|498@21|/@31|",""
+"SLB Move To Entry X-form","slbmte RS,RB","31@0|RS@6|///@11|RB@16|402@21|/@31|",""
+"SLB Move From Entry VSID X-form","slbmfev RT,RB","31@0|RT@6|///@11|RB@16|851@21|/@31|",""
+"SLB Move From Entry ESID X-form","slbmfee RT,RB","31@0|RT@6|///@11|RB@16|915@21|/@31|",""
+"SLB Find Entry ESID X-form","slbfee. RT,RB","31@0|RT@6|///@11|RB@16|979@21|1@31|",""
+"Move To Segment Register X-form","mtsr SR,RS","31@0|RS@6|/@11|SR@12|///@16|210@21|/@31|",""
+"Move To Segment Register Indirect X-form","mtsrin RS,RB","31@0|RS@6|///@11|RB@16|242@21|/@31|",""
+"Move From Segment Register X-form","mfsr RT,SR","31@0|RT@6|/@11|SR@12|///@16|595@21|/@31|",""
+"Move From Segment Register Indirect X-form","mfsrin RT,RB","31@0|RT@6|///@11|RB@16|659@21|/@31|",""
+"TLB Invalidate Entry X-form","tlbie RB,RS","31@0|RS@6|///@11|RB@16|306@21|/@31|",""
+"TLB Invalidate Entry Local X-form","tlbiel RB","31@0|///@6|///@11|RB@16|274@21|/@31|",""
+"TLB Invalidate All X-form","tlbia","31@0|///@6|///@11|///@16|370@21|/@31|",""
+"TLB Synchronize X-form","tlbsync","31@0|///@6|///@11|///@16|566@21|/@31|",""
+"Message Send X-form","msgsnd RB","31@0|///@6|///@11|RB@16|206@21|/@31|",""
+"Message Clear X-form","msgclr RB","31@0|///@6|///@11|RB@16|238@21|/@31|",""
+"Message Send Privileged X-form","msgsndp RB","31@0|///@6|///@11|RB@16|142@21|/@31|",""
+"Message Clear Privileged X-form","msgclrp RB","31@0|///@6|///@11|RB@16|174@21|/@31|",""
+"Move To Thread Management Register XFX-form","mttmr TMR,RS","31@0|RS@6|tmr@11|494@21|/@31|",""
+"System Call SC-form","sc","17@0|///@6|///@11|///@16|///@20|//@27|1@30|/@31|",""
+"Return From Interrupt XL-form","rfi","19@0|///@6|///@11|///@16|50@21|/@31|",""
+"Return From Critical Interrupt XL-form","rfci","19@0|///@6|///@11|///@16|51@21|/@31|",""
+"Return From Debug Interrupt X-form","rfdi|[Category: Embedded.Enhanced Debug]","19@0|///@6|///@11|///@16|39@21|/@31|",""
+"Return From Machine Check Interrupt XL-form","rfmci","19@0|///@6|///@11|///@16|38@21|/@31|",""
+"Return From Guest Interrupt XL-form","rfgi [Category:Embedded.Hypervisor]","19@0|///@6|///@11|///@16|102@21|/@31|",""
+"Embedded Hypervisor Privilege XL-form","ehpriv OC [Category: Embedded.Hypervisor]","31@0|OC@6|270@21|/@31|",""
+"Move To Special Purpose Register XFX-form","mtspr SPR,RS","31@0|RS@6|spr@11|467@21|/@31|",""
+"Move From Special Purpose Register XFX-form","mfspr RT,SPR","31@0|RT@6|spr@11|339@21|/@31|",""
+"Move To Device Control Register XFX-form","mtdcr DCRN,RS|[Category: Embedded.Device Control]","31@0|RS@6|dcr@11|451@21|/@31|",""
+"Move To Device Control Register Indexed X-form","mtdcrx RA,RS|[Category: Embedded.Device Control]","31@0|RS@6|RA@11|///@16|387@21|/@31|",""
+"Move From Device Control Register XFX-form","mfdcr RT,DCRN|[Category: Embedded.Device Control]","31@0|RT@6|dcr@11|323@21|/@31|",""
+"Move From Device Control Register Indexed X-form","mfdcrx RT,RA|[Category: Embedded.Device Control]","31@0|RT@6|RA@11|///@16|259@21|/@31|",""
+"Move To Machine State Register X-form","mtmsr RS","31@0|RS@6|///@11|///@16|146@21|/@31|",""
+"Move From Machine State Register X-form","mfmsr RT","31@0|RT@6|///@11|///@16|83@21|/@31|",""
+"Write MSR External Enable X-form","wrtee RS","31@0|RS@6|///@11|///@16|131@21|/@31|",""
+"Write MSR External Enable Immediate X-form","wrteei E","31@0|///@6|///@11|E@16|///@17|163@21|/@31|",""
+"Load Byte by External Process ID Indexed X-form","lbepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|95@21|/@31|",""
+"Load Halfword by External Process ID Indexed X-form","lhepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|287@21|/@31|",""
+"Load Word by External Process ID Indexed X-form","lwepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|31@21|/@31|",""
+"Load Doubleword by External Process ID Indexed X-form","ldepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|29@21|/@31|",""
+"Store Byte by External Process ID Indexed X-form","stbepx RS,RA,RB","31@0|RS@6|RA@11|RB@16|223@21|/@31|",""
+"Store Halfword by External Process ID Indexed X-form","sthepx RS,RA,RB","31@0|RS@6|RA@11|RB@16|415@21|/@31|",""
+"Store Word by External Process ID Indexed X-form","stwepx RS,RA,RB","31@0|RS@6|RA@11|RB@16|159@21|/@31|",""
+"Store Doubleword by External Process ID Indexed X-form","stdepx RS,RA,RB","31@0|RS@6|RA@11|RB@16|157@21|/@31|",""
+"Data Cache Block Store by External PID X-form","dcbstep RA,RB","31@0|///@6|RA@11|RB@16|63@21|/@31|",""
+"Data Cache Block Touch by External PID X-form","dcbtep TH,RA,RB","31@0|TH@6|RA@11|RB@16|319@21|/@31|",""
+"Data Cache Block Flush by External PID X-form","dcbfep RA,RB,L","31@0|///@6|L@9|RA@11|RB@16|127@21|/@31|",""
+"Data Cache Block Touch for Store by External PID X-form","dcbtstep TH,RA,RB","31@0|TH@6|RA@11|RB@16|255@21|/@31|",""
+"Instruction Cache Block Invalidate by External PID X-form","icbiep RA,RB","31@0|///@6|RA@11|RB@16|991@21|/@31|",""
+"Data Cache Block set to Zero by External PID X-form","dcbzep RA,RB","31@0|///@6|RA@11|RB@16|1023@21|/@31|",""
+"Load Floating-Point Double by External Process ID Indexed X-form","lfdepx FRT,RA,RB","31@0|FRT@6|RA@11|RB@16|607@21|/@31|",""
+"Store Floating-Point Double by External Process ID Indexed X-form","stfdepx FRS,RA,RB","31@0|FRS@6|RA@11|RB@16|735@21|/@31|",""
+"Vector Load Doubleword into Doubleword by External Process ID Indexed EVX-form","evlddepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|799@21|/@31|",""
+"Vector Store Doubleword into Doubleword by External Process ID Indexed EVX-form","evstddepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|927@21|/@31|",""
+"Load Vector by External Process ID Indexed X-form","lvepx VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|295@21|/@31|",""
+"Load Vector by External Process ID Indexed LRU X-form","lvepxl VRT,RA,RB","31@0|VRT@6|RA@11|RB@16|263@21|/@31|",""
+"Store Vector by External Process ID Indexed X-form","stvepx VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|807@21|/@31|",""
+"Store Vector by External Process ID Indexed LRU X-form","stvepxl VRS,RA,RB","31@0|VRS@6|RA@11|RB@16|775@21|/@31|",""
+"Data Cache Block Invalidate X-form","dcbi RA,RB","31@0|///@6|RA@11|RB@16|470@21|/@31|",""
+"Data Cache Block Lock Query X-form","dcblq. CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|422@21|1@31|",""
+"Instruction Cache Block Lock Query X-form","icblq. CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|198@21|1@31|",""
+"Data Cache Block Touch and Lock Set X-form","dcbtls CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|166@21|/@31|",""
+"Data Cache Block Touch for Store and Lock Set X-form","dcbtstls CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|134@21|/@31|",""
+"Instruction Cache Block Touch and Lock Set X-form","icbtls CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|486@21|/@31|",""
+"Instruction Cache Block Lock Clear X-form","icblc CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|230@21|/@31|",""
+"Data Cache Block Lock Clear X-form","dcblc CT,RA,RB","31@0|/@6|CT@7|RA@11|RB@16|390@21|/@31|",""
+"TLB Invalidate Virtual Address Indexed X-form","tlbivax RA,RB","31@0|///@6|RA@11|RB@16|786@21|/@31|",""
+"TLB Invalidate Local Indexed X-form","tlbilx RA,RB [Category: Embedded.Phased In]]","31@0|///@6|T@9|RA@11|RB@16|18@21|/@31|",""
+"TLB Search Indexed X-form","tlbsx RA,RB","31@0|///@6|RA@11|RB@16|914@21|/@31|",""
+"TLB Search and Reserve Indexed X-form","tlbsrx. RA,RB [Category: Embedded.TLB Write|Conditional]","31@0|///@6|RA@11|RB@16|850@21|1@31|",""
+"TLB Read Entry X-form","tlbre","31@0|///@6|///@11|///@16|946@21|/@31|",""
+"TLB Synchronize X-form","tlbsync","31@0|///@6|///@11|///@16|566@21|/@31|",""
+"TLB Write Entry X-form","tlbwe","31@0|///@6|///@11|///@16|978@21|/@31|",""
+"Debugger Notify Halt XFX-form","dnh DUI,DUIS","19@0|DUI@6|DUIS@11|198@21|/@31|",""
+"Message Send X-form","msgsnd RB","31@0|///@6|///@11|RB@16|206@21|/@31|",""
+"Message Clear X-form","msgclr RB","31@0|///@6|///@11|RB@16|238@21|/@31|",""
+"Data Cache Invalidate X-form","dci CT","31@0|/@6|CT@7|///@11|///@16|454@21|/@31|",""
+"Instruction Cache Invalidate X-form","ici CT","31@0|/@6|CT@7|///@11|///@16|966@21|/@31|",""
+"Data Cache Read X-form","dcread RT,RA,RB","31@0|RT@6|RA@11|RB@16|486@21|/@31|",""
+"Instruction Cache Read X-form","icread RA,RB","31@0|///@6|RA@11|RB@16|998@21|/@31|",""
+"Move From Performance Monitor Register XFX-form","mfpmr RT,PMRN","31@0|RT@6|pmrn@11|334@21|/@31|",""
+"Move To Performance Monitor Register XFX-form","mtpmr PMRN,RS","31@0|RS@6|pmrn@11|462@21|/@31|",""
+"Branch [and Link] BD24-form","e_b target_addr (LK=0)|e_bl target_addr (LK=1)","30@0|0@6|BD24@7|LK@31|",""
+"Branch Conditional [and Link] BD15-form","e_bc BO32,BI32,target_addr (LK=0)|e_bcl BO32,BI32,target_addr (LK=1)","30@0|8@6|BO32@10|BI32@12|BD15@16|LK@31|",""
+"Branch [and Link] BD8-form","se_b target_addr (LK=0)|se_bl target_addr (LK=1)","58@0|0@6|LK@7|BD8@8@15|",""
+"Branch Conditional Short Form BD8-form","se_bc BO16,BI16,target_addr","28@0|BO16@5|BI16@6|BD8@8@15|",""
+"Branch to Count Register [and Link] C-form","se_bctr (LK=0)|se_bctrl (LK=1)","03@0|LK@15|",""
+"Branch to Link Register [and Link] C-form","se_blr (LK=0)|se_blrl (LK=1)","02@0|LK@15|",""
+"Illegal C-form","se_illegal","0@0@15|",""
+"Return From Machine Check Interrupt C-form","se_rfmci","11@0@15|",""
+"Return From Critical Interrupt C-form","se_rfci","09@0@15|",""
+"Return From Interrupt C-form","se_rfi","08@0@15|",""
+"Return From Debug Interrupt C-form","se_rfdi","10@0@15|",""
+"Return From Guest Interrupt C-form","se_rfgi i","12@0@15|",""
+"Condition Register AND XL-form","e_crand BT,BA,BB","31@0|BT@6|BA@11|BB@16|257@21|/@31|",""
+"Condition Register Equivalent XL-form","e_creqv BT,BA,BB","31@0|BT@6|BA@11|BB@16|289@21|/@31|",""
+"Condition Register AND with Complement XL-form","e_crandc BT,BA,BB","31@0|BT@6|BA@11|BB@16|129@21|/@31|",""
+"Condition Register NAND XL-form","e_crnand BT,BA,BB","31@0|BT@6|BA@11|BB@16|225@21|/@31|",""
+"Condition Register NOR XL-form","e_crnor BT,BA,BB","31@0|BT@6|BA@11|BB@16|33@21|/@31|",""
+"Condition Register OR with Complement XL-form","e_crorc BT,BA,BB","31@0|BT@6|BA@11|BB@16|417@21|/@31|",""
+"Move CR Field XL-form","e_mcrf BF,BFA","31@0|BF@6|//@9|BFA@11|///@14|///@16|16@21|/@31|",""
+"Condition Register OR XL-form","e_cror BT,BA,BB","31@0|BT@6|BA@11|BB@16|449@21|/@31|",""
+"Condition Register XOR XL-form","e_crxor BT,BA,BB","31@0|BT@6|BA@11|BB@16|193@21|/@31|",""
+"Load Byte and Zero D-form","e_lbz RT,D(RA)","12@0|RT@6|RA@11|D@16|",""
+"Load Byte and Zero with Update D8-form","e_lbzu RT,D8(RA)","06@0|RT@6|RA@11|0@16|D8@24|",""
+"Load Halfword and Zero D-form","e_lhz RT,D(RA)","22@0|RT@6|RA@11|D@16|",""
+"Load Byte and Zero Short Form SD4-form","se_lbz RZ,SD4(RX)","08@0|SD4@4|RZ@8|RX@12@15|",""
+"Load Halfword Algebraic D-form","e_lha RT,D(RA)","14@0|RT@6|RA@11|D@16|",""
+"Load Halfword and Zero Short Form SD4-form","se_lhz RZ,SD4(RX)","10@0|SD4@4|RZ@8|RX@12@15|",""
+"Load Halfword Algebraic with Update D8-form","e_lhau RT,D8(RA)","06@0|RT@6|RA@11|03@16|D8@24|",""
+"Load Word and Zero D-form","e_lwz RT,D(RA)","20@0|RT@6|RA@11|D@16|",""
+"Load Halfword and Zero with Update D8-form","e_lhzu RT,D8(RA)","06@0|RT@6|RA@11|01@16|D8@24|",""
+"Load Word and Zero Short Form SD4-form","se_lwz RZ,SD4(RX)","12@0|SD4@4|RZ@8|RX@12@15|",""
+"Load Word and Zero with Update D8-form","e_lwzu RT,D8(RA)","06@0|RT@6|RA@11|02@16|D8@24|",""
+"Store Byte D-form","e_stb RS,D(RA)","13@0|RS@6|RA@11|D@16|",""
+"Store Byte Short Form SD4-form","se_stb RZ,SD4(RX)","09@0|SD4@4|RZ@8|RX@12@15|",""
+"Store Byte with Update D8-form","e_stbu RS,D8(RA)","06@0|RS@6|RA@11|04@16|D8@24|",""
+"Store Halfword D-form","e_sth RS,D(RA)","23@0|RS@6|RA@11|D@16|",""
+"Store Halfword with Update D8-form","e_sthu RS,D8(RA)","06@0|RS@6|RA@11|05@16|D8@24|",""
+"Store Halfword Short Form SD4-form","se_sth RZ,SD4(RX)","11@0|SD4@4|RZ@8|RX@12@15|",""
+"Store Word D-form","e_stw RS,D(RA)","21@0|RS@6|RA@11|D@16|",""
+"Store Word with Update D8-form","e_stwu RS,D8(RA)","06@0|RS@6|RA@11|06@16|D8@24|",""
+"Store Word Short Form SD4-form","se_stw RZ,SD4(RX)","13@0|SD4@4|RZ@8|RX@12@15|",""
+"Load Multiple Word D8-form","e_lmw RT,D8(RA)","06@0|RT@6|RA@11|08@16|D8@24|",""
+"Store Multiple Word D8-form","e_stmw RS,D8(RA)","06@0|RS@6|RA@11|9@16|D8@24|",""
+"Add Short Form RR-form","se_add RX,RY","01@0|0@6|RY@8|RX@12@15|",""
+"Add (2 operand) Immediate and Record I16A-form","e_add2i. RA,si","28@0|si@6|RA@11|17@16|si@21|",""
+"Add Scaled Immediate SCI8-form","e_addi RT,RA,sci8 (Rc=0)|e_addi. RT,RA,sci8 (Rc=1)","06@0|RT@6|RA@11|8@16|Rc@20|F@21|SCL@22|UI8@24|",""
+"Add Immediate D-form","e_add16i RT,RA,SI","07@0|RT@6|RA@11|SI@16|",""
+"Add (2 operand) Immediate Shifted I16A-form","e_add2is RA,si","28@0|si@6|RA@11|18@16|si@21|",""
+"Add Immediate Short Form OIM5-form","se_addi RX,oimm","08@0|0@6|OIM5@7|RX@12@15|",""
+"Add Scaled Immediate Carrying SCI8-form","e_addic RT,RA,sci8 (Rc=0)|e_addic. RT,RA,sci8 (Rc=1)","06@0|RT@6|RA@11|9@16|Rc@20|F@21|SCL@22|UI8@24|",""
+"Subtract RR-form","se_sub RX,RY","1@0|2@6|RY@8|RX@12@15|",""
+"Subtract From Scaled Immediate Carrying SCI8-form","e_subfic RT,RA,sci8 (Rc=0)|e_subfic. RT,RA,sci8 (Rc=1)","06@0|RT@6|RA@11|11@16|Rc@20|F@21|SCL@22|UI8@24|",""
+"Subtract From Short Form RR-form","se_subf RX,RY","01@0|3@6|RY@8|RX@12@15|",""
+"Subtract Immediate OIM5-form","se_subi RX,oimm (Rc=0)|se_subi. RX,oimm (Rc=1)","09@0|Rc@6|OIM5@7|RX@12@15|",""
+"Multiply Low Scaled Immediate SCI8-form","e_mulli RT,RA,sci8","06@0|RT@6|RA@11|20@16|F@21|SCL@22|UI8@24|",""
+"Multiply Low Word Short Form RR-form","se_mullw RX,RY","01@0|1@6|RY@8|RX@12@15|",""
+"Multiply (2 operand) Low Immediate I16A-form","e_mull2i RA,si","28@0|si@6|RA@11|20@16|si@21|",""
+"Negate Short Form R-form","se_neg RX","0@0|03@6|RX@12@15|",""
+"Bit Test Immediate IM5-form","se_btsti RX,UI5","25@0|1@6|UI5@7|RX@12@15|",""
+"Compare Immediate Word I16A-form","e_cmp16i RA,si","28@0|si@6|RA@11|19@16|si@21|",""
+"Compare Scaled Immediate Word SCI8-form","e_cmpi BF32,RA,sci8","06@0|000@6|BF32@9|RA@11|21@16|F@21|SCL@22|UI8@24|",""
+"Compare Immediate Word Short Form IM5-form","se_cmpi RX,UI5","10@0|1@6|UI5@7|RX@12@15|",""
+"Compare Word RR-form","se_cmp RX,RY","3@0|0@6|RY@8|RX@12@15|",""
+"Compare Logical Immediate Word I16A-form","e_cmpl16i RA,ui","28@0|ui@6|RA@11|21@16|ui@21|",""
+"Compare Logical Scaled Immediate Word SCI8-form","e_cmpli BF32,RA,sci8","06@0|001@6|BF32@9|RA@11|21@16|F@21|SCL@22|UI8@24|",""
+"Compare Logical Immediate Word OIM5-form","se_cmpli RX,oimm","08@0|1@6|OIM5@7|RX@12@15|",""
+"Compare Logical Word RR-form","se_cmpl RX,RY","3@0|1@6|RY@8|RX@12@15|",""
+"Compare Halfword X-form","e_cmph BF,RA,RB","31@0|BF@6|0@9|RA@11|RB@16|14@21|/@31|",""
+"Compare Halfword Short Form RR-form","se_cmph RX,RY","3@0|2@6|RY@8|RX@12@15|",""
+"Compare Halfword Logical X-form","e_cmphl BF,RA,RB","31@0|BF@6|0@9|RA@11|RB@16|46@21|/@31|",""
+"Compare Halfword Immediate I16A-form","e_cmph16i RA,si","28@0|si@6|RA@11|22@16|si@21|",""
+"Compare Halfword Logical Short Form RR-form","se_cmphl RX,RY","3@0|3@6|RY@8|RX@12@15|",""
+"Compare Halfword Logical Immediate I16A-form","e_cmphl16i RA,ui","28@0|ui@6|RA@11|23@16|ui@21|",""
+"AND (two operand) Immediate I16L-form","e_and2i. RT,ui","28@0|RT@6|ui@11|25@16|ui@21|",""
+"AND Scaled Immediate SCI8-form","e_andi RA,RS,sci8 (Rc=0)|e_andi. RA,RS,sci8 (Rc=1)","06@0|RS@6|RA@11|12@16|Rc@20|F@21|SCL@22|UI8@24|",""
+"AND (2 operand) Immediate Shifted I16L-form","e_and2is. RT,ui","28@0|RT@6|ui@11|29@16|ui@21|",""
+"AND Immediate Short Form IM5-form","se_andi RX,UI5","11@0|1@6|UI5@7|RX@12@15|",""
+"OR (two operand) Immediate I16L-form","e_or2i RT,ui","28@0|RT@6|ui@11|24@16|ui@21|",""
+"OR Scaled Immediate SCI8-form","e_ori RA,RS,sci8 (Rc=0)|e_ori. RA,RS,sci8 (Rc=1)","06@0|RS@6|RA@11|13@16|Rc@20|F@21|SCL@22|UI8@24|",""
+"AND Short Form RR-form","se_and RX,RY (Rc=0)|se_and. RX,RY (Rc=1)","17@0|1@6|Rc@7|RY@8|RX@12@15|",""
+"OR (2 operand) Immediate Shifted I16L-form","e_or2is RT,ui","28@0|RT@6|ui@11|26@16|ui@21|",""
+"XOR Scaled Immediate SCI8-form","e_xori RA,RS,sci8 (Rc=0)|e_xori. RA,RS,sci8 (Rc=1)","06@0|RS@6|RA@11|14@16|Rc@20|F@21|SCL@22|UI8@24|",""
+"AND with Complement Short Form RR-form","se_andc RX,RY","17@0|1@6|RY@8|RX@12@15|",""
+"OR Short Form RR-form","se_or RX,RY","17@0|0@6|RY@8|RX@12@15|",""
+"Bit Clear Immediate IM5-form","se_bclri RX,UI5","24@0|0@6|UI5@7|RX@12@15|",""
+"Bit Mask Generate Immediate IM5-form","se_bmaski RX,UI5","11@0|0@6|UI5@7|RX@12@15|",""
+"NOT Short Form R-form","se_not RX","0@0|02@6|RX@12@15|",""
+"Bit Generate Immediate IM5-form","se_bgeni RX,UI5","24@0|1@6|UI5@7|RX@12@15|",""
+"Bit Set Immediate IM5-form","se_bseti RX,UI5","25@0|0@6|UI5@7|RX@12@15|",""
+"Extend Sign Byte Short Form R-form","se_extsb RX","0@0|13@6|RX@12@15|",""
+"Extend Zero Byte R-form","se_extzb RX","0@0|12@6|RX@12@15|",""
+"Load Immediate LI20-form","e_li RT,LI20","28@0|RT@6|li20@11|0@16|li20@17|li20@21|",""
+"Load Immediate Shifted I16L-form","e_lis RT,ui","28@0|RT@6|ui@11|28@16|ui@21|",""
+"Extend Sign Halfword Short Form R-form","se_extsh RX","0@0|15@6|RX@12@15|",""
+"Extend Zero Halfword R-form","se_extzh RX","0@0|14@6|RX@12@15|",""
+"Load Immediate Short Form IM7-form","se_li RX,UI7","09@0|UI7@5|RX@12@15|",""
+"Move from Alternate Register RR-form","se_mfar RX,ARY","0@0|3@6|ARY@8|RX@12@15|",""
+"Move To Alternate Register RR-form","se_mtar ARX,RY","0@0|2@6|RY@8|ARX@12@15|",""
+"Move Register RR-form","se_mr RX,RY","0@0|1@6|RY@8|RX@12@15|",""
+"Rotate Left Word X-form","e_rlw RA,RS,RB (Rc=0)|e_rlw. RA,RS,RB (Rc=1)","31@0|RS@6|RA@11|RB@16|280@21|Rc@31|",""
+"Rotate Left Word Immediate then Mask Insert M-form","e_rlwimi RA,RS,SH,MB,ME","29@0|RS@6|RA@11|SH@16|MB@21|ME@26|0@31|",""
+"Rotate Left Word Immediate X-form","e_rlwi RA,RS,SH (Rc=0)|e_rlwi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|SH@16|312@21|Rc@31|",""
+"Rotate Left Word Immediate then AND with Mask M-form","e_rlwinm RA,RS,SH,MB,ME","29@0|RS@6|RA@11|SH@16|MB@21|ME@26|1@31|",""
+"Shift Left Word Immediate X-form","e_slwi RA,RS,SH (Rc=0)|e_slwi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|SH@16|56@21|Rc@31|",""
+"Shift Left Word RR-form","se_slw RX,RY","16@0|2@6|RY@8|RX@12@15|",""
+"Shift Left Word Immediate Short Form IM5-form","se_slwi RX,UI5","27@0|0@6|UI5@7|RX@12@15|",""
+"Shift Right Algebraic Word Immediate IM5-form","se_srawi RX,UI5","26@0|1@6|UI5@7|RX@12@15|",""
+"Shift Right Algebraic Word RR-form","se_sraw RX,RY","16@0|1@6|RY@8|RX@12@15|",""
+"Shift Right Word Immediate Short Form IM5-form","se_srwi RX,UI5","26@0|0@6|UI5@7|RX@12@15|",""
+"Shift Right Word Immediate X-form","e_srwi RA,RS,SH (Rc=0)|e_srwi. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|SH@16|568@21|Rc@31|",""
+"Shift Right Word RR-form","se_srw RX,RY","16@0|0@6|RY@8|RX@12@15|",""
+"Move From Count Register R-form","se_mfctr RX","0@0|10@6|RX@12@15|",""
+"Move To Count Register R-form","se_mtctr RX","0@0|11@6|RX@12@15|",""
+"Move From Link Register R-form","se_mflr RX","0@0|8@6|RX@12@15|",""
+"Move To Link Register R-form","se_mtlr RX","0@0|9@6|RX@12@15|",""
+"Instruction Synchronize C-form","se_isync","01@0@15|",""

ppc64/ppc64asm/decode.go

diff --git a/ppc64/ppc64asm/decode.go b/ppc64/ppc64asm/decode.go
new file mode 100644
index 0000000..a40b8b7
--- /dev/null
+++ b/ppc64/ppc64asm/decode.go
@@ -0,0 +1,174 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"encoding/binary"
+	"fmt"
+	"log"
+)
+
+const debugDecode = false
+
+// instFormat is a decoding rule for one specific instruction form.
+// a uint32 instruction ins matches the rule if ins&Mask == Value
+// DontCare bits should be zero, but the machine might not reject
+// ones in those bits, they are mainly reserved for future expansion
+// of the instruction set.
+// The Args are stored in the same order as the instruction manual.
+type instFormat struct {
+	Op       Op
+	Mask     uint32
+	Value    uint32
+	DontCare uint32
+	Args     [5]*argField
+}
+
+// argField indicate how to decode an argument to an instruction.
+// First parse the value from the BitFields, shift it left by Shift
+// bits to get the actual numerical value.
+type argField struct {
+	Type  ArgType
+	Shift uint8
+	BitFields
+}
+
+// Parse parses the Arg out from the given binary instruction i.
+func (a argField) Parse(i uint32) Arg {
+	switch a.Type {
+	default:
+		return nil
+	case TypeUnknown:
+		return nil
+	case TypeReg:
+		return R0 + Reg(a.BitFields.Parse(i))
+	case TypeCondRegBit:
+		return Cond0LT + CondReg(a.BitFields.Parse(i))
+	case TypeCondRegField:
+		return CR0 + CondReg(a.BitFields.Parse(i))
+	case TypeFPReg:
+		return F0 + Reg(a.BitFields.Parse(i))
+	case TypeVecReg:
+		return V0 + Reg(a.BitFields.Parse(i))
+	case TypeSpReg:
+		return SpReg(a.BitFields.Parse(i))
+	case TypeImmSigned:
+		return Imm(a.BitFields.ParseSigned(i) << a.Shift)
+	case TypeImmUnsigned:
+		return Imm(a.BitFields.Parse(i) << a.Shift)
+	case TypePCRel:
+		return PCRel(a.BitFields.ParseSigned(i) << a.Shift)
+	case TypeLabel:
+		return Label(a.BitFields.ParseSigned(i) << a.Shift)
+	case TypeOffset:
+		return Offset(a.BitFields.ParseSigned(i) << a.Shift)
+	}
+}
+
+type ArgType int8
+
+const (
+	TypeUnknown      ArgType = iota
+	TypePCRel                // PC-relative address
+	TypeLabel                // absolute address
+	TypeReg                  // integer register
+	TypeCondRegBit           // conditional register bit (0-31)
+	TypeCondRegField         // conditional register field (0-7)
+	TypeFPReg                // floating point register
+	TypeVecReg               // vector register
+	TypeSpReg                // special register (depends on Op)
+	TypeImmSigned            // signed immediate
+	TypeImmUnsigned          // unsigned immediate/flag/mask, this is the catch-all type
+	TypeOffset               // signed offset in load/store
+	TypeLast                 // must be the last one
+)
+
+func (t ArgType) String() string {
+	switch t {
+	default:
+		return fmt.Sprintf("ArgType(%d)", int(t))
+	case TypeUnknown:
+		return "Unknown"
+	case TypeReg:
+		return "Reg"
+	case TypeCondRegBit:
+		return "CondRegBit"
+	case TypeCondRegField:
+		return "CondRegField"
+	case TypeFPReg:
+		return "FPReg"
+	case TypeVecReg:
+		return "VecReg"
+	case TypeSpReg:
+		return "SpReg"
+	case TypeImmSigned:
+		return "ImmSigned"
+	case TypeImmUnsigned:
+		return "ImmUnsigned"
+	case TypePCRel:
+		return "PCRel"
+	case TypeLabel:
+		return "Label"
+	case TypeOffset:
+		return "Offset"
+	}
+}
+
+func (t ArgType) GoString() string {
+	s := t.String()
+	if t > 0 && t < TypeLast {
+		return "Type" + s
+	}
+	return s
+}
+
+var (
+	// Errors
+	errShort   = fmt.Errorf("truncated instruction")
+	errUnknown = fmt.Errorf("unknown instruction")
+)
+
+var decoderCover []bool
+
+// Decode decodes the leading bytes in src as a single instruction using
+// byte order ord.
+func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
+	if len(src) < 4 {
+		return inst, errShort
+	}
+	if decoderCover == nil {
+		decoderCover = make([]bool, len(instFormats))
+	}
+	inst.Len = 4 // only 4-byte instructions are supported
+	ui := ord.Uint32(src[:inst.Len])
+	inst.Enc = ui
+	for i, iform := range instFormats {
+		if ui&iform.Mask != iform.Value {
+			continue
+		}
+		if ui&iform.DontCare != 0 {
+			if debugDecode {
+				log.Printf("Decode(%#x): unused bit is 1 for Op %s", ui, iform.Op)
+			}
+			// to match GNU objdump (libopcodes), we ignore don't care bits
+		}
+		for i, argfield := range iform.Args {
+			if argfield == nil {
+				break
+			}
+			inst.Args[i] = argfield.Parse(ui)
+		}
+		inst.Op = iform.Op
+		if debugDecode {
+			log.Printf("%#x: search entry %d", ui, i)
+			continue
+		}
+		break
+	}
+	if inst.Op == 0 {
+		return inst, errUnknown
+	}
+	return inst, nil
+}

ppc64/ppc64asm/decode_test.go

diff --git a/ppc64/ppc64asm/decode_test.go b/ppc64/ppc64asm/decode_test.go
new file mode 100644
index 0000000..735cb2f
--- /dev/null
+++ b/ppc64/ppc64asm/decode_test.go
@@ -0,0 +1,64 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"encoding/binary"
+	"encoding/hex"
+	"io/ioutil"
+	"strings"
+	"testing"
+)
+
+func TestDecode(t *testing.T) {
+	data, err := ioutil.ReadFile("testdata/decode.txt")
+	if err != nil {
+		t.Fatal(err)
+	}
+	all := string(data)
+	for strings.Contains(all, "\t\t") {
+		all = strings.Replace(all, "\t\t", "\t", -1)
+	}
+	for _, line := range strings.Split(all, "\n") {
+		line = strings.TrimSpace(line)
+		if line == "" || strings.HasPrefix(line, "#") {
+			continue
+		}
+		f := strings.SplitN(line, "\t", 3)
+		i := strings.Index(f[0], "|")
+		if i < 0 {
+			t.Errorf("parsing %q: missing | separator", f[0])
+			continue
+		}
+		if i%2 != 0 {
+			t.Errorf("parsing %q: misaligned | separator", f[0])
+		}
+		size := i / 2
+		code, err := hex.DecodeString(f[0][:i] + f[0][i+1:])
+		if err != nil {
+			t.Errorf("parsing %q: %v", f[0], err)
+			continue
+		}
+		syntax, asm := f[1], f[2]
+		inst, err := Decode(code, binary.BigEndian)
+		var out string
+		if err != nil {
+			out = "error: " + err.Error()
+		} else {
+			switch syntax {
+			case "gnu":
+				out = GNUSyntax(inst)
+			//case "plan9":
+			//	out = plan9Syntax(inst, 0, nil, nil)
+			default:
+				t.Errorf("unknown syntax %q", syntax)
+				continue
+			}
+		}
+		if out != asm || inst.Len != size {
+			t.Errorf("Decode(%s) [%s] = %s want %s", f[0], syntax, out, asm)
+		}
+	}
+}

ppc64/ppc64asm/doc.go

diff --git a/ppc64/ppc64asm/doc.go b/ppc64/ppc64asm/doc.go
new file mode 100644
index 0000000..5f4ef7d
--- /dev/null
+++ b/ppc64/ppc64asm/doc.go
@@ -0,0 +1,6 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Package ppc64asm implements decoding of 64-bit PowerPC machine code.
+package ppc64asm

ppc64/ppc64asm/ext_test.go

diff --git a/ppc64/ppc64asm/ext_test.go b/ppc64/ppc64asm/ext_test.go
new file mode 100644
index 0000000..443326c
--- /dev/null
+++ b/ppc64/ppc64asm/ext_test.go
@@ -0,0 +1,535 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Support for testing against external disassembler program.
+// Copied and simplified from rsc.io/arm/armasm/ext_test.go.
+
+package ppc64asm
+
+import (
+	"bufio"
+	"bytes"
+	"encoding/binary"
+	"encoding/hex"
+	"flag"
+	"fmt"
+	"io/ioutil"
+	"log"
+	"math/rand"
+	"os"
+	"os/exec"
+	"regexp"
+	"runtime"
+	"strings"
+	"testing"
+	"time"
+)
+
+var (
+	printTests = flag.Bool("printtests", false, "print test cases that exercise new code paths")
+	dumpTest   = flag.Bool("dump", false, "dump all encodings")
+	mismatch   = flag.Bool("mismatch", false, "log allowed mismatches")
+	longTest   = flag.Bool("long", false, "long test")
+	keep       = flag.Bool("keep", false, "keep object files around")
+	debug      = false
+)
+
+// A ExtInst represents a single decoded instruction parsed
+// from an external disassembler's output.
+type ExtInst struct {
+	addr uint32
+	enc  [4]byte
+	nenc int
+	text string
+}
+
+func (r ExtInst) String() string {
+	return fmt.Sprintf("%#x: % x: %s", r.addr, r.enc, r.text)
+}
+
+// An ExtDis is a connection between an external disassembler and a test.
+type ExtDis struct {
+	Dec      chan ExtInst
+	File     *os.File
+	Size     int
+	KeepFile bool
+	Cmd      *exec.Cmd
+}
+
+// Run runs the given command - the external disassembler - and returns
+// a buffered reader of its standard output.
+func (ext *ExtDis) Run(cmd ...string) (*bufio.Reader, error) {
+	if *keep {
+		log.Printf("%s\n", strings.Join(cmd, " "))
+	}
+	ext.Cmd = exec.Command(cmd[0], cmd[1:]...)
+	out, err := ext.Cmd.StdoutPipe()
+	if err != nil {
+		return nil, fmt.Errorf("stdoutpipe: %v", err)
+	}
+	if err := ext.Cmd.Start(); err != nil {
+		return nil, fmt.Errorf("exec: %v", err)
+	}
+
+	b := bufio.NewReaderSize(out, 1<<20)
+	return b, nil
+}
+
+// Wait waits for the command started with Run to exit.
+func (ext *ExtDis) Wait() error {
+	return ext.Cmd.Wait()
+}
+
+// testExtDis tests a set of byte sequences against an external disassembler.
+// The disassembler is expected to produce the given syntax and be run
+// in the given architecture mode (16, 32, or 64-bit).
+// The extdis function must start the external disassembler
+// and then parse its output, sending the parsed instructions on ext.Dec.
+// The generate function calls its argument f once for each byte sequence
+// to be tested. The generate function itself will be called twice, and it must
+// make the same sequence of calls to f each time.
+// When a disassembly does not match the internal decoding,
+// allowedMismatch determines whether this mismatch should be
+// allowed, or else considered an error.
+func testExtDis(
+	t *testing.T,
+	syntax string,
+	extdis func(ext *ExtDis) error,
+	generate func(f func([]byte)),
+	allowedMismatch func(text string, size int, inst *Inst, dec ExtInst) bool,
+) {
+	start := time.Now()
+	ext := &ExtDis{
+		Dec: make(chan ExtInst),
+	}
+	errc := make(chan error)
+
+	// First pass: write instructions to input file for external disassembler.
+	file, f, size, err := writeInst(generate)
+	if err != nil {
+		t.Fatal(err)
+	}
+	ext.Size = size
+	ext.File = f
+	defer func() {
+		f.Close()
+		if !*keep {
+			os.Remove(file)
+		}
+	}()
+
+	// Second pass: compare disassembly against our decodings.
+	var (
+		totalTests  = 0
+		totalSkips  = 0
+		totalErrors = 0
+
+		errors = make([]string, 0, 100) // sampled errors, at most cap
+	)
+	go func() {
+		errc <- extdis(ext)
+	}()
+	generate(func(enc []byte) {
+		dec, ok := <-ext.Dec
+		if !ok {
+			t.Errorf("decoding stream ended early")
+			return
+		}
+		inst, text := disasm(syntax, pad(enc))
+		totalTests++
+		if *dumpTest {
+			fmt.Printf("%x -> %s [%d]\n", enc[:len(enc)], dec.text, dec.nenc)
+		}
+		if text != dec.text || inst.Len != dec.nenc {
+			suffix := ""
+			if allowedMismatch(text, size, &inst, dec) {
+				totalSkips++
+				if !*mismatch {
+					return
+				}
+				suffix += " (allowed mismatch)"
+			}
+			totalErrors++
+			if len(errors) >= cap(errors) {
+				j := rand.Intn(totalErrors)
+				if j >= cap(errors) {
+					return
+				}
+				errors = append(errors[:j], errors[j+1:]...)
+			}
+			errors = append(errors, fmt.Sprintf("decode(%x) = %q, %d, want %q, %d%s", enc, text, inst.Len, dec.text, dec.nenc, suffix))
+		}
+	})
+
+	if *mismatch {
+		totalErrors -= totalSkips
+	}
+
+	for _, b := range errors {
+		t.Log(b)
+	}
+
+	if totalErrors > 0 {
+		t.Fail()
+	}
+	t.Logf("%d test cases, %d expected mismatches, %d failures; %.0f cases/second", totalTests, totalSkips, totalErrors, float64(totalTests)/time.Since(start).Seconds())
+
+	if err := <-errc; err != nil {
+		t.Fatal("external disassembler: %v", err)
+	}
+
+}
+
+const start = 0x8000 // start address of text
+
+// writeInst writes the generated byte sequences to a new file
+// starting at offset start. That file is intended to be the input to
+// the external disassembler.
+func writeInst(generate func(func([]byte))) (file string, f *os.File, size int, err error) {
+	f, err = ioutil.TempFile("", "ppc64asm")
+	if err != nil {
+		return
+	}
+
+	file = f.Name()
+
+	f.Seek(start, 0)
+	w := bufio.NewWriter(f)
+	defer w.Flush()
+	size = 0
+	generate(func(x []byte) {
+		if len(x) > 4 {
+			x = x[:4]
+		}
+		if debug {
+			fmt.Printf("%#x: %x%x\n", start+size, x, zeros[len(x):])
+		}
+		w.Write(x)
+		w.Write(zeros[len(x):])
+		size += len(zeros)
+	})
+	return file, f, size, nil
+}
+
+var zeros = []byte{0, 0, 0, 0}
+
+// pad pads the code sequence with pops.
+func pad(enc []byte) []byte {
+	if len(enc) < 4 {
+		enc = append(enc[:len(enc):len(enc)], zeros[:4-len(enc)]...)
+	}
+	return enc
+}
+
+// disasm returns the decoded instruction and text
+// for the given source bytes, using the given syntax and mode.
+func disasm(syntax string, src []byte) (inst Inst, text string) {
+	// If printTests is set, we record the coverage value
+	// before and after, and we write out the inputs for which
+	// coverage went up, in the format expected in testdata/decode.text.
+	// This produces a fairly small set of test cases that exercise nearly
+	// all the code.
+	var cover float64
+	if *printTests {
+		cover -= coverage()
+	}
+
+	inst, err := Decode(src, binary.BigEndian)
+	if err != nil {
+		text = "error: " + err.Error()
+	} else {
+		text = inst.String()
+		switch syntax {
+		//case "arm":
+		//	text = ARMSyntax(inst)
+		case "gnu":
+			text = GNUSyntax(inst)
+		//case "plan9":
+		//	text = plan9Syntax(inst, 0, nil)
+		default:
+			text = "error: unknown syntax " + syntax
+		}
+	}
+
+	if *printTests {
+		cover += coverage()
+		if cover > 0 {
+			max := len(src)
+			if max > 4 && inst.Len <= 4 {
+				max = 4
+			}
+			fmt.Printf("%x|%x\t%s\t%s\n", src[:inst.Len], src[inst.Len:max], syntax, text)
+		}
+	}
+
+	return
+}
+
+// coverage returns a floating point number denoting the
+// test coverage until now. The number increases when new code paths are exercised,
+// both in the Go program and in the decoder byte code.
+func coverage() float64 {
+	var f float64
+	f += testing.Coverage()
+	f += decodeCoverage()
+	return f
+}
+
+func decodeCoverage() float64 {
+	n := 0
+	for _, t := range decoderCover {
+		if t {
+			n++
+		}
+	}
+	return float64(1+n) / float64(1+len(decoderCover))
+}
+
+// Helpers for writing disassembler output parsers.
+
+// hasPrefix reports whether any of the space-separated words in the text s
+// begins with any of the given prefixes.
+func hasPrefix(s string, prefixes ...string) bool {
+	for _, prefix := range prefixes {
+		for s := s; s != ""; {
+			if strings.HasPrefix(s, prefix) {
+				return true
+			}
+			i := strings.Index(s, " ")
+			if i < 0 {
+				break
+			}
+			s = s[i+1:]
+		}
+	}
+	return false
+}
+
+// contains reports whether the text s contains any of the given substrings.
+func contains(s string, substrings ...string) bool {
+	for _, sub := range substrings {
+		if strings.Contains(s, sub) {
+			return true
+		}
+	}
+	return false
+}
+
+// isHex reports whether b is a hexadecimal character (0-9A-Fa-f).
+func isHex(b byte) bool { return b == '0' || unhex[b] > 0 }
+
+// parseHex parses the hexadecimal byte dump in hex,
+// appending the parsed bytes to raw and returning the updated slice.
+// The returned bool signals whether any invalid hex was found.
+// Spaces and tabs between bytes are okay but any other non-hex is not.
+func parseHex(hex []byte, raw []byte) ([]byte, bool) {
+	hex = trimSpace(hex)
+	for j := 0; j < len(hex); {
+		for hex[j] == ' ' || hex[j] == '\t' {
+			j++
+		}
+		if j >= len(hex) {
+			break
+		}
+		if j+2 > len(hex) || !isHex(hex[j]) || !isHex(hex[j+1]) {
+			return nil, false
+		}
+		raw = append(raw, unhex[hex[j]]<<4|unhex[hex[j+1]])
+		j += 2
+	}
+	return raw, true
+}
+
+var unhex = [256]byte{
+	'0': 0,
+	'1': 1,
+	'2': 2,
+	'3': 3,
+	'4': 4,
+	'5': 5,
+	'6': 6,
+	'7': 7,
+	'8': 8,
+	'9': 9,
+	'A': 10,
+	'B': 11,
+	'C': 12,
+	'D': 13,
+	'E': 14,
+	'F': 15,
+	'a': 10,
+	'b': 11,
+	'c': 12,
+	'd': 13,
+	'e': 14,
+	'f': 15,
+}
+
+// index is like bytes.Index(s, []byte(t)) but avoids the allocation.
+func index(s []byte, t string) int {
+	i := 0
+	for {
+		j := bytes.IndexByte(s[i:], t[0])
+		if j < 0 {
+			return -1
+		}
+		i = i + j
+		if i+len(t) > len(s) {
+			return -1
+		}
+		for k := 1; k < len(t); k++ {
+			if s[i+k] != t[k] {
+				goto nomatch
+			}
+		}
+		return i
+	nomatch:
+		i++
+	}
+}
+
+// fixSpace rewrites runs of spaces, tabs, and newline characters into single spaces in s.
+// If s must be rewritten, it is rewritten in place.
+func fixSpace(s []byte) []byte {
+	s = trimSpace(s)
+	for i := 0; i < len(s); i++ {
+		if s[i] == '\t' || s[i] == '\n' || i > 0 && s[i] == ' ' && s[i-1] == ' ' {
+			goto Fix
+		}
+	}
+	return s
+
+Fix:
+	b := s
+	w := 0
+	for i := 0; i < len(s); i++ {
+		c := s[i]
+		if c == '\t' || c == '\n' {
+			c = ' '
+		}
+		if c == ' ' && w > 0 && b[w-1] == ' ' {
+			continue
+		}
+		b[w] = c
+		w++
+	}
+	if w > 0 && b[w-1] == ' ' {
+		w--
+	}
+	return b[:w]
+}
+
+// trimSpace trims leading and trailing space from s, returning a subslice of s.
+func trimSpace(s []byte) []byte {
+	j := len(s)
+	for j > 0 && (s[j-1] == ' ' || s[j-1] == '\t' || s[j-1] == '\n') {
+		j--
+	}
+	i := 0
+	for i < j && (s[i] == ' ' || s[i] == '\t') {
+		i++
+	}
+	return s[i:j]
+}
+
+// pcrel matches instructions using relative addressing mode.
+var (
+	pcrel = regexp.MustCompile(`^((?:.* )?(?:b|bc)[^ac ]* (?:(?:[0-9]{1,2},)|(?:[0-7]\*)|\+|lt|gt|eq|so|cr[0-7]|,)*)0x([0-9a-f]+)$`)
+)
+
+// Generators.
+//
+// The test cases are described as functions that invoke a callback repeatedly,
+// with a new input sequence each time. These helpers make writing those
+// a little easier.
+
+// randomCases generates random instructions.
+func randomCases(t *testing.T) func(func([]byte)) {
+	return func(try func([]byte)) {
+		// All the strides are relatively prime to 2 and therefore to 2²⁸,
+		// so we will not repeat any instructions until we have tried all 2²⁸.
+		// Using a stride other than 1 is meant to visit the instructions in a
+		// pseudorandom order, which gives better variety in the set of
+		// test cases chosen by -printtests.
+		stride := uint32(10007)
+		n := 1 << 28 / 7
+		if testing.Short() {
+			stride = 100003
+			n = 1 << 28 / 1001
+		} else if *longTest {
+			stride = 2000033
+			n = 1 << 29
+		}
+		x := uint32(0)
+		for i := 0; i < n; i++ {
+			enc := (x%15)<<28 | x&(1<<28-1)
+			try([]byte{byte(enc), byte(enc >> 8), byte(enc >> 16), byte(enc >> 24)})
+			x += stride
+		}
+	}
+}
+
+// hexCases generates the cases written in hexadecimal in the encoded string.
+// Spaces in 'encoded' separate entire test cases, not individual bytes.
+func hexCases(t *testing.T, encoded string) func(func([]byte)) {
+	return func(try func([]byte)) {
+		for _, x := range strings.Fields(encoded) {
+			src, err := hex.DecodeString(x)
+			if err != nil {
+				t.Errorf("parsing %q: %v", x, err)
+			}
+			try(src)
+		}
+	}
+}
+
+// testdataCases generates the test cases recorded in testdata/decode.txt.
+// It only uses the inputs; it ignores the answers recorded in that file.
+func testdataCases(t *testing.T) func(func([]byte)) {
+	var codes [][]byte
+	data, err := ioutil.ReadFile("testdata/decode.txt")
+	if err != nil {
+		t.Fatal(err)
+	}
+	for _, line := range strings.Split(string(data), "\n") {
+		line = strings.TrimSpace(line)
+		if line == "" || strings.HasPrefix(line, "#") {
+			continue
+		}
+		f := strings.Fields(line)[0]
+		i := strings.Index(f, "|")
+		if i < 0 {
+			t.Errorf("parsing %q: missing | separator", f)
+			continue
+		}
+		if i%2 != 0 {
+			t.Errorf("parsing %q: misaligned | separator", f)
+		}
+		code, err := hex.DecodeString(f[:i] + f[i+1:])
+		if err != nil {
+			t.Errorf("parsing %q: %v", f, err)
+			continue
+		}
+		codes = append(codes, code)
+	}
+
+	return func(try func([]byte)) {
+		for _, code := range codes {
+			try(code)
+		}
+	}
+}
+
+func caller(skip int) string {
+	pc, _, _, _ := runtime.Caller(skip)
+	f := runtime.FuncForPC(pc)
+	name := "?"
+	if f != nil {
+		name = f.Name()
+		if i := strings.LastIndex(name, "."); i >= 0 {
+			name = name[i+1:]
+		}
+	}
+	return name
+}

ppc64/ppc64asm/field.go

diff --git a/ppc64/ppc64asm/field.go b/ppc64/ppc64asm/field.go
new file mode 100644
index 0000000..26a4fdf
--- /dev/null
+++ b/ppc64/ppc64asm/field.go
@@ -0,0 +1,84 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"fmt"
+	"strings"
+)
+
+// A BitField is a bit-field in a 32-bit word.
+// Bits are counted from 0 from the MSB to 31 as the LSB.
+type BitField struct {
+	Offs uint8 // the offset of the left-most bit.
+	Bits uint8 // length in bits.
+}
+
+func (b BitField) String() string {
+	if b.Bits > 1 {
+		return fmt.Sprintf("[%d:%d]", b.Offs, int(b.Offs+b.Bits)-1)
+	} else if b.Bits == 1 {
+		return fmt.Sprintf("[%d]", b.Offs)
+	} else {
+		return fmt.Sprintf("[%d, len=0]", b.Offs)
+	}
+}
+
+// Parse extracts the bitfield b from i, and return it as an unsigned integer.
+// Parse will panic if b is invalid.
+func (b BitField) Parse(i uint32) uint32 {
+	if b.Bits > 32 || b.Bits == 0 || b.Offs > 31 || b.Offs+b.Bits > 32 {
+		panic(fmt.Sprintf("invalid bitfiled %v", b))
+	}
+	return (i >> (32 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1)
+}
+
+// ParseSigned extracts the bitfield b from i, and return it as a signed integer.
+// ParseSigned will panic if b is invalid.
+func (b BitField) ParseSigned(i uint32) int32 {
+	u := int32(b.Parse(i))
+	return u << (32 - b.Bits) >> (32 - b.Bits)
+}
+
+// BitFields is a series of BitFields representing a single number.
+type BitFields []BitField
+
+func (bs BitFields) String() string {
+	ss := make([]string, len(bs))
+	for i, bf := range bs {
+		ss[i] = bf.String()
+	}
+	return fmt.Sprintf("<%s>", strings.Join(ss, "|"))
+}
+
+func (bs *BitFields) Append(b BitField) {
+	*bs = append(*bs, b)
+}
+
+// parse extracts the bitfields from i, concatenate them and return the result
+// as an unsigned integer and the total length of all the bitfields.
+// parse will panic if any bitfield in b is invalid, but it doesn't check if
+// the sequence of bitfields is reasonable.
+func (bs BitFields) parse(i uint32) (u uint32, Bits uint8) {
+	for _, b := range bs {
+		u = (u << b.Bits) | b.Parse(i)
+		Bits += b.Bits
+	}
+	return u, Bits
+}
+
+// Parse extracts the bitfields from i, concatenate them and return the result
+// as an unsigned integer. Parse will panic if any bitfield in b is invalid.
+func (bs BitFields) Parse(i uint32) uint32 {
+	u, _ := bs.parse(i)
+	return u
+}
+
+// Parse extracts the bitfields from i, concatenate them and return the result
+// as a signed integer. Parse will panic if any bitfield in b is invalid.
+func (bs BitFields) ParseSigned(i uint32) int32 {
+	u, l := bs.parse(i)
+	return int32(u) << (32 - l) >> (32 - l)
+}

ppc64/ppc64asm/field_test.go

diff --git a/ppc64/ppc64asm/field_test.go b/ppc64/ppc64asm/field_test.go
new file mode 100644
index 0000000..14eb2f8
--- /dev/null
+++ b/ppc64/ppc64asm/field_test.go
@@ -0,0 +1,60 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"testing"
+)
+
+func panicOrNot(f func()) (panicked bool) {
+	defer func() {
+		if err := recover(); err != nil {
+			panicked = true
+		}
+	}()
+	f()
+	return false
+}
+
+func TestBitField(t *testing.T) {
+	var tests = []struct {
+		b    BitField
+		i    uint32 // input
+		u    uint32 // unsigned output
+		s    int32  // signed output
+		fail bool   // if the check should panic
+	}{
+		{BitField{0, 0}, 0, 0, 0, true},
+		{BitField{31, 2}, 0, 0, 0, true},
+		{BitField{31, 1}, 1, 1, -1, false},
+		{BitField{29, 2}, 0 << 1, 0, 0, false},
+		{BitField{29, 2}, 1 << 1, 1, 1, false},
+		{BitField{29, 2}, 2 << 1, 2, -2, false},
+		{BitField{29, 2}, 3 << 1, 3, -1, false},
+		{BitField{0, 32}, 1<<32 - 1, 1<<32 - 1, -1, false},
+		{BitField{16, 3}, 1 << 15, 4, -4, false},
+	}
+	for i, tst := range tests {
+		var (
+			ou uint32
+			os int32
+		)
+		failed := panicOrNot(func() {
+			ou = tst.b.Parse(tst.i)
+			os = tst.b.ParseSigned(tst.i)
+		})
+		if failed != tst.fail {
+			t.Errorf("case %d: %v: fail test failed, got %v, expected %v", i, tst.b, failed, tst.fail)
+			continue
+		}
+		if ou != tst.u {
+			t.Errorf("case %d: %v.Parse(%d) returned %d, expected %d", i, tst.b, tst.i, ou, tst.u)
+			continue
+		}
+		if os != tst.s {
+			t.Errorf("case %d: %v.ParseSigned(%d) returned %d, expected %d", i, tst.b, tst.i, os, tst.s)
+		}
+	}
+}

ppc64/ppc64asm/gnu.go

diff --git a/ppc64/ppc64asm/gnu.go b/ppc64/ppc64asm/gnu.go
new file mode 100644
index 0000000..1ea3ab5
--- /dev/null
+++ b/ppc64/ppc64asm/gnu.go
@@ -0,0 +1,125 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"bytes"
+	"fmt"
+	"strings"
+)
+
+// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils.
+// This form typically matches the syntax defined in the Power ISA Reference Manual.
+func GNUSyntax(inst Inst) string {
+	var buf bytes.Buffer
+	if inst.Op == 0 {
+		return "error: unkown instruction"
+	}
+	buf.WriteString(inst.Op.String())
+	sep := " "
+	for i, arg := range inst.Args[:] {
+		if arg == nil {
+			break
+		}
+		text := gnuArg(&inst, i, arg)
+		if text == "" {
+			continue
+		}
+		buf.WriteString(sep)
+		sep = ","
+		buf.WriteString(text)
+	}
+	return buf.String()
+}
+
+// gnuArg formats arg (which is the argIndex's arg in inst) according to GNU rules.
+// NOTE: because GNUSyntax is the only caller of this func, and it receives a copy
+//       of inst, it's ok to modify inst.Args here.
+func gnuArg(inst *Inst, argIndex int, arg Arg) string {
+	// special cases for load/store instructions
+	if _, ok := arg.(Offset); ok {
+		if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil {
+			panic(fmt.Errorf("wrong table: offset not followed by register"))
+		}
+	}
+	switch arg := arg.(type) {
+	case Reg:
+		if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 {
+			return "0"
+		}
+		return arg.String()
+	case CondReg:
+		if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
+			return "" // don't show cr0 for cmp instructions
+		} else if arg >= CR0 {
+			return fmt.Sprintf("cr%d", int(arg-CR0))
+		}
+		bit := [4]string{"lt", "gt", "eq", "so"}[(arg-Cond0LT)%4]
+		if arg <= Cond0SO {
+			return bit
+		}
+		return fmt.Sprintf("4*cr%d+%s", int(arg-Cond0LT)/4, bit)
+	case Imm:
+		return fmt.Sprintf("%d", arg)
+	case SpReg:
+		return fmt.Sprintf("%d", int(arg))
+	case PCRel:
+		return fmt.Sprintf(".%+#x", int(arg))
+	case Label:
+		return fmt.Sprintf("%#x", int(arg))
+	case Offset:
+		reg := inst.Args[argIndex+1].(Reg)
+		removeArg(inst, argIndex+1)
+		if reg == R0 {
+			return fmt.Sprintf("%d(0)", int(arg))
+		}
+		return fmt.Sprintf("%d(r%d)", int(arg), reg-R0)
+	}
+	return fmt.Sprintf("???(%v)", arg)
+}
+
+// removeArg removes the arg in inst.Args[index].
+func removeArg(inst *Inst, index int) {
+	for i := index; i < len(inst.Args); i++ {
+		if i+1 < len(inst.Args) {
+			inst.Args[i] = inst.Args[i+1]
+		} else {
+			inst.Args[i] = nil
+		}
+	}
+}
+
+// isLoadStoreOp returns true if op is a load or store instruction
+func isLoadStoreOp(op Op) bool {
+	switch op {
+	case LBZ, LBZU, LBZX, LBZUX:
+		return true
+	case LHZ, LHZU, LHZX, LHZUX:
+		return true
+	case LHA, LHAU, LHAX, LHAUX:
+		return true
+	case LWZ, LWZU, LWZX, LWZUX:
+		return true
+	case LWA, LWAX, LWAUX:
+		return true
+	case LD, LDU, LDX, LDUX:
+		return true
+	case LQ:
+		return true
+	case STB, STBU, STBX, STBUX:
+		return true
+	case STH, STHU, STHX, STHUX:
+		return true
+	case STW, STWU, STWX, STWUX:
+		return true
+	case STD, STDU, STDX, STDUX:
+		return true
+	case STQ:
+		return true
+	case LHBRX, LWBRX, STHBRX, STWBRX:
+		return true
+	}
+	return false
+}

ppc64/ppc64asm/inst.go

diff --git a/ppc64/ppc64asm/inst.go b/ppc64/ppc64asm/inst.go
new file mode 100644
index 0000000..bf72ac6
--- /dev/null
+++ b/ppc64/ppc64asm/inst.go
@@ -0,0 +1,310 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"bytes"
+	"fmt"
+)
+
+type Inst struct {
+	Op   Op     // Opcode mnemonic
+	Enc  uint32 // Raw encoding bits
+	Len  int    // Length of encoding in bytes.
+	Args Args   // Instruction arguments, in Power ISA manual order.
+}
+
+func (i Inst) String() string {
+	var buf bytes.Buffer
+	buf.WriteString(i.Op.String())
+	for j, arg := range i.Args {
+		if arg == nil {
+			break
+		}
+		if j == 0 {
+			buf.WriteString(" ")
+		} else {
+			buf.WriteString(", ")
+		}
+		buf.WriteString(arg.String())
+	}
+	return buf.String()
+}
+
+// An Op is an instruction operation.
+type Op uint16
+
+func (o Op) String() string {
+	if int(o) >= len(opstr) || opstr[o] == "" {
+		return fmt.Sprintf("Op(%d)", int(o))
+	}
+	return opstr[o]
+}
+
+// An Arg is a single instruction argument, one of these types: Reg, CondReg, SpReg, Imm, PCRel, Label, or Offset.
+type Arg interface {
+	IsArg()
+	String() string
+}
+
+// An Args holds the instruction arguments.
+// If an instruction has fewer than 4 arguments,
+// the final elements in the array are nil.
+type Args [5]Arg
+
+// A Reg is a single register. The zero value means R0, not the absence of a register.
+// It also includes special registers.
+type Reg uint16
+
+const (
+	_ Reg = iota
+	R0
+	R1
+	R2
+	R3
+	R4
+	R5
+	R6
+	R7
+	R8
+	R9
+	R10
+	R11
+	R12
+	R13
+	R14
+	R15
+	R16
+	R17
+	R18
+	R19
+	R20
+	R21
+	R22
+	R23
+	R24
+	R25
+	R26
+	R27
+	R28
+	R29
+	R30
+	R31
+	F0
+	F1
+	F2
+	F3
+	F4
+	F5
+	F6
+	F7
+	F8
+	F9
+	F10
+	F11
+	F12
+	F13
+	F14
+	F15
+	F16
+	F17
+	F18
+	F19
+	F20
+	F21
+	F22
+	F23
+	F24
+	F25
+	F26
+	F27
+	F28
+	F29
+	F30
+	F31
+	V0 // VSX extension, F0 is V0[0:63].
+	V1
+	V2
+	V3
+	V4
+	V5
+	V6
+	V7
+	V8
+	V9
+	V10
+	V11
+	V12
+	V13
+	V14
+	V15
+	V16
+	V17
+	V18
+	V19
+	V20
+	V21
+	V22
+	V23
+	V24
+	V25
+	V26
+	V27
+	V28
+	V29
+	V30
+	V31
+	V32
+	V33
+	V34
+	V35
+	V36
+	V37
+	V38
+	V39
+	V40
+	V41
+	V42
+	V43
+	V44
+	V45
+	V46
+	V47
+	V48
+	V49
+	V50
+	V51
+	V52
+	V53
+	V54
+	V55
+	V56
+	V57
+	V58
+	V59
+	V60
+	V61
+	V62
+	V63
+)
+
+func (Reg) IsArg() {}
+func (r Reg) String() string {
+	switch {
+	case R0 <= r && r <= R31:
+		return fmt.Sprintf("r%d", int(r-R0))
+	case F0 <= r && r <= F31:
+		return fmt.Sprintf("f%d", int(r-F0))
+	case V0 <= r && r <= V63:
+		return fmt.Sprintf("v%d", int(r-V0))
+	default:
+		return fmt.Sprint("Reg(%d)", int(r))
+	}
+}
+
+// CondReg is a bit or field in the conditon register.
+type CondReg int8
+
+const (
+	_ CondReg = iota
+	// Condition Regster bits
+	Cond0LT
+	Cond0GT
+	Cond0EQ
+	Cond0SO
+	Cond1LT
+	Cond1GT
+	Cond1EQ
+	Cond1SO
+	Cond2LT
+	Cond2GT
+	Cond2EQ
+	Cond2SO
+	Cond3LT
+	Cond3GT
+	Cond3EQ
+	Cond3SO
+	Cond4LT
+	Cond4GT
+	Cond4EQ
+	Cond4SO
+	Cond5LT
+	Cond5GT
+	Cond5EQ
+	Cond5SO
+	Cond6LT
+	Cond6GT
+	Cond6EQ
+	Cond6SO
+	Cond7LT
+	Cond7GT
+	Cond7EQ
+	Cond7SO
+	// Condition Register Fields
+	CR0
+	CR1
+	CR2
+	CR3
+	CR4
+	CR5
+	CR6
+	CR7
+)
+
+func (CondReg) IsArg() {}
+func (c CondReg) String() string {
+	switch {
+	default:
+		return fmt.Sprintf("CondReg(%d)", int(c))
+	case c >= CR0:
+		return fmt.Sprintf("CR%d", int(c-CR0))
+	case c >= Cond0LT && c < CR0:
+		return fmt.Sprintf("Cond%d%s", int((c-Cond0LT)/4), [4]string{"LT", "GT", "EQ", "SO"}[(c-Cond0LT)%4])
+	}
+}
+
+// SpReg is a special register, its meaning depends on Op.
+type SpReg uint16
+
+const (
+	SpRegZero SpReg = 0
+)
+
+func (SpReg) IsArg() {}
+func (s SpReg) String() string {
+	return fmt.Sprintf("SpReg(%d)", int(s))
+}
+
+// PCRel is a PC-relative offset, used only in branch instructions.
+type PCRel int32
+
+func (PCRel) IsArg() {}
+func (r PCRel) String() string {
+	return fmt.Sprintf("PC%+#x", int32(r))
+}
+
+// A Label is a code (text) address, used only in absolute branch instructions.
+type Label uint32
+
+func (Label) IsArg() {}
+func (l Label) String() string {
+	return fmt.Sprintf("%#x", uint32(l))
+}
+
+// Imm represents an immediate number.
+type Imm int32
+
+func (Imm) IsArg() {}
+func (i Imm) String() string {
+	return fmt.Sprintf("%d", int32(i))
+}
+
+// Offset represents a memory offset immediate.
+type Offset int32
+
+func (Offset) IsArg() {}
+func (o Offset) String() string {
+	return fmt.Sprintf("%+d", int32(o))
+}

ppc64/ppc64asm/objdump_test.go

diff --git a/ppc64/ppc64asm/objdump_test.go b/ppc64/ppc64asm/objdump_test.go
new file mode 100644
index 0000000..101c9df
--- /dev/null
+++ b/ppc64/ppc64asm/objdump_test.go
@@ -0,0 +1,130 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"encoding/binary"
+	"strings"
+	"testing"
+)
+
+func TestObjdumpPowerTestdata(t *testing.T) { testObjdump(t, testdataCases(t)) }
+func TestObjdumpPowerManual(t *testing.T)   { testObjdump(t, hexCases(t, objdumpManualTests)) }
+func TestObjdumpPowerRandom(t *testing.T)   { testObjdump(t, randomCases(t)) }
+
+// objdumpManualTests holds test cases that will be run by TestObjdumpARMManual.
+// If you are debugging a few cases that turned up in a longer run, it can be useful
+// to list them here and then use -run=Manual, particularly with tracing enabled.
+// Note that these are byte sequences, so they must be reversed from the usual
+// word presentation.
+var objdumpManualTests = `
+6d746162
+4c040000
+88000017
+`
+
+// allowedMismatchObjdump reports whether the mismatch between text and dec
+// should be allowed by the test.
+func allowedMismatchObjdump(text string, size int, inst *Inst, dec ExtInst) bool {
+	if hasPrefix(dec.text, deleted...) {
+		return true
+	}
+
+	// we support more instructions than binutils
+	if strings.Contains(dec.text, ".long") {
+		return true
+	}
+
+	if hasPrefix(text, "error:") {
+		if hasPrefix(dec.text, unsupported...) {
+			return true
+		}
+	}
+
+	switch inst.Op {
+	case BC, BCA, BL, BLA, BCL, BCLA, TDI, TWI, TW, TD:
+		return true // TODO(minux): we lack the support for extended opcodes here
+	case RLWNM, RLWNM_, RLDICL, RLDICL_, RLWINM, RLWINM_, RLDCL, RLDCL_:
+		return true // TODO(minux): we lack the support for extended opcodes here
+	case DCBTST, DCBT:
+		return true // objdump uses the embedded argument order, we use the server argument order
+	case MTFSF, MTFSF_: // objdump doesn't show the last two arguments
+		return true
+	case VSPLTB, VSPLTH, VSPLTW: // objdump generates unreasonable result "vspltw v6,v19,4" for 10c49a8c, the last 4 should be 0.
+		return true
+	}
+	if hasPrefix(text, "evm", "evl", "efs") { // objdump will disassemble them wrong (e.g. evmhoumia as vsldoi)
+		return true
+	}
+
+	if len(dec.enc) >= 4 {
+		_ = binary.BigEndian.Uint32(dec.enc[:4])
+	}
+
+	return false
+}
+
+// Instructions known to libopcodes (or xed) but not to us.
+// TODO(minux): those single precision instructions are missing from ppc64.csv
+// those data cache instructions are deprecated, but must be treated as no-ops, see 4.3.2.1 pg. 774.
+var unsupported = strings.Fields(`
+fmsubs
+fmsubs.
+fnmadds
+fnmadds.
+fnmsubs
+fnmsubs.
+fmuls
+fmuls.
+fdivs
+fdivs.
+fadds
+fadds.
+fsubs
+fsubs.
+dst
+dstst
+dssall
+`)
+
+// Instructions explicitly dropped in Power ISA that were in POWER architecture.
+// See A.30 Deleted Instructions and A.31 Discontiued Opcodes
+var deleted = strings.Fields(`
+abs
+clcs
+clf
+cli
+dclst
+div
+divs
+doz
+dozi
+lscbx
+maskg
+maskir
+mfsri
+mul
+nabs
+rac
+rfi
+rfsvc
+rlmi
+rrib
+sle
+sleq
+sliq
+slliq
+sllq
+slq
+sraiq
+sraq
+sre
+srea
+sreq
+sriq
+srliq
+srlq
+srq
+maskg`)

ppc64/ppc64asm/objdumpext_test.go

diff --git a/ppc64/ppc64asm/objdumpext_test.go b/ppc64/ppc64asm/objdumpext_test.go
new file mode 100644
index 0000000..413a626
--- /dev/null
+++ b/ppc64/ppc64asm/objdumpext_test.go
@@ -0,0 +1,251 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Copied and simplified from rsc.io/arm/armasm/objdumpext_test.go.
+
+package ppc64asm
+
+import (
+	"bytes"
+	"debug/elf"
+	"encoding/binary"
+	"fmt"
+	"io"
+	"log"
+	"os"
+	"strconv"
+	"strings"
+	"testing"
+)
+
+const objdumpPath = "/usr/local/bin/powerpc64-unknown-linux-gnu-objdump"
+
+func testObjdump(t *testing.T, generate func(func([]byte))) {
+	if _, err := os.Stat(objdumpPath); err != nil {
+		if !testing.Short() {
+			t.Fatal(err)
+		}
+		t.Skip(err)
+	}
+
+	testExtDis(t, "gnu", objdump, generate, allowedMismatchObjdump)
+}
+
+func objdump(ext *ExtDis) error {
+	// File already written with instructions; add ELF header.
+	if err := writeELF64(ext.File, ext.Size); err != nil {
+		return err
+	}
+
+	b, err := ext.Run(objdumpPath, "-d", "-z", ext.File.Name())
+	if err != nil {
+		return err
+	}
+
+	var (
+		nmatch  int
+		reading bool
+		next    uint32 = start
+		addr    uint32
+		encbuf  [4]byte
+		enc     []byte
+		text    string
+	)
+	flush := func() {
+		if addr == next {
+			if m := pcrel.FindStringSubmatch(text); m != nil {
+				targ, _ := strconv.ParseUint(m[2], 16, 64)
+				text = fmt.Sprintf("%s.%+#x", m[1], int32(uint32(targ)-addr))
+			}
+			if strings.HasPrefix(text, "stmia") {
+				text = "stm" + text[5:]
+			}
+			if strings.HasPrefix(text, "stmfd") {
+				text = "stmdb" + text[5:]
+			}
+			if strings.HasPrefix(text, "ldmfd") {
+				text = "ldm" + text[5:]
+			}
+			text = strings.Replace(text, "#0.0", "#0", -1)
+			if text == "undefined" && len(enc) == 4 {
+				text = "error: unknown instruction"
+				enc = nil
+			}
+			if len(enc) == 4 {
+				// prints as word but we want to record bytes
+				enc[0], enc[3] = enc[3], enc[0]
+				enc[1], enc[2] = enc[2], enc[1]
+			}
+			ext.Dec <- ExtInst{addr, encbuf, len(enc), text}
+			encbuf = [4]byte{}
+			enc = nil
+			next += 4
+		}
+	}
+	var textangle = []byte("<.text>:")
+	for {
+		line, err := b.ReadSlice('\n')
+		if err != nil {
+			if err == io.EOF {
+				break
+			}
+			return fmt.Errorf("reading objdump output: %v", err)
+		}
+		if bytes.Contains(line, textangle) {
+			reading = true
+			continue
+		}
+		if !reading {
+			continue
+		}
+		if debug {
+			os.Stdout.Write(line)
+		}
+		if enc1 := parseContinuation(line, encbuf[:len(enc)]); enc1 != nil {
+			enc = enc1
+			continue
+		}
+		flush()
+		nmatch++
+		addr, enc, text = parseLine(line, encbuf[:0])
+		if addr > next {
+			return fmt.Errorf("address out of sync expected <= %#x at %q in:\n%s", next, line, line)
+		}
+	}
+	flush()
+	if next != start+uint32(ext.Size) {
+		return fmt.Errorf("not enough results found [%d %d]", next, start+ext.Size)
+	}
+	if err := ext.Wait(); err != nil {
+		return fmt.Errorf("exec: %v", err)
+	}
+
+	return nil
+}
+
+var (
+	undefined      = []byte("<UNDEFINED>")
+	unpredictable  = []byte("<UNPREDICTABLE>")
+	illegalShifter = []byte("<illegal shifter operand>")
+)
+
+func parseLine(line []byte, encstart []byte) (addr uint32, enc []byte, text string) {
+	oline := line
+	i := index(line, ":\t")
+	if i < 0 {
+		log.Fatalf("cannot parse disassembly: %q", oline)
+	}
+	x, err := strconv.ParseUint(string(trimSpace(line[:i])), 16, 32)
+	if err != nil {
+		log.Fatalf("cannot parse disassembly: %q", oline)
+	}
+	addr = uint32(x)
+	line = line[i+2:]
+	i = bytes.IndexByte(line, '\t')
+	if i < 0 {
+		log.Fatalf("cannot parse disassembly: %q", oline)
+	}
+	enc, ok := parseHex(line[:i], encstart)
+	if !ok {
+		log.Fatalf("cannot parse disassembly: %q", oline)
+	}
+	line = trimSpace(line[i:])
+	if bytes.Contains(line, undefined) {
+		text = "undefined"
+		return
+	}
+	if bytes.Contains(line, illegalShifter) {
+		text = "undefined"
+		return
+	}
+	if false && bytes.Contains(line, unpredictable) {
+		text = "unpredictable"
+		return
+	}
+	if i := bytes.IndexByte(line, ';'); i >= 0 {
+		line = trimSpace(line[:i])
+	}
+	text = string(fixSpace(line))
+	return
+}
+
+func parseContinuation(line []byte, enc []byte) []byte {
+	i := index(line, ":\t")
+	if i < 0 {
+		return nil
+	}
+	line = line[i+1:]
+	enc, _ = parseHex(line, enc)
+	return enc
+}
+
+// writeELF64 writes an ELF64 header to the file,
+// describing a text segment that starts at start
+// and extends for size bytes.
+func writeELF64(f *os.File, size int) error {
+	f.Seek(0, 0)
+	var hdr elf.Header64
+	var prog elf.Prog64
+	var sect elf.Section64
+	var buf bytes.Buffer
+	binary.Write(&buf, binary.BigEndian, &hdr)
+	off1 := buf.Len()
+	binary.Write(&buf, binary.BigEndian, &prog)
+	off2 := buf.Len()
+	binary.Write(&buf, binary.BigEndian, &sect)
+	off3 := buf.Len()
+	buf.Reset()
+	data := byte(elf.ELFDATA2MSB)
+	hdr = elf.Header64{
+		Ident:     [16]byte{0x7F, 'E', 'L', 'F', 2, data, 1},
+		Type:      2,
+		Machine:   uint16(elf.EM_PPC64),
+		Version:   1,
+		Entry:     start,
+		Phoff:     uint64(off1),
+		Shoff:     uint64(off2),
+		Flags:     0x05000002,
+		Ehsize:    uint16(off1),
+		Phentsize: uint16(off2 - off1),
+		Phnum:     1,
+		Shentsize: uint16(off3 - off2),
+		Shnum:     3,
+		Shstrndx:  2,
+	}
+	binary.Write(&buf, binary.BigEndian, &hdr)
+	prog = elf.Prog64{
+		Type:   1,
+		Off:    start,
+		Vaddr:  start,
+		Paddr:  start,
+		Filesz: uint64(size),
+		Memsz:  uint64(size),
+		Flags:  5,
+		Align:  start,
+	}
+	binary.Write(&buf, binary.BigEndian, &prog)
+	binary.Write(&buf, binary.BigEndian, &sect) // NULL section
+	sect = elf.Section64{
+		Name:      1,
+		Type:      uint32(elf.SHT_PROGBITS),
+		Addr:      start,
+		Off:       start,
+		Size:      uint64(size),
+		Flags:     uint64(elf.SHF_ALLOC | elf.SHF_EXECINSTR),
+		Addralign: 4,
+	}
+	binary.Write(&buf, binary.BigEndian, &sect) // .text
+	sect = elf.Section64{
+		Name:      uint32(len("\x00.text\x00")),
+		Type:      uint32(elf.SHT_STRTAB),
+		Addr:      0,
+		Off:       uint64(off2 + (off3-off2)*3),
+		Size:      uint64(len("\x00.text\x00.shstrtab\x00")),
+		Addralign: 1,
+	}
+	binary.Write(&buf, binary.BigEndian, &sect)
+	buf.WriteString("\x00.text\x00.shstrtab\x00")
+	f.Write(buf.Bytes())
+	return nil
+}

ppc64/ppc64asm/plan9.go

diff --git a/ppc64/ppc64asm/plan9.go b/ppc64/ppc64asm/plan9.go
new file mode 100644
index 0000000..b0b5270
--- /dev/null
+++ b/ppc64/ppc64asm/plan9.go
@@ -0,0 +1,164 @@
+// Copyright 2015 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"fmt"
+	"strings"
+)
+
+// plan9Syntax returns the Go assembler syntax for the instruction.
+// The syntax was originally defined by Plan 9.
+// The pc is the program counter of the first instruction, used for expanding
+// PC-relative addresses into absolute ones.
+// The symname function queries the symbol table for the program
+// being disassembled. It returns the name and base address of the symbol
+// containing the target, if any; otherwise it returns "", 0.
+func plan9Syntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string {
+	if symname == nil {
+		symname = func(uint64) (string, uint64) { return "", 0 }
+	}
+	if inst.Op == 0 {
+		return "?"
+	}
+	var args []string
+	for i, a := range inst.Args[:] {
+		if a == nil {
+			break
+		}
+		if s := plan9Arg(&inst, i, pc, a, symname); s != "" {
+			args = append(args, s)
+		}
+	}
+	var op string
+	op = plan9OpMap[inst.Op]
+	if op == "" {
+		op = strings.ToUpper(inst.Op.String())
+	}
+	// laid out the instruction
+	switch inst.Op {
+	default: // dst, sA, sB, ...
+		if len(args) == 0 {
+			return op
+		} else if len(args) == 1 {
+			return fmt.Sprintf("%s %s", op, args[0])
+		}
+		args = append(args, args[0])
+		return op + " " + strings.Join(args[1:], ", ")
+	// store instructions always have the memory operand at the end, no need to reorder
+	case STB, STBU, STBX, STBUX,
+		STH, STHU, STHX, STHUX,
+		STW, STWU, STWX, STWUX,
+		STD, STDU, STDX, STDUX,
+		STQ,
+		STHBRX, STWBRX:
+		return op + " " + strings.Join(args, ", ")
+	// branch instructions needs additional handling
+	case BCLR:
+		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
+			return "RET"
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BC:
+		if int(inst.Args[0].(Imm))&0x1c == 12 { // jump on cond bit set
+			return fmt.Sprintf("B%s %s", args[1], args[2])
+		} else if int(inst.Args[0].(Imm))&0x1c == 4 && revCondMap[args[1]] != "" { // jump on cond bit not set
+			return fmt.Sprintf("B%s %s", revCondMap[args[1]], args[2])
+		}
+	case BCCTR:
+		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
+			return "BR (CTR)"
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BCCTRL:
+		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
+			return "BL (CTR)"
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BCA, BCL, BCLA, BCLRL, BCTAR, BCTARL:
+		return op + " " + strings.Join(args, ", ")
+	}
+	panic("unreachable")
+}
+
+// plan9Arg formats arg (which is the argIndex's arg in inst) according to Plan 9 rules.
+// NOTE: because Plan9Syntax is the only caller of this func, and it receives a copy
+//       of inst, it's ok to modify inst.Args here.
+func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64) (string, uint64)) string {
+	// special cases for load/store instructions
+	if _, ok := arg.(Offset); ok {
+		if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil {
+			panic(fmt.Errorf("wrong table: offset not followed by register"))
+		}
+	}
+	switch arg := arg.(type) {
+	case Reg:
+		if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 {
+			return "0"
+		}
+		if arg == R30 {
+			return "g"
+		}
+		return strings.ToUpper(arg.String())
+	case CondReg:
+		if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
+			return "" // don't show cr0 for cmp instructions
+		} else if arg >= CR0 {
+			return fmt.Sprintf("CR%d", int(arg-CR0))
+		}
+		bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4]
+		if arg <= Cond0SO {
+			return bit
+		}
+		return fmt.Sprintf("4*CR%d+%s", int(arg-Cond0LT)/4, bit)
+	case Imm:
+		return fmt.Sprintf("$%d", arg)
+	case SpReg:
+		switch arg {
+		case 8:
+			return "LR"
+		case 9:
+			return "CTR"
+		}
+		return fmt.Sprintf("SPR(%d)", int(arg))
+	case PCRel:
+		addr := pc + uint64(int64(arg))
+		if s, base := symname(addr); s != "" && base == addr {
+			return fmt.Sprintf("%s(SB)", s)
+		}
+		return fmt.Sprintf("%#x", addr)
+	case Label:
+		return fmt.Sprintf("%#x", int(arg))
+	case Offset:
+		reg := inst.Args[argIndex+1].(Reg)
+		removeArg(inst, argIndex+1)
+		if reg == R0 {
+			return fmt.Sprintf("%d(0)", int(arg))
+		}
+		return fmt.Sprintf("%d(R%d)", int(arg), reg-R0)
+	}
+	return fmt.Sprintf("???(%v)", arg)
+}
+
+// revCondMap maps a conditional register bit to its inverse, if possible.
+var revCondMap = map[string]string{
+	"LT": "GE", "GT": "LE", "EQ": "NE",
+}
+
+// plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics.
+var plan9OpMap = map[Op]string{
+	LBZ: "MOVBZ", STB: "MOVB",
+	LBZU: "MOVBZU", STBU: "MOVBU", // TODO(minux): indexed forms are not handled
+	LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
+	LHZU: "MOVHZU", STHU: "MOVHU",
+	LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW",
+	LWZU: "MOVWZU", STWU: "MOVWU",
+	LD: "MOVD", STD: "MOVD",
+	LDU: "MOVDU", STDU: "MOVDU",
+	MTSPR: "MOV", MFSPR: "MOV", // the width is ambiguous for SPRs
+	B:     "BR",
+	CMPLD: "CMPU", CMPLW: "CMPWU",
+	CMPD: "CMP", CMPW: "CMPW",
+}

ppc64/ppc64asm/tables.go

diff --git a/ppc64/ppc64asm/tables.go b/ppc64/ppc64asm/tables.go
new file mode 100644
index 0000000..a9bd796
--- /dev/null
+++ b/ppc64/ppc64asm/tables.go
@@ -0,0 +1,5418 @@
+package ppc64asm
+
+const (
+	_ Op = iota
+	CNTLZW
+	CNTLZW_
+	B
+	BA
+	BL
+	BLA
+	BC
+	BCA
+	BCL
+	BCLA
+	BCLR
+	BCLRL
+	BCCTR
+	BCCTRL
+	BCTAR
+	BCTARL
+	CRAND
+	CROR
+	CRNAND
+	CRXOR
+	CRNOR
+	CRANDC
+	MCRF
+	CREQV
+	CRORC
+	SC
+	CLRBHRB
+	MFBHRBE
+	LBZ
+	LBZU
+	LBZX
+	LBZUX
+	LHZ
+	LHZU
+	LHZX
+	LHZUX
+	LHA
+	LHAU
+	LHAX
+	LHAUX
+	LWZ
+	LWZU
+	LWZX
+	LWZUX
+	LWA
+	LWAX
+	LWAUX
+	LD
+	LDU
+	LDX
+	LDUX
+	STB
+	STBU
+	STBX
+	STBUX
+	STH
+	STHU
+	STHX
+	STHUX
+	STW
+	STWU
+	STWX
+	STWUX
+	STD
+	STDU
+	STDX
+	STDUX
+	LQ
+	STQ
+	LHBRX
+	LWBRX
+	STHBRX
+	STWBRX
+	LDBRX
+	STDBRX
+	LMW
+	STMW
+	LSWI
+	LSWX
+	STSWI
+	STSWX
+	LI
+	ADDI
+	LIS
+	ADDIS
+	ADD
+	ADD_
+	ADDO
+	ADDO_
+	ADDIC
+	SUBF
+	SUBF_
+	SUBFO
+	SUBFO_
+	ADDIC_
+	SUBFIC
+	ADDC
+	ADDC_
+	ADDCO
+	ADDCO_
+	SUBFC
+	SUBFC_
+	SUBFCO
+	SUBFCO_
+	ADDE
+	ADDE_
+	ADDEO
+	ADDEO_
+	ADDME
+	ADDME_
+	ADDMEO
+	ADDMEO_
+	SUBFE
+	SUBFE_
+	SUBFEO
+	SUBFEO_
+	SUBFME
+	SUBFME_
+	SUBFMEO
+	SUBFMEO_
+	ADDZE
+	ADDZE_
+	ADDZEO
+	ADDZEO_
+	SUBFZE
+	SUBFZE_
+	SUBFZEO
+	SUBFZEO_
+	NEG
+	NEG_
+	NEGO
+	NEGO_
+	MULLI
+	MULLW
+	MULLW_
+	MULLWO
+	MULLWO_
+	MULHW
+	MULHW_
+	MULHWU
+	MULHWU_
+	DIVW
+	DIVW_
+	DIVWO
+	DIVWO_
+	DIVWU
+	DIVWU_
+	DIVWUO
+	DIVWUO_
+	DIVWE
+	DIVWE_
+	DIVWEO
+	DIVWEO_
+	DIVWEU
+	DIVWEU_
+	DIVWEUO
+	DIVWEUO_
+	MULLD
+	MULLD_
+	MULLDO
+	MULLDO_
+	MULHDU
+	MULHDU_
+	MULHD
+	MULHD_
+	DIVD
+	DIVD_
+	DIVDO
+	DIVDO_
+	DIVDU
+	DIVDU_
+	DIVDUO
+	DIVDUO_
+	DIVDE
+	DIVDE_
+	DIVDEO
+	DIVDEO_
+	DIVDEU
+	DIVDEU_
+	DIVDEUO
+	DIVDEUO_
+	CMPWI
+	CMPDI
+	CMPW
+	CMPD
+	CMPLWI
+	CMPLDI
+	CMPLW
+	CMPLD
+	TWI
+	TW
+	TDI
+	ISEL
+	TD
+	ANDI_
+	ANDIS_
+	ORI
+	ORIS
+	XORI
+	XORIS
+	AND
+	AND_
+	XOR
+	XOR_
+	NAND
+	NAND_
+	OR
+	OR_
+	NOR
+	NOR_
+	ANDC
+	ANDC_
+	EXTSB
+	EXTSB_
+	EQV
+	EQV_
+	ORC
+	ORC_
+	EXTSH
+	EXTSH_
+	CMPB
+	POPCNTB
+	POPCNTW
+	PRTYD
+	PRTYW
+	EXTSW
+	EXTSW_
+	CNTLZD
+	CNTLZD_
+	POPCNTD
+	BPERMD
+	RLWINM
+	RLWINM_
+	RLWNM
+	RLWNM_
+	RLWIMI
+	RLWIMI_
+	RLDICL
+	RLDICL_
+	RLDICR
+	RLDICR_
+	RLDIC
+	RLDIC_
+	RLDCL
+	RLDCL_
+	RLDCR
+	RLDCR_
+	RLDIMI
+	RLDIMI_
+	SLW
+	SLW_
+	SRW
+	SRW_
+	SRAWI
+	SRAWI_
+	SRAW
+	SRAW_
+	SLD
+	SLD_
+	SRD
+	SRD_
+	SRADI
+	SRADI_
+	SRAD
+	SRAD_
+	CDTBCD
+	CBCDTD
+	ADDG6S
+	MTSPR
+	MFSPR
+	MTCRF
+	MFCR
+	MTSLE
+	MFVSRD
+	MFVSRWZ
+	MTVSRD
+	MTVSRWA
+	MTVSRWZ
+	MTOCRF
+	MFOCRF
+	MCRXR
+	MTDCRUX
+	MFDCRUX
+	LFS
+	LFSU
+	LFSX
+	LFSUX
+	LFD
+	LFDU
+	LFDX
+	LFDUX
+	LFIWAX
+	LFIWZX
+	STFS
+	STFSU
+	STFSX
+	STFSUX
+	STFD
+	STFDU
+	STFDX
+	STFDUX
+	STFIWX
+	LFDP
+	LFDPX
+	STFDP
+	STFDPX
+	FMR
+	FMR_
+	FABS
+	FABS_
+	FNABS
+	FNABS_
+	FNEG
+	FNEG_
+	FCPSGN
+	FCPSGN_
+	FMRGEW
+	FMRGOW
+	FADD
+	FADD_
+	FADDS
+	FADDS_
+	FSUB
+	FSUB_
+	FSUBS
+	FSUBS_
+	FMUL
+	FMUL_
+	FMULS
+	FMULS_
+	FDIV
+	FDIV_
+	FDIVS
+	FDIVS_
+	FSQRT
+	FSQRT_
+	FSQRTS
+	FSQRTS_
+	FRE
+	FRE_
+	FRES
+	FRES_
+	FRSQRTE
+	FRSQRTE_
+	FRSQRTES
+	FRSQRTES_
+	FTDIV
+	FTSQRT
+	FMADD
+	FMADD_
+	FMADDS
+	FMADDS_
+	FMSUB
+	FMSUB_
+	FMSUBS
+	FMSUBS_
+	FNMADD
+	FNMADD_
+	FNMADDS
+	FNMADDS_
+	FNMSUB
+	FNMSUB_
+	FNMSUBS
+	FNMSUBS_
+	FRSP
+	FRSP_
+	FCTID
+	FCTID_
+	FCTIDZ
+	FCTIDZ_
+	FCTIDU
+	FCTIDU_
+	FCTIDUZ
+	FCTIDUZ_
+	FCTIW
+	FCTIW_
+	FCTIWZ
+	FCTIWZ_
+	FCTIWU
+	FCTIWU_
+	FCTIWUZ
+	FCTIWUZ_
+	FCFID
+	FCFID_
+	FCFIDU
+	FCFIDU_
+	FCFIDS
+	FCFIDS_
+	FCFIDUS
+	FCFIDUS_
+	FRIN
+	FRIN_
+	FRIZ
+	FRIZ_
+	FRIP
+	FRIP_
+	FRIM
+	FRIM_
+	FCMPU
+	FCMPO
+	FSEL
+	FSEL_
+	MFFS
+	MFFS_
+	MCRFS
+	MTFSFI
+	MTFSFI_
+	MTFSF
+	MTFSF_
+	MTFSB0
+	MTFSB0_
+	MTFSB1
+	MTFSB1_
+	LVEBX
+	LVEHX
+	LVEWX
+	LVX
+	LVXL
+	STVEBX
+	STVEHX
+	STVEWX
+	STVX
+	STVXL
+	LVSL
+	LVSR
+	VPKPX
+	VPKSDSS
+	VPKSDUS
+	VPKSHSS
+	VPKSHUS
+	VPKSWSS
+	VPKSWUS
+	VPKUDUM
+	VPKUDUS
+	VPKUHUM
+	VPKUHUS
+	VPKUWUM
+	VPKUWUS
+	VUPKHPX
+	VUPKLPX
+	VUPKHSB
+	VUPKHSH
+	VUPKHSW
+	VUPKLSB
+	VUPKLSH
+	VUPKLSW
+	VMRGHB
+	VMRGHH
+	VMRGLB
+	VMRGLH
+	VMRGHW
+	VMRGLW
+	VMRGEW
+	VMRGOW
+	VSPLTB
+	VSPLTH
+	VSPLTW
+	VSPLTISB
+	VSPLTISH
+	VSPLTISW
+	VPERM
+	VSEL
+	VSL
+	VSLDOI
+	VSLO
+	VSR
+	VSRO
+	VADDCUW
+	VADDSBS
+	VADDSHS
+	VADDSWS
+	VADDUBM
+	VADDUDM
+	VADDUHM
+	VADDUWM
+	VADDUBS
+	VADDUHS
+	VADDUWS
+	VADDUQM
+	VADDEUQM
+	VADDCUQ
+	VADDECUQ
+	VSUBCUW
+	VSUBSBS
+	VSUBSHS
+	VSUBSWS
+	VSUBUBM
+	VSUBUDM
+	VSUBUHM
+	VSUBUWM
+	VSUBUBS
+	VSUBUHS
+	VSUBUWS
+	VSUBUQM
+	VSUBEUQM
+	VSUBCUQ
+	VSUBECUQ
+	VMULESB
+	VMULEUB
+	VMULOSB
+	VMULOUB
+	VMULESH
+	VMULEUH
+	VMULOSH
+	VMULOUH
+	VMULESW
+	VMULEUW
+	VMULOSW
+	VMULOUW
+	VMULUWM
+	VMHADDSHS
+	VMHRADDSHS
+	VMLADDUHM
+	VMSUMUBM
+	VMSUMMBM
+	VMSUMSHM
+	VMSUMSHS
+	VMSUMUHM
+	VMSUMUHS
+	VSUMSWS
+	VSUM2SWS
+	VSUM4SBS
+	VSUM4SHS
+	VSUM4UBS
+	VAVGSB
+	VAVGSH
+	VAVGSW
+	VAVGUB
+	VAVGUW
+	VAVGUH
+	VMAXSB
+	VMAXSD
+	VMAXUB
+	VMAXUD
+	VMAXSH
+	VMAXSW
+	VMAXUH
+	VMAXUW
+	VMINSB
+	VMINSD
+	VMINUB
+	VMINUD
+	VMINSH
+	VMINSW
+	VMINUH
+	VMINUW
+	VCMPEQUB
+	VCMPEQUB_
+	VCMPEQUH
+	VCMPEQUH_
+	VCMPEQUW
+	VCMPEQUW_
+	VCMPEQUD
+	VCMPEQUD_
+	VCMPGTSB
+	VCMPGTSB_
+	VCMPGTSD
+	VCMPGTSD_
+	VCMPGTSH
+	VCMPGTSH_
+	VCMPGTSW
+	VCMPGTSW_
+	VCMPGTUB
+	VCMPGTUB_
+	VCMPGTUD
+	VCMPGTUD_
+	VCMPGTUH
+	VCMPGTUH_
+	VCMPGTUW
+	VCMPGTUW_
+	VAND
+	VANDC
+	VEQV
+	VNAND
+	VORC
+	VNOR
+	VOR
+	VXOR
+	VRLB
+	VRLH
+	VRLW
+	VRLD
+	VSLB
+	VSLH
+	VSLW
+	VSLD
+	VSRB
+	VSRH
+	VSRW
+	VSRD
+	VSRAB
+	VSRAH
+	VSRAW
+	VSRAD
+	VADDFP
+	VSUBFP
+	VMADDFP
+	VNMSUBFP
+	VMAXFP
+	VMINFP
+	VCTSXS
+	VCTUXS
+	VCFSX
+	VCFUX
+	VRFIM
+	VRFIN
+	VRFIP
+	VRFIZ
+	VCMPBFP
+	VCMPBFP_
+	VCMPEQFP
+	VCMPEQFP_
+	VCMPGEFP
+	VCMPGEFP_
+	VCMPGTFP
+	VCMPGTFP_
+	VEXPTEFP
+	VLOGEFP
+	VREFP
+	VRSQRTEFP
+	VCIPHER
+	VCIPHERLAST
+	VNCIPHER
+	VNCIPHERLAST
+	VSBOX
+	VSHASIGMAD
+	VSHASIGMAW
+	VPMSUMB
+	VPMSUMD
+	VPMSUMH
+	VPMSUMW
+	VPERMXOR
+	VGBBD
+	VCLZB
+	VCLZH
+	VCLZW
+	VCLZD
+	VPOPCNTB
+	VPOPCNTD
+	VPOPCNTH
+	VPOPCNTW
+	VBPERMQ
+	BCDADD_
+	BCDSUB_
+	MTVSCR
+	MFVSCR
+	DADD
+	DADD_
+	DSUB
+	DSUB_
+	DMUL
+	DMUL_
+	DDIV
+	DDIV_
+	DCMPU
+	DCMPO
+	DTSTDC
+	DTSTDG
+	DTSTEX
+	DTSTSF
+	DQUAI
+	DQUAI_
+	DQUA
+	DQUA_
+	DRRND
+	DRRND_
+	DRINTX
+	DRINTX_
+	DRINTN
+	DRINTN_
+	DCTDP
+	DCTDP_
+	DCTQPQ
+	DCTQPQ_
+	DRSP
+	DRSP_
+	DRDPQ
+	DRDPQ_
+	DCFFIX
+	DCFFIX_
+	DCFFIXQ
+	DCFFIXQ_
+	DCTFIX
+	DCTFIX_
+	DDEDPD
+	DDEDPD_
+	DENBCD
+	DENBCD_
+	DXEX
+	DXEX_
+	DIEX
+	DIEX_
+	DSCLI
+	DSCLI_
+	DSCRI
+	DSCRI_
+	LXSDX
+	LXSIWAX
+	LXSIWZX
+	LXSSPX
+	LXVD2X
+	LXVDSX
+	LXVW4X
+	STXSDX
+	STXSIWX
+	STXSSPX
+	STXVD2X
+	STXVW4X
+	XSABSDP
+	XSADDDP
+	XSADDSP
+	XSCMPODP
+	XSCMPUDP
+	XSCPSGNDP
+	XSCVDPSP
+	XSCVDPSPN
+	XSCVDPSXDS
+	XSCVDPSXWS
+	XSCVDPUXDS
+	XSCVDPUXWS
+	XSCVSPDP
+	XSCVSPDPN
+	XSCVSXDDP
+	XSCVSXDSP
+	XSCVUXDDP
+	XSCVUXDSP
+	XSDIVDP
+	XSDIVSP
+	XSMADDADP
+	XSMADDASP
+	XSMAXDP
+	XSMINDP
+	XSMSUBADP
+	XSMSUBASP
+	XSMULDP
+	XSMULSP
+	XSNABSDP
+	XSNEGDP
+	XSNMADDADP
+	XSNMADDASP
+	XSNMSUBADP
+	XSNMSUBASP
+	XSRDPI
+	XSRDPIC
+	XSRDPIM
+	XSRDPIP
+	XSRDPIZ
+	XSREDP
+	XSRESP
+	XSRSP
+	XSRSQRTEDP
+	XSRSQRTESP
+	XSSQRTDP
+	XSSQRTSP
+	XSSUBDP
+	XSSUBSP
+	XSTDIVDP
+	XSTSQRTDP
+	XVABSDP
+	XVABSSP
+	XVADDDP
+	XVADDSP
+	XVCMPEQDP
+	XVCMPEQDP_
+	XVCMPEQSP
+	XVCMPEQSP_
+	XVCMPGEDP
+	XVCMPGEDP_
+	XVCMPGESP
+	XVCMPGESP_
+	XVCMPGTDP
+	XVCMPGTDP_
+	XVCMPGTSP
+	XVCMPGTSP_
+	XVCPSGNDP
+	XVCPSGNSP
+	XVCVDPSP
+	XVCVDPSXDS
+	XVCVDPSXWS
+	XVCVDPUXDS
+	XVCVDPUXWS
+	XVCVSPDP
+	XVCVSPSXDS
+	XVCVSPSXWS
+	XVCVSPUXDS
+	XVCVSPUXWS
+	XVCVSXDDP
+	XVCVSXDSP
+	XVCVSXWDP
+	XVCVSXWSP
+	XVCVUXDDP
+	XVCVUXDSP
+	XVCVUXWDP
+	XVCVUXWSP
+	XVDIVDP
+	XVDIVSP
+	XVMADDADP
+	XVMADDASP
+	XVMAXDP
+	XVMAXSP
+	XVMINDP
+	XVMINSP
+	XVMSUBADP
+	XVMSUBASP
+	XVMULDP
+	XVMULSP
+	XVNABSDP
+	XVNABSSP
+	XVNEGDP
+	XVNEGSP
+	XVNMADDADP
+	XVNMADDASP
+	XVNMSUBADP
+	XVNMSUBASP
+	XVRDPI
+	XVRDPIC
+	XVRDPIM
+	XVRDPIP
+	XVRDPIZ
+	XVREDP
+	XVRESP
+	XVRSPI
+	XVRSPIC
+	XVRSPIM
+	XVRSPIP
+	XVRSPIZ
+	XVRSQRTEDP
+	XVRSQRTESP
+	XVSQRTDP
+	XVSQRTSP
+	XVSUBDP
+	XVSUBSP
+	XVTDIVDP
+	XVTDIVSP
+	XVTSQRTDP
+	XVTSQRTSP
+	XXLAND
+	XXLANDC
+	XXLEQV
+	XXLNAND
+	XXLORC
+	XXLNOR
+	XXLOR
+	XXLXOR
+	XXMRGHW
+	XXMRGLW
+	XXPERMDI
+	XXSEL
+	XXSLDWI
+	XXSPLTW
+	BRINC
+	EVABS
+	EVADDIW
+	EVADDSMIAAW
+	EVADDSSIAAW
+	EVADDUMIAAW
+	EVADDUSIAAW
+	EVADDW
+	EVAND
+	EVCMPEQ
+	EVANDC
+	EVCMPGTS
+	EVCMPGTU
+	EVCMPLTU
+	EVCMPLTS
+	EVCNTLSW
+	EVCNTLZW
+	EVDIVWS
+	EVDIVWU
+	EVEQV
+	EVEXTSB
+	EVEXTSH
+	EVLDD
+	EVLDH
+	EVLDDX
+	EVLDHX
+	EVLDW
+	EVLHHESPLAT
+	EVLDWX
+	EVLHHESPLATX
+	EVLHHOSSPLAT
+	EVLHHOUSPLAT
+	EVLHHOSSPLATX
+	EVLHHOUSPLATX
+	EVLWHE
+	EVLWHOS
+	EVLWHEX
+	EVLWHOSX
+	EVLWHOU
+	EVLWHSPLAT
+	EVLWHOUX
+	EVLWHSPLATX
+	EVLWWSPLAT
+	EVMERGEHI
+	EVLWWSPLATX
+	EVMERGELO
+	EVMERGEHILO
+	EVMHEGSMFAA
+	EVMERGELOHI
+	EVMHEGSMFAN
+	EVMHEGSMIAA
+	EVMHEGUMIAA
+	EVMHEGSMIAN
+	EVMHEGUMIAN
+	EVMHESMF
+	EVMHESMFAAW
+	EVMHESMFA
+	EVMHESMFANW
+	EVMHESMI
+	EVMHESMIAAW
+	EVMHESMIA
+	EVMHESMIANW
+	EVMHESSF
+	EVMHESSFA
+	EVMHESSFAAW
+	EVMHESSFANW
+	EVMHESSIAAW
+	EVMHESSIANW
+	EVMHEUMI
+	EVMHEUMIAAW
+	EVMHEUMIA
+	EVMHEUMIANW
+	EVMHEUSIAAW
+	EVMHEUSIANW
+	EVMHOGSMFAA
+	EVMHOGSMIAA
+	EVMHOGSMFAN
+	EVMHOGSMIAN
+	EVMHOGUMIAA
+	EVMHOSMF
+	EVMHOGUMIAN
+	EVMHOSMFA
+	EVMHOSMFAAW
+	EVMHOSMI
+	EVMHOSMFANW
+	EVMHOSMIA
+	EVMHOSMIAAW
+	EVMHOSMIANW
+	EVMHOSSF
+	EVMHOSSFA
+	EVMHOSSFAAW
+	EVMHOSSFANW
+	EVMHOSSIAAW
+	EVMHOUMI
+	EVMHOSSIANW
+	EVMHOUMIA
+	EVMHOUMIAAW
+	EVMHOUSIAAW
+	EVMHOUMIANW
+	EVMHOUSIANW
+	EVMRA
+	EVMWHSMF
+	EVMWHSMI
+	EVMWHSMFA
+	EVMWHSMIA
+	EVMWHSSF
+	EVMWHUMI
+	EVMWHSSFA
+	EVMWHUMIA
+	EVMWLSMIAAW
+	EVMWLSSIAAW
+	EVMWLSMIANW
+	EVMWLSSIANW
+	EVMWLUMI
+	EVMWLUMIAAW
+	EVMWLUMIA
+	EVMWLUMIANW
+	EVMWLUSIAAW
+	EVMWSMF
+	EVMWLUSIANW
+	EVMWSMFA
+	EVMWSMFAA
+	EVMWSMI
+	EVMWSMIAA
+	EVMWSMFAN
+	EVMWSMIA
+	EVMWSMIAN
+	EVMWSSF
+	EVMWSSFA
+	EVMWSSFAA
+	EVMWUMI
+	EVMWSSFAN
+	EVMWUMIA
+	EVMWUMIAA
+	EVNAND
+	EVMWUMIAN
+	EVNEG
+	EVNOR
+	EVORC
+	EVOR
+	EVRLW
+	EVRLWI
+	EVSEL
+	EVRNDW
+	EVSLW
+	EVSPLATFI
+	EVSRWIS
+	EVSLWI
+	EVSPLATI
+	EVSRWIU
+	EVSRWS
+	EVSTDD
+	EVSRWU
+	EVSTDDX
+	EVSTDH
+	EVSTDW
+	EVSTDHX
+	EVSTDWX
+	EVSTWHE
+	EVSTWHO
+	EVSTWWE
+	EVSTWHEX
+	EVSTWHOX
+	EVSTWWEX
+	EVSTWWO
+	EVSUBFSMIAAW
+	EVSTWWOX
+	EVSUBFSSIAAW
+	EVSUBFUMIAAW
+	EVSUBFUSIAAW
+	EVSUBFW
+	EVSUBIFW
+	EVXOR
+	EVFSABS
+	EVFSNABS
+	EVFSNEG
+	EVFSADD
+	EVFSMUL
+	EVFSSUB
+	EVFSDIV
+	EVFSCMPGT
+	EVFSCMPLT
+	EVFSCMPEQ
+	EVFSTSTGT
+	EVFSTSTLT
+	EVFSTSTEQ
+	EVFSCFSI
+	EVFSCFSF
+	EVFSCFUI
+	EVFSCFUF
+	EVFSCTSI
+	EVFSCTUI
+	EVFSCTSIZ
+	EVFSCTUIZ
+	EVFSCTSF
+	EVFSCTUF
+	EFSABS
+	EFSNEG
+	EFSNABS
+	EFSADD
+	EFSMUL
+	EFSSUB
+	EFSDIV
+	EFSCMPGT
+	EFSCMPLT
+	EFSCMPEQ
+	EFSTSTGT
+	EFSTSTLT
+	EFSTSTEQ
+	EFSCFSI
+	EFSCFSF
+	EFSCTSI
+	EFSCFUI
+	EFSCFUF
+	EFSCTUI
+	EFSCTSIZ
+	EFSCTSF
+	EFSCTUIZ
+	EFSCTUF
+	EFDABS
+	EFDNEG
+	EFDNABS
+	EFDADD
+	EFDMUL
+	EFDSUB
+	EFDDIV
+	EFDCMPGT
+	EFDCMPEQ
+	EFDCMPLT
+	EFDTSTGT
+	EFDTSTLT
+	EFDCFSI
+	EFDTSTEQ
+	EFDCFUI
+	EFDCFSID
+	EFDCFSF
+	EFDCFUF
+	EFDCFUID
+	EFDCTSI
+	EFDCTUI
+	EFDCTSIDZ
+	EFDCTUIDZ
+	EFDCTSIZ
+	EFDCTSF
+	EFDCTUF
+	EFDCTUIZ
+	EFDCFS
+	EFSCFD
+	DLMZB
+	DLMZB_
+	MACCHW
+	MACCHW_
+	MACCHWO
+	MACCHWO_
+	MACCHWS
+	MACCHWS_
+	MACCHWSO
+	MACCHWSO_
+	MACCHWU
+	MACCHWU_
+	MACCHWUO
+	MACCHWUO_
+	MACCHWSU
+	MACCHWSU_
+	MACCHWSUO
+	MACCHWSUO_
+	MACHHW
+	MACHHW_
+	MACHHWO
+	MACHHWO_
+	MACHHWS
+	MACHHWS_
+	MACHHWSO
+	MACHHWSO_
+	MACHHWU
+	MACHHWU_
+	MACHHWUO
+	MACHHWUO_
+	MACHHWSU
+	MACHHWSU_
+	MACHHWSUO
+	MACHHWSUO_
+	MACLHW
+	MACLHW_
+	MACLHWO
+	MACLHWO_
+	MACLHWS
+	MACLHWS_
+	MACLHWSO
+	MACLHWSO_
+	MACLHWU
+	MACLHWU_
+	MACLHWUO
+	MACLHWUO_
+	MULCHW
+	MULCHW_
+	MACLHWSU
+	MACLHWSU_
+	MACLHWSUO
+	MACLHWSUO_
+	MULCHWU
+	MULCHWU_
+	MULHHW
+	MULHHW_
+	MULLHW
+	MULLHW_
+	MULHHWU
+	MULHHWU_
+	MULLHWU
+	MULLHWU_
+	NMACCHW
+	NMACCHW_
+	NMACCHWO
+	NMACCHWO_
+	NMACCHWS
+	NMACCHWS_
+	NMACCHWSO
+	NMACCHWSO_
+	NMACHHW
+	NMACHHW_
+	NMACHHWO
+	NMACHHWO_
+	NMACHHWS
+	NMACHHWS_
+	NMACHHWSO
+	NMACHHWSO_
+	NMACLHW
+	NMACLHW_
+	NMACLHWO
+	NMACLHWO_
+	NMACLHWS
+	NMACLHWS_
+	NMACLHWSO
+	NMACLHWSO_
+	ICBI
+	ICBT
+	DCBA
+	DCBT
+	DCBTST
+	DCBZ
+	DCBST
+	DCBF
+	ISYNC
+	LBARX
+	LHARX
+	LWARX
+	STBCX_
+	STHCX_
+	STWCX_
+	LDARX
+	STDCX_
+	LQARX
+	STQCX_
+	SYNC
+	EIEIO
+	MBAR
+	WAIT
+	TBEGIN_
+	TEND_
+	TABORT_
+	TABORTWC_
+	TABORTWCI_
+	TABORTDC_
+	TABORTDCI_
+	TSR_
+	TCHECK
+	MFTB
+	RFEBB
+	LBDX
+	LHDX
+	LWDX
+	LDDX
+	LFDDX
+	STBDX
+	STHDX
+	STWDX
+	STDDX
+	STFDDX
+	DSN
+	ECIWX
+	ECOWX
+	RFID
+	HRFID
+	DOZE
+	NAP
+	SLEEP
+	RVWINKLE
+	LBZCIX
+	LWZCIX
+	LHZCIX
+	LDCIX
+	STBCIX
+	STWCIX
+	STHCIX
+	STDCIX
+	TRECLAIM_
+	TRECHKPT_
+	MTMSR
+	MTMSRD
+	MFMSR
+	SLBIE
+	SLBIA
+	SLBMTE
+	SLBMFEV
+	SLBMFEE
+	SLBFEE_
+	MTSR
+	MTSRIN
+	MFSR
+	MFSRIN
+	TLBIE
+	TLBIEL
+	TLBIA
+	TLBSYNC
+	MSGSND
+	MSGCLR
+	MSGSNDP
+	MSGCLRP
+	MTTMR
+	RFI
+	RFCI
+	RFDI
+	RFMCI
+	RFGI
+	EHPRIV
+	MTDCR
+	MTDCRX
+	MFDCR
+	MFDCRX
+	WRTEE
+	WRTEEI
+	LBEPX
+	LHEPX
+	LWEPX
+	LDEPX
+	STBEPX
+	STHEPX
+	STWEPX
+	STDEPX
+	DCBSTEP
+	DCBTEP
+	DCBFEP
+	DCBTSTEP
+	ICBIEP
+	DCBZEP
+	LFDEPX
+	STFDEPX
+	EVLDDEPX
+	EVSTDDEPX
+	LVEPX
+	LVEPXL
+	STVEPX
+	STVEPXL
+	DCBI
+	DCBLQ_
+	ICBLQ_
+	DCBTLS
+	DCBTSTLS
+	ICBTLS
+	ICBLC
+	DCBLC
+	TLBIVAX
+	TLBILX
+	TLBSX
+	TLBSRX_
+	TLBRE
+	TLBWE
+	DNH
+	DCI
+	ICI
+	DCREAD
+	ICREAD
+	MFPMR
+	MTPMR
+)
+
+var opstr = [...]string{
+	CNTLZW:        "cntlzw",
+	CNTLZW_:       "cntlzw.",
+	B:             "b",
+	BA:            "ba",
+	BL:            "bl",
+	BLA:           "bla",
+	BC:            "bc",
+	BCA:           "bca",
+	BCL:           "bcl",
+	BCLA:          "bcla",
+	BCLR:          "bclr",
+	BCLRL:         "bclrl",
+	BCCTR:         "bcctr",
+	BCCTRL:        "bcctrl",
+	BCTAR:         "bctar",
+	BCTARL:        "bctarl",
+	CRAND:         "crand",
+	CROR:          "cror",
+	CRNAND:        "crnand",
+	CRXOR:         "crxor",
+	CRNOR:         "crnor",
+	CRANDC:        "crandc",
+	MCRF:          "mcrf",
+	CREQV:         "creqv",
+	CRORC:         "crorc",
+	SC:            "sc",
+	CLRBHRB:       "clrbhrb",
+	MFBHRBE:       "mfbhrbe",
+	LBZ:           "lbz",
+	LBZU:          "lbzu",
+	LBZX:          "lbzx",
+	LBZUX:         "lbzux",
+	LHZ:           "lhz",
+	LHZU:          "lhzu",
+	LHZX:          "lhzx",
+	LHZUX:         "lhzux",
+	LHA:           "lha",
+	LHAU:          "lhau",
+	LHAX:          "lhax",
+	LHAUX:         "lhaux",
+	LWZ:           "lwz",
+	LWZU:          "lwzu",
+	LWZX:          "lwzx",
+	LWZUX:         "lwzux",
+	LWA:           "lwa",
+	LWAX:          "lwax",
+	LWAUX:         "lwaux",
+	LD:            "ld",
+	LDU:           "ldu",
+	LDX:           "ldx",
+	LDUX:          "ldux",
+	STB:           "stb",
+	STBU:          "stbu",
+	STBX:          "stbx",
+	STBUX:         "stbux",
+	STH:           "sth",
+	STHU:          "sthu",
+	STHX:          "sthx",
+	STHUX:         "sthux",
+	STW:           "stw",
+	STWU:          "stwu",
+	STWX:          "stwx",
+	STWUX:         "stwux",
+	STD:           "std",
+	STDU:          "stdu",
+	STDX:          "stdx",
+	STDUX:         "stdux",
+	LQ:            "lq",
+	STQ:           "stq",
+	LHBRX:         "lhbrx",
+	LWBRX:         "lwbrx",
+	STHBRX:        "sthbrx",
+	STWBRX:        "stwbrx",
+	LDBRX:         "ldbrx",
+	STDBRX:        "stdbrx",
+	LMW:           "lmw",
+	STMW:          "stmw",
+	LSWI:          "lswi",
+	LSWX:          "lswx",
+	STSWI:         "stswi",
+	STSWX:         "stswx",
+	LI:            "li",
+	ADDI:          "addi",
+	LIS:           "lis",
+	ADDIS:         "addis",
+	ADD:           "add",
+	ADD_:          "add.",
+	ADDO:          "addo",
+	ADDO_:         "addo.",
+	ADDIC:         "addic",
+	SUBF:          "subf",
+	SUBF_:         "subf.",
+	SUBFO:         "subfo",
+	SUBFO_:        "subfo.",
+	ADDIC_:        "addic.",
+	SUBFIC:        "subfic",
+	ADDC:          "addc",
+	ADDC_:         "addc.",
+	ADDCO:         "addco",
+	ADDCO_:        "addco.",
+	SUBFC:         "subfc",
+	SUBFC_:        "subfc.",
+	SUBFCO:        "subfco",
+	SUBFCO_:       "subfco.",
+	ADDE:          "adde",
+	ADDE_:         "adde.",
+	ADDEO:         "addeo",
+	ADDEO_:        "addeo.",
+	ADDME:         "addme",
+	ADDME_:        "addme.",
+	ADDMEO:        "addmeo",
+	ADDMEO_:       "addmeo.",
+	SUBFE:         "subfe",
+	SUBFE_:        "subfe.",
+	SUBFEO:        "subfeo",
+	SUBFEO_:       "subfeo.",
+	SUBFME:        "subfme",
+	SUBFME_:       "subfme.",
+	SUBFMEO:       "subfmeo",
+	SUBFMEO_:      "subfmeo.",
+	ADDZE:         "addze",
+	ADDZE_:        "addze.",
+	ADDZEO:        "addzeo",
+	ADDZEO_:       "addzeo.",
+	SUBFZE:        "subfze",
+	SUBFZE_:       "subfze.",
+	SUBFZEO:       "subfzeo",
+	SUBFZEO_:      "subfzeo.",
+	NEG:           "neg",
+	NEG_:          "neg.",
+	NEGO:          "nego",
+	NEGO_:         "nego.",
+	MULLI:         "mulli",
+	MULLW:         "mullw",
+	MULLW_:        "mullw.",
+	MULLWO:        "mullwo",
+	MULLWO_:       "mullwo.",
+	MULHW:         "mulhw",
+	MULHW_:        "mulhw.",
+	MULHWU:        "mulhwu",
+	MULHWU_:       "mulhwu.",
+	DIVW:          "divw",
+	DIVW_:         "divw.",
+	DIVWO:         "divwo",
+	DIVWO_:        "divwo.",
+	DIVWU:         "divwu",
+	DIVWU_:        "divwu.",
+	DIVWUO:        "divwuo",
+	DIVWUO_:       "divwuo.",
+	DIVWE:         "divwe",
+	DIVWE_:        "divwe.",
+	DIVWEO:        "divweo",
+	DIVWEO_:       "divweo.",
+	DIVWEU:        "divweu",
+	DIVWEU_:       "divweu.",
+	DIVWEUO:       "divweuo",
+	DIVWEUO_:      "divweuo.",
+	MULLD:         "mulld",
+	MULLD_:        "mulld.",
+	MULLDO:        "mulldo",
+	MULLDO_:       "mulldo.",
+	MULHDU:        "mulhdu",
+	MULHDU_:       "mulhdu.",
+	MULHD:         "mulhd",
+	MULHD_:        "mulhd.",
+	DIVD:          "divd",
+	DIVD_:         "divd.",
+	DIVDO:         "divdo",
+	DIVDO_:        "divdo.",
+	DIVDU:         "divdu",
+	DIVDU_:        "divdu.",
+	DIVDUO:        "divduo",
+	DIVDUO_:       "divduo.",
+	DIVDE:         "divde",
+	DIVDE_:        "divde.",
+	DIVDEO:        "divdeo",
+	DIVDEO_:       "divdeo.",
+	DIVDEU:        "divdeu",
+	DIVDEU_:       "divdeu.",
+	DIVDEUO:       "divdeuo",
+	DIVDEUO_:      "divdeuo.",
+	CMPWI:         "cmpwi",
+	CMPDI:         "cmpdi",
+	CMPW:          "cmpw",
+	CMPD:          "cmpd",
+	CMPLWI:        "cmplwi",
+	CMPLDI:        "cmpldi",
+	CMPLW:         "cmplw",
+	CMPLD:         "cmpld",
+	TWI:           "twi",
+	TW:            "tw",
+	TDI:           "tdi",
+	ISEL:          "isel",
+	TD:            "td",
+	ANDI_:         "andi.",
+	ANDIS_:        "andis.",
+	ORI:           "ori",
+	ORIS:          "oris",
+	XORI:          "xori",
+	XORIS:         "xoris",
+	AND:           "and",
+	AND_:          "and.",
+	XOR:           "xor",
+	XOR_:          "xor.",
+	NAND:          "nand",
+	NAND_:         "nand.",
+	OR:            "or",
+	OR_:           "or.",
+	NOR:           "nor",
+	NOR_:          "nor.",
+	ANDC:          "andc",
+	ANDC_:         "andc.",
+	EXTSB:         "extsb",
+	EXTSB_:        "extsb.",
+	EQV:           "eqv",
+	EQV_:          "eqv.",
+	ORC:           "orc",
+	ORC_:          "orc.",
+	EXTSH:         "extsh",
+	EXTSH_:        "extsh.",
+	CMPB:          "cmpb",
+	POPCNTB:       "popcntb",
+	POPCNTW:       "popcntw",
+	PRTYD:         "prtyd",
+	PRTYW:         "prtyw",
+	EXTSW:         "extsw",
+	EXTSW_:        "extsw.",
+	CNTLZD:        "cntlzd",
+	CNTLZD_:       "cntlzd.",
+	POPCNTD:       "popcntd",
+	BPERMD:        "bpermd",
+	RLWINM:        "rlwinm",
+	RLWINM_:       "rlwinm.",
+	RLWNM:         "rlwnm",
+	RLWNM_:        "rlwnm.",
+	RLWIMI:        "rlwimi",
+	RLWIMI_:       "rlwimi.",
+	RLDICL:        "rldicl",
+	RLDICL_:       "rldicl.",
+	RLDICR:        "rldicr",
+	RLDICR_:       "rldicr.",
+	RLDIC:         "rldic",
+	RLDIC_:        "rldic.",
+	RLDCL:         "rldcl",
+	RLDCL_:        "rldcl.",
+	RLDCR:         "rldcr",
+	RLDCR_:        "rldcr.",
+	RLDIMI:        "rldimi",
+	RLDIMI_:       "rldimi.",
+	SLW:           "slw",
+	SLW_:          "slw.",
+	SRW:           "srw",
+	SRW_:          "srw.",
+	SRAWI:         "srawi",
+	SRAWI_:        "srawi.",
+	SRAW:          "sraw",
+	SRAW_:         "sraw.",
+	SLD:           "sld",
+	SLD_:          "sld.",
+	SRD:           "srd",
+	SRD_:          "srd.",
+	SRADI:         "sradi",
+	SRADI_:        "sradi.",
+	SRAD:          "srad",
+	SRAD_:         "srad.",
+	CDTBCD:        "cdtbcd",
+	CBCDTD:        "cbcdtd",
+	ADDG6S:        "addg6s",
+	MTSPR:         "mtspr",
+	MFSPR:         "mfspr",
+	MTCRF:         "mtcrf",
+	MFCR:          "mfcr",
+	MTSLE:         "mtsle",
+	MFVSRD:        "mfvsrd",
+	MFVSRWZ:       "mfvsrwz",
+	MTVSRD:        "mtvsrd",
+	MTVSRWA:       "mtvsrwa",
+	MTVSRWZ:       "mtvsrwz",
+	MTOCRF:        "mtocrf",
+	MFOCRF:        "mfocrf",
+	MCRXR:         "mcrxr",
+	MTDCRUX:       "mtdcrux",
+	MFDCRUX:       "mfdcrux",
+	LFS:           "lfs",
+	LFSU:          "lfsu",
+	LFSX:          "lfsx",
+	LFSUX:         "lfsux",
+	LFD:           "lfd",
+	LFDU:          "lfdu",
+	LFDX:          "lfdx",
+	LFDUX:         "lfdux",
+	LFIWAX:        "lfiwax",
+	LFIWZX:        "lfiwzx",
+	STFS:          "stfs",
+	STFSU:         "stfsu",
+	STFSX:         "stfsx",
+	STFSUX:        "stfsux",
+	STFD:          "stfd",
+	STFDU:         "stfdu",
+	STFDX:         "stfdx",
+	STFDUX:        "stfdux",
+	STFIWX:        "stfiwx",
+	LFDP:          "lfdp",
+	LFDPX:         "lfdpx",
+	STFDP:         "stfdp",
+	STFDPX:        "stfdpx",
+	FMR:           "fmr",
+	FMR_:          "fmr.",
+	FABS:          "fabs",
+	FABS_:         "fabs.",
+	FNABS:         "fnabs",
+	FNABS_:        "fnabs.",
+	FNEG:          "fneg",
+	FNEG_:         "fneg.",
+	FCPSGN:        "fcpsgn",
+	FCPSGN_:       "fcpsgn.",
+	FMRGEW:        "fmrgew",
+	FMRGOW:        "fmrgow",
+	FADD:          "fadd",
+	FADD_:         "fadd.",
+	FADDS:         "fadds",
+	FADDS_:        "fadds.",
+	FSUB:          "fsub",
+	FSUB_:         "fsub.",
+	FSUBS:         "fsubs",
+	FSUBS_:        "fsubs.",
+	FMUL:          "fmul",
+	FMUL_:         "fmul.",
+	FMULS:         "fmuls",
+	FMULS_:        "fmuls.",
+	FDIV:          "fdiv",
+	FDIV_:         "fdiv.",
+	FDIVS:         "fdivs",
+	FDIVS_:        "fdivs.",
+	FSQRT:         "fsqrt",
+	FSQRT_:        "fsqrt.",
+	FSQRTS:        "fsqrts",
+	FSQRTS_:       "fsqrts.",
+	FRE:           "fre",
+	FRE_:          "fre.",
+	FRES:          "fres",
+	FRES_:         "fres.",
+	FRSQRTE:       "frsqrte",
+	FRSQRTE_:      "frsqrte.",
+	FRSQRTES:      "frsqrtes",
+	FRSQRTES_:     "frsqrtes.",
+	FTDIV:         "ftdiv",
+	FTSQRT:        "ftsqrt",
+	FMADD:         "fmadd",
+	FMADD_:        "fmadd.",
+	FMADDS:        "fmadds",
+	FMADDS_:       "fmadds.",
+	FMSUB:         "fmsub",
+	FMSUB_:        "fmsub.",
+	FMSUBS:        "fmsubs",
+	FMSUBS_:       "fmsubs.",
+	FNMADD:        "fnmadd",
+	FNMADD_:       "fnmadd.",
+	FNMADDS:       "fnmadds",
+	FNMADDS_:      "fnmadds.",
+	FNMSUB:        "fnmsub",
+	FNMSUB_:       "fnmsub.",
+	FNMSUBS:       "fnmsubs",
+	FNMSUBS_:      "fnmsubs.",
+	FRSP:          "frsp",
+	FRSP_:         "frsp.",
+	FCTID:         "fctid",
+	FCTID_:        "fctid.",
+	FCTIDZ:        "fctidz",
+	FCTIDZ_:       "fctidz.",
+	FCTIDU:        "fctidu",
+	FCTIDU_:       "fctidu.",
+	FCTIDUZ:       "fctiduz",
+	FCTIDUZ_:      "fctiduz.",
+	FCTIW:         "fctiw",
+	FCTIW_:        "fctiw.",
+	FCTIWZ:        "fctiwz",
+	FCTIWZ_:       "fctiwz.",
+	FCTIWU:        "fctiwu",
+	FCTIWU_:       "fctiwu.",
+	FCTIWUZ:       "fctiwuz",
+	FCTIWUZ_:      "fctiwuz.",
+	FCFID:         "fcfid",
+	FCFID_:        "fcfid.",
+	FCFIDU:        "fcfidu",
+	FCFIDU_:       "fcfidu.",
+	FCFIDS:        "fcfids",
+	FCFIDS_:       "fcfids.",
+	FCFIDUS:       "fcfidus",
+	FCFIDUS_:      "fcfidus.",
+	FRIN:          "frin",
+	FRIN_:         "frin.",
+	FRIZ:          "friz",
+	FRIZ_:         "friz.",
+	FRIP:          "frip",
+	FRIP_:         "frip.",
+	FRIM:          "frim",
+	FRIM_:         "frim.",
+	FCMPU:         "fcmpu",
+	FCMPO:         "fcmpo",
+	FSEL:          "fsel",
+	FSEL_:         "fsel.",
+	MFFS:          "mffs",
+	MFFS_:         "mffs.",
+	MCRFS:         "mcrfs",
+	MTFSFI:        "mtfsfi",
+	MTFSFI_:       "mtfsfi.",
+	MTFSF:         "mtfsf",
+	MTFSF_:        "mtfsf.",
+	MTFSB0:        "mtfsb0",
+	MTFSB0_:       "mtfsb0.",
+	MTFSB1:        "mtfsb1",
+	MTFSB1_:       "mtfsb1.",
+	LVEBX:         "lvebx",
+	LVEHX:         "lvehx",
+	LVEWX:         "lvewx",
+	LVX:           "lvx",
+	LVXL:          "lvxl",
+	STVEBX:        "stvebx",
+	STVEHX:        "stvehx",
+	STVEWX:        "stvewx",
+	STVX:          "stvx",
+	STVXL:         "stvxl",
+	LVSL:          "lvsl",
+	LVSR:          "lvsr",
+	VPKPX:         "vpkpx",
+	VPKSDSS:       "vpksdss",
+	VPKSDUS:       "vpksdus",
+	VPKSHSS:       "vpkshss",
+	VPKSHUS:       "vpkshus",
+	VPKSWSS:       "vpkswss",
+	VPKSWUS:       "vpkswus",
+	VPKUDUM:       "vpkudum",
+	VPKUDUS:       "vpkudus",
+	VPKUHUM:       "vpkuhum",
+	VPKUHUS:       "vpkuhus",
+	VPKUWUM:       "vpkuwum",
+	VPKUWUS:       "vpkuwus",
+	VUPKHPX:       "vupkhpx",
+	VUPKLPX:       "vupklpx",
+	VUPKHSB:       "vupkhsb",
+	VUPKHSH:       "vupkhsh",
+	VUPKHSW:       "vupkhsw",
+	VUPKLSB:       "vupklsb",
+	VUPKLSH:       "vupklsh",
+	VUPKLSW:       "vupklsw",
+	VMRGHB:        "vmrghb",
+	VMRGHH:        "vmrghh",
+	VMRGLB:        "vmrglb",
+	VMRGLH:        "vmrglh",
+	VMRGHW:        "vmrghw",
+	VMRGLW:        "vmrglw",
+	VMRGEW:        "vmrgew",
+	VMRGOW:        "vmrgow",
+	VSPLTB:        "vspltb",
+	VSPLTH:        "vsplth",
+	VSPLTW:        "vspltw",
+	VSPLTISB:      "vspltisb",
+	VSPLTISH:      "vspltish",
+	VSPLTISW:      "vspltisw",
+	VPERM:         "vperm",
+	VSEL:          "vsel",
+	VSL:           "vsl",
+	VSLDOI:        "vsldoi",
+	VSLO:          "vslo",
+	VSR:           "vsr",
+	VSRO:          "vsro",
+	VADDCUW:       "vaddcuw",
+	VADDSBS:       "vaddsbs",
+	VADDSHS:       "vaddshs",
+	VADDSWS:       "vaddsws",
+	VADDUBM:       "vaddubm",
+	VADDUDM:       "vaddudm",
+	VADDUHM:       "vadduhm",
+	VADDUWM:       "vadduwm",
+	VADDUBS:       "vaddubs",
+	VADDUHS:       "vadduhs",
+	VADDUWS:       "vadduws",
+	VADDUQM:       "vadduqm",
+	VADDEUQM:      "vaddeuqm",
+	VADDCUQ:       "vaddcuq",
+	VADDECUQ:      "vaddecuq",
+	VSUBCUW:       "vsubcuw",
+	VSUBSBS:       "vsubsbs",
+	VSUBSHS:       "vsubshs",
+	VSUBSWS:       "vsubsws",
+	VSUBUBM:       "vsububm",
+	VSUBUDM:       "vsubudm",
+	VSUBUHM:       "vsubuhm",
+	VSUBUWM:       "vsubuwm",
+	VSUBUBS:       "vsububs",
+	VSUBUHS:       "vsubuhs",
+	VSUBUWS:       "vsubuws",
+	VSUBUQM:       "vsubuqm",
+	VSUBEUQM:      "vsubeuqm",
+	VSUBCUQ:       "vsubcuq",
+	VSUBECUQ:      "vsubecuq",
+	VMULESB:       "vmulesb",
+	VMULEUB:       "vmuleub",
+	VMULOSB:       "vmulosb",
+	VMULOUB:       "vmuloub",
+	VMULESH:       "vmulesh",
+	VMULEUH:       "vmuleuh",
+	VMULOSH:       "vmulosh",
+	VMULOUH:       "vmulouh",
+	VMULESW:       "vmulesw",
+	VMULEUW:       "vmuleuw",
+	VMULOSW:       "vmulosw",
+	VMULOUW:       "vmulouw",
+	VMULUWM:       "vmuluwm",
+	VMHADDSHS:     "vmhaddshs",
+	VMHRADDSHS:    "vmhraddshs",
+	VMLADDUHM:     "vmladduhm",
+	VMSUMUBM:      "vmsumubm",
+	VMSUMMBM:      "vmsummbm",
+	VMSUMSHM:      "vmsumshm",
+	VMSUMSHS:      "vmsumshs",
+	VMSUMUHM:      "vmsumuhm",
+	VMSUMUHS:      "vmsumuhs",
+	VSUMSWS:       "vsumsws",
+	VSUM2SWS:      "vsum2sws",
+	VSUM4SBS:      "vsum4sbs",
+	VSUM4SHS:      "vsum4shs",
+	VSUM4UBS:      "vsum4ubs",
+	VAVGSB:        "vavgsb",
+	VAVGSH:        "vavgsh",
+	VAVGSW:        "vavgsw",
+	VAVGUB:        "vavgub",
+	VAVGUW:        "vavguw",
+	VAVGUH:        "vavguh",
+	VMAXSB:        "vmaxsb",
+	VMAXSD:        "vmaxsd",
+	VMAXUB:        "vmaxub",
+	VMAXUD:        "vmaxud",
+	VMAXSH:        "vmaxsh",
+	VMAXSW:        "vmaxsw",
+	VMAXUH:        "vmaxuh",
+	VMAXUW:        "vmaxuw",
+	VMINSB:        "vminsb",
+	VMINSD:        "vminsd",
+	VMINUB:        "vminub",
+	VMINUD:        "vminud",
+	VMINSH:        "vminsh",
+	VMINSW:        "vminsw",
+	VMINUH:        "vminuh",
+	VMINUW:        "vminuw",
+	VCMPEQUB:      "vcmpequb",
+	VCMPEQUB_:     "vcmpequb.",
+	VCMPEQUH:      "vcmpequh",
+	VCMPEQUH_:     "vcmpequh.",
+	VCMPEQUW:      "vcmpequw",
+	VCMPEQUW_:     "vcmpequw.",
+	VCMPEQUD:      "vcmpequd",
+	VCMPEQUD_:     "vcmpequd.",
+	VCMPGTSB:      "vcmpgtsb",
+	VCMPGTSB_:     "vcmpgtsb.",
+	VCMPGTSD:      "vcmpgtsd",
+	VCMPGTSD_:     "vcmpgtsd.",
+	VCMPGTSH:      "vcmpgtsh",
+	VCMPGTSH_:     "vcmpgtsh.",
+	VCMPGTSW:      "vcmpgtsw",
+	VCMPGTSW_:     "vcmpgtsw.",
+	VCMPGTUB:      "vcmpgtub",
+	VCMPGTUB_:     "vcmpgtub.",
+	VCMPGTUD:      "vcmpgtud",
+	VCMPGTUD_:     "vcmpgtud.",
+	VCMPGTUH:      "vcmpgtuh",
+	VCMPGTUH_:     "vcmpgtuh.",
+	VCMPGTUW:      "vcmpgtuw",
+	VCMPGTUW_:     "vcmpgtuw.",
+	VAND:          "vand",
+	VANDC:         "vandc",
+	VEQV:          "veqv",
+	VNAND:         "vnand",
+	VORC:          "vorc",
+	VNOR:          "vnor",
+	VOR:           "vor",
+	VXOR:          "vxor",
+	VRLB:          "vrlb",
+	VRLH:          "vrlh",
+	VRLW:          "vrlw",
+	VRLD:          "vrld",
+	VSLB:          "vslb",
+	VSLH:          "vslh",
+	VSLW:          "vslw",
+	VSLD:          "vsld",
+	VSRB:          "vsrb",
+	VSRH:          "vsrh",
+	VSRW:          "vsrw",
+	VSRD:          "vsrd",
+	VSRAB:         "vsrab",
+	VSRAH:         "vsrah",
+	VSRAW:         "vsraw",
+	VSRAD:         "vsrad",
+	VADDFP:        "vaddfp",
+	VSUBFP:        "vsubfp",
+	VMADDFP:       "vmaddfp",
+	VNMSUBFP:      "vnmsubfp",
+	VMAXFP:        "vmaxfp",
+	VMINFP:        "vminfp",
+	VCTSXS:        "vctsxs",
+	VCTUXS:        "vctuxs",
+	VCFSX:         "vcfsx",
+	VCFUX:         "vcfux",
+	VRFIM:         "vrfim",
+	VRFIN:         "vrfin",
+	VRFIP:         "vrfip",
+	VRFIZ:         "vrfiz",
+	VCMPBFP:       "vcmpbfp",
+	VCMPBFP_:      "vcmpbfp.",
+	VCMPEQFP:      "vcmpeqfp",
+	VCMPEQFP_:     "vcmpeqfp.",
+	VCMPGEFP:      "vcmpgefp",
+	VCMPGEFP_:     "vcmpgefp.",
+	VCMPGTFP:      "vcmpgtfp",
+	VCMPGTFP_:     "vcmpgtfp.",
+	VEXPTEFP:      "vexptefp",
+	VLOGEFP:       "vlogefp",
+	VREFP:         "vrefp",
+	VRSQRTEFP:     "vrsqrtefp",
+	VCIPHER:       "vcipher",
+	VCIPHERLAST:   "vcipherlast",
+	VNCIPHER:      "vncipher",
+	VNCIPHERLAST:  "vncipherlast",
+	VSBOX:         "vsbox",
+	VSHASIGMAD:    "vshasigmad",
+	VSHASIGMAW:    "vshasigmaw",
+	VPMSUMB:       "vpmsumb",
+	VPMSUMD:       "vpmsumd",
+	VPMSUMH:       "vpmsumh",
+	VPMSUMW:       "vpmsumw",
+	VPERMXOR:      "vpermxor",
+	VGBBD:         "vgbbd",
+	VCLZB:         "vclzb",
+	VCLZH:         "vclzh",
+	VCLZW:         "vclzw",
+	VCLZD:         "vclzd",
+	VPOPCNTB:      "vpopcntb",
+	VPOPCNTD:      "vpopcntd",
+	VPOPCNTH:      "vpopcnth",
+	VPOPCNTW:      "vpopcntw",
+	VBPERMQ:       "vbpermq",
+	BCDADD_:       "bcdadd.",
+	BCDSUB_:       "bcdsub.",
+	MTVSCR:        "mtvscr",
+	MFVSCR:        "mfvscr",
+	DADD:          "dadd",
+	DADD_:         "dadd.",
+	DSUB:          "dsub",
+	DSUB_:         "dsub.",
+	DMUL:          "dmul",
+	DMUL_:         "dmul.",
+	DDIV:          "ddiv",
+	DDIV_:         "ddiv.",
+	DCMPU:         "dcmpu",
+	DCMPO:         "dcmpo",
+	DTSTDC:        "dtstdc",
+	DTSTDG:        "dtstdg",
+	DTSTEX:        "dtstex",
+	DTSTSF:        "dtstsf",
+	DQUAI:         "dquai",
+	DQUAI_:        "dquai.",
+	DQUA:          "dqua",
+	DQUA_:         "dqua.",
+	DRRND:         "drrnd",
+	DRRND_:        "drrnd.",
+	DRINTX:        "drintx",
+	DRINTX_:       "drintx.",
+	DRINTN:        "drintn",
+	DRINTN_:       "drintn.",
+	DCTDP:         "dctdp",
+	DCTDP_:        "dctdp.",
+	DCTQPQ:        "dctqpq",
+	DCTQPQ_:       "dctqpq.",
+	DRSP:          "drsp",
+	DRSP_:         "drsp.",
+	DRDPQ:         "drdpq",
+	DRDPQ_:        "drdpq.",
+	DCFFIX:        "dcffix",
+	DCFFIX_:       "dcffix.",
+	DCFFIXQ:       "dcffixq",
+	DCFFIXQ_:      "dcffixq.",
+	DCTFIX:        "dctfix",
+	DCTFIX_:       "dctfix.",
+	DDEDPD:        "ddedpd",
+	DDEDPD_:       "ddedpd.",
+	DENBCD:        "denbcd",
+	DENBCD_:       "denbcd.",
+	DXEX:          "dxex",
+	DXEX_:         "dxex.",
+	DIEX:          "diex",
+	DIEX_:         "diex.",
+	DSCLI:         "dscli",
+	DSCLI_:        "dscli.",
+	DSCRI:         "dscri",
+	DSCRI_:        "dscri.",
+	LXSDX:         "lxsdx",
+	LXSIWAX:       "lxsiwax",
+	LXSIWZX:       "lxsiwzx",
+	LXSSPX:        "lxsspx",
+	LXVD2X:        "lxvd2x",
+	LXVDSX:        "lxvdsx",
+	LXVW4X:        "lxvw4x",
+	STXSDX:        "stxsdx",
+	STXSIWX:       "stxsiwx",
+	STXSSPX:       "stxsspx",
+	STXVD2X:       "stxvd2x",
+	STXVW4X:       "stxvw4x",
+	XSABSDP:       "xsabsdp",
+	XSADDDP:       "xsadddp",
+	XSADDSP:       "xsaddsp",
+	XSCMPODP:      "xscmpodp",
+	XSCMPUDP:      "xscmpudp",
+	XSCPSGNDP:     "xscpsgndp",
+	XSCVDPSP:      "xscvdpsp",
+	XSCVDPSPN:     "xscvdpspn",
+	XSCVDPSXDS:    "xscvdpsxds",
+	XSCVDPSXWS:    "xscvdpsxws",
+	XSCVDPUXDS:    "xscvdpuxds",
+	XSCVDPUXWS:    "xscvdpuxws",
+	XSCVSPDP:      "xscvspdp",
+	XSCVSPDPN:     "xscvspdpn",
+	XSCVSXDDP:     "xscvsxddp",
+	XSCVSXDSP:     "xscvsxdsp",
+	XSCVUXDDP:     "xscvuxddp",
+	XSCVUXDSP:     "xscvuxdsp",
+	XSDIVDP:       "xsdivdp",
+	XSDIVSP:       "xsdivsp",
+	XSMADDADP:     "xsmaddadp",
+	XSMADDASP:     "xsmaddasp",
+	XSMAXDP:       "xsmaxdp",
+	XSMINDP:       "xsmindp",
+	XSMSUBADP:     "xsmsubadp",
+	XSMSUBASP:     "xsmsubasp",
+	XSMULDP:       "xsmuldp",
+	XSMULSP:       "xsmulsp",
+	XSNABSDP:      "xsnabsdp",
+	XSNEGDP:       "xsnegdp",
+	XSNMADDADP:    "xsnmaddadp",
+	XSNMADDASP:    "xsnmaddasp",
+	XSNMSUBADP:    "xsnmsubadp",
+	XSNMSUBASP:    "xsnmsubasp",
+	XSRDPI:        "xsrdpi",
+	XSRDPIC:       "xsrdpic",
+	XSRDPIM:       "xsrdpim",
+	XSRDPIP:       "xsrdpip",
+	XSRDPIZ:       "xsrdpiz",
+	XSREDP:        "xsredp",
+	XSRESP:        "xsresp",
+	XSRSP:         "xsrsp",
+	XSRSQRTEDP:    "xsrsqrtedp",
+	XSRSQRTESP:    "xsrsqrtesp",
+	XSSQRTDP:      "xssqrtdp",
+	XSSQRTSP:      "xssqrtsp",
+	XSSUBDP:       "xssubdp",
+	XSSUBSP:       "xssubsp",
+	XSTDIVDP:      "xstdivdp",
+	XSTSQRTDP:     "xstsqrtdp",
+	XVABSDP:       "xvabsdp",
+	XVABSSP:       "xvabssp",
+	XVADDDP:       "xvadddp",
+	XVADDSP:       "xvaddsp",
+	XVCMPEQDP:     "xvcmpeqdp",
+	XVCMPEQDP_:    "xvcmpeqdp.",
+	XVCMPEQSP:     "xvcmpeqsp",
+	XVCMPEQSP_:    "xvcmpeqsp.",
+	XVCMPGEDP:     "xvcmpgedp",
+	XVCMPGEDP_:    "xvcmpgedp.",
+	XVCMPGESP:     "xvcmpgesp",
+	XVCMPGESP_:    "xvcmpgesp.",
+	XVCMPGTDP:     "xvcmpgtdp",
+	XVCMPGTDP_:    "xvcmpgtdp.",
+	XVCMPGTSP:     "xvcmpgtsp",
+	XVCMPGTSP_:    "xvcmpgtsp.",
+	XVCPSGNDP:     "xvcpsgndp",
+	XVCPSGNSP:     "xvcpsgnsp",
+	XVCVDPSP:      "xvcvdpsp",
+	XVCVDPSXDS:    "xvcvdpsxds",
+	XVCVDPSXWS:    "xvcvdpsxws",
+	XVCVDPUXDS:    "xvcvdpuxds",
+	XVCVDPUXWS:    "xvcvdpuxws",
+	XVCVSPDP:      "xvcvspdp",
+	XVCVSPSXDS:    "xvcvspsxds",
+	XVCVSPSXWS:    "xvcvspsxws",
+	XVCVSPUXDS:    "xvcvspuxds",
+	XVCVSPUXWS:    "xvcvspuxws",
+	XVCVSXDDP:     "xvcvsxddp",
+	XVCVSXDSP:     "xvcvsxdsp",
+	XVCVSXWDP:     "xvcvsxwdp",
+	XVCVSXWSP:     "xvcvsxwsp",
+	XVCVUXDDP:     "xvcvuxddp",
+	XVCVUXDSP:     "xvcvuxdsp",
+	XVCVUXWDP:     "xvcvuxwdp",
+	XVCVUXWSP:     "xvcvuxwsp",
+	XVDIVDP:       "xvdivdp",
+	XVDIVSP:       "xvdivsp",
+	XVMADDADP:     "xvmaddadp",
+	XVMADDASP:     "xvmaddasp",
+	XVMAXDP:       "xvmaxdp",
+	XVMAXSP:       "xvmaxsp",
+	XVMINDP:       "xvmindp",
+	XVMINSP:       "xvminsp",
+	XVMSUBADP:     "xvmsubadp",
+	XVMSUBASP:     "xvmsubasp",
+	XVMULDP:       "xvmuldp",
+	XVMULSP:       "xvmulsp",
+	XVNABSDP:      "xvnabsdp",
+	XVNABSSP:      "xvnabssp",
+	XVNEGDP:       "xvnegdp",
+	XVNEGSP:       "xvnegsp",
+	XVNMADDADP:    "xvnmaddadp",
+	XVNMADDASP:    "xvnmaddasp",
+	XVNMSUBADP:    "xvnmsubadp",
+	XVNMSUBASP:    "xvnmsubasp",
+	XVRDPI:        "xvrdpi",
+	XVRDPIC:       "xvrdpic",
+	XVRDPIM:       "xvrdpim",
+	XVRDPIP:       "xvrdpip",
+	XVRDPIZ:       "xvrdpiz",
+	XVREDP:        "xvredp",
+	XVRESP:        "xvresp",
+	XVRSPI:        "xvrspi",
+	XVRSPIC:       "xvrspic",
+	XVRSPIM:       "xvrspim",
+	XVRSPIP:       "xvrspip",
+	XVRSPIZ:       "xvrspiz",
+	XVRSQRTEDP:    "xvrsqrtedp",
+	XVRSQRTESP:    "xvrsqrtesp",
+	XVSQRTDP:      "xvsqrtdp",
+	XVSQRTSP:      "xvsqrtsp",
+	XVSUBDP:       "xvsubdp",
+	XVSUBSP:       "xvsubsp",
+	XVTDIVDP:      "xvtdivdp",
+	XVTDIVSP:      "xvtdivsp",
+	XVTSQRTDP:     "xvtsqrtdp",
+	XVTSQRTSP:     "xvtsqrtsp",
+	XXLAND:        "xxland",
+	XXLANDC:       "xxlandc",
+	XXLEQV:        "xxleqv",
+	XXLNAND:       "xxlnand",
+	XXLORC:        "xxlorc",
+	XXLNOR:        "xxlnor",
+	XXLOR:         "xxlor",
+	XXLXOR:        "xxlxor",
+	XXMRGHW:       "xxmrghw",
+	XXMRGLW:       "xxmrglw",
+	XXPERMDI:      "xxpermdi",
+	XXSEL:         "xxsel",
+	XXSLDWI:       "xxsldwi",
+	XXSPLTW:       "xxspltw",
+	BRINC:         "brinc",
+	EVABS:         "evabs",
+	EVADDIW:       "evaddiw",
+	EVADDSMIAAW:   "evaddsmiaaw",
+	EVADDSSIAAW:   "evaddssiaaw",
+	EVADDUMIAAW:   "evaddumiaaw",
+	EVADDUSIAAW:   "evaddusiaaw",
+	EVADDW:        "evaddw",
+	EVAND:         "evand",
+	EVCMPEQ:       "evcmpeq",
+	EVANDC:        "evandc",
+	EVCMPGTS:      "evcmpgts",
+	EVCMPGTU:      "evcmpgtu",
+	EVCMPLTU:      "evcmpltu",
+	EVCMPLTS:      "evcmplts",
+	EVCNTLSW:      "evcntlsw",
+	EVCNTLZW:      "evcntlzw",
+	EVDIVWS:       "evdivws",
+	EVDIVWU:       "evdivwu",
+	EVEQV:         "eveqv",
+	EVEXTSB:       "evextsb",
+	EVEXTSH:       "evextsh",
+	EVLDD:         "evldd",
+	EVLDH:         "evldh",
+	EVLDDX:        "evlddx",
+	EVLDHX:        "evldhx",
+	EVLDW:         "evldw",
+	EVLHHESPLAT:   "evlhhesplat",
+	EVLDWX:        "evldwx",
+	EVLHHESPLATX:  "evlhhesplatx",
+	EVLHHOSSPLAT:  "evlhhossplat",
+	EVLHHOUSPLAT:  "evlhhousplat",
+	EVLHHOSSPLATX: "evlhhossplatx",
+	EVLHHOUSPLATX: "evlhhousplatx",
+	EVLWHE:        "evlwhe",
+	EVLWHOS:       "evlwhos",
+	EVLWHEX:       "evlwhex",
+	EVLWHOSX:      "evlwhosx",
+	EVLWHOU:       "evlwhou",
+	EVLWHSPLAT:    "evlwhsplat",
+	EVLWHOUX:      "evlwhoux",
+	EVLWHSPLATX:   "evlwhsplatx",
+	EVLWWSPLAT:    "evlwwsplat",
+	EVMERGEHI:     "evmergehi",
+	EVLWWSPLATX:   "evlwwsplatx",
+	EVMERGELO:     "evmergelo",
+	EVMERGEHILO:   "evmergehilo",
+	EVMHEGSMFAA:   "evmhegsmfaa",
+	EVMERGELOHI:   "evmergelohi",
+	EVMHEGSMFAN:   "evmhegsmfan",
+	EVMHEGSMIAA:   "evmhegsmiaa",
+	EVMHEGUMIAA:   "evmhegumiaa",
+	EVMHEGSMIAN:   "evmhegsmian",
+	EVMHEGUMIAN:   "evmhegumian",
+	EVMHESMF:      "evmhesmf",
+	EVMHESMFAAW:   "evmhesmfaaw",
+	EVMHESMFA:     "evmhesmfa",
+	EVMHESMFANW:   "evmhesmfanw",
+	EVMHESMI:      "evmhesmi",
+	EVMHESMIAAW:   "evmhesmiaaw",
+	EVMHESMIA:     "evmhesmia",
+	EVMHESMIANW:   "evmhesmianw",
+	EVMHESSF:      "evmhessf",
+	EVMHESSFA:     "evmhessfa",
+	EVMHESSFAAW:   "evmhessfaaw",
+	EVMHESSFANW:   "evmhessfanw",
+	EVMHESSIAAW:   "evmhessiaaw",
+	EVMHESSIANW:   "evmhessianw",
+	EVMHEUMI:      "evmheumi",
+	EVMHEUMIAAW:   "evmheumiaaw",
+	EVMHEUMIA:     "evmheumia",
+	EVMHEUMIANW:   "evmheumianw",
+	EVMHEUSIAAW:   "evmheusiaaw",
+	EVMHEUSIANW:   "evmheusianw",
+	EVMHOGSMFAA:   "evmhogsmfaa",
+	EVMHOGSMIAA:   "evmhogsmiaa",
+	EVMHOGSMFAN:   "evmhogsmfan",
+	EVMHOGSMIAN:   "evmhogsmian",
+	EVMHOGUMIAA:   "evmhogumiaa",
+	EVMHOSMF:      "evmhosmf",
+	EVMHOGUMIAN:   "evmhogumian",
+	EVMHOSMFA:     "evmhosmfa",
+	EVMHOSMFAAW:   "evmhosmfaaw",
+	EVMHOSMI:      "evmhosmi",
+	EVMHOSMFANW:   "evmhosmfanw",
+	EVMHOSMIA:     "evmhosmia",
+	EVMHOSMIAAW:   "evmhosmiaaw",
+	EVMHOSMIANW:   "evmhosmianw",
+	EVMHOSSF:      "evmhossf",
+	EVMHOSSFA:     "evmhossfa",
+	EVMHOSSFAAW:   "evmhossfaaw",
+	EVMHOSSFANW:   "evmhossfanw",
+	EVMHOSSIAAW:   "evmhossiaaw",
+	EVMHOUMI:      "evmhoumi",
+	EVMHOSSIANW:   "evmhossianw",
+	EVMHOUMIA:     "evmhoumia",
+	EVMHOUMIAAW:   "evmhoumiaaw",
+	EVMHOUSIAAW:   "evmhousiaaw",
+	EVMHOUMIANW:   "evmhoumianw",
+	EVMHOUSIANW:   "evmhousianw",
+	EVMRA:         "evmra",
+	EVMWHSMF:      "evmwhsmf",
+	EVMWHSMI:      "evmwhsmi",
+	EVMWHSMFA:     "evmwhsmfa",
+	EVMWHSMIA:     "evmwhsmia",
+	EVMWHSSF:      "evmwhssf",
+	EVMWHUMI:      "evmwhumi",
+	EVMWHSSFA:     "evmwhssfa",
+	EVMWHUMIA:     "evmwhumia",
+	EVMWLSMIAAW:   "evmwlsmiaaw",
+	EVMWLSSIAAW:   "evmwlssiaaw",
+	EVMWLSMIANW:   "evmwlsmianw",
+	EVMWLSSIANW:   "evmwlssianw",
+	EVMWLUMI:      "evmwlumi",
+	EVMWLUMIAAW:   "evmwlumiaaw",
+	EVMWLUMIA:     "evmwlumia",
+	EVMWLUMIANW:   "evmwlumianw",
+	EVMWLUSIAAW:   "evmwlusiaaw",
+	EVMWSMF:       "evmwsmf",
+	EVMWLUSIANW:   "evmwlusianw",
+	EVMWSMFA:      "evmwsmfa",
+	EVMWSMFAA:     "evmwsmfaa",
+	EVMWSMI:       "evmwsmi",
+	EVMWSMIAA:     "evmwsmiaa",
+	EVMWSMFAN:     "evmwsmfan",
+	EVMWSMIA:      "evmwsmia",
+	EVMWSMIAN:     "evmwsmian",
+	EVMWSSF:       "evmwssf",
+	EVMWSSFA:      "evmwssfa",
+	EVMWSSFAA:     "evmwssfaa",
+	EVMWUMI:       "evmwumi",
+	EVMWSSFAN:     "evmwssfan",
+	EVMWUMIA:      "evmwumia",
+	EVMWUMIAA:     "evmwumiaa",
+	EVNAND:        "evnand",
+	EVMWUMIAN:     "evmwumian",
+	EVNEG:         "evneg",
+	EVNOR:         "evnor",
+	EVORC:         "evorc",
+	EVOR:          "evor",
+	EVRLW:         "evrlw",
+	EVRLWI:        "evrlwi",
+	EVSEL:         "evsel",
+	EVRNDW:        "evrndw",
+	EVSLW:         "evslw",
+	EVSPLATFI:     "evsplatfi",
+	EVSRWIS:       "evsrwis",
+	EVSLWI:        "evslwi",
+	EVSPLATI:      "evsplati",
+	EVSRWIU:       "evsrwiu",
+	EVSRWS:        "evsrws",
+	EVSTDD:        "evstdd",
+	EVSRWU:        "evsrwu",
+	EVSTDDX:       "evstddx",
+	EVSTDH:        "evstdh",
+	EVSTDW:        "evstdw",
+	EVSTDHX:       "evstdhx",
+	EVSTDWX:       "evstdwx",
+	EVSTWHE:       "evstwhe",
+	EVSTWHO:       "evstwho",
+	EVSTWWE:       "evstwwe",
+	EVSTWHEX:      "evstwhex",
+	EVSTWHOX:      "evstwhox",
+	EVSTWWEX:      "evstwwex",
+	EVSTWWO:       "evstwwo",
+	EVSUBFSMIAAW:  "evsubfsmiaaw",
+	EVSTWWOX:      "evstwwox",
+	EVSUBFSSIAAW:  "evsubfssiaaw",
+	EVSUBFUMIAAW:  "evsubfumiaaw",
+	EVSUBFUSIAAW:  "evsubfusiaaw",
+	EVSUBFW:       "evsubfw",
+	EVSUBIFW:      "evsubifw",
+	EVXOR:         "evxor",
+	EVFSABS:       "evfsabs",
+	EVFSNABS:      "evfsnabs",
+	EVFSNEG:       "evfsneg",
+	EVFSADD:       "evfsadd",
+	EVFSMUL:       "evfsmul",
+	EVFSSUB:       "evfssub",
+	EVFSDIV:       "evfsdiv",
+	EVFSCMPGT:     "evfscmpgt",
+	EVFSCMPLT:     "evfscmplt",
+	EVFSCMPEQ:     "evfscmpeq",
+	EVFSTSTGT:     "evfststgt",
+	EVFSTSTLT:     "evfststlt",
+	EVFSTSTEQ:     "evfststeq",
+	EVFSCFSI:      "evfscfsi",
+	EVFSCFSF:      "evfscfsf",
+	EVFSCFUI:      "evfscfui",
+	EVFSCFUF:      "evfscfuf",
+	EVFSCTSI:      "evfsctsi",
+	EVFSCTUI:      "evfsctui",
+	EVFSCTSIZ:     "evfsctsiz",
+	EVFSCTUIZ:     "evfsctuiz",
+	EVFSCTSF:      "evfsctsf",
+	EVFSCTUF:      "evfsctuf",
+	EFSABS:        "efsabs",
+	EFSNEG:        "efsneg",
+	EFSNABS:       "efsnabs",
+	EFSADD:        "efsadd",
+	EFSMUL:        "efsmul",
+	EFSSUB:        "efssub",
+	EFSDIV:        "efsdiv",
+	EFSCMPGT:      "efscmpgt",
+	EFSCMPLT:      "efscmplt",
+	EFSCMPEQ:      "efscmpeq",
+	EFSTSTGT:      "efststgt",
+	EFSTSTLT:      "efststlt",
+	EFSTSTEQ:      "efststeq",
+	EFSCFSI:       "efscfsi",
+	EFSCFSF:       "efscfsf",
+	EFSCTSI:       "efsctsi",
+	EFSCFUI:       "efscfui",
+	EFSCFUF:       "efscfuf",
+	EFSCTUI:       "efsctui",
+	EFSCTSIZ:      "efsctsiz",
+	EFSCTSF:       "efsctsf",
+	EFSCTUIZ:      "efsctuiz",
+	EFSCTUF:       "efsctuf",
+	EFDABS:        "efdabs",
+	EFDNEG:        "efdneg",
+	EFDNABS:       "efdnabs",
+	EFDADD:        "efdadd",
+	EFDMUL:        "efdmul",
+	EFDSUB:        "efdsub",
+	EFDDIV:        "efddiv",
+	EFDCMPGT:      "efdcmpgt",
+	EFDCMPEQ:      "efdcmpeq",
+	EFDCMPLT:      "efdcmplt",
+	EFDTSTGT:      "efdtstgt",
+	EFDTSTLT:      "efdtstlt",
+	EFDCFSI:       "efdcfsi",
+	EFDTSTEQ:      "efdtsteq",
+	EFDCFUI:       "efdcfui",
+	EFDCFSID:      "efdcfsid",
+	EFDCFSF:       "efdcfsf",
+	EFDCFUF:       "efdcfuf",
+	EFDCFUID:      "efdcfuid",
+	EFDCTSI:       "efdctsi",
+	EFDCTUI:       "efdctui",
+	EFDCTSIDZ:     "efdctsidz",
+	EFDCTUIDZ:     "efdctuidz",
+	EFDCTSIZ:      "efdctsiz",
+	EFDCTSF:       "efdctsf",
+	EFDCTUF:       "efdctuf",
+	EFDCTUIZ:      "efdctuiz",
+	EFDCFS:        "efdcfs",
+	EFSCFD:        "efscfd",
+	DLMZB:         "dlmzb",
+	DLMZB_:        "dlmzb.",
+	MACCHW:        "macchw",
+	MACCHW_:       "macchw.",
+	MACCHWO:       "macchwo",
+	MACCHWO_:      "macchwo.",
+	MACCHWS:       "macchws",
+	MACCHWS_:      "macchws.",
+	MACCHWSO:      "macchwso",
+	MACCHWSO_:     "macchwso.",
+	MACCHWU:       "macchwu",
+	MACCHWU_:      "macchwu.",
+	MACCHWUO:      "macchwuo",
+	MACCHWUO_:     "macchwuo.",
+	MACCHWSU:      "macchwsu",
+	MACCHWSU_:     "macchwsu.",
+	MACCHWSUO:     "macchwsuo",
+	MACCHWSUO_:    "macchwsuo.",
+	MACHHW:        "machhw",
+	MACHHW_:       "machhw.",
+	MACHHWO:       "machhwo",
+	MACHHWO_:      "machhwo.",
+	MACHHWS:       "machhws",
+	MACHHWS_:      "machhws.",
+	MACHHWSO:      "machhwso",
+	MACHHWSO_:     "machhwso.",
+	MACHHWU:       "machhwu",
+	MACHHWU_:      "machhwu.",
+	MACHHWUO:      "machhwuo",
+	MACHHWUO_:     "machhwuo.",
+	MACHHWSU:      "machhwsu",
+	MACHHWSU_:     "machhwsu.",
+	MACHHWSUO:     "machhwsuo",
+	MACHHWSUO_:    "machhwsuo.",
+	MACLHW:        "maclhw",
+	MACLHW_:       "maclhw.",
+	MACLHWO:       "maclhwo",
+	MACLHWO_:      "maclhwo.",
+	MACLHWS:       "maclhws",
+	MACLHWS_:      "maclhws.",
+	MACLHWSO:      "maclhwso",
+	MACLHWSO_:     "maclhwso.",
+	MACLHWU:       "maclhwu",
+	MACLHWU_:      "maclhwu.",
+	MACLHWUO:      "maclhwuo",
+	MACLHWUO_:     "maclhwuo.",
+	MULCHW:        "mulchw",
+	MULCHW_:       "mulchw.",
+	MACLHWSU:      "maclhwsu",
+	MACLHWSU_:     "maclhwsu.",
+	MACLHWSUO:     "maclhwsuo",
+	MACLHWSUO_:    "maclhwsuo.",
+	MULCHWU:       "mulchwu",
+	MULCHWU_:      "mulchwu.",
+	MULHHW:        "mulhhw",
+	MULHHW_:       "mulhhw.",
+	MULLHW:        "mullhw",
+	MULLHW_:       "mullhw.",
+	MULHHWU:       "mulhhwu",
+	MULHHWU_:      "mulhhwu.",
+	MULLHWU:       "mullhwu",
+	MULLHWU_:      "mullhwu.",
+	NMACCHW:       "nmacchw",
+	NMACCHW_:      "nmacchw.",
+	NMACCHWO:      "nmacchwo",
+	NMACCHWO_:     "nmacchwo.",
+	NMACCHWS:      "nmacchws",
+	NMACCHWS_:     "nmacchws.",
+	NMACCHWSO:     "nmacchwso",
+	NMACCHWSO_:    "nmacchwso.",
+	NMACHHW:       "nmachhw",
+	NMACHHW_:      "nmachhw.",
+	NMACHHWO:      "nmachhwo",
+	NMACHHWO_:     "nmachhwo.",
+	NMACHHWS:      "nmachhws",
+	NMACHHWS_:     "nmachhws.",
+	NMACHHWSO:     "nmachhwso",
+	NMACHHWSO_:    "nmachhwso.",
+	NMACLHW:       "nmaclhw",
+	NMACLHW_:      "nmaclhw.",
+	NMACLHWO:      "nmaclhwo",
+	NMACLHWO_:     "nmaclhwo.",
+	NMACLHWS:      "nmaclhws",
+	NMACLHWS_:     "nmaclhws.",
+	NMACLHWSO:     "nmaclhwso",
+	NMACLHWSO_:    "nmaclhwso.",
+	ICBI:          "icbi",
+	ICBT:          "icbt",
+	DCBA:          "dcba",
+	DCBT:          "dcbt",
+	DCBTST:        "dcbtst",
+	DCBZ:          "dcbz",
+	DCBST:         "dcbst",
+	DCBF:          "dcbf",
+	ISYNC:         "isync",
+	LBARX:         "lbarx",
+	LHARX:         "lharx",
+	LWARX:         "lwarx",
+	STBCX_:        "stbcx.",
+	STHCX_:        "sthcx.",
+	STWCX_:        "stwcx.",
+	LDARX:         "ldarx",
+	STDCX_:        "stdcx.",
+	LQARX:         "lqarx",
+	STQCX_:        "stqcx.",
+	SYNC:          "sync",
+	EIEIO:         "eieio",
+	MBAR:          "mbar",
+	WAIT:          "wait",
+	TBEGIN_:       "tbegin.",
+	TEND_:         "tend.",
+	TABORT_:       "tabort.",
+	TABORTWC_:     "tabortwc.",
+	TABORTWCI_:    "tabortwci.",
+	TABORTDC_:     "tabortdc.",
+	TABORTDCI_:    "tabortdci.",
+	TSR_:          "tsr.",
+	TCHECK:        "tcheck",
+	MFTB:          "mftb",
+	RFEBB:         "rfebb",
+	LBDX:          "lbdx",
+	LHDX:          "lhdx",
+	LWDX:          "lwdx",
+	LDDX:          "lddx",
+	LFDDX:         "lfddx",
+	STBDX:         "stbdx",
+	STHDX:         "sthdx",
+	STWDX:         "stwdx",
+	STDDX:         "stddx",
+	STFDDX:        "stfddx",
+	DSN:           "dsn",
+	ECIWX:         "eciwx",
+	ECOWX:         "ecowx",
+	RFID:          "rfid",
+	HRFID:         "hrfid",
+	DOZE:          "doze",
+	NAP:           "nap",
+	SLEEP:         "sleep",
+	RVWINKLE:      "rvwinkle",
+	LBZCIX:        "lbzcix",
+	LWZCIX:        "lwzcix",
+	LHZCIX:        "lhzcix",
+	LDCIX:         "ldcix",
+	STBCIX:        "stbcix",
+	STWCIX:        "stwcix",
+	STHCIX:        "sthcix",
+	STDCIX:        "stdcix",
+	TRECLAIM_:     "treclaim.",
+	TRECHKPT_:     "trechkpt.",
+	MTMSR:         "mtmsr",
+	MTMSRD:        "mtmsrd",
+	MFMSR:         "mfmsr",
+	SLBIE:         "slbie",
+	SLBIA:         "slbia",
+	SLBMTE:        "slbmte",
+	SLBMFEV:       "slbmfev",
+	SLBMFEE:       "slbmfee",
+	SLBFEE_:       "slbfee.",
+	MTSR:          "mtsr",
+	MTSRIN:        "mtsrin",
+	MFSR:          "mfsr",
+	MFSRIN:        "mfsrin",
+	TLBIE:         "tlbie",
+	TLBIEL:        "tlbiel",
+	TLBIA:         "tlbia",
+	TLBSYNC:       "tlbsync",
+	MSGSND:        "msgsnd",
+	MSGCLR:        "msgclr",
+	MSGSNDP:       "msgsndp",
+	MSGCLRP:       "msgclrp",
+	MTTMR:         "mttmr",
+	RFI:           "rfi",
+	RFCI:          "rfci",
+	RFDI:          "rfdi",
+	RFMCI:         "rfmci",
+	RFGI:          "rfgi",
+	EHPRIV:        "ehpriv",
+	MTDCR:         "mtdcr",
+	MTDCRX:        "mtdcrx",
+	MFDCR:         "mfdcr",
+	MFDCRX:        "mfdcrx",
+	WRTEE:         "wrtee",
+	WRTEEI:        "wrteei",
+	LBEPX:         "lbepx",
+	LHEPX:         "lhepx",
+	LWEPX:         "lwepx",
+	LDEPX:         "ldepx",
+	STBEPX:        "stbepx",
+	STHEPX:        "sthepx",
+	STWEPX:        "stwepx",
+	STDEPX:        "stdepx",
+	DCBSTEP:       "dcbstep",
+	DCBTEP:        "dcbtep",
+	DCBFEP:        "dcbfep",
+	DCBTSTEP:      "dcbtstep",
+	ICBIEP:        "icbiep",
+	DCBZEP:        "dcbzep",
+	LFDEPX:        "lfdepx",
+	STFDEPX:       "stfdepx",
+	EVLDDEPX:      "evlddepx",
+	EVSTDDEPX:     "evstddepx",
+	LVEPX:         "lvepx",
+	LVEPXL:        "lvepxl",
+	STVEPX:        "stvepx",
+	STVEPXL:       "stvepxl",
+	DCBI:          "dcbi",
+	DCBLQ_:        "dcblq.",
+	ICBLQ_:        "icblq.",
+	DCBTLS:        "dcbtls",
+	DCBTSTLS:      "dcbtstls",
+	ICBTLS:        "icbtls",
+	ICBLC:         "icblc",
+	DCBLC:         "dcblc",
+	TLBIVAX:       "tlbivax",
+	TLBILX:        "tlbilx",
+	TLBSX:         "tlbsx",
+	TLBSRX_:       "tlbsrx.",
+	TLBRE:         "tlbre",
+	TLBWE:         "tlbwe",
+	DNH:           "dnh",
+	DCI:           "dci",
+	ICI:           "ici",
+	DCREAD:        "dcread",
+	ICREAD:        "icread",
+	MFPMR:         "mfpmr",
+	MTPMR:         "mtpmr",
+}
+
+var (
+	ap_Reg_11_15               = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}}
+	ap_Reg_6_10                = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}}
+	ap_PCRel_6_29_shift2       = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}}
+	ap_Label_6_29_shift2       = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}}
+	ap_ImmUnsigned_6_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}}
+	ap_CondRegBit_11_15        = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}}
+	ap_PCRel_16_29_shift2      = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}}
+	ap_Label_16_29_shift2      = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}}
+	ap_ImmUnsigned_19_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}}
+	ap_CondRegBit_6_10         = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}}
+	ap_CondRegBit_16_20        = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}}
+	ap_CondRegField_6_8        = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}}
+	ap_CondRegField_11_13      = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}}
+	ap_ImmUnsigned_20_26       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}}
+	ap_SpReg_11_20             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}}
+	ap_Offset_16_31            = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}}
+	ap_Reg_16_20               = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}}
+	ap_Offset_16_29_shift2     = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}}
+	ap_Offset_16_27_shift4     = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}}
+	ap_ImmUnsigned_16_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}}
+	ap_ImmSigned_16_31         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}}
+	ap_ImmUnsigned_16_31       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}}
+	ap_CondRegBit_21_25        = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}}
+	ap_ImmUnsigned_21_25       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}}
+	ap_ImmUnsigned_26_30       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}}
+	ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
+	ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}}
+	ap_SpReg_16_20_11_15       = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}}
+	ap_ImmUnsigned_12_19       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}}
+	ap_ImmUnsigned_10_10       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}}
+	ap_VecReg_31_31_6_10       = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}}
+	ap_FPReg_6_10              = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}}
+	ap_FPReg_16_20             = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}}
+	ap_FPReg_11_15             = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}}
+	ap_FPReg_21_25             = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}}
+	ap_ImmUnsigned_16_19       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}}
+	ap_ImmUnsigned_15_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}}
+	ap_ImmUnsigned_7_14        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}}
+	ap_ImmUnsigned_6_6         = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}}
+	ap_VecReg_6_10             = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}}
+	ap_VecReg_11_15            = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}}
+	ap_VecReg_16_20            = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}}
+	ap_ImmUnsigned_12_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}}
+	ap_ImmUnsigned_13_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}}
+	ap_ImmUnsigned_14_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}}
+	ap_ImmSigned_11_15         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}}
+	ap_VecReg_21_25            = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}}
+	ap_ImmUnsigned_22_25       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}}
+	ap_ImmUnsigned_11_15       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}}
+	ap_ImmUnsigned_16_16       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}}
+	ap_ImmUnsigned_17_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}}
+	ap_ImmUnsigned_22_22       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}}
+	ap_ImmUnsigned_16_21       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}}
+	ap_ImmUnsigned_21_22       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
+	ap_ImmUnsigned_11_12       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
+	ap_ImmUnsigned_11_11       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
+	ap_VecReg_30_30_16_20      = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
+	ap_VecReg_29_29_11_15      = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
+	ap_ImmUnsigned_22_23       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
+	ap_VecReg_28_28_21_25      = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}}
+	ap_CondRegField_29_31      = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}}
+	ap_ImmUnsigned_7_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}}
+	ap_ImmUnsigned_9_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}}
+	ap_ImmUnsigned_31_31       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}}
+	ap_ImmSigned_16_20         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}}
+	ap_ImmUnsigned_20_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}}
+	ap_ImmUnsigned_8_10        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}}
+	ap_SpReg_12_15             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}}
+	ap_ImmUnsigned_6_20        = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}}
+	ap_ImmUnsigned_11_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}}
+)
+
+var instFormats = [...]instFormat{
+	{CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{CNTLZW_, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr)
+		[5]*argField{ap_PCRel_6_29_shift2}},
+	{BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr)
+		[5]*argField{ap_Label_6_29_shift2}},
+	{BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr)
+		[5]*argField{ap_PCRel_6_29_shift2}},
+	{BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr)
+		[5]*argField{ap_Label_6_29_shift2}},
+	{BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
+	{BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
+	{BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
+	{BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
+	{BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+	{BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+	{BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+	{BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+	{BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+	{BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
+	{CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA)
+		[5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
+	{CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB)
+		[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
+	{SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
+		[5]*argField{ap_ImmUnsigned_20_26}},
+	{CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb)
+		[5]*argField{}},
+	{MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From Branch History Rolling Buffer XFX-form (mfbhrbe RT,BHRBE)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
+	{LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+	{STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+	{LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+	{STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI)
+		[5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
+	{ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT, SI)
+		[5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
+	{ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADD_, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDO_, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBF_, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFO_, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDIC_, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDC_, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDCO_, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFC_, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFCO_, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDE_, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDEO_, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDME_, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDMEO_, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFE_, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFEO_, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFME_, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFMEO_, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDZE_, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{ADDZEO_, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFZE_, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{SUBFZEO_, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{NEG_, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{NEGO_, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLW_, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLWO_, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHW_, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHWU_, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVW_, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWO_, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWU_, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWUO_, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWE_, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWEO_, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWEU_, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVWEUO_, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLD_, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLDO_, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHDU_, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHD_, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVD_, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDO_, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDU_, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDUO_, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDE_, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDEO_, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDEU_, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DIVDEUO_, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
+	{CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
+	{CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
+	{ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
+	{TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ANDI_, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+	{ANDIS_, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+	{ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+	{ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+	{XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+	{XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
+	{AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{AND_, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{XOR_, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{NAND_, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{OR_, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{NOR_, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{ANDC_, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{EXTSB_, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{EQV_, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{ORC_, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{EXTSH_, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{EXTSW_, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{CNTLZD_, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+	{RLWINM_, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+	{RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+	{RLWNM_, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+	{RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+	{RLWIMI_, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
+	{RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDICL_, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDICR_, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDIC_, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDCL_, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDCR_, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{RLDIMI_, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
+	{SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SLW_, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRW_, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
+	{SRAWI_, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
+	{SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRAW_, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SLD_, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRD_, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+	{SRADI_, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
+	{SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{SRAD_, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
+		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
+	{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+	{MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
+		[5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
+	{MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT)
+		[5]*argField{ap_Reg_6_10}},
+	{MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801, // Move To Split Little Endian X-form (mtsle L)
+		[5]*argField{ap_ImmUnsigned_10_10}},
+	{MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword XX1-form (mfvsrd RA,XS)
+		[5]*argField{ap_Reg_11_15, ap_VecReg_31_31_6_10}},
+	{MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero XX1-form (mfvsrwz RA,XS)
+		[5]*argField{ap_Reg_11_15, ap_VecReg_31_31_6_10}},
+	{MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword XX1-form (mtvsrd XT,RA)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15}},
+	{MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic XX1-form (mtvsrwa XT,RA)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15}},
+	{MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero XX1-form (mtvsrwz XT,RA)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15}},
+	{MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS)
+		[5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
+	{MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM)
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
+	{MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801, // Move to Condition Register from XER X-form (mcrxr BF)
+		[5]*argField{ap_CondRegField_6_8}},
+	{MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801, // Move To Device Control Register User-mode Indexed X-form (mtdcrux RS,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801, // Move From Device Control Register User-mode Indexed X-form (mfdcrux RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word and Zero Indexed X-form (lfiwzx FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
+	{STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA))
+		[5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
+	{STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FMR_, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FABS_, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FNABS_, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FNEG_, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FCPSGN_, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FADD_, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FADDS_, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FSUB_, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FSUBS_, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+	{FMUL_, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+	{FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+	{FMULS_, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
+	{FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FDIV_, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FDIVS_, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FSQRT_, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FSQRTS_, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRE_, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRES_, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRSQRTE_, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRSQRTES_, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
+	{FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMADD_, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMADDS_, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMSUB_, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FMSUBS_, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMADD_, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMADDS_, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMSUB_, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FNMSUBS_, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRSP_, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTID_, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIDZ_, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIDU_, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIDUZ_, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIW_, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIWZ_, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIWU_, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCTIWUZ_, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFID_, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFIDU_, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFIDS_, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCFIDUS_, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIN_, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIZ_, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIP_, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FRIM_, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{FSEL_, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
+	{MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT)
+		[5]*argField{ap_FPReg_6_10}},
+	{MFFS_, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT)
+		[5]*argField{ap_FPReg_6_10}},
+	{MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
+		[5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
+	{MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
+		[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
+	{MTFSFI_, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
+		[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
+	{MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
+		[5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
+	{MTFSF_, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
+		[5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
+	{MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
+		[5]*argField{ap_CondRegBit_6_10}},
+	{MTFSB0_, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
+		[5]*argField{ap_CondRegBit_6_10}},
+	{MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
+		[5]*argField{ap_CondRegBit_6_10}},
+	{MTFSB1_, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
+		[5]*argField{ap_CondRegBit_6_10}},
+	{LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVX, 0xfc0007fe, 0x7c0000ce, 0x1, // Load Vector Indexed X-form (lvx VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVXL, 0xfc0007fe, 0x7c0002ce, 0x1, // Load Vector Indexed LRU X-form (lvxl VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVEBX, 0xfc0007fe, 0x7c00010e, 0x1, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVEHX, 0xfc0007fe, 0x7c00014e, 0x1, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVEWX, 0xfc0007fe, 0x7c00018e, 0x1, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVX, 0xfc0007fe, 0x7c0001ce, 0x1, // Store Vector Indexed X-form (stvx VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVXL, 0xfc0007fe, 0x7c0003ce, 0x1, // Store Vector Indexed LRU X-form (stvxl VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVSL, 0xfc0007fe, 0x7c00000c, 0x1, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVSR, 0xfc0007fe, 0x7c00004c, 0x1, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{VPKPX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VUPKLSW, 0xfc0007ff, 0x100006ce, 0x1f0000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VMRGHB, 0xfc0007ff, 0x1000000c, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGHH, 0xfc0007ff, 0x1000004c, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGLB, 0xfc0007ff, 0x1000010c, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGLH, 0xfc0007ff, 0x1000014c, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGHW, 0xfc0007ff, 0x1000008c, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGLW, 0xfc0007ff, 0x1000018c, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGEW, 0xfc0007ff, 0x1000078c, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMRGOW, 0xfc0007ff, 0x1000068c, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSPLTB, 0xfc0007ff, 0x1000020c, 0x100000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
+	{VSPLTH, 0xfc0007ff, 0x1000024c, 0x180000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
+	{VSPLTW, 0xfc0007ff, 0x1000028c, 0x1c0000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}},
+	{VSPLTISB, 0xfc0007ff, 0x1000030c, 0xf800, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM)
+		[5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
+	{VSPLTISH, 0xfc0007ff, 0x1000034c, 0xf800, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM)
+		[5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
+	{VSPLTISW, 0xfc0007ff, 0x1000038c, 0xf800, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM)
+		[5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
+	{VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSLDOI, 0xfc00003f, 0x1000002c, 0x400, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}},
+	{VSLO, 0xfc0007ff, 0x1000040c, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSR, 0xfc0007ff, 0x100002c4, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRO, 0xfc0007ff, 0x1000044c, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDCUW, 0xfc0007ff, 0x10000180, 0x0, // Vector Add and Write Carry-Out Unsigned Word VX-form (vaddcuw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDSBS, 0xfc0007ff, 0x10000300, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDSHS, 0xfc0007ff, 0x10000340, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDSWS, 0xfc0007ff, 0x10000380, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUBM, 0xfc0007ff, 0x10000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUDM, 0xfc0007ff, 0x100000c0, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUHM, 0xfc0007ff, 0x10000040, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUWM, 0xfc0007ff, 0x10000080, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUBS, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUHS, 0xfc0007ff, 0x10000240, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUWS, 0xfc0007ff, 0x10000280, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDUQM, 0xfc0007ff, 0x10000100, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDEUQM, 0xfc00003f, 0x1000003c, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VADDCUQ, 0xfc0007ff, 0x10000140, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDECUQ, 0xfc00003f, 0x1000003d, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VSUBCUW, 0xfc0007ff, 0x10000580, 0x0, // Vector Subtract and Write Carry-Out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBSBS, 0xfc0007ff, 0x10000700, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBSHS, 0xfc0007ff, 0x10000740, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBSWS, 0xfc0007ff, 0x10000780, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUBM, 0xfc0007ff, 0x10000400, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUDM, 0xfc0007ff, 0x100004c0, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUHM, 0xfc0007ff, 0x10000440, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUWM, 0xfc0007ff, 0x10000480, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUBS, 0xfc0007ff, 0x10000600, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUHS, 0xfc0007ff, 0x10000640, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUWS, 0xfc0007ff, 0x10000680, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBUQM, 0xfc0007ff, 0x10000500, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBEUQM, 0xfc00003f, 0x1000003e, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VSUBCUQ, 0xfc0007ff, 0x10000540, 0x0, // Vector Subtract & write Carry Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBECUQ, 0xfc00003f, 0x1000003f, 0x0, // Vector Subtract Extended & write Carry Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMULESB, 0xfc0007ff, 0x10000308, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULEUB, 0xfc0007ff, 0x10000208, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULOSB, 0xfc0007ff, 0x10000108, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULOUB, 0xfc0007ff, 0x10000008, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULESH, 0xfc0007ff, 0x10000348, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULEUH, 0xfc0007ff, 0x10000248, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULOSH, 0xfc0007ff, 0x10000148, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULOUH, 0xfc0007ff, 0x10000048, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULESW, 0xfc0007ff, 0x10000388, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULEUW, 0xfc0007ff, 0x10000288, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULOSW, 0xfc0007ff, 0x10000188, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULOUW, 0xfc0007ff, 0x10000088, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMULUWM, 0xfc0007ff, 0x10000089, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMHADDSHS, 0xfc00003f, 0x10000020, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMHRADDSHS, 0xfc00003f, 0x10000021, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMLADDUHM, 0xfc00003f, 0x10000022, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMUBM, 0xfc00003f, 0x10000024, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMMBM, 0xfc00003f, 0x10000025, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMSHM, 0xfc00003f, 0x10000028, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMSHS, 0xfc00003f, 0x10000029, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMUHM, 0xfc00003f, 0x10000026, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUM4SBS, 0xfc0007ff, 0x10000708, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUM4SHS, 0xfc0007ff, 0x10000648, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUM4UBS, 0xfc0007ff, 0x10000608, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAVGSB, 0xfc0007ff, 0x10000502, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAVGSH, 0xfc0007ff, 0x10000542, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAVGSW, 0xfc0007ff, 0x10000582, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAVGUB, 0xfc0007ff, 0x10000402, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAVGUW, 0xfc0007ff, 0x10000482, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAVGUH, 0xfc0007ff, 0x10000442, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXSB, 0xfc0007ff, 0x10000102, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXSD, 0xfc0007ff, 0x100001c2, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXUB, 0xfc0007ff, 0x10000002, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXUD, 0xfc0007ff, 0x100000c2, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXSH, 0xfc0007ff, 0x10000142, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXSW, 0xfc0007ff, 0x10000182, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXUH, 0xfc0007ff, 0x10000042, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMAXUW, 0xfc0007ff, 0x10000082, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINSB, 0xfc0007ff, 0x10000302, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINSD, 0xfc0007ff, 0x100003c2, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINUB, 0xfc0007ff, 0x10000202, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINUD, 0xfc0007ff, 0x100002c2, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINSH, 0xfc0007ff, 0x10000342, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINSW, 0xfc0007ff, 0x10000382, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINUH, 0xfc0007ff, 0x10000242, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINUW, 0xfc0007ff, 0x10000282, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUB_, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUH_, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUW_, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQUD_, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSB_, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSD_, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSH_, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTSW_, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUB_, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUD_, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUH_, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTUW_, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VAND, 0xfc0007ff, 0x10000404, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VANDC, 0xfc0007ff, 0x10000444, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VEQV, 0xfc0007ff, 0x10000684, 0x0, // Vector Logical Equivalent VX-form (veqv VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VNAND, 0xfc0007ff, 0x10000584, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VORC, 0xfc0007ff, 0x10000544, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VNOR, 0xfc0007ff, 0x10000504, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VOR, 0xfc0007ff, 0x10000484, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VXOR, 0xfc0007ff, 0x100004c4, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VRLB, 0xfc0007ff, 0x10000004, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VRLH, 0xfc0007ff, 0x10000044, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VRLW, 0xfc0007ff, 0x10000084, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VRLD, 0xfc0007ff, 0x100000c4, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSLB, 0xfc0007ff, 0x10000104, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSLH, 0xfc0007ff, 0x10000144, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSLW, 0xfc0007ff, 0x10000184, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSLD, 0xfc0007ff, 0x100005c4, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRB, 0xfc0007ff, 0x10000204, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRH, 0xfc0007ff, 0x10000244, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRW, 0xfc0007ff, 0x10000284, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRD, 0xfc0007ff, 0x100006c4, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRAB, 0xfc0007ff, 0x10000304, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRAH, 0xfc0007ff, 0x10000344, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRAW, 0xfc0007ff, 0x10000384, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSRAD, 0xfc0007ff, 0x100003c4, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VADDFP, 0xfc0007ff, 0x1000000a, 0x0, // Vector Add Single-Precision VX-form (vaddfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSUBFP, 0xfc0007ff, 0x1000004a, 0x0, // Vector Subtract Single-Precision VX-form (vsubfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMADDFP, 0xfc00003f, 0x1000002e, 0x0, // Vector Multiply-Add Single-Precision VA-form (vmaddfp VRT,VRA,VRC,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
+	{VNMSUBFP, 0xfc00003f, 0x1000002f, 0x0, // Vector Negative Multiply-Subtract Single-Precision VA-form (vnmsubfp VRT,VRA,VRC,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
+	{VMAXFP, 0xfc0007ff, 0x1000040a, 0x0, // Vector Maximum Single-Precision VX-form (vmaxfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VMINFP, 0xfc0007ff, 0x1000044a, 0x0, // Vector Minimum Single-Precision VX-form (vminfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCTSXS, 0xfc0007ff, 0x100003ca, 0x0, // Vector Convert To Signed Fixed-Point Word Saturate VX-form (vctsxs VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+	{VCTUXS, 0xfc0007ff, 0x1000038a, 0x0, // Vector Convert To Unsigned Fixed-Point Word Saturate VX-form (vctuxs VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+	{VCFSX, 0xfc0007ff, 0x1000034a, 0x0, // Vector Convert From Signed Fixed-Point Word VX-form (vcfsx VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+	{VCFUX, 0xfc0007ff, 0x1000030a, 0x0, // Vector Convert From Unsigned Fixed-Point Word VX-form (vcfux VRT,VRB,UIM)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
+	{VRFIM, 0xfc0007ff, 0x100002ca, 0x1f0000, // Vector Round to Single-Precision Integer toward -Infinity VX-form (vrfim VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VRFIN, 0xfc0007ff, 0x1000020a, 0x1f0000, // Vector Round to Single-Precision Integer Nearest VX-form (vrfin VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VRFIP, 0xfc0007ff, 0x1000028a, 0x1f0000, // Vector Round to Single-Precision Integer toward +Infinity VX-form (vrfip VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VRFIZ, 0xfc0007ff, 0x1000024a, 0x1f0000, // Vector Round to Single-Precision Integer toward Zero VX-form (vrfiz VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPBFP_, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPEQFP_, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGEFP_, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPGTFP_, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VLOGEFP, 0xfc0007ff, 0x100001ca, 0x1f0000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VREFP, 0xfc0007ff, 0x1000010a, 0x1f0000, // Vector Reciprocal Estimate Single-Precision VX-form (vrefp VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VRSQRTEFP, 0xfc0007ff, 0x1000014a, 0x1f0000, // Vector Reciprocal Square Root Estimate Single-Precision VX-form (vrsqrtefp VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VCIPHER, 0xfc0007ff, 0x10000508, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCIPHERLAST, 0xfc0007ff, 0x10000509, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VNCIPHER, 0xfc0007ff, 0x10000548, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VNCIPHERLAST, 0xfc0007ff, 0x10000549, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VSBOX, 0xfc0007ff, 0x100005c8, 0xf800, // Vector AES SubBytes VX-form (vsbox VRT,VRA)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
+	{VSHASIGMAD, 0xfc0007ff, 0x100006c2, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
+	{VSHASIGMAW, 0xfc0007ff, 0x10000682, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
+	{VPMSUMB, 0xfc0007ff, 0x10000408, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPMSUMD, 0xfc0007ff, 0x100004c8, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPMSUMH, 0xfc0007ff, 0x10000448, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPMSUMW, 0xfc0007ff, 0x10000488, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VPERMXOR, 0xfc00003f, 0x1000002d, 0x0, // Vector Permute and Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VGBBD, 0xfc0007ff, 0x1000050c, 0x1f0000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VCLZB, 0xfc0007ff, 0x10000702, 0x1f0000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VCLZH, 0xfc0007ff, 0x10000742, 0x1f0000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VCLZW, 0xfc0007ff, 0x10000782, 0x1f0000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VCLZD, 0xfc0007ff, 0x100007c2, 0x1f0000, // Vector Count Leading Zeros Doubleword (vclzd VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VPOPCNTB, 0xfc0007ff, 0x10000703, 0x1f0000, // Vector Population Count Byte (vpopcntb VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VPOPCNTD, 0xfc0007ff, 0x100007c3, 0x1f0000, // Vector Population Count Doubleword (vpopcntd VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VPOPCNTH, 0xfc0007ff, 0x10000743, 0x1f0000, // Vector Population Count Halfword (vpopcnth VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VPOPCNTW, 0xfc0007ff, 0x10000783, 0x1f0000, // Vector Population Count Word (vpopcntw VRT,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
+	{VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{BCDADD_, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+	{BCDSUB_, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
+	{MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000, // Move To Vector Status and Control Register VX-form (mtvscr VRB)
+		[5]*argField{ap_VecReg_16_20}},
+	{MFVSCR, 0xfc0007ff, 0x10000604, 0x1ff800, // Move From Vector Status and Control Register VX-form (mfvscr VRT)
+		[5]*argField{ap_VecReg_6_10}},
+	{DADD, 0xfc0007ff, 0xec000004, 0x0, // DFP Add [Quad] X-form (dadd FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DADD_, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DSUB, 0xfc0007ff, 0xec000404, 0x0, // DFP Subtract [Quad] X-form (dsub FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DSUB_, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DMUL, 0xfc0007ff, 0xec000044, 0x0, // DFP Multiply [Quad] X-form (dmul FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DMUL_, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DDIV, 0xfc0007ff, 0xec000444, 0x0, // DFP Divide [Quad] X-form (ddiv FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DDIV_, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DCMPU, 0xfc0007fe, 0xec000504, 0x600001, // DFP Compare Unordered [Quad] X-form (dcmpu BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DCMPO, 0xfc0007fe, 0xec000104, 0x600001, // DFP Compare Ordered [Quad] X-form (dcmpo BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DTSTDC, 0xfc0003fe, 0xec000184, 0x600001, // DFP Test Data Class [Quad] Z22-form (dtstdc BF,FRA,DCM)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+	{DTSTDG, 0xfc0003fe, 0xec0001c4, 0x600001, // DFP Test Data Group [Quad] Z22-form (dtstdg BF,FRA,DGM)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+	{DTSTEX, 0xfc0007fe, 0xec000144, 0x600001, // DFP Test Exponent [Quad] X-form (dtstex BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DTSTSF, 0xfc0007fe, 0xec000544, 0x600001, // DFP Test Significance [Quad] X-form (dtstsf BF,FRA,FRB)
+		[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DQUAI, 0xfc0001ff, 0xec000086, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai TE,FRT,FRB,RMC)
+		[5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DQUAI_, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC)
+		[5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DQUA, 0xfc0001ff, 0xec000006, 0x0, // DFP Quantize [Quad] Z23-form (dqua FRT,FRA,FRB,RMC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DQUA_, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DRRND, 0xfc0001ff, 0xec000046, 0x0, // DFP Reround [Quad] Z23-form (drrnd FRT,FRA,FRB,RMC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DRRND_, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx R,FRT,FRB,RMC)
+		[5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DRINTX_, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC)
+		[5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn R,FRT,FRB,RMC)
+		[5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DRINTN_, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC)
+		[5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
+	{DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCTDP_, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCTQPQ_, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DRSP, 0xfc0007ff, 0xec000604, 0x1f0000, // DFP Round To DFP Short X-form (drsp FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DRSP_, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DRDPQ_, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000, // DFP Convert From Fixed X-form (dcffix FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCFFIX_, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCFFIXQ_, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DCTFIX_, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DDEDPD, 0xfc0007ff, 0xec000284, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd SP,FRT,FRB)
+		[5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DDEDPD_, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB)
+		[5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DENBCD, 0xfc0007ff, 0xec000684, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd S,FRT,FRB)
+		[5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DENBCD_, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB)
+		[5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DXEX_, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
+	{DIEX, 0xfc0007ff, 0xec0006c4, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DIEX_, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
+	{DSCLI, 0xfc0003ff, 0xec000084, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli FRT,FRA,SH)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+	{DSCLI_, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+	{DSCRI, 0xfc0003ff, 0xec0000c4, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri FRT,FRA,SH)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+	{DSCRI_, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH)
+		[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
+	{LXSDX, 0xfc0007fe, 0x7c000498, 0x0, // Load VSX Scalar Doubleword Indexed XX1-form (lxsdx XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXSIWAX, 0xfc0007fe, 0x7c000098, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed XX1-form (lxsiwax XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXSIWZX, 0xfc0007fe, 0x7c000018, 0x0, // Load VSX Scalar as Integer Word and Zero Indexed XX1-form (lxsiwzx XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXSSPX, 0xfc0007fe, 0x7c000418, 0x0, // Load VSX Scalar Single-Precision Indexed XX1-form (lxsspx XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVD2X, 0xfc0007fe, 0x7c000698, 0x0, // Load VSX Vector Doubleword*2 Indexed XX1-form (lxvd2x XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVDSX, 0xfc0007fe, 0x7c000298, 0x0, // Load VSX Vector Doubleword & Splat Indexed XX1-form (lxvdsx XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXSSPX, 0xfc0007fe, 0x7c000518, 0x0, // Store VSX Scalar Single-Precision Indexed XX1-form (stxsspx XS,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXVD2X, 0xfc0007fe, 0x7c000798, 0x0, // Store VSX Vector Doubleword*2 Indexed XX1-form (stxvd2x XS,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSADDSP, 0xfc0007f8, 0xf0000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSCMPODP, 0xfc0007f8, 0xf0000158, 0x600001, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSCMPUDP, 0xfc0007f8, 0xf0000118, 0x600001, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSCPSGNDP, 0xfc0007f8, 0xf0000580, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSCVDPSP, 0xfc0007fc, 0xf0000424, 0x1f0000, // VSX Scalar round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xscvdpsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVDPSPN, 0xfc0007fc, 0xf000042c, 0x1f0000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVDPSXDS, 0xfc0007fc, 0xf0000560, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xscvdpsxds XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVDPSXWS, 0xfc0007fc, 0xf0000160, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xscvdpsxws XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVDPUXDS, 0xfc0007fc, 0xf0000520, 0x1f0000, // VSX Scalar truncate Double-Precision integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xscvdpuxds XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVDPUXWS, 0xfc0007fc, 0xf0000120, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xscvdpuxws XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVSPDP, 0xfc0007fc, 0xf0000524, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVSPDPN, 0xfc0007fc, 0xf000052c, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVSXDDP, 0xfc0007fc, 0xf00005e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvsxddp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVSXDSP, 0xfc0007fc, 0xf00004e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvsxdsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVUXDDP, 0xfc0007fc, 0xf00005a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvuxddp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSCVUXDSP, 0xfc0007fc, 0xf00004a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvuxdsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSDIVDP, 0xfc0007f8, 0xf00001c0, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSDIVSP, 0xfc0007f8, 0xf00000c0, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMADDADP, 0xfc0007f8, 0xf0000108, 0x0, // VSX Scalar Multiply-Add Double-Precision XX3-form (xsmaddadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMADDASP, 0xfc0007f8, 0xf0000008, 0x0, // VSX Scalar Multiply-Add Single-Precision XX3-form (xsmaddasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMAXDP, 0xfc0007f8, 0xf0000500, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMINDP, 0xfc0007f8, 0xf0000540, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMSUBADP, 0xfc0007f8, 0xf0000188, 0x0, // VSX Scalar Multiply-Subtract Double-Precision XX3-form (xsmsubadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMSUBASP, 0xfc0007f8, 0xf0000088, 0x0, // VSX Scalar Multiply-Subtract Single-Precision XX3-form (xsmsubasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMULDP, 0xfc0007f8, 0xf0000180, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSMULSP, 0xfc0007f8, 0xf0000080, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSNABSDP, 0xfc0007fc, 0xf00005a4, 0x1f0000, // VSX Scalar Negative Absolute Value Double-Precision XX2-form (xsnabsdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSNEGDP, 0xfc0007fc, 0xf00005e4, 0x1f0000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSNMADDADP, 0xfc0007f8, 0xf0000508, 0x0, // VSX Scalar Negative Multiply-Add Double-Precision XX3-form (xsnmaddadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSNMADDASP, 0xfc0007f8, 0xf0000408, 0x0, // VSX Scalar Negative Multiply-Add Single-Precision XX3-form (xsnmaddasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSNMSUBADP, 0xfc0007f8, 0xf0000588, 0x0, // VSX Scalar Negative Multiply-Subtract Double-Precision XX3-form (xsnmsubadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSNMSUBASP, 0xfc0007f8, 0xf0000488, 0x0, // VSX Scalar Negative Multiply-Subtract Single-Precision XX3-form (xsnmsubasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSRDPI, 0xfc0007fc, 0xf0000124, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRDPIC, 0xfc0007fc, 0xf00001ac, 0x1f0000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRDPIM, 0xfc0007fc, 0xf00001e4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRDPIP, 0xfc0007fc, 0xf00001a4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRDPIZ, 0xfc0007fc, 0xf0000164, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSREDP, 0xfc0007fc, 0xf0000168, 0x1f0000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRESP, 0xfc0007fc, 0xf0000068, 0x1f0000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRSP, 0xfc0007fc, 0xf0000464, 0x1f0000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRSQRTEDP, 0xfc0007fc, 0xf0000128, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSRSQRTESP, 0xfc0007fc, 0xf0000028, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSSQRTDP, 0xfc0007fc, 0xf000012c, 0x1f0000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSSQRTSP, 0xfc0007fc, 0xf000002c, 0x1f0000, // VSX Scalar Square Root Single-Precision XX-form (xssqrtsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XSSUBDP, 0xfc0007f8, 0xf0000140, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSSUBSP, 0xfc0007f8, 0xf0000040, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSTDIVDP, 0xfc0007f8, 0xf00001e8, 0x600001, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XSTSQRTDP, 0xfc0007fc, 0xf00001a8, 0x7f0001, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_30_30_16_20}},
+	{XVABSDP, 0xfc0007fc, 0xf0000764, 0x1f0000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVABSSP, 0xfc0007fc, 0xf0000664, 0x1f0000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVADDDP, 0xfc0007f8, 0xf0000300, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVADDSP, 0xfc0007f8, 0xf0000200, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPEQDP_, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPEQSP_, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGEDP_, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGESP_, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGTDP_, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCMPGTSP_, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCPSGNSP, 0xfc0007f8, 0xf0000680, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVCVDPSP, 0xfc0007fc, 0xf0000624, 0x1f0000, // VSX Vector round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xvcvdpsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVDPSXDS, 0xfc0007fc, 0xf0000760, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvdpsxds XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVDPSXWS, 0xfc0007fc, 0xf0000360, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvdpsxws XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVDPUXDS, 0xfc0007fc, 0xf0000720, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvdpuxds XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVDPUXWS, 0xfc0007fc, 0xf0000320, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvdpuxws XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSPDP, 0xfc0007fc, 0xf0000724, 0x1f0000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSPSXDS, 0xfc0007fc, 0xf0000660, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvspsxds XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSPSXWS, 0xfc0007fc, 0xf0000260, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvspsxws XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSPUXDS, 0xfc0007fc, 0xf0000620, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvspuxds XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSPUXWS, 0xfc0007fc, 0xf0000220, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvspuxws XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSXDDP, 0xfc0007fc, 0xf00007e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSXDSP, 0xfc0007fc, 0xf00006e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSXWDP, 0xfc0007fc, 0xf00003e0, 0x1f0000, // VSX Vector Convert Signed Integer Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVSXWSP, 0xfc0007fc, 0xf00002e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVUXDDP, 0xfc0007fc, 0xf00007a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVUXDSP, 0xfc0007fc, 0xf00006a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVUXWDP, 0xfc0007fc, 0xf00003a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVCVUXWSP, 0xfc0007fc, 0xf00002a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVDIVDP, 0xfc0007f8, 0xf00003c0, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVDIVSP, 0xfc0007f8, 0xf00002c0, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMADDADP, 0xfc0007f8, 0xf0000308, 0x0, // VSX Vector Multiply-Add Double-Precision XX3-form (xvmaddadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMADDASP, 0xfc0007f8, 0xf0000208, 0x0, // VSX Vector Multiply-Add Single-Precision XX3-form (xvmaddasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMAXDP, 0xfc0007f8, 0xf0000700, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMAXSP, 0xfc0007f8, 0xf0000600, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMINDP, 0xfc0007f8, 0xf0000740, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMINSP, 0xfc0007f8, 0xf0000640, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMSUBADP, 0xfc0007f8, 0xf0000388, 0x0, // VSX Vector Multiply-Subtract Double-Precision XX3-form (xvmsubadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMSUBASP, 0xfc0007f8, 0xf0000288, 0x0, // VSX Vector Multiply-Subtract Single-Precision XX3-form (xvmsubasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMULDP, 0xfc0007f8, 0xf0000380, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVMULSP, 0xfc0007f8, 0xf0000280, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVNABSDP, 0xfc0007fc, 0xf00007a4, 0x1f0000, // VSX Vector Negative Absolute Value Double-Precision XX2-form (xvnabsdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVNABSSP, 0xfc0007fc, 0xf00006a4, 0x1f0000, // VSX Vector Negative Absolute Value Single-Precision XX2-form (xvnabssp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVNEGDP, 0xfc0007fc, 0xf00007e4, 0x1f0000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVNEGSP, 0xfc0007fc, 0xf00006e4, 0x1f0000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVNMADDADP, 0xfc0007f8, 0xf0000708, 0x0, // VSX Vector Negative Multiply-Add Double-Precision XX3-form (xvnmaddadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVNMADDASP, 0xfc0007f8, 0xf0000608, 0x0, // VSX Vector Negative Multiply-Add Single-Precision XX3-form (xvnmaddasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVNMSUBADP, 0xfc0007f8, 0xf0000788, 0x0, // VSX Vector Negative Multiply-Subtract Double-Precision XX3-form (xvnmsubadp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVNMSUBASP, 0xfc0007f8, 0xf0000688, 0x0, // VSX Vector Negative Multiply-Subtract Single-Precision XX3-form (xvnmsubasp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVRDPI, 0xfc0007fc, 0xf0000324, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRDPIC, 0xfc0007fc, 0xf00003ac, 0x1f0000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRDPIM, 0xfc0007fc, 0xf00003e4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRDPIP, 0xfc0007fc, 0xf00003a4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRDPIZ, 0xfc0007fc, 0xf0000364, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVREDP, 0xfc0007fc, 0xf0000368, 0x1f0000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRESP, 0xfc0007fc, 0xf0000268, 0x1f0000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSPI, 0xfc0007fc, 0xf0000224, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSPIC, 0xfc0007fc, 0xf00002ac, 0x1f0000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSPIM, 0xfc0007fc, 0xf00002e4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSPIP, 0xfc0007fc, 0xf00002a4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSPIZ, 0xfc0007fc, 0xf0000264, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSQRTEDP, 0xfc0007fc, 0xf0000328, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVRSQRTESP, 0xfc0007fc, 0xf0000228, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVSQRTDP, 0xfc0007fc, 0xf000032c, 0x1f0000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVSQRTSP, 0xfc0007fc, 0xf000022c, 0x1f0000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20}},
+	{XVSUBDP, 0xfc0007f8, 0xf0000340, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVSUBSP, 0xfc0007f8, 0xf0000240, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVTDIVDP, 0xfc0007f8, 0xf00003e8, 0x600001, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVTDIVSP, 0xfc0007f8, 0xf00002e8, 0x600001, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XVTSQRTDP, 0xfc0007fc, 0xf00003a8, 0x7f0001, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_30_30_16_20}},
+	{XVTSQRTSP, 0xfc0007fc, 0xf00002a8, 0x7f0001, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB)
+		[5]*argField{ap_CondRegField_6_8, ap_VecReg_30_30_16_20}},
+	{XXLAND, 0xfc0007f8, 0xf0000410, 0x0, // VSX Logical AND XX3-form (xxland XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLANDC, 0xfc0007f8, 0xf0000450, 0x0, // VSX Logical AND with Complement XX3-form (xxlandc XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLEQV, 0xfc0007f8, 0xf00005d0, 0x0, // VSX Logical Equivalence XX3-form (xxleqv XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLNAND, 0xfc0007f8, 0xf0000590, 0x0, // VSX Logical NAND XX3-form (xxlnand XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLORC, 0xfc0007f8, 0xf0000550, 0x0, // VSX Logical OR with Complement XX3-form (xxlorc XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLNOR, 0xfc0007f8, 0xf0000510, 0x0, // VSX Logical NOR XX3-form (xxlnor XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLOR, 0xfc0007f8, 0xf0000490, 0x0, // VSX Logical OR XX3-form (xxlor XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXLXOR, 0xfc0007f8, 0xf00004d0, 0x0, // VSX Logical XOR XX3-form (xxlxor XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXMRGHW, 0xfc0007f8, 0xf0000090, 0x0, // VSX Merge High Word XX3-form (xxmrghw XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXMRGLW, 0xfc0007f8, 0xf0000190, 0x0, // VSX Merge Low Word XX3-form (xxmrglw XT,XA,XB)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20}},
+	{XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20, ap_ImmUnsigned_22_23}},
+	{XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20, ap_VecReg_28_28_21_25}},
+	{XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_29_29_11_15, ap_VecReg_30_30_16_20, ap_ImmUnsigned_22_23}},
+	{XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM)
+		[5]*argField{ap_VecReg_31_31_6_10, ap_VecReg_30_30_16_20, ap_ImmUnsigned_14_15}},
+	{BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVADDIW, 0xfc0007ff, 0x10000202, 0x0, // Vector Add Immediate Word EVX-form (evaddiw RT,RB,UI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_11_15}},
+	{EVADDSMIAAW, 0xfc0007ff, 0x100004c9, 0xf800, // Vector Add Signed, Modulo, Integer to Accumulator Word EVX-form (evaddsmiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVADDSSIAAW, 0xfc0007ff, 0x100004c1, 0xf800, // Vector Add Signed, Saturate, Integer to Accumulator Word EVX-form (evaddssiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVADDUMIAAW, 0xfc0007ff, 0x100004c8, 0xf800, // Vector Add Unsigned, Modulo, Integer to Accumulator Word EVX-form (evaddumiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVADDUSIAAW, 0xfc0007ff, 0x100004c0, 0xf800, // Vector Add Unsigned, Saturate, Integer to Accumulator Word EVX-form (evaddusiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVADDW, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Word EVX-form (evaddw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVAND, 0xfc0007ff, 0x10000211, 0x0, // Vector AND EVX-form (evand RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVCMPEQ, 0xfc0007ff, 0x10000234, 0x600000, // Vector Compare Equal EVX-form (evcmpeq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVANDC, 0xfc0007ff, 0x10000212, 0x0, // Vector AND with Complement EVX-form (evandc RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVCMPGTS, 0xfc0007ff, 0x10000231, 0x600000, // Vector Compare Greater Than Signed EVX-form (evcmpgts BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVCMPGTU, 0xfc0007ff, 0x10000230, 0x600000, // Vector Compare Greater Than Unsigned EVX-form (evcmpgtu BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVCMPLTU, 0xfc0007ff, 0x10000232, 0x600000, // Vector Compare Less Than Unsigned EVX-form (evcmpltu BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVCMPLTS, 0xfc0007ff, 0x10000233, 0x600000, // Vector Compare Less Than Signed EVX-form (evcmplts BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVCNTLSW, 0xfc0007ff, 0x1000020e, 0xf800, // Vector Count Leading Signed Bits Word EVX-form (evcntlsw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVCNTLZW, 0xfc0007ff, 0x1000020d, 0xf800, // Vector Count Leading Zeros Word EVX-form (evcntlzw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVDIVWS, 0xfc0007ff, 0x100004c6, 0x0, // Vector Divide Word Signed EVX-form (evdivws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVDIVWU, 0xfc0007ff, 0x100004c7, 0x0, // Vector Divide Word Unsigned EVX-form (evdivwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVEQV, 0xfc0007ff, 0x10000219, 0x0, // Vector Equivalent EVX-form (eveqv RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVEXTSB, 0xfc0007ff, 0x1000020a, 0xf800, // Vector Extend Sign Byte EVX-form (evextsb RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVEXTSH, 0xfc0007ff, 0x1000020b, 0xf800, // Vector Extend Sign Halfword EVX-form (evextsh RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVLDD, 0xfc0007ff, 0x10000301, 0x0, // Vector Load Double Word into Double Word EVX-form (evldd RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLDH, 0xfc0007ff, 0x10000305, 0x0, // Vector Load Double into Four Halfwords EVX-form (evldh RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLDDX, 0xfc0007ff, 0x10000300, 0x0, // Vector Load Double Word into Double Word Indexed EVX-form (evlddx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLDHX, 0xfc0007ff, 0x10000304, 0x0, // Vector Load Double into Four Halfwords Indexed EVX-form (evldhx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLDW, 0xfc0007ff, 0x10000303, 0x0, // Vector Load Double into Two Words EVX-form (evldw RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLHHESPLAT, 0xfc0007ff, 0x10000309, 0x0, // Vector Load Halfword into Halfwords Even and Splat EVX-form (evlhhesplat RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLDWX, 0xfc0007ff, 0x10000302, 0x0, // Vector Load Double into Two Words Indexed EVX-form (evldwx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLHHESPLATX, 0xfc0007ff, 0x10000308, 0x0, // Vector Load Halfword into Halfwords Even and Splat Indexed EVX-form (evlhhesplatx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLHHOSSPLAT, 0xfc0007ff, 0x1000030f, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat EVX-form (evlhhossplat RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLHHOUSPLAT, 0xfc0007ff, 0x1000030d, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat EVX-form (evlhhousplat RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLHHOSSPLATX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat Indexed EVX-form (evlhhossplatx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLHHOUSPLATX, 0xfc0007ff, 0x1000030c, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed EVX-form (evlhhousplatx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLWHE, 0xfc0007ff, 0x10000311, 0x0, // Vector Load Word into Two Halfwords Even EVX-form (evlwhe RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLWHOS, 0xfc0007ff, 0x10000317, 0x0, // Vector Load Word into Two Halfwords Odd Signed (with sign extension) EVX-form (evlwhos RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLWHEX, 0xfc0007ff, 0x10000310, 0x0, // Vector Load Word into Two Halfwords Even Indexed EVX-form (evlwhex RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLWHOSX, 0xfc0007ff, 0x10000316, 0x0, // Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) EVX-form (evlwhosx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLWHOU, 0xfc0007ff, 0x10000315, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) EVX-form (evlwhou RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLWHSPLAT, 0xfc0007ff, 0x1000031d, 0x0, // Vector Load Word into Two Halfwords and Splat EVX-form (evlwhsplat RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVLWHOUX, 0xfc0007ff, 0x10000314, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) EVX-form (evlwhoux RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLWHSPLATX, 0xfc0007ff, 0x1000031c, 0x0, // Vector Load Word into Two Halfwords and Splat Indexed EVX-form (evlwhsplatx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLWWSPLAT, 0xfc0007ff, 0x10000319, 0x0, // Vector Load Word into Word and Splat EVX-form (evlwwsplat RT,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVMERGEHI, 0xfc0007ff, 0x1000022c, 0x0, // Vector Merge High EVX-form (evmergehi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLWWSPLATX, 0xfc0007ff, 0x10000318, 0x0, // Vector Load Word into Word and Splat Indexed EVX-form (evlwwsplatx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMERGELO, 0xfc0007ff, 0x1000022d, 0x0, // Vector Merge Low EVX-form (evmergelo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMERGEHILO, 0xfc0007ff, 0x1000022e, 0x0, // Vector Merge High/Low EVX-form (evmergehilo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEGSMFAA, 0xfc0007ff, 0x1000052b, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhegsmfaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMERGELOHI, 0xfc0007ff, 0x1000022f, 0x0, // Vector Merge Low/High EVX-form (evmergelohi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEGSMFAN, 0xfc0007ff, 0x100005ab, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhegsmfan RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEGSMIAA, 0xfc0007ff, 0x10000529, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhegsmiaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEGUMIAA, 0xfc0007ff, 0x10000528, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhegumiaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEGSMIAN, 0xfc0007ff, 0x100005a9, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhegsmian RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEGUMIAN, 0xfc0007ff, 0x100005a8, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhegumian RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMF, 0xfc0007ff, 0x1000040b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional EVX-form (evmhesmf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMFAAW, 0xfc0007ff, 0x1000050b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhesmfaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMFA, 0xfc0007ff, 0x1000042b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator EVX-form (evmhesmfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMFANW, 0xfc0007ff, 0x1000058b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhesmfanw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMI, 0xfc0007ff, 0x10000409, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer EVX-form (evmhesmi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMIAAW, 0xfc0007ff, 0x10000509, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhesmiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMIA, 0xfc0007ff, 0x10000429, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator EVX-form (evmhesmia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESMIANW, 0xfc0007ff, 0x10000589, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhesmianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESSF, 0xfc0007ff, 0x10000403, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional EVX-form (evmhessf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESSFA, 0xfc0007ff, 0x10000423, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator EVX-form (evmhessfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESSFAAW, 0xfc0007ff, 0x10000503, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhessfaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESSFANW, 0xfc0007ff, 0x10000583, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhessfanw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESSIAAW, 0xfc0007ff, 0x10000501, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhessiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHESSIANW, 0xfc0007ff, 0x10000581, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhessianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEUMI, 0xfc0007ff, 0x10000408, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer EVX-form (evmheumi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEUMIAAW, 0xfc0007ff, 0x10000508, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmheumiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEUMIA, 0xfc0007ff, 0x10000428, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator EVX-form (evmheumia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEUMIANW, 0xfc0007ff, 0x10000588, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmheumianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEUSIAAW, 0xfc0007ff, 0x10000500, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmheusiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHEUSIANW, 0xfc0007ff, 0x10000580, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmheusianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOGSMFAA, 0xfc0007ff, 0x1000052f, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhogsmfaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOGSMIAA, 0xfc0007ff, 0x1000052d, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhogsmiaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOGSMFAN, 0xfc0007ff, 0x100005af, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhogsmfan RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOGSMIAN, 0xfc0007ff, 0x100005ad, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhogsmian RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOGUMIAA, 0xfc0007ff, 0x1000052c, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhogumiaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMF, 0xfc0007ff, 0x1000040f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional EVX-form (evmhosmf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOGUMIAN, 0xfc0007ff, 0x100005ac, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhogumian RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMFA, 0xfc0007ff, 0x1000042f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator EVX-form (evmhosmfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMFAAW, 0xfc0007ff, 0x1000050f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhosmfaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMI, 0xfc0007ff, 0x1000040d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer EVX-form (evmhosmi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMFANW, 0xfc0007ff, 0x1000058f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhosmfanw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMIA, 0xfc0007ff, 0x1000042d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator EVX-form (evmhosmia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMIAAW, 0xfc0007ff, 0x1000050d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhosmiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSMIANW, 0xfc0007ff, 0x1000058d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhosmianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSSF, 0xfc0007ff, 0x10000407, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional EVX-form (evmhossf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSSFA, 0xfc0007ff, 0x10000427, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator EVX-form (evmhossfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSSFAAW, 0xfc0007ff, 0x10000507, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhossfaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSSFANW, 0xfc0007ff, 0x10000587, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhossfanw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSSIAAW, 0xfc0007ff, 0x10000505, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhossiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOUMI, 0xfc0007ff, 0x1000040c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer EVX-form (evmhoumi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOSSIANW, 0xfc0007ff, 0x10000585, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhossianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOUMIA, 0xfc0007ff, 0x1000042c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator EVX-form (evmhoumia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOUMIAAW, 0xfc0007ff, 0x1000050c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmhoumiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOUSIAAW, 0xfc0007ff, 0x10000504, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmhousiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOUMIANW, 0xfc0007ff, 0x1000058c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhoumianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMHOUSIANW, 0xfc0007ff, 0x10000584, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhousianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMRA, 0xfc0007ff, 0x100004c4, 0xf800, // Initialize Accumulator EVX-form (evmra RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVMWHSMF, 0xfc0007ff, 0x1000044f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional EVX-form (evmwhsmf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHSMI, 0xfc0007ff, 0x1000044d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer EVX-form (evmwhsmi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHSMFA, 0xfc0007ff, 0x1000046f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional to Accumulator EVX-form (evmwhsmfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHSMIA, 0xfc0007ff, 0x1000046d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer to Accumulator EVX-form (evmwhsmia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHSSF, 0xfc0007ff, 0x10000447, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional EVX-form (evmwhssf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHUMI, 0xfc0007ff, 0x1000044c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer EVX-form (evmwhumi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHSSFA, 0xfc0007ff, 0x10000467, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional to Accumulator EVX-form (evmwhssfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWHUMIA, 0xfc0007ff, 0x1000046c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator EVX-form (evmwhumia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLSMIAAW, 0xfc0007ff, 0x10000549, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words EVX-form (evmwlsmiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLSSIAAW, 0xfc0007ff, 0x10000541, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate into Words EVX-form (evmwlssiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLSMIANW, 0xfc0007ff, 0x100005c9, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlsmianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLSSIANW, 0xfc0007ff, 0x100005c1, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlssianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLUMI, 0xfc0007ff, 0x10000448, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer EVX-form (evmwlumi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLUMIAAW, 0xfc0007ff, 0x10000548, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmwlumiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLUMIA, 0xfc0007ff, 0x10000468, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator EVX-form (evmwlumia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLUMIANW, 0xfc0007ff, 0x100005c8, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlumianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLUSIAAW, 0xfc0007ff, 0x10000540, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmwlusiaaw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMF, 0xfc0007ff, 0x1000045b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional EVX-form (evmwsmf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWLUSIANW, 0xfc0007ff, 0x100005c0, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlusianw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMFA, 0xfc0007ff, 0x1000047b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional to Accumulator EVX-form (evmwsmfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMFAA, 0xfc0007ff, 0x1000055b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate EVX-form (evmwsmfaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMI, 0xfc0007ff, 0x10000459, 0x0, // Vector Multiply Word Signed, Modulo, Integer EVX-form (evmwsmi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMIAA, 0xfc0007ff, 0x10000559, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate EVX-form (evmwsmiaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMFAN, 0xfc0007ff, 0x100005db, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmwsmfan RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMIA, 0xfc0007ff, 0x10000479, 0x0, // Vector Multiply Word Signed, Modulo, Integer to Accumulator EVX-form (evmwsmia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSMIAN, 0xfc0007ff, 0x100005d9, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative EVX-form (evmwsmian RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSSF, 0xfc0007ff, 0x10000453, 0x0, // Vector Multiply Word Signed, Saturate, Fractional EVX-form (evmwssf RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSSFA, 0xfc0007ff, 0x10000473, 0x0, // Vector Multiply Word Signed, Saturate, Fractional to Accumulator EVX-form (evmwssfa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSSFAA, 0xfc0007ff, 0x10000553, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate EVX-form (evmwssfaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWUMI, 0xfc0007ff, 0x10000458, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer EVX-form (evmwumi RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWSSFAN, 0xfc0007ff, 0x100005d3, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative EVX-form (evmwssfan RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWUMIA, 0xfc0007ff, 0x10000478, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer to Accumulator EVX-form (evmwumia RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWUMIAA, 0xfc0007ff, 0x10000558, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate EVX-form (evmwumiaa RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVNAND, 0xfc0007ff, 0x1000021e, 0x0, // Vector NAND EVX-form (evnand RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVMWUMIAN, 0xfc0007ff, 0x100005d8, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmwumian RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVNEG, 0xfc0007ff, 0x10000209, 0xf800, // Vector Negate EVX-form (evneg RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVNOR, 0xfc0007ff, 0x10000218, 0x0, // Vector NOR EVX-form (evnor RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVORC, 0xfc0007ff, 0x1000021b, 0x0, // Vector OR with Complement EVX-form (evorc RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVOR, 0xfc0007ff, 0x10000217, 0x0, // Vector OR EVX-form (evor RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVRLW, 0xfc0007ff, 0x10000228, 0x0, // Vector Rotate Left Word EVX-form (evrlw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVRLWI, 0xfc0007ff, 0x1000022a, 0x0, // Vector Rotate Left Word Immediate EVX-form (evrlwi RT,RA,UI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+	{EVSEL, 0xfc0007f8, 0x10000278, 0x0, // Vector Select EVS-form (evsel RT,RA,RB,BFA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegField_29_31}},
+	{EVRNDW, 0xfc0007ff, 0x1000020c, 0xf800, // Vector Round Word EVX-form (evrndw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVSLW, 0xfc0007ff, 0x10000224, 0x0, // Vector Shift Left Word EVX-form (evslw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSPLATFI, 0xfc0007ff, 0x1000022b, 0xf800, // Vector Splat Fractional Immediate EVX-form (evsplatfi RT,SI)
+		[5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}},
+	{EVSRWIS, 0xfc0007ff, 0x10000223, 0x0, // Vector Shift Right Word Immediate Signed EVX-form (evsrwis RT,RA,UI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+	{EVSLWI, 0xfc0007ff, 0x10000226, 0x0, // Vector Shift Left Word Immediate EVX-form (evslwi RT,RA,UI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+	{EVSPLATI, 0xfc0007ff, 0x10000229, 0xf800, // Vector Splat Immediate EVX-form (evsplati RT,SI)
+		[5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}},
+	{EVSRWIU, 0xfc0007ff, 0x10000222, 0x0, // Vector Shift Right Word Immediate Unsigned EVX-form (evsrwiu RT,RA,UI)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
+	{EVSRWS, 0xfc0007ff, 0x10000221, 0x0, // Vector Shift Right Word Signed EVX-form (evsrws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTDD, 0xfc0007ff, 0x10000321, 0x0, // Vector Store Double of Double EVX-form (evstdd RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSRWU, 0xfc0007ff, 0x10000220, 0x0, // Vector Shift Right Word Unsigned EVX-form (evsrwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTDDX, 0xfc0007ff, 0x10000320, 0x0, // Vector Store Double of Double Indexed EVX-form (evstddx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTDH, 0xfc0007ff, 0x10000325, 0x0, // Vector Store Double of Four Halfwords EVX-form (evstdh RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSTDW, 0xfc0007ff, 0x10000323, 0x0, // Vector Store Double of Two Words EVX-form (evstdw RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSTDHX, 0xfc0007ff, 0x10000324, 0x0, // Vector Store Double of Four Halfwords Indexed EVX-form (evstdhx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTDWX, 0xfc0007ff, 0x10000322, 0x0, // Vector Store Double of Two Words Indexed EVX-form (evstdwx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTWHE, 0xfc0007ff, 0x10000331, 0x0, // Vector Store Word of Two Halfwords from Even EVX-form (evstwhe RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSTWHO, 0xfc0007ff, 0x10000335, 0x0, // Vector Store Word of Two Halfwords from Odd EVX-form (evstwho RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSTWWE, 0xfc0007ff, 0x10000339, 0x0, // Vector Store Word of Word from Even EVX-form (evstwwe RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSTWHEX, 0xfc0007ff, 0x10000330, 0x0, // Vector Store Word of Two Halfwords from Even Indexed EVX-form (evstwhex RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTWHOX, 0xfc0007ff, 0x10000334, 0x0, // Vector Store Word of Two Halfwords from Odd Indexed EVX-form (evstwhox RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTWWEX, 0xfc0007ff, 0x10000338, 0x0, // Vector Store Word of Word from Even Indexed EVX-form (evstwwex RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTWWO, 0xfc0007ff, 0x1000033d, 0x0, // Vector Store Word of Word from Odd EVX-form (evstwwo RS,D(RA))
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
+	{EVSUBFSMIAAW, 0xfc0007ff, 0x100004cb, 0xf800, // Vector Subtract Signed, Modulo, Integer to Accumulator Word EVX-form (evsubfsmiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVSTWWOX, 0xfc0007ff, 0x1000033c, 0x0, // Vector Store Word of Word from Odd Indexed EVX-form (evstwwox RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSUBFSSIAAW, 0xfc0007ff, 0x100004c3, 0xf800, // Vector Subtract Signed, Saturate, Integer to Accumulator Word EVX-form (evsubfssiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVSUBFUMIAAW, 0xfc0007ff, 0x100004ca, 0xf800, // Vector Subtract Unsigned, Modulo, Integer to Accumulator Word EVX-form (evsubfumiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVSUBFUSIAAW, 0xfc0007ff, 0x100004c2, 0xf800, // Vector Subtract Unsigned, Saturate, Integer to Accumulator Word EVX-form (evsubfusiaaw RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVSUBFW, 0xfc0007ff, 0x10000204, 0x0, // Vector Subtract from Word EVX-form (evsubfw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSUBIFW, 0xfc0007ff, 0x10000206, 0x0, // Vector Subtract Immediate from Word EVX-form (evsubifw RT,UI,RB)
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_15, ap_Reg_16_20}},
+	{EVXOR, 0xfc0007ff, 0x10000216, 0x0, // Vector XOR EVX-form (evxor RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSABS, 0xfc0007ff, 0x10000284, 0xf800, // Vector Floating-Point Single-Precision Absolute Value EVX-form (evfsabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVFSNABS, 0xfc0007ff, 0x10000285, 0xf800, // Vector Floating-Point Single-Precision Negative Absolute Value EVX-form (evfsnabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVFSNEG, 0xfc0007ff, 0x10000286, 0xf800, // Vector Floating-Point Single-Precision Negate EVX-form (evfsneg RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EVFSADD, 0xfc0007ff, 0x10000280, 0x0, // Vector Floating-Point Single-Precision Add EVX-form (evfsadd RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSMUL, 0xfc0007ff, 0x10000288, 0x0, // Vector Floating-Point Single-Precision Multiply EVX-form (evfsmul RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSSUB, 0xfc0007ff, 0x10000281, 0x0, // Vector Floating-Point Single-Precision Subtract EVX-form (evfssub RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSDIV, 0xfc0007ff, 0x10000289, 0x0, // Vector Floating-Point Single-Precision Divide EVX-form (evfsdiv RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSCMPGT, 0xfc0007ff, 0x1000028c, 0x600000, // Vector Floating-Point Single-Precision Compare Greater Than EVX-form (evfscmpgt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSCMPLT, 0xfc0007ff, 0x1000028d, 0x600000, // Vector Floating-Point Single-Precision Compare Less Than EVX-form (evfscmplt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSCMPEQ, 0xfc0007ff, 0x1000028e, 0x600000, // Vector Floating-Point Single-Precision Compare Equal EVX-form (evfscmpeq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSTSTGT, 0xfc0007ff, 0x1000029c, 0x600000, // Vector Floating-Point Single-Precision Test Greater Than EVX-form (evfststgt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSTSTLT, 0xfc0007ff, 0x1000029d, 0x600000, // Vector Floating-Point Single-Precision Test Less Than EVX-form (evfststlt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSTSTEQ, 0xfc0007ff, 0x1000029e, 0x600000, // Vector Floating-Point Single-Precision Test Equal EVX-form (evfststeq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVFSCFSI, 0xfc0007ff, 0x10000291, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Integer EVX-form (evfscfsi RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCFSF, 0xfc0007ff, 0x10000293, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Fraction EVX-form (evfscfsf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCFUI, 0xfc0007ff, 0x10000290, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (evfscfui RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCFUF, 0xfc0007ff, 0x10000292, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (evfscfuf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCTSI, 0xfc0007ff, 0x10000295, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer EVX-form (evfsctsi RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCTUI, 0xfc0007ff, 0x10000294, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (evfsctui RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCTSIZ, 0xfc0007ff, 0x1000029a, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (evfsctsiz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCTUIZ, 0xfc0007ff, 0x10000298, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (evfsctuiz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCTSF, 0xfc0007ff, 0x10000297, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Fraction EVX-form (evfsctsf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EVFSCTUF, 0xfc0007ff, 0x10000296, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (evfsctuf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSABS, 0xfc0007ff, 0x100002c4, 0xf800, // Floating-Point Single-Precision Absolute Value EVX-form (efsabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EFSNEG, 0xfc0007ff, 0x100002c6, 0xf800, // Floating-Point Single-Precision Negate EVX-form (efsneg RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EFSNABS, 0xfc0007ff, 0x100002c5, 0xf800, // Floating-Point Single-Precision Negative Absolute Value EVX-form (efsnabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EFSADD, 0xfc0007ff, 0x100002c0, 0x0, // Floating-Point Single-Precision Add EVX-form (efsadd RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSMUL, 0xfc0007ff, 0x100002c8, 0x0, // Floating-Point Single-Precision Multiply EVX-form (efsmul RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSSUB, 0xfc0007ff, 0x100002c1, 0x0, // Floating-Point Single-Precision Subtract EVX-form (efssub RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSDIV, 0xfc0007ff, 0x100002c9, 0x0, // Floating-Point Single-Precision Divide EVX-form (efsdiv RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSCMPGT, 0xfc0007ff, 0x100002cc, 0x600000, // Floating-Point Single-Precision Compare Greater Than EVX-form (efscmpgt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSCMPLT, 0xfc0007ff, 0x100002cd, 0x600000, // Floating-Point Single-Precision Compare Less Than EVX-form (efscmplt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSCMPEQ, 0xfc0007ff, 0x100002ce, 0x600000, // Floating-Point Single-Precision Compare Equal EVX-form (efscmpeq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSTSTGT, 0xfc0007ff, 0x100002dc, 0x600000, // Floating-Point Single-Precision Test Greater Than EVX-form (efststgt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSTSTLT, 0xfc0007ff, 0x100002dd, 0x600000, // Floating-Point Single-Precision Test Less Than EVX-form (efststlt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSTSTEQ, 0xfc0007ff, 0x100002de, 0x600000, // Floating-Point Single-Precision Test Equal EVX-form (efststeq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFSCFSI, 0xfc0007ff, 0x100002d1, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Integer EVX-form (efscfsi RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCFSF, 0xfc0007ff, 0x100002d3, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Fraction EVX-form (efscfsf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCTSI, 0xfc0007ff, 0x100002d5, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer EVX-form (efsctsi RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCFUI, 0xfc0007ff, 0x100002d0, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (efscfui RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCFUF, 0xfc0007ff, 0x100002d2, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (efscfuf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCTUI, 0xfc0007ff, 0x100002d4, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (efsctui RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCTSIZ, 0xfc0007ff, 0x100002da, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (efsctsiz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCTSF, 0xfc0007ff, 0x100002d7, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Fraction EVX-form (efsctsf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCTUIZ, 0xfc0007ff, 0x100002d8, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (efsctuiz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCTUF, 0xfc0007ff, 0x100002d6, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (efsctuf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDABS, 0xfc0007ff, 0x100002e4, 0xf800, // Floating-Point Double-Precision Absolute Value EVX-form (efdabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EFDNEG, 0xfc0007ff, 0x100002e6, 0xf800, // Floating-Point Double-Precision Negate EVX-form (efdneg RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EFDNABS, 0xfc0007ff, 0x100002e5, 0xf800, // Floating-Point Double-Precision Negative Absolute Value EVX-form (efdnabs RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{EFDADD, 0xfc0007ff, 0x100002e0, 0x0, // Floating-Point Double-Precision Add EVX-form (efdadd RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDMUL, 0xfc0007ff, 0x100002e8, 0x0, // Floating-Point Double-Precision Multiply EVX-form (efdmul RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDSUB, 0xfc0007ff, 0x100002e1, 0x0, // Floating-Point Double-Precision Subtract EVX-form (efdsub RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDDIV, 0xfc0007ff, 0x100002e9, 0x0, // Floating-Point Double-Precision Divide EVX-form (efddiv RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDCMPGT, 0xfc0007ff, 0x100002ec, 0x600000, // Floating-Point Double-Precision Compare Greater Than EVX-form (efdcmpgt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDCMPEQ, 0xfc0007ff, 0x100002ee, 0x600000, // Floating-Point Double-Precision Compare Equal EVX-form (efdcmpeq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDCMPLT, 0xfc0007ff, 0x100002ed, 0x600000, // Floating-Point Double-Precision Compare Less Than EVX-form (efdcmplt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDTSTGT, 0xfc0007ff, 0x100002fc, 0x600000, // Floating-Point Double-Precision Test Greater Than EVX-form (efdtstgt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDTSTLT, 0xfc0007ff, 0x100002fd, 0x600000, // Floating-Point Double-Precision Test Less Than EVX-form (efdtstlt BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDCFSI, 0xfc0007ff, 0x100002f1, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer EVX-form (efdcfsi RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDTSTEQ, 0xfc0007ff, 0x100002fe, 0x600000, // Floating-Point Double-Precision Test Equal EVX-form (efdtsteq BF,RA,RB)
+		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
+	{EFDCFUI, 0xfc0007ff, 0x100002f0, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer EVX-form (efdcfui RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCFSID, 0xfc0007ff, 0x100002e3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer Doubleword EVX-form (efdcfsid RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCFSF, 0xfc0007ff, 0x100002f3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Fraction EVX-form (efdcfsf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCFUF, 0xfc0007ff, 0x100002f2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Fraction EVX-form (efdcfuf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCFUID, 0xfc0007ff, 0x100002e2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer Doubleword EVX-form (efdcfuid RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTSI, 0xfc0007ff, 0x100002f5, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer EVX-form (efdctsi RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTUI, 0xfc0007ff, 0x100002f4, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer EVX-form (efdctui RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTSIDZ, 0xfc0007ff, 0x100002eb, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero EVX-form (efdctsidz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTUIDZ, 0xfc0007ff, 0x100002ea, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero EVX-form (efdctuidz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTSIZ, 0xfc0007ff, 0x100002fa, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero EVX-form (efdctsiz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTSF, 0xfc0007ff, 0x100002f7, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Fraction EVX-form (efdctsf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTUF, 0xfc0007ff, 0x100002f6, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Fraction EVX-form (efdctuf RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCTUIZ, 0xfc0007ff, 0x100002f8, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero EVX-form (efdctuiz RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFDCFS, 0xfc0007ff, 0x100002ef, 0x1f0000, // Floating-Point Double-Precision Convert from Single-Precision EVX-form (efdcfs RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{EFSCFD, 0xfc0007ff, 0x100002cf, 0x1f0000, // Floating-Point Single-Precision Convert from Double-Precision EVX-form (efscfd RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{DLMZB, 0xfc0007ff, 0x7c00009c, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{DLMZB_, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
+	{MACCHW, 0xfc0007ff, 0x10000158, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHW_, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWO, 0xfc0007ff, 0x10000558, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWO_, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWS, 0xfc0007ff, 0x100001d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWS_, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWSO_, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWU, 0xfc0007ff, 0x10000118, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWU_, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWUO, 0xfc0007ff, 0x10000518, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWUO_, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWSU, 0xfc0007ff, 0x10000198, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWSU_, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACCHWSUO_, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHW, 0xfc0007ff, 0x10000058, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHW_, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWO, 0xfc0007ff, 0x10000458, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWO_, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWS, 0xfc0007ff, 0x100000d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWS_, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWSO_, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWU, 0xfc0007ff, 0x10000018, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWU_, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWUO, 0xfc0007ff, 0x10000418, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWUO_, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWSU, 0xfc0007ff, 0x10000098, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWSU_, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACHHWSUO_, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHW, 0xfc0007ff, 0x10000358, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHW_, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWO, 0xfc0007ff, 0x10000758, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWO_, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWS, 0xfc0007ff, 0x100003d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWS_, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWSO_, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWU, 0xfc0007ff, 0x10000318, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWU_, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWUO, 0xfc0007ff, 0x10000718, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWUO_, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULCHW, 0xfc0007ff, 0x10000150, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULCHW_, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWSU, 0xfc0007ff, 0x10000398, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWSU_, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MACLHWSUO_, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULCHWU, 0xfc0007ff, 0x10000110, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULCHWU_, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHHW, 0xfc0007ff, 0x10000050, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHHW_, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLHW, 0xfc0007ff, 0x10000350, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLHW_, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHHWU, 0xfc0007ff, 0x10000010, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULHHWU_, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLHWU, 0xfc0007ff, 0x10000310, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MULLHWU_, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHW, 0xfc0007ff, 0x1000015c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHW_, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHWO_, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHWS_, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACCHWSO_, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHW, 0xfc0007ff, 0x1000005c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHW_, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHWO_, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHWS_, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACHHWSO_, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHW, 0xfc0007ff, 0x1000035c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHW_, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHWO_, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHWS_, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{NMACLHWSO_, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001, // Instruction Cache Block Invalidate X-form (icbi RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{ICBT, 0xfc0007fe, 0x7c00002c, 0x2000001, // Instruction Cache Block Touch X-form (icbt CT, RA, RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBA, 0xfc0007fe, 0x7c0005ec, 0x3e00001, // Data Cache Block Allocate X-form (dcba RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt RA,RB,TH)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
+	{DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt TH,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
+	{DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst TH,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBZ, 0xfc0007fe, 0x7c0007ec, 0x3e00001, // Data Cache Block set to Zero X-form (dcbz RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBST, 0xfc0007fe, 0x7c00006c, 0x3e00001, // Data Cache Block Store X-form (dcbst RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBF, 0xfc0007fe, 0x7c0000ac, 0x3800001, // Data Cache Block Flush X-form (dcbf RA,RB,L)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}},
+	{ISYNC, 0xfc0007fe, 0x4c00012c, 0x3fff801, // Instruction Synchronize XL-form (isync)
+		[5]*argField{}},
+	{LBARX, 0xfc0007ff, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LBARX, 0xfc0007fe, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB,EH)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+	{LHARX, 0xfc0007ff, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHARX, 0xfc0007fe, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB,EH)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+	{LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWARX, 0xfc0007fe, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB,EH)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+	{STBCX_, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STHCX_, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STWCX_, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDARX, 0xfc0007ff, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDARX, 0xfc0007fe, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+	{STDCX_, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LQARX, 0xfc0007ff, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LQARX, 0xfc0007fe, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
+	{STQCX_, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801, // Synchronize X-form (sync L, E)
+		[5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}},
+	{EIEIO, 0xfc0007fe, 0x7c0006ac, 0x3fff801, // Enforce In-order Execution of I/O X-form (eieio)
+		[5]*argField{}},
+	{MBAR, 0xfc0007fe, 0x7c0006ac, 0x1ff801, // Memory Barrier X-form (mbar MO)
+		[5]*argField{ap_ImmUnsigned_6_10}},
+	{WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801, // Wait X-form (wait WC)
+		[5]*argField{ap_ImmUnsigned_9_10}},
+	{TBEGIN_, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R)
+		[5]*argField{ap_ImmUnsigned_10_10}},
+	{TEND_, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A)
+		[5]*argField{ap_ImmUnsigned_6_6}},
+	{TABORT_, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA)
+		[5]*argField{ap_Reg_11_15}},
+	{TABORTWC_, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{TABORTWCI_, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
+	{TABORTDC_, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{TABORTDCI_, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
+	{TSR_, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L)
+		[5]*argField{ap_ImmUnsigned_10_10}},
+	{TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801, // Transaction Check X-form (tcheck BF)
+		[5]*argField{ap_CondRegField_6_8}},
+	{MFTB, 0xfc0007fe, 0x7c0002e6, 0x1, // Move From Time Base XFX-form (mftb RT,TBR)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+	{RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001, // Return from Event-Based Branch XL-form (rfebb S)
+		[5]*argField{ap_ImmUnsigned_20_20}},
+	{LBDX, 0xfc0007fe, 0x7c000406, 0x1, // Load Byte with Decoration Indexed X-form (lbdx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHDX, 0xfc0007fe, 0x7c000446, 0x1, // Load Halfword with Decoration Indexed X-form (lhdx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWDX, 0xfc0007fe, 0x7c000486, 0x1, // Load Word with Decoration Indexed X-form (lwdx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDDX, 0xfc0007fe, 0x7c0004c6, 0x1, // Load Doubleword with Decoration Indexed X-form (lddx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LFDDX, 0xfc0007fe, 0x7c000646, 0x1, // Load Floating Doubleword with Decoration Indexed X-form (lfddx FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STBDX, 0xfc0007fe, 0x7c000506, 0x1, // Store Byte with Decoration Indexed X-form (stbdx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STHDX, 0xfc0007fe, 0x7c000546, 0x1, // Store Halfword with Decoration Indexed X-form (sthdx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STWDX, 0xfc0007fe, 0x7c000586, 0x1, // Store Word with Decoration Indexed X-form (stwdx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STDDX, 0xfc0007fe, 0x7c0005c6, 0x1, // Store Doubleword with Decoration Indexed X-form (stddx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFDDX, 0xfc0007fe, 0x7c000746, 0x1, // Store Floating Doubleword with Decoration Indexed X-form (stfddx FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DSN, 0xfc0007fe, 0x7c0003c6, 0x3e00001, // Decorated Storage Notify X-form (dsn RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{ECIWX, 0xfc0007fe, 0x7c00026c, 0x1, // External Control In Word Indexed X-form (eciwx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ECOWX, 0xfc0007fe, 0x7c00036c, 0x1, // External Control Out Word Indexed X-form (ecowx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
+		[5]*argField{ap_ImmUnsigned_20_26}},
+	{RFID, 0xfc0007fe, 0x4c000024, 0x3fff801, // Return From Interrupt Doubleword XL-form (rfid)
+		[5]*argField{}},
+	{HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801, // Hypervisor Return From Interrupt Doubleword XL-form (hrfid)
+		[5]*argField{}},
+	{DOZE, 0xfc0007fe, 0x4c000324, 0x3fff801, // Doze XL-form (doze)
+		[5]*argField{}},
+	{NAP, 0xfc0007fe, 0x4c000364, 0x3fff801, // Nap XL-form (nap)
+		[5]*argField{}},
+	{SLEEP, 0xfc0007fe, 0x4c0003a4, 0x3fff801, // Sleep XL-form (sleep)
+		[5]*argField{}},
+	{RVWINKLE, 0xfc0007fe, 0x4c0003e4, 0x3fff801, // Rip Van Winkle XL-form (rvwinkle)
+		[5]*argField{}},
+	{LBZCIX, 0xfc0007fe, 0x7c0006aa, 0x1, // Load Byte and Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWZCIX, 0xfc0007fe, 0x7c00062a, 0x1, // Load Word and Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHZCIX, 0xfc0007fe, 0x7c00066a, 0x1, // Load Halfword and Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDCIX, 0xfc0007fe, 0x7c0006ea, 0x1, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STBCIX, 0xfc0007fe, 0x7c0007aa, 0x1, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STWCIX, 0xfc0007fe, 0x7c00072a, 0x1, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STHCIX, 0xfc0007fe, 0x7c00076a, 0x1, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{TRECLAIM_, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA)
+		[5]*argField{ap_Reg_11_15}},
+	{TRECHKPT_, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.)
+		[5]*argField{}},
+	{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
+		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
+	{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+	{MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To Machine State Register X-form (mtmsr RS,L)
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
+	{MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801, // Move To Machine State Register Doubleword X-form (mtmsrd RS,L)
+		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
+	{MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT)
+		[5]*argField{ap_Reg_6_10}},
+	{SLBIE, 0xfc0007fe, 0x7c000364, 0x3ff0001, // SLB Invalidate Entry X-form (slbie RB)
+		[5]*argField{ap_Reg_16_20}},
+	{SLBIA, 0xfc0007fe, 0x7c0003e4, 0x31ff801, // SLB Invalidate All X-form (slbia IH)
+		[5]*argField{ap_ImmUnsigned_8_10}},
+	{SLBMTE, 0xfc0007fe, 0x7c000324, 0x1f0001, // SLB Move To Entry X-form (slbmte RS,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{SLBMFEV, 0xfc0007fe, 0x7c0006a6, 0x1f0001, // SLB Move From Entry VSID X-form (slbmfev RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001, // SLB Move From Entry ESID X-form (slbmfee RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{SLBFEE_, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801, // Move To Segment Register X-form (mtsr SR,RS)
+		[5]*argField{ap_SpReg_12_15, ap_Reg_6_10}},
+	{MTSRIN, 0xfc0007fe, 0x7c0001e4, 0x1f0001, // Move To Segment Register Indirect X-form (mtsrin RS,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{MFSR, 0xfc0007fe, 0x7c0004a6, 0x10f801, // Move From Segment Register X-form (mfsr RT,SR)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_12_15}},
+	{MFSRIN, 0xfc0007fe, 0x7c000526, 0x1f0001, // Move From Segment Register Indirect X-form (mfsrin RT,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
+	{TLBIE, 0xfc0007fe, 0x7c000264, 0x1f0001, // TLB Invalidate Entry X-form (tlbie RB,RS)
+		[5]*argField{ap_Reg_16_20, ap_Reg_6_10}},
+	{TLBIEL, 0xfc0007fe, 0x7c000224, 0x3ff0001, // TLB Invalidate Entry Local X-form (tlbiel RB)
+		[5]*argField{ap_Reg_16_20}},
+	{TLBIA, 0xfc0007fe, 0x7c0002e4, 0x3fff801, // TLB Invalidate All X-form (tlbia)
+		[5]*argField{}},
+	{TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync)
+		[5]*argField{}},
+	{MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB)
+		[5]*argField{ap_Reg_16_20}},
+	{MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB)
+		[5]*argField{ap_Reg_16_20}},
+	{MSGSNDP, 0xfc0007fe, 0x7c00011c, 0x3ff0001, // Message Send Privileged X-form (msgsndp RB)
+		[5]*argField{ap_Reg_16_20}},
+	{MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001, // Message Clear Privileged X-form (msgclrp RB)
+		[5]*argField{ap_Reg_16_20}},
+	{MTTMR, 0xfc0007fe, 0x7c0003dc, 0x1, // Move To Thread Management Register XFX-form (mttmr TMR,RS)
+		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
+	{SC, 0xfc000002, 0x44000002, 0x3fffffd, // System Call SC-form (sc)
+		[5]*argField{}},
+	{RFI, 0xfc0007fe, 0x4c000064, 0x3fff801, // Return From Interrupt XL-form (rfi)
+		[5]*argField{}},
+	{RFCI, 0xfc0007fe, 0x4c000066, 0x3fff801, // Return From Critical Interrupt XL-form (rfci)
+		[5]*argField{}},
+	{RFDI, 0xfc0007fe, 0x4c00004e, 0x3fff801, // Return From Debug Interrupt X-form (rfdi)
+		[5]*argField{}},
+	{RFMCI, 0xfc0007fe, 0x4c00004c, 0x3fff801, // Return From Machine Check Interrupt XL-form (rfmci)
+		[5]*argField{}},
+	{RFGI, 0xfc0007fe, 0x4c0000cc, 0x3fff801, // Return From Guest Interrupt XL-form (rfgi)
+		[5]*argField{}},
+	{EHPRIV, 0xfc0007fe, 0x7c00021c, 0x1, // Embedded Hypervisor Privilege XL-form (ehpriv OC)
+		[5]*argField{ap_ImmUnsigned_6_20}},
+	{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
+		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
+	{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+	{MTDCR, 0xfc0007fe, 0x7c000386, 0x1, // Move To Device Control Register XFX-form (mtdcr DCRN,RS)
+		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
+	{MTDCRX, 0xfc0007fe, 0x7c000306, 0xf801, // Move To Device Control Register Indexed X-form (mtdcrx RA,RS)
+		[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
+	{MFDCR, 0xfc0007fe, 0x7c000286, 0x1, // Move From Device Control Register XFX-form (mfdcr RT,DCRN)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
+	{MFDCRX, 0xfc0007fe, 0x7c000206, 0xf801, // Move From Device Control Register Indexed X-form (mfdcrx RT,RA)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
+	{MTMSR, 0xfc0007fe, 0x7c000124, 0x1ff801, // Move To Machine State Register X-form (mtmsr RS)
+		[5]*argField{ap_Reg_6_10}},
+	{MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT)
+		[5]*argField{ap_Reg_6_10}},
+	{WRTEE, 0xfc0007fe, 0x7c000106, 0x1ff801, // Write MSR External Enable X-form (wrtee RS)
+		[5]*argField{ap_Reg_6_10}},
+	{WRTEEI, 0xfc0007fe, 0x7c000146, 0x3ff7801, // Write MSR External Enable Immediate X-form (wrteei E)
+		[5]*argField{ap_ImmUnsigned_16_16}},
+	{LBEPX, 0xfc0007fe, 0x7c0000be, 0x1, // Load Byte by External Process ID Indexed X-form (lbepx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LHEPX, 0xfc0007fe, 0x7c00023e, 0x1, // Load Halfword by External Process ID Indexed X-form (lhepx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LWEPX, 0xfc0007fe, 0x7c00003e, 0x1, // Load Word by External Process ID Indexed X-form (lwepx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LDEPX, 0xfc0007fe, 0x7c00003a, 0x1, // Load Doubleword by External Process ID Indexed X-form (ldepx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STBEPX, 0xfc0007fe, 0x7c0001be, 0x1, // Store Byte by External Process ID Indexed X-form (stbepx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STHEPX, 0xfc0007fe, 0x7c00033e, 0x1, // Store Halfword by External Process ID Indexed X-form (sthepx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STWEPX, 0xfc0007fe, 0x7c00013e, 0x1, // Store Word by External Process ID Indexed X-form (stwepx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STDEPX, 0xfc0007fe, 0x7c00013a, 0x1, // Store Doubleword by External Process ID Indexed X-form (stdepx RS,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBSTEP, 0xfc0007fe, 0x7c00007e, 0x3e00001, // Data Cache Block Store by External PID X-form (dcbstep RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBTEP, 0xfc0007fe, 0x7c00027e, 0x1, // Data Cache Block Touch by External PID X-form (dcbtep TH,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBFEP, 0xfc0007fe, 0x7c0000fe, 0x3800001, // Data Cache Block Flush by External PID X-form (dcbfep RA,RB,L)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}},
+	{DCBTSTEP, 0xfc0007fe, 0x7c0001fe, 0x1, // Data Cache Block Touch for Store by External PID X-form (dcbtstep TH,RA,RB)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ICBIEP, 0xfc0007fe, 0x7c0007be, 0x3e00001, // Instruction Cache Block Invalidate by External PID X-form (icbiep RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBZEP, 0xfc0007fe, 0x7c0007fe, 0x3e00001, // Data Cache Block set to Zero by External PID X-form (dcbzep RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{LFDEPX, 0xfc0007fe, 0x7c0004be, 0x1, // Load Floating-Point Double by External Process ID Indexed X-form (lfdepx FRT,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STFDEPX, 0xfc0007fe, 0x7c0005be, 0x1, // Store Floating-Point Double by External Process ID Indexed X-form (stfdepx FRS,RA,RB)
+		[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVLDDEPX, 0xfc0007fe, 0x7c00063e, 0x1, // Vector Load Doubleword into Doubleword by External Process ID Indexed EVX-form (evlddepx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{EVSTDDEPX, 0xfc0007fe, 0x7c00073e, 0x1, // Vector Store Doubleword into Doubleword by External Process ID Indexed EVX-form (evstddepx RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVEPX, 0xfc0007fe, 0x7c00024e, 0x1, // Load Vector by External Process ID Indexed X-form (lvepx VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LVEPXL, 0xfc0007fe, 0x7c00020e, 0x1, // Load Vector by External Process ID Indexed LRU X-form (lvepxl VRT,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVEPX, 0xfc0007fe, 0x7c00064e, 0x1, // Store Vector by External Process ID Indexed X-form (stvepx VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STVEPXL, 0xfc0007fe, 0x7c00060e, 0x1, // Store Vector by External Process ID Indexed LRU X-form (stvepxl VRS,RA,RB)
+		[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001, // Data Cache Block Invalidate X-form (dcbi RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBLQ_, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ICBLQ_, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001, // Data Cache Block Touch and Lock Set X-form (dcbtls CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBTSTLS, 0xfc0007fe, 0x7c00010c, 0x2000001, // Data Cache Block Touch for Store and Lock Set X-form (dcbtstls CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ICBTLS, 0xfc0007fe, 0x7c0003cc, 0x2000001, // Instruction Cache Block Touch and Lock Set X-form (icbtls CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ICBLC, 0xfc0007fe, 0x7c0001cc, 0x2000001, // Instruction Cache Block Lock Clear X-form (icblc CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{DCBLC, 0xfc0007fe, 0x7c00030c, 0x2000001, // Data Cache Block Lock Clear X-form (dcblc CT,RA,RB)
+		[5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{TLBIVAX, 0xfc0007fe, 0x7c000624, 0x3e00001, // TLB Invalidate Virtual Address Indexed X-form (tlbivax RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{TLBILX, 0xfc0007fe, 0x7c000024, 0x3800001, // TLB Invalidate Local Indexed X-form (tlbilx RA,RB])
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001, // TLB Search Indexed X-form (tlbsx RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{TLBSRX_, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801, // TLB Read Entry X-form (tlbre)
+		[5]*argField{}},
+	{TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync)
+		[5]*argField{}},
+	{TLBWE, 0xfc0007fe, 0x7c0007a4, 0x3fff801, // TLB Write Entry X-form (tlbwe)
+		[5]*argField{}},
+	{DNH, 0xfc0007fe, 0x4c00018c, 0x1, // Debugger Notify Halt XFX-form (dnh DUI,DUIS)
+		[5]*argField{ap_ImmUnsigned_6_10, ap_ImmUnsigned_11_20}},
+	{MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB)
+		[5]*argField{ap_Reg_16_20}},
+	{MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB)
+		[5]*argField{ap_Reg_16_20}},
+	{DCI, 0xfc0007fe, 0x7c00038c, 0x21ff801, // Data Cache Invalidate X-form (dci CT)
+		[5]*argField{ap_ImmUnsigned_7_10}},
+	{ICI, 0xfc0007fe, 0x7c00078c, 0x21ff801, // Instruction Cache Invalidate X-form (ici CT)
+		[5]*argField{ap_ImmUnsigned_7_10}},
+	{DCREAD, 0xfc0007fe, 0x7c0003cc, 0x1, // Data Cache Read X-form (dcread RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{ICREAD, 0xfc0007fe, 0x7c0007cc, 0x3e00001, // Instruction Cache Read X-form (icread RA,RB)
+		[5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
+	{MFPMR, 0xfc0007fe, 0x7c00029c, 0x1, // Move From Performance Monitor Register XFX-form (mfpmr RT,PMRN)
+		[5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
+	{MTPMR, 0xfc0007fe, 0x7c00039c, 0x1, // Move To Performance Monitor Register XFX-form (mtpmr PMRN,RS)
+		[5]*argField{ap_SpReg_11_20, ap_Reg_6_10}},
+}

ppc64/ppc64asm/testdata/decode.txt

diff --git a/ppc64/ppc64asm/testdata/decode.txt b/ppc64/ppc64asm/testdata/decode.txt
new file mode 100644
index 0000000..956d5cd
--- /dev/null
+++ b/ppc64/ppc64asm/testdata/decode.txt
@@ -0,0 +1,25 @@
+6d746162|	gnu	xoris r20,r11,24930
+4c040000|	gnu	mcrf cr0,cr1
+88000017|	gnu	lbz r0,23(0)
+4abaa88a|	gnu	ba 0xfebaa888
+7d8fc2a6|	gnu	mfspr r12,783
+00000000|	gnu	error: unknown instruction
+a1841e80|	gnu	lhz r12,7808(r4)
+42093d10|	gnu	bc 16,4*cr2+gt,.+0x3d10
+e38d5b90|	gnu	lq r28,23440(r13)
+84127a20|	gnu	lwzu r0,31264(r18)
+c61bb730|	gnu	lfsu f16,-18640(r27)
+0825f440|	gnu	tdi 1,r5,-3008
+a9a912c1|	gnu	lha r13,4801(r9)
+ebb24fd1|	gnu	ldu r29,20432(r18)
+b1ce0612|	gnu	sth r14,1554(r14)
+f3d74322|	gnu	xvcvdpuxws v30,v40
+945c62a2|	gnu	stwu r2,25250(r28)
+9c8156e3|	gnu	stbu r4,22243(r1)
+f91b9c7a|	gnu	stq r8,-25480(r27)
+2c1c81b4|	gnu	cmpwi r28,-32332
+f87b904d|	gnu	stdu r3,-28596(r27)
+eab3c832|	gnu	lwa r21,-14288(r19)
+4320336b|	gnu	bcla 25,lt,0x3368
+7e40092e|	gnu	stwx r18,0,r1
+7c103c2c|	gnu	lwbrx r0,r16,r7

ppc64/ppc64map/map.go

diff --git a/ppc64/ppc64map/map.go b/ppc64/ppc64map/map.go
new file mode 100644
index 0000000..e6f5ef5
--- /dev/null
+++ b/ppc64/ppc64map/map.go
@@ -0,0 +1,592 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Power64map constructs the Power64 opcode map from the instruction set CSV file.
+//
+// Usage:
+//	ppc64map [-fmt=format] ppc64.csv
+//
+// The known output formats are:
+//
+//  text (default) - print decoding tree in text form
+//  decoder - print decoding tables for the ppc64asm package
+package main
+
+import (
+	"bufio"
+	"bytes"
+	"encoding/csv"
+	"flag"
+	"fmt"
+	gofmt "go/format"
+	"log"
+	"os"
+	"regexp"
+	"strconv"
+	"strings"
+	"text/template"
+
+	asm "golang.org/x/arch/ppc64/ppc64asm"
+)
+
+var format = flag.String("fmt", "text", "output format: text, decoder")
+var debug = flag.Bool("debug", false, "enable debugging output")
+
+var inputFile string
+
+func usage() {
+	fmt.Fprintf(os.Stderr, "usage: ppc64map [-fmt=format] ppc64.csv\n")
+	os.Exit(2)
+}
+
+func main() {
+	log.SetFlags(0)
+	log.SetPrefix("ppc64map: ")
+
+	flag.Usage = usage
+	flag.Parse()
+	if flag.NArg() != 1 {
+		usage()
+	}
+
+	inputFile = flag.Arg(0)
+
+	var print func(*Prog)
+	switch *format {
+	default:
+		log.Fatalf("unknown output format %q", *format)
+	case "text":
+		print = printText
+	case "decoder":
+		print = printDecoder
+	}
+
+	p, err := readCSV(flag.Arg(0))
+	log.Printf("Parsed %d instruction forms.", len(p.Insts))
+	if err != nil {
+		log.Fatal(err)
+	}
+
+	print(p)
+}
+
+// readCSV reads the CSV file and returns the corresponding Prog.
+// It may print details about problems to standard error using the log package.
+func readCSV(file string) (*Prog, error) {
+	// Read input.
+	// Skip leading blank and # comment lines.
+	f, err := os.Open(file)
+	if err != nil {
+		return nil, err
+	}
+	b := bufio.NewReader(f)
+	for {
+		c, err := b.ReadByte()
+		if err != nil {
+			break
+		}
+		if c == '\n' {
+			continue
+		}
+		if c == '#' {
+			b.ReadBytes('\n')
+			continue
+		}
+		b.UnreadByte()
+		break
+	}
+	table, err := csv.NewReader(b).ReadAll()
+	if err != nil {
+		return nil, fmt.Errorf("parsing %s: %v", file, err)
+	}
+	if len(table) == 0 {
+		return nil, fmt.Errorf("empty csv input")
+	}
+	if len(table[0]) < 4 {
+		return nil, fmt.Errorf("csv too narrow: need at least four columns")
+	}
+
+	p := &Prog{}
+	for _, row := range table {
+		add(p, row[0], row[1], row[2], row[3])
+	}
+	return p, nil
+}
+
+type Prog struct {
+	Insts    []Inst
+	OpRanges map[string]string
+}
+
+type Field struct {
+	Name      string
+	BitFields asm.BitFields
+	Type      asm.ArgType
+	Shift     uint8
+}
+
+func (f Field) String() string {
+	return fmt.Sprintf("%v(%s%v)", f.Type, f.Name, f.BitFields)
+}
+
+type Inst struct {
+	Text     string
+	Encoding string
+	Op       string
+	Mask     uint32
+	Value    uint32
+	DontCare uint32
+	Fields   []Field
+}
+
+func (i Inst) String() string {
+	return fmt.Sprintf("%s (%s) %08x/%08x[%08x] %v (%s)", i.Op, i.Encoding, i.Value, i.Mask, i.DontCare, i.Fields, i.Text)
+}
+
+type Arg struct {
+	Name string
+	Bits int8
+	Offs int8
+}
+
+func (a Arg) String() string {
+	return fmt.Sprintf("%s[%d:%d]", a.Name, a.Offs, a.Offs+a.Bits-1)
+}
+
+func (a Arg) Maximum() int {
+	return 1<<uint8(a.Bits) - 1
+}
+
+func (a Arg) BitMask() uint32 {
+	return uint32(a.Maximum()) << a.Shift()
+}
+
+func (a Arg) Shift() uint8 {
+	return uint8(32 - a.Offs - a.Bits)
+}
+
+type Args []Arg
+
+func (as Args) String() string {
+	ss := make([]string, len(as))
+	for i := range as {
+		ss[i] = as[i].String()
+	}
+	return strings.Join(ss, "|")
+}
+
+func (as Args) Find(name string) int {
+	for i := range as {
+		if as[i].Name == name {
+			return i
+		}
+	}
+	return -1
+}
+
+func (as *Args) Append(a Arg) {
+	*as = append(*as, a)
+}
+
+func (as *Args) Delete(i int) {
+	*as = append((*as)[:i], (*as)[i+1:]...)
+}
+
+func (as Args) Clone() Args {
+	return append(Args{}, as...)
+}
+
+func (a Arg) isDontCare() bool {
+	return a.Name[0] == '/' && a.Name == strings.Repeat("/", len(a.Name))
+}
+
+// add adds the entry from the CSV described by text, mnemonics, encoding, and tags
+// to the program p.
+func add(p *Prog, text, mnemonics, encoding, tags string) {
+	if strings.HasPrefix(mnemonics, "e_") || strings.HasPrefix(mnemonics, "se_") {
+		// TODO(minux): VLE instructions are ignored.
+		return
+	}
+
+	// Parse encoding, building size and offset of each field.
+	// The first field in the encoding is the smallest offset.
+	// And note the MSB is bit 0, not bit 31.
+	// Example: "31@0|RS@6|RA@11|///@16|26@21|Rc@31|"
+	var args Args
+	fields := strings.Split(encoding, "|")
+	for i, f := range fields {
+		name, off := "", -1
+		if f == "" {
+			off = 32
+			if i == 0 || i != len(fields)-1 {
+				fmt.Fprintf(os.Stderr, "%s: wrong %d-th encoding field: %q\n", text, i, f)
+				return
+			}
+		} else {
+			j := strings.Index(f, "@")
+			if j < 0 {
+				fmt.Fprintf(os.Stderr, "%s: wrong %d-th encoding field: %q\n", text, i, f)
+				continue
+			}
+			off, _ = strconv.Atoi(f[j+1:])
+			name = f[:j]
+		}
+		if len(args) > 0 {
+			args[len(args)-1].Bits += int8(off)
+		}
+		if name != "" {
+			arg := Arg{Name: name, Offs: int8(off), Bits: int8(-off)}
+			args.Append(arg)
+		}
+	}
+
+	var mask, value, dontCare uint32
+	for i := 0; i < len(args); i++ {
+		arg := args[i]
+		v, err := strconv.Atoi(arg.Name)
+		switch {
+		case err == nil: // is a numbered field
+			if v < 0 || v > arg.Maximum() {
+				fmt.Fprintf(os.Stderr, "%s: field %s value (%d) is out of range (%d-bit)\n", text, arg, v, arg.Bits)
+			}
+			mask |= arg.BitMask()
+			value |= uint32(v) << arg.Shift()
+			args.Delete(i)
+			i--
+		case arg.Name[0] == '/': // is don't care
+			if arg.Name != strings.Repeat("/", len(arg.Name)) {
+				log.Fatalf("%s: arg %v named like a don't care bit, but it's not", text, arg)
+			}
+			dontCare |= arg.BitMask()
+			args.Delete(i)
+			i--
+		default:
+			continue
+		}
+	}
+
+	// rename duplicated fields (e.g. 30@0|RS@6|RA@11|sh@16|mb@21|0@27|sh@30|Rc@31|)
+	// but only support two duplicated fields
+	for i := 1; i < len(args); i++ {
+		if args[:i].Find(args[i].Name) >= 0 {
+			args[i].Name += "2"
+		}
+		if args[:i].Find(args[i].Name) >= 0 {
+			log.Fatalf("%s: more than one duplicated fields: %s", text, args)
+		}
+	}
+
+	// sanity checks
+	if mask&dontCare != 0 {
+		log.Fatalf("%s: mask (%08x) and don't care (%08x) collide", text, mask, dontCare)
+	}
+	if value&^mask != 0 {
+		log.Fatalf("%s: value (%08x) out of range of mask (%08x)", text, value, mask)
+	}
+	var argMask uint32
+	for _, arg := range args {
+		if arg.Bits <= 0 || arg.Bits > 32 || arg.Offs > 31 || arg.Offs <= 0 {
+			log.Fatalf("%s: arg %v has wrong bit field spec", text, arg)
+		}
+		if mask&arg.BitMask() != 0 {
+			log.Fatalf("%s: mask (%08x) intersect with arg %v", text, mask, arg)
+		}
+		if argMask&arg.BitMask() != 0 {
+			log.Fatalf("%s: arg %v overlap with other args %v", text, arg, args)
+		}
+		argMask |= arg.BitMask()
+	}
+	if 1<<32-1 != mask|dontCare|argMask {
+		log.Fatalf("%s: args %v fail to cover all 32 bits", text, args)
+	}
+
+	// split mnemonics into individual instructions
+	// example: "b target_addr (AA=0 LK=0)|ba target_addr (AA=1 LK=0)|bl target_addr (AA=0 LK=1)|bla target_addr (AA=1 LK=1)"
+	insts := strings.Split(categoryRe.ReplaceAllString(mnemonics, ""), "|")
+	for _, inst := range insts {
+		value, mask := value, mask
+		args := args.Clone()
+		if inst == "" {
+			continue
+		}
+		// amend mask and value
+		parts := instRe.FindStringSubmatch(inst)
+		if parts == nil {
+			log.Fatalf("%v couldn't match %s", instRe, inst)
+		}
+		conds := condRe.FindAllStringSubmatch(parts[2], -1)
+		isPCRel := true
+		for _, cond := range conds {
+			i := args.Find(cond[1])
+			v, _ := strconv.ParseInt(cond[2], 16, 32) // the regular expression has checked the number format
+			if i < 0 {
+				log.Fatalf("%s: %s don't contain arg %s used in %s", text, args, cond[1], inst)
+			}
+			if cond[1] == "AA" && v == 1 {
+				isPCRel = false
+			}
+			mask |= args[i].BitMask()
+			value |= uint32(v) << args[i].Shift()
+			args.Delete(i)
+		}
+		inst := Inst{Text: text, Encoding: parts[1], Value: value, Mask: mask, DontCare: dontCare}
+
+		// order inst.Args according to mnemonics order
+		for i, opr := range operandRe.FindAllString(parts[1], -1) {
+			if i == 0 { // operation
+				inst.Op = opr
+				continue
+			}
+			field := Field{Name: opr}
+			typ := asm.TypeUnknown
+			var shift uint8
+			opr2 := ""
+			switch opr {
+			case "target_addr":
+				shift = 2
+				if isPCRel {
+					typ = asm.TypePCRel
+				} else {
+					typ = asm.TypeLabel
+				}
+				if args.Find("LI") >= 0 {
+					opr = "LI"
+				} else {
+					opr = "BD"
+				}
+			case "UI", "BO", "BH", "TH", "LEV", "NB", "L", "TO", "FXM", "U", "W", "FLM", "UIM", "SHB", "SHW", "ST", "SIX", "PS", "DCM", "DGM", "RMC", "R", "SP", "S", "DM", "CT", "EH", "E", "MO", "WC", "A", "IH", "OC", "DUI", "DUIS":
+				typ = asm.TypeImmUnsigned
+				if i := args.Find(opr); i < 0 {
+					opr = "D"
+				}
+			case "SH":
+				typ = asm.TypeImmUnsigned
+				if args.Find("sh2") >= 0 { // sh2 || sh
+					opr = "sh2"
+					opr2 = "sh"
+				}
+			case "MB", "ME":
+				typ = asm.TypeImmUnsigned
+				if n := strings.ToLower(opr); args.Find(n) >= 0 {
+					opr = n // xx[5] || xx[0:4]
+				}
+			case "SI", "SIM", "TE":
+				typ = asm.TypeImmSigned
+				if i := args.Find(opr); i < 0 {
+					opr = "D"
+				}
+			case "DS":
+				typ = asm.TypeOffset
+				shift = 2
+			case "DQ":
+				typ = asm.TypeOffset
+				shift = 4
+			case "D":
+				if i := args.Find(opr); i >= 0 {
+					typ = asm.TypeOffset
+					break
+				}
+				if i := args.Find("UI"); i >= 0 {
+					typ = asm.TypeImmUnsigned
+					opr = "UI"
+					break
+				}
+				if i := args.Find("SI"); i >= 0 {
+					typ = asm.TypeImmSigned
+					opr = "SI"
+					break
+				}
+			case "RA", "RB", "RS", "RSp", "RT", "RTp":
+				typ = asm.TypeReg
+			case "BT", "BA", "BB", "BC", "BI":
+				typ = asm.TypeCondRegBit
+			case "BF", "BFA":
+				typ = asm.TypeCondRegField
+			case "FRA", "FRB", "FRBp", "FRC", "FRS", "FRSp", "FRT", "FRTp":
+				typ = asm.TypeFPReg
+			case "XA", "XB", "XC", "XS", "XT": // 5-bit, split field
+				typ = asm.TypeVecReg
+				opr2 = opr[1:]
+				opr = opr[1:] + "X"
+			case "VRA", "VRB", "VRC", "VRS", "VRT":
+				typ = asm.TypeVecReg
+			case "SPR", "DCRN", "BHRBE", "TBR", "SR", "TMR", "PMRN": // Note: if you add to this list and the register field needs special handling, add it to switch statement below
+				typ = asm.TypeSpReg
+				switch opr {
+				case "BHRBE":
+					opr = "bhrbe" // no special handling
+				case "DCRN":
+					opr = "DCR"
+				}
+				if n := strings.ToLower(opr); n != opr && args.Find(n) >= 0 {
+					opr = n // spr[5:9] || spr[0:4]
+				}
+			}
+			if typ == asm.TypeUnknown {
+				log.Fatalf("%s %s unknown type for opr %s", text, inst, opr)
+			}
+			field.Type = typ
+			field.Shift = shift
+			var f1, f2 asm.BitField
+			switch {
+			case opr2 != "":
+				ext := args.Find(opr)
+				if ext < 0 {
+					log.Fatalf("%s: couldn't find extended field %s in %s", text, opr, args)
+				}
+				f1.Offs, f1.Bits = uint8(args[ext].Offs), uint8(args[ext].Bits)
+				base := args.Find(opr2)
+				if base < 0 {
+					log.Fatalf("%s: couldn't find base field %s in %s", text, opr2, args)
+				}
+				f2.Offs, f2.Bits = uint8(args[base].Offs), uint8(args[base].Bits)
+			case opr == "mb", opr == "me": // xx[5] || xx[0:4]
+				i := args.Find(opr)
+				if i < 0 {
+					log.Fatalf("%s: couldn't find special 'm[be]' field for %s in %s", text, opr, args)
+				}
+				f1.Offs, f1.Bits = uint8(args[i].Offs+args[i].Bits)-1, 1
+				f2.Offs, f2.Bits = uint8(args[i].Offs), uint8(args[i].Bits)-1
+			case opr == "spr", opr == "tbr", opr == "tmr", opr == "dcr": // spr[5:9] || spr[0:4]
+				i := args.Find(opr)
+				if i < 0 {
+					log.Fatalf("%s: couldn't find special 'spr' field for %s in %s", text, opr, args)
+				}
+				if args[i].Bits != 10 {
+					log.Fatalf("%s: special 'spr' field is not 10-bit: %s", text, args)
+				}
+				f1.Offs, f1.Bits = uint8(args[i].Offs)+5, 5
+				f2.Offs, f2.Bits = uint8(args[i].Offs), 5
+			default:
+				i := args.Find(opr)
+				if i < 0 {
+					log.Fatalf("%s: couldn't find %s in %s", text, opr, args)
+				}
+				f1.Offs, f1.Bits = uint8(args[i].Offs), uint8(args[i].Bits)
+			}
+			field.BitFields.Append(f1)
+			if f2.Bits > 0 {
+				field.BitFields.Append(f2)
+			}
+			inst.Fields = append(inst.Fields, field)
+		}
+		if *debug {
+			fmt.Printf("%v\n", inst)
+		}
+
+		p.Insts = append(p.Insts, inst)
+	}
+}
+
+// condRegexp is a regular expression that matches condition in mnemonics (e.g. "AA=1")
+const condRegexp = `\s*([[:alpha:]]+)=([0-9a-f]+)\s*`
+
+// condRe matches condition in mnemonics (e.g. "AA=1")
+var condRe = regexp.MustCompile(condRegexp)
+
+// instRe matches instruction with potentially multiple conditions in mnemonics
+var instRe = regexp.MustCompile(`^(.*?)\s?(\((` + condRegexp + `)+\))?$`)
+
+// categoryRe matches intruction category notices in mnemonics
+var categoryRe = regexp.MustCompile(`(\s*\[Category:[^]]*\]\s*)|(\s*\[Co-requisite[^]]*\]\s*)|(\s*\(\s*0[Xx][[0-9A-Fa-f_]{9}\s*\)\s*)`)
+
+// operandRe matches each operand (including opcode) in instruction mnemonics
+var operandRe = regexp.MustCompile(`([[:alpha:]][[:alnum:]_]*\.?)`)
+
+// printText implements the -fmt=text mode, which is not implemented (yet?).
+func printText(p *Prog) {
+	log.Fatal("-fmt=text not implemented")
+}
+
+// opName translate an opcode to a valid Go identifier all-cap op name.
+func opName(op string) string {
+	return strings.ToUpper(strings.Replace(op, ".", "_", 1))
+}
+
+// argFieldName constructs a name for the argField
+func argFieldName(f Field) string {
+	ns := []string{"ap", f.Type.String()}
+	for _, b := range f.BitFields {
+		ns = append(ns, fmt.Sprintf("%d_%d", b.Offs, b.Offs+b.Bits-1))
+	}
+	if f.Shift > 0 {
+		ns = append(ns, fmt.Sprintf("shift%d", f.Shift))
+	}
+	return strings.Join(ns, "_")
+}
+
+var funcBodyTmpl = template.Must(template.New("funcBody").Parse(``))
+
+// printDecoder implements the -fmt=decoder mode.
+// It emits the tables.go for package armasm's decoder.
+func printDecoder(p *Prog) {
+	var buf bytes.Buffer
+
+	fmt.Fprintf(&buf, "package ppc64asm\n\n")
+
+	// Build list of opcodes, using the csv order (which corresponds to ISA docs order)
+	m := map[string]bool{}
+	fmt.Fprintf(&buf, "const (\n\t_ Op = iota\n")
+	for _, inst := range p.Insts {
+		name := opName(inst.Op)
+		if ok := m[name]; ok {
+			continue
+		}
+		m[name] = true
+		fmt.Fprintf(&buf, "\t%s\n", name)
+	}
+	fmt.Fprintln(&buf, ")\n\n")
+
+	// Emit slice mapping opcode number to name string.
+	m = map[string]bool{}
+	fmt.Fprintf(&buf, "var opstr = [...]string{\n")
+	for _, inst := range p.Insts {
+		name := opName(inst.Op)
+		if ok := m[name]; ok {
+			continue
+		}
+		m[name] = true
+		fmt.Fprintf(&buf, "\t%s: %q,\n", opName(inst.Op), inst.Op)
+	}
+	fmt.Fprintln(&buf, "}\n\n")
+
+	// print out argFields
+	fmt.Fprintf(&buf, "var (\n")
+	m = map[string]bool{}
+	for _, inst := range p.Insts {
+		for _, f := range inst.Fields {
+			name := argFieldName(f)
+			if ok := m[name]; ok {
+				continue
+			}
+			m[name] = true
+			fmt.Fprintf(&buf, "\t%s = &argField{Type: %#v, Shift: %d, BitFields: BitFields{", name, f.Type, f.Shift)
+			for _, b := range f.BitFields {
+				fmt.Fprintf(&buf, "{%d, %d},", b.Offs, b.Bits)
+			}
+			fmt.Fprintf(&buf, "}}\n")
+		}
+	}
+	fmt.Fprintln(&buf, ")\n\n")
+
+	// Emit decoding table.
+	fmt.Fprintf(&buf, "var instFormats = [...]instFormat{\n")
+	for _, inst := range p.Insts {
+		fmt.Fprintf(&buf, "\t{ %s, %#x, %#x, %#x,", opName(inst.Op), inst.Mask, inst.Value, inst.DontCare)
+		fmt.Fprintf(&buf, " // %s (%s)\n\t\t[5]*argField{", inst.Text, inst.Encoding)
+		for _, f := range inst.Fields {
+			fmt.Fprintf(&buf, "%s, ", argFieldName(f))
+		}
+		fmt.Fprintf(&buf, "}},\n")
+	}
+	fmt.Fprintln(&buf, "}\n")
+
+	out, err := gofmt.Source(buf.Bytes())
+	if err != nil {
+		log.Fatalf("gofmt error: %v", err)
+		fmt.Printf("%s", buf.Bytes())
+	} else {
+		fmt.Printf("%s", out)
+	}
+}

ppc64/ppc64spec/spec.go

diff --git a/ppc64/ppc64spec/spec.go b/ppc64/ppc64spec/spec.go
new file mode 100644
index 0000000..b965160
--- /dev/null
+++ b/ppc64/ppc64spec/spec.go
@@ -0,0 +1,503 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Power64spec reads the ``Power ISA V2.07'' Manual
+// to collect instruction encoding details and writes those details to standard output
+// in CSV format.
+//
+// Usage:
+//	ppc64spec PowerISA_V2.07_PUBLIC.pdf >ppc64.csv
+//
+// Each CSV line contains four fields:
+//
+//	instruction
+//		The instruction heading, such as "AAD imm8".
+//	mnemonic
+//		The instruction mnemonics, separated by | symbols.
+//	encoding
+//		The instruction encoding, a sequence of name@startbit| describing each bit field in turn.
+//	tags
+//		For now, empty.
+//
+// For more on the exact meaning of these fields, see the Power manual.
+//
+package main
+
+import (
+	"bufio"
+	"fmt"
+	"log"
+	"math"
+	"os"
+	"regexp"
+	"sort"
+	"strconv"
+	"strings"
+
+	"rsc.io/pdf"
+)
+
+type Inst struct {
+	Name string
+	Text string
+	Enc  string
+}
+
+const debugPage = 0
+
+var stdout *bufio.Writer
+
+func main() {
+	log.SetFlags(0)
+	log.SetPrefix("armspec: ")
+
+	if len(os.Args) != 2 {
+		fmt.Fprintf(os.Stderr, "usage: armspec file.pdf\n")
+		os.Exit(2)
+	}
+
+	f, err := pdf.Open(os.Args[1])
+	if err != nil {
+		log.Fatal(err)
+	}
+
+	// Find instruction set reference in outline, to build instruction list.
+	instList := instHeadings(f.Outline())
+	if len(instList) < 200 {
+		log.Fatalf("only found %d instructions in table of contents", len(instList))
+	}
+
+	var all = []Inst{
+		// Split across multiple columns and pages!
+		{"Count Leading Zeros Word X-form", "cntlzw RA, RS (Rc=0)\ncntlzw. RA, RS (Rc=1)", "31@0|RS@6|RA@11|///@16|26@21|Rc@31|"},
+	}
+
+	for j, headline := range instList {
+		for _, inst := range all {
+			if headline == inst.Name {
+				instList[j] = ""
+				break
+			}
+		}
+	}
+
+	// Scan document looking for instructions.
+	// Must find exactly the ones in the outline.
+	n := f.NumPage()
+	for pageNum := 1; pageNum <= n; pageNum++ {
+		if debugPage > 0 && pageNum != debugPage {
+			continue
+		}
+		p := f.Page(pageNum)
+		table := parsePage(pageNum, p)
+		if len(table) == 0 {
+			continue
+		}
+	InstLoop:
+		for _, inst := range table {
+			for j, headline := range instList {
+				if inst.Name == headline {
+					instList[j] = ""
+					continue InstLoop
+				}
+			}
+			fmt.Fprintf(os.Stderr, "page %d: unexpected instruction %q\n", pageNum, inst.Name)
+		}
+		all = append(all, table...)
+	}
+
+	if debugPage == 0 {
+		for _, headline := range instList {
+			if headline != "" {
+				switch headline {
+				default:
+					fmt.Fprintf(os.Stderr, "missing instruction %q\n", headline)
+				case "CHKA": // ThumbEE
+				case "CPS": // system instruction
+				case "CPY": // synonym for MOV
+				case "ENTERX": // ThumbEE
+				case "F* (former VFP instruction mnemonics)": // synonyms
+				case "HB, HBL, HBLP, HBP": // ThumbEE
+				case "LEAVEX": // ThumbEE
+				case "MOV (shifted register)": // pseudo instruction for ASR, LSL, LSR, ROR, and RRX
+				case "NEG": // synonym for RSB
+				case "RFE": // system instruction
+				case "SMC (previously SMI)": // system instruction
+				case "SRS": // system instruction
+				case "SUBS PC, LR and related instructions": // system instruction
+				case "VAND (immediate)": // pseudo instruction
+				case "VCLE (register)": // pseudo instruction
+				case "VCLT (register)": // pseudo instruction
+				case "VORN (immediate)": // pseudo instruction
+				}
+			}
+		}
+	}
+
+	stdout = bufio.NewWriter(os.Stdout)
+	for _, inst := range all {
+		fmt.Fprintf(stdout, "%q,%q,%q,%q\n", inst.Name, strings.Replace(inst.Text, "\n", "|", -1), inst.Enc, "")
+	}
+	stdout.Flush()
+
+}
+
+func instHeadings(outline pdf.Outline) []string {
+	return appendInstHeadings(outline, nil)
+}
+
+var instRE = regexp.MustCompile(` ([A-Z0-9]+-form|Byte|Word|Doubleword|Halfword)($| \[)`)
+var sectionRE = regexp.MustCompile(`^[0-9A-Z]+\.[0-9]`)
+
+func appendInstHeadings(outline pdf.Outline, list []string) []string {
+	if strings.Contains(outline.Title, "Variable Length Encoding (VLE) Encoding") {
+		for _, child := range outline.Child {
+			vle = appendInstHeadings(child, vle)
+		}
+		return list
+	}
+	if instRE.MatchString(outline.Title) && !sectionRE.MatchString(outline.Title) {
+		list = append(list, outline.Title)
+	}
+	if outline.Title == "Transaction Abort Word Conditional" {
+		list = append(list, outline.Title+" X-form")
+	}
+	for _, child := range outline.Child {
+		list = appendInstHeadings(child, list)
+	}
+	return list
+}
+
+const inch = 72.0
+
+func parsePage(num int, p pdf.Page) []Inst {
+	content := p.Content()
+
+	var text []pdf.Text
+	for _, t := range content.Text {
+		text = append(text, t)
+	}
+
+	text = findWords(text)
+
+	if debugPage > 0 {
+		for _, t := range text {
+			fmt.Println(t)
+		}
+		for _, r := range content.Rect {
+			fmt.Println(r)
+		}
+	}
+
+	// Look for instruction encodings.
+	// Some begin with a Helvetica-BoldOblique size 11 headline like "AND   X-Form",
+	// is followed by Helvetica 9 mnemonic, and then a bit box with
+	// Helvetica 9 fields and Helvetica 7 bit offsets.
+	// Others use Arial,BoldItalic 11 for the headline,
+	// Arial 8 for the mnemonic, and Arial 4.2 for the bit offsets.
+
+	var insts []Inst
+	for {
+		// Heading
+		for len(text) > 0 && !match(text[0], "Helvetica-BoldOblique", 11, "") && !match(text[0], "Arial,BoldItalic", 11, "") && !match(text[0], "Arial,BoldItalic", 10, "") {
+			text = text[1:]
+		}
+		if len(text) == 0 {
+			break
+		}
+		heading := text[0].S
+		text = text[1:]
+		for len(text) > 0 && (match(text[0], "Helvetica-BoldOblique", 11, "") || match(text[0], "Arial,BoldItalic", 11, "") || match(text[0], "Arial,BoldItalic", 10, "")) {
+			heading += " " + text[0].S
+			text = text[1:]
+		}
+		heading = strings.Replace(heading, "]", "] ", -1)
+		heading = strings.Replace(heading, "  ", " ", -1)
+		heading = strings.Replace(heading, "rEVX-form", "r EVX-form", -1)
+		heading = strings.Replace(heading, "eX-form", "e X-form", -1)
+		heading = strings.Replace(heading, "mSD4-form", "m SD4-form", -1)
+		heading = strings.Replace(heading, "eSCI8-form", "e SCI8-form", -1)
+		heading = strings.TrimSpace(heading)
+		if isVLE(heading) {
+			continue
+		}
+
+		// Mnemonic
+		if len(text) == 0 || (!match(text[0], "Helvetica", 9, "") && !match(text[0], "Helvetica-BoldOblique", 9, "") && !match(text[0], "Arial", 9, "") && !match(text[0], "Arial", 10, "")) {
+			continue
+		}
+		mnemonic := ""
+		y := text[0].Y
+		x0 := text[0].X
+		for len(text) > 0 && (match(text[0], "Helvetica", 9, "") || match(text[0], "Helvetica-BoldOblique", 9, "") || match(text[0], "Arial", 9, "") || match(text[0], "Courier", 8, "") || match(text[0], "LucidaConsole", 7.17, "") || text[0].Y == y) {
+			if text[0].Y != y {
+				if math.Abs(text[0].X-x0) > 4 {
+					break
+				}
+				mnemonic += "\n"
+				y = text[0].Y
+			} else if mnemonic != "" {
+				mnemonic += " "
+			}
+			mnemonic += text[0].S
+			text = text[1:]
+		}
+
+		// Encoding
+		bits, i := readBitBox(heading, content, text, num)
+		if i == 0 {
+			continue
+		}
+
+		insts = append(insts, Inst{heading, mnemonic, bits})
+	}
+	return insts
+}
+
+var vle = []string{
+	"System Call C-form,ESC-form",
+}
+
+func isVLE(s string) bool {
+	for _, v := range vle {
+		if s == v {
+			return true
+		}
+	}
+	return false
+}
+
+func readBitBox(headline string, content pdf.Content, text []pdf.Text, pageNum int) (string, int) {
+	// fields
+	i := 0
+	if len(text) == 0 || (!match(text[i], "Helvetica", 9, "") && !match(text[i], "Helvetica", 7.26, "") && !match(text[i], "Arial", 9, "") && !match(text[i], "Arial", 7.98, "") && !match(text[i], "Arial", 7.2, "")) {
+		fmt.Fprintf(os.Stderr, "page %d: no bit fields for %q\n", pageNum, headline)
+		if len(text) > 0 {
+			fmt.Fprintf(os.Stderr, "\tlast text: %v\n", text[0])
+		}
+		return "", 0
+	}
+	sz := text[i].FontSize
+	y2 := text[i].Y
+	x2 := 0.0
+	for i < len(text) && text[i].Y == y2 {
+		if x2 < text[i].X+text[i].W {
+			x2 = text[i].X + text[i].W
+		}
+		i++
+	}
+	y2 += sz / 2
+
+	// bit numbers
+	if i >= len(text) || text[i].S != "0" {
+		if headline == "Transaction Abort Doubleword Conditional X-form" {
+			// Split across the next page.
+			return "31@0|TO@6|RA@11|RB@16|814@21|1@31|", i
+		}
+		if headline == "Add Scaled Immediate SCI8-form" {
+			// Very strange fonts.
+			return "06@0|RT@6|RA@11|8@16|Rc@20|F@21|SCL@22|UI8@24|", i
+		}
+		fmt.Fprintf(os.Stderr, "page %d: no bit numbers for %s\n", pageNum, headline)
+		if i < len(text) {
+			fmt.Fprintf(os.Stderr, "\tlast text: %v\n", text[i])
+		}
+		return "", 0
+	}
+	sz = text[i].FontSize
+	y1 := text[i].Y
+	x1 := text[i].X
+	for i < len(text) && text[i].Y == y1 {
+		if x2 < text[i].X+text[i].W {
+			x2 = text[i].X + text[i].W
+		}
+		i++
+	}
+
+	if debugPage > 0 {
+		fmt.Println("encoding box", x1, y1, x2, y2, i, text[0], text[i])
+	}
+
+	// Find lines (thin rectangles) separating bit fields.
+	var bottom, top pdf.Rect
+	const (
+		yMargin = 0.25 * 72
+		xMargin = 1 * 72
+	)
+	for _, r := range content.Rect {
+		// Only consider lines in the same column.
+		if (x1 < 306) != (r.Max.X < 306) {
+			continue
+		}
+		if r.Max.Y-r.Min.Y < 2 && x1-xMargin < r.Min.X && r.Min.X < x1 && x2 < r.Max.X && r.Max.X < x2+xMargin {
+			if y1-yMargin < r.Min.Y && r.Min.Y < y1 {
+				bottom = r
+			}
+			if y2 < r.Min.Y && r.Min.Y < y2+8 {
+				top = r
+			}
+		}
+	}
+
+	if bottom.Min.X == 0 {
+		// maybe bit numbers are outside box; see doze, nap, sleep, rvwinkle.
+		for _, r := range content.Rect {
+			// Only consider lines in the same column.
+			if (x1 < 306) != (r.Max.X < 306) {
+				continue
+			}
+			if r.Max.Y-r.Min.Y < 2 && x1-xMargin < r.Min.X && r.Min.X < x1 && x2 < r.Max.X && r.Max.X < x2+xMargin {
+				if y1+sz/2 < r.Min.Y && r.Min.Y < y2 {
+					bottom = r
+				}
+			}
+		}
+	}
+
+	if debugPage > 0 {
+		fmt.Println("top", top, "bottom", bottom)
+	}
+
+	const ε = 0.1 * 72
+	var bars []pdf.Rect
+	for _, r := range content.Rect {
+		if r.Max.X-r.Min.X < 2 && math.Abs(r.Min.Y-bottom.Min.Y) < ε && math.Abs(r.Max.Y-top.Min.Y) < ε && (bottom.Min.X < 306) == (r.Max.X < 306) {
+			bars = append(bars, r)
+		}
+	}
+	sort.Sort(RectHorizontal(bars))
+
+	out := ""
+	for i := 0; i < len(bars)-1; i++ {
+		var sub []pdf.Text
+		x1, x2 := bars[i].Min.X, bars[i+1].Min.X
+		for _, t := range content.Text {
+			tx := t.X + t.W/2
+			ty := t.Y + t.FontSize/4
+			if x1 < tx && tx < x2 && y1 < ty && ty < y2 {
+				sub = append(sub, t)
+			}
+		}
+		var str []string
+		for _, t := range findWords(sub) {
+			str = append(str, t.S)
+		}
+		s := strings.Join(str, "@")
+		out += s + "|"
+	}
+
+	if out == "" {
+		fmt.Fprintf(os.Stderr, "page %d: no bit encodings for %s\n", pageNum, headline)
+	}
+	return out, i
+}
+
+type RectHorizontal []pdf.Rect
+
+func (x RectHorizontal) Swap(i, j int)      { x[i], x[j] = x[j], x[i] }
+func (x RectHorizontal) Less(i, j int) bool { return x[i].Min.X < x[j].Min.X }
+func (x RectHorizontal) Len() int           { return len(x) }
+
+func checkNoEncodings(num int, text []pdf.Text) {
+	for _, t := range text {
+		if match(t, "Helvetica-Bold", 9, "Encoding") {
+			fmt.Fprintf(os.Stderr, "page %d: unexpected encoding: %s\n", num, t.S)
+		}
+	}
+}
+
+func match(t pdf.Text, font string, size float64, substr string) bool {
+	return t.Font == font && (size == 0 || math.Abs(t.FontSize-size) < 0.1) && strings.Contains(t.S, substr)
+}
+
+func findWords(chars []pdf.Text) (words []pdf.Text) {
+	// Sort by Y coordinate and normalize.
+	const nudge = 1.5
+	sort.Sort(pdf.TextVertical(chars))
+	old := -100000.0
+	for i, c := range chars {
+		if c.Y != old && math.Abs(old-c.Y) < nudge {
+			chars[i].Y = old
+		} else {
+			old = c.Y
+		}
+	}
+
+	// Sort by Y coordinate, breaking ties with X.
+	// This will bring letters in a single word together.
+	sort.Sort(pdf.TextVertical(chars))
+
+	// Loop over chars.
+	for i := 0; i < len(chars); {
+		// Find all chars on line.
+		j := i + 1
+		for j < len(chars) && chars[j].Y == chars[i].Y {
+			j++
+		}
+		var end float64
+		// Split line into words (really, phrases).
+		for k := i; k < j; {
+			ck := &chars[k]
+			s := ck.S
+			end = ck.X + ck.W
+			charSpace := ck.FontSize / 6
+			wordSpace := ck.FontSize * 2 / 3
+			l := k + 1
+			for l < j {
+				// Grow word.
+				cl := &chars[l]
+				if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+charSpace {
+					s += cl.S
+					end = cl.X + cl.W
+					l++
+					continue
+				}
+				// Add space to phrase before next word.
+				if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+wordSpace {
+					s += " " + cl.S
+					end = cl.X + cl.W
+					l++
+					continue
+				}
+				break
+			}
+			f := ck.Font
+			f = strings.TrimSuffix(f, ",Italic")
+			f = strings.TrimSuffix(f, "-Italic")
+			words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end - ck.X, s})
+			k = l
+		}
+		i = j
+	}
+
+	// Split into two columns.
+	var col1, col2 []pdf.Text
+	for _, w := range words {
+		if w.X > 306 {
+			col2 = append(col2, w)
+		} else {
+			col1 = append(col1, w)
+		}
+	}
+	return append(col1, col2...)
+}
+
+func sameFont(f1, f2 string) bool {
+	f1 = strings.TrimSuffix(f1, ",Italic")
+	f1 = strings.TrimSuffix(f1, "-Italic")
+	f2 = strings.TrimSuffix(f1, ",Italic")
+	f2 = strings.TrimSuffix(f1, "-Italic")
+	return strings.TrimSuffix(f1, ",Italic") == strings.TrimSuffix(f2, ",Italic") || f1 == "Symbol" || f2 == "Symbol" || f1 == "TimesNewRoman" || f2 == "TimesNewRoman"
+}
+
+var jsFix = strings.NewReplacer(
+//	`\u003c`, `<`,
+//	`\u003e`, `>`,
+//	`\u0026`, `&`,
+//	`\u0009`, `\t`,
+)
+
+func printTable(name string, table []Inst) {
+	_ = strconv.Atoi
+}