commit 1b0b01032b87c8a67535b946ea8290b6f902c1de
author Than McIntosh <thanm@google.com> Fri Feb 28 11:28:08 2020 -0500
committer Than McIntosh <thanm@google.com> Fri Feb 28 19:07:46 2020 +0000
tree 1521f0c301cdc3d457162ce35ed8686551a23140
parent 761ca297b3d63e514b6ef0211c040b408c2857a4

gollvm: sync with LLVM trunk

This patch brings the gollvm source into sync with LLVM trunk
circa revision ddd11273d9d0807e25a34181e5978e3307d78dc2.

Fixes golang/go#37509.

Change-Id: I5005c7b5dd330de1f33e29f0452303e3c6876013
Reviewed-on: https://go-review.googlesource.com/c/gollvm/+/221537
Reviewed-by: Cherry Zhang <cherryyz@google.com>

bridge/go-llvm-irbuilders.h

diff --git a/bridge/go-llvm-irbuilders.h b/bridge/go-llvm-irbuilders.h
index a557fce..39363ab 100644
--- a/bridge/go-llvm-irbuilders.h
+++ b/bridge/go-llvm-irbuilders.h
@@ -25,7 +25,7 @@
 // Insertion helper for Bexpressions; inserts any instructions
 // created by IRBuilder into the specified Bexpression's inst list.
 
-class BexprInserter {
+class BexprInserter : public llvm::IRBuilderDefaultInserter {
  public:
   BexprInserter() : expr_(nullptr) { }
   void setDest(Bexpression *expr) { assert(!expr_); expr_ = expr; }
@@ -46,17 +46,17 @@
 
 class BexprLIRBuilder :
     public llvm::IRBuilder<llvm::ConstantFolder, BexprInserter> {
-  typedef llvm::IRBuilder<llvm::ConstantFolder, BexprInserter> IRBuilderBase;
+  typedef llvm::IRBuilder<llvm::ConstantFolder, BexprInserter> IRBuilderB;
  public:
   BexprLIRBuilder(llvm::LLVMContext &context, Bexpression *expr) :
-      IRBuilderBase(context, llvm::ConstantFolder()) {
-    setDest(expr);
+      IRBuilderB(context, llvm::ConstantFolder(), getInserter(), nullptr, llvm::None) {
+    getInserter().setDest(expr);
   }
 };
 
 // Similar to the above, but adds to a Binstructions object.
 
-class BinstructionsInserter {
+class BinstructionsInserter : public llvm::IRBuilderDefaultInserter {
  public:
   BinstructionsInserter() : insns_(nullptr) { }
   void setDest(Binstructions *insns) { assert(!insns_); insns_ = insns; }
@@ -78,11 +78,11 @@
 class BinstructionsLIRBuilder :
     public llvm::IRBuilder<llvm::ConstantFolder, BinstructionsInserter> {
   typedef llvm::IRBuilder<llvm::ConstantFolder,
-                          BinstructionsInserter> IRBuilderBase;
+                          BinstructionsInserter> IRBuilderB;
  public:
   BinstructionsLIRBuilder(llvm::LLVMContext &context, Binstructions *insns) :
-      IRBuilderBase(context, llvm::ConstantFolder()) {
-    setDest(insns);
+      IRBuilderB(context, llvm::ConstantFolder(), getInserter(), nullptr, llvm::None) {
+    getInserter().setDest(insns);
   }
 };
 

passes/GC.cpp

diff --git a/passes/GC.cpp b/passes/GC.cpp
index adc7cbb..9bdd602 100644
--- a/passes/GC.cpp
+++ b/passes/GC.cpp
@@ -159,7 +159,7 @@
       if (Sym->isDefined())
         // We may have emitted one, due to tail duplication.
         continue;
-      OS.EmitLabel(Sym);
+      OS.emitLabel(Sym);
 
       // Stack map entry:
       //   uint32_t nbits;
@@ -167,11 +167,11 @@
       uint32_t Size;
       std::vector<uint8_t> V =
           computeBitVector(FR.second.StackSize, (*CSI).Locations, Size);
-      OS.EmitIntValue(Size, 4);
+      OS.emitIntValue(Size, 4);
       for (uint8_t Byte : V)
-        OS.EmitIntValue(Byte, 1);
+        OS.emitIntValue(Byte, 1);
     }
-    OS.EmitValueToAlignment(8);
+    OS.emitValueToAlignment(8);
   }
 }
 

passes/GoNilChecks.cpp

diff --git a/passes/GoNilChecks.cpp b/passes/GoNilChecks.cpp
index 19e08b8..9cacec4 100644
--- a/passes/GoNilChecks.cpp
+++ b/passes/GoNilChecks.cpp
@@ -375,11 +375,16 @@
                                 ArrayRef<MachineInstr *> PrevInsts) {
   int64_t Offset;
   const MachineOperand *BaseOp;
+  bool OffsetIsScalable;
 
-  if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) ||
+  if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI) ||
       !BaseOp->isReg() || BaseOp->getReg() != PointerReg)
     return SR_Unsuitable;
 
+  // FIXME: This algorithm assumes instructions have fixed-size offsets.
+  if (OffsetIsScalable)
+    return SR_Unsuitable;
+
   // We want the mem access to be issued at a sane offset from PointerReg,
   // so that if PointerReg is null then the access reliably page faults.
   if (!((MI.mayLoad() || MI.mayStore()) && !MI.isPredicable() &&