blob: be8cdd60aca1392be731657c9eaf516e93acf6b1 [file] [log] [blame]
// autogenerated: do not edit!
// generated from gen/*Ops.go
package ssa
import (
"cmd/internal/obj"
"cmd/internal/obj/arm"
"cmd/internal/obj/arm64"
"cmd/internal/obj/ppc64"
"cmd/internal/obj/x86"
)
const (
BlockInvalid BlockKind = iota
Block386EQ
Block386NE
Block386LT
Block386LE
Block386GT
Block386GE
Block386ULT
Block386ULE
Block386UGT
Block386UGE
Block386EQF
Block386NEF
Block386ORD
Block386NAN
BlockAMD64EQ
BlockAMD64NE
BlockAMD64LT
BlockAMD64LE
BlockAMD64GT
BlockAMD64GE
BlockAMD64ULT
BlockAMD64ULE
BlockAMD64UGT
BlockAMD64UGE
BlockAMD64EQF
BlockAMD64NEF
BlockAMD64ORD
BlockAMD64NAN
BlockARMEQ
BlockARMNE
BlockARMLT
BlockARMLE
BlockARMGT
BlockARMGE
BlockARMULT
BlockARMULE
BlockARMUGT
BlockARMUGE
BlockARM64EQ
BlockARM64NE
BlockARM64LT
BlockARM64LE
BlockARM64GT
BlockARM64GE
BlockARM64ULT
BlockARM64ULE
BlockARM64UGT
BlockARM64UGE
BlockPPC64EQ
BlockPPC64NE
BlockPPC64LT
BlockPPC64LE
BlockPPC64GT
BlockPPC64GE
BlockPPC64FLT
BlockPPC64FLE
BlockPPC64FGT
BlockPPC64FGE
BlockPlain
BlockIf
BlockCall
BlockDefer
BlockCheck
BlockRet
BlockRetJmp
BlockExit
BlockFirst
)
var blockString = [...]string{
BlockInvalid: "BlockInvalid",
Block386EQ: "EQ",
Block386NE: "NE",
Block386LT: "LT",
Block386LE: "LE",
Block386GT: "GT",
Block386GE: "GE",
Block386ULT: "ULT",
Block386ULE: "ULE",
Block386UGT: "UGT",
Block386UGE: "UGE",
Block386EQF: "EQF",
Block386NEF: "NEF",
Block386ORD: "ORD",
Block386NAN: "NAN",
BlockAMD64EQ: "EQ",
BlockAMD64NE: "NE",
BlockAMD64LT: "LT",
BlockAMD64LE: "LE",
BlockAMD64GT: "GT",
BlockAMD64GE: "GE",
BlockAMD64ULT: "ULT",
BlockAMD64ULE: "ULE",
BlockAMD64UGT: "UGT",
BlockAMD64UGE: "UGE",
BlockAMD64EQF: "EQF",
BlockAMD64NEF: "NEF",
BlockAMD64ORD: "ORD",
BlockAMD64NAN: "NAN",
BlockARMEQ: "EQ",
BlockARMNE: "NE",
BlockARMLT: "LT",
BlockARMLE: "LE",
BlockARMGT: "GT",
BlockARMGE: "GE",
BlockARMULT: "ULT",
BlockARMULE: "ULE",
BlockARMUGT: "UGT",
BlockARMUGE: "UGE",
BlockARM64EQ: "EQ",
BlockARM64NE: "NE",
BlockARM64LT: "LT",
BlockARM64LE: "LE",
BlockARM64GT: "GT",
BlockARM64GE: "GE",
BlockARM64ULT: "ULT",
BlockARM64ULE: "ULE",
BlockARM64UGT: "UGT",
BlockARM64UGE: "UGE",
BlockPPC64EQ: "EQ",
BlockPPC64NE: "NE",
BlockPPC64LT: "LT",
BlockPPC64LE: "LE",
BlockPPC64GT: "GT",
BlockPPC64GE: "GE",
BlockPPC64FLT: "FLT",
BlockPPC64FLE: "FLE",
BlockPPC64FGT: "FGT",
BlockPPC64FGE: "FGE",
BlockPlain: "Plain",
BlockIf: "If",
BlockCall: "Call",
BlockDefer: "Defer",
BlockCheck: "Check",
BlockRet: "Ret",
BlockRetJmp: "RetJmp",
BlockExit: "Exit",
BlockFirst: "First",
}
func (k BlockKind) String() string { return blockString[k] }
const (
OpInvalid Op = iota
Op386ADDSS
Op386ADDSD
Op386SUBSS
Op386SUBSD
Op386MULSS
Op386MULSD
Op386DIVSS
Op386DIVSD
Op386MOVSSload
Op386MOVSDload
Op386MOVSSconst
Op386MOVSDconst
Op386MOVSSloadidx1
Op386MOVSSloadidx4
Op386MOVSDloadidx1
Op386MOVSDloadidx8
Op386MOVSSstore
Op386MOVSDstore
Op386MOVSSstoreidx1
Op386MOVSSstoreidx4
Op386MOVSDstoreidx1
Op386MOVSDstoreidx8
Op386ADDL
Op386ADDLconst
Op386ADDLcarry
Op386ADDLconstcarry
Op386ADCL
Op386ADCLconst
Op386SUBL
Op386SUBLconst
Op386SUBLcarry
Op386SUBLconstcarry
Op386SBBL
Op386SBBLconst
Op386MULL
Op386MULLconst
Op386HMULL
Op386HMULLU
Op386HMULW
Op386HMULB
Op386HMULWU
Op386HMULBU
Op386MULLQU
Op386DIVL
Op386DIVW
Op386DIVLU
Op386DIVWU
Op386MODL
Op386MODW
Op386MODLU
Op386MODWU
Op386ANDL
Op386ANDLconst
Op386ORL
Op386ORLconst
Op386XORL
Op386XORLconst
Op386CMPL
Op386CMPW
Op386CMPB
Op386CMPLconst
Op386CMPWconst
Op386CMPBconst
Op386UCOMISS
Op386UCOMISD
Op386TESTL
Op386TESTW
Op386TESTB
Op386TESTLconst
Op386TESTWconst
Op386TESTBconst
Op386SHLL
Op386SHLLconst
Op386SHRL
Op386SHRW
Op386SHRB
Op386SHRLconst
Op386SHRWconst
Op386SHRBconst
Op386SARL
Op386SARW
Op386SARB
Op386SARLconst
Op386SARWconst
Op386SARBconst
Op386ROLLconst
Op386ROLWconst
Op386ROLBconst
Op386NEGL
Op386NOTL
Op386BSFL
Op386BSFW
Op386BSRL
Op386BSRW
Op386BSWAPL
Op386SQRTSD
Op386SBBLcarrymask
Op386SETEQ
Op386SETNE
Op386SETL
Op386SETLE
Op386SETG
Op386SETGE
Op386SETB
Op386SETBE
Op386SETA
Op386SETAE
Op386SETEQF
Op386SETNEF
Op386SETORD
Op386SETNAN
Op386SETGF
Op386SETGEF
Op386MOVBLSX
Op386MOVBLZX
Op386MOVWLSX
Op386MOVWLZX
Op386MOVLconst
Op386CVTTSD2SL
Op386CVTTSS2SL
Op386CVTSL2SS
Op386CVTSL2SD
Op386CVTSD2SS
Op386CVTSS2SD
Op386PXOR
Op386LEAL
Op386LEAL1
Op386LEAL2
Op386LEAL4
Op386LEAL8
Op386MOVBload
Op386MOVBLSXload
Op386MOVWload
Op386MOVWLSXload
Op386MOVLload
Op386MOVBstore
Op386MOVWstore
Op386MOVLstore
Op386MOVBloadidx1
Op386MOVWloadidx1
Op386MOVWloadidx2
Op386MOVLloadidx1
Op386MOVLloadidx4
Op386MOVBstoreidx1
Op386MOVWstoreidx1
Op386MOVWstoreidx2
Op386MOVLstoreidx1
Op386MOVLstoreidx4
Op386MOVBstoreconst
Op386MOVWstoreconst
Op386MOVLstoreconst
Op386MOVBstoreconstidx1
Op386MOVWstoreconstidx1
Op386MOVWstoreconstidx2
Op386MOVLstoreconstidx1
Op386MOVLstoreconstidx4
Op386DUFFZERO
Op386REPSTOSL
Op386CALLstatic
Op386CALLclosure
Op386CALLdefer
Op386CALLgo
Op386CALLinter
Op386DUFFCOPY
Op386REPMOVSL
Op386InvertFlags
Op386LoweredGetG
Op386LoweredGetClosurePtr
Op386LoweredNilCheck
Op386MOVLconvert
Op386FlagEQ
Op386FlagLT_ULT
Op386FlagLT_UGT
Op386FlagGT_UGT
Op386FlagGT_ULT
Op386FCHS
Op386MOVSSconst1
Op386MOVSDconst1
Op386MOVSSconst2
Op386MOVSDconst2
OpAMD64ADDSS
OpAMD64ADDSD
OpAMD64SUBSS
OpAMD64SUBSD
OpAMD64MULSS
OpAMD64MULSD
OpAMD64DIVSS
OpAMD64DIVSD
OpAMD64MOVSSload
OpAMD64MOVSDload
OpAMD64MOVSSconst
OpAMD64MOVSDconst
OpAMD64MOVSSloadidx1
OpAMD64MOVSSloadidx4
OpAMD64MOVSDloadidx1
OpAMD64MOVSDloadidx8
OpAMD64MOVSSstore
OpAMD64MOVSDstore
OpAMD64MOVSSstoreidx1
OpAMD64MOVSSstoreidx4
OpAMD64MOVSDstoreidx1
OpAMD64MOVSDstoreidx8
OpAMD64ADDQ
OpAMD64ADDL
OpAMD64ADDQconst
OpAMD64ADDLconst
OpAMD64SUBQ
OpAMD64SUBL
OpAMD64SUBQconst
OpAMD64SUBLconst
OpAMD64MULQ
OpAMD64MULL
OpAMD64MULQconst
OpAMD64MULLconst
OpAMD64HMULQ
OpAMD64HMULL
OpAMD64HMULW
OpAMD64HMULB
OpAMD64HMULQU
OpAMD64HMULLU
OpAMD64HMULWU
OpAMD64HMULBU
OpAMD64AVGQU
OpAMD64DIVQ
OpAMD64DIVL
OpAMD64DIVW
OpAMD64DIVQU
OpAMD64DIVLU
OpAMD64DIVWU
OpAMD64ANDQ
OpAMD64ANDL
OpAMD64ANDQconst
OpAMD64ANDLconst
OpAMD64ORQ
OpAMD64ORL
OpAMD64ORQconst
OpAMD64ORLconst
OpAMD64XORQ
OpAMD64XORL
OpAMD64XORQconst
OpAMD64XORLconst
OpAMD64CMPQ
OpAMD64CMPL
OpAMD64CMPW
OpAMD64CMPB
OpAMD64CMPQconst
OpAMD64CMPLconst
OpAMD64CMPWconst
OpAMD64CMPBconst
OpAMD64UCOMISS
OpAMD64UCOMISD
OpAMD64TESTQ
OpAMD64TESTL
OpAMD64TESTW
OpAMD64TESTB
OpAMD64TESTQconst
OpAMD64TESTLconst
OpAMD64TESTWconst
OpAMD64TESTBconst
OpAMD64SHLQ
OpAMD64SHLL
OpAMD64SHLQconst
OpAMD64SHLLconst
OpAMD64SHRQ
OpAMD64SHRL
OpAMD64SHRW
OpAMD64SHRB
OpAMD64SHRQconst
OpAMD64SHRLconst
OpAMD64SHRWconst
OpAMD64SHRBconst
OpAMD64SARQ
OpAMD64SARL
OpAMD64SARW
OpAMD64SARB
OpAMD64SARQconst
OpAMD64SARLconst
OpAMD64SARWconst
OpAMD64SARBconst
OpAMD64ROLQconst
OpAMD64ROLLconst
OpAMD64ROLWconst
OpAMD64ROLBconst
OpAMD64NEGQ
OpAMD64NEGL
OpAMD64NOTQ
OpAMD64NOTL
OpAMD64BSFQ
OpAMD64BSFL
OpAMD64BSFW
OpAMD64BSRQ
OpAMD64BSRL
OpAMD64BSRW
OpAMD64CMOVQEQconst
OpAMD64CMOVLEQconst
OpAMD64CMOVWEQconst
OpAMD64CMOVQNEconst
OpAMD64CMOVLNEconst
OpAMD64CMOVWNEconst
OpAMD64BSWAPQ
OpAMD64BSWAPL
OpAMD64SQRTSD
OpAMD64SBBQcarrymask
OpAMD64SBBLcarrymask
OpAMD64SETEQ
OpAMD64SETNE
OpAMD64SETL
OpAMD64SETLE
OpAMD64SETG
OpAMD64SETGE
OpAMD64SETB
OpAMD64SETBE
OpAMD64SETA
OpAMD64SETAE
OpAMD64SETEQF
OpAMD64SETNEF
OpAMD64SETORD
OpAMD64SETNAN
OpAMD64SETGF
OpAMD64SETGEF
OpAMD64MOVBQSX
OpAMD64MOVBQZX
OpAMD64MOVWQSX
OpAMD64MOVWQZX
OpAMD64MOVLQSX
OpAMD64MOVLQZX
OpAMD64MOVLconst
OpAMD64MOVQconst
OpAMD64CVTTSD2SL
OpAMD64CVTTSD2SQ
OpAMD64CVTTSS2SL
OpAMD64CVTTSS2SQ
OpAMD64CVTSL2SS
OpAMD64CVTSL2SD
OpAMD64CVTSQ2SS
OpAMD64CVTSQ2SD
OpAMD64CVTSD2SS
OpAMD64CVTSS2SD
OpAMD64PXOR
OpAMD64LEAQ
OpAMD64LEAQ1
OpAMD64LEAQ2
OpAMD64LEAQ4
OpAMD64LEAQ8
OpAMD64LEAL
OpAMD64MOVBload
OpAMD64MOVBQSXload
OpAMD64MOVWload
OpAMD64MOVWQSXload
OpAMD64MOVLload
OpAMD64MOVLQSXload
OpAMD64MOVQload
OpAMD64MOVBstore
OpAMD64MOVWstore
OpAMD64MOVLstore
OpAMD64MOVQstore
OpAMD64MOVOload
OpAMD64MOVOstore
OpAMD64MOVBloadidx1
OpAMD64MOVWloadidx1
OpAMD64MOVWloadidx2
OpAMD64MOVLloadidx1
OpAMD64MOVLloadidx4
OpAMD64MOVQloadidx1
OpAMD64MOVQloadidx8
OpAMD64MOVBstoreidx1
OpAMD64MOVWstoreidx1
OpAMD64MOVWstoreidx2
OpAMD64MOVLstoreidx1
OpAMD64MOVLstoreidx4
OpAMD64MOVQstoreidx1
OpAMD64MOVQstoreidx8
OpAMD64MOVBstoreconst
OpAMD64MOVWstoreconst
OpAMD64MOVLstoreconst
OpAMD64MOVQstoreconst
OpAMD64MOVBstoreconstidx1
OpAMD64MOVWstoreconstidx1
OpAMD64MOVWstoreconstidx2
OpAMD64MOVLstoreconstidx1
OpAMD64MOVLstoreconstidx4
OpAMD64MOVQstoreconstidx1
OpAMD64MOVQstoreconstidx8
OpAMD64DUFFZERO
OpAMD64MOVOconst
OpAMD64REPSTOSQ
OpAMD64CALLstatic
OpAMD64CALLclosure
OpAMD64CALLdefer
OpAMD64CALLgo
OpAMD64CALLinter
OpAMD64DUFFCOPY
OpAMD64REPMOVSQ
OpAMD64InvertFlags
OpAMD64LoweredGetG
OpAMD64LoweredGetClosurePtr
OpAMD64LoweredNilCheck
OpAMD64MOVQconvert
OpAMD64MOVLconvert
OpAMD64FlagEQ
OpAMD64FlagLT_ULT
OpAMD64FlagLT_UGT
OpAMD64FlagGT_UGT
OpAMD64FlagGT_ULT
OpARMADD
OpARMADDconst
OpARMSUB
OpARMSUBconst
OpARMRSB
OpARMRSBconst
OpARMMUL
OpARMHMUL
OpARMHMULU
OpARMDIV
OpARMDIVU
OpARMMOD
OpARMMODU
OpARMADDS
OpARMADDSconst
OpARMADC
OpARMADCconst
OpARMSUBS
OpARMSUBSconst
OpARMRSBSconst
OpARMSBC
OpARMSBCconst
OpARMRSCconst
OpARMMULLU
OpARMMULA
OpARMADDF
OpARMADDD
OpARMSUBF
OpARMSUBD
OpARMMULF
OpARMMULD
OpARMDIVF
OpARMDIVD
OpARMAND
OpARMANDconst
OpARMOR
OpARMORconst
OpARMXOR
OpARMXORconst
OpARMBIC
OpARMBICconst
OpARMMVN
OpARMNEGF
OpARMNEGD
OpARMSQRTD
OpARMSLL
OpARMSLLconst
OpARMSRL
OpARMSRLconst
OpARMSRA
OpARMSRAconst
OpARMSRRconst
OpARMADDshiftLL
OpARMADDshiftRL
OpARMADDshiftRA
OpARMSUBshiftLL
OpARMSUBshiftRL
OpARMSUBshiftRA
OpARMRSBshiftLL
OpARMRSBshiftRL
OpARMRSBshiftRA
OpARMANDshiftLL
OpARMANDshiftRL
OpARMANDshiftRA
OpARMORshiftLL
OpARMORshiftRL
OpARMORshiftRA
OpARMXORshiftLL
OpARMXORshiftRL
OpARMXORshiftRA
OpARMBICshiftLL
OpARMBICshiftRL
OpARMBICshiftRA
OpARMMVNshiftLL
OpARMMVNshiftRL
OpARMMVNshiftRA
OpARMADCshiftLL
OpARMADCshiftRL
OpARMADCshiftRA
OpARMSBCshiftLL
OpARMSBCshiftRL
OpARMSBCshiftRA
OpARMRSCshiftLL
OpARMRSCshiftRL
OpARMRSCshiftRA
OpARMADDSshiftLL
OpARMADDSshiftRL
OpARMADDSshiftRA
OpARMSUBSshiftLL
OpARMSUBSshiftRL
OpARMSUBSshiftRA
OpARMRSBSshiftLL
OpARMRSBSshiftRL
OpARMRSBSshiftRA
OpARMADDshiftLLreg
OpARMADDshiftRLreg
OpARMADDshiftRAreg
OpARMSUBshiftLLreg
OpARMSUBshiftRLreg
OpARMSUBshiftRAreg
OpARMRSBshiftLLreg
OpARMRSBshiftRLreg
OpARMRSBshiftRAreg
OpARMANDshiftLLreg
OpARMANDshiftRLreg
OpARMANDshiftRAreg
OpARMORshiftLLreg
OpARMORshiftRLreg
OpARMORshiftRAreg
OpARMXORshiftLLreg
OpARMXORshiftRLreg
OpARMXORshiftRAreg
OpARMBICshiftLLreg
OpARMBICshiftRLreg
OpARMBICshiftRAreg
OpARMMVNshiftLLreg
OpARMMVNshiftRLreg
OpARMMVNshiftRAreg
OpARMADCshiftLLreg
OpARMADCshiftRLreg
OpARMADCshiftRAreg
OpARMSBCshiftLLreg
OpARMSBCshiftRLreg
OpARMSBCshiftRAreg
OpARMRSCshiftLLreg
OpARMRSCshiftRLreg
OpARMRSCshiftRAreg
OpARMADDSshiftLLreg
OpARMADDSshiftRLreg
OpARMADDSshiftRAreg
OpARMSUBSshiftLLreg
OpARMSUBSshiftRLreg
OpARMSUBSshiftRAreg
OpARMRSBSshiftLLreg
OpARMRSBSshiftRLreg
OpARMRSBSshiftRAreg
OpARMCMP
OpARMCMPconst
OpARMCMN
OpARMCMNconst
OpARMTST
OpARMTSTconst
OpARMTEQ
OpARMTEQconst
OpARMCMPF
OpARMCMPD
OpARMCMPshiftLL
OpARMCMPshiftRL
OpARMCMPshiftRA
OpARMCMPshiftLLreg
OpARMCMPshiftRLreg
OpARMCMPshiftRAreg
OpARMCMPF0
OpARMCMPD0
OpARMMOVWconst
OpARMMOVFconst
OpARMMOVDconst
OpARMMOVWaddr
OpARMMOVBload
OpARMMOVBUload
OpARMMOVHload
OpARMMOVHUload
OpARMMOVWload
OpARMMOVFload
OpARMMOVDload
OpARMMOVBstore
OpARMMOVHstore
OpARMMOVWstore
OpARMMOVFstore
OpARMMOVDstore
OpARMMOVWloadidx
OpARMMOVWloadshiftLL
OpARMMOVWloadshiftRL
OpARMMOVWloadshiftRA
OpARMMOVWstoreidx
OpARMMOVWstoreshiftLL
OpARMMOVWstoreshiftRL
OpARMMOVWstoreshiftRA
OpARMMOVBreg
OpARMMOVBUreg
OpARMMOVHreg
OpARMMOVHUreg
OpARMMOVWreg
OpARMMOVWnop
OpARMMOVWF
OpARMMOVWD
OpARMMOVWUF
OpARMMOVWUD
OpARMMOVFW
OpARMMOVDW
OpARMMOVFWU
OpARMMOVDWU
OpARMMOVFD
OpARMMOVDF
OpARMCMOVWHSconst
OpARMCMOVWLSconst
OpARMSRAcond
OpARMCALLstatic
OpARMCALLclosure
OpARMCALLdefer
OpARMCALLgo
OpARMCALLinter
OpARMLoweredNilCheck
OpARMEqual
OpARMNotEqual
OpARMLessThan
OpARMLessEqual
OpARMGreaterThan
OpARMGreaterEqual
OpARMLessThanU
OpARMLessEqualU
OpARMGreaterThanU
OpARMGreaterEqualU
OpARMDUFFZERO
OpARMDUFFCOPY
OpARMLoweredZero
OpARMLoweredMove
OpARMLoweredGetClosurePtr
OpARMMOVWconvert
OpARMFlagEQ
OpARMFlagLT_ULT
OpARMFlagLT_UGT
OpARMFlagGT_UGT
OpARMFlagGT_ULT
OpARMInvertFlags
OpARM64ADD
OpARM64ADDconst
OpARM64SUB
OpARM64SUBconst
OpARM64MUL
OpARM64MULW
OpARM64MULH
OpARM64UMULH
OpARM64MULL
OpARM64UMULL
OpARM64DIV
OpARM64UDIV
OpARM64DIVW
OpARM64UDIVW
OpARM64MOD
OpARM64UMOD
OpARM64MODW
OpARM64UMODW
OpARM64FADDS
OpARM64FADDD
OpARM64FSUBS
OpARM64FSUBD
OpARM64FMULS
OpARM64FMULD
OpARM64FDIVS
OpARM64FDIVD
OpARM64AND
OpARM64ANDconst
OpARM64OR
OpARM64ORconst
OpARM64XOR
OpARM64XORconst
OpARM64BIC
OpARM64BICconst
OpARM64MVN
OpARM64NEG
OpARM64FNEGS
OpARM64FNEGD
OpARM64FSQRTD
OpARM64SLL
OpARM64SLLconst
OpARM64SRL
OpARM64SRLconst
OpARM64SRA
OpARM64SRAconst
OpARM64RORconst
OpARM64RORWconst
OpARM64CMP
OpARM64CMPconst
OpARM64CMPW
OpARM64CMPWconst
OpARM64CMN
OpARM64CMNconst
OpARM64CMNW
OpARM64CMNWconst
OpARM64FCMPS
OpARM64FCMPD
OpARM64ADDshiftLL
OpARM64ADDshiftRL
OpARM64ADDshiftRA
OpARM64SUBshiftLL
OpARM64SUBshiftRL
OpARM64SUBshiftRA
OpARM64ANDshiftLL
OpARM64ANDshiftRL
OpARM64ANDshiftRA
OpARM64ORshiftLL
OpARM64ORshiftRL
OpARM64ORshiftRA
OpARM64XORshiftLL
OpARM64XORshiftRL
OpARM64XORshiftRA
OpARM64BICshiftLL
OpARM64BICshiftRL
OpARM64BICshiftRA
OpARM64CMPshiftLL
OpARM64CMPshiftRL
OpARM64CMPshiftRA
OpARM64MOVDconst
OpARM64FMOVSconst
OpARM64FMOVDconst
OpARM64MOVDaddr
OpARM64MOVBload
OpARM64MOVBUload
OpARM64MOVHload
OpARM64MOVHUload
OpARM64MOVWload
OpARM64MOVWUload
OpARM64MOVDload
OpARM64FMOVSload
OpARM64FMOVDload
OpARM64MOVBstore
OpARM64MOVHstore
OpARM64MOVWstore
OpARM64MOVDstore
OpARM64FMOVSstore
OpARM64FMOVDstore
OpARM64MOVBstorezero
OpARM64MOVHstorezero
OpARM64MOVWstorezero
OpARM64MOVDstorezero
OpARM64MOVBreg
OpARM64MOVBUreg
OpARM64MOVHreg
OpARM64MOVHUreg
OpARM64MOVWreg
OpARM64MOVWUreg
OpARM64MOVDreg
OpARM64MOVDnop
OpARM64SCVTFWS
OpARM64SCVTFWD
OpARM64UCVTFWS
OpARM64UCVTFWD
OpARM64SCVTFS
OpARM64SCVTFD
OpARM64UCVTFS
OpARM64UCVTFD
OpARM64FCVTZSSW
OpARM64FCVTZSDW
OpARM64FCVTZUSW
OpARM64FCVTZUDW
OpARM64FCVTZSS
OpARM64FCVTZSD
OpARM64FCVTZUS
OpARM64FCVTZUD
OpARM64FCVTSD
OpARM64FCVTDS
OpARM64CSELULT
OpARM64CSELULT0
OpARM64CALLstatic
OpARM64CALLclosure
OpARM64CALLdefer
OpARM64CALLgo
OpARM64CALLinter
OpARM64LoweredNilCheck
OpARM64Equal
OpARM64NotEqual
OpARM64LessThan
OpARM64LessEqual
OpARM64GreaterThan
OpARM64GreaterEqual
OpARM64LessThanU
OpARM64LessEqualU
OpARM64GreaterThanU
OpARM64GreaterEqualU
OpARM64DUFFZERO
OpARM64LoweredZero
OpARM64LoweredMove
OpARM64LoweredGetClosurePtr
OpARM64MOVDconvert
OpARM64FlagEQ
OpARM64FlagLT_ULT
OpARM64FlagLT_UGT
OpARM64FlagGT_UGT
OpARM64FlagGT_ULT
OpARM64InvertFlags
OpPPC64ADD
OpPPC64ADDconst
OpPPC64FADD
OpPPC64FADDS
OpPPC64SUB
OpPPC64FSUB
OpPPC64FSUBS
OpPPC64MULLD
OpPPC64MULLW
OpPPC64MULHD
OpPPC64MULHW
OpPPC64MULHDU
OpPPC64MULHWU
OpPPC64FMUL
OpPPC64FMULS
OpPPC64SRAD
OpPPC64SRAW
OpPPC64SRD
OpPPC64SRW
OpPPC64SLD
OpPPC64SLW
OpPPC64ADDconstForCarry
OpPPC64MaskIfNotCarry
OpPPC64SRADconst
OpPPC64SRAWconst
OpPPC64SRDconst
OpPPC64SRWconst
OpPPC64SLDconst
OpPPC64SLWconst
OpPPC64FDIV
OpPPC64FDIVS
OpPPC64DIVD
OpPPC64DIVW
OpPPC64DIVDU
OpPPC64DIVWU
OpPPC64FCTIDZ
OpPPC64FCTIWZ
OpPPC64FCFID
OpPPC64FRSP
OpPPC64Xf2i64
OpPPC64Xi2f64
OpPPC64AND
OpPPC64ANDN
OpPPC64OR
OpPPC64ORN
OpPPC64XOR
OpPPC64EQV
OpPPC64NEG
OpPPC64FNEG
OpPPC64FSQRT
OpPPC64FSQRTS
OpPPC64ORconst
OpPPC64XORconst
OpPPC64ANDconst
OpPPC64MOVBreg
OpPPC64MOVBZreg
OpPPC64MOVHreg
OpPPC64MOVHZreg
OpPPC64MOVWreg
OpPPC64MOVWZreg
OpPPC64MOVBload
OpPPC64MOVBZload
OpPPC64MOVHload
OpPPC64MOVHZload
OpPPC64MOVWload
OpPPC64MOVWZload
OpPPC64MOVDload
OpPPC64FMOVDload
OpPPC64FMOVSload
OpPPC64MOVBstore
OpPPC64MOVHstore
OpPPC64MOVWstore
OpPPC64MOVDstore
OpPPC64FMOVDstore
OpPPC64FMOVSstore
OpPPC64MOVBstorezero
OpPPC64MOVHstorezero
OpPPC64MOVWstorezero
OpPPC64MOVDstorezero
OpPPC64MOVDaddr
OpPPC64MOVDconst
OpPPC64MOVWconst
OpPPC64FMOVDconst
OpPPC64FMOVSconst
OpPPC64FCMPU
OpPPC64CMP
OpPPC64CMPU
OpPPC64CMPW
OpPPC64CMPWU
OpPPC64CMPconst
OpPPC64CMPUconst
OpPPC64CMPWconst
OpPPC64CMPWUconst
OpPPC64Equal
OpPPC64NotEqual
OpPPC64LessThan
OpPPC64FLessThan
OpPPC64LessEqual
OpPPC64FLessEqual
OpPPC64GreaterThan
OpPPC64FGreaterThan
OpPPC64GreaterEqual
OpPPC64FGreaterEqual
OpPPC64LoweredGetClosurePtr
OpPPC64LoweredNilCheck
OpPPC64MOVDconvert
OpPPC64CALLstatic
OpPPC64CALLclosure
OpPPC64CALLdefer
OpPPC64CALLgo
OpPPC64CALLinter
OpPPC64LoweredZero
OpPPC64LoweredMove
OpPPC64InvertFlags
OpPPC64FlagEQ
OpPPC64FlagLT
OpPPC64FlagGT
OpAdd8
OpAdd16
OpAdd32
OpAdd64
OpAddPtr
OpAdd32F
OpAdd64F
OpSub8
OpSub16
OpSub32
OpSub64
OpSubPtr
OpSub32F
OpSub64F
OpMul8
OpMul16
OpMul32
OpMul64
OpMul32F
OpMul64F
OpDiv32F
OpDiv64F
OpHmul8
OpHmul8u
OpHmul16
OpHmul16u
OpHmul32
OpHmul32u
OpHmul64
OpHmul64u
OpAvg64u
OpDiv8
OpDiv8u
OpDiv16
OpDiv16u
OpDiv32
OpDiv32u
OpDiv64
OpDiv64u
OpMod8
OpMod8u
OpMod16
OpMod16u
OpMod32
OpMod32u
OpMod64
OpMod64u
OpAnd8
OpAnd16
OpAnd32
OpAnd64
OpOr8
OpOr16
OpOr32
OpOr64
OpXor8
OpXor16
OpXor32
OpXor64
OpLsh8x8
OpLsh8x16
OpLsh8x32
OpLsh8x64
OpLsh16x8
OpLsh16x16
OpLsh16x32
OpLsh16x64
OpLsh32x8
OpLsh32x16
OpLsh32x32
OpLsh32x64
OpLsh64x8
OpLsh64x16
OpLsh64x32
OpLsh64x64
OpRsh8x8
OpRsh8x16
OpRsh8x32
OpRsh8x64
OpRsh16x8
OpRsh16x16
OpRsh16x32
OpRsh16x64
OpRsh32x8
OpRsh32x16
OpRsh32x32
OpRsh32x64
OpRsh64x8
OpRsh64x16
OpRsh64x32
OpRsh64x64
OpRsh8Ux8
OpRsh8Ux16
OpRsh8Ux32
OpRsh8Ux64
OpRsh16Ux8
OpRsh16Ux16
OpRsh16Ux32
OpRsh16Ux64
OpRsh32Ux8
OpRsh32Ux16
OpRsh32Ux32
OpRsh32Ux64
OpRsh64Ux8
OpRsh64Ux16
OpRsh64Ux32
OpRsh64Ux64
OpLrot8
OpLrot16
OpLrot32
OpLrot64
OpEq8
OpEq16
OpEq32
OpEq64
OpEqPtr
OpEqInter
OpEqSlice
OpEq32F
OpEq64F
OpNeq8
OpNeq16
OpNeq32
OpNeq64
OpNeqPtr
OpNeqInter
OpNeqSlice
OpNeq32F
OpNeq64F
OpLess8
OpLess8U
OpLess16
OpLess16U
OpLess32
OpLess32U
OpLess64
OpLess64U
OpLess32F
OpLess64F
OpLeq8
OpLeq8U
OpLeq16
OpLeq16U
OpLeq32
OpLeq32U
OpLeq64
OpLeq64U
OpLeq32F
OpLeq64F
OpGreater8
OpGreater8U
OpGreater16
OpGreater16U
OpGreater32
OpGreater32U
OpGreater64
OpGreater64U
OpGreater32F
OpGreater64F
OpGeq8
OpGeq8U
OpGeq16
OpGeq16U
OpGeq32
OpGeq32U
OpGeq64
OpGeq64U
OpGeq32F
OpGeq64F
OpAndB
OpOrB
OpEqB
OpNeqB
OpNot
OpNeg8
OpNeg16
OpNeg32
OpNeg64
OpNeg32F
OpNeg64F
OpCom8
OpCom16
OpCom32
OpCom64
OpCtz16
OpCtz32
OpCtz64
OpClz16
OpClz32
OpClz64
OpBswap32
OpBswap64
OpSqrt
OpPhi
OpCopy
OpConvert
OpConstBool
OpConstString
OpConstNil
OpConst8
OpConst16
OpConst32
OpConst64
OpConst32F
OpConst64F
OpConstInterface
OpConstSlice
OpInitMem
OpArg
OpAddr
OpSP
OpSB
OpFunc
OpLoad
OpStore
OpMove
OpZero
OpClosureCall
OpStaticCall
OpDeferCall
OpGoCall
OpInterCall
OpSignExt8to16
OpSignExt8to32
OpSignExt8to64
OpSignExt16to32
OpSignExt16to64
OpSignExt32to64
OpZeroExt8to16
OpZeroExt8to32
OpZeroExt8to64
OpZeroExt16to32
OpZeroExt16to64
OpZeroExt32to64
OpTrunc16to8
OpTrunc32to8
OpTrunc32to16
OpTrunc64to8
OpTrunc64to16
OpTrunc64to32
OpCvt32to32F
OpCvt32to64F
OpCvt64to32F
OpCvt64to64F
OpCvt32Fto32
OpCvt32Fto64
OpCvt64Fto32
OpCvt64Fto64
OpCvt32Fto64F
OpCvt64Fto32F
OpIsNonNil
OpIsInBounds
OpIsSliceInBounds
OpNilCheck
OpGetG
OpGetClosurePtr
OpArrayIndex
OpPtrIndex
OpOffPtr
OpSliceMake
OpSlicePtr
OpSliceLen
OpSliceCap
OpComplexMake
OpComplexReal
OpComplexImag
OpStringMake
OpStringPtr
OpStringLen
OpIMake
OpITab
OpIData
OpStructMake0
OpStructMake1
OpStructMake2
OpStructMake3
OpStructMake4
OpStructSelect
OpStoreReg
OpLoadReg
OpFwdRef
OpUnknown
OpVarDef
OpVarKill
OpVarLive
OpKeepAlive
OpInt64Make
OpInt64Hi
OpInt64Lo
OpAdd32carry
OpAdd32withcarry
OpSub32carry
OpSub32withcarry
OpMul32uhilo
OpSignmask
OpZeromask
OpCvt32Uto32F
OpCvt32Uto64F
OpCvt32Fto32U
OpCvt64Fto32U
OpSelect0
OpSelect1
)
var opcodeTable = [...]opInfo{
{name: "OpInvalid"},
{
name: "ADDSS",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AADDSS,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "ADDSD",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AADDSD,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "SUBSS",
argLen: 2,
resultInArg0: true,
asm: x86.ASUBSS,
reg: regInfo{
inputs: []inputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
clobbers: 32768, // X7
outputs: []outputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
},
},
{
name: "SUBSD",
argLen: 2,
resultInArg0: true,
asm: x86.ASUBSD,
reg: regInfo{
inputs: []inputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
clobbers: 32768, // X7
outputs: []outputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
},
},
{
name: "MULSS",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AMULSS,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MULSD",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AMULSD,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "DIVSS",
argLen: 2,
resultInArg0: true,
asm: x86.ADIVSS,
reg: regInfo{
inputs: []inputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
clobbers: 32768, // X7
outputs: []outputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
},
},
{
name: "DIVSD",
argLen: 2,
resultInArg0: true,
asm: x86.ADIVSD,
reg: regInfo{
inputs: []inputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
{1, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
clobbers: 32768, // X7
outputs: []outputInfo{
{0, 32512}, // X0 X1 X2 X3 X4 X5 X6
},
},
},
{
name: "MOVSSload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSDload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSSconst",
auxType: auxFloat32,
argLen: 0,
rematerializeable: true,
asm: x86.AMOVSS,
reg: regInfo{
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSDconst",
auxType: auxFloat64,
argLen: 0,
rematerializeable: true,
asm: x86.AMOVSD,
reg: regInfo{
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSSloadidx1",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSSloadidx4",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSDloadidx1",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSDloadidx8",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSSstore",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVSDstore",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVSSstoreidx1",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVSSstoreidx4",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVSDstoreidx1",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVSDstoreidx8",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "ADDL",
argLen: 2,
commutative: true,
clobberFlags: true,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{1, 239}, // AX CX DX BX BP SI DI
{0, 255}, // AX CX DX BX SP BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ADDLconst",
auxType: auxInt32,
argLen: 1,
clobberFlags: true,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ADDLcarry",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 0},
{1, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ADDLconstcarry",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 0},
{1, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ADCL",
argLen: 3,
commutative: true,
resultInArg0: true,
clobberFlags: true,
asm: x86.AADCL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ADCLconst",
auxType: auxInt32,
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.AADCL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SUBL",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SUBLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SUBLcarry",
argLen: 2,
resultInArg0: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 0},
{1, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SUBLconstcarry",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 0},
{1, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SBBL",
argLen: 3,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASBBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SBBLconst",
auxType: auxInt32,
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASBBL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MULL",
argLen: 2,
commutative: true,
resultInArg0: true,
clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MULLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "HMULL",
argLen: 2,
clobberFlags: true,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "HMULLU",
argLen: 2,
clobberFlags: true,
asm: x86.AMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "HMULW",
argLen: 2,
clobberFlags: true,
asm: x86.AIMULW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "HMULB",
argLen: 2,
clobberFlags: true,
asm: x86.AIMULB,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "HMULWU",
argLen: 2,
clobberFlags: true,
asm: x86.AMULW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "HMULBU",
argLen: 2,
clobberFlags: true,
asm: x86.AMULB,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "MULLQU",
argLen: 2,
clobberFlags: true,
asm: x86.AMULL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 255}, // AX CX DX BX SP BP SI DI
},
outputs: []outputInfo{
{0, 4}, // DX
{1, 1}, // AX
},
},
},
{
name: "DIVL",
argLen: 2,
clobberFlags: true,
asm: x86.AIDIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
name: "DIVW",
argLen: 2,
clobberFlags: true,
asm: x86.AIDIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
name: "DIVLU",
argLen: 2,
clobberFlags: true,
asm: x86.ADIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
name: "DIVWU",
argLen: 2,
clobberFlags: true,
asm: x86.ADIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 4, // DX
outputs: []outputInfo{
{0, 1}, // AX
},
},
},
{
name: "MODL",
argLen: 2,
clobberFlags: true,
asm: x86.AIDIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "MODW",
argLen: 2,
clobberFlags: true,
asm: x86.AIDIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "MODLU",
argLen: 2,
clobberFlags: true,
asm: x86.ADIVL,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "MODWU",
argLen: 2,
clobberFlags: true,
asm: x86.ADIVW,
reg: regInfo{
inputs: []inputInfo{
{0, 1}, // AX
{1, 251}, // AX CX BX SP BP SI DI
},
clobbers: 1, // AX
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "ANDL",
argLen: 2,
commutative: true,
resultInArg0: true,
clobberFlags: true,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ANDLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ORL",
argLen: 2,
commutative: true,
resultInArg0: true,
clobberFlags: true,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ORLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "XORL",
argLen: 2,
commutative: true,
resultInArg0: true,
clobberFlags: true,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
{1, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "XORLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "CMPL",
argLen: 2,
asm: x86.ACMPL,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "CMPW",
argLen: 2,
asm: x86.ACMPW,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "CMPB",
argLen: 2,
asm: x86.ACMPB,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "CMPLconst",
auxType: auxInt32,
argLen: 1,
asm: x86.ACMPL,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "CMPWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.ACMPW,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "CMPBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.ACMPB,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "UCOMISS",
argLen: 2,
asm: x86.AUCOMISS,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "UCOMISD",
argLen: 2,
asm: x86.AUCOMISD,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "TESTL",
argLen: 2,
asm: x86.ATESTL,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "TESTW",
argLen: 2,
asm: x86.ATESTW,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "TESTB",
argLen: 2,
asm: x86.ATESTB,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
{1, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "TESTLconst",
auxType: auxInt32,
argLen: 1,
asm: x86.ATESTL,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "TESTWconst",
auxType: auxInt16,
argLen: 1,
asm: x86.ATESTW,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "TESTBconst",
auxType: auxInt8,
argLen: 1,
asm: x86.ATESTB,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "SHLL",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHLLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHRL",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHRW",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHRB",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHRLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHRWconst",
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SHRBconst",
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SARL",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SARW",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SARB",
argLen: 2,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
{1, 2}, // CX
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SARLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SARWconst",
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SARBconst",
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ROLLconst",
auxType: auxInt32,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AROLL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ROLWconst",
auxType: auxInt16,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AROLW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "ROLBconst",
auxType: auxInt8,
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.AROLB,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "NEGL",
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ANEGL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "NOTL",
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ANOTL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "BSFL",
argLen: 1,
clobberFlags: true,
asm: x86.ABSFL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "BSFW",
argLen: 1,
clobberFlags: true,
asm: x86.ABSFW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "BSRL",
argLen: 1,
clobberFlags: true,
asm: x86.ABSRL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "BSRW",
argLen: 1,
clobberFlags: true,
asm: x86.ABSRW,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "BSWAPL",
argLen: 1,
resultInArg0: true,
clobberFlags: true,
asm: x86.ABSWAPL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SQRTSD",
argLen: 1,
asm: x86.ASQRTSD,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "SBBLcarrymask",
argLen: 1,
asm: x86.ASBBL,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETEQ",
argLen: 1,
asm: x86.ASETEQ,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETNE",
argLen: 1,
asm: x86.ASETNE,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETL",
argLen: 1,
asm: x86.ASETLT,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETLE",
argLen: 1,
asm: x86.ASETLE,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETG",
argLen: 1,
asm: x86.ASETGT,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETGE",
argLen: 1,
asm: x86.ASETGE,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETB",
argLen: 1,
asm: x86.ASETCS,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETBE",
argLen: 1,
asm: x86.ASETLS,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETA",
argLen: 1,
asm: x86.ASETHI,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETAE",
argLen: 1,
asm: x86.ASETCC,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETEQF",
argLen: 1,
clobberFlags: true,
asm: x86.ASETEQ,
reg: regInfo{
clobbers: 1, // AX
outputs: []outputInfo{
{0, 238}, // CX DX BX BP SI DI
},
},
},
{
name: "SETNEF",
argLen: 1,
clobberFlags: true,
asm: x86.ASETNE,
reg: regInfo{
clobbers: 1, // AX
outputs: []outputInfo{
{0, 238}, // CX DX BX BP SI DI
},
},
},
{
name: "SETORD",
argLen: 1,
asm: x86.ASETPC,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETNAN",
argLen: 1,
asm: x86.ASETPS,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETGF",
argLen: 1,
asm: x86.ASETHI,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "SETGEF",
argLen: 1,
asm: x86.ASETCC,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVBLSX",
argLen: 1,
asm: x86.AMOVBLSX,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVBLZX",
argLen: 1,
asm: x86.AMOVBLZX,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVWLSX",
argLen: 1,
asm: x86.AMOVWLSX,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVWLZX",
argLen: 1,
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVLconst",
auxType: auxInt32,
argLen: 0,
rematerializeable: true,
asm: x86.AMOVL,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "CVTTSD2SL",
argLen: 1,
asm: x86.ACVTTSD2SL,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "CVTTSS2SL",
argLen: 1,
asm: x86.ACVTTSS2SL,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "CVTSL2SS",
argLen: 1,
asm: x86.ACVTSL2SS,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "CVTSL2SD",
argLen: 1,
asm: x86.ACVTSL2SD,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "CVTSD2SS",
argLen: 1,
asm: x86.ACVTSD2SS,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "CVTSS2SD",
argLen: 1,
asm: x86.ACVTSS2SD,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "PXOR",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.APXOR,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "LEAL",
auxType: auxSymOff,
argLen: 1,
rematerializeable: true,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "LEAL1",
auxType: auxSymOff,
argLen: 2,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "LEAL2",
auxType: auxSymOff,
argLen: 2,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "LEAL4",
auxType: auxSymOff,
argLen: 2,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "LEAL8",
auxType: auxSymOff,
argLen: 2,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVBload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVBLZX,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVBLSXload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVBLSX,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVWload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVWLSXload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVWLSX,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVLload",
auxType: auxSymOff,
argLen: 2,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVBstore",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVWstore",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVLstore",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVBloadidx1",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVBLZX,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVWloadidx1",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVWloadidx2",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVWLZX,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVLloadidx1",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVLloadidx4",
auxType: auxSymOff,
argLen: 3,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVBstoreidx1",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVWstoreidx1",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVWstoreidx2",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVLstoreidx1",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVLstoreidx4",
auxType: auxSymOff,
argLen: 4,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{2, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVBstoreconst",
auxType: auxSymValAndOff,
argLen: 2,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVWstoreconst",
auxType: auxSymValAndOff,
argLen: 2,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVLstoreconst",
auxType: auxSymValAndOff,
argLen: 2,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVBstoreconstidx1",
auxType: auxSymValAndOff,
argLen: 3,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVWstoreconstidx1",
auxType: auxSymValAndOff,
argLen: 3,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVWstoreconstidx2",
auxType: auxSymValAndOff,
argLen: 3,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVLstoreconstidx1",
auxType: auxSymValAndOff,
argLen: 3,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "MOVLstoreconstidx4",
auxType: auxSymValAndOff,
argLen: 3,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{1, 255}, // AX CX DX BX SP BP SI DI
{0, 65791}, // AX CX DX BX SP BP SI DI SB
},
},
},
{
name: "DUFFZERO",
auxType: auxInt64,
argLen: 3,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 1}, // AX
},
clobbers: 130, // CX DI
},
},
{
name: "REPSTOSL",
argLen: 4,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 2}, // CX
{2, 1}, // AX
},
clobbers: 130, // CX DI
},
},
{
name: "CALLstatic",
auxType: auxSymOff,
argLen: 1,
clobberFlags: true,
reg: regInfo{
clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
name: "CALLclosure",
auxType: auxInt64,
argLen: 3,
clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{1, 4}, // DX
{0, 255}, // AX CX DX BX SP BP SI DI
},
clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
name: "CALLdefer",
auxType: auxInt64,
argLen: 1,
clobberFlags: true,
reg: regInfo{
clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
name: "CALLgo",
auxType: auxInt64,
argLen: 1,
clobberFlags: true,
reg: regInfo{
clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
name: "CALLinter",
auxType: auxInt64,
argLen: 2,
clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
},
},
{
name: "DUFFCOPY",
auxType: auxInt64,
argLen: 3,
clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 64}, // SI
},
clobbers: 194, // CX SI DI
},
},
{
name: "REPMOVSL",
argLen: 4,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // DI
{1, 64}, // SI
{2, 2}, // CX
},
clobbers: 194, // CX SI DI
},
},
{
name: "InvertFlags",
argLen: 1,
reg: regInfo{},
},
{
name: "LoweredGetG",
argLen: 1,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "LoweredGetClosurePtr",
argLen: 0,
reg: regInfo{
outputs: []outputInfo{
{0, 4}, // DX
},
},
},
{
name: "LoweredNilCheck",
argLen: 2,
clobberFlags: true,
reg: regInfo{
inputs: []inputInfo{
{0, 255}, // AX CX DX BX SP BP SI DI
},
},
},
{
name: "MOVLconvert",
argLen: 2,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "FlagEQ",
argLen: 0,
reg: regInfo{},
},
{
name: "FlagLT_ULT",
argLen: 0,
reg: regInfo{},
},
{
name: "FlagLT_UGT",
argLen: 0,
reg: regInfo{},
},
{
name: "FlagGT_UGT",
argLen: 0,
reg: regInfo{},
},
{
name: "FlagGT_ULT",
argLen: 0,
reg: regInfo{},
},
{
name: "FCHS",
argLen: 1,
reg: regInfo{
inputs: []inputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSSconst1",
auxType: auxFloat32,
argLen: 0,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVSDconst1",
auxType: auxFloat64,
argLen: 0,
reg: regInfo{
outputs: []outputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
},
},
{
name: "MOVSSconst2",
argLen: 1,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "MOVSDconst2",
argLen: 1,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
{0, 239}, // AX CX DX BX BP SI DI
},
outputs: []outputInfo{
{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
},
},
},
{
name: "ADDSS",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AADDSS,
reg: regInfo{
inputs: []inputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
outputs: []outputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
},
{
name: "ADDSD",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AADDSD,
reg: regInfo{
inputs: []inputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
outputs: []outputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
},
{
name: "SUBSS",
argLen: 2,
resultInArg0: true,
asm: x86.ASUBSS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
clobbers: 2147483648, // X15
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
name: "SUBSD",
argLen: 2,
resultInArg0: true,
asm: x86.ASUBSD,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
clobbers: 2147483648, // X15
outputs: []outputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
},
},
{
name: "MULSS",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AMULSS,
reg: regInfo{
inputs: []inputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
outputs: []outputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
},
{
name: "MULSD",
argLen: 2,
commutative: true,
resultInArg0: true,
asm: x86.AMULSD,
reg: regInfo{
inputs: []inputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
outputs: []outputInfo{
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
},
},
},
{
name: "DIVSS",
argLen: 2,
resultInArg0: true,
asm: x86.ADIVSS,
reg: regInfo{
inputs: []inputInfo{
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
},
clobbers: 2147483648, // X15