// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// Lowering arithmetic
(Add(64|32|16|8) ...) => (ADD(Q|L|L|L) ...)
(AddPtr ...) => (ADDQ ...)
(Add(32|64)F ...) => (ADDS(S|D) ...)

(Sub(64|32|16|8) ...) => (SUB(Q|L|L|L) ...)
(SubPtr ...) => (SUBQ ...)
(Sub(32|64)F ...) => (SUBS(S|D) ...)

(Mul(64|32|16|8) ...) => (MUL(Q|L|L|L) ...)
(Mul(32|64)F ...) => (MULS(S|D) ...)

(Select0 (Mul64uover x y)) => (Select0 <typ.UInt64> (MULQU x y))
(Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
(Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y)))

(Hmul(64|32) ...) => (HMUL(Q|L) ...)
(Hmul(64|32)u ...) => (HMUL(Q|L)U ...)

(Div(64|32|16) [a] x y) => (Select0 (DIV(Q|L|W) [a] x y))
(Div8  x y) => (Select0 (DIVW  (SignExt8to16 x) (SignExt8to16 y)))
(Div(64|32|16)u x y) => (Select0 (DIV(Q|L|W)U x y))
(Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
(Div(32|64)F ...) => (DIVS(S|D) ...)

(Select0 (Add64carry x y c)) => (Select0 (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
(Select1 (Add64carry x y c)) => (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
(Select0 (Sub64borrow x y c)) => (Select0 (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
(Select1 (Sub64borrow x y c)) => (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
// Optimize ADCQ and friends
(ADCQ x (MOVQconst [c]) carry) && ssa.Is32Bit(c) => (ADCQconst x [int32(c)] carry)
(ADCQ x y (FlagEQ)) => (ADDQcarry x y)
(ADCQconst x [c] (FlagEQ)) => (ADDQconstcarry x [c])
(ADDQcarry x (MOVQconst [c])) && ssa.Is32Bit(c) => (ADDQconstcarry x [int32(c)])
(SBBQ x (MOVQconst [c]) borrow) && ssa.Is32Bit(c) => (SBBQconst x [int32(c)] borrow)
(SBBQ x y (FlagEQ)) => (SUBQborrow x y)
(SBBQconst x [c] (FlagEQ)) => (SUBQconstborrow x [c])
(SUBQborrow x (MOVQconst [c])) && ssa.Is32Bit(c) => (SUBQconstborrow x [int32(c)])
(Select1 (NEGLflags (MOVQconst [0]))) => (FlagEQ)
(Select1 (NEGLflags (MOVBQZX (SETB x)))) => x
// Absorb InvertFlags into ADCQ/SBBQ: CF(InvertFlags(f)) = SETA(f), so
// re-materialize the carry/borrow through the SETA+NEGLflags path.
(ADCQ x y (InvertFlags f)) => (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
(ADCQconst x [c] (InvertFlags f)) => (ADCQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
(SBBQ x y (InvertFlags f)) => (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
(SBBQconst x [c] (InvertFlags f)) => (SBBQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
// ADDQ/SUBQ an from a carry flag into ADCQ/SBBQ
// TODO: maybe add ADCL and SBBL ?
(ADDQ x (MOVBQZX (SETB flags))) => (Select0 (ADCQconst [0] x flags))
(SUBQ x (MOVBQZX (SETB flags))) => (Select0 (SBBQconst [0] x flags))

(Mul64uhilo x y) && buildcfg.GOAMD64 >= 3 => (MULXQ x y)
(Mul64uhilo x y) && buildcfg.GOAMD64 <  3 => (MULQU2 x y)
(Div128u ...) => (DIVQU2 ...)

(Avg64u ...) => (AVGQU ...)

(Mod(64|32|16) [a] x y) => (Select1 (DIV(Q|L|W) [a] x y))
(Mod8  x y) => (Select1 (DIVW  (SignExt8to16 x) (SignExt8to16 y)))
(Mod(64|32|16)u x y) => (Select1 (DIV(Q|L|W)U x y))
(Mod8u x y) => (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))

(And(64|32|16|8) ...) => (AND(Q|L|L|L) ...)
(Or(64|32|16|8) ...) => (OR(Q|L|L|L) ...)
(Xor(64|32|16|8) ...) => (XOR(Q|L|L|L) ...)
(Com(64|32|16|8) ...) => (NOT(Q|L|L|L) ...)

(Neg(64|32|16|8) ...) => (NEG(Q|L|L|L) ...)
(Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
(Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))

// Lowering boolean ops
(AndB ...) => (ANDL ...)
(OrB ...) => (ORL ...)
(Not x) => (XORLconst [1] x)

// Lowering pointer arithmetic
(OffPtr [off] ptr) && ssa.Is32Bit(off) => (ADDQconst [int32(off)] ptr)
(OffPtr [off] ptr) => (ADDQ (MOVQconst [off]) ptr)

// Lowering other arithmetic
(Ctz64 x)     && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
(Ctz32 x)     && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
(Ctz64 <t> x) && buildcfg.GOAMD64 <  3 => (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
(Ctz32 x)     && buildcfg.GOAMD64 <  3 => (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
(Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [1<<16] x))
(Ctz8  x) => (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))

(Ctz64NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
(Ctz32NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
(Ctz16NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
(Ctz8NonZero  x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
(Ctz64NonZero x) && buildcfg.GOAMD64 <  3 => (Select0 (BSFQ x))
(Ctz32NonZero x) && buildcfg.GOAMD64 <  3 => (BSFL x)
(Ctz16NonZero x) && buildcfg.GOAMD64 <  3 => (BSFL x)
(Ctz8NonZero  x) && buildcfg.GOAMD64 <  3 => (BSFL x)

// BitLen64 of a 64 bit value x requires checking whether x == 0, since BSRQ is undefined when x == 0.
// However, for zero-extended values, we can cheat a bit, and calculate
// BSR(x<<1 + 1), which is guaranteed to be non-zero, and which conveniently
// places the index of the highest set bit where we want it.
// For GOAMD64>=3, BitLen can be calculated by OperandSize - LZCNT(x).
(BitLen64 <t> x) && buildcfg.GOAMD64 < 3 => (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
(BitLen32 x) && buildcfg.GOAMD64 <  3 => (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
(BitLen16 x) && buildcfg.GOAMD64 <  3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
(BitLen8  x) && buildcfg.GOAMD64 <  3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
(BitLen64 <t> x)        && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
// Use 64-bit version to allow const-fold remove unnecessary arithmetic.
(BitLen32 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
(BitLen16 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
(BitLen8 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))

(Bswap(64|32) ...) => (BSWAP(Q|L) ...)
(Bswap16 x) => (ROLWconst [8] x)

(PopCount(64|32) ...) => (POPCNT(Q|L) ...)
(PopCount16 x) => (POPCNTL (MOVWQZX <typ.UInt32> x))
(PopCount8 x) => (POPCNTL (MOVBQZX <typ.UInt32> x))

(Sqrt ...) => (SQRTSD ...)
(Sqrt32 ...) => (SQRTSS ...)

(RoundToEven x) => (ROUNDSD [0] x)
(Floor x)       => (ROUNDSD [1] x)
(Ceil x)        => (ROUNDSD [2] x)
(Trunc x)       => (ROUNDSD [3] x)

(CVTSD2SS (ROUNDSD [c] (CVTSS2SD x))) => (ROUNDSS [c] x)

(FMA x y z) => (VFMADD231SD z x y)

// Lowering extension
// Note: we always extend to 64 bits even though some ops don't need that many result bits.
(SignExt8to16  ...) => (MOVBQSX ...)
(SignExt8to32  ...) => (MOVBQSX ...)
(SignExt8to64  ...) => (MOVBQSX ...)
(SignExt16to32 ...) => (MOVWQSX ...)
(SignExt16to64 ...) => (MOVWQSX ...)
(SignExt32to64 ...) => (MOVLQSX ...)

(ZeroExt8to16  ...) => (MOVBQZX ...)
(ZeroExt8to32  ...) => (MOVBQZX ...)
(ZeroExt8to64  ...) => (MOVBQZX ...)
(ZeroExt16to32 ...) => (MOVWQZX ...)
(ZeroExt16to64 ...) => (MOVWQZX ...)
(ZeroExt32to64 ...) => (MOVLQZX ...)

(Slicemask <t> x) => (SARQconst (NEGQ <t> x) [63])

(SpectreIndex <t> x y) => (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
(SpectreSliceIndex <t> x y) => (CMOVQHI x (MOVQconst [0]) (CMPQ x y))

// Lowering truncation
// Because we ignore high parts of registers, truncates are just copies.
(Trunc16to8  ...) => (Copy ...)
(Trunc32to8  ...) => (Copy ...)
(Trunc32to16 ...) => (Copy ...)
(Trunc64to8  ...) => (Copy ...)
(Trunc64to16 ...) => (Copy ...)
(Trunc64to32 ...) => (Copy ...)

// Lowering float <-> int
(Cvt32to32F ...) => (CVTSL2SS ...)
(Cvt32to64F ...) => (CVTSL2SD ...)
(Cvt64to32F ...) => (CVTSQ2SS ...)
(Cvt64to64F ...) => (CVTSQ2SD ...)

// Float, to int.
// To make AMD64 "overflow" return max positive instead of max negative, compute
// y and not x, smear the sign bit, and xor.
(Cvt32Fto32 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSS2SL <t> x) (NOTL <typ.Int32> (MOVLf2i x)))))
(Cvt64Fto32 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSD2SL <t> x) (NOTL <typ.Int32> (MOVLf2i (CVTSD2SS <typ.Float32> x))))))

(Cvt32Fto64 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSS2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i (CVTSS2SD <typ.Float64> x))) )))
(Cvt64Fto64 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSD2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i x)))))

(Cvt32Fto32 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSS2SL <t> x)
(Cvt32Fto64 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSS2SQ <t> x)
(Cvt64Fto32 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSD2SL <t> x)
(Cvt64Fto64 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSD2SQ <t> x)

(Cvt32Fto64F ...) => (CVTSS2SD ...)
(Cvt64Fto32F ...) => (CVTSD2SS ...)

(Round(32|64)F ...) => (LoweredRound(32|64)F ...)

// Floating-point min is tricky, as the hardware op isn't right for various special
// cases (-0 and NaN). We use two hardware ops organized just right to make the
// result come out how we want it. See https://github.com/golang/go/issues/59488#issuecomment-1553493207
// (although that comment isn't exactly right, as the value overwritten is not simulated correctly).
//    t1 = MINSD x, y   => incorrect if x==NaN or x==-0,y==+0
//    t2 = MINSD t1, x  => fixes x==NaN case
//   res = POR t1, t2   => fixes x==-0,y==+0 case
// Note that this trick depends on the special property that (NaN OR x) produces a NaN (although
// it might not produce the same NaN as the input).
(Min(64|32)F <t> x y) => (POR (MINS(D|S) <t> (MINS(D|S) <t> x y) x) (MINS(D|S) <t> x y))
// Floating-point max is even trickier. Punt to using min instead.
// max(x,y) == -min(-x,-y)
(Max(64|32)F <t> x y) => (Neg(64|32)F <t> (Min(64|32)F <t> (Neg(64|32)F <t> x) (Neg(64|32)F <t> y)))

(CvtBoolToUint8 ...) => (Copy ...)

// Lowering shifts
// Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
//   result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff)
(Lsh64x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
(Lsh32x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
(Lsh16x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
(Lsh8x(64|32|16|8)  <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))

(Lsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLQ x y)
(Lsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLL x y)
(Lsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLL x y)
(Lsh8x(64|32|16|8)  x y) && ssa.ShiftIsBounded(v) => (SHLL x y)

(Rsh64Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
(Rsh32Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
(Rsh16Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [16])))
(Rsh8Ux(64|32|16|8)  <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [8])))

(Rsh64Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRQ x y)
(Rsh32Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRL x y)
(Rsh16Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRW x y)
(Rsh8Ux(64|32|16|8)  x y) && ssa.ShiftIsBounded(v) => (SHRB x y)

// Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
// We implement this by setting the shift value to -1 (all ones) if the shift value is >= width.
(Rsh64x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARQ <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [64])))))
(Rsh32x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARL <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [32])))))
(Rsh16x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARW <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [16])))))
(Rsh8x(64|32|16|8)  <t> x y) && !ssa.ShiftIsBounded(v) => (SARB <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [8])))))

(Rsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARQ x y)
(Rsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARL x y)
(Rsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARW x y)
(Rsh8x(64|32|16|8) x y)  && ssa.ShiftIsBounded(v) => (SARB x y)

// Lowering integer comparisons
(Less(64|32|16|8)      x y) => (SETL  (CMP(Q|L|W|B)     x y))
(Less(64|32|16|8)U     x y) => (SETB  (CMP(Q|L|W|B)     x y))
(Leq(64|32|16|8)       x y) => (SETLE (CMP(Q|L|W|B)     x y))
(Leq(64|32|16|8)U      x y) => (SETBE (CMP(Q|L|W|B)     x y))
(Eq(Ptr|64|32|16|8|B)  x y) => (SETEQ (CMP(Q|Q|L|W|B|B) x y))
(Neq(Ptr|64|32|16|8|B) x y) => (SETNE (CMP(Q|Q|L|W|B|B) x y))

// Lowering floating point comparisons
// Note Go assembler gets UCOMISx operand order wrong, but it is right here
// and the operands are reversed when generating assembly language.
(Eq(32|64)F   x y) => (SETEQF (UCOMIS(S|D) x y))
(Neq(32|64)F  x y) => (SETNEF (UCOMIS(S|D) x y))
// Use SETGF/SETGEF with reversed operands to dodge NaN case.
(Less(32|64)F x y) => (SETGF  (UCOMIS(S|D) y x))
(Leq(32|64)F  x y) => (SETGEF (UCOMIS(S|D) y x))

// Lowering loads
(Load <t> ptr mem) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t)) => (MOVQload ptr mem)
(Load <t> ptr mem) && ssa.Is32BitInt(t) => (MOVLload ptr mem)
(Load <t> ptr mem) && ssa.Is16BitInt(t) => (MOVWload ptr mem)
(Load <t> ptr mem) && (t.IsBoolean() || ssa.Is8BitInt(t)) => (MOVBload ptr mem)
(Load <t> ptr mem) && ssa.Is32BitFloat(t) => (MOVSSload ptr mem)
(Load <t> ptr mem) && ssa.Is64BitFloat(t) => (MOVSDload ptr mem)

// Lowering stores
(Store {t} ptr val mem) && t.Size() == 8 &&  t.IsFloat() => (MOVSDstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 &&  t.IsFloat() => (MOVSSstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)

// Lowering moves
(Move [0] _ _ mem) => mem
(Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
(Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem)
(Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem)
(Move [8] dst src mem) => (MOVQstore dst (MOVQload src mem) mem)
(Move [16] dst src mem) => (MOVOstore dst (MOVOload src mem) mem)

(Move [3] dst src mem) =>
	(MOVBstore [2] dst (MOVBload [2] src mem)
		(MOVWstore dst (MOVWload src mem) mem))
(Move [5] dst src mem) =>
	(MOVBstore [4] dst (MOVBload [4] src mem)
		(MOVLstore dst (MOVLload src mem) mem))
(Move [6] dst src mem) =>
	(MOVWstore [4] dst (MOVWload [4] src mem)
		(MOVLstore dst (MOVLload src mem) mem))
(Move [7] dst src mem) =>
	(MOVLstore [3] dst (MOVLload [3] src mem)
		(MOVLstore dst (MOVLload src mem) mem))
(Move [9] dst src mem) =>
	(MOVBstore [8] dst (MOVBload [8] src mem)
		(MOVQstore dst (MOVQload src mem) mem))
(Move [10] dst src mem) =>
	(MOVWstore [8] dst (MOVWload [8] src mem)
		(MOVQstore dst (MOVQload src mem) mem))
(Move [11] dst src mem) =>
	(MOVLstore [7] dst (MOVLload [7] src mem)
		(MOVQstore dst (MOVQload src mem) mem))
(Move [12] dst src mem) =>
	(MOVLstore [8] dst (MOVLload [8] src mem)
		(MOVQstore dst (MOVQload src mem) mem))
(Move [s] dst src mem) && s >= 13 && s <= 15 =>
	(MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem)
		(MOVQstore dst (MOVQload src mem) mem))

// Copying up to 192 bytes uses straightline code.
(Move [s] dst src mem) && s > 16 && s < 192 && ssa.LogLargeCopyValue(v, s) => (LoweredMove [s] dst src mem)

// Copying up to ~1KB uses a small loop.
(Move [s] dst src mem) && s >= 192 && s <= ssa.RepMoveThreshold && ssa.LogLargeCopyValue(v, s) => (LoweredMoveLoop [s] dst src mem)

// Large copying uses REP MOVSQ.
(Move [s] dst src mem) && s > ssa.RepMoveThreshold && s%8 != 0 =>
	(Move [s-s%8]
		(OffPtr <dst.Type> dst [s%8])
		(OffPtr <src.Type> src [s%8])
		(MOVQstore dst (MOVQload src mem) mem))
(Move [s] dst src mem) && s > ssa.RepMoveThreshold && s%8 == 0 && ssa.LogLargeCopyValue(v, s) =>
	(REPMOVSQ dst src (MOVQconst [s/8]) mem)

// Lowering Zero instructions
(Zero [0] _ mem) => mem
(Zero [1] destptr mem) => (MOVBstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
(Zero [2] destptr mem) => (MOVWstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
(Zero [4] destptr mem) => (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
(Zero [8] destptr mem) => (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)

(Zero [3] destptr mem) =>
	(MOVBstoreconst [ssa.MakeValAndOff(0,2)] destptr
		(MOVWstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
(Zero [5] destptr mem) =>
	(MOVBstoreconst [ssa.MakeValAndOff(0,4)] destptr
		(MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
(Zero [6] destptr mem) =>
	(MOVWstoreconst [ssa.MakeValAndOff(0,4)] destptr
		(MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
(Zero [7] destptr mem) =>
	(MOVLstoreconst [ssa.MakeValAndOff(0,3)] destptr
		(MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))

// Zero small numbers of words directly.
(Zero [9] destptr mem) =>
	(MOVBstoreconst [ssa.MakeValAndOff(0,8)] destptr
		(MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))

(Zero [10] destptr mem) =>
	(MOVWstoreconst [ssa.MakeValAndOff(0,8)] destptr
		(MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))

(Zero [11] destptr mem) =>
	(MOVLstoreconst [ssa.MakeValAndOff(0,7)] destptr
		(MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))

(Zero [12] destptr mem) =>
	(MOVLstoreconst [ssa.MakeValAndOff(0,8)] destptr
		(MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))

(Zero [s] destptr mem) && s > 12 && s < 16 =>
	(MOVQstoreconst [ssa.MakeValAndOff(0,int32(s-8))] destptr
		(MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))

// Zeroing up to 192 bytes uses straightline code.
(Zero [s] destptr mem)	&& s >= 16 && s < 192 => (LoweredZero [s] destptr mem)

// Zeroing up to ~1KB uses a small loop.
(Zero [s] destptr mem)	&& s >= 192 && s <= ssa.RepZeroThreshold => (LoweredZeroLoop [s] destptr mem)

// Large zeroing uses REP STOSQ.
(Zero [s] destptr mem) && s > ssa.RepZeroThreshold && s%8 != 0 =>
       (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8])
               (MOVOstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
(Zero [s] destptr mem) && s > ssa.RepZeroThreshold && s%8 == 0 =>
	(REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)

// Lowering constants
(Const8   [c]) => (MOVLconst [int32(c)])
(Const16  [c]) => (MOVLconst [int32(c)])
(Const32  ...) => (MOVLconst ...)
(Const64  ...) => (MOVQconst ...)
(Const32F ...) => (MOVSSconst ...)
(Const64F ...) => (MOVSDconst ...)
(ConstNil    ) => (MOVQconst [0])
(ConstBool [c]) => (MOVLconst [ssa.B2i32(c)])

// Lowering calls
(StaticCall ...) => (CALLstatic ...)
(ClosureCall ...) => (CALLclosure ...)
(InterCall ...) => (CALLinter ...)
(TailCall ...) => (CALLtail ...)
(TailCallInter ...) => (CALLtailinter ...)

// Lowering conditional moves
// If the condition is a SETxx, we can just run a CMOV from the comparison that was
// setting the flags.
// Legend: HI=unsigned ABOVE, CS=unsigned BELOW, CC=unsigned ABOVE EQUAL, LS=unsigned BELOW EQUAL
(CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
    => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
(CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && ssa.Is32BitInt(t)
    => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
(CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && ssa.Is16BitInt(t)
    => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)

// Float min/max comparison-select idioms lower to a single instruction.
// These ops carry their semantics directly (no embedded comparison), so the
// lowering always triggers.
(Min64FSel ...) => (MINSD ...)
(Min32FSel ...) => (MINSS ...)
(Max64FSel ...) => (MAXSD ...)
(Max32FSel ...) => (MAXSS ...)

(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
    => (CMOVQNE y x (CMPQconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is32BitInt(t)
    => (CMOVLNE y x (CMPQconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is16BitInt(t)
    => (CMOVWNE y x (CMPQconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
    => (CMOVQNE y x (CMPLconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is32BitInt(t)
    => (CMOVLNE y x (CMPLconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is16BitInt(t)
    => (CMOVWNE y x (CMPLconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
    => (CMOVQNE y x (CMPWconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is32BitInt(t)
    => (CMOVLNE y x (CMPWconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is16BitInt(t)
    => (CMOVWNE y x (CMPWconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
    => (CMOVQNE y x (CMPBconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is32BitInt(t)
    => (CMOVLNE y x (CMPBconst [0] check))
(CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is16BitInt(t)
    => (CMOVWNE y x (CMPBconst [0] check))

// Absorb InvertFlags
(CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
    => (CMOVQ(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
(CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
    => (CMOVL(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
(CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
    => (CMOVW(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)

// Absorb constants generated during lower
(CMOV(QEQ|QLE|QGE|QCC|QLS|LEQ|LLE|LGE|LCC|LLS|WEQ|WLE|WGE|WCC|WLS) _ x (FlagEQ)) => x
(CMOV(QNE|QLT|QGT|QCS|QHI|LNE|LLT|LGT|LCS|LHI|WNE|WLT|WGT|WCS|WHI) y _ (FlagEQ)) => y
(CMOV(QNE|QGT|QGE|QHI|QCC|LNE|LGT|LGE|LHI|LCC|WNE|WGT|WGE|WHI|WCC) _ x (FlagGT_UGT)) => x
(CMOV(QEQ|QLE|QLT|QLS|QCS|LEQ|LLE|LLT|LLS|LCS|WEQ|WLE|WLT|WLS|WCS) y _ (FlagGT_UGT)) => y
(CMOV(QNE|QGT|QGE|QLS|QCS|LNE|LGT|LGE|LLS|LCS|WNE|WGT|WGE|WLS|WCS) _ x (FlagGT_ULT)) => x
(CMOV(QEQ|QLE|QLT|QHI|QCC|LEQ|LLE|LLT|LHI|LCC|WEQ|WLE|WLT|WHI|WCC) y _ (FlagGT_ULT)) => y
(CMOV(QNE|QLT|QLE|QCS|QLS|LNE|LLT|LLE|LCS|LLS|WNE|WLT|WLE|WCS|WLS) _ x (FlagLT_ULT)) => x
(CMOV(QEQ|QGT|QGE|QHI|QCC|LEQ|LGT|LGE|LHI|LCC|WEQ|WGT|WGE|WHI|WCC) y _ (FlagLT_ULT)) => y
(CMOV(QNE|QLT|QLE|QHI|QCC|LNE|LLT|LLE|LHI|LCC|WNE|WLT|WLE|WHI|WCC) _ x (FlagLT_UGT)) => x
(CMOV(QEQ|QGT|QGE|QCS|QLS|LEQ|LGT|LGE|LCS|LLS|WEQ|WGT|WGE|WCS|WLS) y _ (FlagLT_UGT)) => y

// Miscellaneous
(IsNonNil p) => (SETNE (TESTQ p p))
(IsInBounds idx len) => (SETB (CMPQ idx len))
(IsSliceInBounds idx len) => (SETBE (CMPQ idx len))
(NilCheck ...) => (LoweredNilCheck ...)
(GetG mem) && v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal => (LoweredGetG mem) // only lower in old ABI. in new ABI we have a G register.
(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
(GetCallerPC ...) => (LoweredGetCallerPC ...)
(GetCallerSP ...) => (LoweredGetCallerSP ...)

(HasCPUFeature {s}) => (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
(Addr {sym} base) => (LEAQ {sym} base)
(LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (LEAQ {sym} (SPanchored base mem))
(LocalAddr <t> {sym} base _)  && !t.Elem().HasPointers() => (LEAQ {sym} base)

(MOVBstore [off] {sym} ptr y:(SETL x) mem) && y.Uses == 1 => (SETLstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETLE x) mem) && y.Uses == 1 => (SETLEstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETG x) mem) && y.Uses == 1 => (SETGstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETGE x) mem) && y.Uses == 1 => (SETGEstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETEQ x) mem) && y.Uses == 1 => (SETEQstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETNE x) mem) && y.Uses == 1 => (SETNEstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETB x) mem) && y.Uses == 1 => (SETBstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETBE x) mem) && y.Uses == 1 => (SETBEstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETA x) mem) && y.Uses == 1 => (SETAstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr y:(SETAE x) mem) && y.Uses == 1 => (SETAEstore [off] {sym} ptr x mem)

// block rewrites
(If (SETL  cmp) yes no) => (LT  cmp yes no)
(If (SETLE cmp) yes no) => (LE  cmp yes no)
(If (SETG  cmp) yes no) => (GT  cmp yes no)
(If (SETGE cmp) yes no) => (GE  cmp yes no)
(If (SETEQ cmp) yes no) => (EQ  cmp yes no)
(If (SETNE cmp) yes no) => (NE  cmp yes no)
(If (SETB  cmp) yes no) => (ULT cmp yes no)
(If (SETBE cmp) yes no) => (ULE cmp yes no)
(If (SETA  cmp) yes no) => (UGT cmp yes no)
(If (SETAE cmp) yes no) => (UGE cmp yes no)
(If (SETO cmp) yes no) => (OS cmp yes no)

// Special case for floating point - LF/LEF not generated
(If (SETGF  cmp) yes no) => (UGT  cmp yes no)
(If (SETGEF cmp) yes no) => (UGE  cmp yes no)
(If (SETEQF cmp) yes no) => (EQF  cmp yes no)
(If (SETNEF cmp) yes no) => (NEF  cmp yes no)

(If cond yes no) => (NE (TESTB cond cond) yes no)

(JumpTable idx) => (JUMPTABLE {ssa.MakeJumpTableSym(b)} idx (LEAQ <typ.Uintptr> {ssa.MakeJumpTableSym(b)} (SB)))

// Atomic loads.  Other than preserving their ordering with respect to other loads, nothing special here.
(AtomicLoad8 ptr mem) => (MOVBatomicload ptr mem)
(AtomicLoad32 ptr mem) => (MOVLatomicload ptr mem)
(AtomicLoad64 ptr mem) => (MOVQatomicload ptr mem)
(AtomicLoadPtr ptr mem) => (MOVQatomicload ptr mem)

// Atomic stores.  We use XCHG to prevent the hardware reordering a subsequent load.
// TODO: most runtime uses of atomic stores don't need that property.  Use normal stores for those?
(AtomicStore8 ptr val mem) => (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
(AtomicStore32 ptr val mem) => (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
(AtomicStore64 ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
(AtomicStorePtrNoWB ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))

// Atomic exchanges.
(AtomicExchange8 ptr val mem) => (XCHGB val ptr mem)
(AtomicExchange32 ptr val mem) => (XCHGL val ptr mem)
(AtomicExchange64 ptr val mem) => (XCHGQ val ptr mem)

// Atomic adds.
(AtomicAdd32 ptr val mem) => (AddTupleFirst32 val (XADDLlock val ptr mem))
(AtomicAdd64 ptr val mem) => (AddTupleFirst64 val (XADDQlock val ptr mem))
(Select0 <t> (AddTupleFirst32 val tuple)) => (ADDL val (Select0 <t> tuple))
(Select1     (AddTupleFirst32   _ tuple)) => (Select1 tuple)
(Select0 <t> (AddTupleFirst64 val tuple)) => (ADDQ val (Select0 <t> tuple))
(Select1     (AddTupleFirst64   _ tuple)) => (Select1 tuple)

(Select1 xadd:(XADDLlock [off] {sym} val ptr mem)) && xadd.Uses == 1 && ssa.Clobber(xadd) => (ADDLlock [off] {sym} ptr val mem)
(Select1 xadd:(XADDQlock [off] {sym} val ptr mem)) && xadd.Uses == 1 && ssa.Clobber(xadd) => (ADDQlock [off] {sym} ptr val mem)
// FIXME: remove when we teach rewrite to remove dead values
(AddTupleFirst32 _ _) && v.Uses == 0 => (Invalid)
(AddTupleFirst64 _ _) && v.Uses == 0 => (Invalid)

// Atomic subtracts.
(ADDLlock [off] {sym} ptr n:(NEGL val) mem) && n.Uses == 1 => (SUBLlock [off] {sym} ptr val mem)
(ADDQlock [off] {sym} ptr n:(NEGQ val) mem) && n.Uses == 1 => (SUBQlock [off] {sym} ptr val mem)

// Atomic inc and dec.
(ADDLlock [off] {sym} ptr (MOVLconst [1]) mem) => (INCLlock [off] {sym} ptr mem)
(ADDQlock [off] {sym} ptr (MOVQconst [1]) mem) => (INCQlock [off] {sym} ptr mem)
(ADDLlock [off] {sym} ptr (MOVLconst [-1]) mem) => (DECLlock [off] {sym} ptr mem)
(ADDQlock [off] {sym} ptr (MOVQconst [-1]) mem) => (DECQlock [off] {sym} ptr mem)

// Atomic compare and swap.
(AtomicCompareAndSwap32 ptr old new_ mem) => (CMPXCHGLlock ptr old new_ mem)
(AtomicCompareAndSwap64 ptr old new_ mem) => (CMPXCHGQlock ptr old new_ mem)

// Atomic memory logical operations (old style).
(AtomicAnd8  ptr val mem) => (ANDBlock ptr val mem)
(AtomicAnd32 ptr val mem) => (ANDLlock ptr val mem)
(AtomicOr8   ptr val mem) => (ORBlock  ptr val mem)
(AtomicOr32  ptr val mem) => (ORLlock  ptr val mem)

// Atomic memory logical operations (new style).
(Atomic(And64|And32|Or64|Or32)value ptr val mem) => (LoweredAtomic(And64|And32|Or64|Or32) ptr val mem)

// Write barrier.
(WB ...) => (LoweredWB ...)

(PanicBounds ...) => (LoweredPanicBoundsRR ...)
(LoweredPanicBoundsRR [kind] x (MOVQconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {ssa.PanicBoundsC{C:c}} mem)
(LoweredPanicBoundsRR [kind] (MOVQconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {ssa.PanicBoundsC{C:c}} y mem)
(LoweredPanicBoundsRC [kind] {p} (MOVQconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:c, Cy:p.C}} mem)
(LoweredPanicBoundsCR [kind] {p} (MOVQconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:p.C, Cy:c}} mem)

// lowering rotates
(RotateLeft8  ...) => (ROLB ...)
(RotateLeft16 ...) => (ROLW ...)
(RotateLeft32 ...) => (ROLL ...)
(RotateLeft64 ...) => (ROLQ ...)

// ***************************
// Above: lowering rules
// Below: optimizations
// ***************************
// TODO: Should the optimizations be a separate pass?

// Fold boolean tests into blocks
(NE (TESTB (SETL  cmp) (SETL  cmp)) yes no) => (LT  cmp yes no)
(NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE  cmp yes no)
(NE (TESTB (SETG  cmp) (SETG  cmp)) yes no) => (GT  cmp yes no)
(NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE  cmp yes no)
(NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ  cmp yes no)
(NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE  cmp yes no)
(NE (TESTB (SETB  cmp) (SETB  cmp)) yes no) => (ULT cmp yes no)
(NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no)
(NE (TESTB (SETA  cmp) (SETA  cmp)) yes no) => (UGT cmp yes no)
(NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no)
(NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no)

// Unsigned comparisons to 0/1
(ULT (TEST(Q|L|W|B) x x) yes no) => (First no yes)
(UGE (TEST(Q|L|W|B) x x) yes no) => (First yes no)
(SETB (TEST(Q|L|W|B) x x)) => (ConstBool [false])
(SETAE (TEST(Q|L|W|B) x x)) => (ConstBool [true])

// x & 1 != 0 -> x & 1
(SETNE (TEST(B|W)const [1] x)) => (AND(L|L)const [1] x)
(SETB (BT(L|Q)const [0] x)) => (AND(L|Q)const [1] x)
// x & 1 == 0 -> (x & 1) ^ 1
(SETAE (BT(L|Q)const [0] x)) => (XORLconst [1] (ANDLconst <typ.Bool> [1] x))

// Shorten compare by rewriting x < 128 as x <= 127, which can be encoded in a single-byte immediate on x86.
(SETL c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETLE (CMP(Q|L)const [127] x))
(SETB c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETBE (CMP(Q|L)const [127] x))

// x >= 128 -> x > 127
(SETGE c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETG (CMP(Q|L)const [127] x))
(SETAE c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETA (CMP(Q|L)const [127] x))

(CMOVQLT x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVQLE x y (CMP(Q|L)const [127] z))
(CMOVLLT x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVLLE x y (CMP(Q|L)const [127] z))
(LT          c:(CMP(Q|L)const [128] z) yes no) && c.Uses == 1 => (LE (CMP(Q|L)const [127] z) yes no)
(CMOVQGE x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVQGT x y (CMP(Q|L)const [127] z))
(CMOVLGE x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVLGT x y (CMP(Q|L)const [127] z))
(GE          c:(CMP(Q|L)const [128] z) yes no) && c.Uses == 1 => (GT (CMP(Q|L)const [127] z)  yes no)

// Recognize bit tests: a&(1<<b) != 0 for b suitably bounded
// Note that BTx instructions use the carry bit, so we need to convert tests for zero flag
// into tests for carry flags.
// ULT and SETB check the carry flag; they are identical to CS and SETCS. Same, mutatis
// mutandis, for UGE and SETAE, and CC and SETCC.
((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => ((ULT|UGE) (BTL x y))
((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => ((ULT|UGE) (BTQ x y))
((NE|EQ) (TESTLconst [c] x)) && ssa.IsPowerOfTwo(uint32(c))
    => ((ULT|UGE) (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
((NE|EQ) (TESTQconst [c] x)) && ssa.IsPowerOfTwo(uint64(c))
    => ((ULT|UGE) (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
((NE|EQ) (TESTQ (MOVQconst [c]) x)) && ssa.IsPowerOfTwo(uint64(c))
    => ((ULT|UGE) (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
(SET(NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => (SET(B|AE)  (BTL x y))
(SET(NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => (SET(B|AE)  (BTQ x y))
(SET(NE|EQ) (TESTLconst [c] x)) && ssa.IsPowerOfTwo(uint32(c))
    => (SET(B|AE)  (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
(SET(NE|EQ) (TESTQconst [c] x)) && ssa.IsPowerOfTwo(uint64(c))
    => (SET(B|AE)  (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
(SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && ssa.IsPowerOfTwo(uint64(c))
    => (SET(B|AE)  (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
// SET..store variant
(SET(NE|EQ)store [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
    => (SET(B|AE)store  [off] {sym} ptr (BTL x y) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
    => (SET(B|AE)store  [off] {sym} ptr (BTQ x y) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && ssa.IsPowerOfTwo(uint32(c))
    => (SET(B|AE)store  [off] {sym} ptr (BTLconst [int8(ssa.Log32u(uint32(c)))] x) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && ssa.IsPowerOfTwo(uint64(c))
    => (SET(B|AE)store  [off] {sym} ptr (BTQconst [int8(ssa.Log32u(uint32(c)))] x) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && ssa.IsPowerOfTwo(uint64(c))
    => (SET(B|AE)store  [off] {sym} ptr (BTQconst [int8(ssa.Log64u(uint64(c)))] x) mem)

// Handle bit-testing in the form (a>>b)&1 != 0 by building the above rules
// and further combining shifts.
(BT(Q|L)const [c] (SHRQconst [d] x)) && (c+d)<64 => (BTQconst [c+d] x)
(BT(Q|L)const [c] (ADDQ x x)) && c>1  => (BT(Q|L)const [c-1] x)
(BT(Q|L)const [c] (SHLQconst [d] x)) && c>d      => (BT(Q|L)const [c-d] x)
(BT(Q|L)const [0] s:(SHRQ x y)) => (BTQ y x)
(BTLconst [c] (SHRLconst [d] x)) && (c+d)<32 => (BTLconst [c+d] x)
(BTLconst [c] (ADDL x x)) && c>1 => (BTLconst [c-1] x)
(BTLconst [c] (SHLLconst [d] x)) && c>d      => (BTLconst [c-d] x)
(BTLconst [0] s:(SHR(L|XL) x y)) => (BTL y x)

// Rewrite a & 1 != 1 into a & 1 == 0.
// Among other things, this lets us turn (a>>b)&1 != 1 into a bit test.
(SET(NE|EQ) (CMPLconst [1] s:(ANDLconst [1] _))) => (SET(EQ|NE) (CMPLconst [0] s))
(SET(NE|EQ)store [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPLconst [0] s) mem)
(SET(NE|EQ) (CMPQconst [1] s:(ANDQconst [1] _))) => (SET(EQ|NE) (CMPQconst [0] s))
(SET(NE|EQ)store [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPQconst [0] s) mem)

// Recognize bit setting (a |= 1<<b) and toggling (a ^= 1<<b)
(OR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTS(Q|L) x y)
(XOR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTC(Q|L) x y)
// Note: only convert OR/XOR to BTS/BTC if the constant wouldn't fit in
// the constant field of the OR/XOR instruction. See issue 61694.
((OR|XOR)Q (MOVQconst [c]) x) && ssa.IsPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 => (BT(S|C)Qconst [int8(ssa.Log64u(uint64(c)))] x)

// Recognize bit clearing: a &^= 1<<b
(AND(Q|L) (NOT(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y)) x) => (BTR(Q|L) x y)
(ANDN(Q|L) x (SHL(Q|L) (MOV(Q|L)const [1]) y)) => (BTR(Q|L) x y)
// Note: only convert AND to BTR if the constant wouldn't fit in
// the constant field of the AND instruction. See issue 61694.
(ANDQ (MOVQconst [c]) x) && ssa.IsPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 => (BTRQconst [int8(ssa.Log64u(uint64(^c)))] x)

// Special-case bit patterns on first/last bit.
// generic.rules changes ANDs of high-part/low-part masks into a couple of shifts,
// for instance:
//    x & 0xFFFF0000 -> (x >> 16) << 16
//    x & 0x80000000 -> (x >> 31) << 31
//
// In case the mask is just one bit (like second example above), it conflicts
// with the above rules to detect bit-testing / bit-clearing of first/last bit.
// We thus special-case them, by detecting the shift patterns.

// Special case resetting first/last bit
(ADD(L|Q) (SHR(L|Q)const [1] x) (SHR(L|Q)const [1] x))
	=> (AND(L|Q)const [-2] x)
(SHRLconst [1] (ADDL x x))
	=> (ANDLconst [0x7fffffff] x)
(SHRQconst [1] (ADDQ x x))
	=> (BTRQconst [63] x)

// Special case testing first/last bit (with double-shift generated by generic.rules)
((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) && z1==z2
    => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) && z1==z2
    => ((SETB|SETAE|ULT|UGE) (BTQconst [31] x))
(SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) && z1==z2
    => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) && z1==z2
    => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)

((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) && z1==z2
    => ((SETB|SETAE|ULT|UGE)  (BTQconst [0] x))
((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) && z1==z2
    => ((SETB|SETAE|ULT|UGE)  (BTLconst [0] x))
(SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) && z1==z2
    => (SET(B|AE)store [off] {sym} ptr (BTQconst [0] x) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) && z1==z2
    => (SET(B|AE)store [off] {sym} ptr (BTLconst [0] x) mem)

// Special-case manually testing last bit with "a>>63 != 0" (without "&1")
((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] x) z2)) && z1==z2
    => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] x) z2)) && z1==z2
    => ((SETB|SETAE|ULT|UGE) (BTLconst [31] x))
(SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) && z1==z2
    => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
(SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) && z1==z2
    => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)

// Fold combinations of bit ops on same bit. An example is math.Copysign(c,-1)
(BTSQconst [c] (BTRQconst [c] x)) => (BTSQconst [c] x)
(BTSQconst [c] (BTCQconst [c] x)) => (BTSQconst [c] x)
(BTRQconst [c] (BTSQconst [c] x)) => (BTRQconst [c] x)
(BTRQconst [c] (BTCQconst [c] x)) => (BTRQconst [c] x)

// Fold boolean negation into SETcc.
(XORLconst [1] (SETNE x)) => (SETEQ x)
(XORLconst [1] (SETEQ x)) => (SETNE x)
(XORLconst [1] (SETL  x)) => (SETGE x)
(XORLconst [1] (SETGE x)) => (SETL  x)
(XORLconst [1] (SETLE x)) => (SETG  x)
(XORLconst [1] (SETG  x)) => (SETLE x)
(XORLconst [1] (SETB  x)) => (SETAE x)
(XORLconst [1] (SETAE x)) => (SETB  x)
(XORLconst [1] (SETBE x)) => (SETA  x)
(XORLconst [1] (SETA  x)) => (SETBE x)

// Special case for floating point - LF/LEF not generated
(NE (TESTB (SETGF  cmp) (SETGF  cmp)) yes no) => (UGT  cmp yes no)
(NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE  cmp yes no)
(NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF  cmp yes no)
(NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF  cmp yes no)

// Disabled because it interferes with the pattern match above and makes worse code.
// (SETNEF x) => (ORQ (SETNE <typ.Int8> x) (SETNAN <typ.Int8> x))
// (SETEQF x) => (ANDQ (SETEQ <typ.Int8> x) (SETORD <typ.Int8> x))

// fold constants into instructions
(ADDQ x (MOVQconst <t> [c])) && ssa.Is32Bit(c) && !t.IsPtr() => (ADDQconst [int32(c)] x)
(ADDQ x (MOVLconst [c])) => (ADDQconst [c] x)
(ADDL x (MOVLconst [c])) => (ADDLconst [c] x)

(SUBQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (SUBQconst x [int32(c)])
(SUBQ (MOVQconst [c]) x) && ssa.Is32Bit(c) => (NEGQ (SUBQconst <v.Type> x [int32(c)]))
(SUBL x (MOVLconst [c])) => (SUBLconst x [c])
(SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c]))

(MULQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (MULQconst [int32(c)] x)
(MULL x (MOVLconst [c])) => (MULLconst [c] x)

(ANDQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (ANDQconst [int32(c)] x)
(ANDL x (MOVLconst [c])) => (ANDLconst [c] x)

(AND(L|Q)const [c] (AND(L|Q)const [d] x)) => (AND(L|Q)const [c & d] x)
(XOR(L|Q)const [c] (XOR(L|Q)const [d] x)) => (XOR(L|Q)const [c ^ d] x)
(OR(L|Q)const  [c] (OR(L|Q)const  [d] x)) => (OR(L|Q)const  [c | d] x)

(MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x)
(MULQconst [c] (MULQconst [d] x)) && ssa.Is32Bit(int64(c)*int64(d)) => (MULQconst [c * d] x)

(ORQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (ORQconst [int32(c)] x)
(ORQ x (MOVLconst [c])) => (ORQconst [c] x)
(ORL x (MOVLconst [c])) => (ORLconst [c] x)

(XORQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (XORQconst [int32(c)] x)
(XORL x (MOVLconst [c])) => (XORLconst [c] x)

(SHLQ x (MOV(Q|L)const [c])) => (SHLQconst [int8(c&63)] x)
(SHLL x (MOV(Q|L)const [c])) => (SHLLconst [int8(c&31)] x)

(SHRQ x (MOV(Q|L)const [c])) => (SHRQconst [int8(c&63)] x)
(SHRL x (MOV(Q|L)const [c])) => (SHRLconst [int8(c&31)] x)
(SHRW x (MOV(Q|L)const [c])) && c&31 < 16 => (SHRWconst [int8(c&31)] x)
(SHRW _ (MOV(Q|L)const [c])) && c&31 >= 16 => (MOVLconst [0])
(SHRB x (MOV(Q|L)const [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
(SHRB _ (MOV(Q|L)const [c])) && c&31 >= 8 => (MOVLconst [0])

(SARQ x (MOV(Q|L)const [c])) => (SARQconst [int8(c&63)] x)
(SARL x (MOV(Q|L)const [c])) => (SARLconst [int8(c&31)] x)
(SARW x (MOV(Q|L)const [c])) => (SARWconst [int8(min(int64(c)&31,15))] x)
(SARB x (MOV(Q|L)const [c])) => (SARBconst [int8(min(int64(c)&31,7))] x)

// Operations which don't affect the low 6/5 bits of the shift amount are NOPs.
((SHLQ|SHRQ|SARQ) x (ADDQconst [c] y)) && c & 63 == 0  => ((SHLQ|SHRQ|SARQ) x y)
((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ADDQconst [c] y))) && c & 63 == 0  => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
((SHLQ|SHRQ|SARQ) x (ANDQconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ANDQconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))

((SHLL|SHRL|SARL) x (ADDQconst [c] y)) && c & 31 == 0  => ((SHLL|SHRL|SARL) x y)
((SHLL|SHRL|SARL) x (NEGQ <t> (ADDQconst [c] y))) && c & 31 == 0  => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
((SHLL|SHRL|SARL) x (ANDQconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
((SHLL|SHRL|SARL) x (NEGQ <t> (ANDQconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))

((SHLQ|SHRQ|SARQ) x (ADDLconst [c] y)) && c & 63 == 0  => ((SHLQ|SHRQ|SARQ) x y)
((SHLQ|SHRQ|SARQ) x (NEGL <t> (ADDLconst [c] y))) && c & 63 == 0  => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
((SHLQ|SHRQ|SARQ) x (ANDLconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
((SHLQ|SHRQ|SARQ) x (NEGL <t> (ANDLconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))

((SHLL|SHRL|SARL) x (ADDLconst [c] y)) && c & 31 == 0  => ((SHLL|SHRL|SARL) x y)
((SHLL|SHRL|SARL) x (NEGL <t> (ADDLconst [c] y))) && c & 31 == 0  => ((SHLL|SHRL|SARL) x (NEGL <t> y))
((SHLL|SHRL|SARL) x (ANDLconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
((SHLL|SHRL|SARL) x (NEGL <t> (ANDLconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGL <t> y))

// rotate left negative = rotate right
(ROLQ x (NEG(Q|L) y)) => (RORQ x y)
(ROLL x (NEG(Q|L) y)) => (RORL x y)
(ROLW x (NEG(Q|L) y)) => (RORW x y)
(ROLB x (NEG(Q|L) y)) => (RORB x y)

// rotate right negative = rotate left
(RORQ x (NEG(Q|L) y)) => (ROLQ x y)
(RORL x (NEG(Q|L) y)) => (ROLL x y)
(RORW x (NEG(Q|L) y)) => (ROLW x y)
(RORB x (NEG(Q|L) y)) => (ROLB x y)

// rotate by constants
(ROLQ x (MOV(Q|L)const [c])) => (ROLQconst [int8(c&63)] x)
(ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x)
(ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x)
(ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x)

(RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x)
(RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x)
(RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x)
(RORB x (MOV(Q|L)const [c])) => (ROLBconst [int8((-c)&7) ] x)

// Constant shift simplifications
((SHLQ|SHRQ|SARQ)const      x [0]) => x
((SHLL|SHRL|SARL)const      x [0]) => x
((SHRW|SARW)const           x [0]) => x
((SHRB|SARB)const           x [0]) => x
((ROLQ|ROLL|ROLW|ROLB)const x [0]) => x

// Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
// because the x86 instructions are defined to use all 5 bits of the shift even
// for the small shifts. I don't think we'll ever generate a weird shift (e.g.
// (SHRW x (MOVLconst [24])), but just in case.

(CMPQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (CMPQconst x [int32(c)])
(CMPQ (MOVQconst [c]) x) && ssa.Is32Bit(c) => (InvertFlags (CMPQconst x [int32(c)]))
(CMPL x (MOVLconst [c])) => (CMPLconst x [c])
(CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c]))
(CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)])
(CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)]))
(CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)])
(CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)]))

// Canonicalize the order of arguments to comparisons - helps with CSE.
(CMP(Q|L|W|B) x y) && ssa.CanonLessThan(x,y) => (InvertFlags (CMP(Q|L|W|B) y x))

// Using MOVZX instead of AND is cheaper.
(AND(Q|L)const [  0xFF] x) => (MOVBQZX x)
(AND(Q|L)const [0xFFFF] x) => (MOVWQZX x)
// This rule is currently invalid because 0xFFFFFFFF is not representable by a signed int32.
// Commenting out for now, because it also can't trigger because of the is32bit guard on the
// ANDQconst lowering-rule, above, prevents 0xFFFFFFFF from matching (for the same reason)
// Using an alternate form of this rule segfaults some binaries because of
// adverse interactions with other passes.
// (ANDQconst [0xFFFFFFFF] x) => (MOVLQZX x)

// strength reduction
(MUL(Q|L)const [ 0] _) => (MOV(Q|L)const [0])
(MUL(Q|L)const [ 1] x) => x
(MULQconst [c] x) && ssa.CanMulStrengthReduce(config, int64(c)) => {ssa.MulStrengthReduce(v, x, int64(c))}
(MULLconst [c] x) && v.Type.Size() <= 4 && ssa.CanMulStrengthReduce32(config, c) => {ssa.MulStrengthReduce32(v, x, c)}

// Prefer addition when shifting left by one
(SHL(Q|L)const [1] x) => (ADD(Q|L) x x)

// combine add/shift into LEAQ/LEAL
(ADD(L|Q) x (SHL(L|Q)const [3] y)) => (LEA(L|Q)8 x y)
(ADD(L|Q) x (SHL(L|Q)const [2] y)) => (LEA(L|Q)4 x y)
(ADD(L|Q) x (ADD(L|Q) y y))        => (LEA(L|Q)2 x y)
(ADD(L|Q) x (ADD(L|Q) x y))        => (LEA(L|Q)2 y x)

// combine ADDQ/ADDQconst into LEAQ1/LEAL1
(ADD(Q|L)const [c] (ADD(Q|L) x y)) => (LEA(Q|L)1 [c] x y)
(ADD(Q|L) (ADD(Q|L)const [c] x) y) => (LEA(Q|L)1 [c] x y)
(ADD(Q|L)const [c] (ADD(Q|L) x x)) => (LEA(Q|L)1 [c] x x)

// fold ADDQ/ADDL into LEAQ/LEAL
(ADD(Q|L)const [c] (LEA(Q|L) [d] {s} x)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
(LEA(Q|L) [c] {s} (ADD(Q|L)const [d] x)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
(LEA(Q|L) [c] {s} (ADD(Q|L) x y)) && x.Op != ssaop.OpSB && y.Op != ssaop.OpSB => (LEA(Q|L)1 [c] {s} x y)
(ADD(Q|L) x (LEA(Q|L) [c] {s} y)) && x.Op != ssaop.OpSB && y.Op != ssaop.OpSB => (LEA(Q|L)1 [c] {s} x y)

// fold ADDQconst/ADDLconst into LEAQx/LEALx
(ADD(Q|L)const [c] (LEA(Q|L)1 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)1 [c+d] {s} x y)
(ADD(Q|L)const [c] (LEA(Q|L)2 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)2 [c+d] {s} x y)
(ADD(Q|L)const [c] (LEA(Q|L)4 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)4 [c+d] {s} x y)
(ADD(Q|L)const [c] (LEA(Q|L)8 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)8 [c+d] {s} x y)
(LEA(Q|L)1 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d))   && x.Op != ssaop.OpSB => (LEA(Q|L)1 [c+d] {s} x y)
(LEA(Q|L)2 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d))   && x.Op != ssaop.OpSB => (LEA(Q|L)2 [c+d] {s} x y)
(LEA(Q|L)2 [c] {s} x (ADD(Q|L)const [d] y)) && ssa.Is32Bit(int64(c)+2*int64(d)) && y.Op != ssaop.OpSB => (LEA(Q|L)2 [c+2*d] {s} x y)
(LEA(Q|L)4 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d))   && x.Op != ssaop.OpSB => (LEA(Q|L)4 [c+d] {s} x y)
(LEA(Q|L)4 [c] {s} x (ADD(Q|L)const [d] y)) && ssa.Is32Bit(int64(c)+4*int64(d)) && y.Op != ssaop.OpSB => (LEA(Q|L)4 [c+4*d] {s} x y)
(LEA(Q|L)8 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d))   && x.Op != ssaop.OpSB => (LEA(Q|L)8 [c+d] {s} x y)
(LEA(Q|L)8 [c] {s} x (ADD(Q|L)const [d] y)) && ssa.Is32Bit(int64(c)+8*int64(d)) && y.Op != ssaop.OpSB => (LEA(Q|L)8 [c+8*d] {s} x y)

// fold shifts into LEAQx/LEALx
(LEA(Q|L)1 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)2 [c] {s} x y)
(LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)4 [c] {s} x y)
(LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [3] y)) => (LEA(Q|L)8 [c] {s} x y)
(LEA(Q|L)2 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)4 [c] {s} x y)
(LEA(Q|L)2 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)8 [c] {s} x y)
(LEA(Q|L)4 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)8 [c] {s} x y)

// (x + x) << 1 -> x << 2
(LEA(Q|L)2 [0] {s} (ADD(Q|L) x x) x) && s == nil => (SHL(Q|L)const [2] x)

// (x + x) << 2 -> x << 3 and similar
(SHLQconst [c] (ADDQ x x)) && c < 63 => (SHLQconst [c+1] x)
(SHLLconst [c] (ADDL x x)) && c < 31 => (SHLLconst [c+1] x)

// reverse ordering of compare instruction
(SETL (InvertFlags x)) => (SETG x)
(SETG (InvertFlags x)) => (SETL x)
(SETB (InvertFlags x)) => (SETA x)
(SETA (InvertFlags x)) => (SETB x)
(SETLE (InvertFlags x)) => (SETGE x)
(SETGE (InvertFlags x)) => (SETLE x)
(SETBE (InvertFlags x)) => (SETAE x)
(SETAE (InvertFlags x)) => (SETBE x)
(SETEQ (InvertFlags x)) => (SETEQ x)
(SETNE (InvertFlags x)) => (SETNE x)

(SETLstore [off] {sym} ptr (InvertFlags x) mem) => (SETGstore [off] {sym} ptr x mem)
(SETGstore [off] {sym} ptr (InvertFlags x) mem) => (SETLstore [off] {sym} ptr x mem)
(SETBstore [off] {sym} ptr (InvertFlags x) mem) => (SETAstore [off] {sym} ptr x mem)
(SETAstore [off] {sym} ptr (InvertFlags x) mem) => (SETBstore [off] {sym} ptr x mem)
(SETLEstore [off] {sym} ptr (InvertFlags x) mem) => (SETGEstore [off] {sym} ptr x mem)
(SETGEstore [off] {sym} ptr (InvertFlags x) mem) => (SETLEstore [off] {sym} ptr x mem)
(SETBEstore [off] {sym} ptr (InvertFlags x) mem) => (SETAEstore [off] {sym} ptr x mem)
(SETAEstore [off] {sym} ptr (InvertFlags x) mem) => (SETBEstore [off] {sym} ptr x mem)
(SETEQstore [off] {sym} ptr (InvertFlags x) mem) => (SETEQstore [off] {sym} ptr x mem)
(SETNEstore [off] {sym} ptr (InvertFlags x) mem) => (SETNEstore [off] {sym} ptr x mem)

// sign extended loads
// Note: The combined instruction must end up in the same block
// as the original load. If not, we end up making a value with
// memory type live in two different blocks, which can lead to
// multiple memory values alive simultaneously.
// Make sure we don't combine these ops if the load has another use.
// This prevents a single load from being split into multiple loads
// which then might return different values.  See test/atomicload.go.
(MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
(MOVBQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
(MOVBQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
(MOVBQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
(MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
(MOVBQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
(MOVBQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
(MOVBQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
(MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
(MOVWQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
(MOVWQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
(MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
(MOVWQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
(MOVWQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
(MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
(MOVLQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
(MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
(MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)

// replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVBQZX x)
(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVWQZX x)
(MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVLQZX x)
(MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => x
(MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVBQSX x)
(MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVWQSX x)
(MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVLQSX x)

// Fold extensions and ANDs together.
(MOVBQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x)
(MOVWQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x)
(MOVLQZX (ANDLconst [c] x)) => (ANDLconst [c] x)
(MOVBQSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x)
(MOVWQSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x)
(MOVLQSX (ANDLconst [c] x)) && uint32(c) & 0x80000000 == 0 => (ANDLconst [c & 0x7fffffff] x)

// Don't extend before storing
(MOVLstore [off] {sym} ptr (MOVLQSX x) mem) => (MOVLstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWQSX x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr (MOVBQSX x) mem) => (MOVBstore [off] {sym} ptr x mem)
(MOVLstore [off] {sym} ptr (MOVLQZX x) mem) => (MOVLstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWQZX x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr (MOVBQZX x) mem) => (MOVBstore [off] {sym} ptr x mem)

// fold constants into memory operations
// Note that this is not always a good idea because if not all the uses of
// the ADDQconst get eliminated, we still have to compute the ADDQconst and we now
// have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one.
// Nevertheless, let's do it!
(MOV(Q|L|W|B|SS|SD|O)load  [off1] {sym} (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
    (MOV(Q|L|W|B|SS|SD|O)load  [off1+off2] {sym} ptr mem)
(MOV(Q|L|W|B|SS|SD|O)store  [off1] {sym} (ADDQconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(MOV(Q|L|W|B|SS|SD|O)store  [off1+off2] {sym} ptr val mem)
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {sym} base val mem)
((ADD|SUB|AND|OR|XOR)Qload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {sym} val base mem)
((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
(CMP(Q|L|W|B)load [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(CMP(Q|L|W|B)load [off1+off2] {sym} base val mem)
(CMP(Q|L|W|B)constload [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
	(CMP(Q|L|W|B)constload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)

((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem)
((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem)
((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
	((ADD|AND|OR|XOR)Qconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
	((ADD|AND|OR|XOR)Lconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
((ADD|AND|OR|XOR)Wconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
	((ADD|AND|OR|XOR)Wconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
((ADD|AND|OR|XOR)Bconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
	((ADD|AND|OR|XOR)Bconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {sym} base val mem)
((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)

// Fold constants into stores.
(MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validVal(c) =>
	(MOVQstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
(MOVLstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
	(MOVLstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
(MOVWstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
	(MOVWstoreconst [ssa.MakeValAndOff(int32(int16(c)),off)] {sym} ptr mem)
(MOVBstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
	(MOVBstoreconst [ssa.MakeValAndOff(int32(int8(c)),off)] {sym} ptr mem)

// Fold address offsets into constant stores.
(MOV(Q|L|W|B|O)storeconst [sc] {s} (ADDQconst [off] ptr) mem) && ssa.ValAndOff(sc).CanAdd32(off) =>
	(MOV(Q|L|W|B|O)storeconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)

// We need to fold LEAQ into the MOVx ops so that the live variable analysis knows
// what variables are being read/written by the ops.
(MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	(MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
(MOV(Q|L|W|B|SS|SD|O)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	(MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
(MOV(Q|L|W|B|O)storeconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off) =>
	(MOV(Q|L|W|B|O)storeconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
((ADD|SUB|AND|OR|XOR)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
(CMP(Q|L|W|B)load [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	(CMP(Q|L|W|B)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
(CMP(Q|L|W|B)constload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	&& ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
	(CMP(Q|L|W|B)constload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)

((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|SUB|MUL|DIV)SSload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|SUB|MUL|DIV)SDload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	&& ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|AND|OR|XOR)Qconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	&& ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|AND|OR|XOR)Lconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
((ADD|AND|OR|XOR)Wconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	&& ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|AND|OR|XOR)Wconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
((ADD|AND|OR|XOR)Bconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	&& ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|AND|OR|XOR)Bconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	&& ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)

// fold LEAQs together
(LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
      (LEAQ [off1+off2] {ssa.MergeSym(sym1,sym2)} x)

// LEAQ into LEAQ1
(LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
       (LEAQ1 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)

// LEAQ1 into LEAQ
(LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
       (LEAQ1 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)

// LEAQ into LEAQ[248]
(LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
       (LEAQ2 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
(LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
       (LEAQ4 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
(LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
       (LEAQ8 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)

// LEAQ[248] into LEAQ
(LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
      (LEAQ2 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
(LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
      (LEAQ4 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
(LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
      (LEAQ8 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)

// LEAQ[1248] into LEAQ[1248]. Only some such merges are possible.
(LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
      (LEAQ2 [off1+off2] {ssa.MergeSym(sym1, sym2)} x y)
(LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
      (LEAQ2 [off1+off2] {ssa.MergeSym(sym1, sym2)} y x)
(LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && ssa.Is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil =>
      (LEAQ4 [off1+2*off2] {sym1} x y)
(LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && ssa.Is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil =>
      (LEAQ8 [off1+4*off2] {sym1} x y)
// TODO: more?

// Lower LEAQ2/4/8 when the offset is a constant
(LEAQ2 [off] {sym} x (MOV(Q|L)const [scale])) && ssa.Is32Bit(int64(off)+int64(scale)*2) =>
	(LEAQ [off+int32(scale)*2] {sym} x)
(LEAQ4 [off] {sym} x (MOV(Q|L)const [scale])) && ssa.Is32Bit(int64(off)+int64(scale)*4) =>
	(LEAQ [off+int32(scale)*4] {sym} x)
(LEAQ8 [off] {sym} x (MOV(Q|L)const [scale])) && ssa.Is32Bit(int64(off)+int64(scale)*8) =>
	(LEAQ [off+int32(scale)*8] {sym} x)

// Absorb InvertFlags into branches.
(LT (InvertFlags cmp) yes no) => (GT cmp yes no)
(GT (InvertFlags cmp) yes no) => (LT cmp yes no)
(LE (InvertFlags cmp) yes no) => (GE cmp yes no)
(GE (InvertFlags cmp) yes no) => (LE cmp yes no)
(ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
(UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
(ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
(UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
(EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
(NE (InvertFlags cmp) yes no) => (NE cmp yes no)

// Constant comparisons.
(CMPQconst (MOVQconst [x]) [y]) && x==int64(y) => (FlagEQ)
(CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)<uint64(int64(y)) => (FlagLT_ULT)
(CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)>uint64(int64(y)) => (FlagLT_UGT)
(CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)<uint64(int64(y)) => (FlagGT_ULT)
(CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)>uint64(int64(y)) => (FlagGT_UGT)
(CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ)
(CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT)
(CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT)
(CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT)
(CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT)
(CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ)
(CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT)
(CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT)
(CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT)
(CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT)
(CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ)
(CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT)
(CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT)
(CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT)
(CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT)

// CMPQconst requires a 32 bit const, but we can still constant-fold 64 bit consts.
// In theory this applies to any of the simplifications above,
// but CMPQ is the only one I've actually seen occur.
(CMPQ (MOVQconst [x]) (MOVQconst [y])) && x==y => (FlagEQ)
(CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)<uint64(y) => (FlagLT_ULT)
(CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)>uint64(y) => (FlagLT_UGT)
(CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)<uint64(y) => (FlagGT_ULT)
(CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)>uint64(y) => (FlagGT_UGT)

// Other known comparisons.
(CMPQconst (MOVBQZX _) [c]) && 0xFF < c => (FlagLT_ULT)
(CMPQconst (MOVWQZX _) [c]) && 0xFFFF < c => (FlagLT_ULT)
(CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT)
(CMPQconst (SHRQconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) => (FlagLT_ULT)
(CMPQconst (ANDQconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
(CMPQconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
(CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
(CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT)
(CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m)  && int8(m)  < n => (FlagLT_ULT)

// TESTQ c c sets flags like CMPQ c 0.
(TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c == 0 => (FlagEQ)
(TESTLconst [c] (MOVLconst [c])) && c == 0 => (FlagEQ)
(TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c < 0  => (FlagLT_UGT)
(TESTLconst [c] (MOVLconst [c])) && c < 0  => (FlagLT_UGT)
(TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c > 0  => (FlagGT_UGT)
(TESTLconst [c] (MOVLconst [c])) && c > 0  => (FlagGT_UGT)

// TODO: DIVxU also.

// Absorb flag constants into SBB ops.
(SBBQcarrymask (FlagEQ))     => (MOVQconst [0])
(SBBQcarrymask (FlagLT_ULT)) => (MOVQconst [-1])
(SBBQcarrymask (FlagLT_UGT)) => (MOVQconst [0])
(SBBQcarrymask (FlagGT_ULT)) => (MOVQconst [-1])
(SBBQcarrymask (FlagGT_UGT)) => (MOVQconst [0])
(SBBLcarrymask (FlagEQ))     => (MOVLconst [0])
(SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1])
(SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0])
(SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1])
(SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0])

// Absorb flag constants into branches.
((EQ|LE|GE|ULE|UGE) (FlagEQ) yes no)     => (First yes no)
((NE|LT|GT|ULT|UGT) (FlagEQ) yes no)     => (First no yes)
((NE|LT|LE|ULT|ULE) (FlagLT_ULT) yes no) => (First yes no)
((EQ|GT|GE|UGT|UGE) (FlagLT_ULT) yes no) => (First no yes)
((NE|LT|LE|UGT|UGE) (FlagLT_UGT) yes no) => (First yes no)
((EQ|GT|GE|ULT|ULE) (FlagLT_UGT) yes no) => (First no yes)
((NE|GT|GE|ULT|ULE) (FlagGT_ULT) yes no) => (First yes no)
((EQ|LT|LE|UGT|UGE) (FlagGT_ULT) yes no) => (First no yes)
((NE|GT|GE|UGT|UGE) (FlagGT_UGT) yes no) => (First yes no)
((EQ|LT|LE|ULT|ULE) (FlagGT_UGT) yes no) => (First no yes)

// Absorb flag constants into SETxx ops.
((SETEQ|SETLE|SETGE|SETBE|SETAE) (FlagEQ))     => (MOVLconst [1])
((SETNE|SETL|SETG|SETB|SETA)     (FlagEQ))     => (MOVLconst [0])
((SETNE|SETL|SETLE|SETB|SETBE)   (FlagLT_ULT)) => (MOVLconst [1])
((SETEQ|SETG|SETGE|SETA|SETAE)   (FlagLT_ULT)) => (MOVLconst [0])
((SETNE|SETL|SETLE|SETA|SETAE)   (FlagLT_UGT)) => (MOVLconst [1])
((SETEQ|SETG|SETGE|SETB|SETBE)   (FlagLT_UGT)) => (MOVLconst [0])
((SETNE|SETG|SETGE|SETB|SETBE)   (FlagGT_ULT)) => (MOVLconst [1])
((SETEQ|SETL|SETLE|SETA|SETAE)   (FlagGT_ULT)) => (MOVLconst [0])
((SETNE|SETG|SETGE|SETA|SETAE)   (FlagGT_UGT)) => (MOVLconst [1])
((SETEQ|SETL|SETLE|SETB|SETBE)   (FlagGT_UGT)) => (MOVLconst [0])

(SETEQstore [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)

(SETNEstore [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)

(SETLstore  [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETLstore  [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETLstore  [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETLstore  [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETLstore  [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)

(SETLEstore [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)

(SETGstore  [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETGstore  [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETGstore  [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETGstore  [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETGstore  [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)

(SETGEstore [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)

(SETBstore  [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETBstore  [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETBstore  [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETBstore  [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETBstore  [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)

(SETBEstore [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)

(SETAstore  [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETAstore  [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETAstore  [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETAstore  [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETAstore  [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)

(SETAEstore [off] {sym} ptr (FlagEQ)     mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
(SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
(SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)

// Remove redundant *const ops
(ADD(Q|L)const [0] x) => x
(SUB(Q|L)const [0] x) => x
(AND(Q|L)const [0] _) => (MOVLconst [0])
(AND(Q|L)const [-1] x) => x
(OR(Q|L)const [0] x) => x
(OR(Q|L)const [-1] _) => (MOV(Q|L)const [-1])
(XOR(Q|L)const [0] x) => x
// TODO: since we got rid of the W/B versions, we might miss
// things like (ANDLconst [0x100] x) which were formerly
// (ANDBconst [0] x).  Probably doesn't happen very often.
// If we cared, we might do:
//  (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 -> (MOVLconst [0])

// Remove redundant ops
// Not in generic rules, because they may appear after lowering e. g. Slicemask
(NEG(Q|L) (NEG(Q|L) x)) => x
(NEG(Q|L) s:(SUB(Q|L) x y)) && s.Uses == 1 => (SUB(Q|L) y x)

// Convert constant subtracts to constant adds
(SUBQconst [c] x) && c != -(1<<31) => (ADDQconst [-c] x)
(SUBLconst [c] x) => (ADDLconst [-c] x)

// generic constant folding
// TODO: more of this
(ADDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)+d])
(ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
(ADDQconst [c] (ADDQconst [d] x)) && ssa.Is32Bit(int64(c)+int64(d)) => (ADDQconst [c+d] x)
(ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
(SUBQconst (MOVQconst [d]) [c]) => (MOVQconst [d-int64(c)])
(SUBQconst (SUBQconst x [d]) [c]) && ssa.Is32Bit(int64(-c)-int64(d)) => (ADDQconst [-c-d] x)
(SARQconst [c] (MOVQconst [d])) => (MOVQconst [d>>uint64(c)])
(SARLconst [c] (MOVQconst [d])) => (MOVQconst [int64(int32(d))>>uint64(c)])
(SARWconst [c] (MOVQconst [d])) => (MOVQconst [int64(int16(d))>>uint64(c)])
(SARBconst [c] (MOVQconst [d])) => (MOVQconst [int64(int8(d))>>uint64(c)])
(NEG(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [-c])
(MULQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)*d])
(MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d])
(ANDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)&d])
(ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d])
(ORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)|d])
(ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d])
(XORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)^d])
(XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d])
(NOT(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [^c])
(BTSQconst [c] (MOVQconst [d])) => (MOVQconst [d|(1<<uint32(c))])
(BTRQconst [c] (MOVQconst [d])) => (MOVQconst [d&^(1<<uint32(c))])
(BTCQconst [c] (MOVQconst [d])) => (MOVQconst [d^(1<<uint32(c))])

// If c or d doesn't fit into 32 bits, then we can't construct ORQconst,
// but we can still constant-fold.
// In theory this applies to any of the simplifications above,
// but ORQ is the only one I've actually seen occur.
(ORQ (MOVQconst [c]) (MOVQconst [d])) => (MOVQconst [c|d])

// generic simplifications
// TODO: more of this
(ADD(Q|L) x (NEG(Q|L) y)) => (SUB(Q|L) x y)
(SUB(Q|L) x x) => (MOVLconst [0])
(AND(Q|L) x x) => x
(OR(Q|L) x x)  => x
(XOR(Q|L) x x) => (MOVLconst [0])

(SHLLconst [d] (MOVLconst [c])) => (MOVLconst [c << uint64(d)])
(SHLQconst [d] (MOVQconst [c])) => (MOVQconst [c << uint64(d)])
(SHLQconst [d] (MOVLconst [c])) => (MOVQconst [int64(c) << uint64(d)])

// Fold NEG into ADDconst/MULconst. Take care to keep c in 32 bit range.
(NEGQ (ADDQconst [c] (NEGQ x))) && c != -(1<<31) => (ADDQconst [-c] x)
(MULQconst [c] (NEGQ x)) && c != -(1<<31) => (MULQconst [-c] x)

// checking AND against 0.
(CMP(Q|L|W|B)const a:(AND(Q|L|L|L) x y) [0]) && a.Uses == 1 => (TEST(Q|L|W|B) x y)
(CMPQconst a:(ANDQconst [c] x) [0]) && a.Uses == 1 => (TESTQconst [c] x)
(CMPLconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTLconst [c] x)
(CMPWconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTWconst [int16(c)] x)
(CMPBconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTBconst [int8(c)] x)

// Convert TESTx to TESTxconst if possible.
(TESTQ (MOVQconst [c]) x) && ssa.Is32Bit(c) => (TESTQconst [int32(c)] x)
(TESTL (MOVLconst [c]) x) => (TESTLconst [c] x)
(TESTW (MOVLconst [c]) x) => (TESTWconst [int16(c)] x)
(TESTB (MOVLconst [c]) x) => (TESTBconst [int8(c)] x)

// TEST %reg,%reg is shorter than CMP
(CMP(Q|L|W|B)const x [0]) => (TEST(Q|L|W|B) x x)
(TESTQconst [-1] x) && x.Op != ssaop.OpAMD64MOVQconst => (TESTQ x x)
(TESTLconst [-1] x) && x.Op != ssaop.OpAMD64MOVLconst => (TESTL x x)
(TESTWconst [-1] x) && x.Op != ssaop.OpAMD64MOVLconst => (TESTW x x)
(TESTBconst [-1] x) && x.Op != ssaop.OpAMD64MOVLconst => (TESTB x x)

// Convert LEAQ1 back to ADDQ if we can
(LEAQ1 [0] x y) && v.Aux == nil => (ADDQ x y)

(MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem))
  && x.Uses == 1
  && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
  && a.Val() == 0
  && c.Val() == 0
  && ssa.SetPos(v, x.Pos)
  && ssa.Clobber(x)
  => (MOVOstoreconst [ssa.MakeValAndOff(0,a.Off())] {s} p0 mem)
(MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem))
  && x.Uses == 1
  && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
  && a.Val() == 0
  && c.Val() == 0
  && ssa.SetPos(v, x.Pos)
  && ssa.Clobber(x)
  => (MOVOstoreconst [ssa.MakeValAndOff(0,a.Off())] {s} p0 mem)

// Merge load and op
// TODO: add indexed variants?
((ADD|SUB|AND|OR|XOR)Q x l:(MOVQload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|AND|OR|XOR)Qload x [off] {sym} ptr mem)
((ADD|SUB|AND|OR|XOR)L x l:(MOVLload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|AND|OR|XOR)Lload x [off] {sym} ptr mem)
((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem)
((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem)
(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && ssa.Clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
(MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l) =>
	((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
(MOVQstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Qload x [off] {sym} ptr mem) mem) && y.Uses==1 && ssa.Clobber(y) => ((ADD|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
(MOVQstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)Q l:(MOVQload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l) =>
	((ADD|SUB|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
(MOVQstore {sym} [off] ptr x:(BT(S|R|C)Qconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) && x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l) =>
	(BT(S|R|C)Qconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)

// Merge ADDQconst and LEAQ into atomic loads.
(MOV(Q|L|B)atomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(MOV(Q|L|B)atomicload [off1+off2] {sym} ptr mem)
(MOV(Q|L|B)atomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
	(MOV(Q|L|B)atomicload [off1+off2] {ssa.MergeSym(sym1, sym2)} ptr mem)

// Merge ADDQconst and LEAQ into atomic stores.
(XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(XCHGQ [off1+off2] {sym} val ptr mem)
(XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB =>
	(XCHGQ [off1+off2] {ssa.MergeSym(sym1,sym2)} val ptr mem)
(XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(XCHGL [off1+off2] {sym} val ptr mem)
(XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB =>
	(XCHGL [off1+off2] {ssa.MergeSym(sym1,sym2)} val ptr mem)

// Merge ADDQconst into atomic adds.
// TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
(XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(XADDQlock [off1+off2] {sym} val ptr mem)
(XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(XADDLlock [off1+off2] {sym} val ptr mem)

// Merge ADDQconst into atomic compare and swaps.
// TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
(CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
(CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
	(CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)

// We don't need the conditional move if we know the arg of BSF is not zero.
(CMOVQEQ x _ (Select1 (BS(F|R)Q (ORQconst [c] _)))) && c != 0 => x
// Extension is unnecessary for trailing zeros.
(BSFQ (ORQconst <t> [1<<8] (MOVBQZX x))) => (BSFQ (ORQconst <t> [1<<8] x))
(BSFQ (ORQconst <t> [1<<16] (MOVWQZX x))) => (BSFQ (ORQconst <t> [1<<16] x))

// Redundant sign/zero extensions
// Note: see issue 21963. We have to make sure we use the right type on
// the resulting extension (the outer type, not the inner type).
(MOVLQSX (MOVLQSX x)) => (MOVLQSX x)
(MOVLQSX (MOVWQSX x)) => (MOVWQSX x)
(MOVLQSX (MOVBQSX x)) => (MOVBQSX x)
(MOVWQSX (MOVWQSX x)) => (MOVWQSX x)
(MOVWQSX (MOVBQSX x)) => (MOVBQSX x)
(MOVBQSX (MOVBQSX x)) => (MOVBQSX x)
(MOVLQZX (MOVLQZX x)) => (MOVLQZX x)
(MOVLQZX (MOVWQZX x)) => (MOVWQZX x)
(MOVLQZX (MOVBQZX x)) => (MOVBQZX x)
(MOVWQZX (MOVWQZX x)) => (MOVWQZX x)
(MOVWQZX (MOVBQZX x)) => (MOVBQZX x)
(MOVBQZX (MOVBQZX x)) => (MOVBQZX x)

(MOVQstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Qconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
	&& ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a) =>
	((ADD|AND|OR|XOR)Qconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
(MOVLstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
	&& ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a) =>
	((ADD|AND|OR|XOR)Lconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
// Sub-word read-modify-write. The narrow store keeps only the low 8/16 bits of
// the 32-bit result, so ADDB/ADDW etc. with the same constant is equivalent.
// The constant is restricted to an 8-bit immediate: it keeps every form we emit
// encodable as imm8 (or INC/DEC), which also avoids the 16-bit immediates that
// cause length-changing-prefix stalls.
(MOVWstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVWload [off] {sym} ptr2 mem)) mem)
	&& ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a) =>
	((ADD|AND|OR|XOR)Wconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
(MOVBstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVBload [off] {sym} ptr2 mem)) mem)
	&& ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a) =>
	((ADD|AND|OR|XOR)Bconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)

// float <-> int register moves, with no conversion.
// These come up when compiling math.{Float{32,64}bits,Float{32,64}frombits}.
(MOVQload  [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) => (MOVQf2i val)
(MOVLload  [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) => (MOVLf2i val)
(MOVSDload [off] {sym} ptr (MOVQstore  [off] {sym} ptr val _)) => (MOVQi2f val)
(MOVSSload [off] {sym} ptr (MOVLstore  [off] {sym} ptr val _)) => (MOVLi2f val)

// Other load-like ops.
(ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ADDQ x (MOVQf2i y))
(ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ADDL x (MOVLf2i y))
(SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (SUBQ x (MOVQf2i y))
(SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (SUBL x (MOVLf2i y))
(ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ANDQ x (MOVQf2i y))
(ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ANDL x (MOVLf2i y))
( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => ( ORQ x (MOVQf2i y))
( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => ( ORL x (MOVLf2i y))
(XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (XORQ x (MOVQf2i y))
(XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (XORL x (MOVLf2i y))

(ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (ADDSD x (MOVQi2f y))
(ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (ADDSS x (MOVLi2f y))
(SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (SUBSD x (MOVQi2f y))
(SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (SUBSS x (MOVLi2f y))
(MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (MULSD x (MOVQi2f y))
(MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (MULSS x (MOVLi2f y))

// Detect FMA
(ADDS(S|D) (MULS(S|D) x y) z) && buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v) => (VFMADD231S(S|D) z x y)
(SUBS(S|D) (MULS(S|D) x y) z) && buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v) => (VFMSUB231S(S|D) z x y)
(SUBS(S|D) x (MULS(S|D) y z)) && buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v) => (VFNMADD231S(S|D) x y z)

// Redirect stores to use the other register set.
(MOVQstore  [off] {sym} ptr (MOVQf2i val) mem) => (MOVSDstore [off] {sym} ptr val mem)
(MOVLstore  [off] {sym} ptr (MOVLf2i val) mem) => (MOVSSstore [off] {sym} ptr val mem)
(MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) => (MOVQstore  [off] {sym} ptr val mem)
(MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) => (MOVLstore  [off] {sym} ptr val mem)

(MOVSDstore [off] {sym} ptr (MOVSDconst [f]) mem) && f == f => (MOVQstore [off] {sym} ptr (MOVQconst [int64(math.Float64bits(f))]) mem)
(MOVSSstore [off] {sym} ptr (MOVSSconst [f]) mem) && f == f => (MOVLstore [off] {sym} ptr (MOVLconst [int32(math.Float32bits(f))]) mem)

// Load args directly into the register class where it will be used.
// We do this by just modifying the type of the Arg.
(MOVQf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
(MOVLf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
(MOVQi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
(MOVLi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})

// LEAQ is rematerializeable, so this helps to avoid register spill.
// See issue 22947 for details
(ADD(Q|L)const [off] x:(SP)) => (LEA(Q|L) [off] x)

// HMULx is commutative, but its first argument must go in AX.
// If possible, put a rematerializeable value in the first argument slot,
// to reduce the odds that another value will be have to spilled
// specifically to free up AX.
(HMUL(Q|L)  x y) && !x.Rematerializeable() && y.Rematerializeable() => (HMUL(Q|L)  y x)
(HMUL(Q|L)U x y) && !x.Rematerializeable() && y.Rematerializeable() => (HMUL(Q|L)U y x)

// Fold loads into compares
// Note: these may be undone by the flagalloc pass.
(CMP(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) x) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (CMP(Q|L|W|B)load {sym} [off] ptr x mem)
(CMP(Q|L|W|B) x l:(MOV(Q|L|W|B)load {sym} [off] ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (InvertFlags (CMP(Q|L|W|B)load {sym} [off] ptr x mem))

(CMP(Q|L)const l:(MOV(Q|L)load {sym} [off] ptr mem) [c])
	&& l.Uses == 1
	&& ssa.Clobber(l) =>
@l.Block (CMP(Q|L)constload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
(CMP(W|B)const l:(MOV(W|B)load {sym} [off] ptr mem) [c])
	&& l.Uses == 1
	&& ssa.Clobber(l) =>
@l.Block (CMP(W|B)constload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)

(CMPQload {sym} [off] ptr (MOVQconst [c]) mem) && validVal(c) => (CMPQconstload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
(CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
(CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [ssa.MakeValAndOff(int32(int16(c)),off)] ptr mem)
(CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [ssa.MakeValAndOff(int32(int8(c)),off)] ptr mem)

(TEST(Q|L|W|B)  l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) l2)
        && l == l2
	&& l.Uses == 2
	&& ssa.Clobber(l) =>
  @l.Block (CMP(Q|L|W|B)constload {sym} [ssa.MakeValAndOff(0, off)] ptr mem)

// Convert ANDload to MOVload when we can do the AND in a containing TEST op.
// Only do when it's within the same block, so we don't have flags live across basic block boundaries.
// See issue 44228.
(TEST(Q|L) a:(AND(Q|L)load [off] {sym} x ptr mem) a) && a.Uses == 2 && a.Block == v.Block && ssa.Clobber(a) => (TEST(Q|L) (MOV(Q|L)load <a.Type> [off] {sym} ptr mem) x)

(MOVBload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVLconst [int32(ssa.Read8(sym, int64(off)))])
(MOVWload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVLconst [int32(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
(MOVLload <t> [off] {sym} (SB) _) && ssa.SymIsRO(sym) && ssa.Is32BitInt(t) => (MOVLconst [int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
(MOVLload <t> [off] {sym} (SB) _) && ssa.SymIsRO(sym) && ssa.Is64BitInt(t) => (MOVQconst [int64(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
(MOVQload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(ssa.Read64(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
(MOVBQSXload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(int8(ssa.Read8(sym, int64(off))))])
(MOVWQSXload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(int16(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
(MOVLQSXload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])


(MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) && ssa.SymIsRO(srcSym) =>
  (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(ssa.Read64(srcSym, int64(srcOff)+8, config.Ctxt.Arch.ByteOrder))])
    (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(ssa.Read64(srcSym, int64(srcOff), config.Ctxt.Arch.ByteOrder))]) mem))

// Arch-specific inlining for small or disjoint runtime.memmove
// Match post-lowering calls, memory version.
(SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
	&& sc.Val64() >= 0
	&& ssa.IsSameCall(sym, "runtime.memmove")
	&& s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
	&& ssa.IsInlinableMemmove(dst, src, sc.Val64(), config)
	&& ssa.Clobber(s1, s2, s3, call)
	=> (Move [sc.Val64()] dst src mem)

// Match post-lowering calls, register version.
(SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
	&& sz >= 0
	&& ssa.IsSameCall(sym, "runtime.memmove")
	&& call.Uses == 1
	&& ssa.IsInlinableMemmove(dst, src, sz, config)
	&& ssa.Clobber(call)
	=> (Move [sz] dst src mem)

// Prefetch instructions
(PrefetchCache ...)   => (PrefetchT0 ...)
(PrefetchCacheStreamed ...) => (PrefetchNTA ...)

// CPUID feature: BMI1.
(AND(Q|L) x (NOT(Q|L) y))               && buildcfg.GOAMD64 >= 3 => (ANDN(Q|L) x y)
(AND(Q|L) x (NEG(Q|L) x))               && buildcfg.GOAMD64 >= 3 => (BLSI(Q|L) x)
(XOR(Q|L) x (ADD(Q|L)const [-1] x))     && buildcfg.GOAMD64 >= 3 => (BLSMSK(Q|L) x)
(AND(Q|L) <t> x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (Select0 <t> (BLSR(Q|L) x))
// eliminate TEST instruction in classical "isPowerOfTwo" check
(SETEQ       (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s))        => (SETEQ       (Select1 <types.TypeFlags> blsr))
(CMOVQEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s))        => (CMOVQEQ x y (Select1 <types.TypeFlags> blsr))
(CMOVLEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s))        => (CMOVLEQ x y (Select1 <types.TypeFlags> blsr))
(EQ          (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (EQ          (Select1 <types.TypeFlags> blsr) yes no)
(SETNE       (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s))        => (SETNE       (Select1 <types.TypeFlags> blsr))
(CMOVQNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s))        => (CMOVQNE x y (Select1 <types.TypeFlags> blsr))
(CMOVLNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s))        => (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
(NE          (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (NE          (Select1 <types.TypeFlags> blsr) yes no)

(BSWAP(Q|L) (BSWAP(Q|L) p)) => p

// CPUID feature: MOVBE.
(MOV(Q|L)store   [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBE(Q|L)store [i] {s} p w mem)
(MOVBE(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1                          => (MOV(Q|L)store   [i] {s} p w mem)
(BSWAP(Q|L) x:(MOV(Q|L)load   [i] {s} p mem))  && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => @x.Block (MOVBE(Q|L)load [i] {s} p mem)
(BSWAP(Q|L) x:(MOVBE(Q|L)load [i] {s} p mem))  && x.Uses == 1                          => @x.Block (MOV(Q|L)load   [i] {s} p mem)
(MOVWstore [i] {s} p x:(ROLWconst [8] w) mem)   && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBEWstore [i] {s} p w mem)
(MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 => (MOVWstore [i] {s} p w mem)

(SAR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (SARX(Q|L)load [off] {sym} ptr x mem)
(SHL(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (SHLX(Q|L)load [off] {sym} ptr x mem)
(SHR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (SHRX(Q|L)load [off] {sym} ptr x mem)

((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVQconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
((SHL|SHR|SAR)XLload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Lconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))

// Convert atomic logical operations to easier ones if we don't use the result.
(Select1 a:(LoweredAtomic(And64|And32|Or64|Or32) ptr val mem)) && a.Uses == 1 && ssa.Clobber(a) => ((ANDQ|ANDL|ORQ|ORL)lock ptr val mem)

// If we are checking the results of an add, use the flags directly from the add.
// Note that this only works for EQ/NE. ADD sets the CF/OF flags differently
// than TEST sets them.
// Note also that a.Args[0] here refers to the post-flagify'd value.
((EQ|NE) t:(TESTQ a:(ADDQconst [c] x) a)) && t.Uses == 1 && flagify(a) => ((EQ|NE) (Select1 <types.TypeFlags> a.Args[0]))
((EQ|NE) t:(TESTL a:(ADDLconst [c] x) a)) && t.Uses == 1 && flagify(a) => ((EQ|NE) (Select1 <types.TypeFlags> a.Args[0]))

// If we don't use the flags any more, just use the standard op.
(Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x)

// SIMD lowering rules

// Mask conversions
// integers to masks
(Cvt16toMask8x16 <t> x) => (VPMOVMToVec8x16 <types.TypeVec128> (KMOVWk <t> x))
(Cvt32toMask8x32 <t> x) => (VPMOVMToVec8x32 <types.TypeVec256> (KMOVDk <t> x))
(Cvt64toMask8x64 <t> x) => (VPMOVMToVec8x64 <types.TypeVec512> (KMOVQk <t> x))

(Cvt8toMask16x8 <t> x) => (VPMOVMToVec16x8 <types.TypeVec128> (KMOVBk <t> x))
(Cvt16toMask16x16 <t> x) => (VPMOVMToVec16x16 <types.TypeVec256> (KMOVWk <t> x))
(Cvt32toMask16x32 <t> x) => (VPMOVMToVec16x32 <types.TypeVec512> (KMOVDk <t> x))

(Cvt8toMask32x4 <t> x) => (VPMOVMToVec32x4 <types.TypeVec128> (KMOVBk <t> x))
(Cvt8toMask32x8 <t> x) => (VPMOVMToVec32x8 <types.TypeVec256> (KMOVBk <t> x))
(Cvt16toMask32x16 <t> x) => (VPMOVMToVec32x16 <types.TypeVec512> (KMOVWk <t> x))

(Cvt8toMask64x2 <t> x) => (VPMOVMToVec64x2 <types.TypeVec128> (KMOVBk <t> x))
(Cvt8toMask64x4 <t> x) => (VPMOVMToVec64x4 <types.TypeVec256> (KMOVBk <t> x))
(Cvt8toMask64x8 <t> x) => (VPMOVMToVec64x8 <types.TypeVec512> (KMOVBk <t> x))

// masks to integers
(CvtMask8x16to16 ...) => (VPMOVMSKB128 ...)
(CvtMask8x32to32 ...) => (VPMOVMSKB256 ...)
(CvtMask8x64to64 x) => (KMOVQi (VPMOVVec8x64ToM <types.TypeMask> x))

(CvtMask16x8to8 x) => (KMOVBi (VPMOVVec16x8ToM <types.TypeMask> x))
(CvtMask16x16to16 x) => (KMOVWi (VPMOVVec16x16ToM <types.TypeMask> x))
(CvtMask16x32to32 x) => (KMOVDi (VPMOVVec16x32ToM <types.TypeMask> x))

(CvtMask32x4to8 ...) => (VMOVMSKPS128 ...)
(CvtMask32x8to8 ...) => (VMOVMSKPS256 ...)
(CvtMask32x16to16 x) => (KMOVWi (VPMOVVec32x16ToM <types.TypeMask> x))

(CvtMask64x2to8 ...) => (VMOVMSKPD128 ...)
(CvtMask64x4to8 ...) => (VMOVMSKPD256 ...)
(CvtMask64x8to8 x) => (KMOVBi (VPMOVVec64x8ToM <types.TypeMask> x))

// optimizations
(MOVBstore [off] {sym} ptr (KMOVBi mask) mem) => (KMOVBstore [off] {sym} ptr mask mem)
(MOVWstore [off] {sym} ptr (KMOVWi mask) mem) => (KMOVWstore [off] {sym} ptr mask mem)
(MOVLstore [off] {sym} ptr (KMOVDi mask) mem) => (KMOVDstore [off] {sym} ptr mask mem)
(MOVQstore [off] {sym} ptr (KMOVQi mask) mem) => (KMOVQstore [off] {sym} ptr mask mem)

(KMOVBk l:(MOVBload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVBload [off] {sym} ptr mem)
(KMOVWk l:(MOVWload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVWload [off] {sym} ptr mem)
(KMOVDk l:(MOVLload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVDload [off] {sym} ptr mem)
(KMOVQk l:(MOVQload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVQload [off] {sym} ptr mem)

// SIMD vector loads and stores
(Load <t> ptr mem) && t.Size() == 16 => (VMOVDQUload128 ptr mem)
(Store {t} ptr val mem) && t.Size() == 16 => (VMOVDQUstore128 ptr val mem)

(Load <t> ptr mem) && t.Size() == 32 => (VMOVDQUload256 ptr mem)
(Store {t} ptr val mem) && t.Size() == 32 => (VMOVDQUstore256 ptr val mem)

(Load <t> ptr mem) && t.Size() == 64 => (VMOVDQUload512 ptr mem)
(Store {t} ptr val mem) && t.Size() == 64 => (VMOVDQUstore512 ptr val mem)

// SIMD vector integer-vector-masked loads and stores.
(LoadMasked32 <t> ptr mask mem) && t.Size() == 16 => (VPMASK32load128 ptr mask mem)
(LoadMasked32 <t> ptr mask mem) && t.Size() == 32 => (VPMASK32load256 ptr mask mem)
(LoadMasked64 <t> ptr mask mem) && t.Size() == 16 => (VPMASK64load128 ptr mask mem)
(LoadMasked64 <t> ptr mask mem) && t.Size() == 32 => (VPMASK64load256 ptr mask mem)

(StoreMasked32 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK32store128 ptr mask val mem)
(StoreMasked32 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK32store256 ptr mask val mem)
(StoreMasked64 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK64store128 ptr mask val mem)
(StoreMasked64 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK64store256 ptr mask val mem)

// Misc
(IsZeroVec x) => (SETEQ (VPTEST x x))

(IsNaNFloat32x4  x) => (VCMPPS128 [3] x x)
(IsNaNFloat32x8  x) => (VCMPPS256 [3] x x)
(IsNaNFloat32x16 x) => (VPMOVMToVec32x16 (VCMPPS512 [3] x x))
(IsNaNFloat64x2  x) => (VCMPPD128 [3] x x)
(IsNaNFloat64x4  x) => (VCMPPD256 [3] x x)
(IsNaNFloat64x8  x) => (VPMOVMToVec64x8 (VCMPPD512 [3] x x))

// SIMD vector K-masked loads and stores

(LoadMasked64 <t> ptr mask mem) && t.Size() == 64 => (VPMASK64load512 ptr (VPMOVVec64x8ToM  <types.TypeMask> mask) mem)
(LoadMasked32 <t> ptr mask mem) && t.Size() == 64 => (VPMASK32load512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) mem)
(LoadMasked16 <t> ptr mask mem) && t.Size() == 64 => (VPMASK16load512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) mem)
(LoadMasked8  <t> ptr mask mem) && t.Size() == 64 => (VPMASK8load512  ptr (VPMOVVec8x64ToM  <types.TypeMask> mask) mem)

(StoreMasked64 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK64store512 ptr (VPMOVVec64x8ToM  <types.TypeMask> mask) val mem)
(StoreMasked32 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK32store512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) val mem)
(StoreMasked16 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK16store512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) val mem)
(StoreMasked8  {t} ptr mask val mem) && t.Size() == 64 => (VPMASK8store512  ptr (VPMOVVec8x64ToM  <types.TypeMask> mask) val mem)

(ZeroSIMD <t>) && t.Size() == 16 => (Zero128 <t>)
(ZeroSIMD <t>) && t.Size() == 32 => (Zero256 <t>)
(ZeroSIMD <t>) && t.Size() == 64 => (Zero512 <t>)

// optimize x.IsNaN().Or(y.IsNaN())
// do these before the mask rewrites
(VPOR128 (VCMPP(S|D)128 [3] x x) (VCMPP(S|D)128 [3] y y)) => (VCMPP(S|D)128 [3] x y)
(VPOR256 (VCMPP(S|D)256 [3] x x) (VCMPP(S|D)256 [3] y y)) => (VCMPP(S|D)256 [3] x y)
(VPORD512 (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) (VPMOVMToVec32x16 (VCMPPS512 [3] y y))) =>
	(VPMOVMToVec32x16 (VCMPPS512 [3] x y))
(VPORD512 (VPMOVMToVec64x8  (VCMPPD512 [3] x x)) (VPMOVMToVec64x8  (VCMPPD512 [3] y y))) =>
	(VPMOVMToVec64x8  (VCMPPD512 [3] x y))

// Include these rules because you never know about rewrite order
(KANDB (VCMPPD512 [3] x x) (VCMPPD512 [3] y y)) => (VCMPPD512 [3] x x) // 512 = 64x8 -> KANDB
(KANDW (VCMPPS512 [3] x x) (VCMPPS512 [3] y y)) => (VCMPPS512 [3] x y) // 512 = 32x16 -> KANDW

// These larger simplifying rules must come before the smaller simplifying rules that might break them).
// Rewrite rules for binary logical mask operations that apply to 8-bit elements (B, for bytes) of 128, 256, and 512-bit vectors
(VPAND128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x16 (KANDW x y))
(VPAND256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x32 (KANDD x y))
(VPANDD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x64 (KANDQ x y))

(VPOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x16 (KORW x y))
(VPOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x32 (KORD x y))
(VPORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x64 (KORQ x y))

(VPXOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x16 (KXORW x y))
(VPXOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x32 (KXORD x y))
(VPXORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x64 (KXORQ x y))

// Rewrite rules for binary logical mask operations that apply to 16-bit elements (W, for words) of 128, 256, and 512-bit vectors
(VPAND128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x8 (KANDB x y))
(VPAND256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x16 (KANDW x y))
(VPANDD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x32 (KANDD x y))

(VPOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x8 (KORB x y))
(VPOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x16 (KORW x y))
(VPORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x32 (KORD x y))

(VPXOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x8 (KXORB x y))
(VPXOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x16 (KXORW x y))
(VPXORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x32 (KXORD x y))

// Rewrite rules for binary logical mask operations that apply to 32-bit elements (D, for doublewords) of 128, 256, and 512-bit vectors
(VPAND128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x4 (KANDB x y))
(VPAND256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x8 (KANDB x y))
(VPANDD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x16 (KANDW x y))

(VPOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x4 (KORB x y))
(VPOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x8 (KORB x y))
(VPORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x16 (KORW x y))

(VPXOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x4 (KXORB x y))
(VPXOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x8 (KXORB x y))
(VPXORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x16 (KXORW x y))

// Rewrite rules for binary logical mask operations that apply to 64-bit elements (Q, for quadwords) of 128, 256, and 512-bit vectors
(VPAND128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x2 (KANDB x y))
(VPAND256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x4 (KANDB x y))
(VPANDD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x8 (KANDB x y))

(VPOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x2 (KORB x y))
(VPOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x4 (KORB x y))
(VPORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x8 (KORB x y))

(VPXOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x2 (KXORB x y))
(VPXOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x4 (KXORB x y))
(VPXORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x8 (KXORB x y))

(VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) => x
(VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) => x
(VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) => x

(VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) => x
(VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) => x
(VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) => x

(VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) => x
(VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) => x
(VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) => x

(VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) => x
(VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) => x
(VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) => x

(VPANDQ512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k)
(VPANDQ512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k)
(VPANDQ512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k)
(VPANDQ512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k)
(VPANDD512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k)
(VPANDD512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k)
(VPANDD512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k)
(VPANDD512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k)

(VPAND128 x (VPMOVMToVec8x16 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU8Masked128 x k)
(VPAND128 x (VPMOVMToVec16x8 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU16Masked128 x k)
(VPAND128 x (VPMOVMToVec32x4 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU32Masked128 x k)
(VPAND128 x (VPMOVMToVec64x2 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU64Masked128 x k)

(VPAND256 x (VPMOVMToVec8x32 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU8Masked256 x k)
(VPAND256 x (VPMOVMToVec16x16 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU16Masked256 x k)
(VPAND256 x (VPMOVMToVec32x8 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU32Masked256 x k)
(VPAND256 x (VPMOVMToVec64x4 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU64Masked256 x k)

// Insert to zero of 32/64 bit floats and ints to a zero is just MOVS[SD]
(VPINSRQ128 [0] (Zero128 <t>) y) && y.Type.IsFloat() => (VMOVSDf2v <types.TypeVec128> y)
(VPINSRD128 [0] (Zero128 <t>) y) && y.Type.IsFloat() => (VMOVSSf2v <types.TypeVec128> y)
(VPINSRQ128 [0] (Zero128 <t>) y) && !y.Type.IsFloat() => (VMOVQ <types.TypeVec128> y)
(VPINSRD128 [0] (Zero128 <t>) y) && !y.Type.IsFloat() => (VMOVD <types.TypeVec128> y)

// These rewrites can skip zero-extending the 8/16-bit inputs because they are
// only used as the input to a broadcast; the potentially "bad" bits are ignored
(VPBROADCASTB(128|256|512) x:(VPINSRB128 [0] (Zero128    <t>) y)) && x.Uses == 1 =>
	(VPBROADCASTB(128|256|512) (VMOVQ <types.TypeVec128> y))
(VPBROADCASTW(128|256|512) x:(VPINSRW128 [0] (Zero128    <t>) y)) && x.Uses == 1 =>
	(VPBROADCASTW(128|256|512)   (VMOVQ <types.TypeVec128> y))

(VMOVQ x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVQload <v.Type> [off] {sym} ptr mem)
(VMOVD x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVDload <v.Type> [off] {sym} ptr mem)

(VMOVSDf2v x:(MOVSDload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVSDload <v.Type> [off] {sym} ptr mem)
(VMOVSSf2v x:(MOVSSload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVSSload <v.Type> [off] {sym} ptr mem)

(VMOVSDf2v x:(MOVSDconst [c] )) => (VMOVSDconst [c] )
(VMOVSSf2v x:(MOVSSconst [c] )) => (VMOVSSconst [c] )

(VMOVDQUload(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) => (VMOVDQUload(128|256|512) [off1+off2] {sym} ptr mem)
(VMOVDQUstore(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) => (VMOVDQUstore(128|256|512) [off1+off2] {sym} ptr val mem)
(VMOVDQUload(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) => (VMOVDQUload(128|256|512) [off1+off2] {ssa.MergeSym(sym1, sym2)} base mem)
(VMOVDQUstore(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) => (VMOVDQUstore(128|256|512) [off1+off2] {ssa.MergeSym(sym1, sym2)} base val mem)

// Multiplication of numbers that are the power of 2 can be converted to left shift log(x)
(VPMULLQ128 x (VPBROADCASTQ128 (VMOVQ (MOVQconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLQ128const [uint8(ssa.Log64(c))] x)
(VPMULLQ256 x (VPBROADCASTQ256 (VMOVQ (MOVQconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLQ256const [uint8(ssa.Log64(c))] x)
(VPMULLQ512 x (VPBROADCASTQ512 (VMOVQ (MOVQconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLQ512const [uint8(ssa.Log64(c))] x)

(VPMULLD128 x (VPBROADCASTD128 (VMOVD (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLD128const [uint8(ssa.Log32(int32(c)))] x)
(VPMULLD256 x (VPBROADCASTD256 (VMOVD (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLD256const [uint8(ssa.Log32(int32(c)))] x)
(VPMULLD512 x (VPBROADCASTD512 (VMOVD (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLD512const [uint8(ssa.Log32(int32(c)))] x)

(VPMULLW128 x (VPBROADCASTW128 (VMOVQ (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLW128const [uint8(ssa.Log16(int16(c)))] x) // use VMOVQ because VMOVW doesn't exist
(VPMULLW256 x (VPBROADCASTW256 (VMOVQ (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLW256const [uint8(ssa.Log16(int16(c)))] x)
(VPMULLW512 x (VPBROADCASTW512 (VMOVQ (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLW512const [uint8(ssa.Log16(int16(c)))] x)

// 2-op VPTEST optimizations
(SETEQ (VPTEST x:(VPAND(128|256) j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k))
(SETEQ (VPTEST x:(VPAND(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k))
(SETEQ (VPTEST x:(VPANDN(128|256) j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order
(SETEQ (VPTEST x:(VPANDN(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order
(EQ (VPTEST x:(VPAND(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no)
(EQ (VPTEST x:(VPAND(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no)
(EQ (VPTEST x:(VPANDN(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order
(EQ (VPTEST x:(VPANDN(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order

// remove flags → bool → flags roundtrip
// Only do it if the flag generating instruction is local otherwise the likelihood flagalloc won't undo this optimization and makes things worse are slim.
(NE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
(NE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
(NE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
(NE t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)  s) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)

(CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVQNE yes no t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)  s)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)

(CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVLNE yes no t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)  s)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)

(CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
(CMOVWNE yes no t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)  s)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)

(SETNE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
(SETNE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
(SETNE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
(SETNE t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)  s)) && t.Block == s.Block => s

(EQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
(EQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
(EQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
(EQ t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)  s) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)

(CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVQEQ yes no t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)  s)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)

(CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVLEQ yes no t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)  s)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)

(CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
(CMOVWEQ yes no t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)  s)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)

(SETEQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
(SETEQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
(SETEQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
(SETEQ t:(TESTB            s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)  s)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)