shift bug
R=r
OCL=18166
CL=18166
diff --git a/src/cmd/6g/gen.c b/src/cmd/6g/gen.c
index 39c9d6f..f4a15f2 100644
--- a/src/cmd/6g/gen.c
+++ b/src/cmd/6g/gen.c
@@ -1047,13 +1047,16 @@
regalloc(&n1, nr->type, &n1);
// clean out the CL register
- if(rcl && !samereg(res, &n1)) {
+ if(rcl) {
regalloc(&n2, types[TINT64], N);
gins(AMOVQ, &n1, &n2);
regfree(&n1);
reg[D_CX] = 0;
- cgen_shift(op, nl, nr, res);
+ if(samereg(res, &n1))
+ cgen_shift(op, nl, nr, &n2);
+ else
+ cgen_shift(op, nl, nr, res);
reg[D_CX] = rcl;
gins(AMOVQ, &n2, &n1);