commit edff881ce5ca9c2ee209bcd7a2cd92b63ffe4179
author Alexandru Moșoi <mosoi@google.com> Tue Jul 28 14:58:49 2015 +0200
committer Keith Randall <khr@golang.org> Tue Jul 28 16:52:00 2015 +0000
tree d412464251e686d1104b243dc910e4cf3d6f919b
parent c15b0e83d2e5d00d9b19a5ba191aff26831458d8

[dev.ssa] cmd/compile/internal/ssa/gen: implement OAND.

Before this patch there was only partial support for ANDQconst
which was not lowered. This patch added support for AND operations
for all bit sizes and signs.

Change-Id: I3a6b2cddfac5361b27e85fcd97f7f3537ebfbcb6
Reviewed-on: https://go-review.googlesource.com/12761
Reviewed-by: Keith Randall <khr@golang.org>

src/cmd/compile/internal/gc/ssa.go

diff --git a/src/cmd/compile/internal/gc/ssa.go b/src/cmd/compile/internal/gc/ssa.go
index 91ec5a9..970799c 100644
--- a/src/cmd/compile/internal/gc/ssa.go
+++ b/src/cmd/compile/internal/gc/ssa.go
@@ -699,6 +699,15 @@
 	opAndType{OMUL, TINT64}:  ssa.OpMul64,
 	opAndType{OMUL, TUINT64}: ssa.OpMul64U,
 
+	opAndType{OAND, TINT8}:   ssa.OpAnd8,
+	opAndType{OAND, TUINT8}:  ssa.OpAnd8U,
+	opAndType{OAND, TINT16}:  ssa.OpAnd16,
+	opAndType{OAND, TUINT16}: ssa.OpAnd16U,
+	opAndType{OAND, TINT32}:  ssa.OpAnd32,
+	opAndType{OAND, TUINT32}: ssa.OpAnd32U,
+	opAndType{OAND, TINT64}:  ssa.OpAnd64,
+	opAndType{OAND, TUINT64}: ssa.OpAnd64U,
+
 	opAndType{OLSH, TINT8}:   ssa.OpLsh8,
 	opAndType{OLSH, TUINT8}:  ssa.OpLsh8,
 	opAndType{OLSH, TINT16}:  ssa.OpLsh16,
@@ -838,7 +847,7 @@
 		a := s.expr(n.Left)
 		b := s.expr(n.Right)
 		return s.newValue2(s.ssaOp(n.Op, n.Left.Type), ssa.TypeBool, a, b)
-	case OADD, OSUB, OMUL, OLSH, ORSH:
+	case OADD, OSUB, OMUL, OLSH, ORSH, OAND:
 		a := s.expr(n.Left)
 		b := s.expr(n.Right)
 		return s.newValue2(s.ssaOp(n.Op, n.Type), a.Type, a, b)
@@ -1425,7 +1434,9 @@
 		p.From.Index = regnum(v.Args[1])
 		p.To.Type = obj.TYPE_REG
 		p.To.Reg = regnum(v)
-	case ssa.OpAMD64ADDB, ssa.OpAMD64ANDQ, ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW:
+	case ssa.OpAMD64ADDB,
+		ssa.OpAMD64ANDQ, ssa.OpAMD64ANDL, ssa.OpAMD64ANDW, ssa.OpAMD64ANDB,
+		ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW:
 		r := regnum(v)
 		x := regnum(v.Args[0])
 		y := regnum(v.Args[1])
@@ -1509,7 +1520,7 @@
 		p.From.Reg = regnum(v.Args[1]) // should be CX
 		p.To.Type = obj.TYPE_REG
 		p.To.Reg = r
-	case ssa.OpAMD64SHLQconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SARQconst, ssa.OpAMD64XORQconst:
+	case ssa.OpAMD64ANDQconst, ssa.OpAMD64SHLQconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SARQconst, ssa.OpAMD64XORQconst:
 		x := regnum(v.Args[0])
 		r := regnum(v)
 		if x != r {