cmd/compile: use type information in Aux for Store size
Remove size AuxInt in Store, and alignment in Move/Zero. We still
pass size AuxInt to Move/Zero, as it is used for partial Move/Zero
lowering (e.g. cmd/compile/internal/ssa/gen/386.rules:288).
SizeAndAlign is gone.
Passes "toolstash -cmp" on std.
Change-Id: I1ca34652b65dd30de886940e789fcf41d521475d
Reviewed-on: https://go-review.googlesource.com/38150
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
diff --git a/src/cmd/compile/internal/ssa/check.go b/src/cmd/compile/internal/ssa/check.go
index d78e915..9fcfe9c 100644
--- a/src/cmd/compile/internal/ssa/check.go
+++ b/src/cmd/compile/internal/ssa/check.go
@@ -145,11 +145,9 @@
if !isExactFloat32(v) {
f.Fatalf("value %v has an AuxInt value that is not an exact float32", v)
}
- case auxSizeAndAlign:
- canHaveAuxInt = true
- case auxString, auxSym:
+ case auxString, auxSym, auxTyp:
canHaveAux = true
- case auxSymOff, auxSymValAndOff, auxSymSizeAndAlign:
+ case auxSymOff, auxSymValAndOff, auxTypSize:
canHaveAuxInt = true
canHaveAux = true
case auxSymInt32:
diff --git a/src/cmd/compile/internal/ssa/cse_test.go b/src/cmd/compile/internal/ssa/cse_test.go
index 905939f..2788ca6 100644
--- a/src/cmd/compile/internal/ssa/cse_test.go
+++ b/src/cmd/compile/internal/ssa/cse_test.go
@@ -38,7 +38,7 @@
Valu("r3", OpAdd64, TypeInt64, 0, nil, "arg1", "arg2"),
Valu("r5", OpAdd64, TypeInt64, 0, nil, "r2", "r3"),
Valu("r10", OpAdd64, TypeInt64, 0, nil, "r6", "r9"),
- Valu("rstore", OpStore, TypeMem, 8, nil, "raddr", "r10", "raddrdef"),
+ Valu("rstore", OpStore, TypeMem, 0, TypeInt64, "raddr", "r10", "raddrdef"),
Goto("exit")),
Bloc("exit",
Exit("rstore")))
@@ -104,7 +104,7 @@
Valu("r3", OpAdd64, TypeInt64, 0, nil, "r1", "r2"),
Valu("raddr", OpAddr, TypeInt64Ptr, 0, nil, "sp"),
Valu("raddrdef", OpVarDef, TypeMem, 0, nil, "start"),
- Valu("rstore", OpStore, TypeMem, 8, nil, "raddr", "r3", "raddrdef"),
+ Valu("rstore", OpStore, TypeMem, 0, TypeInt64, "raddr", "r3", "raddrdef"),
Goto("exit")),
Bloc("exit",
Exit("rstore")))
diff --git a/src/cmd/compile/internal/ssa/deadstore.go b/src/cmd/compile/internal/ssa/deadstore.go
index 774fb51..e2e4c47 100644
--- a/src/cmd/compile/internal/ssa/deadstore.go
+++ b/src/cmd/compile/internal/ssa/deadstore.go
@@ -88,9 +88,9 @@
if v.Op == OpStore || v.Op == OpZero {
var sz int64
if v.Op == OpStore {
- sz = v.AuxInt
+ sz = v.Aux.(Type).Size()
} else { // OpZero
- sz = SizeAndAlign(v.AuxInt).Size()
+ sz = v.AuxInt
}
if shadowedSize := int64(shadowed.get(v.Args[0].ID)); shadowedSize != -1 && shadowedSize >= sz {
// Modify store into a copy
diff --git a/src/cmd/compile/internal/ssa/deadstore_test.go b/src/cmd/compile/internal/ssa/deadstore_test.go
index beb6de0..003b228 100644
--- a/src/cmd/compile/internal/ssa/deadstore_test.go
+++ b/src/cmd/compile/internal/ssa/deadstore_test.go
@@ -18,11 +18,11 @@
Valu("addr1", OpAddr, ptrType, 0, nil, "sb"),
Valu("addr2", OpAddr, ptrType, 0, nil, "sb"),
Valu("addr3", OpAddr, ptrType, 0, nil, "sb"),
- Valu("zero1", OpZero, TypeMem, 1, nil, "addr3", "start"),
- Valu("store1", OpStore, TypeMem, 1, nil, "addr1", "v", "zero1"),
- Valu("store2", OpStore, TypeMem, 1, nil, "addr2", "v", "store1"),
- Valu("store3", OpStore, TypeMem, 1, nil, "addr1", "v", "store2"),
- Valu("store4", OpStore, TypeMem, 1, nil, "addr3", "v", "store3"),
+ Valu("zero1", OpZero, TypeMem, 1, TypeBool, "addr3", "start"),
+ Valu("store1", OpStore, TypeMem, 0, TypeBool, "addr1", "v", "zero1"),
+ Valu("store2", OpStore, TypeMem, 0, TypeBool, "addr2", "v", "store1"),
+ Valu("store3", OpStore, TypeMem, 0, TypeBool, "addr1", "v", "store2"),
+ Valu("store4", OpStore, TypeMem, 0, TypeBool, "addr3", "v", "store3"),
Goto("exit")),
Bloc("exit",
Exit("store3")))
@@ -54,7 +54,7 @@
Goto("loop")),
Bloc("loop",
Valu("phi", OpPhi, TypeMem, 0, nil, "start", "store"),
- Valu("store", OpStore, TypeMem, 1, nil, "addr", "v", "phi"),
+ Valu("store", OpStore, TypeMem, 0, TypeBool, "addr", "v", "phi"),
If("v", "loop", "exit")),
Bloc("exit",
Exit("store")))
@@ -79,8 +79,8 @@
Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr1", OpAddr, t1, 0, nil, "sb"),
Valu("addr2", OpAddr, t2, 0, nil, "sb"),
- Valu("store1", OpStore, TypeMem, 1, nil, "addr1", "v", "start"),
- Valu("store2", OpStore, TypeMem, 1, nil, "addr2", "v", "store1"),
+ Valu("store1", OpStore, TypeMem, 0, TypeBool, "addr1", "v", "start"),
+ Valu("store2", OpStore, TypeMem, 0, TypeBool, "addr2", "v", "store1"),
Goto("exit")),
Bloc("exit",
Exit("store2")))
@@ -108,8 +108,8 @@
Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr1", OpAddr, ptrType, 0, nil, "sb"),
- Valu("store1", OpStore, TypeMem, 8, nil, "addr1", "v", "start"), // store 8 bytes
- Valu("store2", OpStore, TypeMem, 1, nil, "addr1", "v", "store1"), // store 1 byte
+ Valu("store1", OpStore, TypeMem, 0, TypeInt64, "addr1", "v", "start"), // store 8 bytes
+ Valu("store2", OpStore, TypeMem, 0, TypeBool, "addr1", "v", "store1"), // store 1 byte
Goto("exit")),
Bloc("exit",
Exit("store2")))
diff --git a/src/cmd/compile/internal/ssa/func.go b/src/cmd/compile/internal/ssa/func.go
index fc7db29..a26c92e 100644
--- a/src/cmd/compile/internal/ssa/func.go
+++ b/src/cmd/compile/internal/ssa/func.go
@@ -352,6 +352,21 @@
return v
}
+// NewValue3A returns a new value in the block with three argument and an aux value.
+func (b *Block) NewValue3A(pos src.XPos, op Op, t Type, aux interface{}, arg0, arg1, arg2 *Value) *Value {
+ v := b.Func.newValue(op, t, b, pos)
+ v.AuxInt = 0
+ v.Aux = aux
+ v.Args = v.argstorage[:3]
+ v.argstorage[0] = arg0
+ v.argstorage[1] = arg1
+ v.argstorage[2] = arg2
+ arg0.Uses++
+ arg1.Uses++
+ arg2.Uses++
+ return v
+}
+
// NewValue4 returns a new value in the block with four arguments and zero aux values.
func (b *Block) NewValue4(pos src.XPos, op Op, t Type, arg0, arg1, arg2, arg3 *Value) *Value {
v := b.Func.newValue(op, t, b, pos)
diff --git a/src/cmd/compile/internal/ssa/gen/386.rules b/src/cmd/compile/internal/ssa/gen/386.rules
index 03002aa..2c3cbfc 100644
--- a/src/cmd/compile/internal/ssa/gen/386.rules
+++ b/src/cmd/compile/internal/ssa/gen/386.rules
@@ -256,47 +256,47 @@
// Lowering stores
// These more-specific FP versions of Store pattern should come first.
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem)
-(Store [4] ptr val mem) -> (MOVLstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVWstore ptr val mem)
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 -> (MOVLstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
// Lowering moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstore dst (MOVWload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstore dst (MOVLload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBload src mem) mem)
+(Move [2] dst src mem) -> (MOVWstore dst (MOVWload src mem) mem)
+(Move [4] dst src mem) -> (MOVLstore dst (MOVLload src mem) mem)
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBload [2] src mem)
(MOVWstore dst (MOVWload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 ->
+(Move [5] dst src mem) ->
(MOVBstore [4] dst (MOVBload [4] src mem)
(MOVLstore dst (MOVLload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 ->
+(Move [6] dst src mem) ->
(MOVWstore [4] dst (MOVWload [4] src mem)
(MOVLstore dst (MOVLload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 ->
+(Move [7] dst src mem) ->
(MOVLstore [3] dst (MOVLload [3] src mem)
(MOVLstore dst (MOVLload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 ->
+(Move [8] dst src mem) ->
(MOVLstore [4] dst (MOVLload [4] src mem)
(MOVLstore dst (MOVLload src mem) mem))
// Adjust moves to be a multiple of 4 bytes.
(Move [s] dst src mem)
- && SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size()%4 != 0 ->
- (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%4]
- (ADDLconst <dst.Type> dst [SizeAndAlign(s).Size()%4])
- (ADDLconst <src.Type> src [SizeAndAlign(s).Size()%4])
+ && s > 8 && s%4 != 0 ->
+ (Move [s-s%4]
+ (ADDLconst <dst.Type> dst [s%4])
+ (ADDLconst <src.Type> src [s%4])
(MOVLstore dst (MOVLload src mem) mem))
// Medium copying uses a duff device.
(Move [s] dst src mem)
- && SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() <= 4*128 && SizeAndAlign(s).Size()%4 == 0
+ && s > 8 && s <= 4*128 && s%4 == 0
&& !config.noDuffDevice ->
- (DUFFCOPY [10*(128-SizeAndAlign(s).Size()/4)] dst src mem)
+ (DUFFCOPY [10*(128-s/4)] dst src mem)
// 10 and 128 are magic constants. 10 is the number of bytes to encode:
// MOVL (SI), CX
// ADDL $4, SI
@@ -305,42 +305,42 @@
// and 128 is the number of such blocks. See src/runtime/duff_386.s:duffcopy.
// Large copying uses REP MOVSL.
-(Move [s] dst src mem) && (SizeAndAlign(s).Size() > 4*128 || config.noDuffDevice) && SizeAndAlign(s).Size()%4 == 0 ->
- (REPMOVSL dst src (MOVLconst [SizeAndAlign(s).Size()/4]) mem)
+(Move [s] dst src mem) && (s > 4*128 || config.noDuffDevice) && s%4 == 0 ->
+ (REPMOVSL dst src (MOVLconst [s/4]) mem)
// Lowering Zero instructions
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstoreconst [0] destptr mem)
+(Zero [0] _ mem) -> mem
+(Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem)
+(Zero [2] destptr mem) -> (MOVWstoreconst [0] destptr mem)
+(Zero [4] destptr mem) -> (MOVLstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] destptr mem) ->
(MOVBstoreconst [makeValAndOff(0,2)] destptr
(MOVWstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 5 ->
+(Zero [5] destptr mem) ->
(MOVBstoreconst [makeValAndOff(0,4)] destptr
(MOVLstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 6 ->
+(Zero [6] destptr mem) ->
(MOVWstoreconst [makeValAndOff(0,4)] destptr
(MOVLstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 7 ->
+(Zero [7] destptr mem) ->
(MOVLstoreconst [makeValAndOff(0,3)] destptr
(MOVLstoreconst [0] destptr mem))
// Strip off any fractional word zeroing.
-(Zero [s] destptr mem) && SizeAndAlign(s).Size()%4 != 0 && SizeAndAlign(s).Size() > 4 ->
- (Zero [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%4] (ADDLconst destptr [SizeAndAlign(s).Size()%4])
+(Zero [s] destptr mem) && s%4 != 0 && s > 4 ->
+ (Zero [s-s%4] (ADDLconst destptr [s%4])
(MOVLstoreconst [0] destptr mem))
// Zero small numbers of words directly.
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 ->
+(Zero [8] destptr mem) ->
(MOVLstoreconst [makeValAndOff(0,4)] destptr
(MOVLstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 12 ->
+(Zero [12] destptr mem) ->
(MOVLstoreconst [makeValAndOff(0,8)] destptr
(MOVLstoreconst [makeValAndOff(0,4)] destptr
(MOVLstoreconst [0] destptr mem)))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 ->
+(Zero [16] destptr mem) ->
(MOVLstoreconst [makeValAndOff(0,12)] destptr
(MOVLstoreconst [makeValAndOff(0,8)] destptr
(MOVLstoreconst [makeValAndOff(0,4)] destptr
@@ -348,20 +348,18 @@
// Medium zeroing uses a duff device.
(Zero [s] destptr mem)
- && SizeAndAlign(s).Size() > 16
- && SizeAndAlign(s).Size() <= 4*128
- && SizeAndAlign(s).Size()%4 == 0
+ && s > 16 && s <= 4*128 && s%4 == 0
&& !config.noDuffDevice ->
- (DUFFZERO [1*(128-SizeAndAlign(s).Size()/4)] destptr (MOVLconst [0]) mem)
+ (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem)
// 1 and 128 are magic constants. 1 is the number of bytes to encode STOSL.
// 128 is the number of STOSL instructions in duffzero.
// See src/runtime/duff_386.s:duffzero.
// Large zeroing uses REP STOSQ.
(Zero [s] destptr mem)
- && (SizeAndAlign(s).Size() > 4*128 || (config.noDuffDevice && SizeAndAlign(s).Size() > 16))
- && SizeAndAlign(s).Size()%4 == 0 ->
- (REPSTOSL destptr (MOVLconst [SizeAndAlign(s).Size()/4]) (MOVLconst [0]) mem)
+ && (s > 4*128 || (config.noDuffDevice && s > 16))
+ && s%4 == 0 ->
+ (REPSTOSL destptr (MOVLconst [s/4]) (MOVLconst [0]) mem)
// Lowering constants
(Const8 [val]) -> (MOVLconst [val])
diff --git a/src/cmd/compile/internal/ssa/gen/AMD64.rules b/src/cmd/compile/internal/ssa/gen/AMD64.rules
index 101d8a2..adfdfe9 100644
--- a/src/cmd/compile/internal/ssa/gen/AMD64.rules
+++ b/src/cmd/compile/internal/ssa/gen/AMD64.rules
@@ -297,56 +297,56 @@
// Lowering stores
// These more-specific FP versions of Store pattern should come first.
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVSDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVSSstore ptr val mem)
-(Store [8] ptr val mem) -> (MOVQstore ptr val mem)
-(Store [4] ptr val mem) -> (MOVLstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVWstore ptr val mem)
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 -> (MOVQstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 -> (MOVLstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
// Lowering moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstore dst (MOVWload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstore dst (MOVLload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 -> (MOVQstore dst (MOVQload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 -> (MOVOstore dst (MOVOload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBload src mem) mem)
+(Move [2] dst src mem) -> (MOVWstore dst (MOVWload src mem) mem)
+(Move [4] dst src mem) -> (MOVLstore dst (MOVLload src mem) mem)
+(Move [8] dst src mem) -> (MOVQstore dst (MOVQload src mem) mem)
+(Move [16] dst src mem) -> (MOVOstore dst (MOVOload src mem) mem)
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBload [2] src mem)
(MOVWstore dst (MOVWload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 ->
+(Move [5] dst src mem) ->
(MOVBstore [4] dst (MOVBload [4] src mem)
(MOVLstore dst (MOVLload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 ->
+(Move [6] dst src mem) ->
(MOVWstore [4] dst (MOVWload [4] src mem)
(MOVLstore dst (MOVLload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 ->
+(Move [7] dst src mem) ->
(MOVLstore [3] dst (MOVLload [3] src mem)
(MOVLstore dst (MOVLload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() < 16 ->
- (MOVQstore [SizeAndAlign(s).Size()-8] dst (MOVQload [SizeAndAlign(s).Size()-8] src mem)
+(Move [s] dst src mem) && s > 8 && s < 16 ->
+ (MOVQstore [s-8] dst (MOVQload [s-8] src mem)
(MOVQstore dst (MOVQload src mem) mem))
// Adjust moves to be a multiple of 16 bytes.
(Move [s] dst src mem)
- && SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 <= 8 ->
- (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%16]
- (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()%16])
- (OffPtr <src.Type> src [SizeAndAlign(s).Size()%16])
+ && s > 16 && s%16 != 0 && s%16 <= 8 ->
+ (Move [s-s%16]
+ (OffPtr <dst.Type> dst [s%16])
+ (OffPtr <src.Type> src [s%16])
(MOVQstore dst (MOVQload src mem) mem))
(Move [s] dst src mem)
- && SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 > 8 ->
- (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%16]
- (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()%16])
- (OffPtr <src.Type> src [SizeAndAlign(s).Size()%16])
+ && s > 16 && s%16 != 0 && s%16 > 8 ->
+ (Move [s-s%16]
+ (OffPtr <dst.Type> dst [s%16])
+ (OffPtr <src.Type> src [s%16])
(MOVOstore dst (MOVOload src mem) mem))
// Medium copying uses a duff device.
(Move [s] dst src mem)
- && SizeAndAlign(s).Size() >= 32 && SizeAndAlign(s).Size() <= 16*64 && SizeAndAlign(s).Size()%16 == 0
+ && s >= 32 && s <= 16*64 && s%16 == 0
&& !config.noDuffDevice ->
- (DUFFCOPY [14*(64-SizeAndAlign(s).Size()/16)] dst src mem)
+ (DUFFCOPY [14*(64-s/16)] dst src mem)
// 14 and 64 are magic constants. 14 is the number of bytes to encode:
// MOVUPS (SI), X0
// ADDQ $16, SI
@@ -355,43 +355,43 @@
// and 64 is the number of such blocks. See src/runtime/duff_amd64.s:duffcopy.
// Large copying uses REP MOVSQ.
-(Move [s] dst src mem) && (SizeAndAlign(s).Size() > 16*64 || config.noDuffDevice) && SizeAndAlign(s).Size()%8 == 0 ->
- (REPMOVSQ dst src (MOVQconst [SizeAndAlign(s).Size()/8]) mem)
+(Move [s] dst src mem) && (s > 16*64 || config.noDuffDevice) && s%8 == 0 ->
+ (REPMOVSQ dst src (MOVQconst [s/8]) mem)
// Lowering Zero instructions
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVWstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVLstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 -> (MOVQstoreconst [0] destptr mem)
+(Zero [0] _ mem) -> mem
+(Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem)
+(Zero [2] destptr mem) -> (MOVWstoreconst [0] destptr mem)
+(Zero [4] destptr mem) -> (MOVLstoreconst [0] destptr mem)
+(Zero [8] destptr mem) -> (MOVQstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] destptr mem) ->
(MOVBstoreconst [makeValAndOff(0,2)] destptr
(MOVWstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 5 ->
+(Zero [5] destptr mem) ->
(MOVBstoreconst [makeValAndOff(0,4)] destptr
(MOVLstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 6 ->
+(Zero [6] destptr mem) ->
(MOVWstoreconst [makeValAndOff(0,4)] destptr
(MOVLstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 7 ->
+(Zero [7] destptr mem) ->
(MOVLstoreconst [makeValAndOff(0,3)] destptr
(MOVLstoreconst [0] destptr mem))
// Strip off any fractional word zeroing.
-(Zero [s] destptr mem) && SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8 ->
- (Zero [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8] (OffPtr <destptr.Type> destptr [SizeAndAlign(s).Size()%8])
+(Zero [s] destptr mem) && s%8 != 0 && s > 8 ->
+ (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8])
(MOVQstoreconst [0] destptr mem))
// Zero small numbers of words directly.
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 ->
+(Zero [16] destptr mem) ->
(MOVQstoreconst [makeValAndOff(0,8)] destptr
(MOVQstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 24 ->
+(Zero [24] destptr mem) ->
(MOVQstoreconst [makeValAndOff(0,16)] destptr
(MOVQstoreconst [makeValAndOff(0,8)] destptr
(MOVQstoreconst [0] destptr mem)))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 32 ->
+(Zero [32] destptr mem) ->
(MOVQstoreconst [makeValAndOff(0,24)] destptr
(MOVQstoreconst [makeValAndOff(0,16)] destptr
(MOVQstoreconst [makeValAndOff(0,8)] destptr
@@ -399,18 +399,18 @@
// Medium zeroing uses a duff device.
(Zero [s] destptr mem)
- && SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size()%16 != 0
+ && s <= 1024 && s%8 == 0 && s%16 != 0
&& !config.noDuffDevice ->
- (Zero [SizeAndAlign(s).Size()-8] (OffPtr <destptr.Type> [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem))
+ (Zero [s-8] (OffPtr <destptr.Type> [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem))
(Zero [s] destptr mem)
- && SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%16 == 0 && !config.noDuffDevice ->
- (DUFFZERO [SizeAndAlign(s).Size()] destptr (MOVOconst [0]) mem)
+ && s <= 1024 && s%16 == 0 && !config.noDuffDevice ->
+ (DUFFZERO [s] destptr (MOVOconst [0]) mem)
// Large zeroing uses REP STOSQ.
(Zero [s] destptr mem)
- && (SizeAndAlign(s).Size() > 1024 || (config.noDuffDevice && SizeAndAlign(s).Size() > 32))
- && SizeAndAlign(s).Size()%8 == 0 ->
- (REPSTOSQ destptr (MOVQconst [SizeAndAlign(s).Size()/8]) (MOVQconst [0]) mem)
+ && (s > 1024 || (config.noDuffDevice && s > 32))
+ && s%8 == 0 ->
+ (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)
// Lowering constants
(Const8 [val]) -> (MOVLconst [val])
diff --git a/src/cmd/compile/internal/ssa/gen/ARM.rules b/src/cmd/compile/internal/ssa/gen/ARM.rules
index a1e6b5a..b2b4bf6 100644
--- a/src/cmd/compile/internal/ssa/gen/ARM.rules
+++ b/src/cmd/compile/internal/ssa/gen/ARM.rules
@@ -290,90 +290,90 @@
(Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem)
// stores
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
-(Store [4] ptr val mem) && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
// zero instructions
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVWconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [0] _ mem) -> mem
+(Zero [1] ptr mem) -> (MOVBstore ptr (MOVWconst [0]) mem)
+(Zero [2] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore ptr (MOVWconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 ->
+(Zero [2] ptr mem) ->
(MOVBstore [1] ptr (MOVWconst [0])
(MOVBstore [0] ptr (MOVWconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [4] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore ptr (MOVWconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [4] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] ptr (MOVWconst [0])
(MOVHstore [0] ptr (MOVWconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 ->
+(Zero [4] ptr mem) ->
(MOVBstore [3] ptr (MOVWconst [0])
(MOVBstore [2] ptr (MOVWconst [0])
(MOVBstore [1] ptr (MOVWconst [0])
(MOVBstore [0] ptr (MOVWconst [0]) mem))))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] ptr mem) ->
(MOVBstore [2] ptr (MOVWconst [0])
(MOVBstore [1] ptr (MOVWconst [0])
(MOVBstore [0] ptr (MOVWconst [0]) mem)))
// Medium zeroing uses a duff device
// 4 and 128 are magic constants, see runtime/mkduff.go
-(Zero [s] ptr mem)
- && SizeAndAlign(s).Size()%4 == 0 && SizeAndAlign(s).Size() > 4 && SizeAndAlign(s).Size() <= 512
- && SizeAndAlign(s).Align()%4 == 0 && !config.noDuffDevice ->
- (DUFFZERO [4 * (128 - int64(SizeAndAlign(s).Size()/4))] ptr (MOVWconst [0]) mem)
+(Zero [s] {t} ptr mem)
+ && s%4 == 0 && s > 4 && s <= 512
+ && t.(Type).Alignment()%4 == 0 && !config.noDuffDevice ->
+ (DUFFZERO [4 * (128 - int64(s/4))] ptr (MOVWconst [0]) mem)
// Large zeroing uses a loop
-(Zero [s] ptr mem)
- && (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%4 != 0 ->
- (LoweredZero [SizeAndAlign(s).Align()]
+(Zero [s] {t} ptr mem)
+ && (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%4 != 0 ->
+ (LoweredZero [t.(Type).Alignment()]
ptr
- (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)])
(MOVWconst [0])
mem)
// moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBUload src mem) mem)
+(Move [2] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore dst (MOVHUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 ->
+(Move [2] dst src mem) ->
(MOVBstore [1] dst (MOVBUload [1] src mem)
(MOVBstore dst (MOVBUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore dst (MOVWload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] dst (MOVHUload [2] src mem)
(MOVHstore dst (MOVHUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 ->
+(Move [4] dst src mem) ->
(MOVBstore [3] dst (MOVBUload [3] src mem)
(MOVBstore [2] dst (MOVBUload [2] src mem)
(MOVBstore [1] dst (MOVBUload [1] src mem)
(MOVBstore dst (MOVBUload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBUload [2] src mem)
(MOVBstore [1] dst (MOVBUload [1] src mem)
(MOVBstore dst (MOVBUload src mem) mem)))
// Medium move uses a duff device
// 8 and 128 are magic constants, see runtime/mkduff.go
-(Move [s] dst src mem)
- && SizeAndAlign(s).Size()%4 == 0 && SizeAndAlign(s).Size() > 4 && SizeAndAlign(s).Size() <= 512
- && SizeAndAlign(s).Align()%4 == 0 && !config.noDuffDevice ->
- (DUFFCOPY [8 * (128 - int64(SizeAndAlign(s).Size()/4))] dst src mem)
+(Move [s] {t} dst src mem)
+ && s%4 == 0 && s > 4 && s <= 512
+ && t.(Type).Alignment()%4 == 0 && !config.noDuffDevice ->
+ (DUFFCOPY [8 * (128 - int64(s/4))] dst src mem)
// Large move uses a loop
-(Move [s] dst src mem)
- && (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%4 != 0 ->
- (LoweredMove [SizeAndAlign(s).Align()]
+(Move [s] {t} dst src mem)
+ && (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%4 != 0 ->
+ (LoweredMove [t.(Type).Alignment()]
dst
src
- (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)])
mem)
// calls
diff --git a/src/cmd/compile/internal/ssa/gen/ARM64.rules b/src/cmd/compile/internal/ssa/gen/ARM64.rules
index 8b6ecba..8dde996 100644
--- a/src/cmd/compile/internal/ssa/gen/ARM64.rules
+++ b/src/cmd/compile/internal/ssa/gen/ARM64.rules
@@ -331,117 +331,117 @@
(Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem)
// stores
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
-(Store [4] ptr val mem) && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
-(Store [8] ptr val mem) && !is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && !is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
// zeroing
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVDconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVHstore ptr (MOVDconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVWstore ptr (MOVDconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 -> (MOVDstore ptr (MOVDconst [0]) mem)
+(Zero [0] _ mem) -> mem
+(Zero [1] ptr mem) -> (MOVBstore ptr (MOVDconst [0]) mem)
+(Zero [2] ptr mem) -> (MOVHstore ptr (MOVDconst [0]) mem)
+(Zero [4] ptr mem) -> (MOVWstore ptr (MOVDconst [0]) mem)
+(Zero [8] ptr mem) -> (MOVDstore ptr (MOVDconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] ptr mem) ->
(MOVBstore [2] ptr (MOVDconst [0])
(MOVHstore ptr (MOVDconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 5 ->
+(Zero [5] ptr mem) ->
(MOVBstore [4] ptr (MOVDconst [0])
(MOVWstore ptr (MOVDconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 6 ->
+(Zero [6] ptr mem) ->
(MOVHstore [4] ptr (MOVDconst [0])
(MOVWstore ptr (MOVDconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 7 ->
+(Zero [7] ptr mem) ->
(MOVBstore [6] ptr (MOVDconst [0])
(MOVHstore [4] ptr (MOVDconst [0])
(MOVWstore ptr (MOVDconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 12 ->
+(Zero [12] ptr mem) ->
(MOVWstore [8] ptr (MOVDconst [0])
(MOVDstore ptr (MOVDconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 16 ->
+(Zero [16] ptr mem) ->
(MOVDstore [8] ptr (MOVDconst [0])
(MOVDstore ptr (MOVDconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 24 ->
+(Zero [24] ptr mem) ->
(MOVDstore [16] ptr (MOVDconst [0])
(MOVDstore [8] ptr (MOVDconst [0])
(MOVDstore ptr (MOVDconst [0]) mem)))
// strip off fractional word zeroing
-(Zero [s] ptr mem) && SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8 ->
- (Zero [MakeSizeAndAlign(SizeAndAlign(s).Size()%8, 1).Int64()]
- (OffPtr <ptr.Type> ptr [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8])
- (Zero [MakeSizeAndAlign(SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8, 1).Int64()] ptr mem))
+(Zero [s] ptr mem) && s%8 != 0 && s > 8 ->
+ (Zero [s%8]
+ (OffPtr <ptr.Type> ptr [s-s%8])
+ (Zero [s-s%8] ptr mem))
// medium zeroing uses a duff device
// 4, 8, and 128 are magic constants, see runtime/mkduff.go
(Zero [s] ptr mem)
- && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128
+ && s%8 == 0 && s > 24 && s <= 8*128
&& !config.noDuffDevice ->
- (DUFFZERO [4 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem)
+ (DUFFZERO [4 * (128 - int64(s/8))] ptr mem)
// large zeroing uses a loop
(Zero [s] ptr mem)
- && SizeAndAlign(s).Size()%8 == 0 && (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) ->
+ && s%8 == 0 && (s > 8*128 || config.noDuffDevice) ->
(LoweredZero
ptr
- (ADDconst <ptr.Type> [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)] ptr)
+ (ADDconst <ptr.Type> [s-8] ptr)
mem)
// moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVHstore dst (MOVHUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVWstore dst (MOVWUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 -> (MOVDstore dst (MOVDload src mem) mem)
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBUload src mem) mem)
+(Move [2] dst src mem) -> (MOVHstore dst (MOVHUload src mem) mem)
+(Move [4] dst src mem) -> (MOVWstore dst (MOVWUload src mem) mem)
+(Move [8] dst src mem) -> (MOVDstore dst (MOVDload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBUload [2] src mem)
(MOVHstore dst (MOVHUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 ->
+(Move [5] dst src mem) ->
(MOVBstore [4] dst (MOVBUload [4] src mem)
(MOVWstore dst (MOVWUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 ->
+(Move [6] dst src mem) ->
(MOVHstore [4] dst (MOVHUload [4] src mem)
(MOVWstore dst (MOVWUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 ->
+(Move [7] dst src mem) ->
(MOVBstore [6] dst (MOVBUload [6] src mem)
(MOVHstore [4] dst (MOVHUload [4] src mem)
(MOVWstore dst (MOVWUload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 12 ->
+(Move [12] dst src mem) ->
(MOVWstore [8] dst (MOVWUload [8] src mem)
(MOVDstore dst (MOVDload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 ->
+(Move [16] dst src mem) ->
(MOVDstore [8] dst (MOVDload [8] src mem)
(MOVDstore dst (MOVDload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 24 ->
+(Move [24] dst src mem) ->
(MOVDstore [16] dst (MOVDload [16] src mem)
(MOVDstore [8] dst (MOVDload [8] src mem)
(MOVDstore dst (MOVDload src mem) mem)))
// strip off fractional word move
-(Move [s] dst src mem) && SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8 ->
- (Move [MakeSizeAndAlign(SizeAndAlign(s).Size()%8, 1).Int64()]
- (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8])
- (OffPtr <src.Type> src [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8])
- (Move [MakeSizeAndAlign(SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8, 1).Int64()] dst src mem))
+(Move [s] dst src mem) && s%8 != 0 && s > 8 ->
+ (Move [s%8]
+ (OffPtr <dst.Type> dst [s-s%8])
+ (OffPtr <src.Type> src [s-s%8])
+ (Move [s-s%8] dst src mem))
// medium move uses a duff device
// 8 and 128 are magic constants, see runtime/mkduff.go
(Move [s] dst src mem)
- && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128
+ && s%8 == 0 && s > 24 && s <= 8*128
&& !config.noDuffDevice ->
- (DUFFCOPY [8 * (128 - int64(SizeAndAlign(s).Size()/8))] dst src mem)
+ (DUFFCOPY [8 * (128 - int64(s/8))] dst src mem)
// large move uses a loop
(Move [s] dst src mem)
- && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size()%8 == 0 ->
+ && s > 24 && s%8 == 0 ->
(LoweredMove
dst
src
- (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <src.Type> src [s-8])
mem)
// calls
diff --git a/src/cmd/compile/internal/ssa/gen/MIPS.rules b/src/cmd/compile/internal/ssa/gen/MIPS.rules
index 619771c..a312aa5 100644
--- a/src/cmd/compile/internal/ssa/gen/MIPS.rules
+++ b/src/cmd/compile/internal/ssa/gen/MIPS.rules
@@ -264,99 +264,98 @@
(Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem)
// stores
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
-(Store [4] ptr val mem) && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
-(Store [8] ptr val mem) && !is64BitFloat(val.Type) -> (MOVWstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
// zero instructions
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVWconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [0] _ mem) -> mem
+(Zero [1] ptr mem) -> (MOVBstore ptr (MOVWconst [0]) mem)
+(Zero [2] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore ptr (MOVWconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 ->
+(Zero [2] ptr mem) ->
(MOVBstore [1] ptr (MOVWconst [0])
(MOVBstore [0] ptr (MOVWconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [4] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore ptr (MOVWconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [4] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] ptr (MOVWconst [0])
(MOVHstore [0] ptr (MOVWconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 ->
+(Zero [4] ptr mem) ->
(MOVBstore [3] ptr (MOVWconst [0])
(MOVBstore [2] ptr (MOVWconst [0])
(MOVBstore [1] ptr (MOVWconst [0])
(MOVBstore [0] ptr (MOVWconst [0]) mem))))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] ptr mem) ->
(MOVBstore [2] ptr (MOVWconst [0])
(MOVBstore [1] ptr (MOVWconst [0])
(MOVBstore [0] ptr (MOVWconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [6] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [4] ptr (MOVWconst [0])
(MOVHstore [2] ptr (MOVWconst [0])
(MOVHstore [0] ptr (MOVWconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [8] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [4] ptr (MOVWconst [0])
(MOVWstore [0] ptr (MOVWconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [12] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [8] ptr (MOVWconst [0])
(MOVWstore [4] ptr (MOVWconst [0])
(MOVWstore [0] ptr (MOVWconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [16] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [12] ptr (MOVWconst [0])
(MOVWstore [8] ptr (MOVWconst [0])
(MOVWstore [4] ptr (MOVWconst [0])
(MOVWstore [0] ptr (MOVWconst [0]) mem))))
// large or unaligned zeroing uses a loop
-(Zero [s] ptr mem)
- && (SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) ->
- (LoweredZero [SizeAndAlign(s).Align()]
+(Zero [s] {t} ptr mem)
+ && (s > 16 || s%4 != 0) ->
+ (LoweredZero [t.(Type).Alignment()]
ptr
- (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)])
mem)
// moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBUload src mem) mem)
+(Move [2] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore dst (MOVHUload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 ->
+(Move [2] dst src mem) ->
(MOVBstore [1] dst (MOVBUload [1] src mem)
(MOVBstore dst (MOVBUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore dst (MOVWload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] dst (MOVHUload [2] src mem)
(MOVHstore dst (MOVHUload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 ->
+(Move [4] dst src mem) ->
(MOVBstore [3] dst (MOVBUload [3] src mem)
(MOVBstore [2] dst (MOVBUload [2] src mem)
(MOVBstore [1] dst (MOVBUload [1] src mem)
(MOVBstore dst (MOVBUload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBUload [2] src mem)
(MOVBstore [1] dst (MOVBUload [1] src mem)
(MOVBstore dst (MOVBUload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [4] dst (MOVWload [4] src mem)
(MOVWstore dst (MOVWload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [6] dst (MOVHload [6] src mem)
(MOVHstore [4] dst (MOVHload [4] src mem)
(MOVHstore [2] dst (MOVHload [2] src mem)
(MOVHstore dst (MOVHload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [6] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [4] dst (MOVHload [4] src mem)
(MOVHstore [2] dst (MOVHload [2] src mem)
(MOVHstore dst (MOVHload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [12] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [8] dst (MOVWload [8] src mem)
(MOVWstore [4] dst (MOVWload [4] src mem)
(MOVWstore dst (MOVWload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [16] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [12] dst (MOVWload [12] src mem)
(MOVWstore [8] dst (MOVWload [8] src mem)
(MOVWstore [4] dst (MOVWload [4] src mem)
@@ -364,12 +363,12 @@
// large or unaligned move uses a loop
-(Move [s] dst src mem)
- && (SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) ->
- (LoweredMove [SizeAndAlign(s).Align()]
+(Move [s] {t} dst src mem)
+ && (s > 16 || t.(Type).Alignment()%4 != 0) ->
+ (LoweredMove [t.(Type).Alignment()]
dst
src
- (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)])
mem)
// calls
diff --git a/src/cmd/compile/internal/ssa/gen/MIPS64.rules b/src/cmd/compile/internal/ssa/gen/MIPS64.rules
index 301ad26..a9ef12d 100644
--- a/src/cmd/compile/internal/ssa/gen/MIPS64.rules
+++ b/src/cmd/compile/internal/ssa/gen/MIPS64.rules
@@ -285,133 +285,133 @@
(Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem)
// stores
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
-(Store [4] ptr val mem) && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
-(Store [8] ptr val mem) && !is64BitFloat(val.Type) -> (MOVVstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && !is64BitFloat(val.Type) -> (MOVVstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVFstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVDstore ptr val mem)
// zeroing
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVVconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [0] _ mem) -> mem
+(Zero [1] ptr mem) -> (MOVBstore ptr (MOVVconst [0]) mem)
+(Zero [2] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore ptr (MOVVconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 ->
+(Zero [2] ptr mem) ->
(MOVBstore [1] ptr (MOVVconst [0])
(MOVBstore [0] ptr (MOVVconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [4] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore ptr (MOVVconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [4] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] ptr (MOVVconst [0])
(MOVHstore [0] ptr (MOVVconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 ->
+(Zero [4] ptr mem) ->
(MOVBstore [3] ptr (MOVVconst [0])
(MOVBstore [2] ptr (MOVVconst [0])
(MOVBstore [1] ptr (MOVVconst [0])
(MOVBstore [0] ptr (MOVVconst [0]) mem))))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [8] {t} ptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVVstore ptr (MOVVconst [0]) mem)
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [8] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [4] ptr (MOVVconst [0])
(MOVWstore [0] ptr (MOVVconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 ->
+(Zero [8] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [6] ptr (MOVVconst [0])
(MOVHstore [4] ptr (MOVVconst [0])
(MOVHstore [2] ptr (MOVVconst [0])
(MOVHstore [0] ptr (MOVVconst [0]) mem))))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] ptr mem) ->
(MOVBstore [2] ptr (MOVVconst [0])
(MOVBstore [1] ptr (MOVVconst [0])
(MOVBstore [0] ptr (MOVVconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [6] {t} ptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [4] ptr (MOVVconst [0])
(MOVHstore [2] ptr (MOVVconst [0])
(MOVHstore [0] ptr (MOVVconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [12] {t} ptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [8] ptr (MOVVconst [0])
(MOVWstore [4] ptr (MOVVconst [0])
(MOVWstore [0] ptr (MOVVconst [0]) mem)))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [16] {t} ptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVVstore [8] ptr (MOVVconst [0])
(MOVVstore [0] ptr (MOVVconst [0]) mem))
-(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [24] {t} ptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVVstore [16] ptr (MOVVconst [0])
(MOVVstore [8] ptr (MOVVconst [0])
(MOVVstore [0] ptr (MOVVconst [0]) mem)))
// medium zeroing uses a duff device
// 8, and 128 are magic constants, see runtime/mkduff.go
-(Zero [s] ptr mem)
- && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128
- && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice ->
- (DUFFZERO [8 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem)
+(Zero [s] {t} ptr mem)
+ && s%8 == 0 && s > 24 && s <= 8*128
+ && t.(Type).Alignment()%8 == 0 && !config.noDuffDevice ->
+ (DUFFZERO [8 * (128 - int64(s/8))] ptr mem)
// large or unaligned zeroing uses a loop
-(Zero [s] ptr mem)
- && (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0 ->
- (LoweredZero [SizeAndAlign(s).Align()]
+(Zero [s] {t} ptr mem)
+ && (s > 8*128 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0 ->
+ (LoweredZero [t.(Type).Alignment()]
ptr
- (ADDVconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDVconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)])
mem)
// moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBload src mem) mem)
+(Move [2] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore dst (MOVHload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 ->
+(Move [2] dst src mem) ->
(MOVBstore [1] dst (MOVBload [1] src mem)
(MOVBstore dst (MOVBload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore dst (MOVWload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] dst (MOVHload [2] src mem)
(MOVHstore dst (MOVHload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 ->
+(Move [4] dst src mem) ->
(MOVBstore [3] dst (MOVBload [3] src mem)
(MOVBstore [2] dst (MOVBload [2] src mem)
(MOVBstore [1] dst (MOVBload [1] src mem)
(MOVBstore dst (MOVBload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%8 == 0 ->
(MOVVstore dst (MOVVload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [4] dst (MOVWload [4] src mem)
(MOVWstore dst (MOVWload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [6] dst (MOVHload [6] src mem)
(MOVHstore [4] dst (MOVHload [4] src mem)
(MOVHstore [2] dst (MOVHload [2] src mem)
(MOVHstore dst (MOVHload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBload [2] src mem)
(MOVBstore [1] dst (MOVBload [1] src mem)
(MOVBstore dst (MOVBload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [6] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [4] dst (MOVHload [4] src mem)
(MOVHstore [2] dst (MOVHload [2] src mem)
(MOVHstore dst (MOVHload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [12] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [8] dst (MOVWload [8] src mem)
(MOVWstore [4] dst (MOVWload [4] src mem)
(MOVWstore dst (MOVWload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 ->
+(Move [16] {t} dst src mem) && t.(Type).Alignment()%8 == 0 ->
(MOVVstore [8] dst (MOVVload [8] src mem)
(MOVVstore dst (MOVVload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 ->
+(Move [24] {t} dst src mem) && t.(Type).Alignment()%8 == 0 ->
(MOVVstore [16] dst (MOVVload [16] src mem)
(MOVVstore [8] dst (MOVVload [8] src mem)
(MOVVstore dst (MOVVload src mem) mem)))
// large or unaligned move uses a loop
-(Move [s] dst src mem)
- && SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0 ->
- (LoweredMove [SizeAndAlign(s).Align()]
+(Move [s] {t} dst src mem)
+ && s > 24 || t.(Type).Alignment()%8 != 0 ->
+ (LoweredMove [t.(Type).Alignment()]
dst
src
- (ADDVconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDVconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)])
mem)
// calls
diff --git a/src/cmd/compile/internal/ssa/gen/PPC64.rules b/src/cmd/compile/internal/ssa/gen/PPC64.rules
index a728979..9fe0ead 100644
--- a/src/cmd/compile/internal/ssa/gen/PPC64.rules
+++ b/src/cmd/compile/internal/ssa/gen/PPC64.rules
@@ -477,111 +477,111 @@
(Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem)
(Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem)
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
-(Store [8] ptr val mem) && is32BitFloat(val.Type) -> (FMOVDstore ptr val mem) // glitch from (Cvt32Fto64F x) -> x -- type is wrong
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
-(Store [8] ptr val mem) && (is64BitInt(val.Type) || isPtr(val.Type)) -> (MOVDstore ptr val mem)
-(Store [4] ptr val mem) && is32BitInt(val.Type) -> (MOVWstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is32BitFloat(val.Type) -> (FMOVDstore ptr val mem) // glitch from (Cvt32Fto64F x) -> x -- type is wrong
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type)) -> (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitInt(val.Type) -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstorezero destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [0] _ mem) -> mem
+(Zero [1] destptr mem) -> (MOVBstorezero destptr mem)
+(Zero [2] {t} destptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstorezero destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 ->
+(Zero [2] destptr mem) ->
(MOVBstorezero [1] destptr
(MOVBstorezero [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [4] {t} destptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstorezero destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [4] {t} destptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstorezero [2] destptr
(MOVHstorezero [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 ->
+(Zero [4] destptr mem) ->
(MOVBstorezero [3] destptr
(MOVBstorezero [2] destptr
(MOVBstorezero [1] destptr
(MOVBstorezero [0] destptr mem))))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [8] {t} destptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVDstorezero [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+(Zero [8] {t} destptr mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstorezero [4] destptr
(MOVWstorezero [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 ->
+(Zero [8] {t} destptr mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstorezero [6] destptr
(MOVHstorezero [4] destptr
(MOVHstorezero [2] destptr
(MOVHstorezero [0] destptr mem))))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [3] destptr mem) ->
(MOVBstorezero [2] destptr
(MOVBstorezero [1] destptr
(MOVBstorezero [0] destptr mem)))
// Zero small numbers of words directly.
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [16] {t} destptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVDstorezero [8] destptr
(MOVDstorezero [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [24] {t} destptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVDstorezero [16] destptr
(MOVDstorezero [8] destptr
(MOVDstorezero [0] destptr mem)))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 32 && SizeAndAlign(s).Align()%8 == 0 ->
+(Zero [32] {t} destptr mem) && t.(Type).Alignment()%8 == 0 ->
(MOVDstorezero [24] destptr
(MOVDstorezero [16] destptr
(MOVDstorezero [8] destptr
(MOVDstorezero [0] destptr mem))))
// Large zeroing uses a loop
-(Zero [s] ptr mem)
- && (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0 ->
- (LoweredZero [SizeAndAlign(s).Align()]
+(Zero [s] {t} ptr mem)
+ && (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0 ->
+ (LoweredZero [t.(Type).Alignment()]
ptr
- (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)])
mem)
// moves
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBZload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBZload src mem) mem)
+(Move [2] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore dst (MOVHZload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 ->
+(Move [2] dst src mem) ->
(MOVBstore [1] dst (MOVBZload [1] src mem)
(MOVBstore dst (MOVBZload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore dst (MOVWload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
+(Move [4] {t} dst src mem) && t.(Type).Alignment()%2 == 0 ->
(MOVHstore [2] dst (MOVHZload [2] src mem)
(MOVHstore dst (MOVHZload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 ->
+(Move [4] dst src mem) ->
(MOVBstore [3] dst (MOVBZload [3] src mem)
(MOVBstore [2] dst (MOVBZload [2] src mem)
(MOVBstore [1] dst (MOVBZload [1] src mem)
(MOVBstore dst (MOVBZload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%8 == 0 ->
(MOVDstore dst (MOVDload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%4 == 0 ->
(MOVWstore [4] dst (MOVWZload [4] src mem)
(MOVWstore dst (MOVWZload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0->
+(Move [8] {t} dst src mem) && t.(Type).Alignment()%2 == 0->
(MOVHstore [6] dst (MOVHZload [6] src mem)
(MOVHstore [4] dst (MOVHZload [4] src mem)
(MOVHstore [2] dst (MOVHZload [2] src mem)
(MOVHstore dst (MOVHZload src mem) mem))))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBZload [2] src mem)
(MOVBstore [1] dst (MOVBZload [1] src mem)
(MOVBstore dst (MOVBZload src mem) mem)))
// Large move uses a loop
-(Move [s] dst src mem)
- && (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0 ->
- (LoweredMove [SizeAndAlign(s).Align()]
+(Move [s] {t} dst src mem)
+ && (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0 ->
+ (LoweredMove [t.(Type).Alignment()]
dst
src
- (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)])
+ (ADDconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)])
mem)
// Calls
diff --git a/src/cmd/compile/internal/ssa/gen/S390X.rules b/src/cmd/compile/internal/ssa/gen/S390X.rules
index c2d1578..0a3dccf 100644
--- a/src/cmd/compile/internal/ssa/gen/S390X.rules
+++ b/src/cmd/compile/internal/ssa/gen/S390X.rules
@@ -320,82 +320,82 @@
// Lowering stores
// These more-specific FP versions of Store pattern should come first.
-(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
-(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
-(Store [8] ptr val mem) -> (MOVDstore ptr val mem)
-(Store [4] ptr val mem) -> (MOVWstore ptr val mem)
-(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
-(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 8 -> (MOVDstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 4 -> (MOVWstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 2 -> (MOVHstore ptr val mem)
+(Store {t} ptr val mem) && t.(Type).Size() == 1 -> (MOVBstore ptr val mem)
// Lowering moves
// Load and store for small copies.
-(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBZload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVHstore dst (MOVHZload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVWstore dst (MOVWZload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 -> (MOVDstore dst (MOVDload src mem) mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 ->
+(Move [0] _ _ mem) -> mem
+(Move [1] dst src mem) -> (MOVBstore dst (MOVBZload src mem) mem)
+(Move [2] dst src mem) -> (MOVHstore dst (MOVHZload src mem) mem)
+(Move [4] dst src mem) -> (MOVWstore dst (MOVWZload src mem) mem)
+(Move [8] dst src mem) -> (MOVDstore dst (MOVDload src mem) mem)
+(Move [16] dst src mem) ->
(MOVDstore [8] dst (MOVDload [8] src mem)
(MOVDstore dst (MOVDload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 24 ->
+(Move [24] dst src mem) ->
(MOVDstore [16] dst (MOVDload [16] src mem)
(MOVDstore [8] dst (MOVDload [8] src mem)
(MOVDstore dst (MOVDload src mem) mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 ->
+(Move [3] dst src mem) ->
(MOVBstore [2] dst (MOVBZload [2] src mem)
(MOVHstore dst (MOVHZload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 ->
+(Move [5] dst src mem) ->
(MOVBstore [4] dst (MOVBZload [4] src mem)
(MOVWstore dst (MOVWZload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 ->
+(Move [6] dst src mem) ->
(MOVHstore [4] dst (MOVHZload [4] src mem)
(MOVWstore dst (MOVWZload src mem) mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 ->
+(Move [7] dst src mem) ->
(MOVBstore [6] dst (MOVBZload [6] src mem)
(MOVHstore [4] dst (MOVHZload [4] src mem)
(MOVWstore dst (MOVWZload src mem) mem)))
// MVC for other moves. Use up to 4 instructions (sizes up to 1024 bytes).
-(Move [s] dst src mem) && SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 256 ->
- (MVC [makeValAndOff(SizeAndAlign(s).Size(), 0)] dst src mem)
-(Move [s] dst src mem) && SizeAndAlign(s).Size() > 256 && SizeAndAlign(s).Size() <= 512 ->
- (MVC [makeValAndOff(SizeAndAlign(s).Size()-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() > 512 && SizeAndAlign(s).Size() <= 768 ->
- (MVC [makeValAndOff(SizeAndAlign(s).Size()-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))
-(Move [s] dst src mem) && SizeAndAlign(s).Size() > 768 && SizeAndAlign(s).Size() <= 1024 ->
- (MVC [makeValAndOff(SizeAndAlign(s).Size()-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))))
+(Move [s] dst src mem) && s > 0 && s <= 256 ->
+ (MVC [makeValAndOff(s, 0)] dst src mem)
+(Move [s] dst src mem) && s > 256 && s <= 512 ->
+ (MVC [makeValAndOff(s-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))
+(Move [s] dst src mem) && s > 512 && s <= 768 ->
+ (MVC [makeValAndOff(s-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))
+(Move [s] dst src mem) && s > 768 && s <= 1024 ->
+ (MVC [makeValAndOff(s-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))))
// Move more than 1024 bytes using a loop.
-(Move [s] dst src mem) && SizeAndAlign(s).Size() > 1024 ->
- (LoweredMove [SizeAndAlign(s).Size()%256] dst src (ADDconst <src.Type> src [(SizeAndAlign(s).Size()/256)*256]) mem)
+(Move [s] dst src mem) && s > 1024 ->
+ (LoweredMove [s%256] dst src (ADDconst <src.Type> src [(s/256)*256]) mem)
// Lowering Zero instructions
-(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVHstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVWstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 -> (MOVDstoreconst [0] destptr mem)
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 ->
+(Zero [0] _ mem) -> mem
+(Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem)
+(Zero [2] destptr mem) -> (MOVHstoreconst [0] destptr mem)
+(Zero [4] destptr mem) -> (MOVWstoreconst [0] destptr mem)
+(Zero [8] destptr mem) -> (MOVDstoreconst [0] destptr mem)
+(Zero [3] destptr mem) ->
(MOVBstoreconst [makeValAndOff(0,2)] destptr
(MOVHstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 5 ->
+(Zero [5] destptr mem) ->
(MOVBstoreconst [makeValAndOff(0,4)] destptr
(MOVWstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 6 ->
+(Zero [6] destptr mem) ->
(MOVHstoreconst [makeValAndOff(0,4)] destptr
(MOVWstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 7 ->
+(Zero [7] destptr mem) ->
(MOVWstoreconst [makeValAndOff(0,3)] destptr
(MOVWstoreconst [0] destptr mem))
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 1024 ->
- (CLEAR [makeValAndOff(SizeAndAlign(s).Size(), 0)] destptr mem)
+(Zero [s] destptr mem) && s > 0 && s <= 1024 ->
+ (CLEAR [makeValAndOff(s, 0)] destptr mem)
// Move more than 1024 bytes using a loop.
-(Zero [s] destptr mem) && SizeAndAlign(s).Size() > 1024 ->
- (LoweredZero [SizeAndAlign(s).Size()%256] destptr (ADDconst <destptr.Type> destptr [(SizeAndAlign(s).Size()/256)*256]) mem)
+(Zero [s] destptr mem) && s > 1024 ->
+ (LoweredZero [s%256] destptr (ADDconst <destptr.Type> destptr [(s/256)*256]) mem)
// Lowering constants
(Const8 [val]) -> (MOVDconst [val])
diff --git a/src/cmd/compile/internal/ssa/gen/dec.rules b/src/cmd/compile/internal/ssa/gen/dec.rules
index 97f6a11..b7050d2 100644
--- a/src/cmd/compile/internal/ssa/gen/dec.rules
+++ b/src/cmd/compile/internal/ssa/gen/dec.rules
@@ -18,11 +18,11 @@
(OffPtr <config.fe.TypeFloat32().PtrTo()> [4] ptr)
mem)
)
-(Store [8] dst (ComplexMake real imag) mem) ->
- (Store [4] {config.fe.TypeFloat32()}
+(Store {t} dst (ComplexMake real imag) mem) && t.(Type).Size() == 8 ->
+ (Store {config.fe.TypeFloat32()}
(OffPtr <config.fe.TypeFloat32().PtrTo()> [4] dst)
imag
- (Store [4] {config.fe.TypeFloat32()} dst real mem))
+ (Store {config.fe.TypeFloat32()} dst real mem))
(Load <t> ptr mem) && t.IsComplex() && t.Size() == 16 ->
(ComplexMake
(Load <config.fe.TypeFloat64()> ptr mem)
@@ -30,11 +30,11 @@
(OffPtr <config.fe.TypeFloat64().PtrTo()> [8] ptr)
mem)
)
-(Store [16] dst (ComplexMake real imag) mem) ->
- (Store [8] {config.fe.TypeFloat64()}
+(Store {t} dst (ComplexMake real imag) mem) && t.(Type).Size() == 16 ->
+ (Store {config.fe.TypeFloat64()}
(OffPtr <config.fe.TypeFloat64().PtrTo()> [8] dst)
imag
- (Store [8] {config.fe.TypeFloat64()} dst real mem))
+ (Store {config.fe.TypeFloat64()} dst real mem))
// string ops
(StringPtr (StringMake ptr _)) -> ptr
@@ -46,11 +46,11 @@
(Load <config.fe.TypeInt()>
(OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] ptr)
mem))
-(Store [2*config.PtrSize] dst (StringMake ptr len) mem) ->
- (Store [config.PtrSize] {config.fe.TypeInt()}
+(Store dst (StringMake ptr len) mem) ->
+ (Store {config.fe.TypeInt()}
(OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst)
len
- (Store [config.PtrSize] {config.fe.TypeBytePtr()} dst ptr mem))
+ (Store {config.fe.TypeBytePtr()} dst ptr mem))
// slice ops
(SlicePtr (SliceMake ptr _ _ )) -> ptr
@@ -66,14 +66,14 @@
(Load <config.fe.TypeInt()>
(OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] ptr)
mem))
-(Store [3*config.PtrSize] dst (SliceMake ptr len cap) mem) ->
- (Store [config.PtrSize] {config.fe.TypeInt()}
+(Store dst (SliceMake ptr len cap) mem) ->
+ (Store {config.fe.TypeInt()}
(OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] dst)
cap
- (Store [config.PtrSize] {config.fe.TypeInt()}
+ (Store {config.fe.TypeInt()}
(OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst)
len
- (Store [config.PtrSize] {config.fe.TypeBytePtr()} dst ptr mem)))
+ (Store {config.fe.TypeBytePtr()} dst ptr mem)))
// interface ops
(ITab (IMake itab _)) -> itab
@@ -85,8 +85,8 @@
(Load <config.fe.TypeBytePtr()>
(OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] ptr)
mem))
-(Store [2*config.PtrSize] dst (IMake itab data) mem) ->
- (Store [config.PtrSize] {config.fe.TypeBytePtr()}
+(Store dst (IMake itab data) mem) ->
+ (Store {config.fe.TypeBytePtr()}
(OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] dst)
data
- (Store [config.PtrSize] {config.fe.TypeUintptr()} dst itab mem))
+ (Store {config.fe.TypeUintptr()} dst itab mem))
diff --git a/src/cmd/compile/internal/ssa/gen/dec64.rules b/src/cmd/compile/internal/ssa/gen/dec64.rules
index 47399e3..6469e59 100644
--- a/src/cmd/compile/internal/ssa/gen/dec64.rules
+++ b/src/cmd/compile/internal/ssa/gen/dec64.rules
@@ -30,17 +30,17 @@
(Load <config.fe.TypeUInt32()> ptr mem)
(Load <config.fe.TypeUInt32()> (OffPtr <config.fe.TypeUInt32().PtrTo()> [4] ptr) mem))
-(Store [8] dst (Int64Make hi lo) mem) && !config.BigEndian ->
- (Store [4] {hi.Type}
+(Store {t} dst (Int64Make hi lo) mem) && t.(Type).Size() == 8 && !config.BigEndian ->
+ (Store {hi.Type}
(OffPtr <hi.Type.PtrTo()> [4] dst)
hi
- (Store [4] {lo.Type} dst lo mem))
+ (Store {lo.Type} dst lo mem))
-(Store [8] dst (Int64Make hi lo) mem) && config.BigEndian ->
- (Store [4] {lo.Type}
+(Store {t} dst (Int64Make hi lo) mem) && t.(Type).Size() == 8 && config.BigEndian ->
+ (Store {lo.Type}
(OffPtr <lo.Type.PtrTo()> [4] dst)
lo
- (Store [4] {hi.Type} dst hi mem))
+ (Store {hi.Type} dst hi mem))
(Arg {n} [off]) && is64BitInt(v.Type) && !config.BigEndian && v.Type.IsSigned() ->
(Int64Make
diff --git a/src/cmd/compile/internal/ssa/gen/generic.rules b/src/cmd/compile/internal/ssa/gen/generic.rules
index 29ff6c1..029a2ca 100644
--- a/src/cmd/compile/internal/ssa/gen/generic.rules
+++ b/src/cmd/compile/internal/ssa/gen/generic.rules
@@ -746,7 +746,7 @@
(NeqSlice x y) -> (NeqPtr (SlicePtr x) (SlicePtr y))
// Load of store of same address, with compatibly typed value and same size
-(Load <t1> p1 (Store [w] p2 x _)) && isSamePtr(p1,p2) && t1.Compare(x.Type)==CMPeq && w == t1.Size() -> x
+(Load <t1> p1 (Store {t2} p2 x _)) && isSamePtr(p1,p2) && t1.Compare(x.Type)==CMPeq && t1.Size() == t2.(Type).Size() -> x
// Collapse OffPtr
(OffPtr (OffPtr p [b]) [a]) -> (OffPtr p [a+b])
@@ -795,35 +795,35 @@
(Store _ (StructMake0) mem) -> mem
(Store dst (StructMake1 <t> f0) mem) ->
- (Store [t.FieldType(0).Size()] {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem)
+ (Store {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem)
(Store dst (StructMake2 <t> f0 f1) mem) ->
- (Store [t.FieldType(1).Size()] {t.FieldType(1)}
+ (Store {t.FieldType(1)}
(OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst)
f1
- (Store [t.FieldType(0).Size()] {t.FieldType(0)}
+ (Store {t.FieldType(0)}
(OffPtr <t.FieldType(0).PtrTo()> [0] dst)
f0 mem))
(Store dst (StructMake3 <t> f0 f1 f2) mem) ->
- (Store [t.FieldType(2).Size()] {t.FieldType(2)}
+ (Store {t.FieldType(2)}
(OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst)
f2
- (Store [t.FieldType(1).Size()] {t.FieldType(1)}
+ (Store {t.FieldType(1)}
(OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst)
f1
- (Store [t.FieldType(0).Size()] {t.FieldType(0)}
+ (Store {t.FieldType(0)}
(OffPtr <t.FieldType(0).PtrTo()> [0] dst)
f0 mem)))
(Store dst (StructMake4 <t> f0 f1 f2 f3) mem) ->
- (Store [t.FieldType(3).Size()] {t.FieldType(3)}
+ (Store {t.FieldType(3)}
(OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] dst)
f3
- (Store [t.FieldType(2).Size()] {t.FieldType(2)}
+ (Store {t.FieldType(2)}
(OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst)
f2
- (Store [t.FieldType(1).Size()] {t.FieldType(1)}
+ (Store {t.FieldType(1)}
(OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst)
f1
- (Store [t.FieldType(0).Size()] {t.FieldType(0)}
+ (Store {t.FieldType(0)}
(OffPtr <t.FieldType(0).PtrTo()> [0] dst)
f0 mem))))
@@ -832,10 +832,10 @@
(StructSelect [0] x:(IData _)) -> x
// un-SSAable values use mem->mem copies
-(Store [size] dst (Load <t> src mem) mem) && !config.fe.CanSSA(t) ->
- (Move [MakeSizeAndAlign(size, t.Alignment()).Int64()] {t} dst src mem)
-(Store [size] dst (Load <t> src mem) (VarDef {x} mem)) && !config.fe.CanSSA(t) ->
- (Move [MakeSizeAndAlign(size, t.Alignment()).Int64()] {t} dst src (VarDef {x} mem))
+(Store {t} dst (Load src mem) mem) && !config.fe.CanSSA(t.(Type)) ->
+ (Move {t} [t.(Type).Size()] dst src mem)
+(Store {t} dst (Load src mem) (VarDef {x} mem)) && !config.fe.CanSSA(t.(Type)) ->
+ (Move {t} [t.(Type).Size()] dst src (VarDef {x} mem))
// array ops
(ArraySelect (ArrayMake1 x)) -> x
@@ -847,7 +847,7 @@
(ArrayMake1 (Load <t.ElemType()> ptr mem))
(Store _ (ArrayMake0) mem) -> mem
-(Store [size] dst (ArrayMake1 e) mem) -> (Store [size] {e.Type} dst e mem)
+(Store dst (ArrayMake1 e) mem) -> (Store {e.Type} dst e mem)
(ArraySelect [0] (Load ptr mem)) -> (Load ptr mem)
diff --git a/src/cmd/compile/internal/ssa/gen/genericOps.go b/src/cmd/compile/internal/ssa/gen/genericOps.go
index 892641d..074b3be 100644
--- a/src/cmd/compile/internal/ssa/gen/genericOps.go
+++ b/src/cmd/compile/internal/ssa/gen/genericOps.go
@@ -286,16 +286,16 @@
{name: "Invalid"}, // unused value
// Memory operations
- {name: "Load", argLength: 2}, // Load from arg0. arg1=memory
- {name: "Store", argLength: 3, typ: "Mem", aux: "SymOff", symEffect: "None"}, // Store arg1 to arg0. arg2=memory, auxint=size, aux=type. Returns memory.
- {name: "Move", argLength: 3, typ: "Mem", aux: "SymSizeAndAlign", symEffect: "None"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size+alignment, aux=type. Returns memory.
- {name: "Zero", argLength: 2, typ: "Mem", aux: "SymSizeAndAlign", symEffect: "None"}, // arg0=destptr, arg1=mem, auxint=size+alignment, aux=type. Returns memory.
+ {name: "Load", argLength: 2}, // Load from arg0. arg1=memory
+ {name: "Store", argLength: 3, typ: "Mem", aux: "Typ"}, // Store arg1 to arg0. arg2=memory, aux=type. Returns memory.
+ {name: "Move", argLength: 3, typ: "Mem", aux: "TypSize"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size, aux=type. Returns memory.
+ {name: "Zero", argLength: 2, typ: "Mem", aux: "TypSize"}, // arg0=destptr, arg1=mem, auxint=size, aux=type. Returns memory.
// Memory operations with write barriers.
// Expand to runtime calls. Write barrier will be removed if write on stack.
- {name: "StoreWB", argLength: 3, typ: "Mem", aux: "SymOff", symEffect: "None"}, // Store arg1 to arg0. arg2=memory, auxint=size, aux=type. Returns memory.
- {name: "MoveWB", argLength: 3, typ: "Mem", aux: "SymSizeAndAlign", symEffect: "None"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size+alignment, aux=type. Returns memory.
- {name: "ZeroWB", argLength: 2, typ: "Mem", aux: "SymSizeAndAlign", symEffect: "None"}, // arg0=destptr, arg1=mem, auxint=size+alignment, aux=type. Returns memory.
+ {name: "StoreWB", argLength: 3, typ: "Mem", aux: "Typ"}, // Store arg1 to arg0. arg2=memory, aux=type. Returns memory.
+ {name: "MoveWB", argLength: 3, typ: "Mem", aux: "TypSize"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size, aux=type. Returns memory.
+ {name: "ZeroWB", argLength: 2, typ: "Mem", aux: "TypSize"}, // arg0=destptr, arg1=mem, auxint=size, aux=type. Returns memory.
// Function calls. Arguments to the call have already been written to the stack.
// Return values appear on the stack. The method receiver, if any, is treated
diff --git a/src/cmd/compile/internal/ssa/gen/rulegen.go b/src/cmd/compile/internal/ssa/gen/rulegen.go
index fd7b33b..3b6e3a9 100644
--- a/src/cmd/compile/internal/ssa/gen/rulegen.go
+++ b/src/cmd/compile/internal/ssa/gen/rulegen.go
@@ -657,14 +657,14 @@
// Sanity check aux, auxint.
if auxint != "" {
switch op.aux {
- case "Bool", "Int8", "Int16", "Int32", "Int64", "Int128", "Float32", "Float64", "SymOff", "SymValAndOff", "SymInt32", "SizeAndAlign", "SymSizeAndAlign":
+ case "Bool", "Int8", "Int16", "Int32", "Int64", "Int128", "Float32", "Float64", "SymOff", "SymValAndOff", "SymInt32", "TypSize":
default:
log.Fatalf("%s: op %s %s can't have auxint", loc, op.name, op.aux)
}
}
if aux != "" {
switch op.aux {
- case "String", "Sym", "SymOff", "SymValAndOff", "SymInt32", "SymSizeAndAlign":
+ case "String", "Sym", "SymOff", "SymValAndOff", "SymInt32", "Typ", "TypSize":
default:
log.Fatalf("%s: op %s %s can't have aux", loc, op.name, op.aux)
}
diff --git a/src/cmd/compile/internal/ssa/loop_test.go b/src/cmd/compile/internal/ssa/loop_test.go
index 40c9aee..901ca5c 100644
--- a/src/cmd/compile/internal/ssa/loop_test.go
+++ b/src/cmd/compile/internal/ssa/loop_test.go
@@ -66,7 +66,7 @@
Goto("b1")),
Bloc("b3",
Valu("retdef", OpVarDef, TypeMem, 0, nil, "mem"),
- Valu("store", OpStore, TypeMem, 8, TypeInt64, "ret", "phisum", "retdef"),
+ Valu("store", OpStore, TypeMem, 0, TypeInt64, "ret", "phisum", "retdef"),
Exit("store")))
CheckFunc(fun.f)
Compile(fun.f)
diff --git a/src/cmd/compile/internal/ssa/nilcheck_test.go b/src/cmd/compile/internal/ssa/nilcheck_test.go
index f12c68c..8f403fb 100644
--- a/src/cmd/compile/internal/ssa/nilcheck_test.go
+++ b/src/cmd/compile/internal/ssa/nilcheck_test.go
@@ -405,7 +405,7 @@
If("bool2", "extra", "exit")),
Bloc("extra",
// prevent fuse from eliminating this block
- Valu("store", OpStore, TypeMem, 8, nil, "ptr1", "nilptr", "mem"),
+ Valu("store", OpStore, TypeMem, 0, ptrType, "ptr1", "nilptr", "mem"),
Goto("exit")),
Bloc("exit",
Valu("phi", OpPhi, TypeMem, 0, nil, "mem", "store"),
diff --git a/src/cmd/compile/internal/ssa/op.go b/src/cmd/compile/internal/ssa/op.go
index f01870e..37c24ee 100644
--- a/src/cmd/compile/internal/ssa/op.go
+++ b/src/cmd/compile/internal/ssa/op.go
@@ -57,21 +57,21 @@
type auxType int8
const (
- auxNone auxType = iota
- auxBool // auxInt is 0/1 for false/true
- auxInt8 // auxInt is an 8-bit integer
- auxInt16 // auxInt is a 16-bit integer
- auxInt32 // auxInt is a 32-bit integer
- auxInt64 // auxInt is a 64-bit integer
- auxInt128 // auxInt represents a 128-bit integer. Always 0.
- auxFloat32 // auxInt is a float32 (encoded with math.Float64bits)
- auxFloat64 // auxInt is a float64 (encoded with math.Float64bits)
- auxSizeAndAlign // auxInt is a SizeAndAlign
- auxString // aux is a string
- auxSym // aux is a symbol
- auxSymOff // aux is a symbol, auxInt is an offset
- auxSymValAndOff // aux is a symbol, auxInt is a ValAndOff
- auxSymSizeAndAlign // aux is a symbol, auxInt is a SizeAndAlign
+ auxNone auxType = iota
+ auxBool // auxInt is 0/1 for false/true
+ auxInt8 // auxInt is an 8-bit integer
+ auxInt16 // auxInt is a 16-bit integer
+ auxInt32 // auxInt is a 32-bit integer
+ auxInt64 // auxInt is a 64-bit integer
+ auxInt128 // auxInt represents a 128-bit integer. Always 0.
+ auxFloat32 // auxInt is a float32 (encoded with math.Float64bits)
+ auxFloat64 // auxInt is a float64 (encoded with math.Float64bits)
+ auxString // aux is a string
+ auxSym // aux is a symbol
+ auxSymOff // aux is a symbol, auxInt is an offset
+ auxSymValAndOff // aux is a symbol, auxInt is a ValAndOff
+ auxTyp // aux is a type
+ auxTypSize // aux is a type, auxInt is a size, must have Aux.(Type).Size() == AuxInt
auxSymInt32 // aux is a symbol, auxInt is a 32-bit integer
)
@@ -154,31 +154,3 @@
}
return makeValAndOff(x.Val(), x.Off()+off)
}
-
-// SizeAndAlign holds both the size and the alignment of a type,
-// used in Zero and Move ops.
-// The high 8 bits hold the alignment.
-// The low 56 bits hold the size.
-type SizeAndAlign int64
-
-func (x SizeAndAlign) Size() int64 {
- return int64(x) & (1<<56 - 1)
-}
-func (x SizeAndAlign) Align() int64 {
- return int64(uint64(x) >> 56)
-}
-func (x SizeAndAlign) Int64() int64 {
- return int64(x)
-}
-func (x SizeAndAlign) String() string {
- return fmt.Sprintf("size=%d,align=%d", x.Size(), x.Align())
-}
-func MakeSizeAndAlign(size, align int64) SizeAndAlign {
- if size&^(1<<56-1) != 0 {
- panic("size too big in SizeAndAlign")
- }
- if align >= 1<<8 {
- panic("alignment too big in SizeAndAlign")
- }
- return SizeAndAlign(size | align<<56)
-}
diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index 9abd265..e8f2b1c 100644
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -21557,46 +21557,40 @@
generic: true,
},
{
- name: "Store",
- auxType: auxSymOff,
- argLen: 3,
- symEffect: SymNone,
- generic: true,
+ name: "Store",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
},
{
- name: "Move",
- auxType: auxSymSizeAndAlign,
- argLen: 3,
- symEffect: SymNone,
- generic: true,
+ name: "Move",
+ auxType: auxTypSize,
+ argLen: 3,
+ generic: true,
},
{
- name: "Zero",
- auxType: auxSymSizeAndAlign,
- argLen: 2,
- symEffect: SymNone,
- generic: true,
+ name: "Zero",
+ auxType: auxTypSize,
+ argLen: 2,
+ generic: true,
},
{
- name: "StoreWB",
- auxType: auxSymOff,
- argLen: 3,
- symEffect: SymNone,
- generic: true,
+ name: "StoreWB",
+ auxType: auxTyp,
+ argLen: 3,
+ generic: true,
},
{
- name: "MoveWB",
- auxType: auxSymSizeAndAlign,
- argLen: 3,
- symEffect: SymNone,
- generic: true,
+ name: "MoveWB",
+ auxType: auxTypSize,
+ argLen: 3,
+ generic: true,
},
{
- name: "ZeroWB",
- auxType: auxSymSizeAndAlign,
- argLen: 2,
- symEffect: SymNone,
- generic: true,
+ name: "ZeroWB",
+ auxType: auxTypSize,
+ argLen: 2,
+ generic: true,
},
{
name: "ClosureCall",
diff --git a/src/cmd/compile/internal/ssa/passbm_test.go b/src/cmd/compile/internal/ssa/passbm_test.go
index e4bb0b8..f40690a 100644
--- a/src/cmd/compile/internal/ssa/passbm_test.go
+++ b/src/cmd/compile/internal/ssa/passbm_test.go
@@ -77,15 +77,15 @@
Valu(valn("addr", i, 1), OpAddr, ptrType, 0, nil, "sb"),
Valu(valn("addr", i, 2), OpAddr, ptrType, 0, nil, "sb"),
Valu(valn("addr", i, 3), OpAddr, ptrType, 0, nil, "sb"),
- Valu(valn("zero", i, 1), OpZero, TypeMem, 8, nil, valn("addr", i, 3),
+ Valu(valn("zero", i, 1), OpZero, TypeMem, 8, elemType, valn("addr", i, 3),
valn("store", i-1, 4)),
- Valu(valn("store", i, 1), OpStore, TypeMem, 0, nil, valn("addr", i, 1),
+ Valu(valn("store", i, 1), OpStore, TypeMem, 0, elemType, valn("addr", i, 1),
valn("v", i, 0), valn("zero", i, 1)),
- Valu(valn("store", i, 2), OpStore, TypeMem, 0, nil, valn("addr", i, 2),
+ Valu(valn("store", i, 2), OpStore, TypeMem, 0, elemType, valn("addr", i, 2),
valn("v", i, 0), valn("store", i, 1)),
- Valu(valn("store", i, 3), OpStore, TypeMem, 0, nil, valn("addr", i, 1),
+ Valu(valn("store", i, 3), OpStore, TypeMem, 0, elemType, valn("addr", i, 1),
valn("v", i, 0), valn("store", i, 2)),
- Valu(valn("store", i, 4), OpStore, TypeMem, 0, nil, valn("addr", i, 3),
+ Valu(valn("store", i, 4), OpStore, TypeMem, 0, elemType, valn("addr", i, 3),
valn("v", i, 0), valn("store", i, 3)),
Goto(blockn(i+1))))
}
diff --git a/src/cmd/compile/internal/ssa/rewrite386.go b/src/cmd/compile/internal/ssa/rewrite386.go
index 881a956..0e7c54b 100644
--- a/src/cmd/compile/internal/ssa/rewrite386.go
+++ b/src/cmd/compile/internal/ssa/rewrite386.go
@@ -11405,31 +11405,29 @@
func rewriteValue386_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(Op386MOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVBload, config.fe.TypeUInt8())
@@ -11439,17 +11437,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVWstore dst (MOVWload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(Op386MOVWstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVWload, config.fe.TypeUInt16())
@@ -11459,17 +11456,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVLstore dst (MOVLload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(Op386MOVLstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, Op386MOVLload, config.fe.TypeUInt32())
@@ -11479,17 +11475,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(Op386MOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -11508,17 +11503,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Move [5] dst src mem)
+ // cond:
// result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 5 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 5) {
- break
- }
v.reset(Op386MOVBstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -11537,17 +11531,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Move [6] dst src mem)
+ // cond:
// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 6) {
- break
- }
v.reset(Op386MOVWstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -11566,17 +11559,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Move [7] dst src mem)
+ // cond:
// result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 7 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 7) {
- break
- }
v.reset(Op386MOVLstore)
v.AuxInt = 3
v.AddArg(dst)
@@ -11595,17 +11587,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Move [8] dst src mem)
+ // cond:
// result: (MOVLstore [4] dst (MOVLload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8) {
- break
- }
v.reset(Op386MOVLstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -11625,24 +11616,24 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size()%4 != 0
- // result: (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%4] (ADDLconst <dst.Type> dst [SizeAndAlign(s).Size()%4]) (ADDLconst <src.Type> src [SizeAndAlign(s).Size()%4]) (MOVLstore dst (MOVLload src mem) mem))
+ // cond: s > 8 && s%4 != 0
+ // result: (Move [s-s%4] (ADDLconst <dst.Type> dst [s%4]) (ADDLconst <src.Type> src [s%4]) (MOVLstore dst (MOVLload src mem) mem))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size()%4 != 0) {
+ if !(s > 8 && s%4 != 0) {
break
}
v.reset(OpMove)
- v.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%4
+ v.AuxInt = s - s%4
v0 := b.NewValue0(v.Pos, Op386ADDLconst, dst.Type)
- v0.AuxInt = SizeAndAlign(s).Size() % 4
+ v0.AuxInt = s % 4
v0.AddArg(dst)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, Op386ADDLconst, src.Type)
- v1.AuxInt = SizeAndAlign(s).Size() % 4
+ v1.AuxInt = s % 4
v1.AddArg(src)
v.AddArg(v1)
v2 := b.NewValue0(v.Pos, Op386MOVLstore, TypeMem)
@@ -11656,39 +11647,39 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() <= 4*128 && SizeAndAlign(s).Size()%4 == 0 && !config.noDuffDevice
- // result: (DUFFCOPY [10*(128-SizeAndAlign(s).Size()/4)] dst src mem)
+ // cond: s > 8 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice
+ // result: (DUFFCOPY [10*(128-s/4)] dst src mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() <= 4*128 && SizeAndAlign(s).Size()%4 == 0 && !config.noDuffDevice) {
+ if !(s > 8 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice) {
break
}
v.reset(Op386DUFFCOPY)
- v.AuxInt = 10 * (128 - SizeAndAlign(s).Size()/4)
+ v.AuxInt = 10 * (128 - s/4)
v.AddArg(dst)
v.AddArg(src)
v.AddArg(mem)
return true
}
// match: (Move [s] dst src mem)
- // cond: (SizeAndAlign(s).Size() > 4*128 || config.noDuffDevice) && SizeAndAlign(s).Size()%4 == 0
- // result: (REPMOVSL dst src (MOVLconst [SizeAndAlign(s).Size()/4]) mem)
+ // cond: (s > 4*128 || config.noDuffDevice) && s%4 == 0
+ // result: (REPMOVSL dst src (MOVLconst [s/4]) mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !((SizeAndAlign(s).Size() > 4*128 || config.noDuffDevice) && SizeAndAlign(s).Size()%4 == 0) {
+ if !((s > 4*128 || config.noDuffDevice) && s%4 == 0) {
break
}
v.reset(Op386REPMOVSL)
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, Op386MOVLconst, config.fe.TypeUInt32())
- v0.AuxInt = SizeAndAlign(s).Size() / 4
+ v0.AuxInt = s / 4
v.AddArg(v0)
v.AddArg(mem)
return true
@@ -12941,17 +12932,15 @@
func rewriteValue386_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (MOVSDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(Op386MOVSDstore)
@@ -12960,17 +12949,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (MOVSSstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(Op386MOVSSstore)
@@ -12979,48 +12966,51 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4
// result: (MOVLstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 4) {
+ break
+ }
v.reset(Op386MOVLstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(Op386MOVWstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(Op386MOVBstore)
v.AddArg(ptr)
v.AddArg(val)
@@ -13241,78 +13231,73 @@
func rewriteValue386_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] destptr mem)
+ // cond:
// result: (MOVBstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVBstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] destptr mem)
+ // cond:
// result: (MOVWstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVWstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] destptr mem)
+ // cond:
// result: (MOVLstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVLstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] destptr mem)
+ // cond:
// result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 2)
v.AddArg(destptr)
@@ -13323,16 +13308,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Zero [5] destptr mem)
+ // cond:
// result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 5) {
+ if v.AuxInt != 5 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -13343,16 +13327,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Zero [6] destptr mem)
+ // cond:
// result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 6) {
+ if v.AuxInt != 6 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVWstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -13363,16 +13346,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Zero [7] destptr mem)
+ // cond:
// result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 7) {
+ if v.AuxInt != 7 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 3)
v.AddArg(destptr)
@@ -13384,19 +13366,19 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size()%4 != 0 && SizeAndAlign(s).Size() > 4
- // result: (Zero [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%4] (ADDLconst destptr [SizeAndAlign(s).Size()%4]) (MOVLstoreconst [0] destptr mem))
+ // cond: s%4 != 0 && s > 4
+ // result: (Zero [s-s%4] (ADDLconst destptr [s%4]) (MOVLstoreconst [0] destptr mem))
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%4 != 0 && SizeAndAlign(s).Size() > 4) {
+ if !(s%4 != 0 && s > 4) {
break
}
v.reset(OpZero)
- v.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%4
+ v.AuxInt = s - s%4
v0 := b.NewValue0(v.Pos, Op386ADDLconst, config.fe.TypeUInt32())
- v0.AuxInt = SizeAndAlign(s).Size() % 4
+ v0.AuxInt = s % 4
v0.AddArg(destptr)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, Op386MOVLstoreconst, TypeMem)
@@ -13406,16 +13388,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Zero [8] destptr mem)
+ // cond:
// result: (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8) {
+ if v.AuxInt != 8 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -13426,16 +13407,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 12
+ // match: (Zero [12] destptr mem)
+ // cond:
// result: (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem)))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 12) {
+ if v.AuxInt != 12 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 8)
v.AddArg(destptr)
@@ -13450,16 +13430,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 16
+ // match: (Zero [16] destptr mem)
+ // cond:
// result: (MOVLstoreconst [makeValAndOff(0,12)] destptr (MOVLstoreconst [makeValAndOff(0,8)] destptr (MOVLstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 16) {
+ if v.AuxInt != 16 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(Op386MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 12)
v.AddArg(destptr)
@@ -13479,17 +13458,17 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size() <= 4*128 && SizeAndAlign(s).Size()%4 == 0 && !config.noDuffDevice
- // result: (DUFFZERO [1*(128-SizeAndAlign(s).Size()/4)] destptr (MOVLconst [0]) mem)
+ // cond: s > 16 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice
+ // result: (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem)
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size() <= 4*128 && SizeAndAlign(s).Size()%4 == 0 && !config.noDuffDevice) {
+ if !(s > 16 && s <= 4*128 && s%4 == 0 && !config.noDuffDevice) {
break
}
v.reset(Op386DUFFZERO)
- v.AuxInt = 1 * (128 - SizeAndAlign(s).Size()/4)
+ v.AuxInt = 1 * (128 - s/4)
v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLconst, config.fe.TypeUInt32())
v0.AuxInt = 0
@@ -13498,19 +13477,19 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: (SizeAndAlign(s).Size() > 4*128 || (config.noDuffDevice && SizeAndAlign(s).Size() > 16)) && SizeAndAlign(s).Size()%4 == 0
- // result: (REPSTOSL destptr (MOVLconst [SizeAndAlign(s).Size()/4]) (MOVLconst [0]) mem)
+ // cond: (s > 4*128 || (config.noDuffDevice && s > 16)) && s%4 == 0
+ // result: (REPSTOSL destptr (MOVLconst [s/4]) (MOVLconst [0]) mem)
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !((SizeAndAlign(s).Size() > 4*128 || (config.noDuffDevice && SizeAndAlign(s).Size() > 16)) && SizeAndAlign(s).Size()%4 == 0) {
+ if !((s > 4*128 || (config.noDuffDevice && s > 16)) && s%4 == 0) {
break
}
v.reset(Op386REPSTOSL)
v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, Op386MOVLconst, config.fe.TypeUInt32())
- v0.AuxInt = SizeAndAlign(s).Size() / 4
+ v0.AuxInt = s / 4
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, Op386MOVLconst, config.fe.TypeUInt32())
v1.AuxInt = 0
diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go
index b75b78d..3774112 100644
--- a/src/cmd/compile/internal/ssa/rewriteAMD64.go
+++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go
@@ -20000,31 +20000,29 @@
func rewriteValueAMD64_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpAMD64MOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVBload, config.fe.TypeUInt8())
@@ -20034,17 +20032,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVWstore dst (MOVWload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpAMD64MOVWstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVWload, config.fe.TypeUInt16())
@@ -20054,17 +20051,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVLstore dst (MOVLload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpAMD64MOVLstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVLload, config.fe.TypeUInt32())
@@ -20074,17 +20070,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Move [8] dst src mem)
+ // cond:
// result: (MOVQstore dst (MOVQload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8) {
- break
- }
v.reset(OpAMD64MOVQstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, config.fe.TypeUInt64())
@@ -20094,17 +20089,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 16
+ // match: (Move [16] dst src mem)
+ // cond:
// result: (MOVOstore dst (MOVOload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 16) {
- break
- }
v.reset(OpAMD64MOVOstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVOload, TypeInt128)
@@ -20114,17 +20108,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpAMD64MOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -20143,17 +20136,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Move [5] dst src mem)
+ // cond:
// result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 5 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 5) {
- break
- }
v.reset(OpAMD64MOVBstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -20172,17 +20164,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Move [6] dst src mem)
+ // cond:
// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 6) {
- break
- }
v.reset(OpAMD64MOVWstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -20201,17 +20192,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Move [7] dst src mem)
+ // cond:
// result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 7 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 7) {
- break
- }
v.reset(OpAMD64MOVLstore)
v.AuxInt = 3
v.AddArg(dst)
@@ -20231,21 +20221,21 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() < 16
- // result: (MOVQstore [SizeAndAlign(s).Size()-8] dst (MOVQload [SizeAndAlign(s).Size()-8] src mem) (MOVQstore dst (MOVQload src mem) mem))
+ // cond: s > 8 && s < 16
+ // result: (MOVQstore [s-8] dst (MOVQload [s-8] src mem) (MOVQstore dst (MOVQload src mem) mem))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 8 && SizeAndAlign(s).Size() < 16) {
+ if !(s > 8 && s < 16) {
break
}
v.reset(OpAMD64MOVQstore)
- v.AuxInt = SizeAndAlign(s).Size() - 8
+ v.AuxInt = s - 8
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQload, config.fe.TypeUInt64())
- v0.AuxInt = SizeAndAlign(s).Size() - 8
+ v0.AuxInt = s - 8
v0.AddArg(src)
v0.AddArg(mem)
v.AddArg(v0)
@@ -20260,24 +20250,24 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 <= 8
- // result: (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%16] (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()%16]) (OffPtr <src.Type> src [SizeAndAlign(s).Size()%16]) (MOVQstore dst (MOVQload src mem) mem))
+ // cond: s > 16 && s%16 != 0 && s%16 <= 8
+ // result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVQstore dst (MOVQload src mem) mem))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 <= 8) {
+ if !(s > 16 && s%16 != 0 && s%16 <= 8) {
break
}
v.reset(OpMove)
- v.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%16
+ v.AuxInt = s - s%16
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
- v0.AuxInt = SizeAndAlign(s).Size() % 16
+ v0.AuxInt = s % 16
v0.AddArg(dst)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
- v1.AuxInt = SizeAndAlign(s).Size() % 16
+ v1.AuxInt = s % 16
v1.AddArg(src)
v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVQstore, TypeMem)
@@ -20291,24 +20281,24 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 > 8
- // result: (Move [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%16] (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()%16]) (OffPtr <src.Type> src [SizeAndAlign(s).Size()%16]) (MOVOstore dst (MOVOload src mem) mem))
+ // cond: s > 16 && s%16 != 0 && s%16 > 8
+ // result: (Move [s-s%16] (OffPtr <dst.Type> dst [s%16]) (OffPtr <src.Type> src [s%16]) (MOVOstore dst (MOVOload src mem) mem))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 16 && SizeAndAlign(s).Size()%16 != 0 && SizeAndAlign(s).Size()%16 > 8) {
+ if !(s > 16 && s%16 != 0 && s%16 > 8) {
break
}
v.reset(OpMove)
- v.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%16
+ v.AuxInt = s - s%16
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
- v0.AuxInt = SizeAndAlign(s).Size() % 16
+ v0.AuxInt = s % 16
v0.AddArg(dst)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
- v1.AuxInt = SizeAndAlign(s).Size() % 16
+ v1.AuxInt = s % 16
v1.AddArg(src)
v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpAMD64MOVOstore, TypeMem)
@@ -20322,39 +20312,39 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() >= 32 && SizeAndAlign(s).Size() <= 16*64 && SizeAndAlign(s).Size()%16 == 0 && !config.noDuffDevice
- // result: (DUFFCOPY [14*(64-SizeAndAlign(s).Size()/16)] dst src mem)
+ // cond: s >= 32 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice
+ // result: (DUFFCOPY [14*(64-s/16)] dst src mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() >= 32 && SizeAndAlign(s).Size() <= 16*64 && SizeAndAlign(s).Size()%16 == 0 && !config.noDuffDevice) {
+ if !(s >= 32 && s <= 16*64 && s%16 == 0 && !config.noDuffDevice) {
break
}
v.reset(OpAMD64DUFFCOPY)
- v.AuxInt = 14 * (64 - SizeAndAlign(s).Size()/16)
+ v.AuxInt = 14 * (64 - s/16)
v.AddArg(dst)
v.AddArg(src)
v.AddArg(mem)
return true
}
// match: (Move [s] dst src mem)
- // cond: (SizeAndAlign(s).Size() > 16*64 || config.noDuffDevice) && SizeAndAlign(s).Size()%8 == 0
- // result: (REPMOVSQ dst src (MOVQconst [SizeAndAlign(s).Size()/8]) mem)
+ // cond: (s > 16*64 || config.noDuffDevice) && s%8 == 0
+ // result: (REPMOVSQ dst src (MOVQconst [s/8]) mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !((SizeAndAlign(s).Size() > 16*64 || config.noDuffDevice) && SizeAndAlign(s).Size()%8 == 0) {
+ if !((s > 16*64 || config.noDuffDevice) && s%8 == 0) {
break
}
v.reset(OpAMD64REPMOVSQ)
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, config.fe.TypeUInt64())
- v0.AuxInt = SizeAndAlign(s).Size() / 8
+ v0.AuxInt = s / 8
v.AddArg(v0)
v.AddArg(mem)
return true
@@ -21903,17 +21893,15 @@
func rewriteValueAMD64_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (MOVSDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpAMD64MOVSDstore)
@@ -21922,17 +21910,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (MOVSSstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpAMD64MOVSSstore)
@@ -21941,64 +21927,68 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8
// result: (MOVQstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 8) {
+ break
+ }
v.reset(OpAMD64MOVQstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4
// result: (MOVLstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 4) {
+ break
+ }
v.reset(OpAMD64MOVLstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpAMD64MOVWstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpAMD64MOVBstore)
v.AddArg(ptr)
v.AddArg(val)
@@ -22277,94 +22267,88 @@
func rewriteValueAMD64_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] destptr mem)
+ // cond:
// result: (MOVBstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] destptr mem)
+ // cond:
// result: (MOVWstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] destptr mem)
+ // cond:
// result: (MOVLstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Zero [8] destptr mem)
+ // cond:
// result: (MOVQstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8) {
+ if v.AuxInt != 8 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] destptr mem)
+ // cond:
// result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVWstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 2)
v.AddArg(destptr)
@@ -22375,16 +22359,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Zero [5] destptr mem)
+ // cond:
// result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 5) {
+ if v.AuxInt != 5 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVBstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -22395,16 +22378,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Zero [6] destptr mem)
+ // cond:
// result: (MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 6) {
+ if v.AuxInt != 6 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVWstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -22415,16 +22397,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Zero [7] destptr mem)
+ // cond:
// result: (MOVLstoreconst [makeValAndOff(0,3)] destptr (MOVLstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 7) {
+ if v.AuxInt != 7 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVLstoreconst)
v.AuxInt = makeValAndOff(0, 3)
v.AddArg(destptr)
@@ -22436,19 +22417,19 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8
- // result: (Zero [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8] (OffPtr <destptr.Type> destptr [SizeAndAlign(s).Size()%8]) (MOVQstoreconst [0] destptr mem))
+ // cond: s%8 != 0 && s > 8
+ // result: (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8]) (MOVQstoreconst [0] destptr mem))
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8) {
+ if !(s%8 != 0 && s > 8) {
break
}
v.reset(OpZero)
- v.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%8
+ v.AuxInt = s - s%8
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() % 8
+ v0.AuxInt = s % 8
v0.AddArg(destptr)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQstoreconst, TypeMem)
@@ -22458,16 +22439,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 16
+ // match: (Zero [16] destptr mem)
+ // cond:
// result: (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 16) {
+ if v.AuxInt != 16 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, 8)
v.AddArg(destptr)
@@ -22478,16 +22458,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 24
+ // match: (Zero [24] destptr mem)
+ // cond:
// result: (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem)))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 24) {
+ if v.AuxInt != 24 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, 16)
v.AddArg(destptr)
@@ -22502,16 +22481,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 32
+ // match: (Zero [32] destptr mem)
+ // cond:
// result: (MOVQstoreconst [makeValAndOff(0,24)] destptr (MOVQstoreconst [makeValAndOff(0,16)] destptr (MOVQstoreconst [makeValAndOff(0,8)] destptr (MOVQstoreconst [0] destptr mem))))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 32) {
+ if v.AuxInt != 32 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpAMD64MOVQstoreconst)
v.AuxInt = makeValAndOff(0, 24)
v.AddArg(destptr)
@@ -22531,17 +22509,17 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size()%16 != 0 && !config.noDuffDevice
- // result: (Zero [SizeAndAlign(s).Size()-8] (OffPtr <destptr.Type> [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem))
+ // cond: s <= 1024 && s%8 == 0 && s%16 != 0 && !config.noDuffDevice
+ // result: (Zero [s-8] (OffPtr <destptr.Type> [8] destptr) (MOVQstore destptr (MOVQconst [0]) mem))
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size()%16 != 0 && !config.noDuffDevice) {
+ if !(s <= 1024 && s%8 == 0 && s%16 != 0 && !config.noDuffDevice) {
break
}
v.reset(OpZero)
- v.AuxInt = SizeAndAlign(s).Size() - 8
+ v.AuxInt = s - 8
v0 := b.NewValue0(v.Pos, OpOffPtr, destptr.Type)
v0.AuxInt = 8
v0.AddArg(destptr)
@@ -22556,17 +22534,17 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%16 == 0 && !config.noDuffDevice
- // result: (DUFFZERO [SizeAndAlign(s).Size()] destptr (MOVOconst [0]) mem)
+ // cond: s <= 1024 && s%16 == 0 && !config.noDuffDevice
+ // result: (DUFFZERO [s] destptr (MOVOconst [0]) mem)
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() <= 1024 && SizeAndAlign(s).Size()%16 == 0 && !config.noDuffDevice) {
+ if !(s <= 1024 && s%16 == 0 && !config.noDuffDevice) {
break
}
v.reset(OpAMD64DUFFZERO)
- v.AuxInt = SizeAndAlign(s).Size()
+ v.AuxInt = s
v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVOconst, TypeInt128)
v0.AuxInt = 0
@@ -22575,19 +22553,19 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: (SizeAndAlign(s).Size() > 1024 || (config.noDuffDevice && SizeAndAlign(s).Size() > 32)) && SizeAndAlign(s).Size()%8 == 0
- // result: (REPSTOSQ destptr (MOVQconst [SizeAndAlign(s).Size()/8]) (MOVQconst [0]) mem)
+ // cond: (s > 1024 || (config.noDuffDevice && s > 32)) && s%8 == 0
+ // result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !((SizeAndAlign(s).Size() > 1024 || (config.noDuffDevice && SizeAndAlign(s).Size() > 32)) && SizeAndAlign(s).Size()%8 == 0) {
+ if !((s > 1024 || (config.noDuffDevice && s > 32)) && s%8 == 0) {
break
}
v.reset(OpAMD64REPSTOSQ)
v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpAMD64MOVQconst, config.fe.TypeUInt64())
- v0.AuxInt = SizeAndAlign(s).Size() / 8
+ v0.AuxInt = s / 8
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpAMD64MOVQconst, config.fe.TypeUInt64())
v1.AuxInt = 0
diff --git a/src/cmd/compile/internal/ssa/rewriteARM.go b/src/cmd/compile/internal/ssa/rewriteARM.go
index 4dd60d5..fa77dea 100644
--- a/src/cmd/compile/internal/ssa/rewriteARM.go
+++ b/src/cmd/compile/internal/ssa/rewriteARM.go
@@ -14990,31 +14990,29 @@
func rewriteValueARM_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpARMMOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARMMOVBUload, config.fe.TypeUInt8())
@@ -15024,15 +15022,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [2] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore dst (MOVHUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpARMMOVHstore)
@@ -15044,17 +15045,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpARMMOVBstore)
v.AuxInt = 1
v.AddArg(dst)
@@ -15073,15 +15073,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore dst (MOVWload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpARMMOVWstore)
@@ -15093,15 +15096,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] dst (MOVHUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpARMMOVHstore)
@@ -15122,17 +15128,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVBstore [3] dst (MOVBUload [3] src mem) (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpARMMOVBstore)
v.AuxInt = 3
v.AddArg(dst)
@@ -15169,17 +15174,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpARMMOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -15207,41 +15211,43 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size()%4 == 0 && SizeAndAlign(s).Size() > 4 && SizeAndAlign(s).Size() <= 512 && SizeAndAlign(s).Align()%4 == 0 && !config.noDuffDevice
- // result: (DUFFCOPY [8 * (128 - int64(SizeAndAlign(s).Size()/4))] dst src mem)
+ // match: (Move [s] {t} dst src mem)
+ // cond: s%4 == 0 && s > 4 && s <= 512 && t.(Type).Alignment()%4 == 0 && !config.noDuffDevice
+ // result: (DUFFCOPY [8 * (128 - int64(s/4))] dst src mem)
for {
s := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size()%4 == 0 && SizeAndAlign(s).Size() > 4 && SizeAndAlign(s).Size() <= 512 && SizeAndAlign(s).Align()%4 == 0 && !config.noDuffDevice) {
+ if !(s%4 == 0 && s > 4 && s <= 512 && t.(Type).Alignment()%4 == 0 && !config.noDuffDevice) {
break
}
v.reset(OpARMDUFFCOPY)
- v.AuxInt = 8 * (128 - int64(SizeAndAlign(s).Size()/4))
+ v.AuxInt = 8 * (128 - int64(s/4))
v.AddArg(dst)
v.AddArg(src)
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%4 != 0
- // result: (LoweredMove [SizeAndAlign(s).Align()] dst src (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Move [s] {t} dst src mem)
+ // cond: (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%4 != 0
+ // result: (LoweredMove [t.(Type).Alignment()] dst src (ADDconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !((SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%4 != 0) {
+ if !((s > 512 || config.noDuffDevice) || t.(Type).Alignment()%4 != 0) {
break
}
v.reset(OpARMLoweredMove)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpARMADDconst, src.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(src)
v.AddArg(v0)
v.AddArg(mem)
@@ -16574,49 +16580,49 @@
func rewriteValueARM_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpARMMOVBstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVHstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpARMMOVHstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: !is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && !is32BitFloat(val.Type)
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(!is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && !is32BitFloat(val.Type)) {
break
}
v.reset(OpARMMOVWstore)
@@ -16625,17 +16631,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (MOVFstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpARMMOVFstore)
@@ -16644,17 +16648,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (MOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpARMMOVDstore)
@@ -16877,30 +16879,28 @@
func rewriteValueARM_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] ptr mem)
+ // cond:
// result: (MOVBstore ptr (MOVWconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARMMOVBstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, config.fe.TypeUInt32())
@@ -16909,14 +16909,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [2] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore ptr (MOVWconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpARMMOVHstore)
@@ -16927,16 +16930,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] ptr mem)
+ // cond:
// result: (MOVBstore [1] ptr (MOVWconst [0]) (MOVBstore [0] ptr (MOVWconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARMMOVBstore)
v.AuxInt = 1
v.AddArg(ptr)
@@ -16953,14 +16955,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [4] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore ptr (MOVWconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpARMMOVWstore)
@@ -16971,14 +16976,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [4] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] ptr (MOVWconst [0]) (MOVHstore [0] ptr (MOVWconst [0]) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpARMMOVHstore)
@@ -16997,16 +17005,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] ptr mem)
+ // cond:
// result: (MOVBstore [3] ptr (MOVWconst [0]) (MOVBstore [2] ptr (MOVWconst [0]) (MOVBstore [1] ptr (MOVWconst [0]) (MOVBstore [0] ptr (MOVWconst [0]) mem))))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARMMOVBstore)
v.AuxInt = 3
v.AddArg(ptr)
@@ -17037,16 +17044,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] ptr mem)
+ // cond:
// result: (MOVBstore [2] ptr (MOVWconst [0]) (MOVBstore [1] ptr (MOVWconst [0]) (MOVBstore [0] ptr (MOVWconst [0]) mem)))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARMMOVBstore)
v.AuxInt = 2
v.AddArg(ptr)
@@ -17070,18 +17076,19 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size()%4 == 0 && SizeAndAlign(s).Size() > 4 && SizeAndAlign(s).Size() <= 512 && SizeAndAlign(s).Align()%4 == 0 && !config.noDuffDevice
- // result: (DUFFZERO [4 * (128 - int64(SizeAndAlign(s).Size()/4))] ptr (MOVWconst [0]) mem)
+ // match: (Zero [s] {t} ptr mem)
+ // cond: s%4 == 0 && s > 4 && s <= 512 && t.(Type).Alignment()%4 == 0 && !config.noDuffDevice
+ // result: (DUFFZERO [4 * (128 - int64(s/4))] ptr (MOVWconst [0]) mem)
for {
s := v.AuxInt
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%4 == 0 && SizeAndAlign(s).Size() > 4 && SizeAndAlign(s).Size() <= 512 && SizeAndAlign(s).Align()%4 == 0 && !config.noDuffDevice) {
+ if !(s%4 == 0 && s > 4 && s <= 512 && t.(Type).Alignment()%4 == 0 && !config.noDuffDevice) {
break
}
v.reset(OpARMDUFFZERO)
- v.AuxInt = 4 * (128 - int64(SizeAndAlign(s).Size()/4))
+ v.AuxInt = 4 * (128 - int64(s/4))
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMMOVWconst, config.fe.TypeUInt32())
v0.AuxInt = 0
@@ -17089,21 +17096,22 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%4 != 0
- // result: (LoweredZero [SizeAndAlign(s).Align()] ptr (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) (MOVWconst [0]) mem)
+ // match: (Zero [s] {t} ptr mem)
+ // cond: (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%4 != 0
+ // result: (LoweredZero [t.(Type).Alignment()] ptr (ADDconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)]) (MOVWconst [0]) mem)
for {
s := v.AuxInt
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !((SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%4 != 0) {
+ if !((s > 512 || config.noDuffDevice) || t.(Type).Alignment()%4 != 0) {
break
}
v.reset(OpARMLoweredZero)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARMADDconst, ptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(ptr)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpARMMOVWconst, config.fe.TypeUInt32())
diff --git a/src/cmd/compile/internal/ssa/rewriteARM64.go b/src/cmd/compile/internal/ssa/rewriteARM64.go
index e340568..f3a7bff 100644
--- a/src/cmd/compile/internal/ssa/rewriteARM64.go
+++ b/src/cmd/compile/internal/ssa/rewriteARM64.go
@@ -12216,31 +12216,29 @@
func rewriteValueARM64_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpARM64MOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVBUload, config.fe.TypeUInt8())
@@ -12250,17 +12248,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVHstore dst (MOVHUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpARM64MOVHstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVHUload, config.fe.TypeUInt16())
@@ -12270,17 +12267,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVWstore dst (MOVWUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpARM64MOVWstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVWUload, config.fe.TypeUInt32())
@@ -12290,17 +12286,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Move [8] dst src mem)
+ // cond:
// result: (MOVDstore dst (MOVDload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8) {
- break
- }
v.reset(OpARM64MOVDstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpARM64MOVDload, config.fe.TypeUInt64())
@@ -12310,17 +12305,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpARM64MOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -12339,17 +12333,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Move [5] dst src mem)
+ // cond:
// result: (MOVBstore [4] dst (MOVBUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 5 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 5) {
- break
- }
v.reset(OpARM64MOVBstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -12368,17 +12361,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Move [6] dst src mem)
+ // cond:
// result: (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 6) {
- break
- }
v.reset(OpARM64MOVHstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -12397,17 +12389,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Move [7] dst src mem)
+ // cond:
// result: (MOVBstore [6] dst (MOVBUload [6] src mem) (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 7 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 7) {
- break
- }
v.reset(OpARM64MOVBstore)
v.AuxInt = 6
v.AddArg(dst)
@@ -12435,17 +12426,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 12
+ // match: (Move [12] dst src mem)
+ // cond:
// result: (MOVWstore [8] dst (MOVWUload [8] src mem) (MOVDstore dst (MOVDload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 12 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 12) {
- break
- }
v.reset(OpARM64MOVWstore)
v.AuxInt = 8
v.AddArg(dst)
@@ -12464,17 +12454,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 16
+ // match: (Move [16] dst src mem)
+ // cond:
// result: (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 16) {
- break
- }
v.reset(OpARM64MOVDstore)
v.AuxInt = 8
v.AddArg(dst)
@@ -12493,17 +12482,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 24
+ // match: (Move [24] dst src mem)
+ // cond:
// result: (MOVDstore [16] dst (MOVDload [16] src mem) (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 24 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 24) {
- break
- }
v.reset(OpARM64MOVDstore)
v.AuxInt = 16
v.AddArg(dst)
@@ -12532,28 +12520,28 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8
- // result: (Move [MakeSizeAndAlign(SizeAndAlign(s).Size()%8, 1).Int64()] (OffPtr <dst.Type> dst [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8]) (OffPtr <src.Type> src [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8]) (Move [MakeSizeAndAlign(SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8, 1).Int64()] dst src mem))
+ // cond: s%8 != 0 && s > 8
+ // result: (Move [s%8] (OffPtr <dst.Type> dst [s-s%8]) (OffPtr <src.Type> src [s-s%8]) (Move [s-s%8] dst src mem))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8) {
+ if !(s%8 != 0 && s > 8) {
break
}
v.reset(OpMove)
- v.AuxInt = MakeSizeAndAlign(SizeAndAlign(s).Size()%8, 1).Int64()
+ v.AuxInt = s % 8
v0 := b.NewValue0(v.Pos, OpOffPtr, dst.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%8
+ v0.AuxInt = s - s%8
v0.AddArg(dst)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpOffPtr, src.Type)
- v1.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%8
+ v1.AuxInt = s - s%8
v1.AddArg(src)
v.AddArg(v1)
v2 := b.NewValue0(v.Pos, OpMove, TypeMem)
- v2.AuxInt = MakeSizeAndAlign(SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8, 1).Int64()
+ v2.AuxInt = s - s%8
v2.AddArg(dst)
v2.AddArg(src)
v2.AddArg(mem)
@@ -12561,39 +12549,39 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && !config.noDuffDevice
- // result: (DUFFCOPY [8 * (128 - int64(SizeAndAlign(s).Size()/8))] dst src mem)
+ // cond: s%8 == 0 && s > 24 && s <= 8*128 && !config.noDuffDevice
+ // result: (DUFFCOPY [8 * (128 - int64(s/8))] dst src mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && !config.noDuffDevice) {
+ if !(s%8 == 0 && s > 24 && s <= 8*128 && !config.noDuffDevice) {
break
}
v.reset(OpARM64DUFFCOPY)
- v.AuxInt = 8 * (128 - int64(SizeAndAlign(s).Size()/8))
+ v.AuxInt = 8 * (128 - int64(s/8))
v.AddArg(dst)
v.AddArg(src)
v.AddArg(mem)
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size()%8 == 0
- // result: (LoweredMove dst src (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // cond: s > 24 && s%8 == 0
+ // result: (LoweredMove dst src (ADDconst <src.Type> src [s-8]) mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size()%8 == 0) {
+ if !(s > 24 && s%8 == 0) {
break
}
v.reset(OpARM64LoweredMove)
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpARM64ADDconst, src.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - 8
v0.AddArg(src)
v.AddArg(v0)
v.AddArg(mem)
@@ -14428,49 +14416,49 @@
func rewriteValueARM64_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpARM64MOVBstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVHstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpARM64MOVHstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: !is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && !is32BitFloat(val.Type)
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(!is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && !is32BitFloat(val.Type)) {
break
}
v.reset(OpARM64MOVWstore)
@@ -14479,17 +14467,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: !is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && !is64BitFloat(val.Type)
// result: (MOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(!is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && !is64BitFloat(val.Type)) {
break
}
v.reset(OpARM64MOVDstore)
@@ -14498,17 +14484,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (FMOVSstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpARM64FMOVSstore)
@@ -14517,17 +14501,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (FMOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpARM64FMOVDstore)
@@ -14790,30 +14772,28 @@
func rewriteValueARM64_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] ptr mem)
+ // cond:
// result: (MOVBstore ptr (MOVDconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVBstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, config.fe.TypeUInt64())
@@ -14822,16 +14802,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] ptr mem)
+ // cond:
// result: (MOVHstore ptr (MOVDconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVHstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, config.fe.TypeUInt64())
@@ -14840,16 +14819,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] ptr mem)
+ // cond:
// result: (MOVWstore ptr (MOVDconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVWstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, config.fe.TypeUInt64())
@@ -14858,16 +14836,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Zero [8] ptr mem)
+ // cond:
// result: (MOVDstore ptr (MOVDconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8) {
+ if v.AuxInt != 8 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVDstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, config.fe.TypeUInt64())
@@ -14876,16 +14853,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] ptr mem)
+ // cond:
// result: (MOVBstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVBstore)
v.AuxInt = 2
v.AddArg(ptr)
@@ -14901,16 +14877,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Zero [5] ptr mem)
+ // cond:
// result: (MOVBstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 5) {
+ if v.AuxInt != 5 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVBstore)
v.AuxInt = 4
v.AddArg(ptr)
@@ -14926,16 +14901,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Zero [6] ptr mem)
+ // cond:
// result: (MOVHstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 6) {
+ if v.AuxInt != 6 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVHstore)
v.AuxInt = 4
v.AddArg(ptr)
@@ -14951,16 +14925,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Zero [7] ptr mem)
+ // cond:
// result: (MOVBstore [6] ptr (MOVDconst [0]) (MOVHstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 7) {
+ if v.AuxInt != 7 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVBstore)
v.AuxInt = 6
v.AddArg(ptr)
@@ -14983,16 +14956,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 12
+ // match: (Zero [12] ptr mem)
+ // cond:
// result: (MOVWstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 12) {
+ if v.AuxInt != 12 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVWstore)
v.AuxInt = 8
v.AddArg(ptr)
@@ -15008,16 +14980,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 16
+ // match: (Zero [16] ptr mem)
+ // cond:
// result: (MOVDstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 16) {
+ if v.AuxInt != 16 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVDstore)
v.AuxInt = 8
v.AddArg(ptr)
@@ -15033,16 +15004,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 24
+ // match: (Zero [24] ptr mem)
+ // cond:
// result: (MOVDstore [16] ptr (MOVDconst [0]) (MOVDstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 24) {
+ if v.AuxInt != 24 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpARM64MOVDstore)
v.AuxInt = 16
v.AddArg(ptr)
@@ -15066,58 +15036,58 @@
return true
}
// match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8
- // result: (Zero [MakeSizeAndAlign(SizeAndAlign(s).Size()%8, 1).Int64()] (OffPtr <ptr.Type> ptr [SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8]) (Zero [MakeSizeAndAlign(SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8, 1).Int64()] ptr mem))
+ // cond: s%8 != 0 && s > 8
+ // result: (Zero [s%8] (OffPtr <ptr.Type> ptr [s-s%8]) (Zero [s-s%8] ptr mem))
for {
s := v.AuxInt
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%8 != 0 && SizeAndAlign(s).Size() > 8) {
+ if !(s%8 != 0 && s > 8) {
break
}
v.reset(OpZero)
- v.AuxInt = MakeSizeAndAlign(SizeAndAlign(s).Size()%8, 1).Int64()
+ v.AuxInt = s % 8
v0 := b.NewValue0(v.Pos, OpOffPtr, ptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - SizeAndAlign(s).Size()%8
+ v0.AuxInt = s - s%8
v0.AddArg(ptr)
v.AddArg(v0)
v1 := b.NewValue0(v.Pos, OpZero, TypeMem)
- v1.AuxInt = MakeSizeAndAlign(SizeAndAlign(s).Size()-SizeAndAlign(s).Size()%8, 1).Int64()
+ v1.AuxInt = s - s%8
v1.AddArg(ptr)
v1.AddArg(mem)
v.AddArg(v1)
return true
}
// match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && !config.noDuffDevice
- // result: (DUFFZERO [4 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem)
+ // cond: s%8 == 0 && s > 24 && s <= 8*128 && !config.noDuffDevice
+ // result: (DUFFZERO [4 * (128 - int64(s/8))] ptr mem)
for {
s := v.AuxInt
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && !config.noDuffDevice) {
+ if !(s%8 == 0 && s > 24 && s <= 8*128 && !config.noDuffDevice) {
break
}
v.reset(OpARM64DUFFZERO)
- v.AuxInt = 4 * (128 - int64(SizeAndAlign(s).Size()/8))
+ v.AuxInt = 4 * (128 - int64(s/8))
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size()%8 == 0 && (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice)
- // result: (LoweredZero ptr (ADDconst <ptr.Type> [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)] ptr) mem)
+ // cond: s%8 == 0 && (s > 8*128 || config.noDuffDevice)
+ // result: (LoweredZero ptr (ADDconst <ptr.Type> [s-8] ptr) mem)
for {
s := v.AuxInt
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%8 == 0 && (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice)) {
+ if !(s%8 == 0 && (s > 8*128 || config.noDuffDevice)) {
break
}
v.reset(OpARM64LoweredZero)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpARM64ADDconst, ptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - 8
v0.AddArg(ptr)
v.AddArg(v0)
v.AddArg(mem)
diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS.go b/src/cmd/compile/internal/ssa/rewriteMIPS.go
index 8c16585..5ffbee6 100644
--- a/src/cmd/compile/internal/ssa/rewriteMIPS.go
+++ b/src/cmd/compile/internal/ssa/rewriteMIPS.go
@@ -6087,31 +6087,29 @@
func rewriteValueMIPS_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpMIPSMOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPSMOVBUload, config.fe.TypeUInt8())
@@ -6121,15 +6119,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [2] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore dst (MOVHUload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -6141,17 +6142,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpMIPSMOVBstore)
v.AuxInt = 1
v.AddArg(dst)
@@ -6170,15 +6170,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore dst (MOVWload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -6190,15 +6193,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] dst (MOVHUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -6219,17 +6225,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVBstore [3] dst (MOVBUload [3] src mem) (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpMIPSMOVBstore)
v.AuxInt = 3
v.AddArg(dst)
@@ -6266,17 +6271,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpMIPSMOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -6304,15 +6308,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -6333,15 +6340,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [6] dst (MOVHload [6] src mem) (MOVHstore [4] dst (MOVHload [4] src mem) (MOVHstore [2] dst (MOVHload [2] src mem) (MOVHstore dst (MOVHload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -6380,15 +6390,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [6] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [4] dst (MOVHload [4] src mem) (MOVHstore [2] dst (MOVHload [2] src mem) (MOVHstore dst (MOVHload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -6418,15 +6431,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [12] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 12 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -6456,15 +6472,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [16] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [12] dst (MOVWload [12] src mem) (MOVWstore [8] dst (MOVWload [8] src mem) (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -6503,23 +6522,24 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: (SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0)
- // result: (LoweredMove [SizeAndAlign(s).Align()] dst src (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Move [s] {t} dst src mem)
+ // cond: (s > 16 || t.(Type).Alignment()%4 != 0)
+ // result: (LoweredMove [t.(Type).Alignment()] dst src (ADDconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) {
+ if !(s > 16 || t.(Type).Alignment()%4 != 0) {
break
}
v.reset(OpMIPSLoweredMove)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpMIPSADDconst, src.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(src)
v.AddArg(v0)
v.AddArg(mem)
@@ -8277,49 +8297,49 @@
func rewriteValueMIPS_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpMIPSMOVBstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVHstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpMIPSMOVHstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: !is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && !is32BitFloat(val.Type)
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(!is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && !is32BitFloat(val.Type)) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -8328,36 +8348,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: !is64BitFloat(val.Type)
- // result: (MOVWstore ptr val mem)
- for {
- if v.AuxInt != 8 {
- break
- }
- ptr := v.Args[0]
- val := v.Args[1]
- mem := v.Args[2]
- if !(!is64BitFloat(val.Type)) {
- break
- }
- v.reset(OpMIPSMOVWstore)
- v.AddArg(ptr)
- v.AddArg(val)
- v.AddArg(mem)
- return true
- }
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (MOVFstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpMIPSMOVFstore)
@@ -8366,17 +8365,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (MOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpMIPSMOVDstore)
@@ -8587,30 +8584,28 @@
func rewriteValueMIPS_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] ptr mem)
+ // cond:
// result: (MOVBstore ptr (MOVWconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPSMOVBstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSMOVWconst, config.fe.TypeUInt32())
@@ -8619,14 +8614,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [2] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore ptr (MOVWconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -8637,16 +8635,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] ptr mem)
+ // cond:
// result: (MOVBstore [1] ptr (MOVWconst [0]) (MOVBstore [0] ptr (MOVWconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPSMOVBstore)
v.AuxInt = 1
v.AddArg(ptr)
@@ -8663,14 +8660,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [4] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore ptr (MOVWconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -8681,14 +8681,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [4] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] ptr (MOVWconst [0]) (MOVHstore [0] ptr (MOVWconst [0]) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -8707,16 +8710,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] ptr mem)
+ // cond:
// result: (MOVBstore [3] ptr (MOVWconst [0]) (MOVBstore [2] ptr (MOVWconst [0]) (MOVBstore [1] ptr (MOVWconst [0]) (MOVBstore [0] ptr (MOVWconst [0]) mem))))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPSMOVBstore)
v.AuxInt = 3
v.AddArg(ptr)
@@ -8747,16 +8749,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] ptr mem)
+ // cond:
// result: (MOVBstore [2] ptr (MOVWconst [0]) (MOVBstore [1] ptr (MOVWconst [0]) (MOVBstore [0] ptr (MOVWconst [0]) mem)))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPSMOVBstore)
v.AuxInt = 2
v.AddArg(ptr)
@@ -8780,14 +8781,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [6] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [4] ptr (MOVWconst [0]) (MOVHstore [2] ptr (MOVWconst [0]) (MOVHstore [0] ptr (MOVWconst [0]) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPSMOVHstore)
@@ -8813,14 +8817,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [8] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [4] ptr (MOVWconst [0]) (MOVWstore [0] ptr (MOVWconst [0]) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -8839,14 +8846,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [12] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [8] ptr (MOVWconst [0]) (MOVWstore [4] ptr (MOVWconst [0]) (MOVWstore [0] ptr (MOVWconst [0]) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 12 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -8872,14 +8882,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [16] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [12] ptr (MOVWconst [0]) (MOVWstore [8] ptr (MOVWconst [0]) (MOVWstore [4] ptr (MOVWconst [0]) (MOVWstore [0] ptr (MOVWconst [0]) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPSMOVWstore)
@@ -8912,21 +8925,22 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: (SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0)
- // result: (LoweredZero [SizeAndAlign(s).Align()] ptr (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Zero [s] {t} ptr mem)
+ // cond: (s > 16 || s%4 != 0)
+ // result: (LoweredZero [t.(Type).Alignment()] ptr (ADDconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() > 16 || SizeAndAlign(s).Align()%4 != 0) {
+ if !(s > 16 || s%4 != 0) {
break
}
v.reset(OpMIPSLoweredZero)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPSADDconst, ptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(ptr)
v.AddArg(v0)
v.AddArg(mem)
diff --git a/src/cmd/compile/internal/ssa/rewriteMIPS64.go b/src/cmd/compile/internal/ssa/rewriteMIPS64.go
index 90ddf02..983bde3 100644
--- a/src/cmd/compile/internal/ssa/rewriteMIPS64.go
+++ b/src/cmd/compile/internal/ssa/rewriteMIPS64.go
@@ -6293,31 +6293,29 @@
func rewriteValueMIPS64_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpMIPS64MOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVBload, config.fe.TypeInt8())
@@ -6327,15 +6325,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [2] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore dst (MOVHload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -6347,17 +6348,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVBstore [1] dst (MOVBload [1] src mem) (MOVBstore dst (MOVBload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 1
v.AddArg(dst)
@@ -6376,15 +6376,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore dst (MOVWload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -6396,15 +6399,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] dst (MOVHload [2] src mem) (MOVHstore dst (MOVHload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -6425,17 +6431,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVBstore [3] dst (MOVBload [3] src mem) (MOVBstore [2] dst (MOVBload [2] src mem) (MOVBstore [1] dst (MOVBload [1] src mem) (MOVBstore dst (MOVBload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 3
v.AddArg(dst)
@@ -6472,15 +6477,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVVstore dst (MOVVload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -6492,15 +6500,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -6521,15 +6532,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [6] dst (MOVHload [6] src mem) (MOVHstore [4] dst (MOVHload [4] src mem) (MOVHstore [2] dst (MOVHload [2] src mem) (MOVHstore dst (MOVHload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -6568,17 +6582,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVBstore [1] dst (MOVBload [1] src mem) (MOVBstore dst (MOVBload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -6606,15 +6619,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [6] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [4] dst (MOVHload [4] src mem) (MOVHstore [2] dst (MOVHload [2] src mem) (MOVHstore dst (MOVHload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -6644,15 +6660,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [12] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 12 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -6682,15 +6701,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Move [16] {t} dst src mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVVstore [8] dst (MOVVload [8] src mem) (MOVVstore dst (MOVVload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -6711,15 +6733,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Move [24] {t} dst src mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVVstore [16] dst (MOVVload [16] src mem) (MOVVstore [8] dst (MOVVload [8] src mem) (MOVVstore dst (MOVVload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 24 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -6749,23 +6774,24 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0
- // result: (LoweredMove [SizeAndAlign(s).Align()] dst src (ADDVconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Move [s] {t} dst src mem)
+ // cond: s > 24 || t.(Type).Alignment()%8 != 0
+ // result: (LoweredMove [t.(Type).Alignment()] dst src (ADDVconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0) {
+ if !(s > 24 || t.(Type).Alignment()%8 != 0) {
break
}
v.reset(OpMIPS64LoweredMove)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpMIPS64ADDVconst, src.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(src)
v.AddArg(v0)
v.AddArg(mem)
@@ -8730,49 +8756,49 @@
func rewriteValueMIPS64_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpMIPS64MOVBstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVHstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpMIPS64MOVHstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: !is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && !is32BitFloat(val.Type)
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(!is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && !is32BitFloat(val.Type)) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -8781,17 +8807,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: !is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && !is64BitFloat(val.Type)
// result: (MOVVstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(!is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && !is64BitFloat(val.Type)) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -8800,17 +8824,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (MOVFstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpMIPS64MOVFstore)
@@ -8819,17 +8841,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (MOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpMIPS64MOVDstore)
@@ -9092,30 +9112,28 @@
func rewriteValueMIPS64_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] ptr mem)
+ // cond:
// result: (MOVBstore ptr (MOVVconst [0]) mem)
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPS64MOVBstore)
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, config.fe.TypeUInt64())
@@ -9124,14 +9142,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [2] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore ptr (MOVVconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -9142,16 +9163,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] ptr mem)
+ // cond:
// result: (MOVBstore [1] ptr (MOVVconst [0]) (MOVBstore [0] ptr (MOVVconst [0]) mem))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 1
v.AddArg(ptr)
@@ -9168,14 +9188,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [4] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore ptr (MOVVconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -9186,14 +9209,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [4] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] ptr (MOVVconst [0]) (MOVHstore [0] ptr (MOVVconst [0]) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -9212,16 +9238,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] ptr mem)
+ // cond:
// result: (MOVBstore [3] ptr (MOVVconst [0]) (MOVBstore [2] ptr (MOVVconst [0]) (MOVBstore [1] ptr (MOVVconst [0]) (MOVBstore [0] ptr (MOVVconst [0]) mem))))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 3
v.AddArg(ptr)
@@ -9252,14 +9277,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [8] {t} ptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVVstore ptr (MOVVconst [0]) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -9270,14 +9298,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [8] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [4] ptr (MOVVconst [0]) (MOVWstore [0] ptr (MOVVconst [0]) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -9296,14 +9327,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [8] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [6] ptr (MOVVconst [0]) (MOVHstore [4] ptr (MOVVconst [0]) (MOVHstore [2] ptr (MOVVconst [0]) (MOVHstore [0] ptr (MOVVconst [0]) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -9336,16 +9370,15 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] ptr mem)
+ // cond:
// result: (MOVBstore [2] ptr (MOVVconst [0]) (MOVBstore [1] ptr (MOVVconst [0]) (MOVBstore [0] ptr (MOVVconst [0]) mem)))
for {
- s := v.AuxInt
- ptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ ptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpMIPS64MOVBstore)
v.AuxInt = 2
v.AddArg(ptr)
@@ -9369,14 +9402,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [6] {t} ptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [4] ptr (MOVVconst [0]) (MOVHstore [2] ptr (MOVVconst [0]) (MOVHstore [0] ptr (MOVVconst [0]) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpMIPS64MOVHstore)
@@ -9402,14 +9438,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [12] {t} ptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [8] ptr (MOVVconst [0]) (MOVWstore [4] ptr (MOVVconst [0]) (MOVWstore [0] ptr (MOVVconst [0]) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 12 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpMIPS64MOVWstore)
@@ -9435,14 +9474,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [16] {t} ptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVVstore [8] ptr (MOVVconst [0]) (MOVVstore [0] ptr (MOVVconst [0]) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -9461,14 +9503,17 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [24] {t} ptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVVstore [16] ptr (MOVVconst [0]) (MOVVstore [8] ptr (MOVVconst [0]) (MOVVstore [0] ptr (MOVVconst [0]) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 24 {
+ break
+ }
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpMIPS64MOVVstore)
@@ -9494,37 +9539,39 @@
v.AddArg(v1)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice
- // result: (DUFFZERO [8 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem)
+ // match: (Zero [s] {t} ptr mem)
+ // cond: s%8 == 0 && s > 24 && s <= 8*128 && t.(Type).Alignment()%8 == 0 && !config.noDuffDevice
+ // result: (DUFFZERO [8 * (128 - int64(s/8))] ptr mem)
for {
s := v.AuxInt
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice) {
+ if !(s%8 == 0 && s > 24 && s <= 8*128 && t.(Type).Alignment()%8 == 0 && !config.noDuffDevice) {
break
}
v.reset(OpMIPS64DUFFZERO)
- v.AuxInt = 8 * (128 - int64(SizeAndAlign(s).Size()/8))
+ v.AuxInt = 8 * (128 - int64(s/8))
v.AddArg(ptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0
- // result: (LoweredZero [SizeAndAlign(s).Align()] ptr (ADDVconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Zero [s] {t} ptr mem)
+ // cond: (s > 8*128 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0
+ // result: (LoweredZero [t.(Type).Alignment()] ptr (ADDVconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !((SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0) {
+ if !((s > 8*128 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0) {
break
}
v.reset(OpMIPS64LoweredZero)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpMIPS64ADDVconst, ptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(ptr)
v.AddArg(v0)
v.AddArg(mem)
diff --git a/src/cmd/compile/internal/ssa/rewritePPC64.go b/src/cmd/compile/internal/ssa/rewritePPC64.go
index 8c2796f..49f469f 100644
--- a/src/cmd/compile/internal/ssa/rewritePPC64.go
+++ b/src/cmd/compile/internal/ssa/rewritePPC64.go
@@ -3672,31 +3672,29 @@
func rewriteValuePPC64_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBZload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpPPC64MOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpPPC64MOVBZload, config.fe.TypeUInt8())
@@ -3706,15 +3704,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [2] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore dst (MOVHZload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpPPC64MOVHstore)
@@ -3726,17 +3727,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVBstore [1] dst (MOVBZload [1] src mem) (MOVBstore dst (MOVBZload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpPPC64MOVBstore)
v.AuxInt = 1
v.AddArg(dst)
@@ -3755,15 +3755,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore dst (MOVWload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpPPC64MOVWstore)
@@ -3775,15 +3778,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [4] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [2] dst (MOVHZload [2] src mem) (MOVHstore dst (MOVHZload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpPPC64MOVHstore)
@@ -3804,17 +3810,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVBstore [3] dst (MOVBZload [3] src mem) (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVBstore [1] dst (MOVBZload [1] src mem) (MOVBstore dst (MOVBZload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpPPC64MOVBstore)
v.AuxInt = 3
v.AddArg(dst)
@@ -3851,15 +3856,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVDstore dst (MOVDload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpPPC64MOVDstore)
@@ -3871,15 +3879,18 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstore [4] dst (MOVWZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpPPC64MOVWstore)
@@ -3900,15 +3911,18 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Move [8] {t} dst src mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstore [6] dst (MOVHZload [6] src mem) (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVHstore [2] dst (MOVHZload [2] src mem) (MOVHstore dst (MOVHZload src mem) mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpPPC64MOVHstore)
@@ -3947,17 +3961,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVBstore [1] dst (MOVBZload [1] src mem) (MOVBstore dst (MOVBZload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpPPC64MOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -3985,23 +3998,24 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0
- // result: (LoweredMove [SizeAndAlign(s).Align()] dst src (ADDconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Move [s] {t} dst src mem)
+ // cond: (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0
+ // result: (LoweredMove [t.(Type).Alignment()] dst src (ADDconst <src.Type> src [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !((SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0) {
+ if !((s > 512 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0) {
break
}
v.reset(OpPPC64LoweredMove)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpPPC64ADDconst, src.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(src)
v.AddArg(v0)
v.AddArg(mem)
@@ -9263,17 +9277,15 @@
func rewriteValuePPC64_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (FMOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpPPC64FMOVDstore)
@@ -9282,17 +9294,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is32BitFloat(val.Type)
// result: (FMOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is32BitFloat(val.Type)) {
break
}
v.reset(OpPPC64FMOVDstore)
@@ -9301,17 +9311,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (FMOVSstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpPPC64FMOVSstore)
@@ -9320,17 +9328,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond: (is64BitInt(val.Type) || isPtr(val.Type))
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type))
// result: (MOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitInt(val.Type) || isPtr(val.Type)) {
+ if !(t.(Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type))) {
break
}
v.reset(OpPPC64MOVDstore)
@@ -9339,17 +9345,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitInt(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitInt(val.Type)
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitInt(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitInt(val.Type)) {
break
}
v.reset(OpPPC64MOVWstore)
@@ -9358,32 +9362,34 @@
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVHstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpPPC64MOVHstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpPPC64MOVBstore)
v.AddArg(ptr)
v.AddArg(val)
@@ -9638,43 +9644,44 @@
func rewriteValuePPC64_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] destptr mem)
+ // cond:
// result: (MOVBstorezero destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpPPC64MOVBstorezero)
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [2] {t} destptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstorezero destptr mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpPPC64MOVHstorezero)
@@ -9682,16 +9689,15 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] destptr mem)
+ // cond:
// result: (MOVBstorezero [1] destptr (MOVBstorezero [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = 1
v.AddArg(destptr)
@@ -9702,14 +9708,17 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [4] {t} destptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstorezero destptr mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpPPC64MOVWstorezero)
@@ -9717,14 +9726,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [4] {t} destptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstorezero [2] destptr (MOVHstorezero [0] destptr mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpPPC64MOVHstorezero)
@@ -9737,16 +9749,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] destptr mem)
+ // cond:
// result: (MOVBstorezero [3] destptr (MOVBstorezero [2] destptr (MOVBstorezero [1] destptr (MOVBstorezero [0] destptr mem))))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = 3
v.AddArg(destptr)
@@ -9765,14 +9776,17 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [8] {t} destptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVDstorezero [0] destptr mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpPPC64MOVDstorezero)
@@ -9781,14 +9795,17 @@
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0
+ // match: (Zero [8] {t} destptr mem)
+ // cond: t.(Type).Alignment()%4 == 0
// result: (MOVWstorezero [4] destptr (MOVWstorezero [0] destptr mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) {
+ if !(t.(Type).Alignment()%4 == 0) {
break
}
v.reset(OpPPC64MOVWstorezero)
@@ -9801,14 +9818,17 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0
+ // match: (Zero [8] {t} destptr mem)
+ // cond: t.(Type).Alignment()%2 == 0
// result: (MOVHstorezero [6] destptr (MOVHstorezero [4] destptr (MOVHstorezero [2] destptr (MOVHstorezero [0] destptr mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) {
+ if !(t.(Type).Alignment()%2 == 0) {
break
}
v.reset(OpPPC64MOVHstorezero)
@@ -9829,16 +9849,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] destptr mem)
+ // cond:
// result: (MOVBstorezero [2] destptr (MOVBstorezero [1] destptr (MOVBstorezero [0] destptr mem)))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpPPC64MOVBstorezero)
v.AuxInt = 2
v.AddArg(destptr)
@@ -9853,14 +9872,17 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [16] {t} destptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpPPC64MOVDstorezero)
@@ -9873,14 +9895,17 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [24] {t} destptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 24 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpPPC64MOVDstorezero)
@@ -9897,14 +9922,17 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 32 && SizeAndAlign(s).Align()%8 == 0
+ // match: (Zero [32] {t} destptr mem)
+ // cond: t.(Type).Alignment()%8 == 0
// result: (MOVDstorezero [24] destptr (MOVDstorezero [16] destptr (MOVDstorezero [8] destptr (MOVDstorezero [0] destptr mem))))
for {
- s := v.AuxInt
+ if v.AuxInt != 32 {
+ break
+ }
+ t := v.Aux
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 32 && SizeAndAlign(s).Align()%8 == 0) {
+ if !(t.(Type).Alignment()%8 == 0) {
break
}
v.reset(OpPPC64MOVDstorezero)
@@ -9925,21 +9953,22 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] ptr mem)
- // cond: (SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0
- // result: (LoweredZero [SizeAndAlign(s).Align()] ptr (ADDconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem)
+ // match: (Zero [s] {t} ptr mem)
+ // cond: (s > 512 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0
+ // result: (LoweredZero [t.(Type).Alignment()] ptr (ADDconst <ptr.Type> ptr [s-moveSize(t.(Type).Alignment(), config)]) mem)
for {
s := v.AuxInt
+ t := v.Aux
ptr := v.Args[0]
mem := v.Args[1]
- if !((SizeAndAlign(s).Size() > 512 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0) {
+ if !((s > 512 || config.noDuffDevice) || t.(Type).Alignment()%8 != 0) {
break
}
v.reset(OpPPC64LoweredZero)
- v.AuxInt = SizeAndAlign(s).Align()
+ v.AuxInt = t.(Type).Alignment()
v.AddArg(ptr)
v0 := b.NewValue0(v.Pos, OpPPC64ADDconst, ptr.Type)
- v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config)
+ v0.AuxInt = s - moveSize(t.(Type).Alignment(), config)
v0.AddArg(ptr)
v.AddArg(v0)
v.AddArg(mem)
diff --git a/src/cmd/compile/internal/ssa/rewriteS390X.go b/src/cmd/compile/internal/ssa/rewriteS390X.go
index 7bf1b6b..cef7365 100644
--- a/src/cmd/compile/internal/ssa/rewriteS390X.go
+++ b/src/cmd/compile/internal/ssa/rewriteS390X.go
@@ -3777,31 +3777,29 @@
func rewriteValueS390X_OpMove(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Move [s] _ _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Move [0] _ _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[2]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Move [1] dst src mem)
+ // cond:
// result: (MOVBstore dst (MOVBZload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 1 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 1) {
- break
- }
v.reset(OpS390XMOVBstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVBZload, config.fe.TypeUInt8())
@@ -3811,17 +3809,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Move [2] dst src mem)
+ // cond:
// result: (MOVHstore dst (MOVHZload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 2 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 2) {
- break
- }
v.reset(OpS390XMOVHstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVHZload, config.fe.TypeUInt16())
@@ -3831,17 +3828,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Move [4] dst src mem)
+ // cond:
// result: (MOVWstore dst (MOVWZload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 4 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 4) {
- break
- }
v.reset(OpS390XMOVWstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVWZload, config.fe.TypeUInt32())
@@ -3851,17 +3847,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Move [8] dst src mem)
+ // cond:
// result: (MOVDstore dst (MOVDload src mem) mem)
for {
- s := v.AuxInt
+ if v.AuxInt != 8 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 8) {
- break
- }
v.reset(OpS390XMOVDstore)
v.AddArg(dst)
v0 := b.NewValue0(v.Pos, OpS390XMOVDload, config.fe.TypeUInt64())
@@ -3871,17 +3866,16 @@
v.AddArg(mem)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 16
+ // match: (Move [16] dst src mem)
+ // cond:
// result: (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 16 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 16) {
- break
- }
v.reset(OpS390XMOVDstore)
v.AuxInt = 8
v.AddArg(dst)
@@ -3900,17 +3894,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 24
+ // match: (Move [24] dst src mem)
+ // cond:
// result: (MOVDstore [16] dst (MOVDload [16] src mem) (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 24 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 24) {
- break
- }
v.reset(OpS390XMOVDstore)
v.AuxInt = 16
v.AddArg(dst)
@@ -3938,17 +3931,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Move [3] dst src mem)
+ // cond:
// result: (MOVBstore [2] dst (MOVBZload [2] src mem) (MOVHstore dst (MOVHZload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 3 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 3) {
- break
- }
v.reset(OpS390XMOVBstore)
v.AuxInt = 2
v.AddArg(dst)
@@ -3967,17 +3959,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Move [5] dst src mem)
+ // cond:
// result: (MOVBstore [4] dst (MOVBZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 5 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 5) {
- break
- }
v.reset(OpS390XMOVBstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -3996,17 +3987,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Move [6] dst src mem)
+ // cond:
// result: (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem))
for {
- s := v.AuxInt
+ if v.AuxInt != 6 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 6) {
- break
- }
v.reset(OpS390XMOVHstore)
v.AuxInt = 4
v.AddArg(dst)
@@ -4025,17 +4015,16 @@
v.AddArg(v1)
return true
}
- // match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Move [7] dst src mem)
+ // cond:
// result: (MOVBstore [6] dst (MOVBZload [6] src mem) (MOVHstore [4] dst (MOVHZload [4] src mem) (MOVWstore dst (MOVWZload src mem) mem)))
for {
- s := v.AuxInt
+ if v.AuxInt != 7 {
+ break
+ }
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() == 7) {
- break
- }
v.reset(OpS390XMOVBstore)
v.AuxInt = 6
v.AddArg(dst)
@@ -4064,36 +4053,36 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 256
- // result: (MVC [makeValAndOff(SizeAndAlign(s).Size(), 0)] dst src mem)
+ // cond: s > 0 && s <= 256
+ // result: (MVC [makeValAndOff(s, 0)] dst src mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 256) {
+ if !(s > 0 && s <= 256) {
break
}
v.reset(OpS390XMVC)
- v.AuxInt = makeValAndOff(SizeAndAlign(s).Size(), 0)
+ v.AuxInt = makeValAndOff(s, 0)
v.AddArg(dst)
v.AddArg(src)
v.AddArg(mem)
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 256 && SizeAndAlign(s).Size() <= 512
- // result: (MVC [makeValAndOff(SizeAndAlign(s).Size()-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))
+ // cond: s > 256 && s <= 512
+ // result: (MVC [makeValAndOff(s-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 256 && SizeAndAlign(s).Size() <= 512) {
+ if !(s > 256 && s <= 512) {
break
}
v.reset(OpS390XMVC)
- v.AuxInt = makeValAndOff(SizeAndAlign(s).Size()-256, 256)
+ v.AuxInt = makeValAndOff(s-256, 256)
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XMVC, TypeMem)
@@ -4105,18 +4094,18 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 512 && SizeAndAlign(s).Size() <= 768
- // result: (MVC [makeValAndOff(SizeAndAlign(s).Size()-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))
+ // cond: s > 512 && s <= 768
+ // result: (MVC [makeValAndOff(s-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 512 && SizeAndAlign(s).Size() <= 768) {
+ if !(s > 512 && s <= 768) {
break
}
v.reset(OpS390XMVC)
- v.AuxInt = makeValAndOff(SizeAndAlign(s).Size()-512, 512)
+ v.AuxInt = makeValAndOff(s-512, 512)
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XMVC, TypeMem)
@@ -4133,18 +4122,18 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 768 && SizeAndAlign(s).Size() <= 1024
- // result: (MVC [makeValAndOff(SizeAndAlign(s).Size()-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))))
+ // cond: s > 768 && s <= 1024
+ // result: (MVC [makeValAndOff(s-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))))
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 768 && SizeAndAlign(s).Size() <= 1024) {
+ if !(s > 768 && s <= 1024) {
break
}
v.reset(OpS390XMVC)
- v.AuxInt = makeValAndOff(SizeAndAlign(s).Size()-768, 768)
+ v.AuxInt = makeValAndOff(s-768, 768)
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XMVC, TypeMem)
@@ -4166,22 +4155,22 @@
return true
}
// match: (Move [s] dst src mem)
- // cond: SizeAndAlign(s).Size() > 1024
- // result: (LoweredMove [SizeAndAlign(s).Size()%256] dst src (ADDconst <src.Type> src [(SizeAndAlign(s).Size()/256)*256]) mem)
+ // cond: s > 1024
+ // result: (LoweredMove [s%256] dst src (ADDconst <src.Type> src [(s/256)*256]) mem)
for {
s := v.AuxInt
dst := v.Args[0]
src := v.Args[1]
mem := v.Args[2]
- if !(SizeAndAlign(s).Size() > 1024) {
+ if !(s > 1024) {
break
}
v.reset(OpS390XLoweredMove)
- v.AuxInt = SizeAndAlign(s).Size() % 256
+ v.AuxInt = s % 256
v.AddArg(dst)
v.AddArg(src)
v0 := b.NewValue0(v.Pos, OpS390XADDconst, src.Type)
- v0.AuxInt = (SizeAndAlign(s).Size() / 256) * 256
+ v0.AuxInt = (s / 256) * 256
v0.AddArg(src)
v.AddArg(v0)
v.AddArg(mem)
@@ -18095,17 +18084,15 @@
func rewriteValueS390X_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [8] ptr val mem)
- // cond: is64BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8 && is64BitFloat(val.Type)
// result: (FMOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is64BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 8 && is64BitFloat(val.Type)) {
break
}
v.reset(OpS390XFMOVDstore)
@@ -18114,17 +18101,15 @@
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond: is32BitFloat(val.Type)
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4 && is32BitFloat(val.Type)
// result: (FMOVSstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
- if !(is32BitFloat(val.Type)) {
+ if !(t.(Type).Size() == 4 && is32BitFloat(val.Type)) {
break
}
v.reset(OpS390XFMOVSstore)
@@ -18133,64 +18118,68 @@
v.AddArg(mem)
return true
}
- // match: (Store [8] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 8
// result: (MOVDstore ptr val mem)
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 8) {
+ break
+ }
v.reset(OpS390XMOVDstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [4] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 4
// result: (MOVWstore ptr val mem)
for {
- if v.AuxInt != 4 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 4) {
+ break
+ }
v.reset(OpS390XMOVWstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [2] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 2
// result: (MOVHstore ptr val mem)
for {
- if v.AuxInt != 2 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 2) {
+ break
+ }
v.reset(OpS390XMOVHstore)
v.AddArg(ptr)
v.AddArg(val)
v.AddArg(mem)
return true
}
- // match: (Store [1] ptr val mem)
- // cond:
+ // match: (Store {t} ptr val mem)
+ // cond: t.(Type).Size() == 1
// result: (MOVBstore ptr val mem)
for {
- if v.AuxInt != 1 {
- break
- }
+ t := v.Aux
ptr := v.Args[0]
val := v.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 1) {
+ break
+ }
v.reset(OpS390XMOVBstore)
v.AddArg(ptr)
v.AddArg(val)
@@ -18451,94 +18440,88 @@
func rewriteValueS390X_OpZero(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Zero [s] _ mem)
- // cond: SizeAndAlign(s).Size() == 0
+ // match: (Zero [0] _ mem)
+ // cond:
// result: mem
for {
- s := v.AuxInt
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 0) {
+ if v.AuxInt != 0 {
break
}
+ mem := v.Args[1]
v.reset(OpCopy)
v.Type = mem.Type
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 1
+ // match: (Zero [1] destptr mem)
+ // cond:
// result: (MOVBstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 1) {
+ if v.AuxInt != 1 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 2
+ // match: (Zero [2] destptr mem)
+ // cond:
// result: (MOVHstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 2) {
+ if v.AuxInt != 2 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 4
+ // match: (Zero [4] destptr mem)
+ // cond:
// result: (MOVWstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 4) {
+ if v.AuxInt != 4 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 8
+ // match: (Zero [8] destptr mem)
+ // cond:
// result: (MOVDstoreconst [0] destptr mem)
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 8) {
+ if v.AuxInt != 8 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVDstoreconst)
v.AuxInt = 0
v.AddArg(destptr)
v.AddArg(mem)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 3
+ // match: (Zero [3] destptr mem)
+ // cond:
// result: (MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVHstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 3) {
+ if v.AuxInt != 3 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = makeValAndOff(0, 2)
v.AddArg(destptr)
@@ -18549,16 +18532,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 5
+ // match: (Zero [5] destptr mem)
+ // cond:
// result: (MOVBstoreconst [makeValAndOff(0,4)] destptr (MOVWstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 5) {
+ if v.AuxInt != 5 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVBstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -18569,16 +18551,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 6
+ // match: (Zero [6] destptr mem)
+ // cond:
// result: (MOVHstoreconst [makeValAndOff(0,4)] destptr (MOVWstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 6) {
+ if v.AuxInt != 6 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVHstoreconst)
v.AuxInt = makeValAndOff(0, 4)
v.AddArg(destptr)
@@ -18589,16 +18570,15 @@
v.AddArg(v0)
return true
}
- // match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() == 7
+ // match: (Zero [7] destptr mem)
+ // cond:
// result: (MOVWstoreconst [makeValAndOff(0,3)] destptr (MOVWstoreconst [0] destptr mem))
for {
- s := v.AuxInt
- destptr := v.Args[0]
- mem := v.Args[1]
- if !(SizeAndAlign(s).Size() == 7) {
+ if v.AuxInt != 7 {
break
}
+ destptr := v.Args[0]
+ mem := v.Args[1]
v.reset(OpS390XMOVWstoreconst)
v.AuxInt = makeValAndOff(0, 3)
v.AddArg(destptr)
@@ -18610,36 +18590,36 @@
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 1024
- // result: (CLEAR [makeValAndOff(SizeAndAlign(s).Size(), 0)] destptr mem)
+ // cond: s > 0 && s <= 1024
+ // result: (CLEAR [makeValAndOff(s, 0)] destptr mem)
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 1024) {
+ if !(s > 0 && s <= 1024) {
break
}
v.reset(OpS390XCLEAR)
- v.AuxInt = makeValAndOff(SizeAndAlign(s).Size(), 0)
+ v.AuxInt = makeValAndOff(s, 0)
v.AddArg(destptr)
v.AddArg(mem)
return true
}
// match: (Zero [s] destptr mem)
- // cond: SizeAndAlign(s).Size() > 1024
- // result: (LoweredZero [SizeAndAlign(s).Size()%256] destptr (ADDconst <destptr.Type> destptr [(SizeAndAlign(s).Size()/256)*256]) mem)
+ // cond: s > 1024
+ // result: (LoweredZero [s%256] destptr (ADDconst <destptr.Type> destptr [(s/256)*256]) mem)
for {
s := v.AuxInt
destptr := v.Args[0]
mem := v.Args[1]
- if !(SizeAndAlign(s).Size() > 1024) {
+ if !(s > 1024) {
break
}
v.reset(OpS390XLoweredZero)
- v.AuxInt = SizeAndAlign(s).Size() % 256
+ v.AuxInt = s % 256
v.AddArg(destptr)
v0 := b.NewValue0(v.Pos, OpS390XADDconst, destptr.Type)
- v0.AuxInt = (SizeAndAlign(s).Size() / 256) * 256
+ v0.AuxInt = (s / 256) * 256
v0.AddArg(destptr)
v.AddArg(v0)
v.AddArg(mem)
diff --git a/src/cmd/compile/internal/ssa/rewritedec.go b/src/cmd/compile/internal/ssa/rewritedec.go
index 8a11374..7da5162 100644
--- a/src/cmd/compile/internal/ssa/rewritedec.go
+++ b/src/cmd/compile/internal/ssa/rewritedec.go
@@ -301,13 +301,11 @@
func rewriteValuedec_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [8] dst (ComplexMake real imag) mem)
- // cond:
- // result: (Store [4] {config.fe.TypeFloat32()} (OffPtr <config.fe.TypeFloat32().PtrTo()> [4] dst) imag (Store [4] {config.fe.TypeFloat32()} dst real mem))
+ // match: (Store {t} dst (ComplexMake real imag) mem)
+ // cond: t.(Type).Size() == 8
+ // result: (Store {config.fe.TypeFloat32()} (OffPtr <config.fe.TypeFloat32().PtrTo()> [4] dst) imag (Store {config.fe.TypeFloat32()} dst real mem))
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpComplexMake {
@@ -316,8 +314,10 @@
real := v_1.Args[0]
imag := v_1.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 8) {
+ break
+ }
v.reset(OpStore)
- v.AuxInt = 4
v.Aux = config.fe.TypeFloat32()
v0 := b.NewValue0(v.Pos, OpOffPtr, config.fe.TypeFloat32().PtrTo())
v0.AuxInt = 4
@@ -325,7 +325,6 @@
v.AddArg(v0)
v.AddArg(imag)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = 4
v1.Aux = config.fe.TypeFloat32()
v1.AddArg(dst)
v1.AddArg(real)
@@ -333,13 +332,11 @@
v.AddArg(v1)
return true
}
- // match: (Store [16] dst (ComplexMake real imag) mem)
- // cond:
- // result: (Store [8] {config.fe.TypeFloat64()} (OffPtr <config.fe.TypeFloat64().PtrTo()> [8] dst) imag (Store [8] {config.fe.TypeFloat64()} dst real mem))
+ // match: (Store {t} dst (ComplexMake real imag) mem)
+ // cond: t.(Type).Size() == 16
+ // result: (Store {config.fe.TypeFloat64()} (OffPtr <config.fe.TypeFloat64().PtrTo()> [8] dst) imag (Store {config.fe.TypeFloat64()} dst real mem))
for {
- if v.AuxInt != 16 {
- break
- }
+ t := v.Aux
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpComplexMake {
@@ -348,8 +345,10 @@
real := v_1.Args[0]
imag := v_1.Args[1]
mem := v.Args[2]
+ if !(t.(Type).Size() == 16) {
+ break
+ }
v.reset(OpStore)
- v.AuxInt = 8
v.Aux = config.fe.TypeFloat64()
v0 := b.NewValue0(v.Pos, OpOffPtr, config.fe.TypeFloat64().PtrTo())
v0.AuxInt = 8
@@ -357,7 +356,6 @@
v.AddArg(v0)
v.AddArg(imag)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = 8
v1.Aux = config.fe.TypeFloat64()
v1.AddArg(dst)
v1.AddArg(real)
@@ -365,13 +363,10 @@
v.AddArg(v1)
return true
}
- // match: (Store [2*config.PtrSize] dst (StringMake ptr len) mem)
+ // match: (Store dst (StringMake ptr len) mem)
// cond:
- // result: (Store [config.PtrSize] {config.fe.TypeInt()} (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) len (Store [config.PtrSize] {config.fe.TypeBytePtr()} dst ptr mem))
+ // result: (Store {config.fe.TypeInt()} (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) len (Store {config.fe.TypeBytePtr()} dst ptr mem))
for {
- if v.AuxInt != 2*config.PtrSize {
- break
- }
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpStringMake {
@@ -381,7 +376,6 @@
len := v_1.Args[1]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = config.PtrSize
v.Aux = config.fe.TypeInt()
v0 := b.NewValue0(v.Pos, OpOffPtr, config.fe.TypeInt().PtrTo())
v0.AuxInt = config.PtrSize
@@ -389,7 +383,6 @@
v.AddArg(v0)
v.AddArg(len)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = config.PtrSize
v1.Aux = config.fe.TypeBytePtr()
v1.AddArg(dst)
v1.AddArg(ptr)
@@ -397,13 +390,10 @@
v.AddArg(v1)
return true
}
- // match: (Store [3*config.PtrSize] dst (SliceMake ptr len cap) mem)
+ // match: (Store dst (SliceMake ptr len cap) mem)
// cond:
- // result: (Store [config.PtrSize] {config.fe.TypeInt()} (OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] dst) cap (Store [config.PtrSize] {config.fe.TypeInt()} (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) len (Store [config.PtrSize] {config.fe.TypeBytePtr()} dst ptr mem)))
+ // result: (Store {config.fe.TypeInt()} (OffPtr <config.fe.TypeInt().PtrTo()> [2*config.PtrSize] dst) cap (Store {config.fe.TypeInt()} (OffPtr <config.fe.TypeInt().PtrTo()> [config.PtrSize] dst) len (Store {config.fe.TypeBytePtr()} dst ptr mem)))
for {
- if v.AuxInt != 3*config.PtrSize {
- break
- }
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpSliceMake {
@@ -414,7 +404,6 @@
cap := v_1.Args[2]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = config.PtrSize
v.Aux = config.fe.TypeInt()
v0 := b.NewValue0(v.Pos, OpOffPtr, config.fe.TypeInt().PtrTo())
v0.AuxInt = 2 * config.PtrSize
@@ -422,7 +411,6 @@
v.AddArg(v0)
v.AddArg(cap)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = config.PtrSize
v1.Aux = config.fe.TypeInt()
v2 := b.NewValue0(v.Pos, OpOffPtr, config.fe.TypeInt().PtrTo())
v2.AuxInt = config.PtrSize
@@ -430,7 +418,6 @@
v1.AddArg(v2)
v1.AddArg(len)
v3 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v3.AuxInt = config.PtrSize
v3.Aux = config.fe.TypeBytePtr()
v3.AddArg(dst)
v3.AddArg(ptr)
@@ -439,13 +426,10 @@
v.AddArg(v1)
return true
}
- // match: (Store [2*config.PtrSize] dst (IMake itab data) mem)
+ // match: (Store dst (IMake itab data) mem)
// cond:
- // result: (Store [config.PtrSize] {config.fe.TypeBytePtr()} (OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] dst) data (Store [config.PtrSize] {config.fe.TypeUintptr()} dst itab mem))
+ // result: (Store {config.fe.TypeBytePtr()} (OffPtr <config.fe.TypeBytePtr().PtrTo()> [config.PtrSize] dst) data (Store {config.fe.TypeUintptr()} dst itab mem))
for {
- if v.AuxInt != 2*config.PtrSize {
- break
- }
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpIMake {
@@ -455,7 +439,6 @@
data := v_1.Args[1]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = config.PtrSize
v.Aux = config.fe.TypeBytePtr()
v0 := b.NewValue0(v.Pos, OpOffPtr, config.fe.TypeBytePtr().PtrTo())
v0.AuxInt = config.PtrSize
@@ -463,7 +446,6 @@
v.AddArg(v0)
v.AddArg(data)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = config.PtrSize
v1.Aux = config.fe.TypeUintptr()
v1.AddArg(dst)
v1.AddArg(itab)
diff --git a/src/cmd/compile/internal/ssa/rewritedec64.go b/src/cmd/compile/internal/ssa/rewritedec64.go
index be16840..db4a3c0 100644
--- a/src/cmd/compile/internal/ssa/rewritedec64.go
+++ b/src/cmd/compile/internal/ssa/rewritedec64.go
@@ -2396,13 +2396,11 @@
func rewriteValuedec64_OpStore(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Store [8] dst (Int64Make hi lo) mem)
- // cond: !config.BigEndian
- // result: (Store [4] {hi.Type} (OffPtr <hi.Type.PtrTo()> [4] dst) hi (Store [4] {lo.Type} dst lo mem))
+ // match: (Store {t} dst (Int64Make hi lo) mem)
+ // cond: t.(Type).Size() == 8 && !config.BigEndian
+ // result: (Store {hi.Type} (OffPtr <hi.Type.PtrTo()> [4] dst) hi (Store {lo.Type} dst lo mem))
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpInt64Make {
@@ -2411,11 +2409,10 @@
hi := v_1.Args[0]
lo := v_1.Args[1]
mem := v.Args[2]
- if !(!config.BigEndian) {
+ if !(t.(Type).Size() == 8 && !config.BigEndian) {
break
}
v.reset(OpStore)
- v.AuxInt = 4
v.Aux = hi.Type
v0 := b.NewValue0(v.Pos, OpOffPtr, hi.Type.PtrTo())
v0.AuxInt = 4
@@ -2423,7 +2420,6 @@
v.AddArg(v0)
v.AddArg(hi)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = 4
v1.Aux = lo.Type
v1.AddArg(dst)
v1.AddArg(lo)
@@ -2431,13 +2427,11 @@
v.AddArg(v1)
return true
}
- // match: (Store [8] dst (Int64Make hi lo) mem)
- // cond: config.BigEndian
- // result: (Store [4] {lo.Type} (OffPtr <lo.Type.PtrTo()> [4] dst) lo (Store [4] {hi.Type} dst hi mem))
+ // match: (Store {t} dst (Int64Make hi lo) mem)
+ // cond: t.(Type).Size() == 8 && config.BigEndian
+ // result: (Store {lo.Type} (OffPtr <lo.Type.PtrTo()> [4] dst) lo (Store {hi.Type} dst hi mem))
for {
- if v.AuxInt != 8 {
- break
- }
+ t := v.Aux
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpInt64Make {
@@ -2446,11 +2440,10 @@
hi := v_1.Args[0]
lo := v_1.Args[1]
mem := v.Args[2]
- if !(config.BigEndian) {
+ if !(t.(Type).Size() == 8 && config.BigEndian) {
break
}
v.reset(OpStore)
- v.AuxInt = 4
v.Aux = lo.Type
v0 := b.NewValue0(v.Pos, OpOffPtr, lo.Type.PtrTo())
v0.AuxInt = 4
@@ -2458,7 +2451,6 @@
v.AddArg(v0)
v.AddArg(lo)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = 4
v1.Aux = hi.Type
v1.AddArg(dst)
v1.AddArg(hi)
diff --git a/src/cmd/compile/internal/ssa/rewritegeneric.go b/src/cmd/compile/internal/ssa/rewritegeneric.go
index 172e777..73dccf2 100644
--- a/src/cmd/compile/internal/ssa/rewritegeneric.go
+++ b/src/cmd/compile/internal/ssa/rewritegeneric.go
@@ -6764,8 +6764,8 @@
func rewriteValuegeneric_OpLoad(v *Value, config *Config) bool {
b := v.Block
_ = b
- // match: (Load <t1> p1 (Store [w] p2 x _))
- // cond: isSamePtr(p1,p2) && t1.Compare(x.Type)==CMPeq && w == t1.Size()
+ // match: (Load <t1> p1 (Store {t2} p2 x _))
+ // cond: isSamePtr(p1,p2) && t1.Compare(x.Type)==CMPeq && t1.Size() == t2.(Type).Size()
// result: x
for {
t1 := v.Type
@@ -6774,10 +6774,10 @@
if v_1.Op != OpStore {
break
}
- w := v_1.AuxInt
+ t2 := v_1.Aux
p2 := v_1.Args[0]
x := v_1.Args[1]
- if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == CMPeq && w == t1.Size()) {
+ if !(isSamePtr(p1, p2) && t1.Compare(x.Type) == CMPeq && t1.Size() == t2.(Type).Size()) {
break
}
v.reset(OpCopy)
@@ -14748,7 +14748,7 @@
}
// match: (Store dst (StructMake1 <t> f0) mem)
// cond:
- // result: (Store [t.FieldType(0).Size()] {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem)
+ // result: (Store {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem)
for {
dst := v.Args[0]
v_1 := v.Args[1]
@@ -14759,7 +14759,6 @@
f0 := v_1.Args[0]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = t.FieldType(0).Size()
v.Aux = t.FieldType(0)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v0.AuxInt = 0
@@ -14771,7 +14770,7 @@
}
// match: (Store dst (StructMake2 <t> f0 f1) mem)
// cond:
- // result: (Store [t.FieldType(1).Size()] {t.FieldType(1)} (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store [t.FieldType(0).Size()] {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem))
+ // result: (Store {t.FieldType(1)} (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem))
for {
dst := v.Args[0]
v_1 := v.Args[1]
@@ -14783,7 +14782,6 @@
f1 := v_1.Args[1]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = t.FieldType(1).Size()
v.Aux = t.FieldType(1)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v0.AuxInt = t.FieldOff(1)
@@ -14791,7 +14789,6 @@
v.AddArg(v0)
v.AddArg(f1)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = t.FieldType(0).Size()
v1.Aux = t.FieldType(0)
v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v2.AuxInt = 0
@@ -14804,7 +14801,7 @@
}
// match: (Store dst (StructMake3 <t> f0 f1 f2) mem)
// cond:
- // result: (Store [t.FieldType(2).Size()] {t.FieldType(2)} (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) f2 (Store [t.FieldType(1).Size()] {t.FieldType(1)} (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store [t.FieldType(0).Size()] {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem)))
+ // result: (Store {t.FieldType(2)} (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem)))
for {
dst := v.Args[0]
v_1 := v.Args[1]
@@ -14817,7 +14814,6 @@
f2 := v_1.Args[2]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = t.FieldType(2).Size()
v.Aux = t.FieldType(2)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo())
v0.AuxInt = t.FieldOff(2)
@@ -14825,7 +14821,6 @@
v.AddArg(v0)
v.AddArg(f2)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = t.FieldType(1).Size()
v1.Aux = t.FieldType(1)
v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v2.AuxInt = t.FieldOff(1)
@@ -14833,7 +14828,6 @@
v1.AddArg(v2)
v1.AddArg(f1)
v3 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v3.AuxInt = t.FieldType(0).Size()
v3.Aux = t.FieldType(0)
v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v4.AuxInt = 0
@@ -14847,7 +14841,7 @@
}
// match: (Store dst (StructMake4 <t> f0 f1 f2 f3) mem)
// cond:
- // result: (Store [t.FieldType(3).Size()] {t.FieldType(3)} (OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] dst) f3 (Store [t.FieldType(2).Size()] {t.FieldType(2)} (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) f2 (Store [t.FieldType(1).Size()] {t.FieldType(1)} (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store [t.FieldType(0).Size()] {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem))))
+ // result: (Store {t.FieldType(3)} (OffPtr <t.FieldType(3).PtrTo()> [t.FieldOff(3)] dst) f3 (Store {t.FieldType(2)} (OffPtr <t.FieldType(2).PtrTo()> [t.FieldOff(2)] dst) f2 (Store {t.FieldType(1)} (OffPtr <t.FieldType(1).PtrTo()> [t.FieldOff(1)] dst) f1 (Store {t.FieldType(0)} (OffPtr <t.FieldType(0).PtrTo()> [0] dst) f0 mem))))
for {
dst := v.Args[0]
v_1 := v.Args[1]
@@ -14861,7 +14855,6 @@
f3 := v_1.Args[3]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = t.FieldType(3).Size()
v.Aux = t.FieldType(3)
v0 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(3).PtrTo())
v0.AuxInt = t.FieldOff(3)
@@ -14869,7 +14862,6 @@
v.AddArg(v0)
v.AddArg(f3)
v1 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v1.AuxInt = t.FieldType(2).Size()
v1.Aux = t.FieldType(2)
v2 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(2).PtrTo())
v2.AuxInt = t.FieldOff(2)
@@ -14877,7 +14869,6 @@
v1.AddArg(v2)
v1.AddArg(f2)
v3 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v3.AuxInt = t.FieldType(1).Size()
v3.Aux = t.FieldType(1)
v4 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(1).PtrTo())
v4.AuxInt = t.FieldOff(1)
@@ -14885,7 +14876,6 @@
v3.AddArg(v4)
v3.AddArg(f1)
v5 := b.NewValue0(v.Pos, OpStore, TypeMem)
- v5.AuxInt = t.FieldType(0).Size()
v5.Aux = t.FieldType(0)
v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
v6.AuxInt = 0
@@ -14898,44 +14888,42 @@
v.AddArg(v1)
return true
}
- // match: (Store [size] dst (Load <t> src mem) mem)
- // cond: !config.fe.CanSSA(t)
- // result: (Move [MakeSizeAndAlign(size, t.Alignment()).Int64()] {t} dst src mem)
+ // match: (Store {t} dst (Load src mem) mem)
+ // cond: !config.fe.CanSSA(t.(Type))
+ // result: (Move {t} [t.(Type).Size()] dst src mem)
for {
- size := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpLoad {
break
}
- t := v_1.Type
src := v_1.Args[0]
mem := v_1.Args[1]
if mem != v.Args[2] {
break
}
- if !(!config.fe.CanSSA(t)) {
+ if !(!config.fe.CanSSA(t.(Type))) {
break
}
v.reset(OpMove)
- v.AuxInt = MakeSizeAndAlign(size, t.Alignment()).Int64()
+ v.AuxInt = t.(Type).Size()
v.Aux = t
v.AddArg(dst)
v.AddArg(src)
v.AddArg(mem)
return true
}
- // match: (Store [size] dst (Load <t> src mem) (VarDef {x} mem))
- // cond: !config.fe.CanSSA(t)
- // result: (Move [MakeSizeAndAlign(size, t.Alignment()).Int64()] {t} dst src (VarDef {x} mem))
+ // match: (Store {t} dst (Load src mem) (VarDef {x} mem))
+ // cond: !config.fe.CanSSA(t.(Type))
+ // result: (Move {t} [t.(Type).Size()] dst src (VarDef {x} mem))
for {
- size := v.AuxInt
+ t := v.Aux
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpLoad {
break
}
- t := v_1.Type
src := v_1.Args[0]
mem := v_1.Args[1]
v_2 := v.Args[2]
@@ -14946,11 +14934,11 @@
if mem != v_2.Args[0] {
break
}
- if !(!config.fe.CanSSA(t)) {
+ if !(!config.fe.CanSSA(t.(Type))) {
break
}
v.reset(OpMove)
- v.AuxInt = MakeSizeAndAlign(size, t.Alignment()).Int64()
+ v.AuxInt = t.(Type).Size()
v.Aux = t
v.AddArg(dst)
v.AddArg(src)
@@ -14974,11 +14962,10 @@
v.AddArg(mem)
return true
}
- // match: (Store [size] dst (ArrayMake1 e) mem)
+ // match: (Store dst (ArrayMake1 e) mem)
// cond:
- // result: (Store [size] {e.Type} dst e mem)
+ // result: (Store {e.Type} dst e mem)
for {
- size := v.AuxInt
dst := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != OpArrayMake1 {
@@ -14987,7 +14974,6 @@
e := v_1.Args[0]
mem := v.Args[2]
v.reset(OpStore)
- v.AuxInt = size
v.Aux = e.Type
v.AddArg(dst)
v.AddArg(e)
diff --git a/src/cmd/compile/internal/ssa/schedule_test.go b/src/cmd/compile/internal/ssa/schedule_test.go
index c3f16b6..c541d48 100644
--- a/src/cmd/compile/internal/ssa/schedule_test.go
+++ b/src/cmd/compile/internal/ssa/schedule_test.go
@@ -14,9 +14,9 @@
Valu("mem0", OpInitMem, TypeMem, 0, nil),
Valu("ptr", OpConst64, TypeInt64, 0xABCD, nil),
Valu("v", OpConst64, TypeInt64, 12, nil),
- Valu("mem1", OpStore, TypeMem, 8, nil, "ptr", "v", "mem0"),
- Valu("mem2", OpStore, TypeMem, 8, nil, "ptr", "v", "mem1"),
- Valu("mem3", OpStore, TypeInt64, 8, nil, "ptr", "sum", "mem2"),
+ Valu("mem1", OpStore, TypeMem, 0, TypeInt64, "ptr", "v", "mem0"),
+ Valu("mem2", OpStore, TypeMem, 0, TypeInt64, "ptr", "v", "mem1"),
+ Valu("mem3", OpStore, TypeMem, 0, TypeInt64, "ptr", "sum", "mem2"),
Valu("l1", OpLoad, TypeInt64, 0, nil, "ptr", "mem1"),
Valu("l2", OpLoad, TypeInt64, 0, nil, "ptr", "mem2"),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "l1", "l2"),
@@ -63,11 +63,11 @@
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem0", OpInitMem, TypeMem, 0, nil),
- Valu("a", OpAdd64, TypeInt64, 0, nil, "b", "c"), // v2
- Valu("b", OpLoad, TypeInt64, 0, nil, "ptr", "mem1"), // v3
- Valu("c", OpNeg64, TypeInt64, 0, nil, "b"), // v4
- Valu("mem1", OpStore, TypeMem, 8, nil, "ptr", "v", "mem0"), // v5
- Valu("mem2", OpStore, TypeMem, 0, nil, "ptr", "a", "mem1"),
+ Valu("a", OpAdd64, TypeInt64, 0, nil, "b", "c"), // v2
+ Valu("b", OpLoad, TypeInt64, 0, nil, "ptr", "mem1"), // v3
+ Valu("c", OpNeg64, TypeInt64, 0, nil, "b"), // v4
+ Valu("mem1", OpStore, TypeMem, 0, TypeInt64, "ptr", "v", "mem0"), // v5
+ Valu("mem2", OpStore, TypeMem, 0, TypeInt64, "ptr", "a", "mem1"),
Valu("ptr", OpConst64, TypeInt64, 0xABCD, nil),
Valu("v", OpConst64, TypeInt64, 12, nil),
Goto("exit")),
diff --git a/src/cmd/compile/internal/ssa/shift_test.go b/src/cmd/compile/internal/ssa/shift_test.go
index e6a5f9b..8a3a429 100644
--- a/src/cmd/compile/internal/ssa/shift_test.go
+++ b/src/cmd/compile/internal/ssa/shift_test.go
@@ -41,7 +41,7 @@
Valu("load", OpLoad, typ, 0, nil, "argptr", "mem"),
Valu("c", OpConst64, TypeUInt64, amount, nil),
Valu("shift", op, typ, 0, nil, "load", "c"),
- Valu("store", OpStore, TypeMem, 8, TypeUInt64, "resptr", "shift", "mem"),
+ Valu("store", OpStore, TypeMem, 0, TypeUInt64, "resptr", "shift", "mem"),
Exit("store")))
Compile(fun.f)
return fun
@@ -101,7 +101,7 @@
Valu("c", OpConst64, TypeUInt64, amount, nil),
Valu("lshift", lshift, typ, 0, nil, "load", "c"),
Valu("rshift", rshift, typ, 0, nil, "lshift", "c"),
- Valu("store", OpStore, TypeMem, 8, TypeUInt64, "resptr", "rshift", "mem"),
+ Valu("store", OpStore, TypeMem, 0, TypeUInt64, "resptr", "rshift", "mem"),
Exit("store")))
Compile(fun.f)
return fun
diff --git a/src/cmd/compile/internal/ssa/value.go b/src/cmd/compile/internal/ssa/value.go
index 93172bc..9401ad5 100644
--- a/src/cmd/compile/internal/ssa/value.go
+++ b/src/cmd/compile/internal/ssa/value.go
@@ -128,17 +128,15 @@
return fmt.Sprintf(" [%d]", v.AuxInt32())
case auxInt64, auxInt128:
return fmt.Sprintf(" [%d]", v.AuxInt)
- case auxSizeAndAlign:
- return fmt.Sprintf(" [%s]", SizeAndAlign(v.AuxInt))
case auxFloat32, auxFloat64:
return fmt.Sprintf(" [%g]", v.AuxFloat())
case auxString:
return fmt.Sprintf(" {%q}", v.Aux)
- case auxSym:
+ case auxSym, auxTyp:
if v.Aux != nil {
return fmt.Sprintf(" {%v}", v.Aux)
}
- case auxSymOff, auxSymInt32:
+ case auxSymOff, auxSymInt32, auxTypSize:
s := ""
if v.Aux != nil {
s = fmt.Sprintf(" {%v}", v.Aux)
@@ -153,12 +151,6 @@
s = fmt.Sprintf(" {%v}", v.Aux)
}
return s + fmt.Sprintf(" [%s]", v.AuxValAndOff())
- case auxSymSizeAndAlign:
- s := ""
- if v.Aux != nil {
- s = fmt.Sprintf(" {%v}", v.Aux)
- }
- return s + fmt.Sprintf(" [%s]", SizeAndAlign(v.AuxInt))
}
return ""
}
diff --git a/src/cmd/compile/internal/ssa/writebarrier.go b/src/cmd/compile/internal/ssa/writebarrier.go
index 3e43d2f..ddc476a 100644
--- a/src/cmd/compile/internal/ssa/writebarrier.go
+++ b/src/cmd/compile/internal/ssa/writebarrier.go
@@ -173,26 +173,21 @@
for _, w := range stores {
var val *Value
ptr := w.Args[0]
- siz := w.AuxInt
var typ interface{}
if w.Op != OpStoreWB {
typ = &ExternSymbol{Typ: f.Config.fe.TypeUintptr(), Sym: w.Aux.(Type).Symbol()}
}
pos = w.Pos
- var op Op
var fn *obj.LSym
switch w.Op {
case OpStoreWB:
- op = OpStore
fn = writebarrierptr
val = w.Args[1]
case OpMoveWB:
- op = OpMove
fn = typedmemmove
val = w.Args[1]
case OpZeroWB:
- op = OpZero
fn = typedmemclr
}
@@ -201,10 +196,15 @@
memThen = wbcall(pos, bThen, fn, typ, ptr, val, memThen, sp, sb, volatile)
// else block: normal store
- if op == OpZero {
- memElse = bElse.NewValue2I(pos, op, TypeMem, siz, ptr, memElse)
- } else {
- memElse = bElse.NewValue3I(pos, op, TypeMem, siz, ptr, val, memElse)
+ switch w.Op {
+ case OpStoreWB:
+ memElse = bElse.NewValue3A(pos, OpStore, TypeMem, w.Aux, ptr, val, memElse)
+ case OpMoveWB:
+ memElse = bElse.NewValue3I(pos, OpMove, TypeMem, w.AuxInt, ptr, val, memElse)
+ memElse.Aux = w.Aux
+ case OpZeroWB:
+ memElse = bElse.NewValue2I(pos, OpZero, TypeMem, w.AuxInt, ptr, memElse)
+ memElse.Aux = w.Aux
}
if f.NoWB {
@@ -270,8 +270,9 @@
aux := &AutoSymbol{Typ: t, Node: tmp}
mem = b.NewValue1A(pos, OpVarDef, TypeMem, tmp, mem)
tmpaddr := b.NewValue1A(pos, OpAddr, t.PtrTo(), aux, sp)
- siz := MakeSizeAndAlign(t.Size(), t.Alignment()).Int64()
+ siz := t.Size()
mem = b.NewValue3I(pos, OpMove, TypeMem, siz, tmpaddr, val, mem)
+ mem.Aux = t
val = tmpaddr
}
@@ -282,19 +283,19 @@
taddr := b.NewValue1A(pos, OpAddr, config.fe.TypeUintptr(), typ, sb)
off = round(off, taddr.Type.Alignment())
arg := b.NewValue1I(pos, OpOffPtr, taddr.Type.PtrTo(), off, sp)
- mem = b.NewValue3I(pos, OpStore, TypeMem, ptr.Type.Size(), arg, taddr, mem)
+ mem = b.NewValue3A(pos, OpStore, TypeMem, ptr.Type, arg, taddr, mem)
off += taddr.Type.Size()
}
off = round(off, ptr.Type.Alignment())
arg := b.NewValue1I(pos, OpOffPtr, ptr.Type.PtrTo(), off, sp)
- mem = b.NewValue3I(pos, OpStore, TypeMem, ptr.Type.Size(), arg, ptr, mem)
+ mem = b.NewValue3A(pos, OpStore, TypeMem, ptr.Type, arg, ptr, mem)
off += ptr.Type.Size()
if val != nil {
off = round(off, val.Type.Alignment())
arg = b.NewValue1I(pos, OpOffPtr, val.Type.PtrTo(), off, sp)
- mem = b.NewValue3I(pos, OpStore, TypeMem, val.Type.Size(), arg, val, mem)
+ mem = b.NewValue3A(pos, OpStore, TypeMem, val.Type, arg, val, mem)
off += val.Type.Size()
}
off = round(off, config.PtrSize)
diff --git a/src/cmd/compile/internal/ssa/writebarrier_test.go b/src/cmd/compile/internal/ssa/writebarrier_test.go
index 422bc94..a4e95f9 100644
--- a/src/cmd/compile/internal/ssa/writebarrier_test.go
+++ b/src/cmd/compile/internal/ssa/writebarrier_test.go
@@ -17,8 +17,8 @@
Valu("sp", OpSP, TypeInvalid, 0, nil),
Valu("v", OpConstNil, ptrType, 0, nil),
Valu("addr1", OpAddr, ptrType, 0, nil, "sb"),
- Valu("wb2", OpStore, TypeMem, 8, ptrType, "addr1", "v", "wb1"),
- Valu("wb1", OpStore, TypeMem, 8, ptrType, "addr1", "v", "start"), // wb1 and wb2 are out of order
+ Valu("wb2", OpStore, TypeMem, 0, ptrType, "addr1", "v", "wb1"),
+ Valu("wb1", OpStore, TypeMem, 0, ptrType, "addr1", "v", "start"), // wb1 and wb2 are out of order
Goto("exit")),
Bloc("exit",
Exit("wb2")))
@@ -44,7 +44,7 @@
Valu("phi", OpPhi, TypeMem, 0, nil, "start", "wb"),
Valu("v", OpConstNil, ptrType, 0, nil),
Valu("addr", OpAddr, ptrType, 0, nil, "sb"),
- Valu("wb", OpStore, TypeMem, 8, ptrType, "addr", "v", "phi"), // has write barrier
+ Valu("wb", OpStore, TypeMem, 0, ptrType, "addr", "v", "phi"), // has write barrier
Goto("loop")))
CheckFunc(fun.f)
