cmd/internal/obj/arm64: add support for most system registers
This patch supports the EL0 and EL1 system registers used in MRS/MSR
instructions. This patch refactors the assembler code, allowing the
assembler to read system register information from the automatically
generated sysRegEnc.go file and move existing declared system registers
to the sysRegEnc.go file.
This patch adds 431 system registers, it is worth noting that the number
of special registers is initialized to less than 1024 in the list7.go file.
This CL also adds some test cases to test the newly added system registers.
The test cases are contributed by Dianhong Xu <Dianhong.Xu@arm.com>
Change-Id: Ic09a937eaaeefe82bd08b5dd726808f8ff6cebf6
Reviewed-on: https://go-review.googlesource.com/c/go/+/189577
Reviewed-by: Ben Shi <powerman1st@163.com>
Run-TryBot: Ben Shi <powerman1st@163.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go
index eaa5cb8..221d805 100644
--- a/src/cmd/asm/internal/arch/arch.go
+++ b/src/cmd/asm/internal/arch/arch.go
@@ -267,21 +267,15 @@
for i := arm64.REG_V0; i <= arm64.REG_V31; i++ {
register[obj.Rconv(i)] = int16(i)
}
+
+ // System registers.
+ for i := 0; i < len(arm64.SystemReg); i++ {
+ register[arm64.SystemReg[i].Name] = arm64.SystemReg[i].Reg
+ }
+
register["LR"] = arm64.REGLINK
- register["DAIF"] = arm64.REG_DAIF
- register["NZCV"] = arm64.REG_NZCV
- register["FPSR"] = arm64.REG_FPSR
- register["FPCR"] = arm64.REG_FPCR
- register["SPSR_EL1"] = arm64.REG_SPSR_EL1
- register["ELR_EL1"] = arm64.REG_ELR_EL1
- register["SPSR_EL2"] = arm64.REG_SPSR_EL2
- register["ELR_EL2"] = arm64.REG_ELR_EL2
- register["CurrentEL"] = arm64.REG_CurrentEL
- register["SP_EL0"] = arm64.REG_SP_EL0
- register["SPSel"] = arm64.REG_SPSel
register["DAIFSet"] = arm64.REG_DAIFSet
register["DAIFClr"] = arm64.REG_DAIFClr
- register["DCZID_EL0"] = arm64.REG_DCZID_EL0
register["PLDL1KEEP"] = arm64.REG_PLDL1KEEP
register["PLDL1STRM"] = arm64.REG_PLDL1STRM
register["PLDL2KEEP"] = arm64.REG_PLDL2KEEP
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 7767122..7fb475f 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -1009,6 +1009,567 @@
FSTPS (F3, F4), x(SB)
FSTPS (F3, F4), x+8(SB)
+// System Register
+ MSR $1, SPSel // bf4100d5
+ MSR $9, DAIFSet // df4903d5
+ MSR $6, DAIFClr // ff4603d5
+ MRS ELR_EL1, R8 // 284038d5
+ MSR R16, ELR_EL1 // 304018d5
+ MSR R2, ACTLR_EL1 // 221018d5
+ MRS TCR_EL1, R5 // 452038d5
+ MRS PMEVCNTR15_EL0, R12 // ece93bd5
+ MSR R20, PMEVTYPER26_EL0 // 54ef1bd5
+ MSR R10, DBGBCR15_EL1 // aa0f10d5
+ MRS ACTLR_EL1, R3 // 231038d5
+ MSR R9, ACTLR_EL1 // 291018d5
+ MRS AFSR0_EL1, R10 // 0a5138d5
+ MSR R1, AFSR0_EL1 // 015118d5
+ MRS AFSR0_EL1, R9 // 095138d5
+ MSR R30, AFSR0_EL1 // 1e5118d5
+ MRS AFSR1_EL1, R0 // 205138d5
+ MSR R1, AFSR1_EL1 // 215118d5
+ MRS AFSR1_EL1, R8 // 285138d5
+ MSR R19, AFSR1_EL1 // 335118d5
+ MRS AIDR_EL1, R11 // eb0039d5
+ MRS AMAIR_EL1, R0 // 00a338d5
+ MSR R22, AMAIR_EL1 // 16a318d5
+ MRS AMAIR_EL1, R14 // 0ea338d5
+ MSR R0, AMAIR_EL1 // 00a318d5
+ MRS APDAKeyHi_EL1, R16 // 302238d5
+ MSR R26, APDAKeyHi_EL1 // 3a2218d5
+ MRS APDAKeyLo_EL1, R21 // 152238d5
+ MSR R22, APDAKeyLo_EL1 // 162218d5
+ MRS APDBKeyHi_EL1, R2 // 622238d5
+ MSR R6, APDBKeyHi_EL1 // 662218d5
+ MRS APDBKeyLo_EL1, R5 // 452238d5
+ MSR R22, APDBKeyLo_EL1 // 562218d5
+ MRS APGAKeyHi_EL1, R22 // 362338d5
+ MSR R5, APGAKeyHi_EL1 // 252318d5
+ MRS APGAKeyLo_EL1, R16 // 102338d5
+ MSR R22, APGAKeyLo_EL1 // 162318d5
+ MRS APIAKeyHi_EL1, R23 // 372138d5
+ MSR R17, APIAKeyHi_EL1 // 312118d5
+ MRS APIAKeyLo_EL1, R16 // 102138d5
+ MSR R6, APIAKeyLo_EL1 // 062118d5
+ MRS APIBKeyHi_EL1, R10 // 6a2138d5
+ MSR R11, APIBKeyHi_EL1 // 6b2118d5
+ MRS APIBKeyLo_EL1, R25 // 592138d5
+ MSR R22, APIBKeyLo_EL1 // 562118d5
+ MRS CCSIDR_EL1, R25 // 190039d5
+ MRS CLIDR_EL1, R16 // 300039d5
+ MRS CNTFRQ_EL0, R20 // 14e03bd5
+ MSR R16, CNTFRQ_EL0 // 10e01bd5
+ MRS CNTKCTL_EL1, R26 // 1ae138d5
+ MSR R0, CNTKCTL_EL1 // 00e118d5
+ MRS CNTP_CTL_EL0, R14 // 2ee23bd5
+ MSR R17, CNTP_CTL_EL0 // 31e21bd5
+ MRS CNTP_CVAL_EL0, R15 // 4fe23bd5
+ MSR R8, CNTP_CVAL_EL0 // 48e21bd5
+ MRS CNTP_TVAL_EL0, R6 // 06e23bd5
+ MSR R29, CNTP_TVAL_EL0 // 1de21bd5
+ MRS CNTP_CTL_EL0, R22 // 36e23bd5
+ MSR R0, CNTP_CTL_EL0 // 20e21bd5
+ MRS CNTP_CVAL_EL0, R9 // 49e23bd5
+ MSR R4, CNTP_CVAL_EL0 // 44e21bd5
+ MRS CNTP_TVAL_EL0, R27 // 1be23bd5
+ MSR R17, CNTP_TVAL_EL0 // 11e21bd5
+ MRS CNTV_CTL_EL0, R27 // 3be33bd5
+ MSR R2, CNTV_CTL_EL0 // 22e31bd5
+ MRS CNTV_CVAL_EL0, R16 // 50e33bd5
+ MSR R27, CNTV_CVAL_EL0 // 5be31bd5
+ MRS CNTV_TVAL_EL0, R12 // 0ce33bd5
+ MSR R19, CNTV_TVAL_EL0 // 13e31bd5
+ MRS CNTV_CTL_EL0, R14 // 2ee33bd5
+ MSR R2, CNTV_CTL_EL0 // 22e31bd5
+ MRS CNTV_CVAL_EL0, R8 // 48e33bd5
+ MSR R26, CNTV_CVAL_EL0 // 5ae31bd5
+ MRS CNTV_TVAL_EL0, R6 // 06e33bd5
+ MSR R19, CNTV_TVAL_EL0 // 13e31bd5
+ MRS CNTKCTL_EL1, R16 // 10e138d5
+ MSR R26, CNTKCTL_EL1 // 1ae118d5
+ MRS CNTPCT_EL0, R9 // 29e03bd5
+ MRS CNTPS_CTL_EL1, R30 // 3ee23fd5
+ MSR R26, CNTPS_CTL_EL1 // 3ae21fd5
+ MRS CNTPS_CVAL_EL1, R8 // 48e23fd5
+ MSR R26, CNTPS_CVAL_EL1 // 5ae21fd5
+ MRS CNTPS_TVAL_EL1, R7 // 07e23fd5
+ MSR R13, CNTPS_TVAL_EL1 // 0de21fd5
+ MRS CNTP_CTL_EL0, R2 // 22e23bd5
+ MSR R10, CNTP_CTL_EL0 // 2ae21bd5
+ MRS CNTP_CVAL_EL0, R6 // 46e23bd5
+ MSR R21, CNTP_CVAL_EL0 // 55e21bd5
+ MRS CNTP_TVAL_EL0, R27 // 1be23bd5
+ MSR R29, CNTP_TVAL_EL0 // 1de21bd5
+ MRS CNTVCT_EL0, R13 // 4de03bd5
+ MRS CNTV_CTL_EL0, R30 // 3ee33bd5
+ MSR R19, CNTV_CTL_EL0 // 33e31bd5
+ MRS CNTV_CVAL_EL0, R27 // 5be33bd5
+ MSR R24, CNTV_CVAL_EL0 // 58e31bd5
+ MRS CNTV_TVAL_EL0, R24 // 18e33bd5
+ MSR R5, CNTV_TVAL_EL0 // 05e31bd5
+ MRS CONTEXTIDR_EL1, R15 // 2fd038d5
+ MSR R27, CONTEXTIDR_EL1 // 3bd018d5
+ MRS CONTEXTIDR_EL1, R29 // 3dd038d5
+ MSR R24, CONTEXTIDR_EL1 // 38d018d5
+ MRS CPACR_EL1, R10 // 4a1038d5
+ MSR R14, CPACR_EL1 // 4e1018d5
+ MRS CPACR_EL1, R27 // 5b1038d5
+ MSR R22, CPACR_EL1 // 561018d5
+ MRS CSSELR_EL1, R3 // 03003ad5
+ MSR R4, CSSELR_EL1 // 04001ad5
+ MRS CTR_EL0, R15 // 2f003bd5
+ MRS CurrentEL, R1 // 414238d5
+ MRS DAIF, R24 // 38423bd5
+ MSR R9, DAIF // 29421bd5
+ MRS DBGAUTHSTATUS_EL1, R5 // c57e30d5
+ MRS DBGBCR0_EL1, R29 // bd0030d5
+ MRS DBGBCR1_EL1, R13 // ad0130d5
+ MRS DBGBCR2_EL1, R22 // b60230d5
+ MRS DBGBCR3_EL1, R8 // a80330d5
+ MRS DBGBCR4_EL1, R2 // a20430d5
+ MRS DBGBCR5_EL1, R4 // a40530d5
+ MRS DBGBCR6_EL1, R2 // a20630d5
+ MRS DBGBCR7_EL1, R6 // a60730d5
+ MRS DBGBCR8_EL1, R1 // a10830d5
+ MRS DBGBCR9_EL1, R16 // b00930d5
+ MRS DBGBCR10_EL1, R23 // b70a30d5
+ MRS DBGBCR11_EL1, R3 // a30b30d5
+ MRS DBGBCR12_EL1, R6 // a60c30d5
+ MRS DBGBCR13_EL1, R16 // b00d30d5
+ MRS DBGBCR14_EL1, R4 // a40e30d5
+ MRS DBGBCR15_EL1, R9 // a90f30d5
+ MSR R4, DBGBCR0_EL1 // a40010d5
+ MSR R14, DBGBCR1_EL1 // ae0110d5
+ MSR R7, DBGBCR2_EL1 // a70210d5
+ MSR R12, DBGBCR3_EL1 // ac0310d5
+ MSR R6, DBGBCR4_EL1 // a60410d5
+ MSR R11, DBGBCR5_EL1 // ab0510d5
+ MSR R6, DBGBCR6_EL1 // a60610d5
+ MSR R13, DBGBCR7_EL1 // ad0710d5
+ MSR R17, DBGBCR8_EL1 // b10810d5
+ MSR R17, DBGBCR9_EL1 // b10910d5
+ MSR R22, DBGBCR10_EL1 // b60a10d5
+ MSR R16, DBGBCR11_EL1 // b00b10d5
+ MSR R24, DBGBCR12_EL1 // b80c10d5
+ MSR R29, DBGBCR13_EL1 // bd0d10d5
+ MSR R1, DBGBCR14_EL1 // a10e10d5
+ MSR R10, DBGBCR15_EL1 // aa0f10d5
+ MRS DBGBVR0_EL1, R16 // 900030d5
+ MRS DBGBVR1_EL1, R21 // 950130d5
+ MRS DBGBVR2_EL1, R13 // 8d0230d5
+ MRS DBGBVR3_EL1, R12 // 8c0330d5
+ MRS DBGBVR4_EL1, R20 // 940430d5
+ MRS DBGBVR5_EL1, R21 // 950530d5
+ MRS DBGBVR6_EL1, R27 // 9b0630d5
+ MRS DBGBVR7_EL1, R6 // 860730d5
+ MRS DBGBVR8_EL1, R14 // 8e0830d5
+ MRS DBGBVR9_EL1, R5 // 850930d5
+ MRS DBGBVR10_EL1, R9 // 890a30d5
+ MRS DBGBVR11_EL1, R25 // 990b30d5
+ MRS DBGBVR12_EL1, R30 // 9e0c30d5
+ MRS DBGBVR13_EL1, R1 // 810d30d5
+ MRS DBGBVR14_EL1, R17 // 910e30d5
+ MRS DBGBVR15_EL1, R25 // 990f30d5
+ MSR R15, DBGBVR0_EL1 // 8f0010d5
+ MSR R6, DBGBVR1_EL1 // 860110d5
+ MSR R24, DBGBVR2_EL1 // 980210d5
+ MSR R17, DBGBVR3_EL1 // 910310d5
+ MSR R3, DBGBVR4_EL1 // 830410d5
+ MSR R21, DBGBVR5_EL1 // 950510d5
+ MSR R5, DBGBVR6_EL1 // 850610d5
+ MSR R6, DBGBVR7_EL1 // 860710d5
+ MSR R25, DBGBVR8_EL1 // 990810d5
+ MSR R4, DBGBVR9_EL1 // 840910d5
+ MSR R25, DBGBVR10_EL1 // 990a10d5
+ MSR R17, DBGBVR11_EL1 // 910b10d5
+ MSR R0, DBGBVR12_EL1 // 800c10d5
+ MSR R5, DBGBVR13_EL1 // 850d10d5
+ MSR R9, DBGBVR14_EL1 // 890e10d5
+ MSR R12, DBGBVR15_EL1 // 8c0f10d5
+ MRS DBGCLAIMCLR_EL1, R27 // db7930d5
+ MSR R0, DBGCLAIMCLR_EL1 // c07910d5
+ MRS DBGCLAIMSET_EL1, R7 // c77830d5
+ MSR R13, DBGCLAIMSET_EL1 // cd7810d5
+ MRS DBGDTRRX_EL0, R0 // 000533d5
+ MSR R29, DBGDTRRX_EL0 // 1d0513d5
+ MRS DBGDTR_EL0, R27 // 1b0433d5
+ MSR R30, DBGDTR_EL0 // 1e0413d5
+ MRS DBGPRCR_EL1, R4 // 841430d5
+ MSR R0, DBGPRCR_EL1 // 801410d5
+ MRS DBGWCR0_EL1, R24 // f80030d5
+ MRS DBGWCR1_EL1, R19 // f30130d5
+ MRS DBGWCR2_EL1, R25 // f90230d5
+ MRS DBGWCR3_EL1, R0 // e00330d5
+ MRS DBGWCR4_EL1, R13 // ed0430d5
+ MRS DBGWCR5_EL1, R8 // e80530d5
+ MRS DBGWCR6_EL1, R22 // f60630d5
+ MRS DBGWCR7_EL1, R11 // eb0730d5
+ MRS DBGWCR8_EL1, R11 // eb0830d5
+ MRS DBGWCR9_EL1, R3 // e30930d5
+ MRS DBGWCR10_EL1, R17 // f10a30d5
+ MRS DBGWCR11_EL1, R21 // f50b30d5
+ MRS DBGWCR12_EL1, R10 // ea0c30d5
+ MRS DBGWCR13_EL1, R22 // f60d30d5
+ MRS DBGWCR14_EL1, R11 // eb0e30d5
+ MRS DBGWCR15_EL1, R0 // e00f30d5
+ MSR R24, DBGWCR0_EL1 // f80010d5
+ MSR R8, DBGWCR1_EL1 // e80110d5
+ MSR R17, DBGWCR2_EL1 // f10210d5
+ MSR R29, DBGWCR3_EL1 // fd0310d5
+ MSR R13, DBGWCR4_EL1 // ed0410d5
+ MSR R22, DBGWCR5_EL1 // f60510d5
+ MSR R3, DBGWCR6_EL1 // e30610d5
+ MSR R4, DBGWCR7_EL1 // e40710d5
+ MSR R7, DBGWCR8_EL1 // e70810d5
+ MSR R29, DBGWCR9_EL1 // fd0910d5
+ MSR R3, DBGWCR10_EL1 // e30a10d5
+ MSR R11, DBGWCR11_EL1 // eb0b10d5
+ MSR R20, DBGWCR12_EL1 // f40c10d5
+ MSR R6, DBGWCR13_EL1 // e60d10d5
+ MSR R22, DBGWCR14_EL1 // f60e10d5
+ MSR R25, DBGWCR15_EL1 // f90f10d5
+ MRS DBGWVR0_EL1, R14 // ce0030d5
+ MRS DBGWVR1_EL1, R16 // d00130d5
+ MRS DBGWVR2_EL1, R15 // cf0230d5
+ MRS DBGWVR3_EL1, R1 // c10330d5
+ MRS DBGWVR4_EL1, R26 // da0430d5
+ MRS DBGWVR5_EL1, R14 // ce0530d5
+ MRS DBGWVR6_EL1, R17 // d10630d5
+ MRS DBGWVR7_EL1, R22 // d60730d5
+ MRS DBGWVR8_EL1, R4 // c40830d5
+ MRS DBGWVR9_EL1, R3 // c30930d5
+ MRS DBGWVR10_EL1, R16 // d00a30d5
+ MRS DBGWVR11_EL1, R2 // c20b30d5
+ MRS DBGWVR12_EL1, R5 // c50c30d5
+ MRS DBGWVR13_EL1, R23 // d70d30d5
+ MRS DBGWVR14_EL1, R5 // c50e30d5
+ MRS DBGWVR15_EL1, R6 // c60f30d5
+ MSR R24, DBGWVR0_EL1 // d80010d5
+ MSR R6, DBGWVR1_EL1 // c60110d5
+ MSR R1, DBGWVR2_EL1 // c10210d5
+ MSR R24, DBGWVR3_EL1 // d80310d5
+ MSR R24, DBGWVR4_EL1 // d80410d5
+ MSR R0, DBGWVR5_EL1 // c00510d5
+ MSR R10, DBGWVR6_EL1 // ca0610d5
+ MSR R17, DBGWVR7_EL1 // d10710d5
+ MSR R7, DBGWVR8_EL1 // c70810d5
+ MSR R8, DBGWVR9_EL1 // c80910d5
+ MSR R15, DBGWVR10_EL1 // cf0a10d5
+ MSR R8, DBGWVR11_EL1 // c80b10d5
+ MSR R7, DBGWVR12_EL1 // c70c10d5
+ MSR R14, DBGWVR13_EL1 // ce0d10d5
+ MSR R16, DBGWVR14_EL1 // d00e10d5
+ MSR R5, DBGWVR15_EL1 // c50f10d5
+ MRS DCZID_EL0, R21 // f5003bd5
+ MRS DISR_EL1, R8 // 28c138d5
+ MSR R5, DISR_EL1 // 25c118d5
+ MRS DIT, R29 // bd423bd5
+ MSR R22, DIT // b6421bd5
+ MRS DLR_EL0, R25 // 39453bd5
+ MSR R9, DLR_EL0 // 29451bd5
+ MRS DSPSR_EL0, R3 // 03453bd5
+ MSR R10, DSPSR_EL0 // 0a451bd5
+ MRS ELR_EL1, R24 // 384038d5
+ MSR R3, ELR_EL1 // 234018d5
+ MRS ELR_EL1, R13 // 2d4038d5
+ MSR R27, ELR_EL1 // 3b4018d5
+ MRS ERRIDR_EL1, R30 // 1e5338d5
+ MRS ERRSELR_EL1, R21 // 355338d5
+ MSR R22, ERRSELR_EL1 // 365318d5
+ MRS ERXADDR_EL1, R30 // 7e5438d5
+ MSR R0, ERXADDR_EL1 // 605418d5
+ MRS ERXCTLR_EL1, R6 // 265438d5
+ MSR R9, ERXCTLR_EL1 // 295418d5
+ MRS ERXFR_EL1, R19 // 135438d5
+ MRS ERXMISC0_EL1, R20 // 145538d5
+ MSR R24, ERXMISC0_EL1 // 185518d5
+ MRS ERXMISC1_EL1, R15 // 2f5538d5
+ MSR R10, ERXMISC1_EL1 // 2a5518d5
+ MRS ERXSTATUS_EL1, R30 // 5e5438d5
+ MSR R3, ERXSTATUS_EL1 // 435418d5
+ MRS ESR_EL1, R6 // 065238d5
+ MSR R21, ESR_EL1 // 155218d5
+ MRS ESR_EL1, R17 // 115238d5
+ MSR R12, ESR_EL1 // 0c5218d5
+ MRS FAR_EL1, R3 // 036038d5
+ MSR R17, FAR_EL1 // 116018d5
+ MRS FAR_EL1, R9 // 096038d5
+ MSR R25, FAR_EL1 // 196018d5
+ MRS FPCR, R1 // 01443bd5
+ MSR R27, FPCR // 1b441bd5
+ MRS FPSR, R5 // 25443bd5
+ MSR R15, FPSR // 2f441bd5
+ MRS ID_AA64AFR0_EL1, R19 // 930538d5
+ MRS ID_AA64AFR1_EL1, R24 // b80538d5
+ MRS ID_AA64DFR0_EL1, R21 // 150538d5
+ MRS ID_AA64DFR1_EL1, R20 // 340538d5
+ MRS ID_AA64ISAR0_EL1, R4 // 040638d5
+ MRS ID_AA64ISAR1_EL1, R6 // 260638d5
+ MRS ID_AA64MMFR0_EL1, R0 // 000738d5
+ MRS ID_AA64MMFR1_EL1, R17 // 310738d5
+ MRS ID_AA64MMFR2_EL1, R23 // 570738d5
+ MRS ID_AA64PFR0_EL1, R20 // 140438d5
+ MRS ID_AA64PFR1_EL1, R26 // 3a0438d5
+ MRS ID_AA64ZFR0_EL1, R26 // 9a0438d5
+ MRS ID_AFR0_EL1, R21 // 750138d5
+ MRS ID_DFR0_EL1, R15 // 4f0138d5
+ MRS ID_ISAR0_EL1, R11 // 0b0238d5
+ MRS ID_ISAR1_EL1, R16 // 300238d5
+ MRS ID_ISAR2_EL1, R10 // 4a0238d5
+ MRS ID_ISAR3_EL1, R13 // 6d0238d5
+ MRS ID_ISAR4_EL1, R24 // 980238d5
+ MRS ID_ISAR5_EL1, R29 // bd0238d5
+ MRS ID_MMFR0_EL1, R10 // 8a0138d5
+ MRS ID_MMFR1_EL1, R29 // bd0138d5
+ MRS ID_MMFR2_EL1, R16 // d00138d5
+ MRS ID_MMFR3_EL1, R10 // ea0138d5
+ MRS ID_MMFR4_EL1, R23 // d70238d5
+ MRS ID_PFR0_EL1, R4 // 040138d5
+ MRS ID_PFR1_EL1, R12 // 2c0138d5
+ MRS ISR_EL1, R24 // 18c138d5
+ MRS MAIR_EL1, R20 // 14a238d5
+ MSR R21, MAIR_EL1 // 15a218d5
+ MRS MAIR_EL1, R20 // 14a238d5
+ MSR R5, MAIR_EL1 // 05a218d5
+ MRS MDCCINT_EL1, R23 // 170230d5
+ MSR R27, MDCCINT_EL1 // 1b0210d5
+ MRS MDCCSR_EL0, R19 // 130133d5
+ MRS MDRAR_EL1, R12 // 0c1030d5
+ MRS MDSCR_EL1, R15 // 4f0230d5
+ MSR R15, MDSCR_EL1 // 4f0210d5
+ MRS MIDR_EL1, R26 // 1a0038d5
+ MRS MPIDR_EL1, R25 // b90038d5
+ MRS MVFR0_EL1, R29 // 1d0338d5
+ MRS MVFR1_EL1, R7 // 270338d5
+ MRS MVFR2_EL1, R19 // 530338d5
+ MRS NZCV, R11 // 0b423bd5
+ MSR R10, NZCV // 0a421bd5
+ MRS OSDLR_EL1, R16 // 901330d5
+ MSR R21, OSDLR_EL1 // 951310d5
+ MRS OSDTRRX_EL1, R5 // 450030d5
+ MSR R30, OSDTRRX_EL1 // 5e0010d5
+ MRS OSDTRTX_EL1, R3 // 430330d5
+ MSR R13, OSDTRTX_EL1 // 4d0310d5
+ MRS OSECCR_EL1, R2 // 420630d5
+ MSR R17, OSECCR_EL1 // 510610d5
+ MSR R3, OSLAR_EL1 // 831010d5
+ MRS OSLSR_EL1, R15 // 8f1130d5
+ MRS PAN, R14 // 6e4238d5
+ MSR R0, PAN // 604218d5
+ MRS PAR_EL1, R27 // 1b7438d5
+ MSR R3, PAR_EL1 // 037418d5
+ MRS PMCCFILTR_EL0, R10 // eaef3bd5
+ MSR R16, PMCCFILTR_EL0 // f0ef1bd5
+ MRS PMCCNTR_EL0, R17 // 119d3bd5
+ MSR R13, PMCCNTR_EL0 // 0d9d1bd5
+ MRS PMCEID0_EL0, R8 // c89c3bd5
+ MRS PMCEID1_EL0, R30 // fe9c3bd5
+ MRS PMCNTENCLR_EL0, R11 // 4b9c3bd5
+ MSR R21, PMCNTENCLR_EL0 // 559c1bd5
+ MRS PMCNTENSET_EL0, R25 // 399c3bd5
+ MSR R13, PMCNTENSET_EL0 // 2d9c1bd5
+ MRS PMCR_EL0, R23 // 179c3bd5
+ MSR R11, PMCR_EL0 // 0b9c1bd5
+ MRS PMEVCNTR0_EL0, R27 // 1be83bd5
+ MRS PMEVCNTR1_EL0, R23 // 37e83bd5
+ MRS PMEVCNTR2_EL0, R26 // 5ae83bd5
+ MRS PMEVCNTR3_EL0, R11 // 6be83bd5
+ MRS PMEVCNTR4_EL0, R14 // 8ee83bd5
+ MRS PMEVCNTR5_EL0, R9 // a9e83bd5
+ MRS PMEVCNTR6_EL0, R30 // dee83bd5
+ MRS PMEVCNTR7_EL0, R19 // f3e83bd5
+ MRS PMEVCNTR8_EL0, R5 // 05e93bd5
+ MRS PMEVCNTR9_EL0, R27 // 3be93bd5
+ MRS PMEVCNTR10_EL0, R23 // 57e93bd5
+ MRS PMEVCNTR11_EL0, R27 // 7be93bd5
+ MRS PMEVCNTR12_EL0, R0 // 80e93bd5
+ MRS PMEVCNTR13_EL0, R13 // ade93bd5
+ MRS PMEVCNTR14_EL0, R27 // dbe93bd5
+ MRS PMEVCNTR15_EL0, R16 // f0e93bd5
+ MRS PMEVCNTR16_EL0, R16 // 10ea3bd5
+ MRS PMEVCNTR17_EL0, R14 // 2eea3bd5
+ MRS PMEVCNTR18_EL0, R10 // 4aea3bd5
+ MRS PMEVCNTR19_EL0, R12 // 6cea3bd5
+ MRS PMEVCNTR20_EL0, R5 // 85ea3bd5
+ MRS PMEVCNTR21_EL0, R26 // baea3bd5
+ MRS PMEVCNTR22_EL0, R19 // d3ea3bd5
+ MRS PMEVCNTR23_EL0, R5 // e5ea3bd5
+ MRS PMEVCNTR24_EL0, R17 // 11eb3bd5
+ MRS PMEVCNTR25_EL0, R0 // 20eb3bd5
+ MRS PMEVCNTR26_EL0, R20 // 54eb3bd5
+ MRS PMEVCNTR27_EL0, R12 // 6ceb3bd5
+ MRS PMEVCNTR28_EL0, R29 // 9deb3bd5
+ MRS PMEVCNTR29_EL0, R22 // b6eb3bd5
+ MRS PMEVCNTR30_EL0, R22 // d6eb3bd5
+ MSR R30, PMEVCNTR0_EL0 // 1ee81bd5
+ MSR R1, PMEVCNTR1_EL0 // 21e81bd5
+ MSR R20, PMEVCNTR2_EL0 // 54e81bd5
+ MSR R9, PMEVCNTR3_EL0 // 69e81bd5
+ MSR R8, PMEVCNTR4_EL0 // 88e81bd5
+ MSR R2, PMEVCNTR5_EL0 // a2e81bd5
+ MSR R30, PMEVCNTR6_EL0 // dee81bd5
+ MSR R14, PMEVCNTR7_EL0 // eee81bd5
+ MSR R1, PMEVCNTR8_EL0 // 01e91bd5
+ MSR R15, PMEVCNTR9_EL0 // 2fe91bd5
+ MSR R15, PMEVCNTR10_EL0 // 4fe91bd5
+ MSR R14, PMEVCNTR11_EL0 // 6ee91bd5
+ MSR R15, PMEVCNTR12_EL0 // 8fe91bd5
+ MSR R25, PMEVCNTR13_EL0 // b9e91bd5
+ MSR R26, PMEVCNTR14_EL0 // dae91bd5
+ MSR R21, PMEVCNTR15_EL0 // f5e91bd5
+ MSR R29, PMEVCNTR16_EL0 // 1dea1bd5
+ MSR R11, PMEVCNTR17_EL0 // 2bea1bd5
+ MSR R16, PMEVCNTR18_EL0 // 50ea1bd5
+ MSR R2, PMEVCNTR19_EL0 // 62ea1bd5
+ MSR R19, PMEVCNTR20_EL0 // 93ea1bd5
+ MSR R17, PMEVCNTR21_EL0 // b1ea1bd5
+ MSR R7, PMEVCNTR22_EL0 // c7ea1bd5
+ MSR R23, PMEVCNTR23_EL0 // f7ea1bd5
+ MSR R15, PMEVCNTR24_EL0 // 0feb1bd5
+ MSR R27, PMEVCNTR25_EL0 // 3beb1bd5
+ MSR R13, PMEVCNTR26_EL0 // 4deb1bd5
+ MSR R2, PMEVCNTR27_EL0 // 62eb1bd5
+ MSR R15, PMEVCNTR28_EL0 // 8feb1bd5
+ MSR R14, PMEVCNTR29_EL0 // aeeb1bd5
+ MSR R23, PMEVCNTR30_EL0 // d7eb1bd5
+ MRS PMEVTYPER0_EL0, R23 // 17ec3bd5
+ MRS PMEVTYPER1_EL0, R30 // 3eec3bd5
+ MRS PMEVTYPER2_EL0, R12 // 4cec3bd5
+ MRS PMEVTYPER3_EL0, R13 // 6dec3bd5
+ MRS PMEVTYPER4_EL0, R25 // 99ec3bd5
+ MRS PMEVTYPER5_EL0, R23 // b7ec3bd5
+ MRS PMEVTYPER6_EL0, R8 // c8ec3bd5
+ MRS PMEVTYPER7_EL0, R2 // e2ec3bd5
+ MRS PMEVTYPER8_EL0, R23 // 17ed3bd5
+ MRS PMEVTYPER9_EL0, R25 // 39ed3bd5
+ MRS PMEVTYPER10_EL0, R0 // 40ed3bd5
+ MRS PMEVTYPER11_EL0, R30 // 7eed3bd5
+ MRS PMEVTYPER12_EL0, R0 // 80ed3bd5
+ MRS PMEVTYPER13_EL0, R9 // a9ed3bd5
+ MRS PMEVTYPER14_EL0, R15 // cfed3bd5
+ MRS PMEVTYPER15_EL0, R13 // eded3bd5
+ MRS PMEVTYPER16_EL0, R11 // 0bee3bd5
+ MRS PMEVTYPER17_EL0, R19 // 33ee3bd5
+ MRS PMEVTYPER18_EL0, R3 // 43ee3bd5
+ MRS PMEVTYPER19_EL0, R17 // 71ee3bd5
+ MRS PMEVTYPER20_EL0, R8 // 88ee3bd5
+ MRS PMEVTYPER21_EL0, R2 // a2ee3bd5
+ MRS PMEVTYPER22_EL0, R5 // c5ee3bd5
+ MRS PMEVTYPER23_EL0, R17 // f1ee3bd5
+ MRS PMEVTYPER24_EL0, R22 // 16ef3bd5
+ MRS PMEVTYPER25_EL0, R3 // 23ef3bd5
+ MRS PMEVTYPER26_EL0, R23 // 57ef3bd5
+ MRS PMEVTYPER27_EL0, R19 // 73ef3bd5
+ MRS PMEVTYPER28_EL0, R24 // 98ef3bd5
+ MRS PMEVTYPER29_EL0, R3 // a3ef3bd5
+ MRS PMEVTYPER30_EL0, R1 // c1ef3bd5
+ MSR R20, PMEVTYPER0_EL0 // 14ec1bd5
+ MSR R20, PMEVTYPER1_EL0 // 34ec1bd5
+ MSR R14, PMEVTYPER2_EL0 // 4eec1bd5
+ MSR R26, PMEVTYPER3_EL0 // 7aec1bd5
+ MSR R11, PMEVTYPER4_EL0 // 8bec1bd5
+ MSR R16, PMEVTYPER5_EL0 // b0ec1bd5
+ MSR R29, PMEVTYPER6_EL0 // ddec1bd5
+ MSR R3, PMEVTYPER7_EL0 // e3ec1bd5
+ MSR R30, PMEVTYPER8_EL0 // 1eed1bd5
+ MSR R17, PMEVTYPER9_EL0 // 31ed1bd5
+ MSR R10, PMEVTYPER10_EL0 // 4aed1bd5
+ MSR R19, PMEVTYPER11_EL0 // 73ed1bd5
+ MSR R13, PMEVTYPER12_EL0 // 8ded1bd5
+ MSR R23, PMEVTYPER13_EL0 // b7ed1bd5
+ MSR R13, PMEVTYPER14_EL0 // cded1bd5
+ MSR R9, PMEVTYPER15_EL0 // e9ed1bd5
+ MSR R1, PMEVTYPER16_EL0 // 01ee1bd5
+ MSR R19, PMEVTYPER17_EL0 // 33ee1bd5
+ MSR R22, PMEVTYPER18_EL0 // 56ee1bd5
+ MSR R23, PMEVTYPER19_EL0 // 77ee1bd5
+ MSR R30, PMEVTYPER20_EL0 // 9eee1bd5
+ MSR R9, PMEVTYPER21_EL0 // a9ee1bd5
+ MSR R3, PMEVTYPER22_EL0 // c3ee1bd5
+ MSR R1, PMEVTYPER23_EL0 // e1ee1bd5
+ MSR R16, PMEVTYPER24_EL0 // 10ef1bd5
+ MSR R12, PMEVTYPER25_EL0 // 2cef1bd5
+ MSR R7, PMEVTYPER26_EL0 // 47ef1bd5
+ MSR R9, PMEVTYPER27_EL0 // 69ef1bd5
+ MSR R10, PMEVTYPER28_EL0 // 8aef1bd5
+ MSR R5, PMEVTYPER29_EL0 // a5ef1bd5
+ MSR R12, PMEVTYPER30_EL0 // ccef1bd5
+ MRS PMINTENCLR_EL1, R24 // 589e38d5
+ MSR R15, PMINTENCLR_EL1 // 4f9e18d5
+ MRS PMINTENSET_EL1, R1 // 219e38d5
+ MSR R4, PMINTENSET_EL1 // 249e18d5
+ MRS PMOVSCLR_EL0, R6 // 669c3bd5
+ MSR R30, PMOVSCLR_EL0 // 7e9c1bd5
+ MRS PMOVSSET_EL0, R16 // 709e3bd5
+ MSR R12, PMOVSSET_EL0 // 6c9e1bd5
+ MRS PMSELR_EL0, R30 // be9c3bd5
+ MSR R5, PMSELR_EL0 // a59c1bd5
+ MSR R27, PMSWINC_EL0 // 9b9c1bd5
+ MRS PMUSERENR_EL0, R8 // 089e3bd5
+ MSR R6, PMUSERENR_EL0 // 069e1bd5
+ MRS PMXEVCNTR_EL0, R26 // 5a9d3bd5
+ MSR R10, PMXEVCNTR_EL0 // 4a9d1bd5
+ MRS PMXEVTYPER_EL0, R4 // 249d3bd5
+ MSR R4, PMXEVTYPER_EL0 // 249d1bd5
+ MRS REVIDR_EL1, R29 // dd0038d5
+ MRS RMR_EL1, R4 // 44c038d5
+ MSR R0, RMR_EL1 // 40c018d5
+ MRS RVBAR_EL1, R7 // 27c038d5
+ MRS SCTLR_EL1, R8 // 081038d5
+ MSR R0, SCTLR_EL1 // 001018d5
+ MRS SCTLR_EL1, R30 // 1e1038d5
+ MSR R13, SCTLR_EL1 // 0d1018d5
+ MRS SPSR_EL1, R1 // 014038d5
+ MSR R2, SPSR_EL1 // 024018d5
+ MRS SPSR_EL1, R3 // 034038d5
+ MSR R14, SPSR_EL1 // 0e4018d5
+ MRS SPSR_abt, R12 // 2c433cd5
+ MSR R4, SPSR_abt // 24431cd5
+ MRS SPSR_fiq, R17 // 71433cd5
+ MSR R9, SPSR_fiq // 69431cd5
+ MRS SPSR_irq, R12 // 0c433cd5
+ MSR R23, SPSR_irq // 17431cd5
+ MRS SPSR_und, R29 // 5d433cd5
+ MSR R3, SPSR_und // 43431cd5
+ MRS SPSel, R29 // 1d4238d5
+ MSR R1, SPSel // 014218d5
+ MRS SP_EL0, R10 // 0a4138d5
+ MSR R4, SP_EL0 // 044118d5
+ MRS SP_EL1, R22 // 16413cd5
+ MSR R17, SP_EL1 // 11411cd5
+ MRS TCR_EL1, R17 // 512038d5
+ MSR R23, TCR_EL1 // 572018d5
+ MRS TCR_EL1, R14 // 4e2038d5
+ MSR R29, TCR_EL1 // 5d2018d5
+ MRS TPIDRRO_EL0, R26 // 7ad03bd5
+ MSR R16, TPIDRRO_EL0 // 70d01bd5
+ MRS TPIDR_EL0, R23 // 57d03bd5
+ MSR R5, TPIDR_EL0 // 45d01bd5
+ MRS TPIDR_EL1, R17 // 91d038d5
+ MSR R22, TPIDR_EL1 // 96d018d5
+ MRS TTBR0_EL1, R30 // 1e2038d5
+ MSR R29, TTBR0_EL1 // 1d2018d5
+ MRS TTBR0_EL1, R23 // 172038d5
+ MSR R15, TTBR0_EL1 // 0f2018d5
+ MRS TTBR1_EL1, R5 // 252038d5
+ MSR R26, TTBR1_EL1 // 3a2018d5
+ MRS TTBR1_EL1, R19 // 332038d5
+ MSR R23, TTBR1_EL1 // 372018d5
+ MRS UAO, R22 // 964238d5
+ MSR R4, UAO // 844218d5
+ MRS VBAR_EL1, R23 // 17c038d5
+ MSR R2, VBAR_EL1 // 02c018d5
+ MRS VBAR_EL1, R6 // 06c038d5
+ MSR R3, VBAR_EL1 // 03c018d5
+ MRS DISR_EL1, R12 // 2cc138d5
+ MSR R24, DISR_EL1 // 38c118d5
+ MRS MPIDR_EL1, R1 // a10038d5
+ MRS MIDR_EL1, R13 // 0d0038d5
+ MRS ZCR_EL1, R24 // 181238d5
+ MSR R13, ZCR_EL1 // 0d1218d5
+ MRS ZCR_EL1, R23 // 171238d5
+ MSR R17, ZCR_EL1 // 111218d5
+
// END
//
// LTYPEE comma
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index 4379f01..53345b1 100644
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -195,22 +195,12 @@
// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
// a special register and the low bits select the register.
+// AUTO_SYSREG_END is the last item in the automatically generated system register
+// declaration, and it is defined in the sysRegEnc.go file.
const (
- REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota
- REG_DAIF
- REG_NZCV
- REG_FPSR
- REG_FPCR
- REG_SPSR_EL1
- REG_ELR_EL1
- REG_SPSR_EL2
- REG_ELR_EL2
- REG_CurrentEL
- REG_SP_EL0
- REG_SPSel
- REG_DAIFSet
+ REG_SPECIAL = obj.RBaseARM64 + 1<<12
+ REG_DAIFSet = AUTO_SYSREG_END + iota
REG_DAIFClr
- REG_DCZID_EL0
REG_PLDL1KEEP
REG_PLDL1STRM
REG_PLDL2KEEP
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index ef9991a..4cae74c 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -842,15 +842,6 @@
{REG_DAIFClr, 3<<16 | 4<<12 | 7<<5},
}
-// the System register values, and value to use in instruction
-var systemreg = []struct {
- reg int16
- enc uint32
-}{
- {REG_ELR_EL1, 8<<16 | 4<<12 | 1<<5},
- {REG_DCZID_EL0, 3<<19 | 3<<16 | 7<<5},
-}
-
var prfopfield = []struct {
reg int16
enc uint32
@@ -3513,12 +3504,8 @@
o1 = c.oprrr(p, AMRS)
v := uint32(0)
- for i := 0; i < len(systemreg); i++ {
- if systemreg[i].reg == p.From.Reg {
- v = systemreg[i].enc
- break
- }
- }
+ // SysRegEnc function returns the system register encoding.
+ _, v = SysRegEnc(p.From.Reg)
if v == 0 {
c.ctxt.Diag("illegal system register:\n%v", p)
}
@@ -3533,12 +3520,8 @@
o1 = c.oprrr(p, AMSR)
v := uint32(0)
- for i := 0; i < len(systemreg); i++ {
- if systemreg[i].reg == p.To.Reg {
- v = systemreg[i].enc
- break
- }
- }
+ // SysRegEnc function returns the system register encoding.
+ _, v = SysRegEnc(p.To.Reg)
if v == 0 {
c.ctxt.Diag("illegal system register:\n%v", p)
}
diff --git a/src/cmd/internal/obj/arm64/list7.go b/src/cmd/internal/obj/arm64/list7.go
index a7df1a7..a4bf005 100644
--- a/src/cmd/internal/obj/arm64/list7.go
+++ b/src/cmd/internal/obj/arm64/list7.go
@@ -112,34 +112,10 @@
return strcond[r-COND_EQ]
case r == REGSP:
return "RSP"
- case r == REG_DAIF:
- return "DAIF"
- case r == REG_NZCV:
- return "NZCV"
- case r == REG_FPSR:
- return "FPSR"
- case r == REG_FPCR:
- return "FPCR"
- case r == REG_SPSR_EL1:
- return "SPSR_EL1"
- case r == REG_ELR_EL1:
- return "ELR_EL1"
- case r == REG_SPSR_EL2:
- return "SPSR_EL2"
- case r == REG_ELR_EL2:
- return "ELR_EL2"
- case r == REG_CurrentEL:
- return "CurrentEL"
- case r == REG_SP_EL0:
- return "SP_EL0"
- case r == REG_SPSel:
- return "SPSel"
case r == REG_DAIFSet:
return "DAIFSet"
case r == REG_DAIFClr:
return "DAIFClr"
- case r == REG_DCZID_EL0:
- return "DCZID_EL0"
case r == REG_PLDL1KEEP:
return "PLDL1KEEP"
case r == REG_PLDL1STRM:
@@ -232,6 +208,11 @@
case REG_ELEM <= r && r < REG_ELEM_END:
return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
}
+ // Return system register name.
+ name, _ := SysRegEnc(int16(r))
+ if name != "" {
+ return name
+ }
return fmt.Sprintf("badreg(%d)", r)
}
diff --git a/src/cmd/internal/obj/arm64/sysRegEnc.go b/src/cmd/internal/obj/arm64/sysRegEnc.go
new file mode 100644
index 0000000..ac6dcec
--- /dev/null
+++ b/src/cmd/internal/obj/arm64/sysRegEnc.go
@@ -0,0 +1,892 @@
+// DO NOT EDIT
+// This file is auto-generated by the following steps, and the sysreggen.go is located at x/arch/arm64/arm64spec/.
+// 1. Get the system register xml files from https://developer.arm.com/-/media/Files/ATG/Beta10/SysReg_xml_v85A-2019-06.tar.gz
+// 2. Extract SysReg_xml_v85A-2019-06.tar/SysReg_xml_v85A-2019-06/SysReg_xml_v85A-2019-06/AArch64-*.xml to ./files folder
+// 3. Run the command: go run sysreggen.go
+
+package arm64
+
+const (
+ AUTO_SYSREG_BEGIN = REG_SPECIAL + iota
+ REG_ACTLR_EL1
+ REG_AFSR0_EL1
+ REG_AFSR1_EL1
+ REG_AIDR_EL1
+ REG_AMAIR_EL1
+ REG_AMCFGR_EL0
+ REG_AMCGCR_EL0
+ REG_AMCNTENCLR0_EL0
+ REG_AMCNTENCLR1_EL0
+ REG_AMCNTENSET0_EL0
+ REG_AMCNTENSET1_EL0
+ REG_AMCR_EL0
+ REG_AMEVCNTR00_EL0
+ REG_AMEVCNTR01_EL0
+ REG_AMEVCNTR02_EL0
+ REG_AMEVCNTR03_EL0
+ REG_AMEVCNTR04_EL0
+ REG_AMEVCNTR05_EL0
+ REG_AMEVCNTR06_EL0
+ REG_AMEVCNTR07_EL0
+ REG_AMEVCNTR08_EL0
+ REG_AMEVCNTR09_EL0
+ REG_AMEVCNTR010_EL0
+ REG_AMEVCNTR011_EL0
+ REG_AMEVCNTR012_EL0
+ REG_AMEVCNTR013_EL0
+ REG_AMEVCNTR014_EL0
+ REG_AMEVCNTR015_EL0
+ REG_AMEVCNTR10_EL0
+ REG_AMEVCNTR11_EL0
+ REG_AMEVCNTR12_EL0
+ REG_AMEVCNTR13_EL0
+ REG_AMEVCNTR14_EL0
+ REG_AMEVCNTR15_EL0
+ REG_AMEVCNTR16_EL0
+ REG_AMEVCNTR17_EL0
+ REG_AMEVCNTR18_EL0
+ REG_AMEVCNTR19_EL0
+ REG_AMEVCNTR110_EL0
+ REG_AMEVCNTR111_EL0
+ REG_AMEVCNTR112_EL0
+ REG_AMEVCNTR113_EL0
+ REG_AMEVCNTR114_EL0
+ REG_AMEVCNTR115_EL0
+ REG_AMEVTYPER00_EL0
+ REG_AMEVTYPER01_EL0
+ REG_AMEVTYPER02_EL0
+ REG_AMEVTYPER03_EL0
+ REG_AMEVTYPER04_EL0
+ REG_AMEVTYPER05_EL0
+ REG_AMEVTYPER06_EL0
+ REG_AMEVTYPER07_EL0
+ REG_AMEVTYPER08_EL0
+ REG_AMEVTYPER09_EL0
+ REG_AMEVTYPER010_EL0
+ REG_AMEVTYPER011_EL0
+ REG_AMEVTYPER012_EL0
+ REG_AMEVTYPER013_EL0
+ REG_AMEVTYPER014_EL0
+ REG_AMEVTYPER015_EL0
+ REG_AMEVTYPER10_EL0
+ REG_AMEVTYPER11_EL0
+ REG_AMEVTYPER12_EL0
+ REG_AMEVTYPER13_EL0
+ REG_AMEVTYPER14_EL0
+ REG_AMEVTYPER15_EL0
+ REG_AMEVTYPER16_EL0
+ REG_AMEVTYPER17_EL0
+ REG_AMEVTYPER18_EL0
+ REG_AMEVTYPER19_EL0
+ REG_AMEVTYPER110_EL0
+ REG_AMEVTYPER111_EL0
+ REG_AMEVTYPER112_EL0
+ REG_AMEVTYPER113_EL0
+ REG_AMEVTYPER114_EL0
+ REG_AMEVTYPER115_EL0
+ REG_AMUSERENR_EL0
+ REG_APDAKeyHi_EL1
+ REG_APDAKeyLo_EL1
+ REG_APDBKeyHi_EL1
+ REG_APDBKeyLo_EL1
+ REG_APGAKeyHi_EL1
+ REG_APGAKeyLo_EL1
+ REG_APIAKeyHi_EL1
+ REG_APIAKeyLo_EL1
+ REG_APIBKeyHi_EL1
+ REG_APIBKeyLo_EL1
+ REG_CCSIDR2_EL1
+ REG_CCSIDR_EL1
+ REG_CLIDR_EL1
+ REG_CNTFRQ_EL0
+ REG_CNTKCTL_EL1
+ REG_CNTP_CTL_EL0
+ REG_CNTP_CVAL_EL0
+ REG_CNTP_TVAL_EL0
+ REG_CNTPCT_EL0
+ REG_CNTPS_CTL_EL1
+ REG_CNTPS_CVAL_EL1
+ REG_CNTPS_TVAL_EL1
+ REG_CNTV_CTL_EL0
+ REG_CNTV_CVAL_EL0
+ REG_CNTV_TVAL_EL0
+ REG_CNTVCT_EL0
+ REG_CONTEXTIDR_EL1
+ REG_CPACR_EL1
+ REG_CSSELR_EL1
+ REG_CTR_EL0
+ REG_CurrentEL
+ REG_DAIF
+ REG_DBGAUTHSTATUS_EL1
+ REG_DBGBCR0_EL1
+ REG_DBGBCR1_EL1
+ REG_DBGBCR2_EL1
+ REG_DBGBCR3_EL1
+ REG_DBGBCR4_EL1
+ REG_DBGBCR5_EL1
+ REG_DBGBCR6_EL1
+ REG_DBGBCR7_EL1
+ REG_DBGBCR8_EL1
+ REG_DBGBCR9_EL1
+ REG_DBGBCR10_EL1
+ REG_DBGBCR11_EL1
+ REG_DBGBCR12_EL1
+ REG_DBGBCR13_EL1
+ REG_DBGBCR14_EL1
+ REG_DBGBCR15_EL1
+ REG_DBGBVR0_EL1
+ REG_DBGBVR1_EL1
+ REG_DBGBVR2_EL1
+ REG_DBGBVR3_EL1
+ REG_DBGBVR4_EL1
+ REG_DBGBVR5_EL1
+ REG_DBGBVR6_EL1
+ REG_DBGBVR7_EL1
+ REG_DBGBVR8_EL1
+ REG_DBGBVR9_EL1
+ REG_DBGBVR10_EL1
+ REG_DBGBVR11_EL1
+ REG_DBGBVR12_EL1
+ REG_DBGBVR13_EL1
+ REG_DBGBVR14_EL1
+ REG_DBGBVR15_EL1
+ REG_DBGCLAIMCLR_EL1
+ REG_DBGCLAIMSET_EL1
+ REG_DBGDTR_EL0
+ REG_DBGDTRRX_EL0
+ REG_DBGDTRTX_EL0
+ REG_DBGPRCR_EL1
+ REG_DBGWCR0_EL1
+ REG_DBGWCR1_EL1
+ REG_DBGWCR2_EL1
+ REG_DBGWCR3_EL1
+ REG_DBGWCR4_EL1
+ REG_DBGWCR5_EL1
+ REG_DBGWCR6_EL1
+ REG_DBGWCR7_EL1
+ REG_DBGWCR8_EL1
+ REG_DBGWCR9_EL1
+ REG_DBGWCR10_EL1
+ REG_DBGWCR11_EL1
+ REG_DBGWCR12_EL1
+ REG_DBGWCR13_EL1
+ REG_DBGWCR14_EL1
+ REG_DBGWCR15_EL1
+ REG_DBGWVR0_EL1
+ REG_DBGWVR1_EL1
+ REG_DBGWVR2_EL1
+ REG_DBGWVR3_EL1
+ REG_DBGWVR4_EL1
+ REG_DBGWVR5_EL1
+ REG_DBGWVR6_EL1
+ REG_DBGWVR7_EL1
+ REG_DBGWVR8_EL1
+ REG_DBGWVR9_EL1
+ REG_DBGWVR10_EL1
+ REG_DBGWVR11_EL1
+ REG_DBGWVR12_EL1
+ REG_DBGWVR13_EL1
+ REG_DBGWVR14_EL1
+ REG_DBGWVR15_EL1
+ REG_DCZID_EL0
+ REG_DISR_EL1
+ REG_DIT
+ REG_DLR_EL0
+ REG_DSPSR_EL0
+ REG_ELR_EL1
+ REG_ERRIDR_EL1
+ REG_ERRSELR_EL1
+ REG_ERXADDR_EL1
+ REG_ERXCTLR_EL1
+ REG_ERXFR_EL1
+ REG_ERXMISC0_EL1
+ REG_ERXMISC1_EL1
+ REG_ERXMISC2_EL1
+ REG_ERXMISC3_EL1
+ REG_ERXPFGCDN_EL1
+ REG_ERXPFGCTL_EL1
+ REG_ERXPFGF_EL1
+ REG_ERXSTATUS_EL1
+ REG_ESR_EL1
+ REG_FAR_EL1
+ REG_FPCR
+ REG_FPSR
+ REG_GCR_EL1
+ REG_GMID_EL1
+ REG_ICC_AP0R0_EL1
+ REG_ICC_AP0R1_EL1
+ REG_ICC_AP0R2_EL1
+ REG_ICC_AP0R3_EL1
+ REG_ICC_AP1R0_EL1
+ REG_ICC_AP1R1_EL1
+ REG_ICC_AP1R2_EL1
+ REG_ICC_AP1R3_EL1
+ REG_ICC_ASGI1R_EL1
+ REG_ICC_BPR0_EL1
+ REG_ICC_BPR1_EL1
+ REG_ICC_CTLR_EL1
+ REG_ICC_DIR_EL1
+ REG_ICC_EOIR0_EL1
+ REG_ICC_EOIR1_EL1
+ REG_ICC_HPPIR0_EL1
+ REG_ICC_HPPIR1_EL1
+ REG_ICC_IAR0_EL1
+ REG_ICC_IAR1_EL1
+ REG_ICC_IGRPEN0_EL1
+ REG_ICC_IGRPEN1_EL1
+ REG_ICC_PMR_EL1
+ REG_ICC_RPR_EL1
+ REG_ICC_SGI0R_EL1
+ REG_ICC_SGI1R_EL1
+ REG_ICC_SRE_EL1
+ REG_ICV_AP0R0_EL1
+ REG_ICV_AP0R1_EL1
+ REG_ICV_AP0R2_EL1
+ REG_ICV_AP0R3_EL1
+ REG_ICV_AP1R0_EL1
+ REG_ICV_AP1R1_EL1
+ REG_ICV_AP1R2_EL1
+ REG_ICV_AP1R3_EL1
+ REG_ICV_BPR0_EL1
+ REG_ICV_BPR1_EL1
+ REG_ICV_CTLR_EL1
+ REG_ICV_DIR_EL1
+ REG_ICV_EOIR0_EL1
+ REG_ICV_EOIR1_EL1
+ REG_ICV_HPPIR0_EL1
+ REG_ICV_HPPIR1_EL1
+ REG_ICV_IAR0_EL1
+ REG_ICV_IAR1_EL1
+ REG_ICV_IGRPEN0_EL1
+ REG_ICV_IGRPEN1_EL1
+ REG_ICV_PMR_EL1
+ REG_ICV_RPR_EL1
+ REG_ID_AA64AFR0_EL1
+ REG_ID_AA64AFR1_EL1
+ REG_ID_AA64DFR0_EL1
+ REG_ID_AA64DFR1_EL1
+ REG_ID_AA64ISAR0_EL1
+ REG_ID_AA64ISAR1_EL1
+ REG_ID_AA64MMFR0_EL1
+ REG_ID_AA64MMFR1_EL1
+ REG_ID_AA64MMFR2_EL1
+ REG_ID_AA64PFR0_EL1
+ REG_ID_AA64PFR1_EL1
+ REG_ID_AA64ZFR0_EL1
+ REG_ID_AFR0_EL1
+ REG_ID_DFR0_EL1
+ REG_ID_ISAR0_EL1
+ REG_ID_ISAR1_EL1
+ REG_ID_ISAR2_EL1
+ REG_ID_ISAR3_EL1
+ REG_ID_ISAR4_EL1
+ REG_ID_ISAR5_EL1
+ REG_ID_ISAR6_EL1
+ REG_ID_MMFR0_EL1
+ REG_ID_MMFR1_EL1
+ REG_ID_MMFR2_EL1
+ REG_ID_MMFR3_EL1
+ REG_ID_MMFR4_EL1
+ REG_ID_PFR0_EL1
+ REG_ID_PFR1_EL1
+ REG_ID_PFR2_EL1
+ REG_ISR_EL1
+ REG_LORC_EL1
+ REG_LOREA_EL1
+ REG_LORID_EL1
+ REG_LORN_EL1
+ REG_LORSA_EL1
+ REG_MAIR_EL1
+ REG_MDCCINT_EL1
+ REG_MDCCSR_EL0
+ REG_MDRAR_EL1
+ REG_MDSCR_EL1
+ REG_MIDR_EL1
+ REG_MPAM0_EL1
+ REG_MPAM1_EL1
+ REG_MPAMIDR_EL1
+ REG_MPIDR_EL1
+ REG_MVFR0_EL1
+ REG_MVFR1_EL1
+ REG_MVFR2_EL1
+ REG_NZCV
+ REG_OSDLR_EL1
+ REG_OSDTRRX_EL1
+ REG_OSDTRTX_EL1
+ REG_OSECCR_EL1
+ REG_OSLAR_EL1
+ REG_OSLSR_EL1
+ REG_PAN
+ REG_PAR_EL1
+ REG_PMBIDR_EL1
+ REG_PMBLIMITR_EL1
+ REG_PMBPTR_EL1
+ REG_PMBSR_EL1
+ REG_PMCCFILTR_EL0
+ REG_PMCCNTR_EL0
+ REG_PMCEID0_EL0
+ REG_PMCEID1_EL0
+ REG_PMCNTENCLR_EL0
+ REG_PMCNTENSET_EL0
+ REG_PMCR_EL0
+ REG_PMEVCNTR0_EL0
+ REG_PMEVCNTR1_EL0
+ REG_PMEVCNTR2_EL0
+ REG_PMEVCNTR3_EL0
+ REG_PMEVCNTR4_EL0
+ REG_PMEVCNTR5_EL0
+ REG_PMEVCNTR6_EL0
+ REG_PMEVCNTR7_EL0
+ REG_PMEVCNTR8_EL0
+ REG_PMEVCNTR9_EL0
+ REG_PMEVCNTR10_EL0
+ REG_PMEVCNTR11_EL0
+ REG_PMEVCNTR12_EL0
+ REG_PMEVCNTR13_EL0
+ REG_PMEVCNTR14_EL0
+ REG_PMEVCNTR15_EL0
+ REG_PMEVCNTR16_EL0
+ REG_PMEVCNTR17_EL0
+ REG_PMEVCNTR18_EL0
+ REG_PMEVCNTR19_EL0
+ REG_PMEVCNTR20_EL0
+ REG_PMEVCNTR21_EL0
+ REG_PMEVCNTR22_EL0
+ REG_PMEVCNTR23_EL0
+ REG_PMEVCNTR24_EL0
+ REG_PMEVCNTR25_EL0
+ REG_PMEVCNTR26_EL0
+ REG_PMEVCNTR27_EL0
+ REG_PMEVCNTR28_EL0
+ REG_PMEVCNTR29_EL0
+ REG_PMEVCNTR30_EL0
+ REG_PMEVTYPER0_EL0
+ REG_PMEVTYPER1_EL0
+ REG_PMEVTYPER2_EL0
+ REG_PMEVTYPER3_EL0
+ REG_PMEVTYPER4_EL0
+ REG_PMEVTYPER5_EL0
+ REG_PMEVTYPER6_EL0
+ REG_PMEVTYPER7_EL0
+ REG_PMEVTYPER8_EL0
+ REG_PMEVTYPER9_EL0
+ REG_PMEVTYPER10_EL0
+ REG_PMEVTYPER11_EL0
+ REG_PMEVTYPER12_EL0
+ REG_PMEVTYPER13_EL0
+ REG_PMEVTYPER14_EL0
+ REG_PMEVTYPER15_EL0
+ REG_PMEVTYPER16_EL0
+ REG_PMEVTYPER17_EL0
+ REG_PMEVTYPER18_EL0
+ REG_PMEVTYPER19_EL0
+ REG_PMEVTYPER20_EL0
+ REG_PMEVTYPER21_EL0
+ REG_PMEVTYPER22_EL0
+ REG_PMEVTYPER23_EL0
+ REG_PMEVTYPER24_EL0
+ REG_PMEVTYPER25_EL0
+ REG_PMEVTYPER26_EL0
+ REG_PMEVTYPER27_EL0
+ REG_PMEVTYPER28_EL0
+ REG_PMEVTYPER29_EL0
+ REG_PMEVTYPER30_EL0
+ REG_PMINTENCLR_EL1
+ REG_PMINTENSET_EL1
+ REG_PMMIR_EL1
+ REG_PMOVSCLR_EL0
+ REG_PMOVSSET_EL0
+ REG_PMSCR_EL1
+ REG_PMSELR_EL0
+ REG_PMSEVFR_EL1
+ REG_PMSFCR_EL1
+ REG_PMSICR_EL1
+ REG_PMSIDR_EL1
+ REG_PMSIRR_EL1
+ REG_PMSLATFR_EL1
+ REG_PMSWINC_EL0
+ REG_PMUSERENR_EL0
+ REG_PMXEVCNTR_EL0
+ REG_PMXEVTYPER_EL0
+ REG_REVIDR_EL1
+ REG_RGSR_EL1
+ REG_RMR_EL1
+ REG_RNDR
+ REG_RNDRRS
+ REG_RVBAR_EL1
+ REG_SCTLR_EL1
+ REG_SCXTNUM_EL0
+ REG_SCXTNUM_EL1
+ REG_SP_EL0
+ REG_SP_EL1
+ REG_SPSel
+ REG_SPSR_abt
+ REG_SPSR_EL1
+ REG_SPSR_fiq
+ REG_SPSR_irq
+ REG_SPSR_und
+ REG_SSBS
+ REG_TCO
+ REG_TCR_EL1
+ REG_TFSR_EL1
+ REG_TFSRE0_EL1
+ REG_TPIDR_EL0
+ REG_TPIDR_EL1
+ REG_TPIDRRO_EL0
+ REG_TRFCR_EL1
+ REG_TTBR0_EL1
+ REG_TTBR1_EL1
+ REG_UAO
+ REG_VBAR_EL1
+ REG_ZCR_EL1
+ AUTO_SYSREG_END
+)
+
+var SystemReg = []struct {
+ Name string
+ Reg int16
+ Enc uint32
+}{
+ {"ACTLR_EL1", REG_ACTLR_EL1, 0x181020},
+ {"AFSR0_EL1", REG_AFSR0_EL1, 0x185100},
+ {"AFSR1_EL1", REG_AFSR1_EL1, 0x185120},
+ {"AIDR_EL1", REG_AIDR_EL1, 0x1900e0},
+ {"AMAIR_EL1", REG_AMAIR_EL1, 0x18a300},
+ {"AMCFGR_EL0", REG_AMCFGR_EL0, 0x1bd220},
+ {"AMCGCR_EL0", REG_AMCGCR_EL0, 0x1bd240},
+ {"AMCNTENCLR0_EL0", REG_AMCNTENCLR0_EL0, 0x1bd280},
+ {"AMCNTENCLR1_EL0", REG_AMCNTENCLR1_EL0, 0x1bd300},
+ {"AMCNTENSET0_EL0", REG_AMCNTENSET0_EL0, 0x1bd2a0},
+ {"AMCNTENSET1_EL0", REG_AMCNTENSET1_EL0, 0x1bd320},
+ {"AMCR_EL0", REG_AMCR_EL0, 0x1bd200},
+ {"AMEVCNTR00_EL0", REG_AMEVCNTR00_EL0, 0x1bd400},
+ {"AMEVCNTR01_EL0", REG_AMEVCNTR01_EL0, 0x1bd420},
+ {"AMEVCNTR02_EL0", REG_AMEVCNTR02_EL0, 0x1bd440},
+ {"AMEVCNTR03_EL0", REG_AMEVCNTR03_EL0, 0x1bd460},
+ {"AMEVCNTR04_EL0", REG_AMEVCNTR04_EL0, 0x1bd480},
+ {"AMEVCNTR05_EL0", REG_AMEVCNTR05_EL0, 0x1bd4a0},
+ {"AMEVCNTR06_EL0", REG_AMEVCNTR06_EL0, 0x1bd4c0},
+ {"AMEVCNTR07_EL0", REG_AMEVCNTR07_EL0, 0x1bd4e0},
+ {"AMEVCNTR08_EL0", REG_AMEVCNTR08_EL0, 0x1bd500},
+ {"AMEVCNTR09_EL0", REG_AMEVCNTR09_EL0, 0x1bd520},
+ {"AMEVCNTR010_EL0", REG_AMEVCNTR010_EL0, 0x1bd540},
+ {"AMEVCNTR011_EL0", REG_AMEVCNTR011_EL0, 0x1bd560},
+ {"AMEVCNTR012_EL0", REG_AMEVCNTR012_EL0, 0x1bd580},
+ {"AMEVCNTR013_EL0", REG_AMEVCNTR013_EL0, 0x1bd5a0},
+ {"AMEVCNTR014_EL0", REG_AMEVCNTR014_EL0, 0x1bd5c0},
+ {"AMEVCNTR015_EL0", REG_AMEVCNTR015_EL0, 0x1bd5e0},
+ {"AMEVCNTR10_EL0", REG_AMEVCNTR10_EL0, 0x1bdc00},
+ {"AMEVCNTR11_EL0", REG_AMEVCNTR11_EL0, 0x1bdc20},
+ {"AMEVCNTR12_EL0", REG_AMEVCNTR12_EL0, 0x1bdc40},
+ {"AMEVCNTR13_EL0", REG_AMEVCNTR13_EL0, 0x1bdc60},
+ {"AMEVCNTR14_EL0", REG_AMEVCNTR14_EL0, 0x1bdc80},
+ {"AMEVCNTR15_EL0", REG_AMEVCNTR15_EL0, 0x1bdca0},
+ {"AMEVCNTR16_EL0", REG_AMEVCNTR16_EL0, 0x1bdcc0},
+ {"AMEVCNTR17_EL0", REG_AMEVCNTR17_EL0, 0x1bdce0},
+ {"AMEVCNTR18_EL0", REG_AMEVCNTR18_EL0, 0x1bdd00},
+ {"AMEVCNTR19_EL0", REG_AMEVCNTR19_EL0, 0x1bdd20},
+ {"AMEVCNTR110_EL0", REG_AMEVCNTR110_EL0, 0x1bdd40},
+ {"AMEVCNTR111_EL0", REG_AMEVCNTR111_EL0, 0x1bdd60},
+ {"AMEVCNTR112_EL0", REG_AMEVCNTR112_EL0, 0x1bdd80},
+ {"AMEVCNTR113_EL0", REG_AMEVCNTR113_EL0, 0x1bdda0},
+ {"AMEVCNTR114_EL0", REG_AMEVCNTR114_EL0, 0x1bddc0},
+ {"AMEVCNTR115_EL0", REG_AMEVCNTR115_EL0, 0x1bdde0},
+ {"AMEVTYPER00_EL0", REG_AMEVTYPER00_EL0, 0x1bd600},
+ {"AMEVTYPER01_EL0", REG_AMEVTYPER01_EL0, 0x1bd620},
+ {"AMEVTYPER02_EL0", REG_AMEVTYPER02_EL0, 0x1bd640},
+ {"AMEVTYPER03_EL0", REG_AMEVTYPER03_EL0, 0x1bd660},
+ {"AMEVTYPER04_EL0", REG_AMEVTYPER04_EL0, 0x1bd680},
+ {"AMEVTYPER05_EL0", REG_AMEVTYPER05_EL0, 0x1bd6a0},
+ {"AMEVTYPER06_EL0", REG_AMEVTYPER06_EL0, 0x1bd6c0},
+ {"AMEVTYPER07_EL0", REG_AMEVTYPER07_EL0, 0x1bd6e0},
+ {"AMEVTYPER08_EL0", REG_AMEVTYPER08_EL0, 0x1bd700},
+ {"AMEVTYPER09_EL0", REG_AMEVTYPER09_EL0, 0x1bd720},
+ {"AMEVTYPER010_EL0", REG_AMEVTYPER010_EL0, 0x1bd740},
+ {"AMEVTYPER011_EL0", REG_AMEVTYPER011_EL0, 0x1bd760},
+ {"AMEVTYPER012_EL0", REG_AMEVTYPER012_EL0, 0x1bd780},
+ {"AMEVTYPER013_EL0", REG_AMEVTYPER013_EL0, 0x1bd7a0},
+ {"AMEVTYPER014_EL0", REG_AMEVTYPER014_EL0, 0x1bd7c0},
+ {"AMEVTYPER015_EL0", REG_AMEVTYPER015_EL0, 0x1bd7e0},
+ {"AMEVTYPER10_EL0", REG_AMEVTYPER10_EL0, 0x1bde00},
+ {"AMEVTYPER11_EL0", REG_AMEVTYPER11_EL0, 0x1bde20},
+ {"AMEVTYPER12_EL0", REG_AMEVTYPER12_EL0, 0x1bde40},
+ {"AMEVTYPER13_EL0", REG_AMEVTYPER13_EL0, 0x1bde60},
+ {"AMEVTYPER14_EL0", REG_AMEVTYPER14_EL0, 0x1bde80},
+ {"AMEVTYPER15_EL0", REG_AMEVTYPER15_EL0, 0x1bdea0},
+ {"AMEVTYPER16_EL0", REG_AMEVTYPER16_EL0, 0x1bdec0},
+ {"AMEVTYPER17_EL0", REG_AMEVTYPER17_EL0, 0x1bdee0},
+ {"AMEVTYPER18_EL0", REG_AMEVTYPER18_EL0, 0x1bdf00},
+ {"AMEVTYPER19_EL0", REG_AMEVTYPER19_EL0, 0x1bdf20},
+ {"AMEVTYPER110_EL0", REG_AMEVTYPER110_EL0, 0x1bdf40},
+ {"AMEVTYPER111_EL0", REG_AMEVTYPER111_EL0, 0x1bdf60},
+ {"AMEVTYPER112_EL0", REG_AMEVTYPER112_EL0, 0x1bdf80},
+ {"AMEVTYPER113_EL0", REG_AMEVTYPER113_EL0, 0x1bdfa0},
+ {"AMEVTYPER114_EL0", REG_AMEVTYPER114_EL0, 0x1bdfc0},
+ {"AMEVTYPER115_EL0", REG_AMEVTYPER115_EL0, 0x1bdfe0},
+ {"AMUSERENR_EL0", REG_AMUSERENR_EL0, 0x1bd260},
+ {"APDAKeyHi_EL1", REG_APDAKeyHi_EL1, 0x182220},
+ {"APDAKeyLo_EL1", REG_APDAKeyLo_EL1, 0x182200},
+ {"APDBKeyHi_EL1", REG_APDBKeyHi_EL1, 0x182260},
+ {"APDBKeyLo_EL1", REG_APDBKeyLo_EL1, 0x182240},
+ {"APGAKeyHi_EL1", REG_APGAKeyHi_EL1, 0x182320},
+ {"APGAKeyLo_EL1", REG_APGAKeyLo_EL1, 0x182300},
+ {"APIAKeyHi_EL1", REG_APIAKeyHi_EL1, 0x182120},
+ {"APIAKeyLo_EL1", REG_APIAKeyLo_EL1, 0x182100},
+ {"APIBKeyHi_EL1", REG_APIBKeyHi_EL1, 0x182160},
+ {"APIBKeyLo_EL1", REG_APIBKeyLo_EL1, 0x182140},
+ {"CCSIDR2_EL1", REG_CCSIDR2_EL1, 0x190040},
+ {"CCSIDR_EL1", REG_CCSIDR_EL1, 0x190000},
+ {"CLIDR_EL1", REG_CLIDR_EL1, 0x190020},
+ {"CNTFRQ_EL0", REG_CNTFRQ_EL0, 0x1be000},
+ {"CNTKCTL_EL1", REG_CNTKCTL_EL1, 0x18e100},
+ {"CNTP_CTL_EL0", REG_CNTP_CTL_EL0, 0x1be220},
+ {"CNTP_CVAL_EL0", REG_CNTP_CVAL_EL0, 0x1be240},
+ {"CNTP_TVAL_EL0", REG_CNTP_TVAL_EL0, 0x1be200},
+ {"CNTPCT_EL0", REG_CNTPCT_EL0, 0x1be020},
+ {"CNTPS_CTL_EL1", REG_CNTPS_CTL_EL1, 0x1fe220},
+ {"CNTPS_CVAL_EL1", REG_CNTPS_CVAL_EL1, 0x1fe240},
+ {"CNTPS_TVAL_EL1", REG_CNTPS_TVAL_EL1, 0x1fe200},
+ {"CNTV_CTL_EL0", REG_CNTV_CTL_EL0, 0x1be320},
+ {"CNTV_CVAL_EL0", REG_CNTV_CVAL_EL0, 0x1be340},
+ {"CNTV_TVAL_EL0", REG_CNTV_TVAL_EL0, 0x1be300},
+ {"CNTVCT_EL0", REG_CNTVCT_EL0, 0x1be040},
+ {"CONTEXTIDR_EL1", REG_CONTEXTIDR_EL1, 0x18d020},
+ {"CPACR_EL1", REG_CPACR_EL1, 0x181040},
+ {"CSSELR_EL1", REG_CSSELR_EL1, 0x1a0000},
+ {"CTR_EL0", REG_CTR_EL0, 0x1b0020},
+ {"CurrentEL", REG_CurrentEL, 0x184240},
+ {"DAIF", REG_DAIF, 0x1b4220},
+ {"DBGAUTHSTATUS_EL1", REG_DBGAUTHSTATUS_EL1, 0x107ec0},
+ {"DBGBCR0_EL1", REG_DBGBCR0_EL1, 0x1000a0},
+ {"DBGBCR1_EL1", REG_DBGBCR1_EL1, 0x1001a0},
+ {"DBGBCR2_EL1", REG_DBGBCR2_EL1, 0x1002a0},
+ {"DBGBCR3_EL1", REG_DBGBCR3_EL1, 0x1003a0},
+ {"DBGBCR4_EL1", REG_DBGBCR4_EL1, 0x1004a0},
+ {"DBGBCR5_EL1", REG_DBGBCR5_EL1, 0x1005a0},
+ {"DBGBCR6_EL1", REG_DBGBCR6_EL1, 0x1006a0},
+ {"DBGBCR7_EL1", REG_DBGBCR7_EL1, 0x1007a0},
+ {"DBGBCR8_EL1", REG_DBGBCR8_EL1, 0x1008a0},
+ {"DBGBCR9_EL1", REG_DBGBCR9_EL1, 0x1009a0},
+ {"DBGBCR10_EL1", REG_DBGBCR10_EL1, 0x100aa0},
+ {"DBGBCR11_EL1", REG_DBGBCR11_EL1, 0x100ba0},
+ {"DBGBCR12_EL1", REG_DBGBCR12_EL1, 0x100ca0},
+ {"DBGBCR13_EL1", REG_DBGBCR13_EL1, 0x100da0},
+ {"DBGBCR14_EL1", REG_DBGBCR14_EL1, 0x100ea0},
+ {"DBGBCR15_EL1", REG_DBGBCR15_EL1, 0x100fa0},
+ {"DBGBVR0_EL1", REG_DBGBVR0_EL1, 0x100080},
+ {"DBGBVR1_EL1", REG_DBGBVR1_EL1, 0x100180},
+ {"DBGBVR2_EL1", REG_DBGBVR2_EL1, 0x100280},
+ {"DBGBVR3_EL1", REG_DBGBVR3_EL1, 0x100380},
+ {"DBGBVR4_EL1", REG_DBGBVR4_EL1, 0x100480},
+ {"DBGBVR5_EL1", REG_DBGBVR5_EL1, 0x100580},
+ {"DBGBVR6_EL1", REG_DBGBVR6_EL1, 0x100680},
+ {"DBGBVR7_EL1", REG_DBGBVR7_EL1, 0x100780},
+ {"DBGBVR8_EL1", REG_DBGBVR8_EL1, 0x100880},
+ {"DBGBVR9_EL1", REG_DBGBVR9_EL1, 0x100980},
+ {"DBGBVR10_EL1", REG_DBGBVR10_EL1, 0x100a80},
+ {"DBGBVR11_EL1", REG_DBGBVR11_EL1, 0x100b80},
+ {"DBGBVR12_EL1", REG_DBGBVR12_EL1, 0x100c80},
+ {"DBGBVR13_EL1", REG_DBGBVR13_EL1, 0x100d80},
+ {"DBGBVR14_EL1", REG_DBGBVR14_EL1, 0x100e80},
+ {"DBGBVR15_EL1", REG_DBGBVR15_EL1, 0x100f80},
+ {"DBGCLAIMCLR_EL1", REG_DBGCLAIMCLR_EL1, 0x1079c0},
+ {"DBGCLAIMSET_EL1", REG_DBGCLAIMSET_EL1, 0x1078c0},
+ {"DBGDTR_EL0", REG_DBGDTR_EL0, 0x130400},
+ {"DBGDTRRX_EL0", REG_DBGDTRRX_EL0, 0x130500},
+ {"DBGDTRTX_EL0", REG_DBGDTRTX_EL0, 0x130500},
+ {"DBGPRCR_EL1", REG_DBGPRCR_EL1, 0x101480},
+ {"DBGWCR0_EL1", REG_DBGWCR0_EL1, 0x1000e0},
+ {"DBGWCR1_EL1", REG_DBGWCR1_EL1, 0x1001e0},
+ {"DBGWCR2_EL1", REG_DBGWCR2_EL1, 0x1002e0},
+ {"DBGWCR3_EL1", REG_DBGWCR3_EL1, 0x1003e0},
+ {"DBGWCR4_EL1", REG_DBGWCR4_EL1, 0x1004e0},
+ {"DBGWCR5_EL1", REG_DBGWCR5_EL1, 0x1005e0},
+ {"DBGWCR6_EL1", REG_DBGWCR6_EL1, 0x1006e0},
+ {"DBGWCR7_EL1", REG_DBGWCR7_EL1, 0x1007e0},
+ {"DBGWCR8_EL1", REG_DBGWCR8_EL1, 0x1008e0},
+ {"DBGWCR9_EL1", REG_DBGWCR9_EL1, 0x1009e0},
+ {"DBGWCR10_EL1", REG_DBGWCR10_EL1, 0x100ae0},
+ {"DBGWCR11_EL1", REG_DBGWCR11_EL1, 0x100be0},
+ {"DBGWCR12_EL1", REG_DBGWCR12_EL1, 0x100ce0},
+ {"DBGWCR13_EL1", REG_DBGWCR13_EL1, 0x100de0},
+ {"DBGWCR14_EL1", REG_DBGWCR14_EL1, 0x100ee0},
+ {"DBGWCR15_EL1", REG_DBGWCR15_EL1, 0x100fe0},
+ {"DBGWVR0_EL1", REG_DBGWVR0_EL1, 0x1000c0},
+ {"DBGWVR1_EL1", REG_DBGWVR1_EL1, 0x1001c0},
+ {"DBGWVR2_EL1", REG_DBGWVR2_EL1, 0x1002c0},
+ {"DBGWVR3_EL1", REG_DBGWVR3_EL1, 0x1003c0},
+ {"DBGWVR4_EL1", REG_DBGWVR4_EL1, 0x1004c0},
+ {"DBGWVR5_EL1", REG_DBGWVR5_EL1, 0x1005c0},
+ {"DBGWVR6_EL1", REG_DBGWVR6_EL1, 0x1006c0},
+ {"DBGWVR7_EL1", REG_DBGWVR7_EL1, 0x1007c0},
+ {"DBGWVR8_EL1", REG_DBGWVR8_EL1, 0x1008c0},
+ {"DBGWVR9_EL1", REG_DBGWVR9_EL1, 0x1009c0},
+ {"DBGWVR10_EL1", REG_DBGWVR10_EL1, 0x100ac0},
+ {"DBGWVR11_EL1", REG_DBGWVR11_EL1, 0x100bc0},
+ {"DBGWVR12_EL1", REG_DBGWVR12_EL1, 0x100cc0},
+ {"DBGWVR13_EL1", REG_DBGWVR13_EL1, 0x100dc0},
+ {"DBGWVR14_EL1", REG_DBGWVR14_EL1, 0x100ec0},
+ {"DBGWVR15_EL1", REG_DBGWVR15_EL1, 0x100fc0},
+ {"DCZID_EL0", REG_DCZID_EL0, 0x1b00e0},
+ {"DISR_EL1", REG_DISR_EL1, 0x18c120},
+ {"DIT", REG_DIT, 0x1b42a0},
+ {"DLR_EL0", REG_DLR_EL0, 0x1b4520},
+ {"DSPSR_EL0", REG_DSPSR_EL0, 0x1b4500},
+ {"ELR_EL1", REG_ELR_EL1, 0x184020},
+ {"ERRIDR_EL1", REG_ERRIDR_EL1, 0x185300},
+ {"ERRSELR_EL1", REG_ERRSELR_EL1, 0x185320},
+ {"ERXADDR_EL1", REG_ERXADDR_EL1, 0x185460},
+ {"ERXCTLR_EL1", REG_ERXCTLR_EL1, 0x185420},
+ {"ERXFR_EL1", REG_ERXFR_EL1, 0x185400},
+ {"ERXMISC0_EL1", REG_ERXMISC0_EL1, 0x185500},
+ {"ERXMISC1_EL1", REG_ERXMISC1_EL1, 0x185520},
+ {"ERXMISC2_EL1", REG_ERXMISC2_EL1, 0x185540},
+ {"ERXMISC3_EL1", REG_ERXMISC3_EL1, 0x185560},
+ {"ERXPFGCDN_EL1", REG_ERXPFGCDN_EL1, 0x1854c0},
+ {"ERXPFGCTL_EL1", REG_ERXPFGCTL_EL1, 0x1854a0},
+ {"ERXPFGF_EL1", REG_ERXPFGF_EL1, 0x185480},
+ {"ERXSTATUS_EL1", REG_ERXSTATUS_EL1, 0x185440},
+ {"ESR_EL1", REG_ESR_EL1, 0x185200},
+ {"FAR_EL1", REG_FAR_EL1, 0x186000},
+ {"FPCR", REG_FPCR, 0x1b4400},
+ {"FPSR", REG_FPSR, 0x1b4420},
+ {"GCR_EL1", REG_GCR_EL1, 0x1810c0},
+ {"GMID_EL1", REG_GMID_EL1, 0x31400},
+ {"ICC_AP0R0_EL1", REG_ICC_AP0R0_EL1, 0x18c880},
+ {"ICC_AP0R1_EL1", REG_ICC_AP0R1_EL1, 0x18c8a0},
+ {"ICC_AP0R2_EL1", REG_ICC_AP0R2_EL1, 0x18c8c0},
+ {"ICC_AP0R3_EL1", REG_ICC_AP0R3_EL1, 0x18c8e0},
+ {"ICC_AP1R0_EL1", REG_ICC_AP1R0_EL1, 0x18c900},
+ {"ICC_AP1R1_EL1", REG_ICC_AP1R1_EL1, 0x18c920},
+ {"ICC_AP1R2_EL1", REG_ICC_AP1R2_EL1, 0x18c940},
+ {"ICC_AP1R3_EL1", REG_ICC_AP1R3_EL1, 0x18c960},
+ {"ICC_ASGI1R_EL1", REG_ICC_ASGI1R_EL1, 0x18cbc0},
+ {"ICC_BPR0_EL1", REG_ICC_BPR0_EL1, 0x18c860},
+ {"ICC_BPR1_EL1", REG_ICC_BPR1_EL1, 0x18cc60},
+ {"ICC_CTLR_EL1", REG_ICC_CTLR_EL1, 0x18cc80},
+ {"ICC_DIR_EL1", REG_ICC_DIR_EL1, 0x18cb20},
+ {"ICC_EOIR0_EL1", REG_ICC_EOIR0_EL1, 0x18c820},
+ {"ICC_EOIR1_EL1", REG_ICC_EOIR1_EL1, 0x18cc20},
+ {"ICC_HPPIR0_EL1", REG_ICC_HPPIR0_EL1, 0x18c840},
+ {"ICC_HPPIR1_EL1", REG_ICC_HPPIR1_EL1, 0x18cc40},
+ {"ICC_IAR0_EL1", REG_ICC_IAR0_EL1, 0x18c800},
+ {"ICC_IAR1_EL1", REG_ICC_IAR1_EL1, 0x18cc00},
+ {"ICC_IGRPEN0_EL1", REG_ICC_IGRPEN0_EL1, 0x18ccc0},
+ {"ICC_IGRPEN1_EL1", REG_ICC_IGRPEN1_EL1, 0x18cce0},
+ {"ICC_PMR_EL1", REG_ICC_PMR_EL1, 0x184600},
+ {"ICC_RPR_EL1", REG_ICC_RPR_EL1, 0x18cb60},
+ {"ICC_SGI0R_EL1", REG_ICC_SGI0R_EL1, 0x18cbe0},
+ {"ICC_SGI1R_EL1", REG_ICC_SGI1R_EL1, 0x18cba0},
+ {"ICC_SRE_EL1", REG_ICC_SRE_EL1, 0x18cca0},
+ {"ICV_AP0R0_EL1", REG_ICV_AP0R0_EL1, 0x18c880},
+ {"ICV_AP0R1_EL1", REG_ICV_AP0R1_EL1, 0x18c8a0},
+ {"ICV_AP0R2_EL1", REG_ICV_AP0R2_EL1, 0x18c8c0},
+ {"ICV_AP0R3_EL1", REG_ICV_AP0R3_EL1, 0x18c8e0},
+ {"ICV_AP1R0_EL1", REG_ICV_AP1R0_EL1, 0x18c900},
+ {"ICV_AP1R1_EL1", REG_ICV_AP1R1_EL1, 0x18c920},
+ {"ICV_AP1R2_EL1", REG_ICV_AP1R2_EL1, 0x18c940},
+ {"ICV_AP1R3_EL1", REG_ICV_AP1R3_EL1, 0x18c960},
+ {"ICV_BPR0_EL1", REG_ICV_BPR0_EL1, 0x18c860},
+ {"ICV_BPR1_EL1", REG_ICV_BPR1_EL1, 0x18cc60},
+ {"ICV_CTLR_EL1", REG_ICV_CTLR_EL1, 0x18cc80},
+ {"ICV_DIR_EL1", REG_ICV_DIR_EL1, 0x18cb20},
+ {"ICV_EOIR0_EL1", REG_ICV_EOIR0_EL1, 0x18c820},
+ {"ICV_EOIR1_EL1", REG_ICV_EOIR1_EL1, 0x18cc20},
+ {"ICV_HPPIR0_EL1", REG_ICV_HPPIR0_EL1, 0x18c840},
+ {"ICV_HPPIR1_EL1", REG_ICV_HPPIR1_EL1, 0x18cc40},
+ {"ICV_IAR0_EL1", REG_ICV_IAR0_EL1, 0x18c800},
+ {"ICV_IAR1_EL1", REG_ICV_IAR1_EL1, 0x18cc00},
+ {"ICV_IGRPEN0_EL1", REG_ICV_IGRPEN0_EL1, 0x18ccc0},
+ {"ICV_IGRPEN1_EL1", REG_ICV_IGRPEN1_EL1, 0x18cce0},
+ {"ICV_PMR_EL1", REG_ICV_PMR_EL1, 0x184600},
+ {"ICV_RPR_EL1", REG_ICV_RPR_EL1, 0x18cb60},
+ {"ID_AA64AFR0_EL1", REG_ID_AA64AFR0_EL1, 0x180580},
+ {"ID_AA64AFR1_EL1", REG_ID_AA64AFR1_EL1, 0x1805a0},
+ {"ID_AA64DFR0_EL1", REG_ID_AA64DFR0_EL1, 0x180500},
+ {"ID_AA64DFR1_EL1", REG_ID_AA64DFR1_EL1, 0x180520},
+ {"ID_AA64ISAR0_EL1", REG_ID_AA64ISAR0_EL1, 0x180600},
+ {"ID_AA64ISAR1_EL1", REG_ID_AA64ISAR1_EL1, 0x180620},
+ {"ID_AA64MMFR0_EL1", REG_ID_AA64MMFR0_EL1, 0x180700},
+ {"ID_AA64MMFR1_EL1", REG_ID_AA64MMFR1_EL1, 0x180720},
+ {"ID_AA64MMFR2_EL1", REG_ID_AA64MMFR2_EL1, 0x180740},
+ {"ID_AA64PFR0_EL1", REG_ID_AA64PFR0_EL1, 0x180400},
+ {"ID_AA64PFR1_EL1", REG_ID_AA64PFR1_EL1, 0x180420},
+ {"ID_AA64ZFR0_EL1", REG_ID_AA64ZFR0_EL1, 0x180480},
+ {"ID_AFR0_EL1", REG_ID_AFR0_EL1, 0x180160},
+ {"ID_DFR0_EL1", REG_ID_DFR0_EL1, 0x180140},
+ {"ID_ISAR0_EL1", REG_ID_ISAR0_EL1, 0x180200},
+ {"ID_ISAR1_EL1", REG_ID_ISAR1_EL1, 0x180220},
+ {"ID_ISAR2_EL1", REG_ID_ISAR2_EL1, 0x180240},
+ {"ID_ISAR3_EL1", REG_ID_ISAR3_EL1, 0x180260},
+ {"ID_ISAR4_EL1", REG_ID_ISAR4_EL1, 0x180280},
+ {"ID_ISAR5_EL1", REG_ID_ISAR5_EL1, 0x1802a0},
+ {"ID_ISAR6_EL1", REG_ID_ISAR6_EL1, 0x1802e0},
+ {"ID_MMFR0_EL1", REG_ID_MMFR0_EL1, 0x180180},
+ {"ID_MMFR1_EL1", REG_ID_MMFR1_EL1, 0x1801a0},
+ {"ID_MMFR2_EL1", REG_ID_MMFR2_EL1, 0x1801c0},
+ {"ID_MMFR3_EL1", REG_ID_MMFR3_EL1, 0x1801e0},
+ {"ID_MMFR4_EL1", REG_ID_MMFR4_EL1, 0x1802c0},
+ {"ID_PFR0_EL1", REG_ID_PFR0_EL1, 0x180100},
+ {"ID_PFR1_EL1", REG_ID_PFR1_EL1, 0x180120},
+ {"ID_PFR2_EL1", REG_ID_PFR2_EL1, 0x180380},
+ {"ISR_EL1", REG_ISR_EL1, 0x18c100},
+ {"LORC_EL1", REG_LORC_EL1, 0x18a460},
+ {"LOREA_EL1", REG_LOREA_EL1, 0x18a420},
+ {"LORID_EL1", REG_LORID_EL1, 0x18a4e0},
+ {"LORN_EL1", REG_LORN_EL1, 0x18a440},
+ {"LORSA_EL1", REG_LORSA_EL1, 0x18a400},
+ {"MAIR_EL1", REG_MAIR_EL1, 0x18a200},
+ {"MDCCINT_EL1", REG_MDCCINT_EL1, 0x100200},
+ {"MDCCSR_EL0", REG_MDCCSR_EL0, 0x130100},
+ {"MDRAR_EL1", REG_MDRAR_EL1, 0x101000},
+ {"MDSCR_EL1", REG_MDSCR_EL1, 0x100240},
+ {"MIDR_EL1", REG_MIDR_EL1, 0x180000},
+ {"MPAM0_EL1", REG_MPAM0_EL1, 0x18a520},
+ {"MPAM1_EL1", REG_MPAM1_EL1, 0x18a500},
+ {"MPAMIDR_EL1", REG_MPAMIDR_EL1, 0x18a480},
+ {"MPIDR_EL1", REG_MPIDR_EL1, 0x1800a0},
+ {"MVFR0_EL1", REG_MVFR0_EL1, 0x180300},
+ {"MVFR1_EL1", REG_MVFR1_EL1, 0x180320},
+ {"MVFR2_EL1", REG_MVFR2_EL1, 0x180340},
+ {"NZCV", REG_NZCV, 0x1b4200},
+ {"OSDLR_EL1", REG_OSDLR_EL1, 0x101380},
+ {"OSDTRRX_EL1", REG_OSDTRRX_EL1, 0x100040},
+ {"OSDTRTX_EL1", REG_OSDTRTX_EL1, 0x100340},
+ {"OSECCR_EL1", REG_OSECCR_EL1, 0x100640},
+ {"OSLAR_EL1", REG_OSLAR_EL1, 0x101080},
+ {"OSLSR_EL1", REG_OSLSR_EL1, 0x101180},
+ {"PAN", REG_PAN, 0x184260},
+ {"PAR_EL1", REG_PAR_EL1, 0x187400},
+ {"PMBIDR_EL1", REG_PMBIDR_EL1, 0x189ae0},
+ {"PMBLIMITR_EL1", REG_PMBLIMITR_EL1, 0x189a00},
+ {"PMBPTR_EL1", REG_PMBPTR_EL1, 0x189a20},
+ {"PMBSR_EL1", REG_PMBSR_EL1, 0x189a60},
+ {"PMCCFILTR_EL0", REG_PMCCFILTR_EL0, 0x1befe0},
+ {"PMCCNTR_EL0", REG_PMCCNTR_EL0, 0x1b9d00},
+ {"PMCEID0_EL0", REG_PMCEID0_EL0, 0x1b9cc0},
+ {"PMCEID1_EL0", REG_PMCEID1_EL0, 0x1b9ce0},
+ {"PMCNTENCLR_EL0", REG_PMCNTENCLR_EL0, 0x1b9c40},
+ {"PMCNTENSET_EL0", REG_PMCNTENSET_EL0, 0x1b9c20},
+ {"PMCR_EL0", REG_PMCR_EL0, 0x1b9c00},
+ {"PMEVCNTR0_EL0", REG_PMEVCNTR0_EL0, 0x1be800},
+ {"PMEVCNTR1_EL0", REG_PMEVCNTR1_EL0, 0x1be820},
+ {"PMEVCNTR2_EL0", REG_PMEVCNTR2_EL0, 0x1be840},
+ {"PMEVCNTR3_EL0", REG_PMEVCNTR3_EL0, 0x1be860},
+ {"PMEVCNTR4_EL0", REG_PMEVCNTR4_EL0, 0x1be880},
+ {"PMEVCNTR5_EL0", REG_PMEVCNTR5_EL0, 0x1be8a0},
+ {"PMEVCNTR6_EL0", REG_PMEVCNTR6_EL0, 0x1be8c0},
+ {"PMEVCNTR7_EL0", REG_PMEVCNTR7_EL0, 0x1be8e0},
+ {"PMEVCNTR8_EL0", REG_PMEVCNTR8_EL0, 0x1be900},
+ {"PMEVCNTR9_EL0", REG_PMEVCNTR9_EL0, 0x1be920},
+ {"PMEVCNTR10_EL0", REG_PMEVCNTR10_EL0, 0x1be940},
+ {"PMEVCNTR11_EL0", REG_PMEVCNTR11_EL0, 0x1be960},
+ {"PMEVCNTR12_EL0", REG_PMEVCNTR12_EL0, 0x1be980},
+ {"PMEVCNTR13_EL0", REG_PMEVCNTR13_EL0, 0x1be9a0},
+ {"PMEVCNTR14_EL0", REG_PMEVCNTR14_EL0, 0x1be9c0},
+ {"PMEVCNTR15_EL0", REG_PMEVCNTR15_EL0, 0x1be9e0},
+ {"PMEVCNTR16_EL0", REG_PMEVCNTR16_EL0, 0x1bea00},
+ {"PMEVCNTR17_EL0", REG_PMEVCNTR17_EL0, 0x1bea20},
+ {"PMEVCNTR18_EL0", REG_PMEVCNTR18_EL0, 0x1bea40},
+ {"PMEVCNTR19_EL0", REG_PMEVCNTR19_EL0, 0x1bea60},
+ {"PMEVCNTR20_EL0", REG_PMEVCNTR20_EL0, 0x1bea80},
+ {"PMEVCNTR21_EL0", REG_PMEVCNTR21_EL0, 0x1beaa0},
+ {"PMEVCNTR22_EL0", REG_PMEVCNTR22_EL0, 0x1beac0},
+ {"PMEVCNTR23_EL0", REG_PMEVCNTR23_EL0, 0x1beae0},
+ {"PMEVCNTR24_EL0", REG_PMEVCNTR24_EL0, 0x1beb00},
+ {"PMEVCNTR25_EL0", REG_PMEVCNTR25_EL0, 0x1beb20},
+ {"PMEVCNTR26_EL0", REG_PMEVCNTR26_EL0, 0x1beb40},
+ {"PMEVCNTR27_EL0", REG_PMEVCNTR27_EL0, 0x1beb60},
+ {"PMEVCNTR28_EL0", REG_PMEVCNTR28_EL0, 0x1beb80},
+ {"PMEVCNTR29_EL0", REG_PMEVCNTR29_EL0, 0x1beba0},
+ {"PMEVCNTR30_EL0", REG_PMEVCNTR30_EL0, 0x1bebc0},
+ {"PMEVTYPER0_EL0", REG_PMEVTYPER0_EL0, 0x1bec00},
+ {"PMEVTYPER1_EL0", REG_PMEVTYPER1_EL0, 0x1bec20},
+ {"PMEVTYPER2_EL0", REG_PMEVTYPER2_EL0, 0x1bec40},
+ {"PMEVTYPER3_EL0", REG_PMEVTYPER3_EL0, 0x1bec60},
+ {"PMEVTYPER4_EL0", REG_PMEVTYPER4_EL0, 0x1bec80},
+ {"PMEVTYPER5_EL0", REG_PMEVTYPER5_EL0, 0x1beca0},
+ {"PMEVTYPER6_EL0", REG_PMEVTYPER6_EL0, 0x1becc0},
+ {"PMEVTYPER7_EL0", REG_PMEVTYPER7_EL0, 0x1bece0},
+ {"PMEVTYPER8_EL0", REG_PMEVTYPER8_EL0, 0x1bed00},
+ {"PMEVTYPER9_EL0", REG_PMEVTYPER9_EL0, 0x1bed20},
+ {"PMEVTYPER10_EL0", REG_PMEVTYPER10_EL0, 0x1bed40},
+ {"PMEVTYPER11_EL0", REG_PMEVTYPER11_EL0, 0x1bed60},
+ {"PMEVTYPER12_EL0", REG_PMEVTYPER12_EL0, 0x1bed80},
+ {"PMEVTYPER13_EL0", REG_PMEVTYPER13_EL0, 0x1beda0},
+ {"PMEVTYPER14_EL0", REG_PMEVTYPER14_EL0, 0x1bedc0},
+ {"PMEVTYPER15_EL0", REG_PMEVTYPER15_EL0, 0x1bede0},
+ {"PMEVTYPER16_EL0", REG_PMEVTYPER16_EL0, 0x1bee00},
+ {"PMEVTYPER17_EL0", REG_PMEVTYPER17_EL0, 0x1bee20},
+ {"PMEVTYPER18_EL0", REG_PMEVTYPER18_EL0, 0x1bee40},
+ {"PMEVTYPER19_EL0", REG_PMEVTYPER19_EL0, 0x1bee60},
+ {"PMEVTYPER20_EL0", REG_PMEVTYPER20_EL0, 0x1bee80},
+ {"PMEVTYPER21_EL0", REG_PMEVTYPER21_EL0, 0x1beea0},
+ {"PMEVTYPER22_EL0", REG_PMEVTYPER22_EL0, 0x1beec0},
+ {"PMEVTYPER23_EL0", REG_PMEVTYPER23_EL0, 0x1beee0},
+ {"PMEVTYPER24_EL0", REG_PMEVTYPER24_EL0, 0x1bef00},
+ {"PMEVTYPER25_EL0", REG_PMEVTYPER25_EL0, 0x1bef20},
+ {"PMEVTYPER26_EL0", REG_PMEVTYPER26_EL0, 0x1bef40},
+ {"PMEVTYPER27_EL0", REG_PMEVTYPER27_EL0, 0x1bef60},
+ {"PMEVTYPER28_EL0", REG_PMEVTYPER28_EL0, 0x1bef80},
+ {"PMEVTYPER29_EL0", REG_PMEVTYPER29_EL0, 0x1befa0},
+ {"PMEVTYPER30_EL0", REG_PMEVTYPER30_EL0, 0x1befc0},
+ {"PMINTENCLR_EL1", REG_PMINTENCLR_EL1, 0x189e40},
+ {"PMINTENSET_EL1", REG_PMINTENSET_EL1, 0x189e20},
+ {"PMMIR_EL1", REG_PMMIR_EL1, 0x189ec0},
+ {"PMOVSCLR_EL0", REG_PMOVSCLR_EL0, 0x1b9c60},
+ {"PMOVSSET_EL0", REG_PMOVSSET_EL0, 0x1b9e60},
+ {"PMSCR_EL1", REG_PMSCR_EL1, 0x189900},
+ {"PMSELR_EL0", REG_PMSELR_EL0, 0x1b9ca0},
+ {"PMSEVFR_EL1", REG_PMSEVFR_EL1, 0x1899a0},
+ {"PMSFCR_EL1", REG_PMSFCR_EL1, 0x189980},
+ {"PMSICR_EL1", REG_PMSICR_EL1, 0x189940},
+ {"PMSIDR_EL1", REG_PMSIDR_EL1, 0x1899e0},
+ {"PMSIRR_EL1", REG_PMSIRR_EL1, 0x189960},
+ {"PMSLATFR_EL1", REG_PMSLATFR_EL1, 0x1899c0},
+ {"PMSWINC_EL0", REG_PMSWINC_EL0, 0x1b9c80},
+ {"PMUSERENR_EL0", REG_PMUSERENR_EL0, 0x1b9e00},
+ {"PMXEVCNTR_EL0", REG_PMXEVCNTR_EL0, 0x1b9d40},
+ {"PMXEVTYPER_EL0", REG_PMXEVTYPER_EL0, 0x1b9d20},
+ {"REVIDR_EL1", REG_REVIDR_EL1, 0x1800c0},
+ {"RGSR_EL1", REG_RGSR_EL1, 0x1810a0},
+ {"RMR_EL1", REG_RMR_EL1, 0x18c040},
+ {"RNDR", REG_RNDR, 0x1b2400},
+ {"RNDRRS", REG_RNDRRS, 0x1b2420},
+ {"RVBAR_EL1", REG_RVBAR_EL1, 0x18c020},
+ {"SCTLR_EL1", REG_SCTLR_EL1, 0x181000},
+ {"SCXTNUM_EL0", REG_SCXTNUM_EL0, 0x1bd0e0},
+ {"SCXTNUM_EL1", REG_SCXTNUM_EL1, 0x18d0e0},
+ {"SP_EL0", REG_SP_EL0, 0x184100},
+ {"SP_EL1", REG_SP_EL1, 0x1c4100},
+ {"SPSel", REG_SPSel, 0x184200},
+ {"SPSR_abt", REG_SPSR_abt, 0x1c4320},
+ {"SPSR_EL1", REG_SPSR_EL1, 0x184000},
+ {"SPSR_fiq", REG_SPSR_fiq, 0x1c4360},
+ {"SPSR_irq", REG_SPSR_irq, 0x1c4300},
+ {"SPSR_und", REG_SPSR_und, 0x1c4340},
+ {"SSBS", REG_SSBS, 0x1b42c0},
+ {"TCO", REG_TCO, 0x1b42e0},
+ {"TCR_EL1", REG_TCR_EL1, 0x182040},
+ {"TFSR_EL1", REG_TFSR_EL1, 0x185600},
+ {"TFSRE0_EL1", REG_TFSRE0_EL1, 0x185620},
+ {"TPIDR_EL0", REG_TPIDR_EL0, 0x1bd040},
+ {"TPIDR_EL1", REG_TPIDR_EL1, 0x18d080},
+ {"TPIDRRO_EL0", REG_TPIDRRO_EL0, 0x1bd060},
+ {"TRFCR_EL1", REG_TRFCR_EL1, 0x181220},
+ {"TTBR0_EL1", REG_TTBR0_EL1, 0x182000},
+ {"TTBR1_EL1", REG_TTBR1_EL1, 0x182020},
+ {"UAO", REG_UAO, 0x184280},
+ {"VBAR_EL1", REG_VBAR_EL1, 0x18c000},
+ {"ZCR_EL1", REG_ZCR_EL1, 0x181200},
+}
+
+func SysRegEnc(r int16) (string, uint32) {
+ // The automatic generator guarantees that the order
+ // of Reg in SystemReg struct is consistent with the
+ // order of system register declarations
+ if r <= AUTO_SYSREG_BEGIN || r >= AUTO_SYSREG_END {
+ return "", 0
+ }
+ v := SystemReg[r-AUTO_SYSREG_BEGIN-1]
+ return v.Name, v.Enc
+}
