diff --git a/src/cmd/internal/gc/gen.go b/src/cmd/internal/gc/gen.go
index fde0a19..e95ddeb 100644
--- a/src/cmd/internal/gc/gen.go
+++ b/src/cmd/internal/gc/gen.go
@@ -1183,12 +1183,18 @@
 		}
 	} else {
 		// When zeroing, prepare a register containing zero.
-		var tmp Node
-		Nodconst(&tmp, nl.Type, 0)
+		if Thearch.REGZERO != 0 {
+			// cpu has a dedicated zero register
+			Nodreg(&nodr, Types[TUINT], Thearch.REGZERO)
+		} else {
+			// no dedicated zero register
+			var tmp Node
+			Nodconst(&tmp, nl.Type, 0)
 
-		Regalloc(&nodr, Types[TUINT], nil)
-		Thearch.Gmove(&tmp, &nodr)
-		defer Regfree(&nodr)
+			Regalloc(&nodr, Types[TUINT], nil)
+			Thearch.Gmove(&tmp, &nodr)
+			defer Regfree(&nodr)
+		}
 	}
 
 	// nl and nr are 'cadable' which basically means they are names (variables) now.
diff --git a/src/cmd/internal/gc/go.go b/src/cmd/internal/gc/go.go
index 5803f39..25ada55 100644
--- a/src/cmd/internal/gc/go.go
+++ b/src/cmd/internal/gc/go.go
@@ -769,6 +769,7 @@
 	REGRETURN    int // AX
 	REGMIN       int
 	REGMAX       int
+	REGZERO      int // architectural zero register, if available
 	FREGMIN      int
 	FREGMAX      int
 	MAXWIDTH     int64