cmd/asm,cmd/internal/obj/ppc64: add {l,st}xvx power9 instructions
These are the indexed vsx load operations with the
same endian and alignment benefits of {l,st}vx.
Likewise, cleanup redundant comments in op{load,store}x and
fix ISA 3.0 typos nearby.
Change-Id: Ie1ace17c6150cf9168a834e435114028ff6eb07c
Reviewed-on: https://go-review.googlesource.com/c/go/+/249025
Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s
index b3736bf..ba64d84 100644
--- a/src/cmd/asm/internal/asm/testdata/ppc64.s
+++ b/src/cmd/asm/internal/asm/testdata/ppc64.s
@@ -1037,6 +1037,7 @@
// VSX load with length X-form (also left-justified)
LXVL R3,R4, VS0
LXVLL R3,R4, VS0
+ LXVX R3,R4, VS0
// VSX load, DQ-form
// <MNEMONIC> DQ(RA), XS produces
// <mnemonic> XS, DQ(RA)
@@ -1060,6 +1061,7 @@
// VSX store with length, X-form (also left-justified)
STXVL VS0, R3,R4
STXVLL VS0, R3,R4
+ STXVX VS0, R3,R4
// VSX move from VSR, XX1-form
// <MNEMONIC> XS,RA produces
diff --git a/src/cmd/asm/internal/asm/testdata/ppc64enc.s b/src/cmd/asm/internal/asm/testdata/ppc64enc.s
index 07a8a54..10a05ec 100644
--- a/src/cmd/asm/internal/asm/testdata/ppc64enc.s
+++ b/src/cmd/asm/internal/asm/testdata/ppc64enc.s
@@ -595,11 +595,13 @@
LXV 16(R3), VS1 // f4230011
LXVL R3, R4, VS1 // 7c23221a
LXVLL R3, R4, VS1 // 7c23225a
+ LXVX R3, R4, VS1 // 7c232218
LXSDX (R3)(R4), VS1 // 7c241c98
STXVD2X VS1, (R3)(R4) // 7c241f98
STXV VS1,16(R3) // f4230015
STXVL VS1, R3, R4 // 7c23231a
STXVLL VS1, R3, R4 // 7c23235a
+ STXVX VS1, R3, R4 // 7c232318
STXSDX VS1, (R3)(R4) // 7c241d98
LXSIWAX (R3)(R4), VS1 // 7c241898
STXSIWX VS1, (R3)(R4) // 7c241918
diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go
index 238ca8f..3c82477 100644
--- a/src/cmd/internal/obj/ppc64/asm9.go
+++ b/src/cmd/internal/obj/ppc64/asm9.go
@@ -1584,8 +1584,9 @@
case ALXV: /* lxv */
opset(ALXV, r0)
- case ALXVL: /* lxvl */
+ case ALXVL: /* lxvl, lxvll, lxvx */
opset(ALXVLL, r0)
+ opset(ALXVX, r0)
case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */
opset(ASTXVW4X, r0)
@@ -1595,8 +1596,9 @@
case ASTXV: /* stxv */
opset(ASTXV, r0)
- case ASTXVL: /* stxvl, stxvll */
+ case ASTXVL: /* stxvl, stxvll, stvx */
opset(ASTXVLL, r0)
+ opset(ASTXVX, r0)
case ALXSDX: /* lxsdx */
opset(ALXSDX, r0)
@@ -5020,11 +5022,13 @@
case AMOVW:
return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */
case ALXV:
- return OPDQ(61, 1, 0) /* lxv - ISA v3.00 */
+ return OPDQ(61, 1, 0) /* lxv - ISA v3.0 */
case ALXVL:
- return OPVXX1(31, 269, 0) /* lxvl - ISA v3.00 */
+ return OPVXX1(31, 269, 0) /* lxvl - ISA v3.0 */
case ALXVLL:
- return OPVXX1(31, 301, 0) /* lxvll - ISA v3.00 */
+ return OPVXX1(31, 301, 0) /* lxvll - ISA v3.0 */
+ case ALXVX:
+ return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
/* no AMOVWU */
case AMOVB, AMOVBZ:
@@ -5122,8 +5126,6 @@
return OPVCC(31, 309, 0, 0) /* ldmx */
/* Vector (VMX/Altivec) instructions */
- /* ISA 2.03 enables these for PPC970. For POWERx processors, these */
- /* are enabled starting at POWER6 (ISA 2.05). */
case ALVEBX:
return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */
case ALVEHX:
@@ -5141,7 +5143,8 @@
/* End of vector instructions */
/* Vector scalar (VSX) instructions */
- /* ISA 2.06 enables these for POWER7. */
+ case ALXVX:
+ return OPVXX1(31, 268, 0) /* lxvx - ISA v3.0 */
case ALXVD2X:
return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */
case ALXVW4X:
@@ -5208,6 +5211,8 @@
return OPVXX1(31, 397, 0) /* stxvl ISA 3.0 */
case ASTXVLL:
return OPVXX1(31, 429, 0) /* stxvll ISA 3.0 */
+ case ASTXVX:
+ return OPVXX1(31, 396, 0) /* stxvx - ISA v3.0 */
}
@@ -5271,8 +5276,6 @@
return OPVCC(31, 181, 0, 0) /* stdux */
/* Vector (VMX/Altivec) instructions */
- /* ISA 2.03 enables these for PPC970. For POWERx processors, these */
- /* are enabled starting at POWER6 (ISA 2.05). */
case ASTVEBX:
return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */
case ASTVEHX:
@@ -5286,15 +5289,16 @@
/* End of vector instructions */
/* Vector scalar (VSX) instructions */
- /* ISA 2.06 enables these for POWER7. */
+ case ASTXVX:
+ return OPVXX1(31, 396, 0) /* stxvx - v3.0 */
case ASTXVD2X:
return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */
case ASTXVW4X:
return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */
case ASTXVH8X:
- return OPVXX1(31, 940, 0) /* stxvh8x - v3.00 */
+ return OPVXX1(31, 940, 0) /* stxvh8x - v3.0 */
case ASTXVB16X:
- return OPVXX1(31, 1004, 0) /* stxvb16x - v3.00 */
+ return OPVXX1(31, 1004, 0) /* stxvb16x - v3.0 */
case ASTXSDX:
return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */
