commit 5ed90cbbb0f6d47d824b3baadb7d22c4528b7dd3
author Josh Bleecher Snyder <josharian@gmail.com> Mon Apr 13 10:28:57 2015 -0700
committer Josh Bleecher Snyder <josharian@gmail.com> Wed Apr 15 19:02:10 2015 +0000
tree 670a30941777dfd703845940aaec735d1cf4e574
parent ab4df700b841fcd9a5d249b77c547bad9574d948

cmd/internal/gc, cmd/gc: move Reg from Val to Node

Val is used to hold constant values.
Reg was the odd duck out.

Generated using eg.

No functional changes. Passes toolstash -cmp.

Change-Id: Ic1de769a1f92bb02e09a4428d998b716f307e2f6
Reviewed-on: https://go-review.googlesource.com/8912
Reviewed-by: Russ Cox <rsc@golang.org>

src/cmd/internal/gc/gsubr.go

diff --git a/src/cmd/internal/gc/gsubr.go b/src/cmd/internal/gc/gsubr.go
index 36a4a95..4483d4e 100644
--- a/src/cmd/internal/gc/gsubr.go
+++ b/src/cmd/internal/gc/gsubr.go
@@ -75,7 +75,7 @@
 	if b.Op != OREGISTER {
 		return false
 	}
-	if a.Val.U.Reg != b.Val.U.Reg {
+	if a.Reg != b.Reg {
 		return false
 	}
 	return true
@@ -135,7 +135,7 @@
 	n.Op = OREGISTER
 	n.Addable = true
 	ullmancalc(n)
-	n.Val.U.Reg = int16(r)
+	n.Reg = int16(r)
 	n.Type = t
 }
 
@@ -304,7 +304,7 @@
 
 	case OREGISTER:
 		a.Type = obj.TYPE_REG
-		a.Reg = n.Val.U.Reg
+		a.Reg = n.Reg
 		a.Sym = nil
 		if Thearch.Thechar == '8' { // TODO(rsc): Never clear a->width.
 			a.Width = 0
@@ -312,7 +312,7 @@
 
 	case OINDREG:
 		a.Type = obj.TYPE_MEM
-		a.Reg = n.Val.U.Reg
+		a.Reg = n.Reg
 		a.Sym = Linksym(n.Sym)
 		a.Offset = n.Xoffset
 		if a.Offset != int64(int32(a.Offset)) {
@@ -561,7 +561,7 @@
 	case 0: // output arg
 		n.Op = OINDREG
 
-		n.Val.U.Reg = int16(Thearch.REGSP)
+		n.Reg = int16(Thearch.REGSP)
 		if HasLinkRegister() {
 			n.Xoffset += int64(Ctxt.Arch.Ptrsize)
 		}
@@ -673,7 +673,7 @@
 
 	case TINT8, TUINT8, TINT16, TUINT16, TINT32, TUINT32, TINT64, TUINT64, TPTR32, TPTR64, TBOOL:
 		if o != nil && o.Op == OREGISTER {
-			i = int(o.Val.U.Reg)
+			i = int(o.Reg)
 			if Thearch.REGMIN <= i && i <= Thearch.REGMAX {
 				break Switch
 			}
@@ -693,7 +693,7 @@
 			break Switch
 		}
 		if o != nil && o.Op == OREGISTER {
-			i = int(o.Val.U.Reg)
+			i = int(o.Reg)
 			if Thearch.FREGMIN <= i && i <= Thearch.FREGMAX {
 				break Switch
 			}
@@ -732,7 +732,7 @@
 	if n.Op != OREGISTER && n.Op != OINDREG {
 		Fatal("regfree: not a register")
 	}
-	i := int(n.Val.U.Reg)
+	i := int(n.Reg)
 	if i == Thearch.REGSP {
 		return
 	}
@@ -773,7 +773,7 @@
 	if n.Op != OREGISTER && n.Op != OINDREG {
 		Fatal("regrealloc: not a register")
 	}
-	i := int(n.Val.U.Reg)
+	i := int(n.Reg)
 	if i == Thearch.REGSP {
 		return
 	}