[dev.ssa] cmd/compile/internal/ssa: implement OMOD
Change-Id: Iec954c4daefef4ab3fa2c98bfb2c70b2dea8dffb
Reviewed-on: https://go-review.googlesource.com/13743
Reviewed-by: Keith Randall <khr@golang.org>
diff --git a/src/cmd/compile/internal/ssa/gen/AMD64.rules b/src/cmd/compile/internal/ssa/gen/AMD64.rules
index 919336e..582528801 100644
--- a/src/cmd/compile/internal/ssa/gen/AMD64.rules
+++ b/src/cmd/compile/internal/ssa/gen/AMD64.rules
@@ -52,6 +52,15 @@
(Hmul8 x y) -> (HMULB x y)
(Hmul8u x y) -> (HMULBU x y)
+(Mod64 x y) -> (MODQ x y)
+(Mod64u x y) -> (MODQU x y)
+(Mod32 x y) -> (MODL x y)
+(Mod32u x y) -> (MODLU x y)
+(Mod16 x y) -> (MODW x y)
+(Mod16u x y) -> (MODWU x y)
+(Mod8 x y) -> (MODW (SignExt8to16 <config.Frontend().TypeInt16()> x) (SignExt8to16 <config.Frontend().TypeInt16()> y))
+(Mod8u x y) -> (MODWU (ZeroExt8to16 <config.Frontend().TypeUInt16()> x) (ZeroExt8to16 <config.Frontend().TypeUInt16()> y))
+
(And64 x y) -> (ANDQ x y)
(And32 x y) -> (ANDL x y)
(And16 x y) -> (ANDW x y)
diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
index b218c66..7469601 100644
--- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go
@@ -103,6 +103,8 @@
clobbers: dx | flags}
gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
clobbers: ax | flags}
+ gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx},
+ clobbers: ax | flags}
gp10 = regInfo{inputs: []regMask{gp}}
gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
@@ -202,6 +204,13 @@
{name: "DIVLU", reg: gp11div, asm: "DIVL"}, // arg0 / arg1
{name: "DIVWU", reg: gp11div, asm: "DIVW"}, // arg0 / arg1
+ {name: "MODQ", reg: gp11mod, asm: "IDIVQ"}, // arg0 % arg1
+ {name: "MODL", reg: gp11mod, asm: "IDIVL"}, // arg0 % arg1
+ {name: "MODW", reg: gp11mod, asm: "IDIVW"}, // arg0 % arg1
+ {name: "MODQU", reg: gp11mod, asm: "DIVQ"}, // arg0 % arg1
+ {name: "MODLU", reg: gp11mod, asm: "DIVL"}, // arg0 % arg1
+ {name: "MODWU", reg: gp11mod, asm: "DIVW"}, // arg0 % arg1
+
{name: "ANDQ", reg: gp21, asm: "ANDQ"}, // arg0 & arg1
{name: "ANDL", reg: gp21, asm: "ANDL"}, // arg0 & arg1
{name: "ANDW", reg: gp21, asm: "ANDW"}, // arg0 & arg1
diff --git a/src/cmd/compile/internal/ssa/gen/genericOps.go b/src/cmd/compile/internal/ssa/gen/genericOps.go
index 5b8b064..78524a5 100644
--- a/src/cmd/compile/internal/ssa/gen/genericOps.go
+++ b/src/cmd/compile/internal/ssa/gen/genericOps.go
@@ -35,7 +35,6 @@
{name: "Div32F"}, // arg0 / arg1
{name: "Div64F"},
- // TODO: Div8, Div16, Div32, Div64 and unsigned
{name: "Hmul8"}, // (arg0 * arg1) >> width
{name: "Hmul8u"},
@@ -54,6 +53,15 @@
{name: "Div64"},
{name: "Div64u"},
+ {name: "Mod8"}, // arg0 % arg1
+ {name: "Mod8u"},
+ {name: "Mod16"},
+ {name: "Mod16u"},
+ {name: "Mod32"},
+ {name: "Mod32u"},
+ {name: "Mod64"},
+ {name: "Mod64u"},
+
{name: "And8"}, // arg0 & arg1
{name: "And16"},
{name: "And32"},
