diff --git a/src/cmd/asm/internal/arch/arm.go b/src/cmd/asm/internal/arch/arm.go
index c030214..8df994e 100644
--- a/src/cmd/asm/internal/arch/arm.go
+++ b/src/cmd/asm/internal/arch/arm.go
@@ -121,6 +121,15 @@
 	return false
 }
 
+// IsARMFloatCmp reports whether the op is a floating comparison instruction.
+func IsARMFloatCmp(op int) bool {
+	switch op {
+	case arm.ACMPF, arm.ACMPD:
+		return true
+	}
+	return false
+}
+
 // ARMMRCOffset implements the peculiar encoding of the MRC and MCR instructions.
 // The difference between MRC and MCR is represented by a bit high in the word, not
 // in the usual way by the opcode itself. Asm must use AMRC for both instructions, so
diff --git a/src/cmd/asm/internal/asm/asm.go b/src/cmd/asm/internal/asm/asm.go
index 7ac8bf4..3563c1a 100644
--- a/src/cmd/asm/internal/asm/asm.go
+++ b/src/cmd/asm/internal/asm/asm.go
@@ -463,6 +463,11 @@
 				}
 				p.errorf("unrecognized addressing for %s", obj.Aconv(op))
 			}
+			if arch.IsARMFloatCmp(op) {
+				prog.From = a[0]
+				prog.Reg = p.getRegister(prog, op, &a[1])
+				break
+			}
 		} else if p.arch.Thechar == '7' && arch.IsARM64CMP(op) {
 			prog.From = a[0]
 			prog.Reg = p.getRegister(prog, op, &a[1])
diff --git a/src/cmd/asm/internal/asm/testdata/arm.out b/src/cmd/asm/internal/asm/testdata/arm.out
index 7501db3..1af3999 100644
--- a/src/cmd/asm/internal/asm/testdata/arm.out
+++ b/src/cmd/asm/internal/asm/testdata/arm.out
@@ -56,4 +56,6 @@
 281 00056 (testdata/arm.s:281)	CALL	foo(SB)
 282 00057 (testdata/arm.s:282)	JMP	foo(SB)
 283 00058 (testdata/arm.s:283)	CALL	foo(SB)
-292 00059 (testdata/arm.s:292)	END
+286 00059 (testdata/arm.s:286)	CMPF	F1, F2
+287 00060 (testdata/arm.s:287)	CMPD	F1, F2
+296 00061 (testdata/arm.s:296)	END
diff --git a/src/cmd/asm/internal/asm/testdata/arm.s b/src/cmd/asm/internal/asm/testdata/arm.s
index b8bdfb2..95fee50 100644
--- a/src/cmd/asm/internal/asm/testdata/arm.s
+++ b/src/cmd/asm/internal/asm/testdata/arm.s
@@ -282,6 +282,10 @@
 	JMP	foo(SB)
 	CALL	foo(SB)
 
+// CMPF and CMPD are special.
+	CMPF F1, F2
+	CMPD F1, F2
+
 //
 // END
 //