cmd/internal/obj/riscv: add assembly support for Zihintpause extensions

Add support for the PAUSE instruction provided by the Zihintpause
extension.

Change-Id: If06cce4ca57137275f567b5fe29ef85517f381ef
Reviewed-on: https://go-review.googlesource.com/c/go/+/710495
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>

src/cmd/asm/internal/asm/testdata/riscv64.s

diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 65ccf09..cee47f7 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -199,6 +199,9 @@
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
+	// 10.1: Zihintpause Extension for Pause Hint
+	PAUSE						// 0f000001
+
 	// 12.3: Integer Conditional Operations (Zicond)
 	CZEROEQZ	X5, X6, X7			// b353530e
 	CZEROEQZ	X5, X7				// b3d3530e

src/cmd/internal/obj/riscv/anames.go

diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go
index 1f777dd..9bc4ac4 100644
--- a/src/cmd/internal/obj/riscv/anames.go
+++ b/src/cmd/internal/obj/riscv/anames.go
@@ -939,6 +939,7 @@
 	"NEG",
 	"NEGW",
 	"NOT",
+	"PAUSE",
 	"RDCYCLE",
 	"RDINSTRET",
 	"RDTIME",

src/cmd/internal/obj/riscv/cpu.go

diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go
index 433c8e1..8112c56 100644
--- a/src/cmd/internal/obj/riscv/cpu.go
+++ b/src/cmd/internal/obj/riscv/cpu.go
@@ -1508,6 +1508,7 @@
 	ANEG
 	ANEGW
 	ANOT
+	APAUSE
 	ARDCYCLE
 	ARDINSTRET
 	ARDTIME

src/cmd/internal/obj/riscv/obj.go

diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index 50c687f..332df52 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -4421,6 +4421,10 @@
 			ins.imm = int64((pred << 4) | succ)
 		}
 
+	case APAUSE:
+		ins.as, ins.rd, ins.rs1, ins.rs2 = AFENCE, REG_ZERO, REG_ZERO, obj.REG_NONE
+		ins.imm = 0x010
+
 	case AFCVTWS, AFCVTLS, AFCVTWUS, AFCVTLUS, AFCVTWD, AFCVTLD, AFCVTWUD, AFCVTLUD:
 		// Set the default rounding mode in funct3 to round to zero.
 		if p.Scond&rmSuffixBit == 0 {