diff --git a/ppc64/pp64.csv b/ppc64/pp64.csv
index c26718e..4f470e4 100644
--- a/ppc64/pp64.csv
+++ b/ppc64/pp64.csv
@@ -116,6 +116,10 @@
 "Divide Doubleword Unsigned XO-form","divdu RT,RA,RB (OE=0 Rc=0)|divdu. RT,RA,RB (OE=0 Rc=1)|divduo RT,RA,RB (OE=1 Rc=0)|divduo. RT,RA,RB (OE=1 Rc=1)","31@0|RT@6|RA@11|RB@16|OE@21|457@22|Rc@31|",""
 "Divide Doubleword Extended XO-form","divde RT,RA,RB (OE=0 Rc=0)|divde. RT,RA,RB (OE=0 Rc=1)|divdeo RT,RA,RB (OE=1 Rc=0)|divdeo. RT,RA,RB (OE=1 Rc=1)|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RT@6|RA@11|RB@16|OE@21|425@22|Rc@31|",""
 "Divide Doubleword Extended Unsigned XO-form","divdeu RT,RA,RB (OE=0 Rc=0)|divdeu. RT,RA,RB (OE=0 Rc=1)|divdeuo RT,RA,RB (OE=1 Rc=0)|divdeuo. RT,RA,RB (OE=1 Rc=1)|[Category: Server]|[Category: Embedded.Phased-In]","31@0|RT@6|RA@11|RB@16|OE@21|393@22|Rc@31|",""
+"Modulo Signed Doubleword X-form","modsd RT,RA,RB","31@0|RT@6|RA@11|RB@16|777@21|/@31|",""
+"Modulo Unsigned Doubleword X-form","modud RT,RA,RB","31@0|RT@6|RA@11|RB@16|265@21|/@31|",""
+"Modulo Signed Word X-form","modsw RT,RA,RB","31@0|RT@6|RA@11|RB@16|779@21|/@31|",""
+"Modulo Unsigned Word X-form","moduw RT,RA,RB","31@0|RT@6|RA@11|RB@16|267@21|/@31|",""
 "Compare Immediate D-form","cmpwi BF,RA,SI (L=0)|cmpdi BF,RA,SI (L=1)","11@0|BF@6|/@9|L@10|RA@11|SI@16|",""
 "Compare X-form","cmpw BF,RA,RB (L=0)|cmpd BF,RA,RB (L=1)","31@0|BF@6|/@9|L@10|RA@11|RB@16|0@21|/@31|",""
 "Compare Logical Immediate D-form","cmplwi BF,RA,UI (L=0)|cmpldi BF,RA,UI (L=1)","10@0|BF@6|/@9|L@10|RA@11|UI@16|",""
@@ -313,6 +317,7 @@
 "Vector Splat Immediate Signed Halfword VX-form","vspltish VRT,SIM","4@0|VRT@6|SIM@11|///@16|844@21|",""
 "Vector Splat Immediate Signed Word VX-form","vspltisw VRT,SIM","4@0|VRT@6|SIM@11|///@16|908@21|",""
 "Vector Permute VA-form","vperm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|43@26|",""
+"Vector Permute Right-indexed VA-form","vpermr VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|59@26|",""
 "Vector Select VA-form","vsel VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|42@26|",""
 "Vector Shift Left VX-form","vsl VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|452@21|",""
 "Vector Shift Left Double by Octet Immediate VA-form","vsldoi VRT,VRA,VRB,SHB","4@0|VRT@6|VRA@11|VRB@16|/@21|SHB@22|44@26|",""
@@ -371,6 +376,7 @@
 "Vector Multiply-Sum Signed Halfword Saturate VA-form","vmsumshs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|41@26|",""
 "Vector Multiply-Sum Unsigned Halfword Modulo VA-form","vmsumuhm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|38@26|",""
 "Vector Multiply-Sum Unsigned Halfword Saturate VA-form","vmsumuhs VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|39@26|",""
+"Vector Multiply-Sum Unsigned Doubleword Modulo VA-form","vmsumudm VRT,VRA,VRB,VRC","4@0|VRT@6|VRA@11|VRB@16|VRC@21|35@26|",""
 "Vector Sum across Signed Word Saturate VX-form","vsumsws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1928@21|",""
 "Vector Sum across Half Signed Word Saturate VX-form","vsum2sws VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1672@21|",""
 "Vector Sum across Quarter Signed Byte Saturate VX-form","vsum4sbs VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1800@21|",""
@@ -402,6 +408,12 @@
 "Vector Compare Equal To Unsigned Halfword VC-form","vcmpequh VRT,VRA,VRB (Rc=0)|vcmpequh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|70@22|",""
 "Vector Compare Equal To Unsigned Word VC-form","vcmpequw VRT,VRA,VRB ( Rc=0 )|vcmpequw. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|134@22|",""
 "Vector Compare Equal To Unsigned Doubleword VX-form","vcmpequd VRT,VRA,VRB ( Rc=0 )|vcmpequd. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|199@22|",""
+"Vector Compare Not Equal Byte VX-form","vcmpneb VRT,VRA,VRB ( Rc=0 )|vcmpneb. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|7@22|",""
+"Vector Compare Not Equal or Zero Byte VX-form","vcmpnezb VRT,VRA,VRB ( Rc=0 )|vcmpnezb. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|263@22|",""
+"Vector Compare Not Equal Halfword VX-form","vcmpneh VRT,VRA,VRB ( Rc=0 )|vcmpneh. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|71@22|",""
+"Vector Compare Not Equal or Zero Halfword VX-form","vcmpnezh VRT,VRA,VRB ( Rc=0 )|vcmpnezh. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|327@22|",""
+"Vector Compare Not Equal Word VX-form","vcmpnew VRT,VRA,VRB ( Rc=0 )|vcmpnew. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|135@22|",""
+"Vector Compare Not Equal or Zero Word VX-form","vcmpnezw VRT,VRA,VRB ( Rc=0 )|vcmpnezw. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|391@22|",""
 "Vector Compare Greater Than Signed Byte VC-form","vcmpgtsb VRT,VRA,VRB ( Rc=0 )|vcmpgtsb. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|774@22|",""
 "Vector Compare Greater Than Signed Doubleword VX-form","vcmpgtsd VRT,VRA,VRB ( Rc=0 )|vcmpgtsd. VRT,VRA,VRB ( Rc=1 )","4@0|VRT@6|VRA@11|VRB@16|Rc@21|967@22|",""
 "Vector Compare Greater Than Signed Halfword VC-form","vcmpgtsh VRT,VRA,VRB (Rc=0)|vcmpgtsh. VRT,VRA,VRB (Rc=1)","4@0|VRT@6|VRA@11|VRB@16|Rc@21|838@22|",""
@@ -478,6 +490,7 @@
 "Vector Population Count Halfword","vpopcnth VRT,VRB","4@0|VRT@6|///@11|VRB@16|1859@21|",""
 "Vector Population Count Word","vpopcntw VRT,VRB","4@0|VRT@6|///@11|VRB@16|1923@21|",""
 "Vector Bit Permute Quadword VX-form","vbpermq VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1356@21|",""
+"Vector Bit Permute Doubleword VX-form","vbpermd VRT,VRA,VRB","4@0|VRT@6|VRA@11|VRB@16|1484@21|",""
 "Decimal Add Modulo VX-form","bcdadd. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|1@23|",""
 "Decimal Subtract Modulo VX-form","bcdsub. VRT,VRA,VRB,PS","4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|65@23|",""
 "Move To Vector Status and Control Register VX-form","mtvscr VRB","4@0|///@6|///@11|VRB@16|1604@21|",""
@@ -517,11 +530,17 @@
 "Load VSX Vector Doubleword*2 Indexed XX1-form","lxvd2x XT,RA,RB","31@0|T@6|RA@11|RB@16|844@21|TX@31|",""
 "Load VSX Vector Doubleword & Splat Indexed XX1-form","lxvdsx XT,RA,RB ( 0x7C00_0298 )","31@0|T@6|RA@11|RB@16|332@21|TX@31|",""
 "Load VSX Vector Word*4 Indexed XX1-form","lxvw4x XT,RA,RB","31@0|T@6|RA@11|RB@16|780@21|TX@31|",""
+"Load VSX Vector DQ-form","lxv XT,DQ(RA)","61@0|T@6|RA@11|DQ@16|TX@28|1@29|",""
+"Load VSX Vector with Length X-form","lxvl XT,RA,RB","31@0|T@6|RA@11|RB@16|269@21|TX@31|",""
+"Load VSX Vector Left-justified with Length X-form","lxvll XT,RA,RB","31@0|T@6|RA@11|RB@16|301@21|TX@31|",""
 "Store VSX Scalar Doubleword Indexed XX1-form","stxsdx XS,RA,RB","31@0|S@6|RA@11|RB@16|716@21|SX@31|",""
 "Store VSX Scalar as Integer Word Indexed XX1-form","stxsiwx XS,RA,RB","31@0|S@6|RA@11|RB@16|140@21|SX@31|",""
 "Store VSX Scalar Single-Precision Indexed XX1-form","stxsspx XS,RA,RB","31@0|S@6|RA@11|RB@16|652@21|SX@31|",""
 "Store VSX Vector Doubleword*2 Indexed XX1-form","stxvd2x XS,RA,RB","31@0|S@6|RA@11|RB@16|972@21|SX@31|",""
 "Store VSX Vector Word*4 Indexed XX1-form","stxvw4x XS,RA,RB","31@0|S@6|RA@11|RB@16|908@21|SX@31|",""
+"Store VSX Vector DQ-form","stxv XS,DQ(RA)","61@0|S@6|RA@11|DQ@16|SX@28|5@29|",""
+"Store VSX Vector with Length X-form","stxvl XS,RA,RB","31@0|S@6|RA@11|RB@16|397@21|SX@31|",""
+"Store VSX Vector Left-justified with Length X-form","stxvll XS,RA,RB","31@0|S@6|RA@11|RB@16|429@21|SX@31|",""
 "VSX Scalar Absolute Value Double-Precision XX2-form","xsabsdp XT,XB","60@0|T@6|///@11|B@16|345@21|BX@30|TX@31|",""
 "VSX Scalar Add Double-Precision XX3-form","xsadddp XT,XA,XB","60@0|T@6|A@11|B@16|32@21|AX@29|BX@30|TX@31|",""
 "VSX Scalar Add Single-Precision XX3-form","xsaddsp XT,XA,XB","60@0|T@6|A@11|B@16|0@21|AX@29|BX@30|TX@31|",""
@@ -655,6 +674,7 @@
 "VSX Merge High Word XX3-form","xxmrghw XT,XA,XB","60@0|T@6|A@11|B@16|18@21|AX@29|BX@30|TX@31|",""
 "VSX Merge Low Word XX3-form","xxmrglw XT,XA,XB","60@0|T@6|A@11|B@16|50@21|AX@29|BX@30|TX@31|",""
 "VSX Permute Doubleword Immediate XX3-form","xxpermdi XT,XA,XB,DM","60@0|T@6|A@11|B@16|0@21|DM@22|10@24|AX@29|BX@30|TX@31|",""
+"VSX Permute XX3-form","xxperm XT,XA,XB","60@0|T@6|A@11|B@16|26@21|AX@29|BX@30|TX@31|",""
 "VSX Select XX4-form","xxsel XT,XA,XB,XC","60@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|",""
 "VSX Shift Left Double by Word Immediate XX3-form","xxsldwi XT,XA,XB,SHW","60@0|T@6|A@11|B@16|0@21|SHW@22|2@24|AX@29|BX@30|TX@31|",""
 "VSX Splat Word XX2-form","xxspltw XT,XB,UIM","60@0|T@6|///@11|UIM@14|B@16|164@21|BX@30|TX@31|",""
diff --git a/ppc64/ppc64asm/gnu.go b/ppc64/ppc64asm/gnu.go
index fc29164..1849a29 100644
--- a/ppc64/ppc64asm/gnu.go
+++ b/ppc64/ppc64asm/gnu.go
@@ -134,6 +134,19 @@
 			buf.WriteString("spr")
 		}
 
+	case "sync":
+		switch arg := inst.Args[0].(type) {
+		case Imm:
+			switch arg {
+			case 0:
+				buf.WriteString("hwsync")
+			case 1:
+				buf.WriteString("lwsync")
+			case 2:
+				buf.WriteString("ptesync")
+			}
+		}
+		startArg = 2
 	default:
 		buf.WriteString(inst.Op.String())
 	}
@@ -262,6 +275,8 @@
 		return true
 	case LHBRX, LWBRX, STHBRX, STWBRX:
 		return true
+	case LBARX, LWARX, LHARX, LDARX:
+		return true
 	}
 	return false
 }
diff --git a/ppc64/ppc64asm/plan9.go b/ppc64/ppc64asm/plan9.go
index d039d9d..858f9ac 100644
--- a/ppc64/ppc64asm/plan9.go
+++ b/ppc64/ppc64asm/plan9.go
@@ -55,10 +55,24 @@
 	// laid out the instruction
 	switch inst.Op {
 	default: // dst, sA, sB, ...
-		if len(args) == 0 {
+		switch len(args) {
+		case 0:
 			return op
-		} else if len(args) == 1 {
+		case 1:
 			return fmt.Sprintf("%s %s", op, args[0])
+		case 2:
+			if inst.Op == COPY || inst.Op == PASTECC || inst.Op == FCMPO || inst.Op == FCMPU {
+				return op + " " + args[0] + "," + args[1]
+			}
+			return op + " " + args[1] + "," + args[0]
+		case 3:
+			if reverseOperandOrder(inst.Op) {
+				return op + " " + args[2] + "," + args[1] + "," + args[0]
+			}
+		case 4:
+			if reverseMiddleOps(inst.Op) {
+				return op + " " + args[1] + "," + args[3] + "," + args[2] + "," + args[0]
+			}
 		}
 		args = append(args, args[0])
 		return op + " " + strings.Join(args[1:], ",")
@@ -77,7 +91,7 @@
 		STH, STHU,
 		STW, STWU,
 		STD, STDU,
-		STQ:
+		STQ, STFD, STFDU, STFS, STFSU:
 		return op + " " + strings.Join(args, ",")
 
 	case CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
@@ -92,28 +106,41 @@
 		return "ADDIS $0," + args[1] + "," + args[0]
 	// store instructions with index registers
 	case STBX, STBUX, STHX, STHUX, STWX, STWUX, STDX, STDUX,
-		STHBRX, STWBRX, STDBRX, STSWX, STFSX, STFSUX, STFDX, STFDUX, STFIWX, STFDPX:
+		STHBRX, STWBRX, STDBRX, STSWX, STFIWX:
 		return "MOV" + op[2:len(op)-1] + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
 	case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
 		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
-	case STXVD2X, STXVW4X:
+	case STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
 		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
-	// load instructions with index registers
-	case LBZX, LBZUX, LHZX, LHZUX, LWZX, LWZUX, LDX, LDUX,
-		LHBRX, LWBRX, LDBRX, LSWX, LFSX, LFSUX, LFDX, LFDUX, LFIWAX, LFIWZX:
-		return "MOV" + op[1:len(op)-1] + " (" + args[2] + ")(" + args[1] + ")," + args[0]
+	case STXV:
+		return op + " " + args[0] + "," + args[1]
 
-	case LDARX, LWARX, LHARX, LBARX:
+	case STXVL, STXVLL:
+		return op + " " + args[0] + "," + args[1] + "," + args[2]
+
+	case LWAX, LWAUX, LWZX, LHZX, LBZX, LDX, LHAX, LHAUX, LDARX, LWARX, LHARX, LBARX, LFDX, LFDUX, LFSX, LFSUX, LDBRX, LWBRX, LHBRX, LDUX, LWZUX, LHZUX, LBZUX:
+		if args[1] == "0" {
+			return op + " (" + args[2] + ")," + args[0]
+		}
 		return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
 
-	case LXVD2X, LXVW4X:
+	case LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
 		return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
 
-	case DCBT, DCBTST, DCBZ, DCBST:
-		return op + " (" + args[1] + ")"
+	case LXV:
+		return op + " " + args[1] + "," + args[0]
+
+	case LXVL, LXVLL:
+		return op + " " + args[1] + "," + args[2] + "," + args[0]
+
+	case DCBT, DCBTST, DCBZ, DCBST, DCBI, ICBI:
+		if args[0] == "0" || args[0] == "R0" {
+			return op + " (" + args[1] + ")"
+		}
+		return op + " (" + args[1] + ")(" + args[0] + ")"
 
 	// branch instructions needs additional handling
 	case BCLR:
@@ -173,12 +200,15 @@
 		if inst.Op == ISEL {
 			return fmt.Sprintf("$%d", (arg - Cond0LT))
 		}
-		if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
+		if arg == CR0 && (strings.HasPrefix(inst.Op.String(), "cmp") || strings.HasPrefix(inst.Op.String(), "fcmp")) {
 			return "" // don't show cr0 for cmp instructions
 		} else if arg >= CR0 {
 			return fmt.Sprintf("CR%d", int(arg-CR0))
 		}
 		bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4]
+		if strings.HasPrefix(inst.Op.String(), "cr") {
+			return fmt.Sprintf("CR%d%s", int(arg-Cond0LT)/4, bit)
+		}
 		if arg <= Cond0SO {
 			return bit
 		}
@@ -212,6 +242,37 @@
 	return fmt.Sprintf("???(%v)", arg)
 }
 
+func reverseMiddleOps(op Op) bool {
+	switch op {
+	case FMADD, FMADDCC, FMADDS, FMADDSCC, FMSUB, FMSUBCC, FMSUBS, FMSUBSCC, FNMADD, FNMADDCC, FNMADDS, FNMADDSCC, FNMSUB, FNMSUBCC, FNMSUBS, FNMSUBSCC, FSEL, FSELCC:
+		return true
+	}
+	return false
+}
+
+func reverseOperandOrder(op Op) bool {
+	switch op {
+	// Special case for SUBF, SUBFC: not reversed
+	case ADD, ADDC, ADDE, ADDCC, ADDCCC:
+		return true
+	case MULLW, MULLWCC, MULHW, MULHWCC, MULLD, MULLDCC, MULHD, MULHDCC, MULLWO, MULLWOCC, MULHWU, MULHWUCC, MULLDO, MULLDOCC:
+		return true
+	case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
+		return true
+	case MODUD, MODSD, MODUW, MODSW:
+		return true
+	case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC:
+		return true
+	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
+		return true
+	case OR, ORC, AND, ANDC, XOR, NAND, EQV, NOR, ANDCC, ORCC, XORCC, EQVCC, NORCC, NANDCC:
+		return true
+	case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
+		return true
+	}
+	return false
+}
+
 // revCondMap maps a conditional register bit to its inverse, if possible.
 var revCondMap = map[string]string{
 	"LT": "GE", "GT": "LE", "EQ": "NE",
@@ -219,15 +280,65 @@
 
 // plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics.
 var plan9OpMap = map[Op]string{
-	LWARX: "LWAR",
-	LDARX: "LDAR",
-	LHARX: "LHAR",
-	LBARX: "LBAR",
-	ADDI:  "ADD",
-	SRADI: "SRAD",
-	SUBF:  "SUB",
-	LI:    "MOVD",
-	LBZ:   "MOVBZ", STB: "MOVB",
+	LWARX:     "LWAR",
+	LDARX:     "LDAR",
+	LHARX:     "LHAR",
+	LBARX:     "LBAR",
+	LWAX:      "MOVW",
+	LHAX:      "MOVH",
+	LWAUX:     "MOVWU",
+	LHAU:      "MOVHU",
+	LHAUX:     "MOVHU",
+	LDX:       "MOVD",
+	LDUX:      "MOVDU",
+	LWZX:      "MOVWZ",
+	LWZUX:     "MOVWZU",
+	LHZX:      "MOVHZ",
+	LHZUX:     "MOVHZU",
+	LBZX:      "MOVBZ",
+	LBZUX:     "MOVBZU",
+	LDBRX:     "MOVDBR",
+	LWBRX:     "MOVWBR",
+	LHBRX:     "MOVHBR",
+	MCRF:      "MOVFL",
+	XORI:      "XOR",
+	ORI:       "OR",
+	ANDICC:    "ANDCC",
+	ANDC:      "ANDN",
+	ADDEO:     "ADDEV",
+	ADDEOCC:   "ADDEVCC",
+	ADDO:      "ADDV",
+	ADDOCC:    "ADDVCC",
+	ADDMEO:    "ADDMEV",
+	ADDMEOCC:  "ADDMEVCC",
+	ADDCO:     "ADDCV",
+	ADDCOCC:   "ADDCVCC",
+	ADDZEO:    "ADDZEV",
+	ADDZEOCC:  "ADDZEVCC",
+	SUBFME:    "SUBME",
+	SUBFMECC:  "SUBMECC",
+	SUBFZE:    "SUBZE",
+	SUBFZECC:  "SUBZECC",
+	SUBFZEO:   "SUBZEV",
+	SUBFZEOCC: "SUBZEVCC",
+	SUBFC:     "SUBC",
+	ORC:       "ORN",
+	MULLWO:    "MULLWV",
+	MULLWOCC:  "MULLWVCC",
+	MULLDO:    "MULLDV",
+	MULLDOCC:  "MULLDVCC",
+	DIVDO:     "DIVDV",
+	DIVDOCC:   "DIVDVCC",
+	DIVDUO:    "DIVDUV",
+	DIVDUOCC:  "DIVDUVCC",
+	ADDI:      "ADD",
+	SRADI:     "SRAD",
+	SUBF:      "SUB",
+	STBCXCC:   "STBCCC",
+	STWCXCC:   "STWCCC",
+	STDCXCC:   "STDCCC",
+	LI:        "MOVD",
+	LBZ:       "MOVBZ", STB: "MOVB",
 	LBZU: "MOVBZU", STBU: "MOVBU",
 	LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
 	LHZU: "MOVHZU", STHU: "MOVHU",
@@ -235,6 +346,14 @@
 	LWZU: "MOVWZU", STWU: "MOVWU",
 	LD: "MOVD", STD: "MOVD",
 	LDU: "MOVDU", STDU: "MOVDU",
+	LFD: "FMOVD", STFD: "FMOVD",
+	LFS: "FMOVS", STFS: "FMOVS",
+	LFDX: "FMOVD", STFDX: "FMOVD",
+	LFDU: "FMOVDU", STFDU: "FMOVDU",
+	LFDUX: "FMOVDU", STFDUX: "FMOVDU",
+	LFSX: "FMOVS", STFSX: "FMOVS",
+	LFSU: "FMOVSU", STFSU: "FMOVSU",
+	LFSUX: "FMOVSU", STFSUX: "FMOVSU",
 	CMPD: "CMP", CMPDI: "CMP",
 	CMPW: "CMPW", CMPWI: "CMPW",
 	CMPLD: "CMPU", CMPLDI: "CMPU",
diff --git a/ppc64/ppc64asm/tables.go b/ppc64/ppc64asm/tables.go
index f536926..250d3b7 100644
--- a/ppc64/ppc64asm/tables.go
+++ b/ppc64/ppc64asm/tables.go
@@ -186,6 +186,10 @@
 	DIVDEUCC
 	DIVDEUO
 	DIVDEUOCC
+	MODSD
+	MODUD
+	MODSW
+	MODUW
 	CMPWI
 	CMPDI
 	CMPW
@@ -466,6 +470,7 @@
 	VSPLTISH
 	VSPLTISW
 	VPERM
+	VPERMR
 	VSEL
 	VSL
 	VSLDOI
@@ -524,6 +529,7 @@
 	VMSUMSHS
 	VMSUMUHM
 	VMSUMUHS
+	VMSUMUDM
 	VSUMSWS
 	VSUM2SWS
 	VSUM4SBS
@@ -559,6 +565,18 @@
 	VCMPEQUWCC
 	VCMPEQUD
 	VCMPEQUDCC
+	VCMPNEB
+	VCMPNEBCC
+	VCMPNEZB
+	VCMPNEZBCC
+	VCMPNEH
+	VCMPNEHCC
+	VCMPNEZH
+	VCMPNEZHCC
+	VCMPNEW
+	VCMPNEWCC
+	VCMPNEZW
+	VCMPNEZWCC
 	VCMPGTSB
 	VCMPGTSBCC
 	VCMPGTSD
@@ -647,6 +665,7 @@
 	VPOPCNTH
 	VPOPCNTW
 	VBPERMQ
+	VBPERMD
 	BCDADDCC
 	BCDSUBCC
 	MTVSCR
@@ -708,11 +727,17 @@
 	LXVD2X
 	LXVDSX
 	LXVW4X
+	LXV
+	LXVL
+	LXVLL
 	STXSDX
 	STXSIWX
 	STXSSPX
 	STXVD2X
 	STXVW4X
+	STXV
+	STXVL
+	STXVLL
 	XSABSDP
 	XSADDDP
 	XSADDSP
@@ -852,6 +877,7 @@
 	XXMRGHW
 	XXMRGLW
 	XXPERMDI
+	XXPERM
 	XXSEL
 	XXSLDWI
 	XXSPLTW
@@ -1528,6 +1554,10 @@
 	DIVDEUCC:      "divdeu.",
 	DIVDEUO:       "divdeuo",
 	DIVDEUOCC:     "divdeuo.",
+	MODSD:         "modsd",
+	MODUD:         "modud",
+	MODSW:         "modsw",
+	MODUW:         "moduw",
 	CMPWI:         "cmpwi",
 	CMPDI:         "cmpdi",
 	CMPW:          "cmpw",
@@ -1808,6 +1838,7 @@
 	VSPLTISH:      "vspltish",
 	VSPLTISW:      "vspltisw",
 	VPERM:         "vperm",
+	VPERMR:        "vpermr",
 	VSEL:          "vsel",
 	VSL:           "vsl",
 	VSLDOI:        "vsldoi",
@@ -1866,6 +1897,7 @@
 	VMSUMSHS:      "vmsumshs",
 	VMSUMUHM:      "vmsumuhm",
 	VMSUMUHS:      "vmsumuhs",
+	VMSUMUDM:      "vmsumudm",
 	VSUMSWS:       "vsumsws",
 	VSUM2SWS:      "vsum2sws",
 	VSUM4SBS:      "vsum4sbs",
@@ -1901,6 +1933,18 @@
 	VCMPEQUWCC:    "vcmpequw.",
 	VCMPEQUD:      "vcmpequd",
 	VCMPEQUDCC:    "vcmpequd.",
+	VCMPNEB:       "vcmpneb",
+	VCMPNEBCC:     "vcmpneb.",
+	VCMPNEZB:      "vcmpnezb",
+	VCMPNEZBCC:    "vcmpnezb.",
+	VCMPNEH:       "vcmpneh",
+	VCMPNEHCC:     "vcmpneh.",
+	VCMPNEZH:      "vcmpnezh",
+	VCMPNEZHCC:    "vcmpnezh.",
+	VCMPNEW:       "vcmpnew",
+	VCMPNEWCC:     "vcmpnew.",
+	VCMPNEZW:      "vcmpnezw",
+	VCMPNEZWCC:    "vcmpnezw.",
 	VCMPGTSB:      "vcmpgtsb",
 	VCMPGTSBCC:    "vcmpgtsb.",
 	VCMPGTSD:      "vcmpgtsd",
@@ -1989,6 +2033,7 @@
 	VPOPCNTH:      "vpopcnth",
 	VPOPCNTW:      "vpopcntw",
 	VBPERMQ:       "vbpermq",
+	VBPERMD:       "vbpermd",
 	BCDADDCC:      "bcdadd.",
 	BCDSUBCC:      "bcdsub.",
 	MTVSCR:        "mtvscr",
@@ -2050,11 +2095,17 @@
 	LXVD2X:        "lxvd2x",
 	LXVDSX:        "lxvdsx",
 	LXVW4X:        "lxvw4x",
+	LXV:           "lxv",
+	LXVL:          "lxvl",
+	LXVLL:         "lxvll",
 	STXSDX:        "stxsdx",
 	STXSIWX:       "stxsiwx",
 	STXSSPX:       "stxsspx",
 	STXVD2X:       "stxvd2x",
 	STXVW4X:       "stxvw4x",
+	STXV:          "stxv",
+	STXVL:         "stxvl",
+	STXVLL:        "stxvll",
 	XSABSDP:       "xsabsdp",
 	XSADDDP:       "xsadddp",
 	XSADDSP:       "xsaddsp",
@@ -2194,6 +2245,7 @@
 	XXMRGHW:       "xxmrghw",
 	XXMRGLW:       "xxmrglw",
 	XXPERMDI:      "xxpermdi",
+	XXPERM:        "xxperm",
 	XXSEL:         "xxsel",
 	XXSLDWI:       "xxsldwi",
 	XXSPLTW:       "xxspltw",
@@ -2745,6 +2797,7 @@
 	ap_ImmUnsigned_21_22       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
 	ap_ImmUnsigned_11_12       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
 	ap_ImmUnsigned_11_11       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
+	ap_VecSReg_28_28_6_10      = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {6, 5}}}
 	ap_VecSReg_30_30_16_20     = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
 	ap_VecSReg_29_29_11_15     = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
 	ap_ImmUnsigned_22_23       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
@@ -3125,6 +3178,14 @@
 		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
 		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MODSD, 0xfc0007fe, 0x7c000612, 0x1, // Modulo Signed Doubleword X-form (modsd RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MODUD, 0xfc0007fe, 0x7c000212, 0x1, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MODSW, 0xfc0007fe, 0x7c000616, 0x1, // Modulo Signed Word X-form (modsw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{MODUW, 0xfc0007fe, 0x7c000216, 0x1, // Modulo Unsigned Word X-form (moduw RT,RA,RB)
+		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
 		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
 	{CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI)
@@ -3685,6 +3746,8 @@
 		[5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
 	{VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VPERMR, 0xfc00003f, 0x1000003b, 0x0, // Vector Permute Right-indexed VA-form (vpermr VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
 	{VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
 	{VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB)
@@ -3801,6 +3864,8 @@
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
 	{VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
+	{VMSUMUDM, 0xfc00003f, 0x10000023, 0x0, // Vector Multiply-Sum Unsigned Doubleword Modulo VA-form (vmsumudm VRT,VRA,VRB,VRC)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
 	{VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
 	{VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB)
@@ -3871,6 +3936,30 @@
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
 	{VCMPEQUDCC, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEB, 0xfc0007ff, 0x10000007, 0x0, // Vector Compare Not Equal Byte VX-form (vcmpneb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEBCC, 0xfc0007ff, 0x10000407, 0x0, // Vector Compare Not Equal Byte VX-form (vcmpneb. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEZB, 0xfc0007ff, 0x10000107, 0x0, // Vector Compare Not Equal or Zero Byte VX-form (vcmpnezb VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEZBCC, 0xfc0007ff, 0x10000507, 0x0, // Vector Compare Not Equal or Zero Byte VX-form (vcmpnezb. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEH, 0xfc0007ff, 0x10000047, 0x0, // Vector Compare Not Equal Halfword VX-form (vcmpneh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEHCC, 0xfc0007ff, 0x10000447, 0x0, // Vector Compare Not Equal Halfword VX-form (vcmpneh. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEZH, 0xfc0007ff, 0x10000147, 0x0, // Vector Compare Not Equal or Zero Halfword VX-form (vcmpnezh VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEZHCC, 0xfc0007ff, 0x10000547, 0x0, // Vector Compare Not Equal or Zero Halfword VX-form (vcmpnezh. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEW, 0xfc0007ff, 0x10000087, 0x0, // Vector Compare Not Equal Word VX-form (vcmpnew VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEWCC, 0xfc0007ff, 0x10000487, 0x0, // Vector Compare Not Equal Word VX-form (vcmpnew. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEZW, 0xfc0007ff, 0x10000187, 0x0, // Vector Compare Not Equal or Zero Word VX-form (vcmpnezw VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VCMPNEZWCC, 0xfc0007ff, 0x10000587, 0x0, // Vector Compare Not Equal or Zero Word VX-form (vcmpnezw. VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
 	{VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
 	{VCMPGTSBCC, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
@@ -4047,6 +4136,8 @@
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
 	{VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
+	{VBPERMD, 0xfc0007ff, 0x100005cc, 0x0, // Vector Bit Permute Doubleword VX-form (vbpermd VRT,VRA,VRB)
+		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
 	{BCDADDCC, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
 		[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
 	{BCDSUBCC, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
@@ -4169,6 +4260,12 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXV, 0xfc000007, 0xf4000001, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
+		[5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+	{LXVL, 0xfc0007fe, 0x7c00021a, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB)
@@ -4179,6 +4276,12 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXV, 0xfc000007, 0xf4000005, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
+		[5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
+	{STXVL, 0xfc0007fe, 0x7c00031a, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXVLL, 0xfc0007fe, 0x7c00035a, 0x0, // Store VSX Vector Left-justified with Length X-form (stxvll XS,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
 	{XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
@@ -4457,6 +4560,8 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
 	{XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
+	{XXPERM, 0xfc0007f8, 0xf00000d0, 0x0, // VSX Permute XX3-form (xxperm XT,XA,XB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
 	{XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}},
 	{XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW)
diff --git a/ppc64/ppc64asm/testdata/decode.txt b/ppc64/ppc64asm/testdata/decode.txt
index 69e6942..e094383 100644
--- a/ppc64/ppc64asm/testdata/decode.txt
+++ b/ppc64/ppc64asm/testdata/decode.txt
@@ -47,7 +47,7 @@
 7c2b4840|	gnu	cmpld r11,r9
 7c2b4840|	plan9	CMPU R11,R9
 7c6521ad|	gnu	stdcx. r3,r5,r4
-7c6521ad|	plan9	STDCXCC R3,(R4)(R5)
+7c6521ad|	plan9	STDCCC R3,(R4)(R5)
 fbe1ffd1|	gnu	stdu r31,-48(r1)
 fbe1ffd1|	plan9	MOVDU R31,-48(R1)
 7c941f19|	gnu	stxvw4x vs36,r20,r3
@@ -74,3 +74,759 @@
 41880008|	gnu	blt cr2,0x8
 418d0004|	plan9	BGT CR3,0x4
 418d0004|	gnu	bgt cr3,0x4
+e8830008|	plan9	MOVD 8(R3),R4
+7ca4182a|	plan9	MOVD (R3)(R4),R5
+e8830006|	plan9	MOVW 4(R3),R4
+7ca41aaa|	plan9	MOVW (R3)(R4),R5
+80830004|	plan9	MOVWZ 4(R3),R4
+7ca4182e|	plan9	MOVWZ (R3)(R4),R5
+a8830004|	plan9	MOVH 4(R3),R4
+7ca41aae|	plan9	MOVH (R3)(R4),R5
+a0830002|	plan9	MOVHZ 2(R3),R4
+7ca41a2e|	plan9	MOVHZ (R3)(R4),R5
+7ca418ae|	plan9	MOVBZ (R3)(R4),R5
+7ca41c28|	plan9	MOVDBR (R3)(R4),R5
+7ca41c2c|	plan9	MOVWBR (R3)(R4),R5
+7ca41e2c|	plan9	MOVHBR (R3)(R4),R5
+e8830009|	plan9	MOVDU 8(R3),R4
+7ca4186a|	plan9	MOVDU (R3)(R4),R5
+7ca41aea|	plan9	MOVWU (R3)(R4),R5
+84830004|	plan9	MOVWZU 4(R3),R4
+7ca4186e|	plan9	MOVWZU (R3)(R4),R5
+ac830002|	plan9	MOVHU 2(R3),R4
+7ca41aee|	plan9	MOVHU (R3)(R4),R5
+a4830002|	plan9	MOVHZU 2(R3),R4
+7ca41a6e|	plan9	MOVHZU (R3)(R4),R5
+8c830001|	plan9	MOVBZU 1(R3),R4
+7ca418ee|	plan9	MOVBZU (R3)(R4),R5
+f8830008|	plan9	MOVD R4,8(R3)
+7ca4192a|	plan9	MOVD R5,(R3)(R4)
+90830004|	plan9	MOVW R4,4(R3)
+7ca4192e|	plan9	MOVW R5,(R3)(R4)
+b0830002|	plan9	MOVH R4,2(R3)
+7ca41b2e|	plan9	MOVH R5,(R3)(R4)
+98830001|	plan9	MOVB R4,1(R3)
+7ca419ae|	plan9	MOVB R5,(R3)(R4)
+7ca41d28|	plan9	MOVDBR R5,(R3)(R4)
+7ca41d2c|	plan9	MOVWBR R5,(R3)(R4)
+7ca41f2c|	plan9	MOVHBR R5,(R3)(R4)
+f8830009|	plan9	MOVDU R4,8(R3)
+7ca4196a|	plan9	MOVDU R5,(R3)(R4)
+94830004|	plan9	MOVWU R4,4(R3)
+7ca4196e|	plan9	MOVWU R5,(R3)(R4)
+b4830002|	plan9	MOVHU R4,2(R3)
+7ca41b6e|	plan9	MOVHU R5,(R3)(R4)
+9c830001|	plan9	MOVBU R4,1(R3)
+7ca419ee|	plan9	MOVBU R5,(R3)(R4)
+7c232040|	plan9	CMPU R3,R4
+7c032000|	plan9	CMPW R3,R4
+7c032040|	plan9	CMPWU R3,R4
+7ca41a14|	plan9	ADD R3,R4,R5
+7ca41814|	plan9	ADDC R3,R4,R5
+7ca41815|	plan9	ADDCCC R3,R4,R5
+7c851838|	plan9	AND R3,R4,R5
+7c851878|	plan9	ANDN R3,R4,R5
+7c851839|	plan9	ANDCC R3,R4,R5
+7c851b78|	plan9	OR R3,R4,R5
+7c851b38|	plan9	ORN R3,R4,R5
+7c851b79|	plan9	ORCC R3,R4,R5
+7c851a78|	plan9	XOR R3,R4,R5
+7c851a79|	plan9	XORCC R3,R4,R5
+7c851bb8|	plan9	NAND R3,R4,R5
+7c851bb9|	plan9	NANDCC R3,R4,R5
+7c851a38|	plan9	EQV R3,R4,R5
+7c851a39|	plan9	EQVCC R3,R4,R5
+7c8518f8|	plan9	NOR R3,R4,R5
+7c8518f9|	plan9	NORCC R3,R4,R5
+7ca32050|	plan9	SUB R3,R4,R5
+7ca32010|	plan9	SUBC R3,R4,R5
+7ca419d6|	plan9	MULLW R3,R4,R5
+7ca419d7|	plan9	MULLWCC R3,R4,R5
+7ca41896|	plan9	MULHW R3,R4,R5
+7ca41816|	plan9	MULHWU R3,R4,R5
+7ca421d2|	plan9	MULLD R4,R4,R5
+7ca419d3|	plan9	MULLDCC R3,R4,R5
+7ca41892|	plan9	MULHD R3,R4,R5
+7ca41893|	plan9	MULHDCC R3,R4,R5
+7ca41dd6|	plan9	MULLWV R3,R4,R5
+7ca41dd7|	plan9	MULLWVCC R3,R4,R5
+7ca41817|	plan9	MULHWUCC R3,R4,R5
+7ca41dd2|	plan9	MULLDV R3,R4,R5
+7ca41dd3|	plan9	MULLDVCC R3,R4,R5
+7ca41bd2|	plan9	DIVD R3,R4,R5
+7ca41bd3|	plan9	DIVDCC R3,R4,R5
+7ca41b92|	plan9	DIVDU R3,R4,R5
+7ca41fd2|	plan9	DIVDV R3,R4,R5
+7ca41b93|	plan9	DIVDUCC R3,R4,R5
+7ca41fd3|	plan9	DIVDVCC R3,R4,R5
+7ca41f92|	plan9	DIVDUV R3,R4,R5
+7ca41f93|	plan9	DIVDUVCC R3,R4,R5
+7ca41b52|	plan9	DIVDE R3,R4,R5
+7ca41b53|	plan9	DIVDECC R3,R4,R5
+7ca41b12|	plan9	DIVDEU R3,R4,R5
+7ca41b13|	plan9	DIVDEUCC R3,R4,R5
+7ca41a12|	plan9	MODUD R3,R4,R5
+7ca41a16|	plan9	MODUW R3,R4,R5
+7ca41e12|	plan9	MODSD R3,R4,R5
+7ca41e16|	plan9	MODSW R3,R4,R5
+7c851830|	plan9	SLW R3,R4,R5
+7c851836|	plan9	SLD R3,R4,R5
+7c851c30|	plan9	SRW R3,R4,R5
+7c851e30|	plan9	SRAW R3,R4,R5
+7c851c36|	plan9	SRD R3,R4,R5
+7c851e34|	plan9	SRAD R3,R4,R5
+7c6400f4|	plan9	POPCNTB R3,R4
+7c6402f4|	plan9	POPCNTW R3,R4
+7c6403f4|	plan9	POPCNTD R3,R4
+7c23270d|	plan9	PASTECC R3,R4
+7c23260c|	plan9	COPY R3,R4
+7ca01868|	plan9	LBAR (R3),R5
+7ca018e8|	plan9	LHAR (R3),R5
+7ca01828|	plan9	LWAR (R3),R5
+7ca018a8|	plan9	LDAR (R3),R5
+7c65256d|	plan9	STBCCC R3,(R4)(R5)
+7c65212d|	plan9	STWCCC R3,(R4)(R5)
+7c6521ad|	plan9	STDCCC R3,(R4)(R5)
+7c0004ac|	plan9	HWSYNC
+4c00012c|	plan9	ISYNC
+7c2004ac|	plan9	LWSYNC
+7c041bac|	plan9	DCBI (R3)(R4)
+7c04186c|	plan9	DCBST (R3)(R4)
+7c041fec|	plan9	DCBZ (R3)(R4)
+7c041a2c|	plan9	DCBT (R3)(R4)
+7c041fac|	plan9	ICBI (R3)(R4)
+c8230008|	plan9	FMOVD 8(R3),F1
+7c241cae|	plan9	FMOVD (R3)(R4),F1
+cc230008|	plan9	FMOVDU 8(R3),F1
+7c241cee|	plan9	FMOVDU (R3)(R4),F1
+c0230004|	plan9	FMOVS 4(R3),F1
+7c241c2e|	plan9	FMOVS (R3)(R4),F1
+c4230004|	plan9	FMOVSU 4(R3),F1
+7c241c6e|	plan9	FMOVSU (R3)(R4),F1
+d8230008|	plan9	FMOVD F1,8(R3)
+7c241dae|	plan9	FMOVD F1,(R3)(R4)
+dc230008|	plan9	FMOVDU F1,8(R3)
+7c241dee|	plan9	FMOVDU F1,(R3)(R4)
+d0230004|	plan9	FMOVS F1,4(R3)
+7c241d2e|	plan9	FMOVS F1,(R3)(R4)
+d4230004|	plan9	FMOVSU F1,4(R3)
+7c241d6e|	plan9	FMOVSU F1,(R3)(R4)
+fc62082a|	plan9	FADD F1,F2,F3
+fc62082b|	plan9	FADDCC F1,F2,F3
+ec62082a|	plan9	FADDS F1,F2,F3
+ec62082b|	plan9	FADDSCC F1,F2,F3
+fc620828|	plan9	FSUB F1,F2,F3
+fc620829|	plan9	FSUBCC F1,F2,F3
+ec620828|	plan9	FSUBS F1,F2,F3
+fc620829|	plan9	FSUBCC F1,F2,F3
+fc620072|	plan9	FMUL F1,F2,F3
+fc620073|	plan9	FMULCC F1,F2,F3
+ec620072|	plan9	FMULS F1,F2,F3
+ec620073|	plan9	FMULSCC F1,F2,F3
+fc620824|	plan9	FDIV F1,F2,F3
+fc620825|	plan9	FDIVCC F1,F2,F3
+ec620824|	plan9	FDIVS F1,F2,F3
+ec620825|	plan9	FDIVSCC F1,F2,F3
+fc8110fa|	plan9	FMADD F1,F2,F3,F4
+fc8110fb|	plan9	FMADDCC F1,F2,F3,F4
+ec8110fa|	plan9	FMADDS F1,F2,F3,F4
+ec8110fb|	plan9	FMADDSCC F1,F2,F3,F4
+fc8110f8|	plan9	FMSUB F1,F2,F3,F4
+fc8110f9|	plan9	FMSUBCC F1,F2,F3,F4
+ec8110f8|	plan9	FMSUBS F1,F2,F3,F4
+ec8110f9|	plan9	FMSUBSCC F1,F2,F3,F4
+fc8110fe|	plan9	FNMADD F1,F2,F3,F4
+fc8110ff|	plan9	FNMADDCC F1,F2,F3,F4
+ec8110fe|	plan9	FNMADDS F1,F2,F3,F4
+ec8110ff|	plan9	FNMADDSCC F1,F2,F3,F4
+fc8110fc|	plan9	FNMSUB F1,F2,F3,F4
+fc8110fd|	plan9	FNMSUBCC F1,F2,F3,F4
+ec8110fc|	plan9	FNMSUBS F1,F2,F3,F4
+ec8110fd|	plan9	FNMSUBSCC F1,F2,F3,F4
+fc8110ee|	plan9	FSEL F1,F2,F3,F4
+fc8110ef|	plan9	FSELCC F1,F2,F3,F4
+fc400a10|	plan9	FABS F1,F2
+fc400a11|	plan9	FABSCC F1,F2
+fc400850|	plan9	FNEG F1,F2
+fc400a11|	plan9	FABSCC F1,F2
+fc400818|	plan9	FRSP F1,F2
+fc400819|	plan9	FRSPCC F1,F2
+fc40081c|	plan9	FCTIW F1,F2
+fc40081d|	plan9	FCTIWCC F1,F2
+fc40081e|	plan9	FCTIWZ F1,F2
+fc40081f|	plan9	FCTIWZCC F1,F2
+fc400e5c|	plan9	FCTID F1,F2
+fc400e5d|	plan9	FCTIDCC F1,F2
+fc400e5e|	plan9	FCTIDZ F1,F2
+fc400e5f|	plan9	FCTIDZCC F1,F2
+fc400e9c|	plan9	FCFID F1,F2
+fc400e9d|	plan9	FCFIDCC F1,F2
+fc400f9c|	plan9	FCFIDU F1,F2
+fc400f9d|	plan9	FCFIDUCC F1,F2
+ec400e9c|	plan9	FCFIDS F1,F2
+ec400e9d|	plan9	FCFIDSCC F1,F2
+ec400830|	plan9	FRES F1,F2
+ec400831|	plan9	FRESCC F1,F2
+fc400bd0|	plan9	FRIM F1,F2
+fc400bd1|	plan9	FRIMCC F1,F2
+fc400b90|	plan9	FRIP F1,F2
+fc400b91|	plan9	FRIPCC F1,F2
+fc400b50|	plan9	FRIZ F1,F2
+fc400b51|	plan9	FRIZCC F1,F2
+fc400b10|	plan9	FRIN F1,F2
+fc400b11|	plan9	FRINCC F1,F2
+fc400834|	plan9	FRSQRTE F1,F2
+fc400835|	plan9	FRSQRTECC F1,F2
+fc40082c|	plan9	FSQRT F1,F2
+fc40082d|	plan9	FSQRTCC F1,F2
+ec40082c|	plan9	FSQRTS F1,F2
+ec40082d|	plan9	FSQRTSCC F1,F2
+fc011040|	plan9	FCMPO F1,F2
+fc011000|	plan9	FCMPU F1,F2
+7c2418ce|	plan9	LVX (R3)(R4),V1
+7c241ace|	plan9	LVXL (R3)(R4),V1
+7c24180c|	plan9	LVSL (R3)(R4),V1
+7c24184c|	plan9	LVSR (R3)(R4),V1
+7c24180e|	plan9	LVEBX (R3)(R4),V1
+7c24184e|	plan9	LVEHX (R3)(R4),V1
+7c24188e|	plan9	LVEWX (R3)(R4),V1
+7c2419ce|	plan9	STVX V1,(R3)(R4)
+7c241bce|	plan9	STVXL V1,(R3)(R4)
+7c24190e|	plan9	STVEBX V1,(R3)(R4)
+7c24194e|	plan9	STVEHX V1,(R3)(R4)
+7c24198e|	plan9	STVEWX V1,(R3)(R4)
+10611404|	plan9	VAND V1,V2,V3
+10611444|	plan9	VANDC V1,V2,V3
+10611584|	plan9	VNAND V1,V2,V3
+10611484|	plan9	VOR V1,V2,V3
+10611544|	plan9	VORC V1,V2,V3
+106114c4|	plan9	VXOR V1,V2,V3
+10611504|	plan9	VNOR V1,V2,V3
+10611684|	plan9	VEQV V1,V2,V3
+10611000|	plan9	VADDUBM V1,V2,V3
+10611040|	plan9	VADDUHM V1,V2,V3
+10611080|	plan9	VADDUWM V1,V2,V3
+106110c0|	plan9	VADDUDM V1,V2,V3
+10611100|	plan9	VADDUQM V1,V2,V3
+10611140|	plan9	VADDCUQ V1,V2,V3
+10611180|	plan9	VADDCUW V1,V2,V3
+10611200|	plan9	VADDUBS V1,V2,V3
+10611240|	plan9	VADDUHS V1,V2,V3
+10611280|	plan9	VADDUWS V1,V2,V3
+10611400|	plan9	VSUBUBM V1,V2,V3
+10611440|	plan9	VSUBUHM V1,V2,V3
+10611480|	plan9	VSUBUWM V1,V2,V3
+106114c0|	plan9	VSUBUDM V1,V2,V3
+10611500|	plan9	VSUBUQM V1,V2,V3
+10611540|	plan9	VSUBCUQ V1,V2,V3
+10611580|	plan9	VSUBCUW V1,V2,V3
+10611600|	plan9	VSUBUBS V1,V2,V3
+10611640|	plan9	VSUBUHS V1,V2,V3
+10611680|	plan9	VSUBUWS V1,V2,V3
+10611700|	plan9	VSUBSBS V1,V2,V3
+10611740|	plan9	VSUBSHS V1,V2,V3
+10611780|	plan9	VSUBSWS V1,V2,V3
+108110fe|	plan9	VSUBEUQM V1,V2,V3,V4
+108110ff|	plan9	VSUBECUQ V1,V2,V3,V4
+10611308|	plan9	VMULESB V1,V2,V3
+10611108|	plan9	VMULOSB V1,V2,V3
+10611208|	plan9	VMULEUB V1,V2,V3
+10611008|	plan9	VMULOUB V1,V2,V3
+10611348|	plan9	VMULESH V1,V2,V3
+10611148|	plan9	VMULOSH V1,V2,V3
+10611248|	plan9	VMULEUH V1,V2,V3
+10611048|	plan9	VMULOUH V1,V2,V3
+10611348|	plan9	VMULESH V1,V2,V3
+10611188|	plan9	VMULOSW V1,V2,V3
+10611288|	plan9	VMULEUW V1,V2,V3
+10611088|	plan9	VMULOUW V1,V2,V3
+10611089|	plan9	VMULUWM V1,V2,V3
+10611408|	plan9	VPMSUMB V1,V2,V3
+10611448|	plan9	VPMSUMH V1,V2,V3
+10611488|	plan9	VPMSUMW V1,V2,V3
+106114c8|	plan9	VPMSUMD V1,V2,V3
+108110e3|	plan9	VMSUMUDM V1,V2,V3,V4
+10611004|	plan9	VRLB V1,V2,V3
+10611044|	plan9	VRLH V1,V2,V3
+10611084|	plan9	VRLW V1,V2,V3
+106110c4|	plan9	VRLD V1,V2,V3
+10611104|	plan9	VSLB V1,V2,V3
+10611144|	plan9	VSLH V1,V2,V3
+10611184|	plan9	VSLW V1,V2,V3
+106111c4|	plan9	VSL V1,V2,V3
+1061140c|	plan9	VSLO V1,V2,V3
+10611204|	plan9	VSRB V1,V2,V3
+10611244|	plan9	VSRH V1,V2,V3
+10611284|	plan9	VSRW V1,V2,V3
+106112c4|	plan9	VSR V1,V2,V3
+1061144c|	plan9	VSRO V1,V2,V3
+106115c4|	plan9	VSLD V1,V2,V3
+10611304|	plan9	VSRAB V1,V2,V3
+10611344|	plan9	VSRAH V1,V2,V3
+10611384|	plan9	VSRAW V1,V2,V3
+106113c4|	plan9	VSRAD V1,V2,V3
+10400f02|	plan9	VCLZB V1,V2
+10400f42|	plan9	VCLZH V1,V2
+10400f82|	plan9	VCLZW V1,V2
+10400fc2|	plan9	VCLZD V1,V2
+10400f03|	plan9	VPOPCNTB V1,V2
+10400f43|	plan9	VPOPCNTH V1,V2
+10400f83|	plan9	VPOPCNTW V1,V2
+10400fc3|	plan9	VPOPCNTD V1,V2
+10611006|	plan9	VCMPEQUB V1,V2,V3
+10611406|	plan9	VCMPEQUBCC V1,V2,V3
+10611046|	plan9	VCMPEQUH V1,V2,V3
+10611446|	plan9	VCMPEQUHCC V1,V2,V3
+10611086|	plan9	VCMPEQUW V1,V2,V3
+10611486|	plan9	VCMPEQUWCC V1,V2,V3
+106110c7|	plan9	VCMPEQUD V1,V2,V3
+106114c7|	plan9	VCMPEQUDCC V1,V2,V3
+10611206|	plan9	VCMPGTUB V1,V2,V3
+10611606|	plan9	VCMPGTUBCC V1,V2,V3
+10611246|	plan9	VCMPGTUH V1,V2,V3
+10611646|	plan9	VCMPGTUHCC V1,V2,V3
+10611286|	plan9	VCMPGTUW V1,V2,V3
+10611686|	plan9	VCMPGTUWCC V1,V2,V3
+106112c7|	plan9	VCMPGTUD V1,V2,V3
+106116c7|	plan9	VCMPGTUDCC V1,V2,V3
+10611306|	plan9	VCMPGTSB V1,V2,V3
+10611706|	plan9	VCMPGTSBCC V1,V2,V3
+10611346|	plan9	VCMPGTSH V1,V2,V3
+10611746|	plan9	VCMPGTSHCC V1,V2,V3
+10611386|	plan9	VCMPGTSW V1,V2,V3
+10611786|	plan9	VCMPGTSWCC V1,V2,V3
+106113c7|	plan9	VCMPGTSD V1,V2,V3
+106117c7|	plan9	VCMPGTSDCC V1,V2,V3
+10611107|	plan9	VCMPNEZB V1,V2,V3
+10611507|	plan9	VCMPNEZBCC V1,V2,V3
+10611007|	plan9	VCMPNEB V1,V2,V3
+10611407|	plan9	VCMPNEBCC V1,V2,V3
+10611047|	plan9	VCMPNEH V1,V2,V3
+10611447|	plan9	VCMPNEHCC V1,V2,V3
+10611087|	plan9	VCMPNEW V1,V2,V3
+10611487|	plan9	VCMPNEWCC V1,V2,V3
+108110eb|	plan9	VPERM V1,V2,V3,V4
+108110fb|	plan9	VPERMR V1,V2,V3,V4
+108110ed|	plan9	VPERMXOR V1,V2,V3,V4
+1061154c|	plan9	VBPERMQ V1,V2,V3
+106115cc|	plan9	VBPERMD V1,V2,V3
+108110ea|	plan9	VSEL V1,V2,V3,V4
+10611508|	plan9	VCIPHER V1,V2,V3
+10611509|	plan9	VCIPHERLAST V1,V2,V3
+10611548|	plan9	VNCIPHER V1,V2,V3
+10611549|	plan9	VNCIPHERLAST V1,V2,V3
+104105c8|	plan9	VSBOX V1,V2
+7c241e98|	plan9	LXVD2X (R3)(R4),VS1
+f4230011|	plan9	LXV 16(R3),VS1
+7c23221a|	plan9	LXVL R3,R4,VS1
+7c23225a|	plan9	LXVLL R3,R4,VS1
+7c241c98|	plan9	LXSDX (R3)(R4),VS1
+7c241f98|	plan9	STXVD2X VS1,(R3)(R4)
+f4230015|	plan9	STXV VS1,16(R3)
+7c23231a|	plan9	STXVL VS1,R3,R4
+7c23235a|	plan9	STXVLL VS1,R3,R4
+7c241d98|	plan9	STXSDX VS1,(R3)(R4)
+7c241898|	plan9	LXSIWAX (R3)(R4),VS1
+7c241918|	plan9	STXSIWX VS1,(R3)(R4)
+7c230066|	plan9	MFVSRD VS1,R3
+7c230166|	plan9	MTVSRD R3,VS1
+f0611410|	plan9	XXLAND VS1,VS2,VS3
+f0611490|	plan9	XXLOR VS1,VS2,VS3
+f0611550|	plan9	XXLORC VS1,VS2,VS3
+f06114d0|	plan9	XXLXOR VS1,VS2,VS3
+f08110f0|	plan9	XXSEL VS1,VS2,VS3,VS4
+f0611090|	plan9	XXMRGHW VS1,VS2,VS3
+f0410a90|	plan9	XXSPLTW VS1,$1,VS2
+f06110d0|	plan9	XXPERM VS1,VS2,VS3
+f0611110|	plan9	XXSLDWI VS1,VS2,$1,VS3
+f0400c24|	plan9	XSCVDPSP VS1,VS2
+f0400e24|	plan9	XVCVDPSP VS1,VS2
+f0400de0|	plan9	XSCVSXDDP VS1,VS2
+f0400f60|	plan9	XVCVDPSXDS VS1,VS2
+f0400fe0|	plan9	XVCVSXDDP VS1,VS2
+7c6803a6|	plan9	MOVD R3,LR
+7c6903a6|	plan9	MOVD R3,CTR
+7c6802a6|	plan9	MOVD LR,R3
+7c6902a6|	plan9	MOVD CTR,R3
+4c8c0000|	plan9	MOVFL CR3,CR1
+7c6803a6|	gnu	mtlr r3
+7c6802a6|	gnu	mflr r3
+7c6903a6|	gnu	mtctr r3
+7c6902a6|	gnu	mfctr r3
+7c6c42a6|	gnu	mftb r3
+7c8202a6|	gnu	mfspr r4,2
+e8830008|	gnu	ld r4,8(r3)
+7ca4182a|	gnu	ldx r5,r4,r3
+e8830006|	gnu	lwa r4,4(r3)
+7ca41aaa|	gnu	lwax r5,r4,r3
+80830004|	gnu	lwz r4,4(r3)
+7ca4182e|	gnu	lwzx r5,r4,r3
+a8830004|	gnu	lha r4,4(r3)
+7ca41aae|	gnu	lhax r5,r4,r3
+a0830002|	gnu	lhz r4,2(r3)
+7ca41a2e|	gnu	lhzx r5,r4,r3
+7ca418ae|	gnu	lbzx r5,r4,r3
+7ca41c28|	gnu	ldbrx r5,r4,r3
+7ca41c2c|	gnu	lwbrx r5,r4,r3
+7ca41e2c|	gnu	lhbrx r5,r4,r3
+e8830009|	gnu	ldu r4,8(r3)
+7ca4186a|	gnu	ldux r5,r4,r3
+7ca41aea|	gnu	lwaux r5,r4,r3
+84830004|	gnu	lwzu r4,4(r3)
+7ca4186e|	gnu	lwzux r5,r4,r3
+ac830002|	gnu	lhau r4,2(r3)
+7ca41aee|	gnu	lhaux r5,r4,r3
+a4830002|	gnu	lhzu r4,2(r3)
+7ca41a6e|	gnu	lhzux r5,r4,r3
+8c830001|	gnu	lbzu r4,1(r3)
+7ca418ee|	gnu	lbzux r5,r4,r3
+f8830008|	gnu	std r4,8(r3)
+7ca4192a|	gnu	stdx r5,r4,r3
+90830004|	gnu	stw r4,4(r3)
+7ca4192e|	gnu	stwx r5,r4,r3
+b0830002|	gnu	sth r4,2(r3)
+7ca41b2e|	gnu	sthx r5,r4,r3
+98830001|	gnu	stb r4,1(r3)
+7ca419ae|	gnu	stbx r5,r4,r3
+7ca41d28|	gnu	stdbrx r5,r4,r3
+7ca41d2c|	gnu	stwbrx r5,r4,r3
+7ca41f2c|	gnu	sthbrx r5,r4,r3
+f8830009|	gnu	stdu r4,8(r3)
+7ca4196a|	gnu	stdux r5,r4,r3
+94830004|	gnu	stwu r4,4(r3)
+7ca4196e|	gnu	stwux r5,r4,r3
+b4830002|	gnu	sthu r4,2(r3)
+7ca41b6e|	gnu	sthux r5,r4,r3
+9c830001|	gnu	stbu r4,1(r3)
+7ca419ee|	gnu	stbux r5,r4,r3
+7c232040|	gnu	cmpld r3,r4
+7c032000|	gnu	cmpw r3,r4
+7c032040|	gnu	cmplw r3,r4
+7ca41a14|	gnu	add r5,r4,r3
+7ca41814|	gnu	addc r5,r4,r3
+7ca41815|	gnu	addc. r5,r4,r3
+7c851838|	gnu	and r5,r4,r3
+7c851878|	gnu	andc r5,r4,r3
+7c851839|	gnu	and. r5,r4,r3
+7c851b78|	gnu	or r5,r4,r3
+7c851b38|	gnu	orc r5,r4,r3
+7c851b79|	gnu	or. r5,r4,r3
+7c851a78|	gnu	xor r5,r4,r3
+7c851a79|	gnu	xor. r5,r4,r3
+7c851bb8|	gnu	nand r5,r4,r3
+7c851bb9|	gnu	nand. r5,r4,r3
+7c851a38|	gnu	eqv r5,r4,r3
+7c851a39|	gnu	eqv. r5,r4,r3
+7c8518f8|	gnu	nor r5,r4,r3
+7c8518f9|	gnu	nor. r5,r4,r3
+7ca32050|	gnu	subf r5,r3,r4
+7ca32010|	gnu	subfc r5,r3,r4
+7ca419d6|	gnu	mullw r5,r4,r3
+7ca419d7|	gnu	mullw. r5,r4,r3
+7ca41896|	gnu	mulhw r5,r4,r3
+7ca41816|	gnu	mulhwu r5,r4,r3
+7ca421d2|	gnu	mulld r5,r4,r4
+7ca419d3|	gnu	mulld. r5,r4,r3
+7ca41892|	gnu	mulhd r5,r4,r3
+7ca41893|	gnu	mulhd. r5,r4,r3
+7ca41dd6|	gnu	mullwo r5,r4,r3
+7ca41dd7|	gnu	mullwo. r5,r4,r3
+7ca41817|	gnu	mulhwu. r5,r4,r3
+7ca41dd2|	gnu	mulldo r5,r4,r3
+7ca41dd3|	gnu	mulldo. r5,r4,r3
+7ca41bd2|	gnu	divd r5,r4,r3
+7ca41bd3|	gnu	divd. r5,r4,r3
+7ca41b92|	gnu	divdu r5,r4,r3
+7ca41fd2|	gnu	divdo r5,r4,r3
+7ca41b93|	gnu	divdu. r5,r4,r3
+7ca41fd3|	gnu	divdo. r5,r4,r3
+7ca41f92|	gnu	divduo r5,r4,r3
+7ca41f93|	gnu	divduo. r5,r4,r3
+7ca41b52|	gnu	divde r5,r4,r3
+7ca41b53|	gnu	divde. r5,r4,r3
+7ca41b12|	gnu	divdeu r5,r4,r3
+7ca41b13|	gnu	divdeu. r5,r4,r3
+7ca41a12|	gnu	modud r5,r4,r3
+7ca41a16|	gnu	moduw r5,r4,r3
+7ca41e12|	gnu	modsd r5,r4,r3
+7ca41e16|	gnu	modsw r5,r4,r3
+7c851830|	gnu	slw r5,r4,r3
+7c851836|	gnu	sld r5,r4,r3
+7c851c30|	gnu	srw r5,r4,r3
+7c851e30|	gnu	sraw r5,r4,r3
+7c851c36|	gnu	srd r5,r4,r3
+7c851e34|	gnu	srad r5,r4,r3
+7c6400f4|	gnu	popcntb r4,r3
+7c6402f4|	gnu	popcntw r4,r3
+7c6403f4|	gnu	popcntd r4,r3
+7c23270d|	gnu	paste. r3,r4
+7c23260c|	gnu	copy r3,r4
+7ca01868|	gnu	lbarx r5,0,r3
+7ca018e8|	gnu	lharx r5,0,r3
+7ca01828|	gnu	lwarx r5,0,r3
+7ca018a8|	gnu	ldarx r5,0,r3
+7c65256d|	gnu	stbcx. r3,r5,r4
+7c65212d|	gnu	stwcx. r3,r5,r4
+7c6521ad|	gnu	stdcx. r3,r5,r4
+4c00012c|	gnu	isync
+7c0004ac|	gnu	hwsync
+7c2004ac|	gnu	lwsync
+7c041bac|	gnu	dcbi r4,r3
+7c04186c|	gnu	dcbst r4,r3
+7c041fec|	gnu	dcbz r4,r3
+7c041a2c|	gnu	dcbt r4,r3,0
+7c041fac|	gnu	icbi r4,r3
+c8230008|	gnu	lfd f1,8(r3)
+7c241cae|	gnu	lfdx f1,r4,r3
+cc230008|	gnu	lfdu f1,8(r3)
+7c241cee|	gnu	lfdux f1,r4,r3
+c0230004|	gnu	lfs f1,4(r3)
+7c241c2e|	gnu	lfsx f1,r4,r3
+c4230004|	gnu	lfsu f1,4(r3)
+7c241c6e|	gnu	lfsux f1,r4,r3
+d8230008|	gnu	stfd f1,8(r3)
+7c241dae|	gnu	stfdx f1,r4,r3
+dc230008|	gnu	stfdu f1,8(r3)
+7c241dee|	gnu	stfdux f1,r4,r3
+d0230004|	gnu	stfs f1,4(r3)
+7c241d2e|	gnu	stfsx f1,r4,r3
+d4230004|	gnu	stfsu f1,4(r3)
+7c241d6e|	gnu	stfsux f1,r4,r3
+fc62082a|	gnu	fadd f3,f2,f1
+fc62082b|	gnu	fadd. f3,f2,f1
+ec62082a|	gnu	fadds f3,f2,f1
+ec62082b|	gnu	fadds. f3,f2,f1
+fc620828|	gnu	fsub f3,f2,f1
+fc620829|	gnu	fsub. f3,f2,f1
+ec620828|	gnu	fsubs f3,f2,f1
+fc620829|	gnu	fsub. f3,f2,f1
+fc620072|	gnu	fmul f3,f2,f1
+fc620073|	gnu	fmul. f3,f2,f1
+ec620072|	gnu	fmuls f3,f2,f1
+ec620073|	gnu	fmuls. f3,f2,f1
+fc620824|	gnu	fdiv f3,f2,f1
+fc620825|	gnu	fdiv. f3,f2,f1
+ec620824|	gnu	fdivs f3,f2,f1
+ec620825|	gnu	fdivs. f3,f2,f1
+fc8110fa|	gnu	fmadd f4,f1,f3,f2
+fc8110fb|	gnu	fmadd. f4,f1,f3,f2
+ec8110fa|	gnu	fmadds f4,f1,f3,f2
+ec8110fb|	gnu	fmadds. f4,f1,f3,f2
+fc8110f8|	gnu	fmsub f4,f1,f3,f2
+fc8110f9|	gnu	fmsub. f4,f1,f3,f2
+ec8110f8|	gnu	fmsubs f4,f1,f3,f2
+ec8110f9|	gnu	fmsubs. f4,f1,f3,f2
+fc8110fe|	gnu	fnmadd f4,f1,f3,f2
+fc8110ff|	gnu	fnmadd. f4,f1,f3,f2
+ec8110fe|	gnu	fnmadds f4,f1,f3,f2
+ec8110ff|	gnu	fnmadds. f4,f1,f3,f2
+fc8110fc|	gnu	fnmsub f4,f1,f3,f2
+fc8110fd|	gnu	fnmsub. f4,f1,f3,f2
+ec8110fc|	gnu	fnmsubs f4,f1,f3,f2
+ec8110fd|	gnu	fnmsubs. f4,f1,f3,f2
+fc8110ee|	gnu	fsel f4,f1,f3,f2
+fc8110ef|	gnu	fsel. f4,f1,f3,f2
+fc400a10|	gnu	fabs f2,f1
+fc400a11|	gnu	fabs. f2,f1
+fc400850|	gnu	fneg f2,f1
+fc400a11|	gnu	fabs. f2,f1
+fc400818|	gnu	frsp f2,f1
+fc400819|	gnu	frsp. f2,f1
+fc40081c|	gnu	fctiw f2,f1
+fc40081d|	gnu	fctiw. f2,f1
+fc40081e|	gnu	fctiwz f2,f1
+fc40081f|	gnu	fctiwz. f2,f1
+fc400e5c|	gnu	fctid f2,f1
+fc400e5d|	gnu	fctid. f2,f1
+fc400e5e|	gnu	fctidz f2,f1
+fc400e5f|	gnu	fctidz. f2,f1
+fc400e9c|	gnu	fcfid f2,f1
+fc400e9d|	gnu	fcfid. f2,f1
+fc400f9c|	gnu	fcfidu f2,f1
+fc400f9d|	gnu	fcfidu. f2,f1
+ec400e9c|	gnu	fcfids f2,f1
+ec400e9d|	gnu	fcfids. f2,f1
+ec400830|	gnu	fres f2,f1
+ec400831|	gnu	fres. f2,f1
+fc400bd0|	gnu	frim f2,f1
+fc400bd1|	gnu	frim. f2,f1
+fc400b90|	gnu	frip f2,f1
+fc400b91|	gnu	frip. f2,f1
+fc400b50|	gnu	friz f2,f1
+fc400b51|	gnu	friz. f2,f1
+fc400b10|	gnu	frin f2,f1
+fc400b11|	gnu	frin. f2,f1
+fc400834|	gnu	frsqrte f2,f1
+fc400835|	gnu	frsqrte. f2,f1
+fc40082c|	gnu	fsqrt f2,f1
+fc40082d|	gnu	fsqrt. f2,f1
+ec40082c|	gnu	fsqrts f2,f1
+ec40082d|	gnu	fsqrts. f2,f1
+fc011040|	gnu	fcmpo cr0,f1,f2
+fc011000|	gnu	fcmpu cr0,f1,f2
+7c2418ce|	gnu	lvx v1,r4,r3
+7c241ace|	gnu	lvxl v1,r4,r3
+7c24180c|	gnu	lvsl v1,r4,r3
+7c24184c|	gnu	lvsr v1,r4,r3
+7c24180e|	gnu	lvebx v1,r4,r3
+7c24184e|	gnu	lvehx v1,r4,r3
+7c24188e|	gnu	lvewx v1,r4,r3
+7c2419ce|	gnu	stvx v1,r4,r3
+7c241bce|	gnu	stvxl v1,r4,r3
+7c24190e|	gnu	stvebx v1,r4,r3
+7c24194e|	gnu	stvehx v1,r4,r3
+7c24198e|	gnu	stvewx v1,r4,r3
+10611404|	gnu	vand v3,v1,v2
+10611444|	gnu	vandc v3,v1,v2
+10611584|	gnu	vnand v3,v1,v2
+10611484|	gnu	vor v3,v1,v2
+10611544|	gnu	vorc v3,v1,v2
+106114c4|	gnu	vxor v3,v1,v2
+10611504|	gnu	vnor v3,v1,v2
+10611684|	gnu	veqv v3,v1,v2
+10611000|	gnu	vaddubm v3,v1,v2
+10611040|	gnu	vadduhm v3,v1,v2
+10611080|	gnu	vadduwm v3,v1,v2
+106110c0|	gnu	vaddudm v3,v1,v2
+10611100|	gnu	vadduqm v3,v1,v2
+10611140|	gnu	vaddcuq v3,v1,v2
+10611180|	gnu	vaddcuw v3,v1,v2
+10611200|	gnu	vaddubs v3,v1,v2
+10611240|	gnu	vadduhs v3,v1,v2
+10611280|	gnu	vadduws v3,v1,v2
+10611400|	gnu	vsububm v3,v1,v2
+10611440|	gnu	vsubuhm v3,v1,v2
+10611480|	gnu	vsubuwm v3,v1,v2
+106114c0|	gnu	vsubudm v3,v1,v2
+10611500|	gnu	vsubuqm v3,v1,v2
+10611540|	gnu	vsubcuq v3,v1,v2
+10611580|	gnu	vsubcuw v3,v1,v2
+10611600|	gnu	vsububs v3,v1,v2
+10611640|	gnu	vsubuhs v3,v1,v2
+10611680|	gnu	vsubuws v3,v1,v2
+10611700|	gnu	vsubsbs v3,v1,v2
+10611740|	gnu	vsubshs v3,v1,v2
+10611780|	gnu	vsubsws v3,v1,v2
+108110fe|	gnu	vsubeuqm v4,v1,v2,v3
+108110ff|	gnu	vsubecuq v4,v1,v2,v3
+10611308|	gnu	vmulesb v3,v1,v2
+10611108|	gnu	vmulosb v3,v1,v2
+10611208|	gnu	vmuleub v3,v1,v2
+10611008|	gnu	vmuloub v3,v1,v2
+10611348|	gnu	vmulesh v3,v1,v2
+10611148|	gnu	vmulosh v3,v1,v2
+10611248|	gnu	vmuleuh v3,v1,v2
+10611048|	gnu	vmulouh v3,v1,v2
+10611348|	gnu	vmulesh v3,v1,v2
+10611188|	gnu	vmulosw v3,v1,v2
+10611288|	gnu	vmuleuw v3,v1,v2
+10611088|	gnu	vmulouw v3,v1,v2
+10611089|	gnu	vmuluwm v3,v1,v2
+10611408|	gnu	vpmsumb v3,v1,v2
+10611448|	gnu	vpmsumh v3,v1,v2
+10611488|	gnu	vpmsumw v3,v1,v2
+106114c8|	gnu	vpmsumd v3,v1,v2
+108110e3|	gnu	vmsumudm v4,v1,v2,v3
+10611004|	gnu	vrlb v3,v1,v2
+10611044|	gnu	vrlh v3,v1,v2
+10611084|	gnu	vrlw v3,v1,v2
+106110c4|	gnu	vrld v3,v1,v2
+10611104|	gnu	vslb v3,v1,v2
+10611144|	gnu	vslh v3,v1,v2
+10611184|	gnu	vslw v3,v1,v2
+106111c4|	gnu	vsl v3,v1,v2
+1061140c|	gnu	vslo v3,v1,v2
+10611204|	gnu	vsrb v3,v1,v2
+10611244|	gnu	vsrh v3,v1,v2
+10611284|	gnu	vsrw v3,v1,v2
+106112c4|	gnu	vsr v3,v1,v2
+1061144c|	gnu	vsro v3,v1,v2
+106115c4|	gnu	vsld v3,v1,v2
+10611304|	gnu	vsrab v3,v1,v2
+10611344|	gnu	vsrah v3,v1,v2
+10611384|	gnu	vsraw v3,v1,v2
+106113c4|	gnu	vsrad v3,v1,v2
+10400f02|	gnu	vclzb v2,v1
+10400f42|	gnu	vclzh v2,v1
+10400f82|	gnu	vclzw v2,v1
+10400fc2|	gnu	vclzd v2,v1
+10400f03|	gnu	vpopcntb v2,v1
+10400f43|	gnu	vpopcnth v2,v1
+10400f83|	gnu	vpopcntw v2,v1
+10400fc3|	gnu	vpopcntd v2,v1
+10611006|	gnu	vcmpequb v3,v1,v2
+10611406|	gnu	vcmpequb. v3,v1,v2
+10611046|	gnu	vcmpequh v3,v1,v2
+10611446|	gnu	vcmpequh. v3,v1,v2
+10611086|	gnu	vcmpequw v3,v1,v2
+10611486|	gnu	vcmpequw. v3,v1,v2
+106110c7|	gnu	vcmpequd v3,v1,v2
+106114c7|	gnu	vcmpequd. v3,v1,v2
+10611206|	gnu	vcmpgtub v3,v1,v2
+10611606|	gnu	vcmpgtub. v3,v1,v2
+10611246|	gnu	vcmpgtuh v3,v1,v2
+10611646|	gnu	vcmpgtuh. v3,v1,v2
+10611286|	gnu	vcmpgtuw v3,v1,v2
+10611686|	gnu	vcmpgtuw. v3,v1,v2
+106112c7|	gnu	vcmpgtud v3,v1,v2
+106116c7|	gnu	vcmpgtud. v3,v1,v2
+10611306|	gnu	vcmpgtsb v3,v1,v2
+10611706|	gnu	vcmpgtsb. v3,v1,v2
+10611346|	gnu	vcmpgtsh v3,v1,v2
+10611746|	gnu	vcmpgtsh. v3,v1,v2
+10611386|	gnu	vcmpgtsw v3,v1,v2
+10611786|	gnu	vcmpgtsw. v3,v1,v2
+106113c7|	gnu	vcmpgtsd v3,v1,v2
+106117c7|	gnu	vcmpgtsd. v3,v1,v2
+10611107|	gnu	vcmpnezb v3,v1,v2
+10611507|	gnu	vcmpnezb. v3,v1,v2
+10611007|	gnu	vcmpneb v3,v1,v2
+10611407|	gnu	vcmpneb. v3,v1,v2
+10611047|	gnu	vcmpneh v3,v1,v2
+10611447|	gnu	vcmpneh. v3,v1,v2
+10611087|	gnu	vcmpnew v3,v1,v2
+10611487|	gnu	vcmpnew. v3,v1,v2
+108110eb|	gnu	vperm v4,v1,v2,v3
+108110fb|	gnu	vpermr v4,v1,v2,v3
+108110ed|	gnu	vpermxor v4,v1,v2,v3
+1061154c|	gnu	vbpermq v3,v1,v2
+106115cc|	gnu	vbpermd v3,v1,v2
+108110ea|	gnu	vsel v4,v1,v2,v3
+10611508|	gnu	vcipher v3,v1,v2
+10611509|	gnu	vcipherlast v3,v1,v2
+10611548|	gnu	vncipher v3,v1,v2
+10611549|	gnu	vncipherlast v3,v1,v2
+104105c8|	gnu	vsbox v2,v1
+7c241e98|	gnu	lxvd2x vs1,r4,r3
+f4230011|	gnu	lxv vs1,16(r3)
+7c23221a|	gnu	lxvl vs1,r3,r4
+7c23225a|	gnu	lxvll vs1,r3,r4
+7c241c98|	gnu	lxsdx vs1,r4,r3
+7c241f98|	gnu	stxvd2x vs1,r4,r3
+f4230015|	gnu	stxv vs1,16(r3)
+7c23231a|	gnu	stxvl vs1,r3,r4
+7c23235a|	gnu	stxvll vs1,r3,r4
+7c241d98|	gnu	stxsdx vs1,r4,r3
+7c241898|	gnu	lxsiwax vs1,r4,r3
+7c241918|	gnu	stxsiwx vs1,r4,r3
+7c230066|	gnu	mfvsrd r3,vs1
+7c230166|	gnu	mtvsrd vs1,r3
+f0611410|	gnu	xxland vs3,vs1,vs2
+f0611490|	gnu	xxlor vs3,vs1,vs2
+f0611550|	gnu	xxlorc vs3,vs1,vs2
+f06114d0|	gnu	xxlxor vs3,vs1,vs2
+f08110f0|	gnu	xxsel vs4,vs1,vs2,vs3
+f0611090|	gnu	xxmrghw vs3,vs1,vs2
+f0410a90|	gnu	xxspltw vs2,vs1,1
+f06110d0|	gnu	xxperm vs3,vs1,vs2
+f0611110|	gnu	xxsldwi vs3,vs1,vs2,1
+f0400c24|	gnu	xscvdpsp vs2,vs1
+f0400e24|	gnu	xvcvdpsp vs2,vs1
+f0400de0|	gnu	xscvsxddp vs2,vs1
+f0400f60|	gnu	xvcvdpsxds vs2,vs1
+f0400fe0|	gnu	xvcvsxddp vs2,vs1
+7c6803a6|	gnu	mtlr r3
+7c6903a6|	gnu	mtctr r3
+7c6802a6|	gnu	mflr r3
+7c6902a6|	gnu	mfctr r3
+4c8c0000|	gnu	mcrf cr1,cr3