diff --git a/ppc64/pp64.csv b/ppc64/pp64.csv
index 5df22bf..3173ab8 100644
--- a/ppc64/pp64.csv
+++ b/ppc64/pp64.csv
@@ -530,15 +530,19 @@
 "Load VSX Vector Doubleword*2 Indexed XX1-form","lxvd2x XT,RA,RB","31@0|T@6|RA@11|RB@16|844@21|TX@31|",""
 "Load VSX Vector Doubleword & Splat Indexed XX1-form","lxvdsx XT,RA,RB ( 0x7C00_0298 )","31@0|T@6|RA@11|RB@16|332@21|TX@31|",""
 "Load VSX Vector Word*4 Indexed XX1-form","lxvw4x XT,RA,RB","31@0|T@6|RA@11|RB@16|780@21|TX@31|",""
+"Load VSX Vector Halfword*8 Indexed XX1-form","lxvh8x XT,RA,RB","31@0|T@6|RA@11|RB@16|812@21|TX@31|",""
+"Load VSX Vector Byte*16 Indexed XX1-form","lxvb16x XT,RA,RB","31@0|T@6|RA@11|RB@16|876@21|TX@31|",""
 "Load VSX Vector DQ-form","lxv XT,DQ(RA)","61@0|T@6|RA@11|DQ@16|TX@28|1@29|",""
 "Load VSX Vector with Length X-form","lxvl XT,RA,RB","31@0|T@6|RA@11|RB@16|269@21|TX@31|",""
 "Load VSX Vector Left-justified with Length X-form","lxvll XT,RA,RB","31@0|T@6|RA@11|RB@16|301@21|TX@31|",""
-"Load VSX Vector Indexed X-form","lxvx XT,RA,RB","31@0|T@6|RA@11|RB@16|268@21|TX@31|",""
+"Load VSX Vector Indexed X-form","lxvx XT,RA,RB","31@0|T@6|RA@11|RB@16|4@21|///@25|12@26|TX@31|",""
 "Store VSX Scalar Doubleword Indexed XX1-form","stxsdx XS,RA,RB","31@0|S@6|RA@11|RB@16|716@21|SX@31|",""
 "Store VSX Scalar as Integer Word Indexed XX1-form","stxsiwx XS,RA,RB","31@0|S@6|RA@11|RB@16|140@21|SX@31|",""
 "Store VSX Scalar Single-Precision Indexed XX1-form","stxsspx XS,RA,RB","31@0|S@6|RA@11|RB@16|652@21|SX@31|",""
 "Store VSX Vector Doubleword*2 Indexed XX1-form","stxvd2x XS,RA,RB","31@0|S@6|RA@11|RB@16|972@21|SX@31|",""
 "Store VSX Vector Word*4 Indexed XX1-form","stxvw4x XS,RA,RB","31@0|S@6|RA@11|RB@16|908@21|SX@31|",""
+"Store VSX Vector Halfword*4 Indexed XX1-form","stxvh8x XS,RA,RB","31@0|S@6|RA@11|RB@16|940@21|SX@31|",""
+"Store VSX Vector Byte*16 Indexed XX1-form","stxvb16x XS,RA,RB","31@0|S@6|RA@11|RB@16|1004@21|SX@31|",""
 "Store VSX Vector DQ-form","stxv XS,DQ(RA)","61@0|S@6|RA@11|DQ@16|SX@28|5@29|",""
 "Store VSX Vector with Length X-form","stxvl XS,RA,RB","31@0|S@6|RA@11|RB@16|397@21|SX@31|",""
 "Store VSX Vector Left-justified with Length X-form","stxvll XS,RA,RB","31@0|S@6|RA@11|RB@16|429@21|SX@31|",""
@@ -680,6 +684,9 @@
 "VSX Select XX4-form","xxsel XT,XA,XB,XC","60@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|",""
 "VSX Shift Left Double by Word Immediate XX3-form","xxsldwi XT,XA,XB,SHW","60@0|T@6|A@11|B@16|0@21|SHW@22|2@24|AX@29|BX@30|TX@31|",""
 "VSX Splat Word XX2-form","xxspltw XT,XB,UIM","60@0|T@6|///@11|UIM@14|B@16|164@21|BX@30|TX@31|",""
+"VSX Vector Byte-Reverse Doubleword XX2-form","xxbrd XT,XB","60@0|T@6|23@11|B@16|475@21|BX@30|TX@31|",""
+"VSX Vector Byte-Reverse Word XX2-form","xxbrw XT,XB","60@0|T@6|15@11|B@16|475@21|BX@30|TX@31|",""
+"VSX Vector Byte-Reverse Halfword XX2-form","xxbrh XT,XB","60@0|T@6|7@11|B@16|475@21|BX@30|TX@31|",""
 "Bit Reversed Increment EVX-form","brinc RT,RA,RB","4@0|RT@6|RA@11|RB@16|527@21|",""
 "Vector Absolute Value EVX-form","evabs RT,RA","4@0|RT@6|RA@11|///@16|520@21|",""
 "Vector Add Immediate Word EVX-form","evaddiw RT,RB,UI","4@0|RT@6|UI@11|RB@16|514@21|",""
diff --git a/ppc64/ppc64asm/plan9.go b/ppc64/ppc64asm/plan9.go
index 9cb8c8c..48a4e97 100644
--- a/ppc64/ppc64asm/plan9.go
+++ b/ppc64/ppc64asm/plan9.go
@@ -112,7 +112,7 @@
 	case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
 		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
-	case STXVX, STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
+	case STXVX, STXVD2X, STXVW4X, STXVH8X, STXVB16X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
 		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
 	case STXV:
@@ -127,7 +127,7 @@
 		}
 		return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
 
-	case LXVX, LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
+	case LXVX, LXVD2X, LXVW4X, LXVH8X, LXVB16X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
 		return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
 
 	case LXV:
@@ -332,6 +332,7 @@
 	DIVDUO:    "DIVDUV",
 	DIVDUOCC:  "DIVDUVCC",
 	ADDI:      "ADD",
+	MULLI:     "MULLD",
 	SRADI:     "SRAD",
 	SUBF:      "SUB",
 	STBCXCC:   "STBCCC",
diff --git a/ppc64/ppc64asm/tables.go b/ppc64/ppc64asm/tables.go
index 102f836..76f9635 100644
--- a/ppc64/ppc64asm/tables.go
+++ b/ppc64/ppc64asm/tables.go
@@ -1,5 +1,5 @@
 // DO NOT EDIT
-// generated by: ppc64map -fmt=decoder ../pp64.csv
+// generated by: ppc64map -fmt=decoder pp64.csv
 
 package ppc64asm
 
@@ -727,6 +727,8 @@
 	LXVD2X
 	LXVDSX
 	LXVW4X
+	LXVH8X
+	LXVB16X
 	LXV
 	LXVL
 	LXVLL
@@ -736,6 +738,8 @@
 	STXSSPX
 	STXVD2X
 	STXVW4X
+	STXVH8X
+	STXVB16X
 	STXV
 	STXVL
 	STXVLL
@@ -883,6 +887,9 @@
 	XXSEL
 	XXSLDWI
 	XXSPLTW
+	XXBRD
+	XXBRW
+	XXBRH
 	BRINC
 	EVABS
 	EVADDIW
@@ -2097,6 +2104,8 @@
 	LXVD2X:        "lxvd2x",
 	LXVDSX:        "lxvdsx",
 	LXVW4X:        "lxvw4x",
+	LXVH8X:        "lxvh8x",
+	LXVB16X:       "lxvb16x",
 	LXV:           "lxv",
 	LXVL:          "lxvl",
 	LXVLL:         "lxvll",
@@ -2106,6 +2115,8 @@
 	STXSSPX:       "stxsspx",
 	STXVD2X:       "stxvd2x",
 	STXVW4X:       "stxvw4x",
+	STXVH8X:       "stxvh8x",
+	STXVB16X:      "stxvb16x",
 	STXV:          "stxv",
 	STXVL:         "stxvl",
 	STXVLL:        "stxvll",
@@ -2253,6 +2264,9 @@
 	XXSEL:         "xxsel",
 	XXSLDWI:       "xxsldwi",
 	XXSPLTW:       "xxspltw",
+	XXBRD:         "xxbrd",
+	XXBRW:         "xxbrw",
+	XXBRH:         "xxbrh",
 	BRINC:         "brinc",
 	EVABS:         "evabs",
 	EVADDIW:       "evaddiw",
@@ -4264,13 +4278,17 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVH8X, 0xfc0007fe, 0x7c000658, 0x0, // Load VSX Vector Halfword*8 Indexed XX1-form (lxvh8x XT,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVB16X, 0xfc0007fe, 0x7c0006d8, 0x0, // Load VSX Vector Byte*16 Indexed XX1-form (lxvb16x XT,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{LXV, 0xfc000007, 0xf4000001, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
 		[5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
 	{LXVL, 0xfc0007fe, 0x7c00021a, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-	{LXVX, 0xfc0007fe, 0x7c000218, 0x0, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
+	{LXVX, 0xfc0007be, 0x7c000218, 0x40, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
@@ -4282,6 +4300,10 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXVH8X, 0xfc0007fe, 0x7c000758, 0x0, // Store VSX Vector Halfword*4 Indexed XX1-form (stxvh8x XS,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXVB16X, 0xfc0007fe, 0x7c0007d8, 0x0, // Store VSX Vector Byte*16 Indexed XX1-form (stxvb16x XS,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXV, 0xfc000007, 0xf4000005, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
 		[5]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
 	{STXVL, 0xfc0007fe, 0x7c00031a, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
@@ -4576,6 +4598,12 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
 	{XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}},
+	{XXBRD, 0xfc1f07fc, 0xf017076c, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+	{XXBRW, 0xfc1f07fc, 0xf00f076c, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
+	{XXBRH, 0xfc1f07fc, 0xf007076c, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
 	{BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB)
 		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA)
diff --git a/ppc64/ppc64asm/testdata/decode.txt b/ppc64/ppc64asm/testdata/decode.txt
index 5b8ae2f..5547a18 100644
--- a/ppc64/ppc64asm/testdata/decode.txt
+++ b/ppc64/ppc64asm/testdata/decode.txt
@@ -52,6 +52,10 @@
 fbe1ffd1|	plan9	MOVDU R31,-48(R1)
 7c941f19|	gnu	stxvw4x vs36,r20,r3
 7c941f19|	plan9	STXVW4X VS36,(R3)(R20)
+7c941f59|	gnu	stxvh8x vs36,r20,r3
+7c941f59|	plan9	STXVH8X VS36,(R3)(R20)
+7c941fd9|	gnu	stxvb16x vs36,r20,r3
+7c941fd9|	plan9	STXVB16X VS36,(R3)(R20)
 7c6520a8|	gnu	ldarx r3,r5,r4
 7c6520a8|	plan9	LDAR (R4)(R5),R3
 7c6803a6|	plan9	MOVD R3,LR
@@ -145,6 +149,7 @@
 7ca41896|	plan9	MULHW R3,R4,R5
 7ca41816|	plan9	MULHWU R3,R4,R5
 7ca421d2|	plan9	MULLD R4,R4,R5
+1c63000a|	plan9	MULLD R3,$10,R3
 7ca419d3|	plan9	MULLDCC R3,R4,R5
 7ca41892|	plan9	MULHD R3,R4,R5
 7ca41893|	plan9	MULHDCC R3,R4,R5
@@ -175,6 +180,7 @@
 7c851e30|	plan9	SRAW R3,R4,R5
 7c851c36|	plan9	SRD R3,R4,R5
 7c851e34|	plan9	SRAD R3,R4,R5
+7c631ef4|	plan9	EXTSWSLI R3,$3,R3
 7c6400f4|	plan9	POPCNTB R3,R4
 7c6402f4|	plan9	POPCNTW R3,R4
 7c6403f4|	plan9	POPCNTD R3,R4
@@ -417,6 +423,9 @@
 10611549|	plan9	VNCIPHERLAST V1,V2,V3
 104105c8|	plan9	VSBOX V1,V2
 7c241e98|	plan9	LXVD2X (R3)(R4),VS1
+7c241e18|	plan9	LXVW4X (R3)(R4),VS1
+7c241e58|	plan9	LXVH8X (R3)(R4),VS1
+7c241ed8|	plan9	LXVB16X (R3)(R4),VS1
 f4230011|	plan9	LXV 16(R3),VS1
 7c23221a|	plan9	LXVL R3,R4,VS1
 7c23225a|	plan9	LXVLL R3,R4,VS1
@@ -437,6 +446,9 @@
 f0611550|	plan9	XXLORC VS1,VS2,VS3
 f06114d0|	plan9	XXLXOR VS1,VS2,VS3
 f08110f0|	plan9	XXSEL VS1,VS2,VS3,VS4
+f0570f6c|	plan9	XXBRD VS1,VS2
+f04f0f6c|	plan9	XXBRW VS1,VS2
+f0470f6c|	plan9	XXBRH VS1,VS2
 f0611090|	plan9	XXMRGHW VS1,VS2,VS3
 f0410a90|	plan9	XXSPLTW VS1,$1,VS2
 f06110d0|	plan9	XXPERM VS1,VS2,VS3