riscv64: add support for Zicond instructions Add support for the disassembly of Zicond instructions and test cases. Change-Id: I4c10d7ed0819cd08b9f58165796a6d0c331f88f4 GitHub-Last-Rev: d544f98094aa2ad106658fe1789cc3ade21622db GitHub-Pull-Request: golang/arch#12 Reviewed-on: https://go-review.googlesource.com/c/arch/+/707015 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
diff --git a/riscv64/riscv64asm/objdumpext_test.go b/riscv64/riscv64asm/objdumpext_test.go index 03bd9ba..7536476 100644 --- a/riscv64/riscv64asm/objdumpext_test.go +++ b/riscv64/riscv64asm/objdumpext_test.go
@@ -277,7 +277,7 @@ Type: uint32(0x70000003), // SHT_RISCV_ATTRIBUTES Addr: 0, Off: uint64(off2 + (off3-off2)*4 + strtabsize), - Size: 114, + Size: 129, Addralign: 1, } binary.Write(&buf, binary.LittleEndian, §) @@ -293,7 +293,7 @@ buf.WriteString("\x00.text\x00.riscv.attributes\x00.shstrtab\x00") // Contents of .riscv.attributes section // which specify the extension and priv spec version. (1.11) - buf.WriteString("Aq\x00\x00\x00riscv\x00\x01g\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b") + buf.WriteString("A\x80\x00\x00\x00riscv\x00\x01\x76\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_v1p0_zicond1p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b") f.Write(buf.Bytes()) return nil }
diff --git a/riscv64/riscv64asm/tables.go b/riscv64/riscv64asm/tables.go index 18c9fbf..2a951f9 100644 --- a/riscv64/riscv64asm/tables.go +++ b/riscv64/riscv64asm/tables.go
@@ -116,6 +116,8 @@ CSRRWI CTZ CTZW + CZERO_EQZ + CZERO_NEZ C_ADD C_ADDI C_ADDI16SP @@ -1110,6 +1112,8 @@ CSRRWI: "CSRRWI", CTZ: "CTZ", CTZW: "CTZW", + CZERO_EQZ: "CZERO.EQZ", + CZERO_NEZ: "CZERO.NEZ", C_ADD: "C.ADD", C_ADDI: "C.ADDI", C_ADDI16SP: "C.ADDI16SP", @@ -2211,6 +2215,10 @@ {mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}}, // CTZW rd, rs1 {mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}}, + // CZERO.EQZ rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0e005033, op: CZERO_EQZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // CZERO.NEZ rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0e007033, op: CZERO_NEZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // C.ADD rd_rs1_n0, c_rs2_n0 {mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}}, // C.ADDI rd_rs1_n0, c_nzimm6
diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt index 56139a9..b62e6ca 100644 --- a/riscv64/riscv64asm/testdata/gnucases.txt +++ b/riscv64/riscv64asm/testdata/gnucases.txt
@@ -384,6 +384,10 @@ 8624| fld f9,64(x2) 3eb0| fsd f15,32(x2) +# 12.3: "Zicond" Extension for Integer Conditional Operations, Version 1.0.0 +b353530e| czero.eqz x7,x6,x5 +b373530e| czero.nez x7,x6,x5 + # "V" Standard Extension for Vector Operations, Version 1.0 # 31.6: Configuration Setting Instructions
diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt index 59022cd..c8604bc 100644 --- a/riscv64/riscv64asm/testdata/plan9cases.txt +++ b/riscv64/riscv64asm/testdata/plan9cases.txt
@@ -337,6 +337,10 @@ b3115228| BSET X5, X4, X3 1393f32b| BSETI $63, X7, X6 +# 12.3: "Zicond" Extension for Integer Conditional Operations, Version 1.0.0 +b353530e| CZEROEQZ X5, X6, X7 +b373530e| CZERONEZ X5, X6, X7 + # "V" Standard Extension for Vector Operations, Version 1.0 # 31.6: Configuration Setting Instructions
diff --git a/riscv64/riscv64spec/spec.go b/riscv64/riscv64spec/spec.go index 0434337..392965a 100644 --- a/riscv64/riscv64spec/spec.go +++ b/riscv64/riscv64spec/spec.go
@@ -36,6 +36,7 @@ "rv_zbb", "rv_zbs", "rv_zfh", + "rv_zicond", "rv_zicsr", "rv_zifencei", "rv64_a",