blob: 24c745c8485693bf288ba90470f9f2789ac7d4c9 [file] [log] [blame]
// DO NOT EDIT
// generated by: ppc64map -fmt=decoder ../pp64.csv
package ppc64asm
const (
_ Op = iota
CNTLZW
CNTLZW_
B
BA
BL
BLA
BC
BCA
BCL
BCLA
BCLR
BCLRL
BCCTR
BCCTRL
BCTAR
BCTARL
CRAND
CROR
CRNAND
CRXOR
CRNOR
CRANDC
MCRF
CREQV
CRORC
SC
CLRBHRB
MFBHRBE
LBZ
LBZU
LBZX
LBZUX
LHZ
LHZU
LHZX
LHZUX
LHA
LHAU
LHAX
LHAUX
LWZ
LWZU
LWZX
LWZUX
LWA
LWAX
LWAUX
LD
LDU
LDX
LDUX
STB
STBU
STBX
STBUX
STH
STHU
STHX
STHUX
STW
STWU
STWX
STWUX
STD
STDU
STDX
STDUX
LQ
STQ
LHBRX
LWBRX
STHBRX
STWBRX
LDBRX
STDBRX
LMW
STMW
LSWI
LSWX
STSWI
STSWX
LI
ADDI
LIS
ADDIS
ADD
ADD_
ADDO
ADDO_
ADDIC
SUBF
SUBF_
SUBFO
SUBFO_
ADDIC_
SUBFIC
ADDC
ADDC_
ADDCO
ADDCO_
SUBFC
SUBFC_
SUBFCO
SUBFCO_
ADDE
ADDE_
ADDEO
ADDEO_
ADDME
ADDME_
ADDMEO
ADDMEO_
SUBFE
SUBFE_
SUBFEO
SUBFEO_
SUBFME
SUBFME_
SUBFMEO
SUBFMEO_
ADDZE
ADDZE_
ADDZEO
ADDZEO_
SUBFZE
SUBFZE_
SUBFZEO
SUBFZEO_
NEG
NEG_
NEGO
NEGO_
MULLI
MULLW
MULLW_
MULLWO
MULLWO_
MULHW
MULHW_
MULHWU
MULHWU_
DIVW
DIVW_
DIVWO
DIVWO_
DIVWU
DIVWU_
DIVWUO
DIVWUO_
DIVWE
DIVWE_
DIVWEO
DIVWEO_
DIVWEU
DIVWEU_
DIVWEUO
DIVWEUO_
MULLD
MULLD_
MULLDO
MULLDO_
MULHDU
MULHDU_
MULHD
MULHD_
DIVD
DIVD_
DIVDO
DIVDO_
DIVDU
DIVDU_
DIVDUO
DIVDUO_
DIVDE
DIVDE_
DIVDEO
DIVDEO_
DIVDEU
DIVDEU_
DIVDEUO
DIVDEUO_
CMPWI
CMPDI
CMPW
CMPD
CMPLWI
CMPLDI
CMPLW
CMPLD
TWI
TW
TDI
ISEL
TD
ANDI_
ANDIS_
ORI
ORIS
XORI
XORIS
AND
AND_
XOR
XOR_
NAND
NAND_
OR
OR_
NOR
NOR_
ANDC
ANDC_
EXTSB
EXTSB_
EQV
EQV_
ORC
ORC_
EXTSH
EXTSH_
CMPB
POPCNTB
POPCNTW
PRTYD
PRTYW
EXTSW
EXTSW_
CNTLZD
CNTLZD_
POPCNTD
BPERMD
RLWINM
RLWINM_
RLWNM
RLWNM_
RLWIMI
RLWIMI_
RLDICL
RLDICL_
RLDICR
RLDICR_
RLDIC
RLDIC_
RLDCL
RLDCL_
RLDCR
RLDCR_
RLDIMI
RLDIMI_
SLW
SLW_
SRW
SRW_
SRAWI
SRAWI_
SRAW
SRAW_
SLD
SLD_
SRD
SRD_
SRADI
SRADI_
SRAD
SRAD_
CDTBCD
CBCDTD
ADDG6S
MTSPR
MFSPR
MTCRF
MFCR
MTSLE
MFVSRD
MFVSRWZ
MTVSRD
MTVSRWA
MTVSRWZ
MTOCRF
MFOCRF
MCRXR
MTDCRUX
MFDCRUX
LFS
LFSU
LFSX
LFSUX
LFD
LFDU
LFDX
LFDUX
LFIWAX
LFIWZX
STFS
STFSU
STFSX
STFSUX
STFD
STFDU
STFDX
STFDUX
STFIWX
LFDP
LFDPX
STFDP
STFDPX
FMR
FMR_
FABS
FABS_
FNABS
FNABS_
FNEG
FNEG_
FCPSGN
FCPSGN_
FMRGEW
FMRGOW
FADD
FADD_
FADDS
FADDS_
FSUB
FSUB_
FSUBS
FSUBS_
FMUL
FMUL_
FMULS
FMULS_
FDIV
FDIV_
FDIVS
FDIVS_
FSQRT
FSQRT_
FSQRTS
FSQRTS_
FRE
FRE_
FRES
FRES_
FRSQRTE
FRSQRTE_
FRSQRTES
FRSQRTES_
FTDIV
FTSQRT
FMADD
FMADD_
FMADDS
FMADDS_
FMSUB
FMSUB_
FMSUBS
FMSUBS_
FNMADD
FNMADD_
FNMADDS
FNMADDS_
FNMSUB
FNMSUB_
FNMSUBS
FNMSUBS_
FRSP
FRSP_
FCTID
FCTID_
FCTIDZ
FCTIDZ_
FCTIDU
FCTIDU_
FCTIDUZ
FCTIDUZ_
FCTIW
FCTIW_
FCTIWZ
FCTIWZ_
FCTIWU
FCTIWU_
FCTIWUZ
FCTIWUZ_
FCFID
FCFID_
FCFIDU
FCFIDU_
FCFIDS
FCFIDS_
FCFIDUS
FCFIDUS_
FRIN
FRIN_
FRIZ
FRIZ_
FRIP
FRIP_
FRIM
FRIM_
FCMPU
FCMPO
FSEL
FSEL_
MFFS
MFFS_
MCRFS
MTFSFI
MTFSFI_
MTFSF
MTFSF_
MTFSB0
MTFSB0_
MTFSB1
MTFSB1_
LVEBX
LVEHX
LVEWX
LVX
LVXL
STVEBX
STVEHX
STVEWX
STVX
STVXL
LVSL
LVSR
VPKPX
VPKSDSS
VPKSDUS
VPKSHSS
VPKSHUS
VPKSWSS
VPKSWUS
VPKUDUM
VPKUDUS
VPKUHUM
VPKUHUS
VPKUWUM
VPKUWUS
VUPKHPX
VUPKLPX
VUPKHSB
VUPKHSH
VUPKHSW
VUPKLSB
VUPKLSH
VUPKLSW
VMRGHB
VMRGHH
VMRGLB
VMRGLH
VMRGHW
VMRGLW
VMRGEW
VMRGOW
VSPLTB
VSPLTH
VSPLTW
VSPLTISB
VSPLTISH
VSPLTISW
VPERM
VSEL
VSL
VSLDOI
VSLO
VSR
VSRO
VADDCUW
VADDSBS
VADDSHS
VADDSWS
VADDUBM
VADDUDM
VADDUHM
VADDUWM
VADDUBS
VADDUHS
VADDUWS
VADDUQM
VADDEUQM
VADDCUQ
VADDECUQ
VSUBCUW
VSUBSBS
VSUBSHS
VSUBSWS
VSUBUBM
VSUBUDM
VSUBUHM
VSUBUWM
VSUBUBS
VSUBUHS
VSUBUWS
VSUBUQM
VSUBEUQM
VSUBCUQ
VSUBECUQ
VMULESB
VMULEUB
VMULOSB
VMULOUB
VMULESH
VMULEUH
VMULOSH
VMULOUH
VMULESW
VMULEUW
VMULOSW
VMULOUW
VMULUWM
VMHADDSHS
VMHRADDSHS
VMLADDUHM
VMSUMUBM
VMSUMMBM
VMSUMSHM
VMSUMSHS
VMSUMUHM
VMSUMUHS
VSUMSWS
VSUM2SWS
VSUM4SBS
VSUM4SHS
VSUM4UBS
VAVGSB
VAVGSH
VAVGSW
VAVGUB
VAVGUW
VAVGUH
VMAXSB
VMAXSD
VMAXUB
VMAXUD
VMAXSH
VMAXSW
VMAXUH
VMAXUW
VMINSB
VMINSD
VMINUB
VMINUD
VMINSH
VMINSW
VMINUH
VMINUW
VCMPEQUB
VCMPEQUB_
VCMPEQUH
VCMPEQUH_
VCMPEQUW
VCMPEQUW_
VCMPEQUD
VCMPEQUD_
VCMPGTSB
VCMPGTSB_
VCMPGTSD
VCMPGTSD_
VCMPGTSH
VCMPGTSH_
VCMPGTSW
VCMPGTSW_
VCMPGTUB
VCMPGTUB_
VCMPGTUD
VCMPGTUD_
VCMPGTUH
VCMPGTUH_
VCMPGTUW
VCMPGTUW_
VAND
VANDC
VEQV
VNAND
VORC
VNOR
VOR
VXOR
VRLB
VRLH
VRLW
VRLD
VSLB
VSLH
VSLW
VSLD
VSRB
VSRH
VSRW
VSRD
VSRAB
VSRAH
VSRAW
VSRAD
VADDFP
VSUBFP
VMADDFP
VNMSUBFP
VMAXFP
VMINFP
VCTSXS
VCTUXS
VCFSX
VCFUX
VRFIM
VRFIN
VRFIP
VRFIZ
VCMPBFP
VCMPBFP_
VCMPEQFP
VCMPEQFP_
VCMPGEFP
VCMPGEFP_
VCMPGTFP
VCMPGTFP_
VEXPTEFP
VLOGEFP
VREFP
VRSQRTEFP
VCIPHER
VCIPHERLAST
VNCIPHER
VNCIPHERLAST
VSBOX
VSHASIGMAD
VSHASIGMAW
VPMSUMB
VPMSUMD
VPMSUMH
VPMSUMW
VPERMXOR
VGBBD
VCLZB
VCLZH
VCLZW
VCLZD
VPOPCNTB
VPOPCNTD
VPOPCNTH
VPOPCNTW
VBPERMQ
BCDADD_
BCDSUB_
MTVSCR
MFVSCR
DADD
DADD_
DSUB
DSUB_
DMUL
DMUL_
DDIV
DDIV_
DCMPU
DCMPO
DTSTDC
DTSTDG
DTSTEX
DTSTSF
DQUAI
DQUAI_
DQUA
DQUA_
DRRND
DRRND_
DRINTX
DRINTX_
DRINTN
DRINTN_
DCTDP
DCTDP_
DCTQPQ
DCTQPQ_
DRSP
DRSP_
DRDPQ
DRDPQ_
DCFFIX
DCFFIX_
DCFFIXQ
DCFFIXQ_
DCTFIX
DCTFIX_
DDEDPD
DDEDPD_
DENBCD
DENBCD_
DXEX
DXEX_
DIEX
DIEX_
DSCLI
DSCLI_
DSCRI
DSCRI_
LXSDX
LXSIWAX
LXSIWZX
LXSSPX
LXVD2X
LXVDSX
LXVW4X
STXSDX
STXSIWX
STXSSPX
STXVD2X
STXVW4X
XSABSDP
XSADDDP
XSADDSP
XSCMPODP
XSCMPUDP
XSCPSGNDP
XSCVDPSP
XSCVDPSPN
XSCVDPSXDS
XSCVDPSXWS
XSCVDPUXDS
XSCVDPUXWS
XSCVSPDP
XSCVSPDPN
XSCVSXDDP
XSCVSXDSP
XSCVUXDDP
XSCVUXDSP
XSDIVDP
XSDIVSP
XSMADDADP
XSMADDASP
XSMAXDP
XSMINDP
XSMSUBADP
XSMSUBASP
XSMULDP
XSMULSP
XSNABSDP
XSNEGDP
XSNMADDADP
XSNMADDASP
XSNMSUBADP
XSNMSUBASP
XSRDPI
XSRDPIC
XSRDPIM
XSRDPIP
XSRDPIZ
XSREDP
XSRESP
XSRSP
XSRSQRTEDP
XSRSQRTESP
XSSQRTDP
XSSQRTSP
XSSUBDP
XSSUBSP
XSTDIVDP
XSTSQRTDP
XVABSDP
XVABSSP
XVADDDP
XVADDSP
XVCMPEQDP
XVCMPEQDP_
XVCMPEQSP
XVCMPEQSP_
XVCMPGEDP
XVCMPGEDP_
XVCMPGESP
XVCMPGESP_
XVCMPGTDP
XVCMPGTDP_
XVCMPGTSP
XVCMPGTSP_
XVCPSGNDP
XVCPSGNSP
XVCVDPSP
XVCVDPSXDS
XVCVDPSXWS
XVCVDPUXDS
XVCVDPUXWS
XVCVSPDP
XVCVSPSXDS
XVCVSPSXWS
XVCVSPUXDS
XVCVSPUXWS
XVCVSXDDP
XVCVSXDSP
XVCVSXWDP
XVCVSXWSP
XVCVUXDDP
XVCVUXDSP
XVCVUXWDP
XVCVUXWSP
XVDIVDP
XVDIVSP
XVMADDADP
XVMADDASP
XVMAXDP
XVMAXSP
XVMINDP
XVMINSP
XVMSUBADP
XVMSUBASP
XVMULDP
XVMULSP
XVNABSDP
XVNABSSP
XVNEGDP
XVNEGSP
XVNMADDADP
XVNMADDASP
XVNMSUBADP
XVNMSUBASP
XVRDPI
XVRDPIC
XVRDPIM
XVRDPIP
XVRDPIZ
XVREDP
XVRESP
XVRSPI
XVRSPIC
XVRSPIM
XVRSPIP
XVRSPIZ
XVRSQRTEDP
XVRSQRTESP
XVSQRTDP
XVSQRTSP
XVSUBDP
XVSUBSP
XVTDIVDP
XVTDIVSP
XVTSQRTDP
XVTSQRTSP
XXLAND
XXLANDC
XXLEQV
XXLNAND
XXLORC
XXLNOR
XXLOR
XXLXOR
XXMRGHW
XXMRGLW
XXPERMDI
XXSEL
XXSLDWI
XXSPLTW
BRINC
EVABS
EVADDIW
EVADDSMIAAW
EVADDSSIAAW
EVADDUMIAAW
EVADDUSIAAW
EVADDW
EVAND
EVCMPEQ
EVANDC
EVCMPGTS
EVCMPGTU
EVCMPLTU
EVCMPLTS
EVCNTLSW
EVCNTLZW
EVDIVWS
EVDIVWU
EVEQV
EVEXTSB
EVEXTSH
EVLDD
EVLDH
EVLDDX
EVLDHX
EVLDW
EVLHHESPLAT
EVLDWX
EVLHHESPLATX
EVLHHOSSPLAT
EVLHHOUSPLAT
EVLHHOSSPLATX
EVLHHOUSPLATX
EVLWHE
EVLWHOS
EVLWHEX
EVLWHOSX
EVLWHOU
EVLWHSPLAT
EVLWHOUX
EVLWHSPLATX
EVLWWSPLAT
EVMERGEHI
EVLWWSPLATX
EVMERGELO
EVMERGEHILO
EVMHEGSMFAA
EVMERGELOHI
EVMHEGSMFAN
EVMHEGSMIAA
EVMHEGUMIAA
EVMHEGSMIAN
EVMHEGUMIAN
EVMHESMF
EVMHESMFAAW
EVMHESMFA
EVMHESMFANW
EVMHESMI
EVMHESMIAAW
EVMHESMIA
EVMHESMIANW
EVMHESSF
EVMHESSFA
EVMHESSFAAW
EVMHESSFANW
EVMHESSIAAW
EVMHESSIANW
EVMHEUMI
EVMHEUMIAAW
EVMHEUMIA
EVMHEUMIANW
EVMHEUSIAAW
EVMHEUSIANW
EVMHOGSMFAA
EVMHOGSMIAA
EVMHOGSMFAN
EVMHOGSMIAN
EVMHOGUMIAA
EVMHOSMF
EVMHOGUMIAN
EVMHOSMFA
EVMHOSMFAAW
EVMHOSMI
EVMHOSMFANW
EVMHOSMIA
EVMHOSMIAAW
EVMHOSMIANW
EVMHOSSF
EVMHOSSFA
EVMHOSSFAAW
EVMHOSSFANW
EVMHOSSIAAW
EVMHOUMI
EVMHOSSIANW
EVMHOUMIA
EVMHOUMIAAW
EVMHOUSIAAW
EVMHOUMIANW
EVMHOUSIANW
EVMRA
EVMWHSMF
EVMWHSMI
EVMWHSMFA
EVMWHSMIA
EVMWHSSF
EVMWHUMI
EVMWHSSFA
EVMWHUMIA
EVMWLSMIAAW
EVMWLSSIAAW
EVMWLSMIANW
EVMWLSSIANW
EVMWLUMI
EVMWLUMIAAW
EVMWLUMIA
EVMWLUMIANW
EVMWLUSIAAW
EVMWSMF
EVMWLUSIANW
EVMWSMFA
EVMWSMFAA
EVMWSMI
EVMWSMIAA
EVMWSMFAN
EVMWSMIA
EVMWSMIAN
EVMWSSF
EVMWSSFA
EVMWSSFAA
EVMWUMI
EVMWSSFAN
EVMWUMIA
EVMWUMIAA
EVNAND
EVMWUMIAN
EVNEG
EVNOR
EVORC
EVOR
EVRLW
EVRLWI
EVSEL
EVRNDW
EVSLW
EVSPLATFI
EVSRWIS
EVSLWI
EVSPLATI
EVSRWIU
EVSRWS
EVSTDD
EVSRWU
EVSTDDX
EVSTDH
EVSTDW
EVSTDHX
EVSTDWX
EVSTWHE
EVSTWHO
EVSTWWE
EVSTWHEX
EVSTWHOX
EVSTWWEX
EVSTWWO
EVSUBFSMIAAW
EVSTWWOX
EVSUBFSSIAAW
EVSUBFUMIAAW
EVSUBFUSIAAW
EVSUBFW
EVSUBIFW
EVXOR
EVFSABS
EVFSNABS
EVFSNEG
EVFSADD
EVFSMUL
EVFSSUB
EVFSDIV
EVFSCMPGT
EVFSCMPLT
EVFSCMPEQ
EVFSTSTGT
EVFSTSTLT
EVFSTSTEQ
EVFSCFSI
EVFSCFSF
EVFSCFUI
EVFSCFUF
EVFSCTSI
EVFSCTUI
EVFSCTSIZ
EVFSCTUIZ
EVFSCTSF
EVFSCTUF
EFSABS
EFSNEG
EFSNABS
EFSADD
EFSMUL
EFSSUB
EFSDIV
EFSCMPGT
EFSCMPLT
EFSCMPEQ
EFSTSTGT
EFSTSTLT
EFSTSTEQ
EFSCFSI
EFSCFSF
EFSCTSI
EFSCFUI
EFSCFUF
EFSCTUI
EFSCTSIZ
EFSCTSF
EFSCTUIZ
EFSCTUF
EFDABS
EFDNEG
EFDNABS
EFDADD
EFDMUL
EFDSUB
EFDDIV
EFDCMPGT
EFDCMPEQ
EFDCMPLT
EFDTSTGT
EFDTSTLT
EFDCFSI
EFDTSTEQ
EFDCFUI
EFDCFSID
EFDCFSF
EFDCFUF
EFDCFUID
EFDCTSI
EFDCTUI
EFDCTSIDZ
EFDCTUIDZ
EFDCTSIZ
EFDCTSF
EFDCTUF
EFDCTUIZ
EFDCFS
EFSCFD
DLMZB
DLMZB_
MACCHW
MACCHW_
MACCHWO
MACCHWO_
MACCHWS
MACCHWS_
MACCHWSO
MACCHWSO_
MACCHWU
MACCHWU_
MACCHWUO
MACCHWUO_
MACCHWSU
MACCHWSU_
MACCHWSUO
MACCHWSUO_
MACHHW
MACHHW_
MACHHWO
MACHHWO_
MACHHWS
MACHHWS_
MACHHWSO
MACHHWSO_
MACHHWU
MACHHWU_
MACHHWUO
MACHHWUO_
MACHHWSU
MACHHWSU_
MACHHWSUO
MACHHWSUO_
MACLHW
MACLHW_
MACLHWO
MACLHWO_
MACLHWS
MACLHWS_
MACLHWSO
MACLHWSO_
MACLHWU
MACLHWU_
MACLHWUO
MACLHWUO_
MULCHW
MULCHW_
MACLHWSU
MACLHWSU_
MACLHWSUO
MACLHWSUO_
MULCHWU
MULCHWU_
MULHHW
MULHHW_
MULLHW
MULLHW_
MULHHWU
MULHHWU_
MULLHWU
MULLHWU_
NMACCHW
NMACCHW_
NMACCHWO
NMACCHWO_
NMACCHWS
NMACCHWS_
NMACCHWSO
NMACCHWSO_
NMACHHW
NMACHHW_
NMACHHWO
NMACHHWO_
NMACHHWS
NMACHHWS_
NMACHHWSO
NMACHHWSO_
NMACLHW
NMACLHW_
NMACLHWO
NMACLHWO_
NMACLHWS
NMACLHWS_
NMACLHWSO
NMACLHWSO_
ICBI
ICBT
DCBA
DCBT
DCBTST
DCBZ
DCBST
DCBF
ISYNC
LBARX
LHARX
LWARX
STBCX_
STHCX_
STWCX_
LDARX
STDCX_
LQARX
STQCX_
SYNC
EIEIO
MBAR
WAIT
TBEGIN_
TEND_
TABORT_
TABORTWC_
TABORTWCI_
TABORTDC_
TABORTDCI_
TSR_
TCHECK
MFTB
RFEBB
LBDX
LHDX
LWDX
LDDX
LFDDX
STBDX
STHDX
STWDX
STDDX
STFDDX
DSN
ECIWX
ECOWX
RFID
HRFID
DOZE
NAP
SLEEP
RVWINKLE
LBZCIX
LWZCIX
LHZCIX
LDCIX
STBCIX
STWCIX
STHCIX
STDCIX
TRECLAIM_
TRECHKPT_
MTMSR
MTMSRD
MFMSR
SLBIE
SLBIA
SLBMTE
SLBMFEV
SLBMFEE
SLBFEE_
MTSR
MTSRIN
MFSR
MFSRIN
TLBIE
TLBIEL
TLBIA
TLBSYNC
MSGSND
MSGCLR
MSGSNDP
MSGCLRP
MTTMR
RFI
RFCI
RFDI
RFMCI
RFGI
EHPRIV
MTDCR
MTDCRX
MFDCR
MFDCRX
WRTEE
WRTEEI
LBEPX
LHEPX
LWEPX
LDEPX
STBEPX
STHEPX
STWEPX
STDEPX
DCBSTEP
DCBTEP
DCBFEP
DCBTSTEP
ICBIEP
DCBZEP
LFDEPX
STFDEPX
EVLDDEPX
EVSTDDEPX
LVEPX
LVEPXL
STVEPX
STVEPXL
DCBI
DCBLQ_
ICBLQ_
DCBTLS
DCBTSTLS
ICBTLS
ICBLC
DCBLC
TLBIVAX
TLBILX
TLBSX
TLBSRX_
TLBRE
TLBWE
DNH
DCI
ICI
DCREAD
ICREAD
MFPMR
MTPMR
)
var opstr = [...]string{
CNTLZW: "cntlzw",
CNTLZW_: "cntlzw.",
B: "b",
BA: "ba",
BL: "bl",
BLA: "bla",
BC: "bc",
BCA: "bca",
BCL: "bcl",
BCLA: "bcla",
BCLR: "bclr",
BCLRL: "bclrl",
BCCTR: "bcctr",
BCCTRL: "bcctrl",
BCTAR: "bctar",
BCTARL: "bctarl",
CRAND: "crand",
CROR: "cror",
CRNAND: "crnand",
CRXOR: "crxor",
CRNOR: "crnor",
CRANDC: "crandc",
MCRF: "mcrf",
CREQV: "creqv",
CRORC: "crorc",
SC: "sc",
CLRBHRB: "clrbhrb",
MFBHRBE: "mfbhrbe",
LBZ: "lbz",
LBZU: "lbzu",
LBZX: "lbzx",
LBZUX: "lbzux",
LHZ: "lhz",
LHZU: "lhzu",
LHZX: "lhzx",
LHZUX: "lhzux",
LHA: "lha",
LHAU: "lhau",
LHAX: "lhax",
LHAUX: "lhaux",
LWZ: "lwz",
LWZU: "lwzu",
LWZX: "lwzx",
LWZUX: "lwzux",
LWA: "lwa",
LWAX: "lwax",
LWAUX: "lwaux",
LD: "ld",
LDU: "ldu",
LDX: "ldx",
LDUX: "ldux",
STB: "stb",
STBU: "stbu",
STBX: "stbx",
STBUX: "stbux",
STH: "sth",
STHU: "sthu",
STHX: "sthx",
STHUX: "sthux",
STW: "stw",
STWU: "stwu",
STWX: "stwx",
STWUX: "stwux",
STD: "std",
STDU: "stdu",
STDX: "stdx",
STDUX: "stdux",
LQ: "lq",
STQ: "stq",
LHBRX: "lhbrx",
LWBRX: "lwbrx",
STHBRX: "sthbrx",
STWBRX: "stwbrx",
LDBRX: "ldbrx",
STDBRX: "stdbrx",
LMW: "lmw",
STMW: "stmw",
LSWI: "lswi",
LSWX: "lswx",
STSWI: "stswi",
STSWX: "stswx",
LI: "li",
ADDI: "addi",
LIS: "lis",
ADDIS: "addis",
ADD: "add",
ADD_: "add.",
ADDO: "addo",
ADDO_: "addo.",
ADDIC: "addic",
SUBF: "subf",
SUBF_: "subf.",
SUBFO: "subfo",
SUBFO_: "subfo.",
ADDIC_: "addic.",
SUBFIC: "subfic",
ADDC: "addc",
ADDC_: "addc.",
ADDCO: "addco",
ADDCO_: "addco.",
SUBFC: "subfc",
SUBFC_: "subfc.",
SUBFCO: "subfco",
SUBFCO_: "subfco.",
ADDE: "adde",
ADDE_: "adde.",
ADDEO: "addeo",
ADDEO_: "addeo.",
ADDME: "addme",
ADDME_: "addme.",
ADDMEO: "addmeo",
ADDMEO_: "addmeo.",
SUBFE: "subfe",
SUBFE_: "subfe.",
SUBFEO: "subfeo",
SUBFEO_: "subfeo.",
SUBFME: "subfme",
SUBFME_: "subfme.",
SUBFMEO: "subfmeo",
SUBFMEO_: "subfmeo.",
ADDZE: "addze",
ADDZE_: "addze.",
ADDZEO: "addzeo",
ADDZEO_: "addzeo.",
SUBFZE: "subfze",
SUBFZE_: "subfze.",
SUBFZEO: "subfzeo",
SUBFZEO_: "subfzeo.",
NEG: "neg",
NEG_: "neg.",
NEGO: "nego",
NEGO_: "nego.",
MULLI: "mulli",
MULLW: "mullw",
MULLW_: "mullw.",
MULLWO: "mullwo",
MULLWO_: "mullwo.",
MULHW: "mulhw",
MULHW_: "mulhw.",
MULHWU: "mulhwu",
MULHWU_: "mulhwu.",
DIVW: "divw",
DIVW_: "divw.",
DIVWO: "divwo",
DIVWO_: "divwo.",
DIVWU: "divwu",
DIVWU_: "divwu.",
DIVWUO: "divwuo",
DIVWUO_: "divwuo.",
DIVWE: "divwe",
DIVWE_: "divwe.",
DIVWEO: "divweo",
DIVWEO_: "divweo.",
DIVWEU: "divweu",
DIVWEU_: "divweu.",
DIVWEUO: "divweuo",
DIVWEUO_: "divweuo.",
MULLD: "mulld",
MULLD_: "mulld.",
MULLDO: "mulldo",
MULLDO_: "mulldo.",
MULHDU: "mulhdu",
MULHDU_: "mulhdu.",
MULHD: "mulhd",
MULHD_: "mulhd.",
DIVD: "divd",
DIVD_: "divd.",
DIVDO: "divdo",
DIVDO_: "divdo.",
DIVDU: "divdu",
DIVDU_: "divdu.",
DIVDUO: "divduo",
DIVDUO_: "divduo.",
DIVDE: "divde",
DIVDE_: "divde.",
DIVDEO: "divdeo",
DIVDEO_: "divdeo.",
DIVDEU: "divdeu",
DIVDEU_: "divdeu.",
DIVDEUO: "divdeuo",
DIVDEUO_: "divdeuo.",
CMPWI: "cmpwi",
CMPDI: "cmpdi",
CMPW: "cmpw",
CMPD: "cmpd",
CMPLWI: "cmplwi",
CMPLDI: "cmpldi",
CMPLW: "cmplw",
CMPLD: "cmpld",
TWI: "twi",
TW: "tw",
TDI: "tdi",
ISEL: "isel",
TD: "td",
ANDI_: "andi.",
ANDIS_: "andis.",
ORI: "ori",
ORIS: "oris",
XORI: "xori",
XORIS: "xoris",
AND: "and",
AND_: "and.",
XOR: "xor",
XOR_: "xor.",
NAND: "nand",
NAND_: "nand.",
OR: "or",
OR_: "or.",
NOR: "nor",
NOR_: "nor.",
ANDC: "andc",
ANDC_: "andc.",
EXTSB: "extsb",
EXTSB_: "extsb.",
EQV: "eqv",
EQV_: "eqv.",
ORC: "orc",
ORC_: "orc.",
EXTSH: "extsh",
EXTSH_: "extsh.",
CMPB: "cmpb",
POPCNTB: "popcntb",
POPCNTW: "popcntw",
PRTYD: "prtyd",
PRTYW: "prtyw",
EXTSW: "extsw",
EXTSW_: "extsw.",
CNTLZD: "cntlzd",
CNTLZD_: "cntlzd.",
POPCNTD: "popcntd",
BPERMD: "bpermd",
RLWINM: "rlwinm",
RLWINM_: "rlwinm.",
RLWNM: "rlwnm",
RLWNM_: "rlwnm.",
RLWIMI: "rlwimi",
RLWIMI_: "rlwimi.",
RLDICL: "rldicl",
RLDICL_: "rldicl.",
RLDICR: "rldicr",
RLDICR_: "rldicr.",
RLDIC: "rldic",
RLDIC_: "rldic.",
RLDCL: "rldcl",
RLDCL_: "rldcl.",
RLDCR: "rldcr",
RLDCR_: "rldcr.",
RLDIMI: "rldimi",
RLDIMI_: "rldimi.",
SLW: "slw",
SLW_: "slw.",
SRW: "srw",
SRW_: "srw.",
SRAWI: "srawi",
SRAWI_: "srawi.",
SRAW: "sraw",
SRAW_: "sraw.",
SLD: "sld",
SLD_: "sld.",
SRD: "srd",
SRD_: "srd.",
SRADI: "sradi",
SRADI_: "sradi.",
SRAD: "srad",
SRAD_: "srad.",
CDTBCD: "cdtbcd",
CBCDTD: "cbcdtd",
ADDG6S: "addg6s",
MTSPR: "mtspr",
MFSPR: "mfspr",
MTCRF: "mtcrf",
MFCR: "mfcr",
MTSLE: "mtsle",
MFVSRD: "mfvsrd",
MFVSRWZ: "mfvsrwz",
MTVSRD: "mtvsrd",
MTVSRWA: "mtvsrwa",
MTVSRWZ: "mtvsrwz",
MTOCRF: "mtocrf",
MFOCRF: "mfocrf",
MCRXR: "mcrxr",
MTDCRUX: "mtdcrux",
MFDCRUX: "mfdcrux",
LFS: "lfs",
LFSU: "lfsu",
LFSX: "lfsx",
LFSUX: "lfsux",
LFD: "lfd",
LFDU: "lfdu",
LFDX: "lfdx",
LFDUX: "lfdux",
LFIWAX: "lfiwax",
LFIWZX: "lfiwzx",
STFS: "stfs",
STFSU: "stfsu",
STFSX: "stfsx",
STFSUX: "stfsux",
STFD: "stfd",
STFDU: "stfdu",
STFDX: "stfdx",
STFDUX: "stfdux",
STFIWX: "stfiwx",
LFDP: "lfdp",
LFDPX: "lfdpx",
STFDP: "stfdp",
STFDPX: "stfdpx",
FMR: "fmr",
FMR_: "fmr.",
FABS: "fabs",
FABS_: "fabs.",
FNABS: "fnabs",
FNABS_: "fnabs.",
FNEG: "fneg",
FNEG_: "fneg.",
FCPSGN: "fcpsgn",
FCPSGN_: "fcpsgn.",
FMRGEW: "fmrgew",
FMRGOW: "fmrgow",
FADD: "fadd",
FADD_: "fadd.",
FADDS: "fadds",
FADDS_: "fadds.",
FSUB: "fsub",
FSUB_: "fsub.",
FSUBS: "fsubs",
FSUBS_: "fsubs.",
FMUL: "fmul",
FMUL_: "fmul.",
FMULS: "fmuls",
FMULS_: "fmuls.",
FDIV: "fdiv",
FDIV_: "fdiv.",
FDIVS: "fdivs",
FDIVS_: "fdivs.",
FSQRT: "fsqrt",
FSQRT_: "fsqrt.",
FSQRTS: "fsqrts",
FSQRTS_: "fsqrts.",
FRE: "fre",
FRE_: "fre.",
FRES: "fres",
FRES_: "fres.",
FRSQRTE: "frsqrte",
FRSQRTE_: "frsqrte.",
FRSQRTES: "frsqrtes",
FRSQRTES_: "frsqrtes.",
FTDIV: "ftdiv",
FTSQRT: "ftsqrt",
FMADD: "fmadd",
FMADD_: "fmadd.",
FMADDS: "fmadds",
FMADDS_: "fmadds.",
FMSUB: "fmsub",
FMSUB_: "fmsub.",
FMSUBS: "fmsubs",
FMSUBS_: "fmsubs.",
FNMADD: "fnmadd",
FNMADD_: "fnmadd.",
FNMADDS: "fnmadds",
FNMADDS_: "fnmadds.",
FNMSUB: "fnmsub",
FNMSUB_: "fnmsub.",
FNMSUBS: "fnmsubs",
FNMSUBS_: "fnmsubs.",
FRSP: "frsp",
FRSP_: "frsp.",
FCTID: "fctid",
FCTID_: "fctid.",
FCTIDZ: "fctidz",
FCTIDZ_: "fctidz.",
FCTIDU: "fctidu",
FCTIDU_: "fctidu.",
FCTIDUZ: "fctiduz",
FCTIDUZ_: "fctiduz.",
FCTIW: "fctiw",
FCTIW_: "fctiw.",
FCTIWZ: "fctiwz",
FCTIWZ_: "fctiwz.",
FCTIWU: "fctiwu",
FCTIWU_: "fctiwu.",
FCTIWUZ: "fctiwuz",
FCTIWUZ_: "fctiwuz.",
FCFID: "fcfid",
FCFID_: "fcfid.",
FCFIDU: "fcfidu",
FCFIDU_: "fcfidu.",
FCFIDS: "fcfids",
FCFIDS_: "fcfids.",
FCFIDUS: "fcfidus",
FCFIDUS_: "fcfidus.",
FRIN: "frin",
FRIN_: "frin.",
FRIZ: "friz",
FRIZ_: "friz.",
FRIP: "frip",
FRIP_: "frip.",
FRIM: "frim",
FRIM_: "frim.",
FCMPU: "fcmpu",
FCMPO: "fcmpo",
FSEL: "fsel",
FSEL_: "fsel.",
MFFS: "mffs",
MFFS_: "mffs.",
MCRFS: "mcrfs",
MTFSFI: "mtfsfi",
MTFSFI_: "mtfsfi.",
MTFSF: "mtfsf",
MTFSF_: "mtfsf.",
MTFSB0: "mtfsb0",
MTFSB0_: "mtfsb0.",
MTFSB1: "mtfsb1",
MTFSB1_: "mtfsb1.",
LVEBX: "lvebx",
LVEHX: "lvehx",
LVEWX: "lvewx",
LVX: "lvx",
LVXL: "lvxl",
STVEBX: "stvebx",
STVEHX: "stvehx",
STVEWX: "stvewx",
STVX: "stvx",
STVXL: "stvxl",
LVSL: "lvsl",
LVSR: "lvsr",
VPKPX: "vpkpx",
VPKSDSS: "vpksdss",
VPKSDUS: "vpksdus",
VPKSHSS: "vpkshss",
VPKSHUS: "vpkshus",
VPKSWSS: "vpkswss",
VPKSWUS: "vpkswus",
VPKUDUM: "vpkudum",
VPKUDUS: "vpkudus",
VPKUHUM: "vpkuhum",
VPKUHUS: "vpkuhus",
VPKUWUM: "vpkuwum",
VPKUWUS: "vpkuwus",
VUPKHPX: "vupkhpx",
VUPKLPX: "vupklpx",
VUPKHSB: "vupkhsb",
VUPKHSH: "vupkhsh",
VUPKHSW: "vupkhsw",
VUPKLSB: "vupklsb",
VUPKLSH: "vupklsh",
VUPKLSW: "vupklsw",
VMRGHB: "vmrghb",
VMRGHH: "vmrghh",
VMRGLB: "vmrglb",
VMRGLH: "vmrglh",
VMRGHW: "vmrghw",
VMRGLW: "vmrglw",
VMRGEW: "vmrgew",
VMRGOW: "vmrgow",
VSPLTB: "vspltb",
VSPLTH: "vsplth",
VSPLTW: "vspltw",
VSPLTISB: "vspltisb",
VSPLTISH: "vspltish",
VSPLTISW: "vspltisw",
VPERM: "vperm",
VSEL: "vsel",
VSL: "vsl",
VSLDOI: "vsldoi",
VSLO: "vslo",
VSR: "vsr",
VSRO: "vsro",
VADDCUW: "vaddcuw",
VADDSBS: "vaddsbs",
VADDSHS: "vaddshs",
VADDSWS: "vaddsws",
VADDUBM: "vaddubm",
VADDUDM: "vaddudm",
VADDUHM: "vadduhm",
VADDUWM: "vadduwm",
VADDUBS: "vaddubs",
VADDUHS: "vadduhs",
VADDUWS: "vadduws",
VADDUQM: "vadduqm",
VADDEUQM: "vaddeuqm",
VADDCUQ: "vaddcuq",
VADDECUQ: "vaddecuq",
VSUBCUW: "vsubcuw",
VSUBSBS: "vsubsbs",
VSUBSHS: "vsubshs",
VSUBSWS: "vsubsws",
VSUBUBM: "vsububm",
VSUBUDM: "vsubudm",
VSUBUHM: "vsubuhm",
VSUBUWM: "vsubuwm",
VSUBUBS: "vsububs",
VSUBUHS: "vsubuhs",
VSUBUWS: "vsubuws",
VSUBUQM: "vsubuqm",
VSUBEUQM: "vsubeuqm",
VSUBCUQ: "vsubcuq",
VSUBECUQ: "vsubecuq",
VMULESB: "vmulesb",
VMULEUB: "vmuleub",
VMULOSB: "vmulosb",
VMULOUB: "vmuloub",
VMULESH: "vmulesh",
VMULEUH: "vmuleuh",
VMULOSH: "vmulosh",
VMULOUH: "vmulouh",
VMULESW: "vmulesw",
VMULEUW: "vmuleuw",
VMULOSW: "vmulosw",
VMULOUW: "vmulouw",
VMULUWM: "vmuluwm",
VMHADDSHS: "vmhaddshs",
VMHRADDSHS: "vmhraddshs",
VMLADDUHM: "vmladduhm",
VMSUMUBM: "vmsumubm",
VMSUMMBM: "vmsummbm",
VMSUMSHM: "vmsumshm",
VMSUMSHS: "vmsumshs",
VMSUMUHM: "vmsumuhm",
VMSUMUHS: "vmsumuhs",
VSUMSWS: "vsumsws",
VSUM2SWS: "vsum2sws",
VSUM4SBS: "vsum4sbs",
VSUM4SHS: "vsum4shs",
VSUM4UBS: "vsum4ubs",
VAVGSB: "vavgsb",
VAVGSH: "vavgsh",
VAVGSW: "vavgsw",
VAVGUB: "vavgub",
VAVGUW: "vavguw",
VAVGUH: "vavguh",
VMAXSB: "vmaxsb",
VMAXSD: "vmaxsd",
VMAXUB: "vmaxub",
VMAXUD: "vmaxud",
VMAXSH: "vmaxsh",
VMAXSW: "vmaxsw",
VMAXUH: "vmaxuh",
VMAXUW: "vmaxuw",
VMINSB: "vminsb",
VMINSD: "vminsd",
VMINUB: "vminub",
VMINUD: "vminud",
VMINSH: "vminsh",
VMINSW: "vminsw",
VMINUH: "vminuh",
VMINUW: "vminuw",
VCMPEQUB: "vcmpequb",
VCMPEQUB_: "vcmpequb.",
VCMPEQUH: "vcmpequh",
VCMPEQUH_: "vcmpequh.",
VCMPEQUW: "vcmpequw",
VCMPEQUW_: "vcmpequw.",
VCMPEQUD: "vcmpequd",
VCMPEQUD_: "vcmpequd.",
VCMPGTSB: "vcmpgtsb",
VCMPGTSB_: "vcmpgtsb.",
VCMPGTSD: "vcmpgtsd",
VCMPGTSD_: "vcmpgtsd.",
VCMPGTSH: "vcmpgtsh",
VCMPGTSH_: "vcmpgtsh.",
VCMPGTSW: "vcmpgtsw",
VCMPGTSW_: "vcmpgtsw.",
VCMPGTUB: "vcmpgtub",
VCMPGTUB_: "vcmpgtub.",
VCMPGTUD: "vcmpgtud",
VCMPGTUD_: "vcmpgtud.",
VCMPGTUH: "vcmpgtuh",
VCMPGTUH_: "vcmpgtuh.",
VCMPGTUW: "vcmpgtuw",
VCMPGTUW_: "vcmpgtuw.",
VAND: "vand",
VANDC: "vandc",
VEQV: "veqv",
VNAND: "vnand",
VORC: "vorc",
VNOR: "vnor",
VOR: "vor",
VXOR: "vxor",
VRLB: "vrlb",
VRLH: "vrlh",
VRLW: "vrlw",
VRLD: "vrld",
VSLB: "vslb",
VSLH: "vslh",
VSLW: "vslw",
VSLD: "vsld",
VSRB: "vsrb",
VSRH: "vsrh",
VSRW: "vsrw",
VSRD: "vsrd",
VSRAB: "vsrab",
VSRAH: "vsrah",
VSRAW: "vsraw",
VSRAD: "vsrad",
VADDFP: "vaddfp",
VSUBFP: "vsubfp",
VMADDFP: "vmaddfp",
VNMSUBFP: "vnmsubfp",
VMAXFP: "vmaxfp",
VMINFP: "vminfp",
VCTSXS: "vctsxs",
VCTUXS: "vctuxs",
VCFSX: "vcfsx",
VCFUX: "vcfux",
VRFIM: "vrfim",
VRFIN: "vrfin",
VRFIP: "vrfip",
VRFIZ: "vrfiz",
VCMPBFP: "vcmpbfp",
VCMPBFP_: "vcmpbfp.",
VCMPEQFP: "vcmpeqfp",
VCMPEQFP_: "vcmpeqfp.",
VCMPGEFP: "vcmpgefp",
VCMPGEFP_: "vcmpgefp.",
VCMPGTFP: "vcmpgtfp",
VCMPGTFP_: "vcmpgtfp.",
VEXPTEFP: "vexptefp",
VLOGEFP: "vlogefp",
VREFP: "vrefp",
VRSQRTEFP: "vrsqrtefp",
VCIPHER: "vcipher",
VCIPHERLAST: "vcipherlast",
VNCIPHER: "vncipher",
VNCIPHERLAST: "vncipherlast",
VSBOX: "vsbox",
VSHASIGMAD: "vshasigmad",
VSHASIGMAW: "vshasigmaw",
VPMSUMB: "vpmsumb",
VPMSUMD: "vpmsumd",
VPMSUMH: "vpmsumh",
VPMSUMW: "vpmsumw",
VPERMXOR: "vpermxor",
VGBBD: "vgbbd",
VCLZB: "vclzb",
VCLZH: "vclzh",
VCLZW: "vclzw",
VCLZD: "vclzd",
VPOPCNTB: "vpopcntb",
VPOPCNTD: "vpopcntd",
VPOPCNTH: "vpopcnth",
VPOPCNTW: "vpopcntw",
VBPERMQ: "vbpermq",
BCDADD_: "bcdadd.",
BCDSUB_: "bcdsub.",
MTVSCR: "mtvscr",
MFVSCR: "mfvscr",
DADD: "dadd",
DADD_: "dadd.",
DSUB: "dsub",
DSUB_: "dsub.",
DMUL: "dmul",
DMUL_: "dmul.",
DDIV: "ddiv",
DDIV_: "ddiv.",
DCMPU: "dcmpu",
DCMPO: "dcmpo",
DTSTDC: "dtstdc",
DTSTDG: "dtstdg",
DTSTEX: "dtstex",
DTSTSF: "dtstsf",
DQUAI: "dquai",
DQUAI_: "dquai.",
DQUA: "dqua",
DQUA_: "dqua.",
DRRND: "drrnd",
DRRND_: "drrnd.",
DRINTX: "drintx",
DRINTX_: "drintx.",
DRINTN: "drintn",
DRINTN_: "drintn.",
DCTDP: "dctdp",
DCTDP_: "dctdp.",
DCTQPQ: "dctqpq",
DCTQPQ_: "dctqpq.",
DRSP: "drsp",
DRSP_: "drsp.",
DRDPQ: "drdpq",
DRDPQ_: "drdpq.",
DCFFIX: "dcffix",
DCFFIX_: "dcffix.",
DCFFIXQ: "dcffixq",
DCFFIXQ_: "dcffixq.",
DCTFIX: "dctfix",
DCTFIX_: "dctfix.",
DDEDPD: "ddedpd",
DDEDPD_: "ddedpd.",
DENBCD: "denbcd",
DENBCD_: "denbcd.",
DXEX: "dxex",
DXEX_: "dxex.",
DIEX: "diex",
DIEX_: "diex.",
DSCLI: "dscli",
DSCLI_: "dscli.",
DSCRI: "dscri",
DSCRI_: "dscri.",
LXSDX: "lxsdx",
LXSIWAX: "lxsiwax",
LXSIWZX: "lxsiwzx",
LXSSPX: "lxsspx",
LXVD2X: "lxvd2x",
LXVDSX: "lxvdsx",
LXVW4X: "lxvw4x",
STXSDX: "stxsdx",
STXSIWX: "stxsiwx",
STXSSPX: "stxsspx",
STXVD2X: "stxvd2x",
STXVW4X: "stxvw4x",
XSABSDP: "xsabsdp",
XSADDDP: "xsadddp",
XSADDSP: "xsaddsp",
XSCMPODP: "xscmpodp",
XSCMPUDP: "xscmpudp",
XSCPSGNDP: "xscpsgndp",
XSCVDPSP: "xscvdpsp",
XSCVDPSPN: "xscvdpspn",
XSCVDPSXDS: "xscvdpsxds",
XSCVDPSXWS: "xscvdpsxws",
XSCVDPUXDS: "xscvdpuxds",
XSCVDPUXWS: "xscvdpuxws",
XSCVSPDP: "xscvspdp",
XSCVSPDPN: "xscvspdpn",
XSCVSXDDP: "xscvsxddp",
XSCVSXDSP: "xscvsxdsp",
XSCVUXDDP: "xscvuxddp",
XSCVUXDSP: "xscvuxdsp",
XSDIVDP: "xsdivdp",
XSDIVSP: "xsdivsp",
XSMADDADP: "xsmaddadp",
XSMADDASP: "xsmaddasp",
XSMAXDP: "xsmaxdp",
XSMINDP: "xsmindp",
XSMSUBADP: "xsmsubadp",
XSMSUBASP: "xsmsubasp",
XSMULDP: "xsmuldp",
XSMULSP: "xsmulsp",
XSNABSDP: "xsnabsdp",
XSNEGDP: "xsnegdp",
XSNMADDADP: "xsnmaddadp",
XSNMADDASP: "xsnmaddasp",
XSNMSUBADP: "xsnmsubadp",
XSNMSUBASP: "xsnmsubasp",
XSRDPI: "xsrdpi",
XSRDPIC: "xsrdpic",
XSRDPIM: "xsrdpim",
XSRDPIP: "xsrdpip",
XSRDPIZ: "xsrdpiz",
XSREDP: "xsredp",
XSRESP: "xsresp",
XSRSP: "xsrsp",
XSRSQRTEDP: "xsrsqrtedp",
XSRSQRTESP: "xsrsqrtesp",
XSSQRTDP: "xssqrtdp",
XSSQRTSP: "xssqrtsp",
XSSUBDP: "xssubdp",
XSSUBSP: "xssubsp",
XSTDIVDP: "xstdivdp",
XSTSQRTDP: "xstsqrtdp",
XVABSDP: "xvabsdp",
XVABSSP: "xvabssp",
XVADDDP: "xvadddp",
XVADDSP: "xvaddsp",
XVCMPEQDP: "xvcmpeqdp",
XVCMPEQDP_: "xvcmpeqdp.",
XVCMPEQSP: "xvcmpeqsp",
XVCMPEQSP_: "xvcmpeqsp.",
XVCMPGEDP: "xvcmpgedp",
XVCMPGEDP_: "xvcmpgedp.",
XVCMPGESP: "xvcmpgesp",
XVCMPGESP_: "xvcmpgesp.",
XVCMPGTDP: "xvcmpgtdp",
XVCMPGTDP_: "xvcmpgtdp.",
XVCMPGTSP: "xvcmpgtsp",
XVCMPGTSP_: "xvcmpgtsp.",
XVCPSGNDP: "xvcpsgndp",
XVCPSGNSP: "xvcpsgnsp",
XVCVDPSP: "xvcvdpsp",
XVCVDPSXDS: "xvcvdpsxds",
XVCVDPSXWS: "xvcvdpsxws",
XVCVDPUXDS: "xvcvdpuxds",
XVCVDPUXWS: "xvcvdpuxws",
XVCVSPDP: "xvcvspdp",
XVCVSPSXDS: "xvcvspsxds",
XVCVSPSXWS: "xvcvspsxws",
XVCVSPUXDS: "xvcvspuxds",
XVCVSPUXWS: "xvcvspuxws",
XVCVSXDDP: "xvcvsxddp",
XVCVSXDSP: "xvcvsxdsp",
XVCVSXWDP: "xvcvsxwdp",
XVCVSXWSP: "xvcvsxwsp",
XVCVUXDDP: "xvcvuxddp",
XVCVUXDSP: "xvcvuxdsp",
XVCVUXWDP: "xvcvuxwdp",
XVCVUXWSP: "xvcvuxwsp",
XVDIVDP: "xvdivdp",
XVDIVSP: "xvdivsp",
XVMADDADP: "xvmaddadp",
XVMADDASP: "xvmaddasp",
XVMAXDP: "xvmaxdp",
XVMAXSP: "xvmaxsp",
XVMINDP: "xvmindp",
XVMINSP: "xvminsp",
XVMSUBADP: "xvmsubadp",
XVMSUBASP: "xvmsubasp",
XVMULDP: "xvmuldp",
XVMULSP: "xvmulsp",
XVNABSDP: "xvnabsdp",
XVNABSSP: "xvnabssp",
XVNEGDP: "xvnegdp",
XVNEGSP: "xvnegsp",
XVNMADDADP: "xvnmaddadp",
XVNMADDASP: "xvnmaddasp",
XVNMSUBADP: "xvnmsubadp",
XVNMSUBASP: "xvnmsubasp",
XVRDPI: "xvrdpi",
XVRDPIC: "xvrdpic",
XVRDPIM: "xvrdpim",
XVRDPIP: "xvrdpip",
XVRDPIZ: "xvrdpiz",
XVREDP: "xvredp",
XVRESP: "xvresp",
XVRSPI: "xvrspi",
XVRSPIC: "xvrspic",
XVRSPIM: "xvrspim",
XVRSPIP: "xvrspip",
XVRSPIZ: "xvrspiz",
XVRSQRTEDP: "xvrsqrtedp",
XVRSQRTESP: "xvrsqrtesp",
XVSQRTDP: "xvsqrtdp",
XVSQRTSP: "xvsqrtsp",
XVSUBDP: "xvsubdp",
XVSUBSP: "xvsubsp",
XVTDIVDP: "xvtdivdp",
XVTDIVSP: "xvtdivsp",
XVTSQRTDP: "xvtsqrtdp",
XVTSQRTSP: "xvtsqrtsp",
XXLAND: "xxland",
XXLANDC: "xxlandc",
XXLEQV: "xxleqv",
XXLNAND: "xxlnand",
XXLORC: "xxlorc",
XXLNOR: "xxlnor",
XXLOR: "xxlor",
XXLXOR: "xxlxor",
XXMRGHW: "xxmrghw",
XXMRGLW: "xxmrglw",
XXPERMDI: "xxpermdi",
XXSEL: "xxsel",
XXSLDWI: "xxsldwi",
XXSPLTW: "xxspltw",
BRINC: "brinc",
EVABS: "evabs",
EVADDIW: "evaddiw",
EVADDSMIAAW: "evaddsmiaaw",
EVADDSSIAAW: "evaddssiaaw",
EVADDUMIAAW: "evaddumiaaw",
EVADDUSIAAW: "evaddusiaaw",
EVADDW: "evaddw",
EVAND: "evand",
EVCMPEQ: "evcmpeq",
EVANDC: "evandc",
EVCMPGTS: "evcmpgts",
EVCMPGTU: "evcmpgtu",
EVCMPLTU: "evcmpltu",
EVCMPLTS: "evcmplts",
EVCNTLSW: "evcntlsw",
EVCNTLZW: "evcntlzw",
EVDIVWS: "evdivws",
EVDIVWU: "evdivwu",
EVEQV: "eveqv",
EVEXTSB: "evextsb",
EVEXTSH: "evextsh",
EVLDD: "evldd",
EVLDH: "evldh",
EVLDDX: "evlddx",
EVLDHX: "evldhx",
EVLDW: "evldw",
EVLHHESPLAT: "evlhhesplat",
EVLDWX: "evldwx",
EVLHHESPLATX: "evlhhesplatx",
EVLHHOSSPLAT: "evlhhossplat",
EVLHHOUSPLAT: "evlhhousplat",
EVLHHOSSPLATX: "evlhhossplatx",
EVLHHOUSPLATX: "evlhhousplatx",
EVLWHE: "evlwhe",
EVLWHOS: "evlwhos",
EVLWHEX: "evlwhex",
EVLWHOSX: "evlwhosx",
EVLWHOU: "evlwhou",
EVLWHSPLAT: "evlwhsplat",
EVLWHOUX: "evlwhoux",
EVLWHSPLATX: "evlwhsplatx",
EVLWWSPLAT: "evlwwsplat",
EVMERGEHI: "evmergehi",
EVLWWSPLATX: "evlwwsplatx",
EVMERGELO: "evmergelo",
EVMERGEHILO: "evmergehilo",
EVMHEGSMFAA: "evmhegsmfaa",
EVMERGELOHI: "evmergelohi",
EVMHEGSMFAN: "evmhegsmfan",
EVMHEGSMIAA: "evmhegsmiaa",
EVMHEGUMIAA: "evmhegumiaa",
EVMHEGSMIAN: "evmhegsmian",
EVMHEGUMIAN: "evmhegumian",
EVMHESMF: "evmhesmf",
EVMHESMFAAW: "evmhesmfaaw",
EVMHESMFA: "evmhesmfa",
EVMHESMFANW: "evmhesmfanw",
EVMHESMI: "evmhesmi",
EVMHESMIAAW: "evmhesmiaaw",
EVMHESMIA: "evmhesmia",
EVMHESMIANW: "evmhesmianw",
EVMHESSF: "evmhessf",
EVMHESSFA: "evmhessfa",
EVMHESSFAAW: "evmhessfaaw",
EVMHESSFANW: "evmhessfanw",
EVMHESSIAAW: "evmhessiaaw",
EVMHESSIANW: "evmhessianw",
EVMHEUMI: "evmheumi",
EVMHEUMIAAW: "evmheumiaaw",
EVMHEUMIA: "evmheumia",
EVMHEUMIANW: "evmheumianw",
EVMHEUSIAAW: "evmheusiaaw",
EVMHEUSIANW: "evmheusianw",
EVMHOGSMFAA: "evmhogsmfaa",
EVMHOGSMIAA: "evmhogsmiaa",
EVMHOGSMFAN: "evmhogsmfan",
EVMHOGSMIAN: "evmhogsmian",
EVMHOGUMIAA: "evmhogumiaa",
EVMHOSMF: "evmhosmf",
EVMHOGUMIAN: "evmhogumian",
EVMHOSMFA: "evmhosmfa",
EVMHOSMFAAW: "evmhosmfaaw",
EVMHOSMI: "evmhosmi",
EVMHOSMFANW: "evmhosmfanw",
EVMHOSMIA: "evmhosmia",
EVMHOSMIAAW: "evmhosmiaaw",
EVMHOSMIANW: "evmhosmianw",
EVMHOSSF: "evmhossf",
EVMHOSSFA: "evmhossfa",
EVMHOSSFAAW: "evmhossfaaw",
EVMHOSSFANW: "evmhossfanw",
EVMHOSSIAAW: "evmhossiaaw",
EVMHOUMI: "evmhoumi",
EVMHOSSIANW: "evmhossianw",
EVMHOUMIA: "evmhoumia",
EVMHOUMIAAW: "evmhoumiaaw",
EVMHOUSIAAW: "evmhousiaaw",
EVMHOUMIANW: "evmhoumianw",
EVMHOUSIANW: "evmhousianw",
EVMRA: "evmra",
EVMWHSMF: "evmwhsmf",
EVMWHSMI: "evmwhsmi",
EVMWHSMFA: "evmwhsmfa",
EVMWHSMIA: "evmwhsmia",
EVMWHSSF: "evmwhssf",
EVMWHUMI: "evmwhumi",
EVMWHSSFA: "evmwhssfa",
EVMWHUMIA: "evmwhumia",
EVMWLSMIAAW: "evmwlsmiaaw",
EVMWLSSIAAW: "evmwlssiaaw",
EVMWLSMIANW: "evmwlsmianw",
EVMWLSSIANW: "evmwlssianw",
EVMWLUMI: "evmwlumi",
EVMWLUMIAAW: "evmwlumiaaw",
EVMWLUMIA: "evmwlumia",
EVMWLUMIANW: "evmwlumianw",
EVMWLUSIAAW: "evmwlusiaaw",
EVMWSMF: "evmwsmf",
EVMWLUSIANW: "evmwlusianw",
EVMWSMFA: "evmwsmfa",
EVMWSMFAA: "evmwsmfaa",
EVMWSMI: "evmwsmi",
EVMWSMIAA: "evmwsmiaa",
EVMWSMFAN: "evmwsmfan",
EVMWSMIA: "evmwsmia",
EVMWSMIAN: "evmwsmian",
EVMWSSF: "evmwssf",
EVMWSSFA: "evmwssfa",
EVMWSSFAA: "evmwssfaa",
EVMWUMI: "evmwumi",
EVMWSSFAN: "evmwssfan",
EVMWUMIA: "evmwumia",
EVMWUMIAA: "evmwumiaa",
EVNAND: "evnand",
EVMWUMIAN: "evmwumian",
EVNEG: "evneg",
EVNOR: "evnor",
EVORC: "evorc",
EVOR: "evor",
EVRLW: "evrlw",
EVRLWI: "evrlwi",
EVSEL: "evsel",
EVRNDW: "evrndw",
EVSLW: "evslw",
EVSPLATFI: "evsplatfi",
EVSRWIS: "evsrwis",
EVSLWI: "evslwi",
EVSPLATI: "evsplati",
EVSRWIU: "evsrwiu",
EVSRWS: "evsrws",
EVSTDD: "evstdd",
EVSRWU: "evsrwu",
EVSTDDX: "evstddx",
EVSTDH: "evstdh",
EVSTDW: "evstdw",
EVSTDHX: "evstdhx",
EVSTDWX: "evstdwx",
EVSTWHE: "evstwhe",
EVSTWHO: "evstwho",
EVSTWWE: "evstwwe",
EVSTWHEX: "evstwhex",
EVSTWHOX: "evstwhox",
EVSTWWEX: "evstwwex",
EVSTWWO: "evstwwo",
EVSUBFSMIAAW: "evsubfsmiaaw",
EVSTWWOX: "evstwwox",
EVSUBFSSIAAW: "evsubfssiaaw",
EVSUBFUMIAAW: "evsubfumiaaw",
EVSUBFUSIAAW: "evsubfusiaaw",
EVSUBFW: "evsubfw",
EVSUBIFW: "evsubifw",
EVXOR: "evxor",
EVFSABS: "evfsabs",
EVFSNABS: "evfsnabs",
EVFSNEG: "evfsneg",
EVFSADD: "evfsadd",
EVFSMUL: "evfsmul",
EVFSSUB: "evfssub",
EVFSDIV: "evfsdiv",
EVFSCMPGT: "evfscmpgt",
EVFSCMPLT: "evfscmplt",
EVFSCMPEQ: "evfscmpeq",
EVFSTSTGT: "evfststgt",
EVFSTSTLT: "evfststlt",
EVFSTSTEQ: "evfststeq",
EVFSCFSI: "evfscfsi",
EVFSCFSF: "evfscfsf",
EVFSCFUI: "evfscfui",
EVFSCFUF: "evfscfuf",
EVFSCTSI: "evfsctsi",
EVFSCTUI: "evfsctui",
EVFSCTSIZ: "evfsctsiz",
EVFSCTUIZ: "evfsctuiz",
EVFSCTSF: "evfsctsf",
EVFSCTUF: "evfsctuf",
EFSABS: "efsabs",
EFSNEG: "efsneg",
EFSNABS: "efsnabs",
EFSADD: "efsadd",
EFSMUL: "efsmul",
EFSSUB: "efssub",
EFSDIV: "efsdiv",
EFSCMPGT: "efscmpgt",
EFSCMPLT: "efscmplt",
EFSCMPEQ: "efscmpeq",
EFSTSTGT: "efststgt",
EFSTSTLT: "efststlt",
EFSTSTEQ: "efststeq",
EFSCFSI: "efscfsi",
EFSCFSF: "efscfsf",
EFSCTSI: "efsctsi",
EFSCFUI: "efscfui",
EFSCFUF: "efscfuf",
EFSCTUI: "efsctui",
EFSCTSIZ: "efsctsiz",
EFSCTSF: "efsctsf",
EFSCTUIZ: "efsctuiz",
EFSCTUF: "efsctuf",
EFDABS: "efdabs",
EFDNEG: "efdneg",
EFDNABS: "efdnabs",
EFDADD: "efdadd",
EFDMUL: "efdmul",
EFDSUB: "efdsub",
EFDDIV: "efddiv",
EFDCMPGT: "efdcmpgt",
EFDCMPEQ: "efdcmpeq",
EFDCMPLT: "efdcmplt",
EFDTSTGT: "efdtstgt",
EFDTSTLT: "efdtstlt",
EFDCFSI: "efdcfsi",
EFDTSTEQ: "efdtsteq",
EFDCFUI: "efdcfui",
EFDCFSID: "efdcfsid",
EFDCFSF: "efdcfsf",
EFDCFUF: "efdcfuf",
EFDCFUID: "efdcfuid",
EFDCTSI: "efdctsi",
EFDCTUI: "efdctui",
EFDCTSIDZ: "efdctsidz",
EFDCTUIDZ: "efdctuidz",
EFDCTSIZ: "efdctsiz",
EFDCTSF: "efdctsf",
EFDCTUF: "efdctuf",
EFDCTUIZ: "efdctuiz",
EFDCFS: "efdcfs",
EFSCFD: "efscfd",
DLMZB: "dlmzb",
DLMZB_: "dlmzb.",
MACCHW: "macchw",
MACCHW_: "macchw.",
MACCHWO: "macchwo",
MACCHWO_: "macchwo.",
MACCHWS: "macchws",
MACCHWS_: "macchws.",
MACCHWSO: "macchwso",
MACCHWSO_: "macchwso.",
MACCHWU: "macchwu",
MACCHWU_: "macchwu.",
MACCHWUO: "macchwuo",
MACCHWUO_: "macchwuo.",
MACCHWSU: "macchwsu",
MACCHWSU_: "macchwsu.",
MACCHWSUO: "macchwsuo",
MACCHWSUO_: "macchwsuo.",
MACHHW: "machhw",
MACHHW_: "machhw.",
MACHHWO: "machhwo",
MACHHWO_: "machhwo.",
MACHHWS: "machhws",
MACHHWS_: "machhws.",
MACHHWSO: "machhwso",
MACHHWSO_: "machhwso.",
MACHHWU: "machhwu",
MACHHWU_: "machhwu.",
MACHHWUO: "machhwuo",
MACHHWUO_: "machhwuo.",
MACHHWSU: "machhwsu",
MACHHWSU_: "machhwsu.",
MACHHWSUO: "machhwsuo",
MACHHWSUO_: "machhwsuo.",
MACLHW: "maclhw",
MACLHW_: "maclhw.",
MACLHWO: "maclhwo",
MACLHWO_: "maclhwo.",
MACLHWS: "maclhws",
MACLHWS_: "maclhws.",
MACLHWSO: "maclhwso",
MACLHWSO_: "maclhwso.",
MACLHWU: "maclhwu",
MACLHWU_: "maclhwu.",
MACLHWUO: "maclhwuo",
MACLHWUO_: "maclhwuo.",
MULCHW: "mulchw",
MULCHW_: "mulchw.",
MACLHWSU: "maclhwsu",
MACLHWSU_: "maclhwsu.",
MACLHWSUO: "maclhwsuo",
MACLHWSUO_: "maclhwsuo.",
MULCHWU: "mulchwu",
MULCHWU_: "mulchwu.",
MULHHW: "mulhhw",
MULHHW_: "mulhhw.",
MULLHW: "mullhw",
MULLHW_: "mullhw.",
MULHHWU: "mulhhwu",
MULHHWU_: "mulhhwu.",
MULLHWU: "mullhwu",
MULLHWU_: "mullhwu.",
NMACCHW: "nmacchw",
NMACCHW_: "nmacchw.",
NMACCHWO: "nmacchwo",
NMACCHWO_: "nmacchwo.",
NMACCHWS: "nmacchws",
NMACCHWS_: "nmacchws.",
NMACCHWSO: "nmacchwso",
NMACCHWSO_: "nmacchwso.",
NMACHHW: "nmachhw",
NMACHHW_: "nmachhw.",
NMACHHWO: "nmachhwo",
NMACHHWO_: "nmachhwo.",
NMACHHWS: "nmachhws",
NMACHHWS_: "nmachhws.",
NMACHHWSO: "nmachhwso",
NMACHHWSO_: "nmachhwso.",
NMACLHW: "nmaclhw",
NMACLHW_: "nmaclhw.",
NMACLHWO: "nmaclhwo",
NMACLHWO_: "nmaclhwo.",
NMACLHWS: "nmaclhws",
NMACLHWS_: "nmaclhws.",
NMACLHWSO: "nmaclhwso",
NMACLHWSO_: "nmaclhwso.",
ICBI: "icbi",
ICBT: "icbt",
DCBA: "dcba",
DCBT: "dcbt",
DCBTST: "dcbtst",
DCBZ: "dcbz",
DCBST: "dcbst",
DCBF: "dcbf",
ISYNC: "isync",
LBARX: "lbarx",
LHARX: "lharx",
LWARX: "lwarx",
STBCX_: "stbcx.",
STHCX_: "sthcx.",
STWCX_: "stwcx.",
LDARX: "ldarx",
STDCX_: "stdcx.",
LQARX: "lqarx",
STQCX_: "stqcx.",
SYNC: "sync",
EIEIO: "eieio",
MBAR: "mbar",
WAIT: "wait",
TBEGIN_: "tbegin.",
TEND_: "tend.",
TABORT_: "tabort.",
TABORTWC_: "tabortwc.",
TABORTWCI_: "tabortwci.",
TABORTDC_: "tabortdc.",
TABORTDCI_: "tabortdci.",
TSR_: "tsr.",
TCHECK: "tcheck",
MFTB: "mftb",
RFEBB: "rfebb",
LBDX: "lbdx",
LHDX: "lhdx",
LWDX: "lwdx",
LDDX: "lddx",
LFDDX: "lfddx",
STBDX: "stbdx",
STHDX: "sthdx",
STWDX: "stwdx",
STDDX: "stddx",
STFDDX: "stfddx",
DSN: "dsn",
ECIWX: "eciwx",
ECOWX: "ecowx",
RFID: "rfid",
HRFID: "hrfid",
DOZE: "doze",
NAP: "nap",
SLEEP: "sleep",
RVWINKLE: "rvwinkle",
LBZCIX: "lbzcix",
LWZCIX: "lwzcix",
LHZCIX: "lhzcix",
LDCIX: "ldcix",
STBCIX: "stbcix",
STWCIX: "stwcix",
STHCIX: "sthcix",
STDCIX: "stdcix",
TRECLAIM_: "treclaim.",
TRECHKPT_: "trechkpt.",
MTMSR: "mtmsr",
MTMSRD: "mtmsrd",
MFMSR: "mfmsr",
SLBIE: "slbie",
SLBIA: "slbia",
SLBMTE: "slbmte",
SLBMFEV: "slbmfev",
SLBMFEE: "slbmfee",
SLBFEE_: "slbfee.",
MTSR: "mtsr",
MTSRIN: "mtsrin",
MFSR: "mfsr",
MFSRIN: "mfsrin",
TLBIE: "tlbie",
TLBIEL: "tlbiel",
TLBIA: "tlbia",
TLBSYNC: "tlbsync",
MSGSND: "msgsnd",
MSGCLR: "msgclr",
MSGSNDP: "msgsndp",
MSGCLRP: "msgclrp",
MTTMR: "mttmr",
RFI: "rfi",
RFCI: "rfci",
RFDI: "rfdi",
RFMCI: "rfmci",
RFGI: "rfgi",
EHPRIV: "ehpriv",
MTDCR: "mtdcr",
MTDCRX: "mtdcrx",
MFDCR: "mfdcr",
MFDCRX: "mfdcrx",
WRTEE: "wrtee",
WRTEEI: "wrteei",
LBEPX: "lbepx",
LHEPX: "lhepx",
LWEPX: "lwepx",
LDEPX: "ldepx",
STBEPX: "stbepx",
STHEPX: "sthepx",
STWEPX: "stwepx",
STDEPX: "stdepx",
DCBSTEP: "dcbstep",
DCBTEP: "dcbtep",
DCBFEP: "dcbfep",
DCBTSTEP: "dcbtstep",
ICBIEP: "icbiep",
DCBZEP: "dcbzep",
LFDEPX: "lfdepx",
STFDEPX: "stfdepx",
EVLDDEPX: "evlddepx",
EVSTDDEPX: "evstddepx",
LVEPX: "lvepx",
LVEPXL: "lvepxl",
STVEPX: "stvepx",
STVEPXL: "stvepxl",
DCBI: "dcbi",
DCBLQ_: "dcblq.",
ICBLQ_: "icblq.",
DCBTLS: "dcbtls",
DCBTSTLS: "dcbtstls",
ICBTLS: "icbtls",
ICBLC: "icblc",
DCBLC: "dcblc",
TLBIVAX: "tlbivax",
TLBILX: "tlbilx",
TLBSX: "tlbsx",
TLBSRX_: "tlbsrx.",
TLBRE: "tlbre",
TLBWE: "tlbwe",
DNH: "dnh",
DCI: "dci",
ICI: "ici",
DCREAD: "dcread",
ICREAD: "icread",
MFPMR: "mfpmr",
MTPMR: "mtpmr",
}
var (
ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}}
ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}}
ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}}
ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}}
ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}}
ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}}
ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}}
ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}}
ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}}
ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}}
ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}}
ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}}
ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}}
ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}}
ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}}
ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}}
ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}}
ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}}
ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}}
ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}}
ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}}
ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}}
ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}}
ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}}
ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}}
ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}}
ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}}
ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}}
ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}}
ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}}
ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}}
ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}}
ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}}
ap_CondRegField_29_31 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}}
ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}}
ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}}
ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}}
ap_ImmSigned_16_20 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}}
ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}}
ap_SpReg_12_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}}
ap_ImmUnsigned_6_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}}
ap_ImmUnsigned_11_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}}
)
var instFormats = [...]instFormat{
{CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CNTLZW_, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr)
[5]*argField{ap_PCRel_6_29_shift2}},
{BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr)
[5]*argField{ap_Label_6_29_shift2}},
{BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr)
[5]*argField{ap_PCRel_6_29_shift2}},
{BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr)
[5]*argField{ap_Label_6_29_shift2}},
{BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
{BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
{BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
{BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
{BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA)
[5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
{CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
[5]*argField{ap_ImmUnsigned_20_26}},
{CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb)
[5]*argField{}},
{MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From Branch History Rolling Buffer XFX-form (mfbhrbe RT,BHRBE)
[5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
{LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
{STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
{LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
{STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI)
[5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
{ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT, SI)
[5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
{ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADD_, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDO_, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBF_, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFO_, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDIC_, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDC_, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDCO_, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFC_, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFCO_, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDE_, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDEO_, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDME_, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDMEO_, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFE_, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFEO_, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFME_, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFMEO_, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZE_, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZEO_, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZE_, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZEO_, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEG_, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEGO_, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLW_, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLWO_, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHW_, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHWU_, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVW_, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWO_, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWU_, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWUO_, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWE_, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEO_, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEU_, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEUO_, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLD_, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLDO_, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHDU_, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHD_, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVD_, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDO_, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDU_, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDUO_, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDE_, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEO_, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEU_, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEUO_, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
{CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
{CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
{CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
{CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
{TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ANDI_, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{ANDIS_, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{AND_, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{XOR_, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NAND_, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{OR_, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NOR_, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ANDC_, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSB_, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{EQV_, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ORC_, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSH_, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSW_, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CNTLZD_, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWINM_, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWNM_, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWIMI_, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICL_, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICR_, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIC_, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCL_, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCR_, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIMI_, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SLW_, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRW_, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
{SRAWI_, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
{SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRAW_, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SLD_, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRD_, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
{SRADI_, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
{SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRAD_, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
{MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
[5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
{MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT)
[5]*argField{ap_Reg_6_10}},
{MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801, // Move To Split Little Endian X-form (mtsle L)
[5]*argField{ap_ImmUnsigned_10_10}},
{MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword XX1-form (mfvsrd RA,XS)
[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
{MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero XX1-form (mfvsrwz RA,XS)
[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
{MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword XX1-form (mtvsrd XT,RA)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
{MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic XX1-form (mtvsrwa XT,RA)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
{MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero XX1-form (mtvsrwz XT,RA)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
{MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS)
[5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
{MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM)
[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
{MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801, // Move to Condition Register from XER X-form (mcrxr BF)
[5]*argField{ap_CondRegField_6_8}},
{MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801, // Move To Device Control Register User-mode Indexed X-form (mtdcrux RS,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801, // Move From Device Control Register User-mode Indexed X-form (mfdcrux RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word and Zero Indexed X-form (lfiwzx FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FMR_, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FABS_, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNABS_, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNEG_, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FCPSGN_, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADD_, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADDS_, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUB_, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUBS_, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FMUL_, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FMULS_, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FDIV_, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FDIVS_, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FSQRT_, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FSQRTS_, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRE_, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRES_, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTE_, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTES_, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
{FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
{FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMADD_, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMADDS_, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUB_, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUBS_, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADD_, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADDS_, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUB_, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUBS_, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSP_, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTID_, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDZ_, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDU_, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDUZ_, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIW_, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWZ_, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWU_, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWUZ_, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFID_, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDU_, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDS_, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDUS_, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIN_, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIZ_, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIP_, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIM_, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
{FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FSEL_, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT)
[5]*argField{ap_FPReg_6_10}},
{MFFS_, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT)
[5]*argField{ap_FPReg_6_10}},
{MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
[5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
{MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
{MTFSFI_, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
{MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
[5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
{MTFSF_, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
[5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
{MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
[5]*argField{ap_CondRegBit_6_10}},
{MTFSB0_, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
[5]*argField{ap_CondRegBit_6_10}},
{MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
[5]*argField{ap_CondRegBit_6_10}},
{MTFSB1_, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
[5]*argField{ap_CondRegBit_6_10}},
{LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVX, 0xfc0007fe, 0x7c0000ce, 0x1, // Load Vector Indexed X-form (lvx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVXL, 0xfc0007fe, 0x7c0002ce, 0x1, // Load Vector Indexed LRU X-form (lvxl VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STVEBX, 0xfc0007fe, 0x7c00010e, 0x1, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STVEHX, 0xfc0007fe, 0x7c00014e, 0x1, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STVEWX, 0xfc0007fe, 0x7c00018e, 0x1, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STVX, 0xfc0007fe, 0x7c0001ce, 0x1, // Store Vector Indexed X-form (stvx VRS,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STVXL, 0xfc0007fe, 0x7c0003ce, 0x1, // Store Vector Indexed LRU X-form (stvxl VRS,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVSL, 0xfc0007fe, 0x7c00000c, 0x1, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVSR, 0xfc0007fe, 0x7c00004c, 0x1, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{VPKPX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
{VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB)
[5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
{VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB)