x/arch/arm64: implement arm64 disassembler
- Add support for all basic instructions (except for the following
6 system instructions: AT, DC, HVC, SMC, SYS and TLBI)
- Add support for all FP basic instructions
- Add support for all SIMD instructions (plan9 syntax refer to CL 41654)
- Add cases for testing all instructions and comparing disassembly result
with external disassembler (by gnu syntax)
Disassembler framework is mainly contributed by Zheng Xu <zheng.xu@arm.com>
Testing and bug fixing are mainly contributed by Fannie Zhang <fannie.zhang@arm.com>
Other parts (such as decoder table and argument) are mainly contributed by Wei Xiao <wei.xiao@arm.com>
Fixes #19157
Change-Id: I76b6b075f487857124c8ca774a12d764d4ee85c7
Reviewed-on: https://go-review.googlesource.com/43651
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
diff --git a/arm64/arm64asm/arg.go b/arm64/arm64asm/arg.go
new file mode 100644
index 0000000..96df14d
--- /dev/null
+++ b/arm64/arm64asm/arg.go
@@ -0,0 +1,494 @@
+// Generated by ARM internal tool
+// DO NOT EDIT
+
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+// Naming for Go decoder arguments:
+//
+// - arg_Wd: a W register encoded in the Rd[4:0] field (31 is wzr)
+//
+// - arg_Xd: a X register encoded in the Rd[4:0] field (31 is xzr)
+//
+// - arg_Wds: a W register encoded in the Rd[4:0] field (31 is wsp)
+//
+// - arg_Xds: a X register encoded in the Rd[4:0] field (31 is sp)
+//
+// - arg_Wn: encoded in Rn[9:5]
+//
+// - arg_Wm: encoded in Rm[20:16]
+//
+// - arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
+// a W register encoded in Rm with an extend encoded in option[15:13] and an amount
+// encoded in imm3[12:10] in the range [0,4].
+//
+// - arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
+// a W or X register encoded in Rm with an extend encoded in option[15:13] and an
+// amount encoded in imm3[12:10] in the range [0,4]. If the extend is UXTX or SXTX,
+// it's an X register else, it's a W register.
+//
+// - arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31:
+// a W register encoded in Rm with a shift encoded in shift[23:22] and an amount
+// encoded in imm6[15:10] in the range [0,31].
+//
+// - arg_IAddSub:
+// An immediate for a add/sub instruction encoded in imm12[21:10] with an optional
+// left shift of 12 encoded in shift[23:22].
+//
+// - arg_Rt_31_1__W_0__X_1:
+// a W or X register encoded in Rt[4:0]. The width specifier is encoded in the field
+// [31:31] (offset 31, bit count 1) and the register is W for 0 and X for 1.
+//
+// - arg_[s|u]label_FIELDS_POWER:
+// a program label encoded as "FIELDS" times 2^POWER in the range [MIN, MAX] (determined
+// by signd/unsigned, FIELDS and POWER), e.g.
+// arg_slabel_imm14_2
+// arg_slabel_imm19_2
+// arg_slabel_imm26_2
+// arg_slabel_immhi_immlo_0
+// arg_slabel_immhi_immlo_12
+//
+// - arg_Xns_mem_post_imm7_8_signed:
+// addressing mode of post-index with a base register: Xns and a signed offset encoded
+// in the "imm7" field times 8
+//
+// - arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1:
+// addressing mode of extended register with a base register: Xns, an offset register
+// (<Wm>|<Xm>) with an extend encoded in option[15:13] and a shift amount encoded in
+// S[12:12] in the range [0,3] (S=0:0, S=1:3).
+//
+// - arg_Xns_mem_optional_imm12_4_unsigned:
+// addressing mode of unsigned offset with a base register: Xns and an optional unsigned
+// offset encoded in the "imm12" field times 4
+//
+// - arg_Xns_mem_wb_imm7_4_signed:
+// addressing mode of pre-index with a base register: Xns and the signed offset encoded
+// in the "imm7" field times 4
+//
+// - arg_Xns_mem_post_size_1_8_unsigned__4_0__8_1__16_2__32_3:
+// a post-index immediate offset, encoded in the "size" field. It can have the following values:
+// #4 when size = 00
+// #8 when size = 01
+// #16 when size = 10
+// #32 when size = 11
+//
+// - arg_immediate_0_127_CRm_op2:
+// an immediate encoded in "CRm:op2" in the range 0 to 127
+//
+// - arg_immediate_bitmask_64_N_imms_immr:
+// a bitmask immediate for 64-bit variant and encoded in "N:imms:immr"
+//
+// - arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms:
+// an immediate for the <width> bitfield of SBFX 64-bit variant
+//
+// - arg_immediate_shift_32_implicit_inverse_imm16_hw:
+// a 32-bit immediate of the bitwise inverse of which can be encoded in "imm16:hw"
+//
+// - arg_cond_[Not]AllowALNV_[Invert|Normal]:
+// a standard condition, encoded in the "cond" field, excluding (NotAllow) AL and NV with
+// its least significant bit [Yes|No] inverted, e.g.
+// arg_cond_AllowALNV_Normal
+// arg_cond_NotAllowALNV_Invert
+//
+// - arg_immediate_OptLSL_amount_16_0_48:
+// An immediate for MOV[KNZ] instruction encoded in imm16[20:5] with an optional
+// left shift of 16 in the range [0, 48] encoded in hw[22, 21]
+//
+// - arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
+// the left shift amount, in the range 0 to the operand width in bits minus 1,
+// encoded in the "immh:immb" field. It can have the following values:
+// (UInt(immh:immb)-8) when immh = 0001
+// (UInt(immh:immb)-16) when immh = 001x
+// (UInt(immh:immb)-32) when immh = 01xx
+// (UInt(immh:immb)-64) when immh = 1xxx
+//
+// - arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
+// the right shift amount, in the range 1 to the destination operand width in
+// bits, encoded in the "immh:immb" field. It can have the following values:
+// (16-UInt(immh:immb)) when immh = 0001
+// (32-UInt(immh:immb)) when immh = 001x
+// (64-UInt(immh:immb)) when immh = 01xx
+//
+// - arg_immediate_8x8_a_b_c_d_e_f_g_h:
+// a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
+// encoded in "a:b:c:d:e:f:g:h".
+//
+// - arg_immediate_fbits_min_1_max_32_sub_64_scale:
+// the number of bits after the binary point in the fixed-point destination,
+// in the range 1 to 32, encoded as 64 minus "scale".
+//
+// - arg_immediate_floatzero: #0.0
+//
+// - arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h:
+// a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision,
+// encoded in "a:b:c:d:e:f:g:h"
+//
+// - arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8:
+// the number of fractional bits, in the range 1 to the operand width, encoded
+// in the "immh:immb" field. It can have the following values:
+// (64-UInt(immh:immb)) when immh = 01xx
+// (128-UInt(immh:immb)) when immh = 1xxx
+//
+// - arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10:
+// the lowest numbered byte element to be extracted, encoded in the "Q:imm4" field.
+// It can have the following values:
+// imm4<2:0> when Q = 0, imm4<3> = 0
+// imm4 when Q = 1, imm4<3> = x
+//
+// - arg_sysop_AT_SYS_CR_system:
+// system operation for system instruction: AT encoded in the "op1:CRm<0>:op2" field
+//
+// - arg_prfop_Rt:
+// prefectch operation encoded in the "Rt"
+//
+// - arg_sysreg_o0_op1_CRn_CRm_op2:
+// system register name encoded in the "o0:op1:CRn:CRm:op2"
+//
+// - arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37:
+// PSTATE field name encoded in the "op1:op2" field
+//
+// - arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+// one register with arrangement specifier encoded in the "size:Q" field which can have the following values:
+// 8B when size = 00, Q = 0
+// 16B when size = 00, Q = 1
+// 4H when size = 01, Q = 0
+// 8H when size = 01, Q = 1
+// 2S when size = 10, Q = 0
+// 4S when size = 10, Q = 1
+// 2D when size = 11, Q = 1
+// The encoding size = 11, Q = 0 is reserved.
+//
+// - arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
+// three registers with arrangement specifier encoded in the "size:Q" field which can have the following values:
+// 8B when size = 00, Q = 0
+// 16B when size = 00, Q = 1
+// 4H when size = 01, Q = 0
+// 8H when size = 01, Q = 1
+// 2S when size = 10, Q = 0
+// 4S when size = 10, Q = 1
+// 2D when size = 11, Q = 1
+// The encoding size = 11, Q = 0 is reserved.
+//
+// - arg_Vt_1_arrangement_H_index__Q_S_size_1:
+// one register with arrangement:H and element index encoded in "Q:S:size<1>".
+
+type instArg uint16
+
+const (
+ _ instArg = iota
+ arg_Bt
+ arg_Cm
+ arg_Cn
+ arg_cond_AllowALNV_Normal
+ arg_conditional
+ arg_cond_NotAllowALNV_Invert
+ arg_Da
+ arg_Dd
+ arg_Dm
+ arg_Dn
+ arg_Dt
+ arg_Dt2
+ arg_Hd
+ arg_Hn
+ arg_Ht
+ arg_IAddSub
+ arg_immediate_0_127_CRm_op2
+ arg_immediate_0_15_CRm
+ arg_immediate_0_15_nzcv
+ arg_immediate_0_31_imm5
+ arg_immediate_0_31_immr
+ arg_immediate_0_31_imms
+ arg_immediate_0_63_b5_b40
+ arg_immediate_0_63_immh_immb__UIntimmhimmb64_8
+ arg_immediate_0_63_immr
+ arg_immediate_0_63_imms
+ arg_immediate_0_65535_imm16
+ arg_immediate_0_7_op1
+ arg_immediate_0_7_op2
+ arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4
+ arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8
+ arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8
+ arg_immediate_0_width_size__8_0__16_1__32_2
+ arg_immediate_1_64_immh_immb__128UIntimmhimmb_8
+ arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4
+ arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4
+ arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8
+ arg_immediate_8x8_a_b_c_d_e_f_g_h
+ arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr
+ arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr
+ arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr
+ arg_immediate_BFI_BFM_32M_bitfield_width_32_imms
+ arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr
+ arg_immediate_BFI_BFM_64M_bitfield_width_64_imms
+ arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr
+ arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms
+ arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr
+ arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms
+ arg_immediate_bitmask_32_imms_immr
+ arg_immediate_bitmask_64_N_imms_immr
+ arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h
+ arg_immediate_exp_3_pre_4_imm8
+ arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8
+ arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8
+ arg_immediate_fbits_min_1_max_32_sub_64_scale
+ arg_immediate_fbits_min_1_max_64_sub_64_scale
+ arg_immediate_floatzero
+ arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10
+ arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr
+ arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr
+ arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr
+ arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr
+ arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1
+ arg_immediate_optional_0_15_CRm
+ arg_immediate_optional_0_65535_imm16
+ arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1
+ arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3
+ arg_immediate_OptLSL_amount_16_0_16
+ arg_immediate_OptLSL_amount_16_0_48
+ arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h
+ arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr
+ arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms
+ arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr
+ arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms
+ arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr
+ arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms
+ arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr
+ arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms
+ arg_immediate_shift_32_implicit_imm16_hw
+ arg_immediate_shift_32_implicit_inverse_imm16_hw
+ arg_immediate_shift_64_implicit_imm16_hw
+ arg_immediate_shift_64_implicit_inverse_imm16_hw
+ arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr
+ arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms
+ arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr
+ arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms
+ arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr
+ arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms
+ arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr
+ arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms
+ arg_immediate_zero
+ arg_option_DMB_BO_system_CRm
+ arg_option_DSB_BO_system_CRm
+ arg_option_ISB_BI_system_CRm
+ arg_prfop_Rt
+ arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37
+ arg_Qd
+ arg_Qn
+ arg_Qt
+ arg_Qt2
+ arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4
+ arg_Rn_16_5__W_1__W_2__W_4__X_8
+ arg_Rt_31_1__W_0__X_1
+ arg_Sa
+ arg_Sd
+ arg_slabel_imm14_2
+ arg_slabel_imm19_2
+ arg_slabel_imm26_2
+ arg_slabel_immhi_immlo_0
+ arg_slabel_immhi_immlo_12
+ arg_Sm
+ arg_Sn
+ arg_St
+ arg_St2
+ arg_sysop_AT_SYS_CR_system
+ arg_sysop_DC_SYS_CR_system
+ arg_sysop_IC_SYS_CR_system
+ arg_sysop_SYS_CR_system
+ arg_sysop_TLBI_SYS_CR_system
+ arg_sysreg_o0_op1_CRn_CRm_op2
+ arg_Vd_16_5__B_1__H_2__S_4__D_8
+ arg_Vd_19_4__B_1__H_2__S_4
+ arg_Vd_19_4__B_1__H_2__S_4__D_8
+ arg_Vd_19_4__D_8
+ arg_Vd_19_4__S_4__D_8
+ arg_Vd_22_1__S_0
+ arg_Vd_22_1__S_0__D_1
+ arg_Vd_22_1__S_1
+ arg_Vd_22_2__B_0__H_1__S_2
+ arg_Vd_22_2__B_0__H_1__S_2__D_3
+ arg_Vd_22_2__D_3
+ arg_Vd_22_2__H_0__S_1__D_2
+ arg_Vd_22_2__H_1__S_2
+ arg_Vd_22_2__S_1__D_2
+ arg_Vd_arrangement_16B
+ arg_Vd_arrangement_2D
+ arg_Vd_arrangement_4S
+ arg_Vd_arrangement_D_index__1
+ arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1
+ arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81
+ arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81
+ arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41
+ arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81
+ arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4
+ arg_Vd_arrangement_Q___2S_0__4S_1
+ arg_Vd_arrangement_Q___4H_0__8H_1
+ arg_Vd_arrangement_Q___8B_0__16B_1
+ arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11
+ arg_Vd_arrangement_size___4S_1__2D_2
+ arg_Vd_arrangement_size___8H_0__1Q_3
+ arg_Vd_arrangement_size___8H_0__4S_1__2D_2
+ arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21
+ arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21
+ arg_Vd_arrangement_size_Q___8B_00__16B_01
+ arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11
+ arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21
+ arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
+ arg_Vd_arrangement_sz___4S_0__2D_1
+ arg_Vd_arrangement_sz_Q___2S_00__4S_01
+ arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11
+ arg_Vd_arrangement_sz_Q___2S_10__4S_11
+ arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11
+ arg_Vm_22_1__S_0__D_1
+ arg_Vm_22_2__B_0__H_1__S_2__D_3
+ arg_Vm_22_2__D_3
+ arg_Vm_22_2__H_1__S_2
+ arg_Vm_arrangement_4S
+ arg_Vm_arrangement_Q___8B_0__16B_1
+ arg_Vm_arrangement_size___8H_0__4S_1__2D_2
+ arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1
+ arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21
+ arg_Vm_arrangement_size_Q___8B_00__16B_01
+ arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31
+ arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21
+ arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
+ arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11
+ arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1
+ arg_Vn_19_4__B_1__H_2__S_4__D_8
+ arg_Vn_19_4__D_8
+ arg_Vn_19_4__H_1__S_2__D_4
+ arg_Vn_19_4__S_4__D_8
+ arg_Vn_1_arrangement_16B
+ arg_Vn_22_1__D_1
+ arg_Vn_22_1__S_0__D_1
+ arg_Vn_22_2__B_0__H_1__S_2__D_3
+ arg_Vn_22_2__D_3
+ arg_Vn_22_2__H_0__S_1__D_2
+ arg_Vn_22_2__H_1__S_2
+ arg_Vn_2_arrangement_16B
+ arg_Vn_3_arrangement_16B
+ arg_Vn_4_arrangement_16B
+ arg_Vn_arrangement_16B
+ arg_Vn_arrangement_4S
+ arg_Vn_arrangement_D_index__1
+ arg_Vn_arrangement_D_index__imm5_1
+ arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1
+ arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1
+ arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1
+ arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1
+ arg_Vn_arrangement_imm5___D_8_index__imm5_1
+ arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81
+ arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41
+ arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81
+ arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4
+ arg_Vn_arrangement_Q___8B_0__16B_1
+ arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11
+ arg_Vn_arrangement_Q_sz___4S_10
+ arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1
+ arg_Vn_arrangement_size___2D_3
+ arg_Vn_arrangement_size___8H_0__4S_1__2D_2
+ arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21
+ arg_Vn_arrangement_size_Q___8B_00__16B_01
+ arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31
+ arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11
+ arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21
+ arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
+ arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21
+ arg_Vn_arrangement_sz___2D_1
+ arg_Vn_arrangement_sz___2S_0__2D_1
+ arg_Vn_arrangement_sz___4S_0__2D_1
+ arg_Vn_arrangement_sz_Q___2S_00__4S_01
+ arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11
+ arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11
+ arg_Vt_1_arrangement_B_index__Q_S_size_1
+ arg_Vt_1_arrangement_D_index__Q_1
+ arg_Vt_1_arrangement_H_index__Q_S_size_1
+ arg_Vt_1_arrangement_S_index__Q_S_1
+ arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
+ arg_Vt_2_arrangement_B_index__Q_S_size_1
+ arg_Vt_2_arrangement_D_index__Q_1
+ arg_Vt_2_arrangement_H_index__Q_S_size_1
+ arg_Vt_2_arrangement_S_index__Q_S_1
+ arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
+ arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
+ arg_Vt_3_arrangement_B_index__Q_S_size_1
+ arg_Vt_3_arrangement_D_index__Q_1
+ arg_Vt_3_arrangement_H_index__Q_S_size_1
+ arg_Vt_3_arrangement_S_index__Q_S_1
+ arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
+ arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
+ arg_Vt_4_arrangement_B_index__Q_S_size_1
+ arg_Vt_4_arrangement_D_index__Q_1
+ arg_Vt_4_arrangement_H_index__Q_S_size_1
+ arg_Vt_4_arrangement_S_index__Q_S_1
+ arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31
+ arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31
+ arg_Wa
+ arg_Wd
+ arg_Wds
+ arg_Wm
+ arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4
+ arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31
+ arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31
+ arg_Wn
+ arg_Wns
+ arg_Ws
+ arg_Wt
+ arg_Wt2
+ arg_Xa
+ arg_Xd
+ arg_Xds
+ arg_Xm
+ arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63
+ arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63
+ arg_Xn
+ arg_Xns
+ arg_Xns_mem
+ arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1
+ arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1
+ arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1
+ arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1
+ arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1
+ arg_Xns_mem_offset
+ arg_Xns_mem_optional_imm12_16_unsigned
+ arg_Xns_mem_optional_imm12_1_unsigned
+ arg_Xns_mem_optional_imm12_2_unsigned
+ arg_Xns_mem_optional_imm12_4_unsigned
+ arg_Xns_mem_optional_imm12_8_unsigned
+ arg_Xns_mem_optional_imm7_16_signed
+ arg_Xns_mem_optional_imm7_4_signed
+ arg_Xns_mem_optional_imm7_8_signed
+ arg_Xns_mem_optional_imm9_1_signed
+ arg_Xns_mem_post_fixedimm_1
+ arg_Xns_mem_post_fixedimm_12
+ arg_Xns_mem_post_fixedimm_16
+ arg_Xns_mem_post_fixedimm_2
+ arg_Xns_mem_post_fixedimm_24
+ arg_Xns_mem_post_fixedimm_3
+ arg_Xns_mem_post_fixedimm_32
+ arg_Xns_mem_post_fixedimm_4
+ arg_Xns_mem_post_fixedimm_6
+ arg_Xns_mem_post_fixedimm_8
+ arg_Xns_mem_post_imm7_16_signed
+ arg_Xns_mem_post_imm7_4_signed
+ arg_Xns_mem_post_imm7_8_signed
+ arg_Xns_mem_post_imm9_1_signed
+ arg_Xns_mem_post_Q__16_0__32_1
+ arg_Xns_mem_post_Q__24_0__48_1
+ arg_Xns_mem_post_Q__32_0__64_1
+ arg_Xns_mem_post_Q__8_0__16_1
+ arg_Xns_mem_post_size__1_0__2_1__4_2__8_3
+ arg_Xns_mem_post_size__2_0__4_1__8_2__16_3
+ arg_Xns_mem_post_size__3_0__6_1__12_2__24_3
+ arg_Xns_mem_post_size__4_0__8_1__16_2__32_3
+ arg_Xns_mem_post_Xm
+ arg_Xns_mem_wb_imm7_16_signed
+ arg_Xns_mem_wb_imm7_4_signed
+ arg_Xns_mem_wb_imm7_8_signed
+ arg_Xns_mem_wb_imm9_1_signed
+ arg_Xs
+ arg_Xt
+ arg_Xt2
+)
diff --git a/arm64/arm64asm/condition.go b/arm64/arm64asm/condition.go
new file mode 100755
index 0000000..d673857
--- /dev/null
+++ b/arm64/arm64asm/condition.go
@@ -0,0 +1,329 @@
+// Generated by ARM internal tool
+// DO NOT EDIT
+
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+// Following functions are used as the predicator: canDecode of according instruction
+// Refer to instFormat inside decode.go for more details
+
+func at_sys_cr_system_cond(instr uint32) bool {
+ return sys_op_4((instr>>16)&0x7, 0x7, 0x8, (instr>>5)&0x7) == Sys_AT
+}
+
+func bfi_bfm_32m_bitfield_cond(instr uint32) bool {
+ return (instr>>5)&0x1f != 0x1f && uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f)
+}
+
+func bfi_bfm_64m_bitfield_cond(instr uint32) bool {
+ return (instr>>5)&0x1f != 0x1f && uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f)
+}
+
+func bfxil_bfm_32m_bitfield_cond(instr uint32) bool {
+ return uint8((instr>>10)&0x3f) >= uint8((instr>>16)&0x3f)
+}
+
+func bfxil_bfm_64m_bitfield_cond(instr uint32) bool {
+ return uint8((instr>>10)&0x3f) >= uint8((instr>>16)&0x3f)
+}
+
+func cinc_csinc_32_condsel_cond(instr uint32) bool {
+ return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func cinc_csinc_64_condsel_cond(instr uint32) bool {
+ return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func cinv_csinv_32_condsel_cond(instr uint32) bool {
+ return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func cinv_csinv_64_condsel_cond(instr uint32) bool {
+ return instr&0x1f0000 != 0x1f0000 && instr&0xe000 != 0xe000 && instr&0x3e0 != 0x3e0 && (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func cneg_csneg_32_condsel_cond(instr uint32) bool {
+ return instr&0xe000 != 0xe000 && (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func cneg_csneg_64_condsel_cond(instr uint32) bool {
+ return instr&0xe000 != 0xe000 && (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func csinc_general_cond(instr uint32) bool {
+ return instr&0xe000 != 0xe000
+}
+func csinv_general_cond(instr uint32) bool {
+ return instr&0xe000 != 0xe000
+}
+func dc_sys_cr_system_cond(instr uint32) bool {
+ return sys_op_4((instr>>16)&0x7, 0x7, (instr>>8)&0xf, (instr>>5)&0x7) == Sys_DC
+}
+
+func ic_sys_cr_system_cond(instr uint32) bool {
+ return sys_op_4((instr>>16)&0x7, 0x7, (instr>>8)&0xf, (instr>>5)&0x7) == Sys_IC
+}
+
+func lsl_ubfm_32m_bitfield_cond(instr uint32) bool {
+ return instr&0xfc00 != 0x7c00 && (instr>>10)&0x3f+1 == (instr>>16)&0x3f
+}
+
+func lsl_ubfm_64m_bitfield_cond(instr uint32) bool {
+ return instr&0xfc00 != 0xfc00 && (instr>>10)&0x3f+1 == (instr>>16)&0x3f
+}
+
+func mov_orr_32_log_imm_cond(instr uint32) bool {
+ return !move_wide_preferred_4((instr>>31)&0x1, (instr>>22)&0x1, (instr>>10)&0x3f, (instr>>16)&0x3f)
+}
+
+func mov_orr_64_log_imm_cond(instr uint32) bool {
+ return !move_wide_preferred_4((instr>>31)&0x1, (instr>>22)&0x1, (instr>>10)&0x3f, (instr>>16)&0x3f)
+}
+
+func mov_movn_32_movewide_cond(instr uint32) bool {
+ return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0) && !is_ones_n16((instr>>5)&0xffff)
+}
+
+func mov_movn_64_movewide_cond(instr uint32) bool {
+ return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0)
+}
+
+func mov_add_32_addsub_imm_cond(instr uint32) bool {
+ return instr&0x1f == 0x1f || (instr>>5)&0x1f == 0x1f
+}
+
+func mov_add_64_addsub_imm_cond(instr uint32) bool {
+ return instr&0x1f == 0x1f || (instr>>5)&0x1f == 0x1f
+}
+
+func mov_movz_32_movewide_cond(instr uint32) bool {
+ return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0)
+}
+
+func mov_movz_64_movewide_cond(instr uint32) bool {
+ return !(is_zero((instr>>5)&0xffff) && (instr>>21)&0x3 != 0x0)
+}
+
+func ror_extr_32_extract_cond(instr uint32) bool {
+ return (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func ror_extr_64_extract_cond(instr uint32) bool {
+ return (instr>>5)&0x1f == (instr>>16)&0x1f
+}
+
+func sbfiz_sbfm_32m_bitfield_cond(instr uint32) bool {
+ return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f)
+}
+
+func sbfiz_sbfm_64m_bitfield_cond(instr uint32) bool {
+ return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f)
+}
+
+func sbfx_sbfm_32m_bitfield_cond(instr uint32) bool {
+ return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f)
+}
+
+func sbfx_sbfm_64m_bitfield_cond(instr uint32) bool {
+ return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f)
+}
+
+func tlbi_sys_cr_system_cond(instr uint32) bool {
+ return sys_op_4((instr>>16)&0x7, 0x8, (instr>>8)&0xf, (instr>>5)&0x7) == Sys_TLBI
+}
+
+func ubfiz_ubfm_32m_bitfield_cond(instr uint32) bool {
+ return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f)
+}
+
+func ubfiz_ubfm_64m_bitfield_cond(instr uint32) bool {
+ return uint8((instr>>10)&0x3f) < uint8((instr>>16)&0x3f)
+}
+
+func ubfx_ubfm_32m_bitfield_cond(instr uint32) bool {
+ return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f)
+}
+
+func ubfx_ubfm_64m_bitfield_cond(instr uint32) bool {
+ return bfxpreferred_4((instr>>31)&0x1, extract_bit((instr>>29)&0x3, 1), (instr>>10)&0x3f, (instr>>16)&0x3f)
+}
+
+func fcvtzs_asisdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func fcvtzs_asimdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func fcvtzu_asisdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func fcvtzu_asimdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func mov_umov_asimdins_w_w_cond(instr uint32) bool {
+ return ((instr>>16)&0x1f)&0x7 == 0x4
+}
+
+func mov_umov_asimdins_x_x_cond(instr uint32) bool {
+ return ((instr>>16)&0x1f)&0xf == 0x8
+}
+
+func mov_orr_asimdsame_only_cond(instr uint32) bool {
+ return (instr>>16)&0x1f == (instr>>5)&0x1f
+}
+
+func rshrn_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func scvtf_asisdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func scvtf_asimdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func shl_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func shl_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func shrn_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sli_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sli_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqrshrn_asisdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqrshrn_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqrshrun_asisdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqrshrun_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshl_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshl_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshlu_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshlu_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshrn_asisdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshrn_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshrun_asisdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sqshrun_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sri_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sri_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func srshr_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func srshr_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func srsra_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func srsra_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sshll_asimdshf_l_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sshr_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sshr_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ssra_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ssra_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func sxtl_sshll_asimdshf_l_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0 && bit_count((instr>>19)&0xf) == 1
+}
+
+func ucvtf_asisdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ucvtf_asimdshf_c_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uqrshrn_asisdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uqrshrn_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uqshl_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uqshl_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uqshrn_asisdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uqshrn_asimdshf_n_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func urshr_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func urshr_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ursra_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ursra_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ushll_asimdshf_l_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ushr_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func ushr_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func usra_asisdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func usra_asimdshf_r_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0
+}
+func uxtl_ushll_asimdshf_l_cond(instr uint32) bool {
+ return instr&0x780000 != 0x0 && bit_count((instr>>19)&0xf) == 1
+}
diff --git a/arm64/arm64asm/condition_util.go b/arm64/arm64asm/condition_util.go
new file mode 100755
index 0000000..62c0c3b
--- /dev/null
+++ b/arm64/arm64asm/condition_util.go
@@ -0,0 +1,81 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+func extract_bit(value, bit uint32) uint32 {
+ return (value >> bit) & 1
+}
+
+func bfxpreferred_4(sf, opc1, imms, immr uint32) bool {
+ if imms < immr {
+ return false
+ }
+ if (imms>>5 == sf) && (imms&0x1f == 0x1f) {
+ return false
+ }
+ if immr == 0 {
+ if sf == 0 && (imms == 7 || imms == 15) {
+ return false
+ }
+ if sf == 1 && opc1 == 0 && (imms == 7 ||
+ imms == 15 || imms == 31) {
+ return false
+ }
+ }
+ return true
+}
+
+func move_wide_preferred_4(sf, N, imms, immr uint32) bool {
+ if sf == 1 && N != 1 {
+ return false
+ }
+ if sf == 0 && !(N == 0 && ((imms>>5)&1) == 0) {
+ return false
+ }
+ if imms < 16 {
+ return (-immr)%16 <= (15 - imms)
+ }
+ width := uint32(32)
+ if sf == 1 {
+ width = uint32(64)
+ }
+ if imms >= (width - 15) {
+ return (immr % 16) <= (imms - (width - 15))
+ }
+ return false
+}
+
+type Sys uint8
+
+const (
+ Sys_AT Sys = iota
+ Sys_DC
+ Sys_IC
+ Sys_TLBI
+ Sys_SYS
+)
+
+func sys_op_4(op1, crn, crm, op2 uint32) Sys {
+ // TODO: system instruction
+ return Sys_SYS
+}
+
+func is_zero(x uint32) bool {
+ return x == 0
+}
+
+func is_ones_n16(x uint32) bool {
+ return x == 0xffff
+}
+
+func bit_count(x uint32) uint8 {
+ var count uint8
+ for count = 0; x > 0; x >>= 1 {
+ if (x & 1) == 1 {
+ count++
+ }
+ }
+ return count
+}
diff --git a/arm64/arm64asm/decode.go b/arm64/arm64asm/decode.go
new file mode 100644
index 0000000..5e29c47
--- /dev/null
+++ b/arm64/arm64asm/decode.go
@@ -0,0 +1,2768 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+import (
+ "encoding/binary"
+ "fmt"
+)
+
+type instArgs [5]instArg
+
+// An instFormat describes the format of an instruction encoding.
+// An instruction with 32-bit value x matches the format if x&mask == value
+// and the predicator: canDecode(x) return true.
+type instFormat struct {
+ mask uint32
+ value uint32
+ op Op
+ // args describe how to decode the instruction arguments.
+ // args is stored as a fixed-size array.
+ // if there are fewer than len(args) arguments, args[i] == 0 marks
+ // the end of the argument list.
+ args instArgs
+ canDecode func(instr uint32) bool
+}
+
+var (
+ errShort = fmt.Errorf("truncated instruction")
+ errUnknown = fmt.Errorf("unknown instruction")
+)
+
+var decoderCover []bool
+
+func init() {
+ decoderCover = make([]bool, len(instFormats))
+}
+
+// Decode decodes the 4 bytes in src as a single instruction.
+func Decode(src []byte) (inst Inst, err error) {
+ if len(src) < 4 {
+ return Inst{}, errShort
+ }
+
+ x := binary.LittleEndian.Uint32(src)
+
+Search:
+ for i := range instFormats {
+ f := &instFormats[i]
+ if x&f.mask != f.value {
+ continue
+ }
+ if f.canDecode != nil && !f.canDecode(x) {
+ continue
+ }
+ // Decode args.
+ var args Args
+ for j, aop := range f.args {
+ if aop == 0 {
+ break
+ }
+ arg := decodeArg(aop, x)
+ if arg == nil { // Cannot decode argument
+ continue Search
+ }
+ args[j] = arg
+ }
+ decoderCover[i] = true
+ inst = Inst{
+ Op: f.op,
+ Args: args,
+ Enc: x,
+ }
+ return inst, nil
+ }
+ return Inst{}, errUnknown
+}
+
+// decodeArg decodes the arg described by aop from the instruction bits x.
+// It returns nil if x cannot be decoded according to aop.
+func decodeArg(aop instArg, x uint32) Arg {
+ switch aop {
+ default:
+ return nil
+
+ case arg_Da:
+ return D0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Dd:
+ return D0 + Reg(x&(1<<5-1))
+
+ case arg_Dm:
+ return D0 + Reg((x>>16)&(1<<5-1))
+
+ case arg_Dn:
+ return D0 + Reg((x>>5)&(1<<5-1))
+
+ case arg_Hd:
+ return H0 + Reg(x&(1<<5-1))
+
+ case arg_Hn:
+ return H0 + Reg((x>>5)&(1<<5-1))
+
+ case arg_IAddSub:
+ imm12 := (x >> 10) & (1<<12 - 1)
+ shift := (x >> 22) & (1<<2 - 1)
+ if shift > 1 {
+ return nil
+ }
+ shift = shift * 12
+ return ImmShift{uint16(imm12), uint8(shift)}
+
+ case arg_Sa:
+ return S0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Sd:
+ return S0 + Reg(x&(1<<5-1))
+
+ case arg_Sm:
+ return S0 + Reg((x>>16)&(1<<5-1))
+
+ case arg_Sn:
+ return S0 + Reg((x>>5)&(1<<5-1))
+
+ case arg_Wa:
+ return W0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Wd:
+ return W0 + Reg(x&(1<<5-1))
+
+ case arg_Wds:
+ return RegSP(W0) + RegSP(x&(1<<5-1))
+
+ case arg_Wm:
+ return W0 + Reg((x>>16)&(1<<5-1))
+
+ case arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
+ return handle_ExtendedRegister(x, true)
+
+ case arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
+ return handle_ExtendedRegister(x, false)
+
+ case arg_Wn:
+ return W0 + Reg((x>>5)&(1<<5-1))
+
+ case arg_Wns:
+ return RegSP(W0) + RegSP((x>>5)&(1<<5-1))
+
+ case arg_Xa:
+ return X0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Xd:
+ return X0 + Reg(x&(1<<5-1))
+
+ case arg_Xds:
+ return RegSP(X0) + RegSP(x&(1<<5-1))
+
+ case arg_Xm:
+ return X0 + Reg((x>>16)&(1<<5-1))
+
+ case arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31:
+ return handle_ImmediateShiftedRegister(x, 31, true, false)
+
+ case arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31:
+ return handle_ImmediateShiftedRegister(x, 31, true, true)
+
+ case arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63:
+ return handle_ImmediateShiftedRegister(x, 63, false, false)
+
+ case arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63:
+ return handle_ImmediateShiftedRegister(x, 63, false, true)
+
+ case arg_Xn:
+ return X0 + Reg((x>>5)&(1<<5-1))
+
+ case arg_Xns:
+ return RegSP(X0) + RegSP((x>>5)&(1<<5-1))
+
+ case arg_slabel_imm14_2:
+ imm14 := ((x >> 5) & (1<<14 - 1))
+ return PCRel(((int64(imm14) << 2) << 48) >> 48)
+
+ case arg_slabel_imm19_2:
+ imm19 := ((x >> 5) & (1<<19 - 1))
+ return PCRel(((int64(imm19) << 2) << 43) >> 43)
+
+ case arg_slabel_imm26_2:
+ imm26 := (x & (1<<26 - 1))
+ return PCRel(((int64(imm26) << 2) << 36) >> 36)
+
+ case arg_slabel_immhi_immlo_0:
+ immhi := ((x >> 5) & (1<<19 - 1))
+ immlo := ((x >> 29) & (1<<2 - 1))
+ immhilo := (immhi)<<2 | immlo
+ return PCRel((int64(immhilo) << 43) >> 43)
+
+ case arg_slabel_immhi_immlo_12:
+ immhi := ((x >> 5) & (1<<19 - 1))
+ immlo := ((x >> 29) & (1<<2 - 1))
+ immhilo := (immhi)<<2 | immlo
+ return PCRel(((int64(immhilo) << 12) << 31) >> 31)
+
+ case arg_Xns_mem:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrOffset, 0}
+
+ case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1:
+ return handle_MemExtend(x, 1, false)
+
+ case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1:
+ return handle_MemExtend(x, 2, false)
+
+ case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1:
+ return handle_MemExtend(x, 3, false)
+
+ case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1:
+ return handle_MemExtend(x, 1, true)
+
+ case arg_Xns_mem_optional_imm12_1_unsigned:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm12 := (x >> 10) & (1<<12 - 1)
+ return MemImmediate{Rn, AddrOffset, int32(imm12)}
+
+ case arg_Xns_mem_optional_imm12_2_unsigned:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm12 := (x >> 10) & (1<<12 - 1)
+ return MemImmediate{Rn, AddrOffset, int32(imm12 << 1)}
+
+ case arg_Xns_mem_optional_imm12_4_unsigned:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm12 := (x >> 10) & (1<<12 - 1)
+ return MemImmediate{Rn, AddrOffset, int32(imm12 << 2)}
+
+ case arg_Xns_mem_optional_imm12_8_unsigned:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm12 := (x >> 10) & (1<<12 - 1)
+ return MemImmediate{Rn, AddrOffset, int32(imm12 << 3)}
+
+ case arg_Xns_mem_optional_imm7_4_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 2)) << 23) >> 23}
+
+ case arg_Xns_mem_optional_imm7_8_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 3)) << 22) >> 22}
+
+ case arg_Xns_mem_optional_imm9_1_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm9 := (x >> 12) & (1<<9 - 1)
+ return MemImmediate{Rn, AddrOffset, (int32(imm9) << 23) >> 23}
+
+ case arg_Xns_mem_post_imm7_4_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 2)) << 23) >> 23}
+
+ case arg_Xns_mem_post_imm7_8_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 3)) << 22) >> 22}
+
+ case arg_Xns_mem_post_imm9_1_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm9 := (x >> 12) & (1<<9 - 1)
+ return MemImmediate{Rn, AddrPostIndex, ((int32(imm9)) << 23) >> 23}
+
+ case arg_Xns_mem_wb_imm7_4_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 2)) << 23) >> 23}
+
+ case arg_Xns_mem_wb_imm7_8_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 3)) << 22) >> 22}
+
+ case arg_Xns_mem_wb_imm9_1_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm9 := (x >> 12) & (1<<9 - 1)
+ return MemImmediate{Rn, AddrPreIndex, ((int32(imm9)) << 23) >> 23}
+
+ case arg_Ws:
+ return W0 + Reg((x>>16)&(1<<5-1))
+
+ case arg_Wt:
+ return W0 + Reg(x&(1<<5-1))
+
+ case arg_Wt2:
+ return W0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Xs:
+ return X0 + Reg((x>>16)&(1<<5-1))
+
+ case arg_Xt:
+ return X0 + Reg(x&(1<<5-1))
+
+ case arg_Xt2:
+ return X0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_immediate_0_127_CRm_op2:
+ crm_op2 := (x >> 5) & (1<<7 - 1)
+ return Imm_hint(crm_op2)
+
+ case arg_immediate_0_15_CRm:
+ crm := (x >> 8) & (1<<4 - 1)
+ return Imm{crm, false}
+
+ case arg_immediate_0_15_nzcv:
+ nzcv := x & (1<<4 - 1)
+ return Imm{nzcv, false}
+
+ case arg_immediate_0_31_imm5:
+ imm5 := (x >> 16) & (1<<5 - 1)
+ return Imm{imm5, false}
+
+ case arg_immediate_0_31_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{immr, false}
+
+ case arg_immediate_0_31_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ if imms > 31 {
+ return nil
+ }
+ return Imm{imms, true}
+
+ case arg_immediate_0_63_b5_b40:
+ b5 := (x >> 31) & 1
+ b40 := (x >> 19) & (1<<5 - 1)
+ return Imm{(b5 << 5) | b40, true}
+
+ case arg_immediate_0_63_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{immr, false}
+
+ case arg_immediate_0_63_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ return Imm{imms, true}
+
+ case arg_immediate_0_65535_imm16:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ return Imm{imm16, false}
+
+ case arg_immediate_0_7_op1:
+ op1 := (x >> 16) & (1<<3 - 1)
+ return Imm{op1, true}
+
+ case arg_immediate_0_7_op2:
+ op2 := (x >> 5) & (1<<3 - 1)
+ return Imm{op2, true}
+
+ case arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{immr, true}
+
+ case arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{immr, true}
+
+ case arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{32 - immr, true}
+
+ case arg_immediate_BFI_BFM_32M_bitfield_width_32_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ if imms > 31 {
+ return nil
+ }
+ return Imm{imms + 1, true}
+
+ case arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{64 - immr, true}
+
+ case arg_immediate_BFI_BFM_64M_bitfield_width_64_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ return Imm{imms + 1, true}
+
+ case arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{immr, true}
+
+ case arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms:
+ immr := (x >> 16) & (1<<6 - 1)
+ imms := (x >> 10) & (1<<6 - 1)
+ width := imms - immr + 1
+ if width < 1 || width > 32-immr {
+ return nil
+ }
+ return Imm{width, true}
+
+ case arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{immr, true}
+
+ case arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms:
+ immr := (x >> 16) & (1<<6 - 1)
+ imms := (x >> 10) & (1<<6 - 1)
+ width := imms - immr + 1
+ if width < 1 || width > 64-immr {
+ return nil
+ }
+ return Imm{width, true}
+
+ case arg_immediate_bitmask_32_imms_immr:
+ return handle_bitmasks(x, 32)
+
+ case arg_immediate_bitmask_64_N_imms_immr:
+ return handle_bitmasks(x, 64)
+
+ case arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr:
+ imms := (x >> 10) & (1<<6 - 1)
+ shift := 31 - imms
+ if shift > 31 {
+ return nil
+ }
+ return Imm{shift, true}
+
+ case arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr:
+ imms := (x >> 10) & (1<<6 - 1)
+ shift := 63 - imms
+ if shift > 63 {
+ return nil
+ }
+ return Imm{shift, true}
+
+ case arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{immr, true}
+
+ case arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{immr, true}
+
+ case arg_immediate_optional_0_15_CRm:
+ crm := (x >> 8) & (1<<4 - 1)
+ return Imm_clrex(crm)
+
+ case arg_immediate_optional_0_65535_imm16:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ return Imm_dcps(imm16)
+
+ case arg_immediate_OptLSL_amount_16_0_16:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ hw := (x >> 21) & (1<<2 - 1)
+ shift := hw * 16
+ if shift > 16 {
+ return nil
+ }
+ return ImmShift{uint16(imm16), uint8(shift)}
+
+ case arg_immediate_OptLSL_amount_16_0_48:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ hw := (x >> 21) & (1<<2 - 1)
+ shift := hw * 16
+ return ImmShift{uint16(imm16), uint8(shift)}
+
+ case arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{32 - immr, true}
+
+ case arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ if imms > 31 {
+ return nil
+ }
+ return Imm{imms + 1, true}
+
+ case arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{64 - immr, true}
+
+ case arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ return Imm{imms + 1, true}
+
+ case arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{immr, true}
+
+ case arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms:
+ immr := (x >> 16) & (1<<6 - 1)
+ imms := (x >> 10) & (1<<6 - 1)
+ width := imms - immr + 1
+ if width < 1 || width > 32-immr {
+ return nil
+ }
+ return Imm{width, true}
+
+ case arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{immr, true}
+
+ case arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms:
+ immr := (x >> 16) & (1<<6 - 1)
+ imms := (x >> 10) & (1<<6 - 1)
+ width := imms - immr + 1
+ if width < 1 || width > 64-immr {
+ return nil
+ }
+ return Imm{width, true}
+
+ case arg_immediate_shift_32_implicit_imm16_hw:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ hw := (x >> 21) & (1<<2 - 1)
+ shift := hw * 16
+ if shift > 16 {
+ return nil
+ }
+ result := uint32(imm16) << shift
+ return Imm{result, false}
+
+ case arg_immediate_shift_32_implicit_inverse_imm16_hw:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ hw := (x >> 21) & (1<<2 - 1)
+ shift := hw * 16
+ if shift > 16 {
+ return nil
+ }
+ result := uint32(imm16) << shift
+ return Imm{^result, false}
+
+ case arg_immediate_shift_64_implicit_imm16_hw:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ hw := (x >> 21) & (1<<2 - 1)
+ shift := hw * 16
+ result := uint64(imm16) << shift
+ return Imm64{result, false}
+
+ case arg_immediate_shift_64_implicit_inverse_imm16_hw:
+ imm16 := (x >> 5) & (1<<16 - 1)
+ hw := (x >> 21) & (1<<2 - 1)
+ shift := hw * 16
+ result := uint64(imm16) << shift
+ return Imm64{^result, false}
+
+ case arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{32 - immr, true}
+
+ case arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ if imms > 31 {
+ return nil
+ }
+ return Imm{imms + 1, true}
+
+ case arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{64 - immr, true}
+
+ case arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms:
+ imms := (x >> 10) & (1<<6 - 1)
+ return Imm{imms + 1, true}
+
+ case arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ if immr > 31 {
+ return nil
+ }
+ return Imm{immr, true}
+
+ case arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms:
+ immr := (x >> 16) & (1<<6 - 1)
+ imms := (x >> 10) & (1<<6 - 1)
+ width := imms - immr + 1
+ if width < 1 || width > 32-immr {
+ return nil
+ }
+ return Imm{width, true}
+
+ case arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr:
+ immr := (x >> 16) & (1<<6 - 1)
+ return Imm{immr, true}
+
+ case arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms:
+ immr := (x >> 16) & (1<<6 - 1)
+ imms := (x >> 10) & (1<<6 - 1)
+ width := imms - immr + 1
+ if width < 1 || width > 64-immr {
+ return nil
+ }
+ return Imm{width, true}
+
+ case arg_Rt_31_1__W_0__X_1:
+ b5 := (x >> 31) & 1
+ Rt := x & (1<<5 - 1)
+ if b5 == 0 {
+ return W0 + Reg(Rt)
+ } else {
+ return X0 + Reg(Rt)
+ }
+
+ case arg_cond_AllowALNV_Normal:
+ cond := (x >> 12) & (1<<4 - 1)
+ return Cond{uint8(cond), false}
+
+ case arg_conditional:
+ cond := x & (1<<4 - 1)
+ return Cond{uint8(cond), false}
+
+ case arg_cond_NotAllowALNV_Invert:
+ cond := (x >> 12) & (1<<4 - 1)
+ if (cond >> 1) == 7 {
+ return nil
+ }
+ return Cond{uint8(cond), true}
+
+ case arg_Cm:
+ CRm := (x >> 8) & (1<<4 - 1)
+ return Imm_c(CRm)
+
+ case arg_Cn:
+ CRn := (x >> 12) & (1<<4 - 1)
+ return Imm_c(CRn)
+
+ case arg_option_DMB_BO_system_CRm:
+ CRm := (x >> 8) & (1<<4 - 1)
+ return Imm_option(CRm)
+
+ case arg_option_DSB_BO_system_CRm:
+ CRm := (x >> 8) & (1<<4 - 1)
+ return Imm_option(CRm)
+
+ case arg_option_ISB_BI_system_CRm:
+ CRm := (x >> 8) & (1<<4 - 1)
+ if CRm == 15 {
+ return Imm_option(CRm)
+ }
+ return Imm{CRm, false}
+
+ case arg_prfop_Rt:
+ Rt := x & (1<<5 - 1)
+ return Imm_prfop(Rt)
+
+ case arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37:
+ op1 := (x >> 16) & (1<<3 - 1)
+ op2 := (x >> 5) & (1<<3 - 1)
+ if (op1 == 0) && (op2 == 5) {
+ return SPSel
+ } else if (op1 == 3) && (op2 == 6) {
+ return DAIFSet
+ } else if (op1 == 3) && (op2 == 7) {
+ return DAIFClr
+ }
+ return nil
+
+ case arg_sysreg_o0_op1_CRn_CRm_op2:
+ op0 := (x >> 19) & (1<<2 - 1)
+ op1 := (x >> 16) & (1<<3 - 1)
+ CRn := (x >> 12) & (1<<4 - 1)
+ CRm := (x >> 8) & (1<<4 - 1)
+ op2 := (x >> 5) & (1<<3 - 1)
+ return Systemreg{uint8(op0), uint8(op1), uint8(CRn), uint8(CRm), uint8(op2)}
+
+ case arg_sysop_AT_SYS_CR_system:
+ //TODO: system instruction
+ return nil
+
+ case arg_sysop_DC_SYS_CR_system:
+ //TODO: system instruction
+ return nil
+
+ case arg_sysop_SYS_CR_system:
+ //TODO: system instruction
+ return nil
+
+ case arg_sysop_TLBI_SYS_CR_system:
+ //TODO: system instruction
+ return nil
+
+ case arg_Bt:
+ return B0 + Reg(x&(1<<5-1))
+
+ case arg_Dt:
+ return D0 + Reg(x&(1<<5-1))
+
+ case arg_Dt2:
+ return D0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Ht:
+ return H0 + Reg(x&(1<<5-1))
+
+ case arg_immediate_0_63_immh_immb__UIntimmhimmb64_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ if (immh & 8) == 0 {
+ return nil
+ }
+ immb := (x >> 16) & (1<<3 - 1)
+ return Imm{(immh << 3) + immb - 64, true}
+
+ case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4:
+ immh := (x >> 19) & (1<<4 - 1)
+ immb := (x >> 16) & (1<<3 - 1)
+ if immh == 1 {
+ return Imm{(immh << 3) + immb - 8, true}
+ } else if (immh >> 1) == 1 {
+ return Imm{(immh << 3) + immb - 16, true}
+ } else if (immh >> 2) == 1 {
+ return Imm{(immh << 3) + immb - 32, true}
+ } else {
+ return nil
+ }
+
+ case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
+ fallthrough
+
+ case arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ immb := (x >> 16) & (1<<3 - 1)
+ if immh == 1 {
+ return Imm{(immh << 3) + immb - 8, true}
+ } else if (immh >> 1) == 1 {
+ return Imm{(immh << 3) + immb - 16, true}
+ } else if (immh >> 2) == 1 {
+ return Imm{(immh << 3) + immb - 32, true}
+ } else if (immh >> 3) == 1 {
+ return Imm{(immh << 3) + immb - 64, true}
+ } else {
+ return nil
+ }
+
+ case arg_immediate_0_width_size__8_0__16_1__32_2:
+ size := (x >> 22) & (1<<2 - 1)
+ switch size {
+ case 0:
+ return Imm{8, true}
+ case 1:
+ return Imm{16, true}
+ case 2:
+ return Imm{32, true}
+ default:
+ return nil
+ }
+
+ case arg_immediate_1_64_immh_immb__128UIntimmhimmb_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ if (immh & 8) == 0 {
+ return nil
+ }
+ immb := (x >> 16) & (1<<3 - 1)
+ return Imm{128 - ((immh << 3) + immb), true}
+
+ case arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
+ fallthrough
+
+ case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
+ immh := (x >> 19) & (1<<4 - 1)
+ immb := (x >> 16) & (1<<3 - 1)
+ if immh == 1 {
+ return Imm{16 - ((immh << 3) + immb), true}
+ } else if (immh >> 1) == 1 {
+ return Imm{32 - ((immh << 3) + immb), true}
+ } else if (immh >> 2) == 1 {
+ return Imm{64 - ((immh << 3) + immb), true}
+ } else {
+ return nil
+ }
+
+ case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ immb := (x >> 16) & (1<<3 - 1)
+ if immh == 1 {
+ return Imm{16 - ((immh << 3) + immb), true}
+ } else if (immh >> 1) == 1 {
+ return Imm{32 - ((immh << 3) + immb), true}
+ } else if (immh >> 2) == 1 {
+ return Imm{64 - ((immh << 3) + immb), true}
+ } else if (immh >> 3) == 1 {
+ return Imm{128 - ((immh << 3) + immb), true}
+ } else {
+ return nil
+ }
+
+ case arg_immediate_8x8_a_b_c_d_e_f_g_h:
+ var imm uint64
+ if x&(1<<5) != 0 {
+ imm = (1 << 8) - 1
+ } else {
+ imm = 0
+ }
+ if x&(1<<6) != 0 {
+ imm += ((1 << 8) - 1) << 8
+ }
+ if x&(1<<7) != 0 {
+ imm += ((1 << 8) - 1) << 16
+ }
+ if x&(1<<8) != 0 {
+ imm += ((1 << 8) - 1) << 24
+ }
+ if x&(1<<9) != 0 {
+ imm += ((1 << 8) - 1) << 32
+ }
+ if x&(1<<16) != 0 {
+ imm += ((1 << 8) - 1) << 40
+ }
+ if x&(1<<17) != 0 {
+ imm += ((1 << 8) - 1) << 48
+ }
+ if x&(1<<18) != 0 {
+ imm += ((1 << 8) - 1) << 56
+ }
+ return Imm64{imm, false}
+
+ case arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h:
+ pre := (x >> 5) & (1<<4 - 1)
+ exp := 1 - ((x >> 17) & 1)
+ exp = (exp << 2) + (((x >> 16) & 1) << 1) + ((x >> 9) & 1)
+ s := ((x >> 18) & 1)
+ return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)}
+
+ case arg_immediate_exp_3_pre_4_imm8:
+ pre := (x >> 13) & (1<<4 - 1)
+ exp := 1 - ((x >> 19) & 1)
+ exp = (exp << 2) + ((x >> 17) & (1<<2 - 1))
+ s := ((x >> 20) & 1)
+ return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)}
+
+ case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8:
+ fallthrough
+
+ case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ immb := (x >> 16) & (1<<3 - 1)
+ if (immh >> 2) == 1 {
+ return Imm{64 - ((immh << 3) + immb), true}
+ } else if (immh >> 3) == 1 {
+ return Imm{128 - ((immh << 3) + immb), true}
+ } else {
+ return nil
+ }
+
+ case arg_immediate_fbits_min_1_max_32_sub_64_scale:
+ scale := (x >> 10) & (1<<6 - 1)
+ fbits := 64 - scale
+ if fbits > 32 {
+ return nil
+ }
+ return Imm{fbits, true}
+
+ case arg_immediate_fbits_min_1_max_64_sub_64_scale:
+ scale := (x >> 10) & (1<<6 - 1)
+ fbits := 64 - scale
+ return Imm{fbits, true}
+
+ case arg_immediate_floatzero:
+ return Imm{0, true}
+
+ case arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10:
+ Q := (x >> 30) & 1
+ imm4 := (x >> 11) & (1<<4 - 1)
+ if Q == 1 || (imm4>>3) == 0 {
+ return Imm{imm4, true}
+ } else {
+ return nil
+ }
+
+ case arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1:
+ var shift uint8
+ imm8 := (x >> 16) & (1<<3 - 1)
+ imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
+ if (x>>12)&1 == 0 {
+ shift = 8 + 128
+ } else {
+ shift = 16 + 128
+ }
+ return ImmShift{uint16(imm8), shift}
+
+ case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1:
+ imm8 := (x >> 16) & (1<<3 - 1)
+ imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
+ cmode1 := (x >> 13) & 1
+ shift := 8 * cmode1
+ return ImmShift{uint16(imm8), uint8(shift)}
+
+ case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3:
+ imm8 := (x >> 16) & (1<<3 - 1)
+ imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
+ cmode1 := (x >> 13) & (1<<2 - 1)
+ shift := 8 * cmode1
+ return ImmShift{uint16(imm8), uint8(shift)}
+
+ case arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h:
+ imm8 := (x >> 16) & (1<<3 - 1)
+ imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
+ return ImmShift{uint16(imm8), 0}
+
+ case arg_immediate_zero:
+ return Imm{0, true}
+
+ case arg_Qd:
+ return Q0 + Reg(x&(1<<5-1))
+
+ case arg_Qn:
+ return Q0 + Reg((x>>5)&(1<<5-1))
+
+ case arg_Qt:
+ return Q0 + Reg(x&(1<<5-1))
+
+ case arg_Qt2:
+ return Q0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Rn_16_5__W_1__W_2__W_4__X_8:
+ imm5 := (x >> 16) & (1<<5 - 1)
+ if ((imm5 & 1) == 1) || ((imm5 & 2) == 2) || ((imm5 & 4) == 4) {
+ return W0 + Reg((x>>5)&(1<<5-1))
+ } else if (imm5 & 8) == 8 {
+ return X0 + Reg((x>>5)&(1<<5-1))
+ } else {
+ return nil
+ }
+
+ case arg_St:
+ return S0 + Reg(x&(1<<5-1))
+
+ case arg_St2:
+ return S0 + Reg((x>>10)&(1<<5-1))
+
+ case arg_Vd_16_5__B_1__H_2__S_4__D_8:
+ imm5 := (x >> 16) & (1<<5 - 1)
+ Rd := x & (1<<5 - 1)
+ if imm5&1 == 1 {
+ return B0 + Reg(Rd)
+ } else if imm5&2 == 2 {
+ return H0 + Reg(Rd)
+ } else if imm5&4 == 4 {
+ return S0 + Reg(Rd)
+ } else if imm5&8 == 8 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_19_4__B_1__H_2__S_4:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rd := x & (1<<5 - 1)
+ if immh == 1 {
+ return B0 + Reg(Rd)
+ } else if immh>>1 == 1 {
+ return H0 + Reg(Rd)
+ } else if immh>>2 == 1 {
+ return S0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_19_4__B_1__H_2__S_4__D_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rd := x & (1<<5 - 1)
+ if immh == 1 {
+ return B0 + Reg(Rd)
+ } else if immh>>1 == 1 {
+ return H0 + Reg(Rd)
+ } else if immh>>2 == 1 {
+ return S0 + Reg(Rd)
+ } else if immh>>3 == 1 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_19_4__D_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rd := x & (1<<5 - 1)
+ if immh>>3 == 1 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_19_4__S_4__D_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rd := x & (1<<5 - 1)
+ if immh>>2 == 1 {
+ return S0 + Reg(Rd)
+ } else if immh>>3 == 1 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_1__S_0:
+ sz := (x >> 22) & 1
+ Rd := x & (1<<5 - 1)
+ if sz == 0 {
+ return S0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_1__S_0__D_1:
+ sz := (x >> 22) & 1
+ Rd := x & (1<<5 - 1)
+ if sz == 0 {
+ return S0 + Reg(Rd)
+ } else {
+ return D0 + Reg(Rd)
+ }
+
+ case arg_Vd_22_1__S_1:
+ sz := (x >> 22) & 1
+ Rd := x & (1<<5 - 1)
+ if sz == 1 {
+ return S0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_2__B_0__H_1__S_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rd := x & (1<<5 - 1)
+ if size == 0 {
+ return B0 + Reg(Rd)
+ } else if size == 1 {
+ return H0 + Reg(Rd)
+ } else if size == 2 {
+ return S0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_2__B_0__H_1__S_2__D_3:
+ size := (x >> 22) & (1<<2 - 1)
+ Rd := x & (1<<5 - 1)
+ if size == 0 {
+ return B0 + Reg(Rd)
+ } else if size == 1 {
+ return H0 + Reg(Rd)
+ } else if size == 2 {
+ return S0 + Reg(Rd)
+ } else {
+ return D0 + Reg(Rd)
+ }
+
+ case arg_Vd_22_2__D_3:
+ size := (x >> 22) & (1<<2 - 1)
+ Rd := x & (1<<5 - 1)
+ if size == 3 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_2__H_0__S_1__D_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rd := x & (1<<5 - 1)
+ if size == 0 {
+ return H0 + Reg(Rd)
+ } else if size == 1 {
+ return S0 + Reg(Rd)
+ } else if size == 2 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_2__H_1__S_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rd := x & (1<<5 - 1)
+ if size == 1 {
+ return H0 + Reg(Rd)
+ } else if size == 2 {
+ return S0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_22_2__S_1__D_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rd := x & (1<<5 - 1)
+ if size == 1 {
+ return S0 + Reg(Rd)
+ } else if size == 2 {
+ return D0 + Reg(Rd)
+ } else {
+ return nil
+ }
+
+ case arg_Vd_arrangement_16B:
+ Rd := x & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+
+ case arg_Vd_arrangement_2D:
+ Rd := x & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+
+ case arg_Vd_arrangement_4S:
+ Rd := x & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+
+ case arg_Vd_arrangement_D_index__1:
+ Rd := x & (1<<5 - 1)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rd), ArrangementD, 1, 0}
+
+ case arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1:
+ var a Arrangement
+ var index uint32
+ Rd := x & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ if imm5&1 == 1 {
+ a = ArrangementB
+ index = imm5 >> 1
+ } else if imm5&2 == 2 {
+ a = ArrangementH
+ index = imm5 >> 2
+ } else if imm5&4 == 4 {
+ a = ArrangementS
+ index = imm5 >> 3
+ } else if imm5&8 == 8 {
+ a = ArrangementD
+ index = imm5 >> 4
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rd), a, uint8(index), 0}
+
+ case arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
+ Rd := x & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ if imm5&1 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ }
+ } else if imm5&2 == 2 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ }
+ } else if imm5&4 == 4 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ } else if (imm5&8 == 8) && (Q == 1) {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ } else {
+ return nil
+ }
+
+ case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81:
+ Rd := x & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ Q := (x >> 30) & 1
+ if immh>>2 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ } else if immh>>3 == 1 {
+ if Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ }
+ return nil
+
+ case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41:
+ Rd := x & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ Q := (x >> 30) & 1
+ if immh == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ }
+ } else if immh>>1 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ }
+ } else if immh>>2 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ }
+ return nil
+
+ case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
+ Rd := x & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ Q := (x >> 30) & 1
+ if immh == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ }
+ } else if immh>>1 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ }
+ } else if immh>>2 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ } else if immh>>3 == 1 {
+ if Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ }
+ return nil
+
+ case arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4:
+ Rd := x & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ if immh == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if immh>>1 == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if immh>>2 == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_Q___2S_0__4S_1:
+ Rd := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+
+ case arg_Vd_arrangement_Q___4H_0__8H_1:
+ Rd := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ }
+
+ case arg_Vd_arrangement_Q___8B_0__16B_1:
+ Rd := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ }
+
+ case arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11:
+ Rd := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ sz := (x >> 22) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if sz == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size___4S_1__2D_2:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ if size == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if size == 2 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size___8H_0__1Q_3:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ if size == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if size == 3 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1Q, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size___8H_0__4S_1__2D_2:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ if size == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if size == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if size == 2 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1D, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size_Q___8B_00__16B_01:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+ Rd := x & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_sz___4S_0__2D_1:
+ Rd := x & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ if sz == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+
+ case arg_Vd_arrangement_sz_Q___2S_00__4S_01:
+ Rd := x & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11:
+ Rd := x & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ } else if sz == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_sz_Q___2S_10__4S_11:
+ Rd := x & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else if sz == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11:
+ Rd := x & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
+ } else if sz == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
+ } else /* sz == 1 && Q == 1 */ {
+ return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
+ }
+
+ case arg_Vm_22_1__S_0__D_1:
+ sz := (x >> 22) & 1
+ Rm := (x >> 16) & (1<<5 - 1)
+ if sz == 0 {
+ return S0 + Reg(Rm)
+ } else {
+ return D0 + Reg(Rm)
+ }
+
+ case arg_Vm_22_2__B_0__H_1__S_2__D_3:
+ size := (x >> 22) & (1<<2 - 1)
+ Rm := (x >> 16) & (1<<5 - 1)
+ if size == 0 {
+ return B0 + Reg(Rm)
+ } else if size == 1 {
+ return H0 + Reg(Rm)
+ } else if size == 2 {
+ return S0 + Reg(Rm)
+ } else {
+ return D0 + Reg(Rm)
+ }
+
+ case arg_Vm_22_2__D_3:
+ size := (x >> 22) & (1<<2 - 1)
+ Rm := (x >> 16) & (1<<5 - 1)
+ if size == 3 {
+ return D0 + Reg(Rm)
+ } else {
+ return nil
+ }
+
+ case arg_Vm_22_2__H_1__S_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rm := (x >> 16) & (1<<5 - 1)
+ if size == 1 {
+ return H0 + Reg(Rm)
+ } else if size == 2 {
+ return S0 + Reg(Rm)
+ } else {
+ return nil
+ }
+
+ case arg_Vm_arrangement_4S:
+ Rm := (x >> 16) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
+
+ case arg_Vm_arrangement_Q___8B_0__16B_1:
+ Rm := (x >> 16) & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
+ }
+
+ case arg_Vm_arrangement_size___8H_0__4S_1__2D_2:
+ Rm := (x >> 16) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ if size == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
+ } else if size == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
+ } else if size == 2 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1:
+ var a Arrangement
+ var index uint32
+ var vm uint32
+ Rm := (x >> 16) & (1<<4 - 1)
+ size := (x >> 22) & 3
+ H := (x >> 11) & 1
+ L := (x >> 21) & 1
+ M := (x >> 20) & 1
+ if size == 1 {
+ a = ArrangementH
+ index = (H << 2) | (L << 1) | M
+ vm = Rm
+ } else if size == 2 {
+ a = ArrangementS
+ index = (H << 1) | L
+ vm = (M << 4) | Rm
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(vm), a, uint8(index), 0}
+
+ case arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
+ Rm := (x >> 16) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_size_Q___8B_00__16B_01:
+ Rm := (x >> 16) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31:
+ Rm := (x >> 16) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
+ } else if size == 3 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement1D, 0}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
+ Rm := (x >> 16) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+ Rm := (x >> 16) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11:
+ Rm := (x >> 16) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
+ } else if sz == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1:
+ var a Arrangement
+ var index uint32
+ Rm := (x >> 16) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ H := (x >> 11) & 1
+ L := (x >> 21) & 1
+ if sz == 0 {
+ a = ArrangementS
+ index = (H << 1) | L
+ } else if sz == 1 && L == 0 {
+ a = ArrangementD
+ index = H
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rm), a, uint8(index), 0}
+
+ case arg_Vn_19_4__B_1__H_2__S_4__D_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if immh == 1 {
+ return B0 + Reg(Rn)
+ } else if immh>>1 == 1 {
+ return H0 + Reg(Rn)
+ } else if immh>>2 == 1 {
+ return S0 + Reg(Rn)
+ } else if immh>>3 == 1 {
+ return D0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_19_4__D_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if immh>>3 == 1 {
+ return D0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_19_4__H_1__S_2__D_4:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if immh == 1 {
+ return H0 + Reg(Rn)
+ } else if immh>>1 == 1 {
+ return S0 + Reg(Rn)
+ } else if immh>>2 == 1 {
+ return D0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_19_4__S_4__D_8:
+ immh := (x >> 19) & (1<<4 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if immh>>2 == 1 {
+ return S0 + Reg(Rn)
+ } else if immh>>3 == 1 {
+ return D0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_1_arrangement_16B:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 1}
+
+ case arg_Vn_22_1__D_1:
+ sz := (x >> 22) & 1
+ Rn := (x >> 5) & (1<<5 - 1)
+ if sz == 1 {
+ return D0 + Reg(Rn)
+ }
+ return nil
+
+ case arg_Vn_22_1__S_0__D_1:
+ sz := (x >> 22) & 1
+ Rn := (x >> 5) & (1<<5 - 1)
+ if sz == 0 {
+ return S0 + Reg(Rn)
+ } else {
+ return D0 + Reg(Rn)
+ }
+
+ case arg_Vn_22_2__B_0__H_1__S_2__D_3:
+ size := (x >> 22) & (1<<2 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if size == 0 {
+ return B0 + Reg(Rn)
+ } else if size == 1 {
+ return H0 + Reg(Rn)
+ } else if size == 2 {
+ return S0 + Reg(Rn)
+ } else {
+ return D0 + Reg(Rn)
+ }
+
+ case arg_Vn_22_2__D_3:
+ size := (x >> 22) & (1<<2 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if size == 3 {
+ return D0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_22_2__H_0__S_1__D_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if size == 0 {
+ return H0 + Reg(Rn)
+ } else if size == 1 {
+ return S0 + Reg(Rn)
+ } else if size == 2 {
+ return D0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_22_2__H_1__S_2:
+ size := (x >> 22) & (1<<2 - 1)
+ Rn := (x >> 5) & (1<<5 - 1)
+ if size == 1 {
+ return H0 + Reg(Rn)
+ } else if size == 2 {
+ return S0 + Reg(Rn)
+ } else {
+ return nil
+ }
+
+ case arg_Vn_2_arrangement_16B:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 2}
+
+ case arg_Vn_3_arrangement_16B:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 3}
+
+ case arg_Vn_4_arrangement_16B:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 4}
+
+ case arg_Vn_arrangement_16B:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+
+ case arg_Vn_arrangement_4S:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+
+ case arg_Vn_arrangement_D_index__1:
+ Rn := (x >> 5) & (1<<5 - 1)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, 1, 0}
+
+ case arg_Vn_arrangement_D_index__imm5_1:
+ Rn := (x >> 5) & (1<<5 - 1)
+ index := (x >> 20) & 1
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, uint8(index), 0}
+
+ case arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1:
+ var a Arrangement
+ var index uint32
+ Rn := (x >> 5) & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ if imm5&1 == 1 {
+ a = ArrangementB
+ index = imm5 >> 1
+ } else if imm5&2 == 2 {
+ a = ArrangementH
+ index = imm5 >> 2
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
+
+ case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1:
+ var a Arrangement
+ var index uint32
+ Rn := (x >> 5) & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ imm4 := (x >> 11) & (1<<4 - 1)
+ if imm5&1 == 1 {
+ a = ArrangementB
+ index = imm4
+ } else if imm5&2 == 2 {
+ a = ArrangementH
+ index = imm4 >> 1
+ } else if imm5&4 == 4 {
+ a = ArrangementS
+ index = imm4 >> 2
+ } else if imm5&8 == 8 {
+ a = ArrangementD
+ index = imm4 >> 3
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
+
+ case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1:
+ var a Arrangement
+ var index uint32
+ Rn := (x >> 5) & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ if imm5&1 == 1 {
+ a = ArrangementB
+ index = imm5 >> 1
+ } else if imm5&2 == 2 {
+ a = ArrangementH
+ index = imm5 >> 2
+ } else if imm5&4 == 4 {
+ a = ArrangementS
+ index = imm5 >> 3
+ } else if imm5&8 == 8 {
+ a = ArrangementD
+ index = imm5 >> 4
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
+
+ case arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1:
+ var a Arrangement
+ var index uint32
+ Rn := (x >> 5) & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ if imm5&1 == 1 {
+ a = ArrangementB
+ index = imm5 >> 1
+ } else if imm5&2 == 2 {
+ a = ArrangementH
+ index = imm5 >> 2
+ } else if imm5&4 == 4 {
+ a = ArrangementS
+ index = imm5 >> 3
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
+
+ case arg_Vn_arrangement_imm5___D_8_index__imm5_1:
+ var a Arrangement
+ var index uint32
+ Rn := (x >> 5) & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ if imm5&15 == 8 {
+ a = ArrangementD
+ index = imm5 >> 4
+ } else {
+ return nil
+ }
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
+
+ case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81:
+ Rn := (x >> 5) & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ Q := (x >> 30) & 1
+ if immh>>2 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ } else if immh>>3 == 1 {
+ if Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ }
+ return nil
+
+ case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41:
+ Rn := (x >> 5) & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ Q := (x >> 30) & 1
+ if immh == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ }
+ } else if immh>>1 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ }
+ } else if immh>>2 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ }
+ return nil
+
+ case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
+ Rn := (x >> 5) & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ Q := (x >> 30) & 1
+ if immh == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ }
+ } else if immh>>1 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ }
+ } else if immh>>2 == 1 {
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ } else if immh>>3 == 1 {
+ if Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ }
+ return nil
+
+ case arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4:
+ Rn := (x >> 5) & (1<<5 - 1)
+ immh := (x >> 19) & (1<<4 - 1)
+ if immh == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if immh>>1 == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ } else if immh>>2 == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_Q___8B_0__16B_1:
+ Rn := (x >> 5) & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ if Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ }
+
+ case arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11:
+ Rn := (x >> 5) & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ sz := (x >> 22) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ } else if sz == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_Q_sz___4S_10:
+ Rn := (x >> 5) & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ sz := (x >> 22) & 1
+ if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1:
+ var index uint32
+ Rn := (x >> 5) & (1<<5 - 1)
+ imm5 := (x >> 16) & (1<<5 - 1)
+ index = imm5 >> 3
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementS, uint8(index), 0}
+
+ case arg_Vn_arrangement_size___2D_3:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ if size == 3 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size___8H_0__4S_1__2D_2:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ if size == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if size == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ } else if size == 2 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___8B_00__16B_01:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ } else if size == 3 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement1D, 0}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21:
+ Rn := (x >> 5) & (1<<5 - 1)
+ size := (x >> 22) & 3
+ Q := (x >> 30) & 1
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_sz___2D_1:
+ Rn := (x >> 5) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ if sz == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_sz___2S_0__2D_1:
+ Rn := (x >> 5) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ if sz == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+
+ case arg_Vn_arrangement_sz___4S_0__2D_1:
+ Rn := (x >> 5) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ if sz == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ } else {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+
+ case arg_Vn_arrangement_sz_Q___2S_00__4S_01:
+ Rn := (x >> 5) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11:
+ Rn := (x >> 5) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ } else if sz == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
+ }
+ return nil
+
+ case arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11:
+ Rn := (x >> 5) & (1<<5 - 1)
+ sz := (x >> 22) & 1
+ Q := (x >> 30) & 1
+ if sz == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
+ } else if sz == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
+ } else if sz == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
+ } else /* sz == 1 && Q == 1 */ {
+ return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
+ }
+
+ case arg_Vt_1_arrangement_B_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 10) & 3
+ index := (Q << 3) | (S << 2) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 1}
+
+ case arg_Vt_1_arrangement_D_index__Q_1:
+ Rt := x & (1<<5 - 1)
+ index := (x >> 30) & 1
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 1}
+
+ case arg_Vt_1_arrangement_H_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 11) & 1
+ index := (Q << 2) | (S << 1) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 1}
+
+ case arg_Vt_1_arrangement_S_index__Q_S_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ index := (Q << 1) | S
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 1}
+
+ case arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 1}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 1}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 1}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 1}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 1}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 1}
+ } else if size == 3 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 1}
+ } else /* size == 3 && Q == 1 */ {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 1}
+ }
+
+ case arg_Vt_2_arrangement_B_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 10) & 3
+ index := (Q << 3) | (S << 2) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 2}
+
+ case arg_Vt_2_arrangement_D_index__Q_1:
+ Rt := x & (1<<5 - 1)
+ index := (x >> 30) & 1
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 2}
+
+ case arg_Vt_2_arrangement_H_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 11) & 1
+ index := (Q << 2) | (S << 1) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 2}
+
+ case arg_Vt_2_arrangement_S_index__Q_S_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ index := (Q << 1) | S
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 2}
+
+ case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2}
+ } else if size == 3 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 2}
+ } else /* size == 3 && Q == 1 */ {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2}
+ }
+
+ case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2}
+ }
+ return nil
+
+ case arg_Vt_3_arrangement_B_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 10) & 3
+ index := (Q << 3) | (S << 2) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 3}
+
+ case arg_Vt_3_arrangement_D_index__Q_1:
+ Rt := x & (1<<5 - 1)
+ index := (x >> 30) & 1
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 3}
+
+ case arg_Vt_3_arrangement_H_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 11) & 1
+ index := (Q << 2) | (S << 1) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 3}
+
+ case arg_Vt_3_arrangement_S_index__Q_S_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ index := (Q << 1) | S
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 3}
+
+ case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3}
+ } else if size == 3 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 3}
+ } else /* size == 3 && Q == 1 */ {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3}
+ }
+
+ case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3}
+ }
+ return nil
+
+ case arg_Vt_4_arrangement_B_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 10) & 3
+ index := (Q << 3) | (S << 2) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 4}
+
+ case arg_Vt_4_arrangement_D_index__Q_1:
+ Rt := x & (1<<5 - 1)
+ index := (x >> 30) & 1
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 4}
+
+ case arg_Vt_4_arrangement_H_index__Q_S_size_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ size := (x >> 11) & 1
+ index := (Q << 2) | (S << 1) | (size)
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 4}
+
+ case arg_Vt_4_arrangement_S_index__Q_S_1:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ S := (x >> 12) & 1
+ index := (Q << 1) | S
+ return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 4}
+
+ case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4}
+ } else if size == 3 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 4}
+ } else /* size == 3 && Q == 1 */ {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4}
+ }
+
+ case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
+ Rt := x & (1<<5 - 1)
+ Q := (x >> 30) & 1
+ size := (x >> 10) & 3
+ if size == 0 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4}
+ } else if size == 0 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4}
+ } else if size == 1 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4}
+ } else if size == 1 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4}
+ } else if size == 2 && Q == 0 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4}
+ } else if size == 2 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4}
+ } else if size == 3 && Q == 1 {
+ return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4}
+ }
+ return nil
+
+ case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1:
+ return handle_MemExtend(x, 4, false)
+
+ case arg_Xns_mem_offset:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrOffset, 0}
+
+ case arg_Xns_mem_optional_imm12_16_unsigned:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm12 := (x >> 10) & (1<<12 - 1)
+ return MemImmediate{Rn, AddrOffset, int32(imm12 << 4)}
+
+ case arg_Xns_mem_optional_imm7_16_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 4)) << 21) >> 21}
+
+ case arg_Xns_mem_post_fixedimm_1:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 1}
+
+ case arg_Xns_mem_post_fixedimm_12:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 12}
+
+ case arg_Xns_mem_post_fixedimm_16:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 16}
+
+ case arg_Xns_mem_post_fixedimm_2:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 2}
+
+ case arg_Xns_mem_post_fixedimm_24:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 24}
+
+ case arg_Xns_mem_post_fixedimm_3:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 3}
+
+ case arg_Xns_mem_post_fixedimm_32:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 32}
+
+ case arg_Xns_mem_post_fixedimm_4:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 4}
+
+ case arg_Xns_mem_post_fixedimm_6:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 6}
+
+ case arg_Xns_mem_post_fixedimm_8:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ return MemImmediate{Rn, AddrPostIndex, 8}
+
+ case arg_Xns_mem_post_imm7_16_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 4)) << 21) >> 21}
+
+ case arg_Xns_mem_post_Q__16_0__32_1:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ Q := (x >> 30) & 1
+ return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 16)}
+
+ case arg_Xns_mem_post_Q__24_0__48_1:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ Q := (x >> 30) & 1
+ return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 24)}
+
+ case arg_Xns_mem_post_Q__32_0__64_1:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ Q := (x >> 30) & 1
+ return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 32)}
+
+ case arg_Xns_mem_post_Q__8_0__16_1:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ Q := (x >> 30) & 1
+ return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 8)}
+
+ case arg_Xns_mem_post_size__1_0__2_1__4_2__8_3:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ size := (x >> 10) & 3
+ return MemImmediate{Rn, AddrPostIndex, int32(1 << size)}
+
+ case arg_Xns_mem_post_size__2_0__4_1__8_2__16_3:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ size := (x >> 10) & 3
+ return MemImmediate{Rn, AddrPostIndex, int32(2 << size)}
+
+ case arg_Xns_mem_post_size__3_0__6_1__12_2__24_3:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ size := (x >> 10) & 3
+ return MemImmediate{Rn, AddrPostIndex, int32(3 << size)}
+
+ case arg_Xns_mem_post_size__4_0__8_1__16_2__32_3:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ size := (x >> 10) & 3
+ return MemImmediate{Rn, AddrPostIndex, int32(4 << size)}
+
+ case arg_Xns_mem_post_Xm:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ Rm := (x >> 16) & (1<<5 - 1)
+ return MemImmediate{Rn, AddrPostReg, int32(Rm)}
+
+ case arg_Xns_mem_wb_imm7_16_signed:
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ imm7 := (x >> 15) & (1<<7 - 1)
+ return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 4)) << 21) >> 21}
+ }
+}
+
+func handle_ExtendedRegister(x uint32, has_width bool) Arg {
+ s := (x >> 29) & 1
+ rm := (x >> 16) & (1<<5 - 1)
+ option := (x >> 13) & (1<<3 - 1)
+ imm3 := (x >> 10) & (1<<3 - 1)
+ rn := (x >> 5) & (1<<5 - 1)
+ rd := x & (1<<5 - 1)
+ is_32bit := !has_width
+ var rea RegExtshiftAmount
+ if has_width {
+ if option&0x3 != 0x3 {
+ rea.reg = W0 + Reg(rm)
+ } else {
+ rea.reg = X0 + Reg(rm)
+ }
+ } else {
+ rea.reg = W0 + Reg(rm)
+ }
+ switch option {
+ case 0:
+ rea.extShift = uxtb
+ case 1:
+ rea.extShift = uxth
+ case 2:
+ if is_32bit && (rn == 31 || (s == 0 && rd == 31)) {
+ if imm3 != 0 {
+ rea.extShift = lsl
+ } else {
+ rea.extShift = ExtShift(0)
+ }
+ } else {
+ rea.extShift = uxtw
+ }
+ case 3:
+ if !is_32bit && (rn == 31 || (s == 0 && rd == 31)) {
+ if imm3 != 0 {
+ rea.extShift = lsl
+ } else {
+ rea.extShift = ExtShift(0)
+ }
+ } else {
+ rea.extShift = uxtx
+ }
+ case 4:
+ rea.extShift = sxtb
+ case 5:
+ rea.extShift = sxth
+ case 6:
+ rea.extShift = sxtw
+ case 7:
+ rea.extShift = sxtx
+ }
+ rea.show_zero = false
+ rea.amount = uint8(imm3)
+ return rea
+}
+
+func handle_ImmediateShiftedRegister(x uint32, max uint8, is_w, has_ror bool) Arg {
+ var rsa RegExtshiftAmount
+ if is_w {
+ rsa.reg = W0 + Reg((x>>16)&(1<<5-1))
+ } else {
+ rsa.reg = X0 + Reg((x>>16)&(1<<5-1))
+ }
+ switch (x >> 22) & 0x3 {
+ case 0:
+ rsa.extShift = lsl
+ case 1:
+ rsa.extShift = lsr
+ case 2:
+ rsa.extShift = asr
+ case 3:
+ if has_ror {
+ rsa.extShift = ror
+ } else {
+ return nil
+ }
+ }
+ rsa.show_zero = true
+ rsa.amount = uint8((x >> 10) & (1<<6 - 1))
+ if rsa.amount == 0 && rsa.extShift == lsl {
+ rsa.extShift = ExtShift(0)
+ } else if rsa.amount > max {
+ return nil
+ }
+ return rsa
+}
+
+func handle_MemExtend(x uint32, mult uint8, absent bool) Arg {
+ var extend ExtShift
+ var Rm Reg
+ option := (x >> 13) & (1<<3 - 1)
+ Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
+ if (option & 1) != 0 {
+ Rm = Reg(X0) + Reg(x>>16&(1<<5-1))
+ } else {
+ Rm = Reg(W0) + Reg(x>>16&(1<<5-1))
+ }
+ switch option {
+ default:
+ return nil
+ case 2:
+ extend = uxtw
+ case 3:
+ extend = lsl
+ case 6:
+ extend = sxtw
+ case 7:
+ extend = sxtx
+ }
+ amount := (uint8((x >> 12) & 1)) * mult
+ return MemExtend{Rn, Rm, extend, amount, absent}
+}
+
+func handle_bitmasks(x uint32, datasize uint8) Arg {
+ var length, levels, esize, i uint8
+ var welem, wmask uint64
+ n := (x >> 22) & 1
+ imms := uint8((x >> 10) & (1<<6 - 1))
+ immr := uint8((x >> 16) & (1<<6 - 1))
+ if n != 0 {
+ length = 6
+ } else if (imms & 32) == 0 {
+ length = 5
+ } else if (imms & 16) == 0 {
+ length = 4
+ } else if (imms & 8) == 0 {
+ length = 3
+ } else if (imms & 4) == 0 {
+ length = 2
+ } else if (imms & 2) == 0 {
+ length = 1
+ } else {
+ return nil
+ }
+ levels = 1<<length - 1
+ s := imms & levels
+ r := immr & levels
+ esize = 1 << length
+ if esize > datasize {
+ return nil
+ }
+ welem = 1<<(s+1) - 1
+ ror := (welem >> r) | (welem << (esize - r))
+ ror &= ((1 << esize) - 1)
+ wmask = 0
+ for i = 0; i < datasize; i += esize {
+ wmask = (wmask << esize) | ror
+ }
+ return Imm64{wmask, false}
+}
diff --git a/arm64/arm64asm/decode_test.go b/arm64/arm64asm/decode_test.go
new file mode 100644
index 0000000..a79ee1c
--- /dev/null
+++ b/arm64/arm64asm/decode_test.go
@@ -0,0 +1,78 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+import (
+ "encoding/hex"
+ "io/ioutil"
+ "strings"
+ "testing"
+)
+
+func TestDecode(t *testing.T) {
+ data, err := ioutil.ReadFile("testdata/cases.txt")
+ if err != nil {
+ t.Fatal(err)
+ }
+ all := string(data)
+ for strings.Contains(all, "\t\t") {
+ all = strings.Replace(all, "\t\t", "\t", -1)
+ }
+ for _, line := range strings.Split(all, "\n") {
+ line = strings.TrimSpace(line)
+ if line == "" || strings.HasPrefix(line, "#") {
+ continue
+ }
+ f := strings.SplitN(line, "\t", 3)
+ i := strings.Index(f[0], "|")
+ if i < 0 {
+ t.Errorf("parsing %q: missing | separator", f[0])
+ continue
+ }
+ if i%2 != 0 {
+ t.Errorf("parsing %q: misaligned | separator", f[0])
+ }
+ code, err := hex.DecodeString(f[0][:i] + f[0][i+1:])
+ if err != nil {
+ t.Errorf("parsing %q: %v", f[0], err)
+ continue
+ }
+ syntax, asm := f[1], f[2]
+ inst, decodeErr := Decode(code)
+ if decodeErr != nil && decodeErr != errUnknown {
+ // Some rarely used system instructions are not supported
+ // Following logicals will filter such unknown instructions
+
+ t.Errorf("parsing %x: %s", code, decodeErr)
+ continue
+ }
+ var out string
+ switch syntax {
+ case "gnu":
+ out = GNUSyntax(inst)
+ case "plan9":
+ out = GoSyntax(inst, 0, nil, nil)
+ default:
+ t.Errorf("unknown syntax %q", syntax)
+ continue
+ }
+ // TODO: system instruction.
+ var Todo = strings.Fields(`
+ sys
+ dc
+ at
+ tlbi
+ ic
+ hvc
+ smc
+ `)
+ if strings.Replace(out, " ", "", -1) != strings.Replace(asm, " ", "", -1) && !hasPrefix(asm, Todo...) {
+ // Exclude MSR since GNU objdump result is incorrect. eg. 0xd504431f msr s0_4_c4_c3_0, xzr
+ if !strings.HasSuffix(asm, " nv") && !strings.HasPrefix(asm, "msr") {
+ t.Errorf("Decode(%s) [%s] = %s, want %s", f[0], syntax, out, asm)
+ }
+ }
+ }
+}
diff --git a/arm64/arm64asm/ext_test.go b/arm64/arm64asm/ext_test.go
new file mode 100644
index 0000000..ef2162c
--- /dev/null
+++ b/arm64/arm64asm/ext_test.go
@@ -0,0 +1,601 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Support for testing against external disassembler program.
+// Copied and simplified from ../../arm/armasm/ext_test.go.
+
+package arm64asm
+
+import (
+ "bufio"
+ "bytes"
+ "encoding/hex"
+ "encoding/json"
+ "flag"
+ "fmt"
+ "io/ioutil"
+ "log"
+ "math/rand"
+ "os"
+ "os/exec"
+ "regexp"
+ "strconv"
+ "strings"
+ "testing"
+ "time"
+)
+
+var (
+ dumpTest = flag.Bool("dump", false, "dump all encodings")
+ mismatch = flag.Bool("mismatch", false, "log allowed mismatches")
+ longTest = flag.Bool("long", false, "long test")
+ keep = flag.Bool("keep", false, "keep object files around")
+ debug = false
+)
+
+// An ExtInst represents a single decoded instruction parsed
+// from an external disassembler's output.
+type ExtInst struct {
+ addr uint64
+ enc [4]byte
+ nenc int
+ text string
+}
+
+func (r ExtInst) String() string {
+ return fmt.Sprintf("%#x: % x: %s", r.addr, r.enc, r.text)
+}
+
+// An ExtDis is a connection between an external disassembler and a test.
+type ExtDis struct {
+ Arch Mode
+ Dec chan ExtInst
+ File *os.File
+ Size int
+ KeepFile bool
+ Cmd *exec.Cmd
+}
+
+// InstJson describes instruction fields value got from ARMv8-A Reference Manual
+type InstJson struct {
+ Name string
+ Bits string
+ Arch string
+ Syntax string
+ Code string
+ Alias string
+ Enc uint32
+}
+
+// A Mode is an instruction execution mode.
+type Mode int
+
+const (
+ _ Mode = iota
+ ModeARM64
+)
+
+// Run runs the given command - the external disassembler - and returns
+// a buffered reader of its standard output.
+func (ext *ExtDis) Run(cmd ...string) (*bufio.Reader, error) {
+ if *keep {
+ log.Printf("%s\n", strings.Join(cmd, " "))
+ }
+ ext.Cmd = exec.Command(cmd[0], cmd[1:]...)
+ out, err := ext.Cmd.StdoutPipe()
+ if err != nil {
+ return nil, fmt.Errorf("stdoutpipe: %v", err)
+ }
+ if err := ext.Cmd.Start(); err != nil {
+ return nil, fmt.Errorf("exec: %v", err)
+ }
+
+ b := bufio.NewReaderSize(out, 1<<20)
+ return b, nil
+}
+
+// Wait waits for the command started with Run to exit.
+func (ext *ExtDis) Wait() error {
+ return ext.Cmd.Wait()
+}
+
+// testExtDis tests a set of byte sequences against an external disassembler.
+// The disassembler is expected to produce the given syntax and run
+// in the given architecture mode (16, 32, or 64-bit).
+// The extdis function must start the external disassembler
+// and then parse its output, sending the parsed instructions on ext.Dec.
+// The generate function calls its argument f once for each byte sequence
+// to be tested. The generate function itself will be called twice, and it must
+// make the same sequence of calls to f each time.
+// When a disassembly does not match the internal decoding,
+// allowedMismatch determines whether this mismatch should be
+// allowed, or else considered an error.
+func testExtDis(
+ t *testing.T,
+ syntax string,
+ arch Mode,
+ extdis func(ext *ExtDis) error,
+ generate func(f func([]byte)),
+ allowedMismatch func(text string, inst *Inst, dec ExtInst) bool,
+) {
+ start := time.Now()
+ ext := &ExtDis{
+ Dec: make(chan ExtInst),
+ Arch: arch,
+ }
+ errc := make(chan error)
+
+ // First pass: write instructions to input file for external disassembler.
+ file, f, size, err := writeInst(generate)
+ if err != nil {
+ t.Fatal(err)
+ }
+ ext.Size = size
+ ext.File = f
+ defer func() {
+ f.Close()
+ if !*keep {
+ os.Remove(file)
+ }
+ }()
+
+ // Second pass: compare disassembly against our decodings.
+ var (
+ totalTests = 0
+ totalSkips = 0
+ totalErrors = 0
+
+ errors = make([]string, 0, 100) // Sampled errors, at most cap
+ )
+ go func() {
+ errc <- extdis(ext)
+ }()
+
+ generate(func(enc []byte) {
+ dec, ok := <-ext.Dec
+ if !ok {
+ t.Errorf("decoding stream ended early")
+ return
+ }
+ inst, text := disasm(syntax, pad(enc))
+
+ totalTests++
+ if *dumpTest {
+ fmt.Printf("%x -> %s [%d]\n", enc[:len(enc)], dec.text, dec.nenc)
+ }
+ if text != dec.text && !strings.Contains(dec.text, "unknown") && syntax == "gnu" {
+ suffix := ""
+ if allowedMismatch(text, &inst, dec) {
+ totalSkips++
+ if !*mismatch {
+ return
+ }
+ suffix += " (allowed mismatch)"
+ }
+ totalErrors++
+ cmp := fmt.Sprintf("decode(%x) = %q, %d, want %q, %d%s\n", enc, text, len(enc), dec.text, dec.nenc, suffix)
+
+ if len(errors) >= cap(errors) {
+ j := rand.Intn(totalErrors)
+ if j >= cap(errors) {
+ return
+ }
+ errors = append(errors[:j], errors[j+1:]...)
+ }
+ errors = append(errors, cmp)
+ }
+ })
+
+ if *mismatch {
+ totalErrors -= totalSkips
+ }
+
+ for _, b := range errors {
+ t.Log(b)
+ }
+
+ if totalErrors > 0 {
+ t.Fail()
+ }
+ t.Logf("%d test cases, %d expected mismatches, %d failures; %.0f cases/second", totalTests, totalSkips, totalErrors, float64(totalTests)/time.Since(start).Seconds())
+ t.Logf("decoder coverage: %.1f%%;\n", decodeCoverage())
+ if err := <-errc; err != nil {
+ t.Fatalf("external disassembler: %v", err)
+ }
+
+}
+
+// Start address of text.
+const start = 0x8000
+
+// writeInst writes the generated byte sequences to a new file
+// starting at offset start. That file is intended to be the input to
+// the external disassembler.
+func writeInst(generate func(func([]byte))) (file string, f *os.File, size int, err error) {
+ f, err = ioutil.TempFile("", "arm64asm")
+ if err != nil {
+ return
+ }
+
+ file = f.Name()
+
+ f.Seek(start, 0)
+ w := bufio.NewWriter(f)
+ defer w.Flush()
+ size = 0
+ generate(func(x []byte) {
+ if debug {
+ fmt.Printf("%#x: %x%x\n", start+size, x, zeros[len(x):])
+ }
+ w.Write(x)
+ w.Write(zeros[len(x):])
+ size += len(zeros)
+ })
+ return file, f, size, nil
+}
+
+var zeros = []byte{0, 0, 0, 0}
+
+// pad pads the code sequence with pops.
+func pad(enc []byte) []byte {
+ if len(enc) < 4 {
+ enc = append(enc[:len(enc):len(enc)], zeros[:4-len(enc)]...)
+ }
+ return enc
+}
+
+// disasm returns the decoded instruction and text
+// for the given source bytes, using the given syntax and mode.
+func disasm(syntax string, src []byte) (inst Inst, text string) {
+ var err error
+ inst, err = Decode(src)
+ if err != nil {
+ text = "error: " + err.Error()
+ return
+ }
+ text = inst.String()
+ switch syntax {
+ case "gnu":
+ text = GNUSyntax(inst)
+ case "plan9": // [sic]
+ text = GoSyntax(inst, 0, nil, nil)
+ default:
+ text = "error: unknown syntax " + syntax
+ }
+ return
+}
+
+// decodecoverage returns a floating point number denoting the
+// decoder coverage.
+func decodeCoverage() float64 {
+ n := 0
+ for _, t := range decoderCover {
+ if t {
+ n++
+ }
+ }
+ return 100 * float64(1+n) / float64(1+len(decoderCover))
+}
+
+// Helpers for writing disassembler output parsers.
+
+// hasPrefix reports whether any of the space-separated words in the text s
+// begins with any of the given prefixes.
+func hasPrefix(s string, prefixes ...string) bool {
+ for _, prefix := range prefixes {
+ for cur_s := s; cur_s != ""; {
+ if strings.HasPrefix(cur_s, prefix) {
+ return true
+ }
+ i := strings.Index(cur_s, " ")
+ if i < 0 {
+ break
+ }
+ cur_s = cur_s[i+1:]
+ }
+ }
+ return false
+}
+
+// isHex reports whether b is a hexadecimal character (0-9a-fA-F).
+func isHex(b byte) bool {
+ return ('0' <= b && b <= '9') || ('a' <= b && b <= 'f') || ('A' <= b && b <= 'F')
+}
+
+// parseHex parses the hexadecimal byte dump in hex,
+// appending the parsed bytes to raw and returning the updated slice.
+// The returned bool reports whether any invalid hex was found.
+// Spaces and tabs between bytes are okay but any other non-hex is not.
+func parseHex(hex []byte, raw []byte) ([]byte, bool) {
+ hex = bytes.TrimSpace(hex)
+ for j := 0; j < len(hex); {
+ for hex[j] == ' ' || hex[j] == '\t' {
+ j++
+ }
+ if j >= len(hex) {
+ break
+ }
+ if j+2 > len(hex) || !isHex(hex[j]) || !isHex(hex[j+1]) {
+ return nil, false
+ }
+ raw = append(raw, unhex(hex[j])<<4|unhex(hex[j+1]))
+ j += 2
+ }
+ return raw, true
+}
+
+func unhex(b byte) byte {
+ if '0' <= b && b <= '9' {
+ return b - '0'
+ } else if 'A' <= b && b <= 'F' {
+ return b - 'A' + 10
+ } else if 'a' <= b && b <= 'f' {
+ return b - 'a' + 10
+ }
+ return 0
+}
+
+// index is like bytes.Index(s, []byte(t)) but avoids the allocation.
+func index(s []byte, t string) int {
+ i := 0
+ for {
+ j := bytes.IndexByte(s[i:], t[0])
+ if j < 0 {
+ return -1
+ }
+ i = i + j
+ if i+len(t) > len(s) {
+ return -1
+ }
+ for k := 1; k < len(t); k++ {
+ if s[i+k] != t[k] {
+ goto nomatch
+ }
+ }
+ return i
+ nomatch:
+ i++
+ }
+}
+
+// fixSpace rewrites runs of spaces, tabs, and newline characters into single spaces in s.
+// If s must be rewritten, it is rewritten in place.
+func fixSpace(s []byte) []byte {
+ s = bytes.TrimSpace(s)
+ for i := 0; i < len(s); i++ {
+ if s[i] == '\t' || s[i] == '\n' || i > 0 && s[i] == ' ' && s[i-1] == ' ' {
+ goto Fix
+ }
+ }
+ return s
+
+Fix:
+ b := s
+ w := 0
+ for i := 0; i < len(s); i++ {
+ c := s[i]
+ if c == '\t' || c == '\n' {
+ c = ' '
+ }
+ if c == ' ' && w > 0 && b[w-1] == ' ' {
+ continue
+ }
+ b[w] = c
+ w++
+ }
+ if w > 0 && b[w-1] == ' ' {
+ w--
+ }
+ return b[:w]
+}
+
+// Fllowing regular expressions matches instructions using relative addressing mode.
+// pcrel matches B instructions and BL instructions.
+// pcrelr matches instrucions which consisted of register arguments and label arguments.
+// pcrelim matches instructions which consisted of register arguments, immediate
+// arguments and lable arguments.
+// pcrelrzr and prcelimzr matches instructions when register arguments is zero register.
+// pcrelprfm matches PRFM instructions when arguments consisted of register and lable.
+// pcrelprfmim matches PRFM instructions when arguments consisted of immediate and lable.
+var (
+ pcrel = regexp.MustCompile(`^((?:.* )?(?:b|bl)x?(?:\.)?(?:eq|ne|cs|cc|mi|pl|vs|vc|hi|ls|ge|lt|gt|le|al|nv)?) 0x([0-9a-f]+)$`)
+ pcrelr = regexp.MustCompile(`^((?:.*)?(?:ldr|adrp|adr|cbnz|cbz|ldrsw) (?:x|w|s|d|q)(?:[0-9]+,)) 0x([0-9a-f]+)$`)
+ pcrelrzr = regexp.MustCompile(`^((?:.*)?(?:ldr|adrp|adr|cbnz|cbz|ldrsw) (?:x|w)zr,) 0x([0-9a-f]+)$`)
+ pcrelim = regexp.MustCompile(`^((?:.*)?(?:tbnz|tbz) (?:x|w)(?:[0-9]+,) (?:#[0-9a-f]+,)) 0x([0-9a-f]+)$`)
+ pcrelimzr = regexp.MustCompile(`^((?:.*)?(?:tbnz|tbz) (?:x|w)zr, (?:#[0-9a-f]+,)) 0x([0-9a-f]+)$`)
+ pcrelprfm = regexp.MustCompile(`^((?:.*)?(?:prfm) (?:[0-9a-z]+,)) 0x([0-9a-f]+)$`)
+ pcrelprfmim = regexp.MustCompile(`^((?:.*)?(?:prfm) (?:#0x[0-9a-f]+,)) 0x([0-9a-f]+)$`)
+)
+
+// Round is the multiple of the number of instructions that read from Json file.
+// Round used as seed value for pseudo-random number generator provides the same sequence
+// in the same round run for the external disassembler and decoder.
+var Round int
+
+// condmark is used to mark conditional instructions when need to generate and test
+// conditional instructions.
+var condmark bool = false
+
+// Generate instruction binary according to Json file
+// Encode variable field of instruction with random value
+func doFuzzy(inst *InstJson, Ninst int) {
+ var testdata uint32
+ var NonDigRE = regexp.MustCompile(`[\D]`)
+ rand.Seed(int64(Round + Ninst))
+ off := 0
+ DigBit := ""
+ if condmark == true && !strings.Contains(inst.Bits, "cond") {
+ inst.Enc = 0xffffffff
+ } else {
+ for _, f := range strings.Split(inst.Bits, "|") {
+ if i := strings.Index(f, ":"); i >= 0 {
+ // consider f contains "01:2" and "Rm:5"
+ DigBit = f[:i]
+ m := NonDigRE.FindStringSubmatch(DigBit)
+ if m == nil {
+ DigBit = strings.TrimSpace(DigBit)
+ s := strings.Split(DigBit, "")
+ for i := 0; i < len(s); i++ {
+ switch s[i] {
+ case "1", "(1)":
+ testdata |= 1 << uint(31-off)
+ }
+ off++
+ }
+ } else {
+ // DigBit is "Rn" or "imm3"
+ n, _ := strconv.Atoi(f[i+1:])
+ if DigBit == "cond" && condmark == true {
+ r := uint8(Round)
+ for i := n - 1; i >= 0; i-- {
+ switch (r >> uint(i)) & 1 {
+ case 1:
+ testdata |= 1 << uint(31-off)
+ }
+ off++
+ }
+ } else {
+ for i := 0; i < n; i++ {
+ r := rand.Intn(2)
+ switch r {
+ case 1:
+ testdata |= 1 << uint(31-off)
+ }
+ off++
+ }
+ }
+ }
+ continue
+ }
+ for _, bit := range strings.Fields(f) {
+ switch bit {
+ case "0", "(0)":
+ off++
+ continue
+ case "1", "(1)":
+ testdata |= 1 << uint(31-off)
+ default:
+ r := rand.Intn(2)
+ switch r {
+ case 1:
+ testdata |= 1 << uint(31-off)
+ }
+ }
+ off++
+ }
+ }
+ if off != 32 {
+ log.Printf("incorrect bit count for %s %s: have %d", inst.Name, inst.Bits, off)
+ }
+ inst.Enc = testdata
+ }
+}
+
+// Generators.
+//
+// The test cases are described as functions that invoke a callback repeatedly,
+// with a new input sequence each time. These helpers make writing those
+// a little easier.
+
+// JSONCases generates ARM64 instructions according to inst.json.
+func JSONCases(t *testing.T) func(func([]byte)) {
+ return func(try func([]byte)) {
+ data, err := ioutil.ReadFile("inst.json")
+ if err != nil {
+ log.Fatal(err)
+ }
+ var insts []InstJson
+ var instsN []InstJson
+ // Change N value to get more cases only when condmark=false.
+ N := 100
+ if condmark == true {
+ N = 16
+ }
+ if err := json.Unmarshal(data, &insts); err != nil {
+ log.Fatal(err)
+ }
+ // Append instructions to get more test cases.
+ for i := 0; i < N; {
+ for _, inst := range insts {
+ instsN = append(instsN, inst)
+ }
+ i++
+ }
+ Round = 0
+ for i := range instsN {
+ if i%len(insts) == 0 {
+ Round++
+ }
+ doFuzzy(&instsN[i], i)
+ }
+ for _, inst := range instsN {
+ if condmark == true && inst.Enc == 0xffffffff {
+ continue
+ }
+ enc := inst.Enc
+ try([]byte{byte(enc), byte(enc >> 8), byte(enc >> 16), byte(enc >> 24)})
+ }
+ }
+}
+
+// condCases generates conditional instructions.
+func condCases(t *testing.T) func(func([]byte)) {
+ return func(try func([]byte)) {
+ condmark = true
+ JSONCases(t)(func(enc []byte) {
+ try(enc)
+ })
+ }
+}
+
+// hexCases generates the cases written in hexadecimal in the encoded string.
+// Spaces in 'encoded' separate entire test cases, not individual bytes.
+func hexCases(t *testing.T, encoded string) func(func([]byte)) {
+ return func(try func([]byte)) {
+ for _, x := range strings.Fields(encoded) {
+ src, err := hex.DecodeString(x)
+ if err != nil {
+ t.Errorf("parsing %q: %v", x, err)
+ }
+ try(src)
+ }
+ }
+}
+
+// testdataCases generates the test cases recorded in testdata/cases.txt.
+// It only uses the inputs; it ignores the answers recorded in that file.
+func testdataCases(t *testing.T) func(func([]byte)) {
+ var codes [][]byte
+ data, err := ioutil.ReadFile("testdata/cases.txt")
+ if err != nil {
+ t.Fatal(err)
+ }
+ for _, line := range strings.Split(string(data), "\n") {
+ line = strings.TrimSpace(line)
+ if line == "" || strings.HasPrefix(line, "#") {
+ continue
+ }
+ f := strings.Fields(line)[0]
+ i := strings.Index(f, "|")
+ if i < 0 {
+ t.Errorf("parsing %q: missing | separator", f)
+ continue
+ }
+ if i%2 != 0 {
+ t.Errorf("parsing %q: misaligned | separator", f)
+ }
+ code, err := hex.DecodeString(f[:i] + f[i+1:])
+ if err != nil {
+ t.Errorf("parsing %q: %v", f, err)
+ continue
+ }
+ codes = append(codes, code)
+ }
+
+ return func(try func([]byte)) {
+ for _, code := range codes {
+ try(code)
+ }
+ }
+}
diff --git a/arm64/arm64asm/gnu.go b/arm64/arm64asm/gnu.go
new file mode 100644
index 0000000..d1be046
--- /dev/null
+++ b/arm64/arm64asm/gnu.go
@@ -0,0 +1,35 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+import (
+ "strings"
+)
+
+// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils.
+// This form typically matches the syntax defined in the ARM Reference Manual.
+func GNUSyntax(inst Inst) string {
+ switch inst.Op {
+ case RET:
+ if r, ok := inst.Args[0].(Reg); ok && r == X30 {
+ return "ret"
+ }
+ case B:
+ if _, ok := inst.Args[0].(Cond); ok {
+ return strings.ToLower("b." + inst.Args[0].String() + " " + inst.Args[1].String())
+ }
+ case SYSL:
+ result := strings.ToLower(inst.String())
+ return strings.Replace(result, "c", "C", -1)
+ case DCPS1, DCPS2, DCPS3, CLREX:
+ return strings.ToLower(strings.TrimSpace(inst.String()))
+ case ISB:
+ if strings.Contains(inst.String(), "SY") {
+ result := strings.TrimSuffix(inst.String(), " SY")
+ return strings.ToLower(result)
+ }
+ }
+ return strings.ToLower(inst.String())
+}
diff --git a/arm64/arm64asm/inst.go b/arm64/arm64asm/inst.go
new file mode 100644
index 0000000..3ff31be
--- /dev/null
+++ b/arm64/arm64asm/inst.go
@@ -0,0 +1,963 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+import (
+ "fmt"
+ "strings"
+)
+
+// An Op is an ARM64 opcode.
+type Op uint16
+
+// NOTE: The actual Op values are defined in tables.go.
+// They are chosen to simplify instruction decoding and
+// are not a dense packing from 0 to N, although the
+// density is high, probably at least 90%.
+
+func (op Op) String() string {
+ if op >= Op(len(opstr)) || opstr[op] == "" {
+ return fmt.Sprintf("Op(%d)", int(op))
+ }
+ return opstr[op]
+}
+
+// An Inst is a single instruction.
+type Inst struct {
+ Op Op // Opcode mnemonic
+ Enc uint32 // Raw encoding bits.
+ Args Args // Instruction arguments, in ARM manual order.
+}
+
+func (i Inst) String() string {
+ var args []string
+ for _, arg := range i.Args {
+ if arg == nil {
+ break
+ }
+ args = append(args, arg.String())
+ }
+ return i.Op.String() + " " + strings.Join(args, ", ")
+}
+
+// An Args holds the instruction arguments.
+// If an instruction has fewer than 5 arguments,
+// the final elements in the array are nil.
+type Args [5]Arg
+
+// An Arg is a single instruction argument, one of these types:
+// Reg, RegSP, ImmShift, RegExtshiftAmount, PCRel, MemImmediate,
+// MemExtend, Imm, Imm64, Imm_hint, Imm_clrex, Imm_dcps, Cond,
+// Imm_c, Imm_option, Imm_prfop, Pstatefield, Systemreg, Imm_fp
+// RegisterWithArrangement, RegisterWithArrangementAndIndex.
+type Arg interface {
+ isArg()
+ String() string
+}
+
+// A Reg is a single register.
+// The zero value denotes W0, not the absence of a register.
+type Reg uint16
+
+const (
+ W0 Reg = iota
+ W1
+ W2
+ W3
+ W4
+ W5
+ W6
+ W7
+ W8
+ W9
+ W10
+ W11
+ W12
+ W13
+ W14
+ W15
+ W16
+ W17
+ W18
+ W19
+ W20
+ W21
+ W22
+ W23
+ W24
+ W25
+ W26
+ W27
+ W28
+ W29
+ W30
+ WZR
+
+ X0
+ X1
+ X2
+ X3
+ X4
+ X5
+ X6
+ X7
+ X8
+ X9
+ X10
+ X11
+ X12
+ X13
+ X14
+ X15
+ X16
+ X17
+ X18
+ X19
+ X20
+ X21
+ X22
+ X23
+ X24
+ X25
+ X26
+ X27
+ X28
+ X29
+ X30
+ XZR
+
+ B0
+ B1
+ B2
+ B3
+ B4
+ B5
+ B6
+ B7
+ B8
+ B9
+ B10
+ B11
+ B12
+ B13
+ B14
+ B15
+ B16
+ B17
+ B18
+ B19
+ B20
+ B21
+ B22
+ B23
+ B24
+ B25
+ B26
+ B27
+ B28
+ B29
+ B30
+ B31
+
+ H0
+ H1
+ H2
+ H3
+ H4
+ H5
+ H6
+ H7
+ H8
+ H9
+ H10
+ H11
+ H12
+ H13
+ H14
+ H15
+ H16
+ H17
+ H18
+ H19
+ H20
+ H21
+ H22
+ H23
+ H24
+ H25
+ H26
+ H27
+ H28
+ H29
+ H30
+ H31
+
+ S0
+ S1
+ S2
+ S3
+ S4
+ S5
+ S6
+ S7
+ S8
+ S9
+ S10
+ S11
+ S12
+ S13
+ S14
+ S15
+ S16
+ S17
+ S18
+ S19
+ S20
+ S21
+ S22
+ S23
+ S24
+ S25
+ S26
+ S27
+ S28
+ S29
+ S30
+ S31
+
+ D0
+ D1
+ D2
+ D3
+ D4
+ D5
+ D6
+ D7
+ D8
+ D9
+ D10
+ D11
+ D12
+ D13
+ D14
+ D15
+ D16
+ D17
+ D18
+ D19
+ D20
+ D21
+ D22
+ D23
+ D24
+ D25
+ D26
+ D27
+ D28
+ D29
+ D30
+ D31
+
+ Q0
+ Q1
+ Q2
+ Q3
+ Q4
+ Q5
+ Q6
+ Q7
+ Q8
+ Q9
+ Q10
+ Q11
+ Q12
+ Q13
+ Q14
+ Q15
+ Q16
+ Q17
+ Q18
+ Q19
+ Q20
+ Q21
+ Q22
+ Q23
+ Q24
+ Q25
+ Q26
+ Q27
+ Q28
+ Q29
+ Q30
+ Q31
+
+ V0
+ V1
+ V2
+ V3
+ V4
+ V5
+ V6
+ V7
+ V8
+ V9
+ V10
+ V11
+ V12
+ V13
+ V14
+ V15
+ V16
+ V17
+ V18
+ V19
+ V20
+ V21
+ V22
+ V23
+ V24
+ V25
+ V26
+ V27
+ V28
+ V29
+ V30
+ V31
+
+ WSP = WZR // These are different registers with the same encoding.
+ SP = XZR // These are different registers with the same encoding.
+)
+
+func (Reg) isArg() {}
+
+func (r Reg) String() string {
+ switch {
+ case r == WZR:
+ return "WZR"
+ case r == XZR:
+ return "XZR"
+ case W0 <= r && r <= W30:
+ return fmt.Sprintf("W%d", int(r-W0))
+ case X0 <= r && r <= X30:
+ return fmt.Sprintf("X%d", int(r-X0))
+
+ case B0 <= r && r <= B31:
+ return fmt.Sprintf("B%d", int(r-B0))
+ case H0 <= r && r <= H31:
+ return fmt.Sprintf("H%d", int(r-H0))
+ case S0 <= r && r <= S31:
+ return fmt.Sprintf("S%d", int(r-S0))
+ case D0 <= r && r <= D31:
+ return fmt.Sprintf("D%d", int(r-D0))
+ case Q0 <= r && r <= Q31:
+ return fmt.Sprintf("Q%d", int(r-Q0))
+
+ case V0 <= r && r <= V31:
+ return fmt.Sprintf("V%d", int(r-V0))
+ default:
+ return fmt.Sprintf("Reg(%d)", int(r))
+ }
+}
+
+// A RegSP represent a register and X31/W31 is regarded as SP/WSP.
+type RegSP Reg
+
+func (RegSP) isArg() {}
+
+func (r RegSP) String() string {
+ switch Reg(r) {
+ case WSP:
+ return "WSP"
+ case SP:
+ return "SP"
+ default:
+ return Reg(r).String()
+ }
+}
+
+type ImmShift struct {
+ imm uint16
+ shift uint8
+}
+
+func (ImmShift) isArg() {}
+
+func (is ImmShift) String() string {
+ if is.shift == 0 {
+ return fmt.Sprintf("#%#x", is.imm)
+ }
+ if is.shift < 128 {
+ return fmt.Sprintf("#%#x, LSL #%d", is.imm, is.shift)
+ }
+ return fmt.Sprintf("#%#x, MSL #%d", is.imm, is.shift-128)
+}
+
+type ExtShift uint8
+
+const (
+ _ ExtShift = iota
+ uxtb
+ uxth
+ uxtw
+ uxtx
+ sxtb
+ sxth
+ sxtw
+ sxtx
+ lsl
+ lsr
+ asr
+ ror
+)
+
+func (extShift ExtShift) String() string {
+ switch extShift {
+ case uxtb:
+ return "UXTB"
+
+ case uxth:
+ return "UXTH"
+
+ case uxtw:
+ return "UXTW"
+
+ case uxtx:
+ return "UXTX"
+
+ case sxtb:
+ return "SXTB"
+
+ case sxth:
+ return "SXTH"
+
+ case sxtw:
+ return "SXTW"
+
+ case sxtx:
+ return "SXTX"
+
+ case lsl:
+ return "LSL"
+
+ case lsr:
+ return "LSR"
+
+ case asr:
+ return "ASR"
+
+ case ror:
+ return "ROR"
+ }
+ return ""
+}
+
+type RegExtshiftAmount struct {
+ reg Reg
+ extShift ExtShift
+ amount uint8
+ show_zero bool
+}
+
+func (RegExtshiftAmount) isArg() {}
+
+func (rea RegExtshiftAmount) String() string {
+ buf := rea.reg.String()
+ if rea.extShift != ExtShift(0) {
+ buf += ", " + rea.extShift.String()
+ if rea.amount != 0 {
+ buf += fmt.Sprintf(" #%d", rea.amount)
+ } else {
+ if rea.show_zero == true {
+ buf += fmt.Sprintf(" #%d", rea.amount)
+ }
+ }
+ }
+ return buf
+}
+
+// A PCRel describes a memory address (usually a code label)
+// as a distance relative to the program counter.
+type PCRel int64
+
+func (PCRel) isArg() {}
+
+func (r PCRel) String() string {
+ return fmt.Sprintf(".%+#x", uint64(r))
+}
+
+// An AddrMode is an ARM addressing mode.
+type AddrMode uint8
+
+const (
+ _ AddrMode = iota
+ AddrPostIndex // [R], X - use address R, set R = R + X
+ AddrPreIndex // [R, X]! - use address R + X, set R = R + X
+ AddrOffset // [R, X] - use address R + X
+ AddrPostReg // [Rn], Rm - - use address Rn, set Rn = Rn + Rm
+)
+
+// A MemImmediate is a memory reference made up of a base R and immediate X.
+// The effective memory address is R or R+X depending on AddrMode.
+type MemImmediate struct {
+ Base RegSP
+ Mode AddrMode
+ imm int32
+}
+
+func (MemImmediate) isArg() {}
+
+func (m MemImmediate) String() string {
+ R := m.Base.String()
+ X := fmt.Sprintf("#%d", m.imm)
+
+ switch m.Mode {
+ case AddrOffset:
+ if X == "#0" {
+ return fmt.Sprintf("[%s]", R)
+ }
+ return fmt.Sprintf("[%s,%s]", R, X)
+ case AddrPreIndex:
+ return fmt.Sprintf("[%s,%s]!", R, X)
+ case AddrPostIndex:
+ return fmt.Sprintf("[%s],%s", R, X)
+ case AddrPostReg:
+ post := Reg(X0) + Reg(m.imm)
+ postR := post.String()
+ return fmt.Sprintf("[%s], %s", R, postR)
+ }
+ return fmt.Sprintf("unimplemented!")
+}
+
+// A MemExtend is a memory reference made up of a base R and index expression X.
+// The effective memory address is R or R+X depending on Index, Extend and Amount.
+type MemExtend struct {
+ Base RegSP
+ Index Reg
+ Extend ExtShift
+ Amount uint8
+ Absent bool
+}
+
+func (MemExtend) isArg() {}
+
+func (m MemExtend) String() string {
+ Rbase := m.Base.String()
+ RIndex := m.Index.String()
+ if m.Absent {
+ if m.Amount != 0 {
+ return fmt.Sprintf("[%s,%s,%s #0]", Rbase, RIndex, m.Extend.String())
+ } else {
+ if m.Extend != lsl {
+ return fmt.Sprintf("[%s,%s,%s]", Rbase, RIndex, m.Extend.String())
+ } else {
+ return fmt.Sprintf("[%s,%s]", Rbase, RIndex)
+ }
+ }
+ } else {
+ if m.Amount != 0 {
+ return fmt.Sprintf("[%s,%s,%s #%d]", Rbase, RIndex, m.Extend.String(), m.Amount)
+ } else {
+ if m.Extend != lsl {
+ return fmt.Sprintf("[%s,%s,%s]", Rbase, RIndex, m.Extend.String())
+ } else {
+ return fmt.Sprintf("[%s,%s]", Rbase, RIndex)
+ }
+ }
+ }
+}
+
+// An Imm is an integer constant.
+type Imm struct {
+ Imm uint32
+ Decimal bool
+}
+
+func (Imm) isArg() {}
+
+func (i Imm) String() string {
+ if !i.Decimal {
+ return fmt.Sprintf("#%#x", i.Imm)
+ } else {
+ return fmt.Sprintf("#%d", i.Imm)
+ }
+}
+
+type Imm64 struct {
+ Imm uint64
+ Decimal bool
+}
+
+func (Imm64) isArg() {}
+
+func (i Imm64) String() string {
+ if !i.Decimal {
+ return fmt.Sprintf("#%#x", i.Imm)
+ } else {
+ return fmt.Sprintf("#%d", i.Imm)
+ }
+}
+
+// An Imm_hint is an integer constant for HINT instruction.
+type Imm_hint uint8
+
+func (Imm_hint) isArg() {}
+
+func (i Imm_hint) String() string {
+ return fmt.Sprintf("#%#x", uint32(i))
+}
+
+// An Imm_clrex is an integer constant for CLREX instruction.
+type Imm_clrex uint8
+
+func (Imm_clrex) isArg() {}
+
+func (i Imm_clrex) String() string {
+ if i == 15 {
+ return ""
+ }
+ return fmt.Sprintf("#%#x", uint32(i))
+}
+
+// An Imm_dcps is an integer constant for DCPS[123] instruction.
+type Imm_dcps uint16
+
+func (Imm_dcps) isArg() {}
+
+func (i Imm_dcps) String() string {
+ if i == 0 {
+ return ""
+ }
+ return fmt.Sprintf("#%#x", uint32(i))
+}
+
+// Standard conditions.
+type Cond struct {
+ Value uint8
+ Invert bool
+}
+
+func (Cond) isArg() {}
+
+func (c Cond) String() string {
+ cond31 := c.Value >> 1
+ invert := bool((c.Value & 1) == 1)
+ invert = (invert != c.Invert)
+ switch cond31 {
+ case 0:
+ if invert {
+ return "NE"
+ } else {
+ return "EQ"
+ }
+ case 1:
+ if invert {
+ return "CC"
+ } else {
+ return "CS"
+ }
+ case 2:
+ if invert {
+ return "PL"
+ } else {
+ return "MI"
+ }
+ case 3:
+ if invert {
+ return "VC"
+ } else {
+ return "VS"
+ }
+ case 4:
+ if invert {
+ return "LS"
+ } else {
+ return "HI"
+ }
+ case 5:
+ if invert {
+ return "LT"
+ } else {
+ return "GE"
+ }
+ case 6:
+ if invert {
+ return "LE"
+ } else {
+ return "GT"
+ }
+ case 7:
+ return "AL"
+ }
+ return ""
+}
+
+// An Imm_c is an integer constant for SYS/SYSL/TLBI instruction.
+type Imm_c uint8
+
+func (Imm_c) isArg() {}
+
+func (i Imm_c) String() string {
+ return fmt.Sprintf("C%d", uint8(i))
+}
+
+// An Imm_option is an integer constant for DMB/DSB/ISB instruction.
+type Imm_option uint8
+
+func (Imm_option) isArg() {}
+
+func (i Imm_option) String() string {
+ switch uint8(i) {
+ case 15:
+ return "SY"
+ case 14:
+ return "ST"
+ case 13:
+ return "LD"
+ case 11:
+ return "ISH"
+ case 10:
+ return "ISHST"
+ case 9:
+ return "ISHLD"
+ case 7:
+ return "NSH"
+ case 6:
+ return "NSHST"
+ case 5:
+ return "NSHLD"
+ case 3:
+ return "OSH"
+ case 2:
+ return "OSHST"
+ case 1:
+ return "OSHLD"
+ }
+ return fmt.Sprintf("#%#02x", uint8(i))
+}
+
+// An Imm_prfop is an integer constant for PRFM instruction.
+type Imm_prfop uint8
+
+func (Imm_prfop) isArg() {}
+
+func (i Imm_prfop) String() string {
+ prf_type := (i >> 3) & (1<<2 - 1)
+ prf_target := (i >> 1) & (1<<2 - 1)
+ prf_policy := i & 1
+ var result string
+
+ switch prf_type {
+ case 0:
+ result = "PLD"
+ case 1:
+ result = "PLI"
+ case 2:
+ result = "PST"
+ case 3:
+ return fmt.Sprintf("#%#02x", uint8(i))
+ }
+ switch prf_target {
+ case 0:
+ result += "L1"
+ case 1:
+ result += "L2"
+ case 2:
+ result += "L3"
+ case 3:
+ return fmt.Sprintf("#%#02x", uint8(i))
+ }
+ if prf_policy == 0 {
+ result += "KEEP"
+ } else {
+ result += "STRM"
+ }
+ return result
+}
+
+type Pstatefield uint8
+
+const (
+ SPSel Pstatefield = iota
+ DAIFSet
+ DAIFClr
+)
+
+func (Pstatefield) isArg() {}
+
+func (p Pstatefield) String() string {
+ switch p {
+ case SPSel:
+ return "SPSel"
+ case DAIFSet:
+ return "DAIFSet"
+ case DAIFClr:
+ return "DAIFClr"
+ default:
+ return "unimplemented"
+ }
+}
+
+type Systemreg struct {
+ op0 uint8
+ op1 uint8
+ cn uint8
+ cm uint8
+ op2 uint8
+}
+
+func (Systemreg) isArg() {}
+
+func (s Systemreg) String() string {
+ return fmt.Sprintf("S%d_%d_C%d_C%d_%d",
+ s.op0, s.op1, s.cn, s.cm, s.op2)
+}
+
+// An Imm_fp is a signed floating-point constant.
+type Imm_fp struct {
+ s uint8
+ exp int8
+ pre uint8
+}
+
+func (Imm_fp) isArg() {}
+
+func (i Imm_fp) String() string {
+ var s, pre, numerator, denominator int16
+ var result float64
+ if i.s == 0 {
+ s = 1
+ } else {
+ s = -1
+ }
+ pre = s * int16(16+i.pre)
+ if i.exp > 0 {
+ numerator = (pre << uint8(i.exp))
+ denominator = 16
+ } else {
+ numerator = pre
+ denominator = (16 << uint8(-1*i.exp))
+ }
+ result = float64(numerator) / float64(denominator)
+ return fmt.Sprintf("#%.18e", result)
+}
+
+type Arrangement uint8
+
+const (
+ _ Arrangement = iota
+ ArrangementB
+ Arrangement8B
+ Arrangement16B
+ ArrangementH
+ Arrangement4H
+ Arrangement8H
+ ArrangementS
+ Arrangement2S
+ Arrangement4S
+ ArrangementD
+ Arrangement1D
+ Arrangement2D
+ Arrangement1Q
+)
+
+func (a Arrangement) String() (result string) {
+ switch a {
+ case ArrangementB:
+ result = ".B"
+ case Arrangement8B:
+ result = ".8B"
+ case Arrangement16B:
+ result = ".16B"
+ case ArrangementH:
+ result = ".H"
+ case Arrangement4H:
+ result = ".4H"
+ case Arrangement8H:
+ result = ".8H"
+ case ArrangementS:
+ result = ".S"
+ case Arrangement2S:
+ result = ".2S"
+ case Arrangement4S:
+ result = ".4S"
+ case ArrangementD:
+ result = ".D"
+ case Arrangement1D:
+ result = ".1D"
+ case Arrangement2D:
+ result = ".2D"
+ case Arrangement1Q:
+ result = ".1Q"
+ }
+ return
+}
+
+// Register with arrangement: <Vd>.<T>, { <Vt>.8B, <Vt2>.8B},
+type RegisterWithArrangement struct {
+ r Reg
+ a Arrangement
+ cnt uint8
+}
+
+func (RegisterWithArrangement) isArg() {}
+
+func (r RegisterWithArrangement) String() string {
+ result := r.r.String()
+ result += r.a.String()
+ if r.cnt > 0 {
+ result = "{" + result
+ if r.cnt == 2 {
+ r1 := V0 + Reg((uint16(r.r)-uint16(V0)+1)&31)
+ result += ", " + r1.String() + r.a.String()
+ } else if r.cnt > 2 {
+ if (uint16(r.cnt) + ((uint16(r.r) - uint16(V0)) & 31)) > 32 {
+ for i := 1; i < int(r.cnt); i++ {
+ cur := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(i))&31)
+ result += ", " + cur.String() + r.a.String()
+ }
+ } else {
+ r1 := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(r.cnt)-1)&31)
+ result += "-" + r1.String() + r.a.String()
+ }
+ }
+ result += "}"
+ }
+ return result
+}
+
+// Register with arrangement and index: <Vm>.<Ts>[<index>],
+// { <Vt>.B, <Vt2>.B }[<index>].
+type RegisterWithArrangementAndIndex struct {
+ r Reg
+ a Arrangement
+ index uint8
+ cnt uint8
+}
+
+func (RegisterWithArrangementAndIndex) isArg() {}
+
+func (r RegisterWithArrangementAndIndex) String() string {
+ result := r.r.String()
+ result += r.a.String()
+ if r.cnt > 0 {
+ result = "{" + result
+ if r.cnt == 2 {
+ r1 := V0 + Reg((uint16(r.r)-uint16(V0)+1)&31)
+ result += ", " + r1.String() + r.a.String()
+ } else if r.cnt > 2 {
+ if (uint16(r.cnt) + ((uint16(r.r) - uint16(V0)) & 31)) > 32 {
+ for i := 1; i < int(r.cnt); i++ {
+ cur := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(i))&31)
+ result += ", " + cur.String() + r.a.String()
+ }
+ } else {
+ r1 := V0 + Reg((uint16(r.r)-uint16(V0)+uint16(r.cnt)-1)&31)
+ result += "-" + r1.String() + r.a.String()
+ }
+ }
+ result += "}"
+ }
+ return fmt.Sprintf("%s[%d]", result, r.index)
+}
diff --git a/arm64/arm64asm/inst.json b/arm64/arm64asm/inst.json
new file mode 100644
index 0000000..2d25c94
--- /dev/null
+++ b/arm64/arm64asm/inst.json
@@ -0,0 +1,1219 @@
+[{"Name":"ADC","Bits":"0|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADC <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"ADC","Bits":"1|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADC <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"ADCS","Bits":"0|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADCS <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"ADCS","Bits":"1|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADCS <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"ADD (extended register)","Bits":"0|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"ADD (extended register)","Bits":"1|0|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"ADD (immediate)","Bits":"0|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."},
+{"Name":"ADD (immediate)","Bits":"1|0|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias MOV (to/from SP)."},
+{"Name":"ADD (shifted register)","Bits":"0|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADD <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ADD (shifted register)","Bits":"1|0|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ADDS (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."},
+{"Name":"ADDS (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMN (extended register)."},
+{"Name":"ADDS (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."},
+{"Name":"ADDS (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMN (immediate)."},
+{"Name":"ADDS (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."},
+{"Name":"ADDS (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias CMN (shifted register)."},
+{"Name":"ADR","Bits":"0|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADR <Xd>, <label>","Code":"","Alias":""},
+{"Name":"ADRP","Bits":"1|immlo:2|1|0|0|0|0|immhi:19|Rd:5","Arch":"Literal variant","Syntax":"ADRP <Xd>, <label>","Code":"","Alias":""},
+{"Name":"AND (immediate)","Bits":"0|0|0|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"AND <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":""},
+{"Name":"AND (immediate)","Bits":"1|0|0|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"AND <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":""},
+{"Name":"AND (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"AND (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ANDS (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},
+{"Name":"ANDS (immediate)","Bits":"1|1|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ANDS <Xd>, <Xn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},
+{"Name":"ANDS (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias TST (shifted register)."},
+{"Name":"ANDS (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias TST (shifted register)."},
+{"Name":"ASR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the ASRV instruction."},
+{"Name":"ASR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the ASRV instruction."},
+{"Name":"ASR (immediate)","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|011111:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASR <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"ASR (immediate)","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|111111:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASR <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"ASRV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ASRV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias ASR (register)."},
+{"Name":"ASRV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ASRV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias ASR (register)."},
+{"Name":"AT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"AT <at_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"B.cond","Bits":"0|1|0|1|0|1|0|0|imm19:19|0|cond:4","Arch":"19-bit signed PC-relative branch offset variant","Syntax":"B.<cond> <label>","Code":"","Alias":""},
+{"Name":"B","Bits":"0|0|0|1|0|1|imm26:26","Arch":"26-bit signed PC-relative branch offset variant","Syntax":"B <label>","Code":"","Alias":""},
+{"Name":"BFI","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFI <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BFI","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFI <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BFM","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
+{"Name":"BFM","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
+{"Name":"BFXIL","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFXIL <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BFXIL","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFXIL <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the BFM instruction."},
+{"Name":"BIC (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BIC (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BICS (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BICS (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"BL","Bits":"1|0|0|1|0|1|imm26:26","Arch":"26-bit signed PC-relative branch offset variant","Syntax":"BL <label>","Code":"","Alias":""},
+{"Name":"BLR","Bits":"1|1|0|1|0|1|1|0|0|0|1|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"BLR <Xn>","Code":"","Alias":""},
+{"Name":"BR","Bits":"1|1|0|1|0|1|1|0|0|0|0|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"BR <Xn>","Code":"","Alias":""},
+{"Name":"BRK","Bits":"1|1|0|1|0|1|0|0|0|0|1|imm16:16|0|0|0|0|0","Arch":"System variant","Syntax":"BRK #<imm>","Code":"","Alias":""},
+{"Name":"CBNZ","Bits":"0|0|1|1|0|1|0|1|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"CBNZ <Wt>, <label>","Code":"","Alias":""},
+{"Name":"CBNZ","Bits":"1|0|1|1|0|1|0|1|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"CBNZ <Xt>, <label>","Code":"","Alias":""},
+{"Name":"CBZ","Bits":"0|0|1|1|0|1|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"CBZ <Wt>, <label>","Code":"","Alias":""},
+{"Name":"CBZ","Bits":"1|0|1|1|0|1|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"CBZ <Xt>, <label>","Code":"","Alias":""},
+{"Name":"CCMN (immediate)","Bits":"0|0|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMN <Wn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMN (immediate)","Bits":"1|0|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMN <Xn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMN (register)","Bits":"0|0|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMN <Wn>, <Wm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMN (register)","Bits":"1|0|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMN <Xn>, <Xm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (immediate)","Bits":"0|1|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMP <Wn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (immediate)","Bits":"1|1|1|1|1|0|1|0|0|1|0|imm5:5|cond:4|1|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMP <Xn>, #<imm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (register)","Bits":"0|1|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"32-bit variant","Syntax":"CCMP <Wn>, <Wm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CCMP (register)","Bits":"1|1|1|1|1|0|1|0|0|1|0|Rm:5|cond:4|0|0|Rn:5|0|nzcv:4","Arch":"64-bit variant","Syntax":"CCMP <Xn>, <Xm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"CINC","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CINC <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CINC","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CINC <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CINV","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CINV <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CINV","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CINV <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CLREX","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|0|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"CLREX {#<imm>}","Code":"","Alias":""},
+{"Name":"CLS","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CLS <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"CLS","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CLS <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"CLZ","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CLZ <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"CLZ","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CLZ <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"CMN (extended register)","Bits":"0|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the ADDS (extended register) instruction."},
+{"Name":"CMN (extended register)","Bits":"1|0|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the ADDS (extended register) instruction."},
+{"Name":"CMN (immediate)","Bits":"0|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the ADDS (immediate) instruction."},
+{"Name":"CMN (immediate)","Bits":"1|0|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the ADDS (immediate) instruction."},
+{"Name":"CMN (shifted register)","Bits":"0|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMN <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ADDS (shifted register) instruction."},
+{"Name":"CMN (shifted register)","Bits":"1|0|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMN <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ADDS (shifted register) instruction."},
+{"Name":"CMP (extended register)","Bits":"0|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the SUBS (extended register) instruction."},
+{"Name":"CMP (extended register)","Bits":"1|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is an alias of the SUBS (extended register) instruction."},
+{"Name":"CMP (immediate)","Bits":"0|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the SUBS (immediate) instruction."},
+{"Name":"CMP (immediate)","Bits":"1|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is an alias of the SUBS (immediate) instruction."},
+{"Name":"CMP (shifted register)","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"CMP <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"CMP (shifted register)","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"CMP <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"CNEG","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CNEG <Wd>, <Wn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSNEG instruction."},
+{"Name":"CNEG","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CNEG <Xd>, <Xn>, <cond>","Code":"","Alias":"This instruction is an alias of the CSNEG instruction."},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|00:2|Rn:5|Rd:5","Arch":"CRC32B variant","Syntax":"CRC32B <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|01:2|Rn:5|Rd:5","Arch":"CRC32H variant","Syntax":"CRC32H <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|10:2|Rn:5|Rd:5","Arch":"CRC32W variant","Syntax":"CRC32W <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32B, CRC32H, CRC32W, CRC32X","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|0|11:2|Rn:5|Rd:5","Arch":"CRC32X variant","Syntax":"CRC32X <Wd>, <Wn>, <Xm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|00:2|Rn:5|Rd:5","Arch":"CRC32CB variant","Syntax":"CRC32CB <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|01:2|Rn:5|Rd:5","Arch":"CRC32CH variant","Syntax":"CRC32CH <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|10:2|Rn:5|Rd:5","Arch":"CRC32CW variant","Syntax":"CRC32CW <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"CRC32CB, CRC32CH, CRC32CW, CRC32CX","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|1|0|1|11:2|Rn:5|Rd:5","Arch":"CRC32CX variant","Syntax":"CRC32CX <Wd>, <Wn>, <Xm>","Code":"","Alias":""},
+{"Name":"CSEL","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSEL <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":""},
+{"Name":"CSEL","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSEL <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":""},
+{"Name":"CSET","Bits":"0|0|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|1|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"CSET <Wd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CSET","Bits":"1|0|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|1|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"CSET <Xd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINC instruction."},
+{"Name":"CSETM","Bits":"0|1|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"CSETM <Wd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CSETM","Bits":"1|1|0|1|1|0|1|0|1|0|0|1|1|1|1|1|cond:4|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"CSETM <Xd>, <cond>","Code":"","Alias":"This instruction is an alias of the CSINV instruction."},
+{"Name":"CSINC","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSINC <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINC and CSET."},
+{"Name":"CSINC","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSINC <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINC and CSET."},
+{"Name":"CSINV","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSINV <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINV and CSETM."},
+{"Name":"CSINV","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSINV <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the aliases CINV and CSETM."},
+{"Name":"CSNEG","Bits":"0|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSNEG <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":"This instruction is used by the alias CNEG."},
+{"Name":"CSNEG","Bits":"1|1|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSNEG <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":"This instruction is used by the alias CNEG."},
+{"Name":"DC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"DC <dc_op>, <Xt>","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"DCPS1","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"DCPS1 {#<imm>}","Code":"","Alias":""},
+{"Name":"DCPS2","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"DCPS2 {#<imm>}","Code":"","Alias":""},
+{"Name":"DCPS3","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"DCPS3 {#<imm>}","Code":"","Alias":""},
+{"Name":"DMB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"DMB <option>|#<imm>","Code":"","Alias":""},
+{"Name":"DRPS","Bits":"1|1|0|1|0|1|1|0|1|0|1|1|1|1|1|1|0|0|0|0|0|0|1|1|1|1|1|0|0|0|0|0","Arch":"System variant","Syntax":"DRPS","Code":"","Alias":""},
+{"Name":"DSB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"DSB <option>|#<imm>","Code":"","Alias":""},
+{"Name":"EON (shifted register)","Bits":"0|1|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"EON (shifted register)","Bits":"1|1|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"EOR (immediate)","Bits":"0|1|0|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EOR <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":""},
+{"Name":"EOR (immediate)","Bits":"1|1|0|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EOR <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":""},
+{"Name":"EOR (shifted register)","Bits":"0|1|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"EOR (shifted register)","Bits":"1|1|0|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
+{"Name":"ERET","Bits":"1|1|0|1|0|1|1|0|1|0|0|1|1|1|1|1|0|0|0|0|0|0|1|1|1|1|1|0|0|0|0|0","Arch":"System variant","Syntax":"ERET","Code":"","Alias":""},
+{"Name":"EXTR","Bits":"0|0|0|1|0|0|1|1|1|0|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"EXTR <Wd>, <Wn>, <Wm>, #<lsb>","Code":"","Alias":"This instruction is used by the alias ROR (immediate)."},
+{"Name":"EXTR","Bits":"1|0|0|1|0|0|1|1|1|1|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"EXTR <Xd>, <Xn>, <Xm>, #<lsb>","Code":"","Alias":"This instruction is used by the alias ROR (immediate)."},
+{"Name":"HINT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0000:4|op2:3|1|1|1|1|1","Arch":"Hints 6 and 7 variant","Syntax":"HINT #<imm>","Code":"","Alias":""},
+{"Name":"HINT","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|CRm:4|op2:3|1|1|1|1|1","Arch":"Hints 8 to 127 variant","Syntax":"HINT #<imm>","Code":"","Alias":""},
+{"Name":"HLT","Bits":"1|1|0|1|0|1|0|0|0|1|0|imm16:16|0|0|0|0|0","Arch":"System variant","Syntax":"HLT #<imm>","Code":"","Alias":""},
+{"Name":"HVC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"HVC #<imm>","Code":"","Alias":""},
+{"Name":"IC","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|0|1|1|1|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"IC <ic_op>{, <Xt>}","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"ISB","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|1|CRm:4|1|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"ISB {<option>|#<imm>}","Code":"","Alias":""},
+{"Name":"LDAR","Bits":"10:2|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAR","Bits":"11:2|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDARB","Bits":"0|0|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDARB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDARH","Bits":"0|1|0|0|1|0|0|0|1|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDARH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXP","Bits":"1|0|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|1|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXP","Bits":"1|1|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|1|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXR","Bits":"10:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDAXR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXR","Bits":"11:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDAXR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXRB","Bits":"0|0|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDAXRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDAXRH","Bits":"0|1|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDAXRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDNP","Bits":"00:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDNP","Bits":"10:2|1|0|1|0|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP","Bits":"00:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP","Bits":"10:2|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP","Bits":"00:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP","Bits":"10:2|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDPSW","Bits":"0|1|1|0|1|0|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset Signed offset variant","Syntax":"LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"10:2|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate)","Bits":"11:2|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (literal)","Bits":"00:2|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"LDR <Wt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (literal)","Bits":"01:2|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Xt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (register)","Bits":"10:2|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register)","Bits":"11:2|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRH (immediate)","Bits":"0|1|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRH (register)","Bits":"0|1|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDRSB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSB (immediate)","Bits":"0|0|1|1|1|0|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDRSB <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit with extended register offset variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|11:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit with shifted register offset variant","Syntax":"LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit with extended register offset variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDRSB (register)","Bits":"0|0|1|1|1|0|0|0|10:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit with shifted register offset variant","Syntax":"LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSH (immediate)","Bits":"0|1|1|1|1|0|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSH (register)","Bits":"0|1|1|1|1|0|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRSH (register)","Bits":"0|1|1|1|1|0|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRSW <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRSW <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDRSW (immediate)","Bits":"1|0|1|1|1|0|0|1|1|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDRSW (literal)","Bits":"1|0|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"Literal variant","Syntax":"LDRSW <Xt>, <label>","Code":"","Alias":""},
+{"Name":"LDRSW (register)","Bits":"1|0|1|1|1|0|0|0|1|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDTR","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTR","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRB","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRH","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSB","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTRSB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSB","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTRSB <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSH","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDTRSH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSH","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDTRSH <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDTRSW","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDTRSW <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR","Bits":"10:2|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDUR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR","Bits":"11:2|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDUR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURB","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURH","Bits":"0|1|1|1|1|0|0|0|0|1|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSB","Bits":"0|0|1|1|1|0|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDURSB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSB","Bits":"0|0|1|1|1|0|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDURSB <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSH","Bits":"0|1|1|1|1|0|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDURSH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSH","Bits":"0|1|1|1|1|0|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDURSH <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDURSW","Bits":"1|0|1|1|1|0|0|0|1|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"LDURSW <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDXP","Bits":"1|0|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|0|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDXP <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXP","Bits":"1|1|0|0|1|0|0|0|0|1|1|(1)|(1)|(1)|(1)|(1)|0|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXR","Bits":"10:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDXR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXR","Bits":"11:2|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDXR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXRB","Bits":"0|0|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDXRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LDXRH","Bits":"0|1|0|0|1|0|0|0|0|1|0|(1)|(1)|(1)|(1)|(1)|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"LDXRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"LSL (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSL <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSLV instruction."},
+{"Name":"LSL (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSL <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the LSLV instruction."},
+{"Name":"LSL (immediate)","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSL <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSL (immediate)","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSL <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSLV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSLV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias LSL (register)."},
+{"Name":"LSLV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSLV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias LSL (register)."},
+{"Name":"LSR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},
+{"Name":"LSR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the LSRV instruction."},
+{"Name":"LSR (immediate)","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|011111:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSR <Wd>, <Wn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSR (immediate)","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|111111:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSR <Xd>, <Xn>, #<shift>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"LSRV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"LSRV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias LSR (register)."},
+{"Name":"LSRV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"LSRV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias LSR (register)."},
+{"Name":"MADD","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MADD <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MUL."},
+{"Name":"MADD","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MADD <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MUL."},
+{"Name":"MNEG","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MNEG <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the MSUB instruction."},
+{"Name":"MNEG","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MNEG <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the MSUB instruction."},
+{"Name":"MOV (to/from SP)","Bits":"0|0|0|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd|WSP>, <Wn|WSP>","Code":"","Alias":"This instruction is an alias of the ADD (immediate) instruction."},
+{"Name":"MOV (to/from SP)","Bits":"1|0|0|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd|SP>, <Xn|SP>","Code":"","Alias":"This instruction is an alias of the ADD (immediate) instruction."},
+{"Name":"MOV (inverted wide immediate)","Bits":"0|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVN instruction."},
+{"Name":"MOV (inverted wide immediate)","Bits":"1|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVN instruction."},
+{"Name":"MOV (wide immediate)","Bits":"0|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVZ instruction."},
+{"Name":"MOV (wide immediate)","Bits":"1|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, #<imm>","Code":"","Alias":"This instruction is an alias of the MOVZ instruction."},
+{"Name":"MOV (bitmask immediate)","Bits":"0|0|1|1|0|0|1|0|0|0|immr:6|imms:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd|WSP>, #<imm>","Code":"","Alias":"This instruction is an alias of the ORR (immediate) instruction."},
+{"Name":"MOV (bitmask immediate)","Bits":"1|0|1|1|0|0|1|0|0|N|immr:6|imms:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd|SP>, #<imm>","Code":"","Alias":"This instruction is an alias of the ORR (immediate) instruction."},
+{"Name":"MOV (register)","Bits":"0|0|1|0|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the ORR (shifted register) instruction."},
+{"Name":"MOV (register)","Bits":"1|0|1|0|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the ORR (shifted register) instruction."},
+{"Name":"MOVK","Bits":"0|1|1|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVK <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":""},
+{"Name":"MOVK","Bits":"1|1|1|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVK <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":""},
+{"Name":"MOVN","Bits":"0|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVN <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (inverted wide immediate)."},
+{"Name":"MOVN","Bits":"1|0|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVN <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (inverted wide immediate)."},
+{"Name":"MOVZ","Bits":"0|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"32-bit variant","Syntax":"MOVZ <Wd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (wide immediate)."},
+{"Name":"MOVZ","Bits":"1|1|0|1|0|0|1|0|1|hw:2|imm16:16|Rd:5","Arch":"64-bit variant","Syntax":"MOVZ <Xd>, #<imm>{, LSL #<shift>}","Code":"","Alias":"This instruction is used by the alias MOV (wide immediate)."},
+{"Name":"MRS","Bits":"1|1|0|1|0|1|0|1|0|0|1|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MRS <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)","Code":"","Alias":""},
+{"Name":"MSR (immediate)","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|op1:3|0|1|0|0|CRm:4|op2:3|1|1|1|1|1","Arch":"System variant","Syntax":"MSR <pstatefield>, #<imm>","Code":"","Alias":""},
+{"Name":"MSR (register)","Bits":"1|1|0|1|0|1|0|1|0|0|0|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MSR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>","Code":"","Alias":""},
+{"Name":"MSUB","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MSUB <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MNEG."},
+{"Name":"MSUB","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MSUB <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MNEG."},
+{"Name":"MUL","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MUL <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the MADD instruction."},
+{"Name":"MUL","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MUL <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the MADD instruction."},
+{"Name":"MVN","Bits":"0|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"MVN <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ORN (shifted register) instruction."},
+{"Name":"MVN","Bits":"1|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"MVN <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ORN (shifted register) instruction."},
+{"Name":"NEG (shifted register)","Bits":"0|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NEG <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUB (shifted register) instruction."},
+{"Name":"NEG (shifted register)","Bits":"1|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NEG <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUB (shifted register) instruction."},
+{"Name":"NEGS","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NEGS <Wd>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"NEGS","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NEGS <Xd>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the SUBS (shifted register) instruction."},
+{"Name":"NGC","Bits":"0|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NGC <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the SBC instruction."},
+{"Name":"NGC","Bits":"1|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NGC <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the SBC instruction."},
+{"Name":"NGCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"32-bit variant","Syntax":"NGCS <Wd>, <Wm>","Code":"","Alias":"This instruction is an alias of the SBCS instruction."},
+{"Name":"NGCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|1|1|1|1|1|Rd:5","Arch":"64-bit variant","Syntax":"NGCS <Xd>, <Xm>","Code":"","Alias":"This instruction is an alias of the SBCS instruction."},
+{"Name":"NOP","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"NOP","Code":"","Alias":""},
+{"Name":"ORN (shifted register)","Bits":"0|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MVN."},
+{"Name":"ORN (shifted register)","Bits":"1|0|1|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MVN."},
+{"Name":"ORR (immediate)","Bits":"0|0|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Wd|WSP>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias MOV (bitmask immediate)."},
+{"Name":"ORR (immediate)","Bits":"1|0|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORR <Xd|SP>, <Xn>, #<imm>","Code":"","Alias":"This instruction is used by the alias MOV (bitmask immediate)."},
+{"Name":"ORR (shifted register)","Bits":"0|0|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MOV (register)."},
+{"Name":"ORR (shifted register)","Bits":"1|0|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ORR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias MOV (register)."},
+{"Name":"PRFM (immediate)","Bits":"1|1|1|1|1|0|0|1|1|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset variant","Syntax":"PRFM (<prfop>|#<imm5>), [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"PRFM (literal)","Bits":"1|1|0|1|1|0|0|0|imm19:19|Rt:5","Arch":"Literal variant","Syntax":"PRFM (<prfop>|#<imm5>), <label>","Code":"","Alias":""},
+{"Name":"PRFM (register)","Bits":"1|1|1|1|1|0|0|0|1|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Integer variant","Syntax":"PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"PRFM (unscaled offset)","Bits":"1|1|1|1|1|0|0|0|1|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"PRFUM (<prfop>|#<imm5>), [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"RBIT","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"RBIT <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"RBIT","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"RBIT <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"RET","Bits":"1|1|0|1|0|1|1|0|0|1|0|1|1|1|1|1|0|0|0|0|0|0|Rn:5|0|0|0|0|0","Arch":"Integer variant","Syntax":"RET {<Xn>}","Code":"","Alias":""},
+{"Name":"REV","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|10:2|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"REV <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"REV","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|11:2|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"REV16","Bits":"0|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"REV16 <Wd>, <Wn>","Code":"","Alias":""},
+{"Name":"REV16","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV16 <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"REV32","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV32 <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"REV64","Bits":"1|1|0|1|1|0|1|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"REV64 <Xd>, <Xn>","Code":"","Alias":""},
+{"Name":"ROR (immediate)","Bits":"0|0|0|1|0|0|1|1|1|0|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ROR <Wd>, <Ws>, #<shift>","Code":"","Alias":"This instruction is an alias of the EXTR instruction."},
+{"Name":"ROR (immediate)","Bits":"1|0|0|1|0|0|1|1|1|1|0|Rm:5|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ROR <Xd>, <Xs>, #<shift>","Code":"","Alias":"This instruction is an alias of the EXTR instruction."},
+{"Name":"ROR (register)","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ROR <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the RORV instruction."},
+{"Name":"ROR (register)","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ROR <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is an alias of the RORV instruction."},
+{"Name":"RORV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"RORV <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias ROR (register)."},
+{"Name":"RORV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"RORV <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias ROR (register)."},
+{"Name":"SBC","Bits":"0|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBC <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGC."},
+{"Name":"SBC","Bits":"1|1|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBC <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGC."},
+{"Name":"SBCS","Bits":"0|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBCS <Wd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
+{"Name":"SBCS","Bits":"1|1|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBCS <Xd>, <Xn>, <Xm>","Code":"","Alias":"This instruction is used by the alias NGCS."},
+{"Name":"SBFIZ","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFIZ <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SBFIZ","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFIZ <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SBFM","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW."},
+{"Name":"SBFM","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW."},
+{"Name":"SBFX","Bits":"0|0|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SBFX <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SBFX","Bits":"1|0|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SBFX <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"SDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"SEV","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|1|0|0|1|1|1|1|1","Arch":"System variant","Syntax":"SEV","Code":"","Alias":""},
+{"Name":"SEVL","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|1|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"SEVL","Code":"","Alias":""},
+{"Name":"SMADDL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMADDL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias SMULL."},
+{"Name":"SMC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"SMC #<imm>","Code":"","Alias":""},
+{"Name":"SMNEGL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the SMSUBL instruction."},
+{"Name":"SMSUBL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias SMNEGL."},
+{"Name":"SMULH","Bits":"1|0|0|1|1|0|1|1|0|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"SMULL","Bits":"1|0|0|1|1|0|1|1|0|0|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMULL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the SMADDL instruction."},
+{"Name":"STLR","Bits":"10:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLR","Bits":"11:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLRB","Bits":"0|0|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLRB <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLRH","Bits":"0|1|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLRH <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXP","Bits":"1|0|0|0|1|0|0|0|0|0|1|Rs:5|1|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXP","Bits":"1|1|0|0|1|0|0|0|0|0|1|Rs:5|1|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXRB","Bits":"0|0|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STLXRH","Bits":"0|1|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STLXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STNP","Bits":"00:2|1|0|1|0|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STNP","Bits":"10:2|1|0|1|0|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP","Bits":"00:2|1|0|1|0|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP","Bits":"10:2|1|0|1|0|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP","Bits":"00:2|1|0|1|0|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP","Bits":"10:2|1|0|1|0|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP","Bits":"00:2|1|0|1|0|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"STP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP","Bits":"10:2|1|0|1|0|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"10:2|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate)","Bits":"11:2|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (register)","Bits":"10:2|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register)","Bits":"11:2|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"STRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"STRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"STRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STRB (register)","Bits":"0|0|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"STRB (register)","Bits":"0|0|1|1|1|0|0|0|0|0|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"STRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"STRH <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"STRH <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STRH (immediate)","Bits":"0|1|1|1|1|0|0|1|0|0|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"STRH <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STRH (register)","Bits":"0|1|1|1|1|0|0|0|0|0|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STTR","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STTR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STTR","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STTR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STTRB","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STTRB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STTRH","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|1|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STTRH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR","Bits":"10:2|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STUR <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR","Bits":"11:2|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STUR <Xt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STURB","Bits":"0|0|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STURB <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STURH","Bits":"0|1|1|1|1|0|0|0|0|0|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"Unscaled offset variant","Syntax":"STURH <Wt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STXP","Bits":"1|0|0|0|1|0|0|0|0|0|1|Rs:5|0|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXP","Bits":"1|1|0|0|1|0|0|0|0|0|1|Rs:5|0|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXRB","Bits":"0|0|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"STXRH","Bits":"0|1|0|0|1|0|0|0|0|0|0|Rs:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"No offset variant","Syntax":"STXRH <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
+{"Name":"SUB (extended register)","Bits":"0|1|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"SUB (extended register)","Bits":"1|1|0|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":""},
+{"Name":"SUB (immediate)","Bits":"0|1|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":""},
+{"Name":"SUB (immediate)","Bits":"1|1|0|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":""},
+{"Name":"SUB (shifted register)","Bits":"0|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUB <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias NEG (shifted register)."},
+{"Name":"SUB (shifted register)","Bits":"1|1|0|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the alias NEG (shifted register)."},
+{"Name":"SUBS (extended register)","Bits":"0|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMP (extended register)."},
+{"Name":"SUBS (extended register)","Bits":"1|1|1|0|1|0|1|1|0|0|1|Rm:5|option:3|imm3:3|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}","Code":"","Alias":"This instruction is used by the alias CMP (extended register)."},
+{"Name":"SUBS (immediate)","Bits":"0|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMP (immediate)."},
+{"Name":"SUBS (immediate)","Bits":"1|1|1|1|0|0|0|1|shift:2|imm12:12|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}","Code":"","Alias":"This instruction is used by the alias CMP (immediate)."},
+{"Name":"SUBS (shifted register)","Bits":"0|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the aliases CMP (shifted register) and NEGS."},
+{"Name":"SUBS (shifted register)","Bits":"1|1|1|0|1|0|1|1|shift:2|0|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is used by the aliases CMP (shifted register) and NEGS."},
+{"Name":"SVC","Bits":"1|1|0|1|0|1|0|0|0|0|0|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"SVC #<imm>","Code":"","Alias":""},
+{"Name":"SXTB","Bits":"0|0|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SXTB <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTB","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTB <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTH","Bits":"0|0|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SXTH <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTH","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTH <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SXTW","Bits":"1|0|0|1|0|0|1|1|0|1|0|0|0|0|0|0|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SXTW <Xd>, <Wn>","Code":"","Alias":"This instruction is an alias of the SBFM instruction."},
+{"Name":"SYS","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}","Code":"","Alias":"This instruction is used by the aliases AT, DC, IC, and TLBI."},
+{"Name":"SYSL","Bits":"1|1|0|1|0|1|0|1|0|0|1|0|1|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>","Code":"","Alias":""},
+{"Name":"TBNZ","Bits":"b5|0|1|1|0|1|1|1|b40:5|imm14:14|Rt:5","Arch":"14-bit signed PC-relative branch offset variant","Syntax":"TBNZ <R><t>, #<imm>, <label>","Code":"","Alias":""},
+{"Name":"TBZ","Bits":"b5|0|1|1|0|1|1|0|b40:5|imm14:14|Rt:5","Arch":"14-bit signed PC-relative branch offset variant","Syntax":"TBZ <R><t>, #<imm>, <label>","Code":"","Alias":""},
+{"Name":"TLBI","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|1|op1:3|1|0|0|0|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"TLBI <tlbi_op>{, <Xt>}","Code":"","Alias":"This instruction is an alias of the SYS instruction."},
+{"Name":"TST (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"TST <Wn>, #<imm>","Code":"","Alias":"This instruction is an alias of the ANDS (immediate) instruction."},
+{"Name":"TST (immediate)","Bits":"1|1|1|1|0|0|1|0|0|N|immr:6|imms:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"TST <Xn>, #<imm>","Code":"","Alias":"This instruction is an alias of the ANDS (immediate) instruction."},
+{"Name":"TST (shifted register)","Bits":"0|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"32-bit variant","Syntax":"TST <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ANDS (shifted register) instruction."},
+{"Name":"TST (shifted register)","Bits":"1|1|1|0|1|0|1|0|shift:2|0|Rm:5|imm6:6|Rn:5|1|1|1|1|1","Arch":"64-bit variant","Syntax":"TST <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":"This instruction is an alias of the ANDS (shifted register) instruction."},
+{"Name":"UBFIZ","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFIZ <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UBFIZ","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFIZ <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UBFM","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},
+{"Name":"UBFM","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH."},
+{"Name":"UBFX","Bits":"0|1|0|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UBFX <Wd>, <Wn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UBFX","Bits":"1|1|0|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UBFX <Xd>, <Xn>, #<lsb>, #<width>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UDIV","Bits":"0|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UDIV <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
+{"Name":"UDIV","Bits":"1|0|0|1|1|0|1|0|1|1|0|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UDIV <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"UMADDL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMADDL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMULL."},
+{"Name":"UMNEGL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMNEGL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMSUBL instruction."},
+{"Name":"UMSUBL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMSUBL <Xd>, <Wn>, <Wm>, <Xa>","Code":"","Alias":"This instruction is used by the alias UMNEGL."},
+{"Name":"UMULH","Bits":"1|0|0|1|1|0|1|1|1|1|0|Rm:5|0|(1)|(1)|(1)|(1)|(1)|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULH <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
+{"Name":"UMULL","Bits":"1|0|0|1|1|0|1|1|1|0|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMULL <Xd>, <Wn>, <Wm>","Code":"","Alias":"This instruction is an alias of the UMADDL instruction."},
+{"Name":"UXTB","Bits":"0|1|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UXTB <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"UXTH","Bits":"0|1|0|1|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UXTH <Wd>, <Wn>","Code":"","Alias":"This instruction is an alias of the UBFM instruction."},
+{"Name":"WFE","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|1|0|1|1|1|1|1","Arch":"System variant","Syntax":"WFE","Code":"","Alias":""},
+{"Name":"WFI","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|1|1|1|1|1|1|1","Arch":"System variant","Syntax":"WFI","Code":"","Alias":""},
+{"Name":"YIELD","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|1|0|0|0|0|0|0|0|1|1|1|1|1|1","Arch":"System variant","Syntax":"YIELD","Code":"","Alias":""},
+{"Name":"ABS","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"ABS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"ABS","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"ABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"ADD (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"ADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"ADD (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ADDHN, ADDHN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"ADDHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"ADDHN, ADDHN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"ADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"ADDP (scalar)","Bits":"0|1|0|1|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"ADDP (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ADDV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ADDV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"AESD","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESD <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AESE","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESE <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AESIMC","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESIMC <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AESMC","Bits":"0|1|0|0|1|1|1|0|0|0|1|0|1|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"AESMC <Vd>.16B, <Vn>.16B","Code":"","Alias":""},
+{"Name":"AND (vector)","Bits":"0|Q|0|0|1|1|1|0|0|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BIC (vector, immediate)","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit variant","Syntax":"BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"BIC (vector, immediate)","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"BIC (vector, register)","Bits":"0|Q|0|0|1|1|1|0|0|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BIF","Bits":"0|Q|1|0|1|1|1|0|1|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BIT","Bits":"0|Q|1|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"BSL","Bits":"0|Q|1|0|1|1|1|0|0|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CLS (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CLS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"CLZ (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CLZ <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"CMEQ (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMEQ <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMEQ (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMEQ (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMEQ <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMEQ (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMEQ <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMGE (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMGE (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMGE (zero)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGE <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMGE (zero)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGE <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMGT (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMGT (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMGT (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMGT <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMGT (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMGT <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMHI (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMHI <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMHI (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMHI <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMHS (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMHS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMHS (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CMLE (zero)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMLE <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMLE (zero)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMLE <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMLT (zero)","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMLT <V><d>, <V><n>, #0","Code":"","Alias":""},
+{"Name":"CMLT (zero)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMLT <Vd>.<T>, <Vn>.<T>, #0","Code":"","Alias":""},
+{"Name":"CMTST","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"CMTST <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"CMTST","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"CNT","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"CNT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"DUP (element)","Bits":"0|1|0|1|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"DUP <V><d>, <Vn>.<T>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (scalar)."},
+{"Name":"DUP (element)","Bits":"0|Q|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"DUP <Vd>.<T>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (scalar)."},
+{"Name":"DUP (general)","Bits":"0|Q|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"DUP <Vd>.<T>, <R><n>","Code":"","Alias":""},
+{"Name":"EOR (vector)","Bits":"0|Q|1|0|1|1|1|0|0|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"EXT","Bits":"0|Q|1|0|1|1|1|0|0|0|0|Rm:5|0|imm4:4|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>","Code":"","Alias":""},
+{"Name":"FABD","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FABD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FABD","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FABS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FABS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FABS <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FABS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FABS <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FACGE","Bits":"0|1|1|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FACGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FACGE","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FACGT","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FACGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FACGT","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FADD (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FADD <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FADD <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FADDP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FADDP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FADDP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FCCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|0|1|Rn:5|0|nzcv:4","Arch":"Single-precision variant","Syntax":"FCCMP <Sn>, <Sm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|0|1|Rn:5|0|nzcv:4","Arch":"Double-precision variant","Syntax":"FCCMP <Dn>, <Dm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|0|1|Rn:5|1|nzcv:4","Arch":"Single-precision variant","Syntax":"FCCMPE <Sn>, <Sm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|0|1|Rn:5|1|nzcv:4","Arch":"Double-precision variant","Syntax":"FCCMPE <Dn>, <Dm>, #<nzcv>, <cond>","Code":"","Alias":""},
+{"Name":"FCMEQ (register)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMEQ <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FCMEQ (register)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FCMEQ (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMEQ <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMEQ (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGE (register)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGE <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FCMGE (register)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FCMGE (zero)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGE <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGE (zero)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGE <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGT (register)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGT <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FCMGT (register)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FCMGT (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMGT <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMGT (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMGT <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMLE (zero)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMLE <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMLE (zero)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMLE <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMLT (zero)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCMLT <V><d>, <V><n>, #0.0","Code":"","Alias":""},
+{"Name":"FCMLT (zero)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCMLT <Vd>.<T>, <Vn>.<T>, #0.0","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|0|0|Rn:5|00:2|0|0|0","Arch":"Single-precision variant","Syntax":"FCMP <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|00:2|1|(00000):5|0|0|1|0|0|0|Rn:5|01:2|0|0|0","Arch":"Single-precision, zero variant","Syntax":"FCMP <Sn>, #0.0","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|0|0|Rn:5|00:2|0|0|0","Arch":"Double-precision variant","Syntax":"FCMP <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FCMP","Bits":"0|0|0|1|1|1|1|0|01:2|1|(00000):5|0|0|1|0|0|0|Rn:5|01:2|0|0|0","Arch":"Double-precision, zero variant","Syntax":"FCMP <Dn>, #0.0","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|0|0|Rn:5|10:2|0|0|0","Arch":"Single-precision variant","Syntax":"FCMPE <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|00:2|1|(00000):5|0|0|1|0|0|0|Rn:5|11:2|0|0|0","Arch":"Single-precision, zero variant","Syntax":"FCMPE <Sn>, #0.0","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|0|0|0|Rn:5|10:2|0|0|0","Arch":"Double-precision variant","Syntax":"FCMPE <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FCMPE","Bits":"0|0|0|1|1|1|1|0|01:2|1|(00000):5|0|0|1|0|0|0|Rn:5|11:2|0|0|0","Arch":"Double-precision, zero variant","Syntax":"FCMPE <Dn>, #0.0","Code":"","Alias":""},
+{"Name":"FCSEL","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|cond:4|1|1|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FCSEL <Sd>, <Sn>, <Sm>, <cond>","Code":"","Alias":""},
+{"Name":"FCSEL","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|cond:4|1|1|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FCSEL <Dd>, <Dn>, <Dm>, <cond>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|11:2|1|0|0|0|1|00:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Half-precision to single-precision variant","Syntax":"FCVT <Sd>, <Hn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|11:2|1|0|0|0|1|01:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Half-precision to double-precision variant","Syntax":"FCVT <Dd>, <Hn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|11:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to half-precision variant","Syntax":"FCVT <Hd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|01:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to double-precision variant","Syntax":"FCVT <Dd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|11:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to half-precision variant","Syntax":"FCVT <Hd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVT","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|00:2|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to single-precision variant","Syntax":"FCVT <Sd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTAS (vector)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTAS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTAS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTAS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTAS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTAS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTAS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTAS <Wd>, <Dn>","Code":"","Alias":""},
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+{"Name":"FCVTMU (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTMU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
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+{"Name":"FCVTMU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTMU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTMU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTMU <Xd>, <Dn>","Code":"","Alias":""},
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+{"Name":"FCVTNS (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTNS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
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+{"Name":"FCVTNS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTNS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTNS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTNS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTNS <Xd>, <Dn>","Code":"","Alias":""},
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+{"Name":"FCVTNU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTNU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTNU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTNU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTNU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTNU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPS (vector)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTPS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTPS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTPS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTPS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTPS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTPS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPS (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTPS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPU (vector)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTPU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTPU (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTPU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTPU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTPU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTPU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTPU (scalar)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTPU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTXN, FCVTXN2","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTXN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"FCVTXN, FCVTXN2","Bits":"0|0|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTXN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"FCVTXN, FCVTXN2","Bits":"0|1|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTXN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"FCVTZS (vector, fixed-point)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZS <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (vector, fixed-point)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"FCVTZS (vector, integer)","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTZS (vector, integer)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTZS (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTZU (vector, fixed-point)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZU <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (vector, fixed-point)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZU <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"FCVTZU (vector, integer)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FCVTZU <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FCVTZU (vector, integer)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FCVTZU <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Sn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|1|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Sn>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 32-bit variant","Syntax":"FCVTZU <Wd>, <Dn>","Code":"","Alias":""},
+{"Name":"FCVTZU (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|1|1|0|0|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZU <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FDIV (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FDIV <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FDIV (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FDIV <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMADD","Bits":"0|0|0|1|1|1|1|1|00:2|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMADD <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FMADD","Bits":"0|0|0|1|1|1|1|1|01:2|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMADD <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FMAX (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAX (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMAX <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMAX (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMAX <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMAXNM (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAXNM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMAXNM <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMAXNM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMAXNM <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMAXNMP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXNMP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMAXNMP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAXNMV","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXNMV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMAXP (scalar)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMAXP (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMAXV","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMIN (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMIN (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMIN <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMIN (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMIN <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMINNM (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMINNM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMINNM <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMINNM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMINNM <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMINNMP (scalar)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINNMP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMINNMP (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMINNMV","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINNMV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMINP (scalar)","Bits":"0|1|1|1|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINP <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMINP (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMINV","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|1|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision and double-precision variant","Syntax":"FMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FMLA (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|0|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLA (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|0|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLA (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMLS (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|0|1|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMLS <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLS (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|0|1|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMLS (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMOV (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|1|1|1|1|0|1|d|e|f|g|h|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Vd>.<T>, #<imm>","Code":"","Alias":""},
+{"Name":"FMOV (vector, immediate)","Bits":"0|1|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1|1|1|1|0|1|d|e|f|g|h|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Vd>.2D, #<imm>","Code":"","Alias":""},
+{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"FMOV <Sd>, <Wn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FMOV <Wd>, <Sn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|01:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"FMOV <Dd>, <Xn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|10:2|1|01:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to top half of 128-bit variant","Syntax":"FMOV <Vd>.D[1], <Xn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|01:2|1|00:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FMOV <Xd>, <Dn>","Code":"","Alias":""},
+{"Name":"FMOV (general)","Bits":"1|0|0|1|1|1|1|0|10:2|1|01:2|110:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Top half of 128-bit to 64-bit variant","Syntax":"FMOV <Xd>, <Vn>.D[1]","Code":"","Alias":""},
+{"Name":"FMOV (scalar, immediate)","Bits":"0|0|0|1|1|1|1|0|00:2|1|imm8:8|1|0|0|0|0|0|0|0|Rd:5","Arch":"Single-precision variant","Syntax":"FMOV <Sd>, #<imm>","Code":"","Alias":""},
+{"Name":"FMOV (scalar, immediate)","Bits":"0|0|0|1|1|1|1|0|01:2|1|imm8:8|1|0|0|0|0|0|0|0|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, #<imm>","Code":"","Alias":""},
+{"Name":"FMSUB","Bits":"0|0|0|1|1|1|1|1|00:2|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMSUB <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FMSUB","Bits":"0|0|0|1|1|1|1|1|01:2|0|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMSUB <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FMUL (by element)","Bits":"0|1|0|1|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMUL (by element)","Bits":"0|Q|0|0|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMUL (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FMUL <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMUL <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FMULX (by element)","Bits":"0|1|1|1|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMULX <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMULX (by element)","Bits":"0|Q|1|0|1|1|1|1|1|sz|L|M|Rm:4|1|0|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"FMULX","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FMULX <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FMULX","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FMULX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FNEG (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|0|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FNEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FNEG (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNEG <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FNEG (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNEG <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FNMADD","Bits":"0|0|0|1|1|1|1|1|00:2|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMADD <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FNMADD","Bits":"0|0|0|1|1|1|1|1|01:2|1|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMADD <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FNMSUB","Bits":"0|0|0|1|1|1|1|1|00:2|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMSUB <Sd>, <Sn>, <Sm>, <Sa>","Code":"","Alias":""},
+{"Name":"FNMSUB","Bits":"0|0|0|1|1|1|1|1|01:2|1|Rm:5|1|Ra:5|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMSUB <Dd>, <Dn>, <Dm>, <Da>","Code":"","Alias":""},
+{"Name":"FNMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FNMUL <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FNMUL (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FNMUL <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"FRECPE","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRECPE <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FRECPE","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRECPE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRECPS","Bits":"0|1|0|1|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRECPS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FRECPS","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FRECPX","Bits":"0|1|0|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar single-precision and double-precision variant","Syntax":"FRECPX <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FRINTA (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTA <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTA (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTA <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTA (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTA <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTI (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTI <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTI (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTI <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTI (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTI <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTM (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTM <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTM (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTM <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTM (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTM <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTN (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTN <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTN (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTN <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTN (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTN <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTP (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTP <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTP (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTP <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTP (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|0|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTP <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTX (vector)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTX <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTX (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|1|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTX <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTX (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|1|1|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTX <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRINTZ (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FRINTZ <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRINTZ (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|1|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FRINTZ <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FRINTZ (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|1|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FRINTZ <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FRSQRTE","Bits":"0|1|1|1|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRSQRTE <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"FRSQRTE","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRSQRTE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FRSQRTS","Bits":"0|1|0|1|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"FRSQRTS <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"FRSQRTS","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|1|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FSQRT (vector)","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSQRT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"FSQRT (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSQRT <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"FSQRT (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|1|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FSQRT <Dd>, <Dn>","Code":"","Alias":""},
+{"Name":"FSUB (vector)","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FSUB <Sd>, <Sn>, <Sm>","Code":"","Alias":""},
+{"Name":"FSUB (scalar)","Bits":"0|0|0|1|1|1|1|0|01:2|1|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FSUB <Dd>, <Dn>, <Dm>","Code":"","Alias":""},
+{"Name":"INS (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is used by the alias MOV (element)."},
+{"Name":"INS (general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"INS <Vd>.<Ts>[<index>], <R><n>","Code":"","Alias":"This instruction is used by the alias MOV (from general)."},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0111:4|size:2|Rn:5|Rt:5","Arch":"No offset One register variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|1010:4|size:2|Rn:5|Rt:5","Arch":"No offset Two registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0110:4|size:2|Rn:5|Rt:5","Arch":"No offset Three registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0010:4|size:2|Rn:5|Rt:5","Arch":"No offset Four registers variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, immediate offset variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, register offset variant","Syntax":"LD1 { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, immediate offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, register offset variant","Syntax":"LD1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>], #1","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"LD1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD1R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD1R { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"LD2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD2R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|1|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD2R { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24","Code":"","Alias":""},
+{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|11111:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD3R","Bits":"0|Q|0|0|1|1|0|1|1|1|0|Rm:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|1|0|0|0|0|0|0|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|11111:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"LD4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"LD4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"LD4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32","Code":"","Alias":""},
+{"Name":"LD4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"LD4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|0|1|1|0|0|0|0|0|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|11111:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"LD4R","Bits":"0|Q|0|0|1|1|0|1|1|1|1|Rm:5|1|1|1|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD4R { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"LDNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDNP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|1|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|0|1|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 128-bit variant","Syntax":"LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"LDR <St>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|1|01:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|11:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"LDR (literal, SIMD&FP)","Bits":"00:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"32-bit variant","Syntax":"LDR <St>, <label>","Code":"","Alias":""},
+{"Name":"LDR (literal, SIMD&FP)","Bits":"01:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Dt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (literal, SIMD&FP)","Bits":"10:2|0|1|1|1|0|0|imm19:19|Rt:5","Arch":"128-bit variant","Syntax":"LDR <Qt>, <label>","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"LDR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"LDUR <Bt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"LDUR <Ht>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"LDUR <St>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|01:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"LDUR <Dt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"LDUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|11:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"LDUR <Qt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"MLA (by element)","Bits":"0|Q|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"MLA (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"MLS (by element)","Bits":"0|Q|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"MLS (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"MOV (scalar)","Bits":"0|1|0|1|1|1|1|0|0|0|0|imm5:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar variant","Syntax":"MOV <V><d>, <Vn>.<T>[<index>]","Code":"","Alias":"This instruction is an alias of the DUP (element) instruction."},
+{"Name":"MOV (element)","Bits":"0|1|1|0|1|1|1|0|0|0|0|imm5:5|0|imm4:4|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]","Code":"","Alias":"This instruction is an alias of the INS (element) instruction."},
+{"Name":"MOV (from general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"MOV <Vd>.<Ts>[<index>], <R><n>","Code":"","Alias":"This instruction is an alias of the INS (general) instruction."},
+{"Name":"MOV (vector)","Bits":"0|Q|0|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MOV <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is an alias of the ORR (vector, register) instruction."},
+{"Name":"MOV (to general)","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MOV <Wd>, <Vn>.S[<index>]","Code":"","Alias":"This instruction is an alias of the UMOV instruction."},
+{"Name":"MOV (to general)","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MOV <Xd>, <Vn>.D[<index>]","Code":"","Alias":"This instruction is an alias of the UMOV instruction."},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"8-bit variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #0}","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit shifted immediate variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifted immediate variant","Syntax":"MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifting ones variant","Syntax":"MOVI <Vd>.<T>, #<imm8>, MSL #<amount>","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|0|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"64-bit scalar variant","Syntax":"MOVI <Dd>, #<imm>","Code":"","Alias":""},
+{"Name":"MOVI","Bits":"0|1|1|0|1|1|1|1|0|0|0|0|0|a|b|c|1110:4|0|1|d|e|f|g|h|Rd:5","Arch":"64-bit vector variant","Syntax":"MOVI <Vd>.2D, #<imm>","Code":"","Alias":""},
+{"Name":"MUL (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|0|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"MUL (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"MVN","Bits":"0|Q|1|0|1|1|1|0|0|0|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"MVN <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is an alias of the NOT instruction."},
+{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit shifted immediate variant","Syntax":"MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifted immediate variant","Syntax":"MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"MVNI","Bits":"0|Q|1|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit shifting ones variant","Syntax":"MVNI <Vd>.<T>, #<imm8>, MSL #<amount>","Code":"","Alias":""},
+{"Name":"NEG (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"NEG <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"NEG (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|1|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"NEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"NOT","Bits":"0|Q|1|0|1|1|1|0|0|0|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"NOT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":"This instruction is used by the alias MVN."},
+{"Name":"ORN (vector)","Bits":"0|Q|0|0|1|1|1|0|1|1|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ORR (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"16-bit variant","Syntax":"ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"ORR (vector, immediate)","Bits":"0|Q|0|0|1|1|1|1|0|0|0|0|0|a|b|c|cmode:4|0|1|d|e|f|g|h|Rd:5","Arch":"32-bit variant","Syntax":"ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}","Code":"","Alias":""},
+{"Name":"ORR (vector, register)","Bits":"0|Q|0|0|1|1|1|0|1|0|1|Rm:5|0|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":"This instruction is used by the alias MOV (vector)."},
+{"Name":"PMUL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"PMULL, PMULL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"PMULL, PMULL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"RADDHN, RADDHN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RADDHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"RADDHN, RADDHN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RADDHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"RBIT (vector)","Bits":"0|Q|1|0|1|1|1|0|0|1|1|0|0|0|0|0|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RBIT <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"REV16 (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV16 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"REV32 (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV32 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"REV64","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"REV64 <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"RSHRN, RSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"RSHRN, RSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"RSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"RSUBHN, RSUBHN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RSUBHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"RSUBHN, RSUBHN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"RSUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"SABA","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SABAL, SABAL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SABAL, SABAL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SABD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SABDL, SABDL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SABDL, SABDL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADALP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SADALP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDL, SADDL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDL, SADDL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDLP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SADDLP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDLV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SADDLV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SADDW, SADDW2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SADDW, SADDW2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SCVTF (vector, fixed-point)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SCVTF <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (vector, fixed-point)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SCVTF (vector, integer)","Bits":"0|1|0|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SCVTF <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SCVTF (vector, integer)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SCVTF <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|0|0|0|1|0|scale:6|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Wn>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Wn>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"SCVTF <Sd>, <Xn>","Code":"","Alias":""},
+{"Name":"SCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|1|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"SCVTF <Dd>, <Xn>","Code":"","Alias":""},
+{"Name":"SHA1C","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1C <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1H","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|0|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1H <Sd>, <Sn>","Code":"","Alias":""},
+{"Name":"SHA1M","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1M <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1P","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1P <Qd>, <Sn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1SU0","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA1SU1","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA1SU1 <Vd>.4S, <Vn>.4S","Code":"","Alias":""},
+{"Name":"SHA256H2","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256H2 <Qd>, <Qn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA256H","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256H <Qd>, <Qn>, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHA256SU0","Bits":"0|1|0|1|1|1|1|0|0|0|1|0|1|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256SU0 <Vd>.4S, <Vn>.4S","Code":"","Alias":""},
+{"Name":"SHA256SU1","Bits":"0|1|0|1|1|1|1|0|0|0|0|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S","Code":"","Alias":""},
+{"Name":"SHADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SHL","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SHL","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SHLL, SHLL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"","Alias":""},
+{"Name":"SHLL, SHLL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"","Alias":""},
+{"Name":"SHRN, SHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SHRN, SHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SHSUB","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SLI","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SLI <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SLI","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SLI <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SMAX","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMAXP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMAXV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SMIN","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMINP","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SMINV","Bits":"0|Q|0|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"SMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMLAL, SMLAL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMLSL, SMLSL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMOV","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"SMOV <Wd>, <Vn>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMOV","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"SMOV <Xd>, <Vn>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SMULL, SMULL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQABS","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQABS <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SQABS","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQABS <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SQADD","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLAL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMLAL, SQDMLAL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLSL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMLSL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMLSL, SQDMLSL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMULH (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|1|0|0|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULH (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|1|0|0|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULH (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULH <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQDMULH (vector)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|0|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (by element)","Bits":"0|1|0|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQDMULL <Va><d>, <Vb><n>, <Vb><m>","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQDMULL, SQDMULL2 (vector)","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|1|1|0|1|0|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQDMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SQNEG","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQNEG <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SQNEG","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQNEG <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SQRDMULH (by element)","Bits":"0|1|0|1|1|1|1|1|size:2|L|M|Rm:4|1|1|0|1|H|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQRDMULH (by element)","Bits":"0|Q|0|0|1|1|1|1|size:2|L|M|Rm:4|1|1|0|1|H|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"SQRDMULH (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRDMULH <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQRDMULH (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQRSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQRSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQRSHRN, SQRSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQRSHRUN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRUN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQRSHRUN, SQRSHRUN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQRSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHL (immediate)","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHL (immediate)","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHL (register)","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQSHL (register)","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQSHLU","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHLU <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHLU","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHLU <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRN, SQSHRN2","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHRN, SQSHRN2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRN, SQSHRN2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSHRUN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRUN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSHRUN, SQSHRUN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSHRUN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SQSUB","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQSUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SQSUB","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SQXTN, SQXTN2","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQXTN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"SQXTN, SQXTN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SQXTN, SQXTN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SQXTUN, SQXTUN2","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SQXTUN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"SQXTUN, SQXTUN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTUN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SQXTUN, SQXTUN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SQXTUN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"SRHADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SRI","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRI <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SRI","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRI <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SRSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SRSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SRSHR","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SRSHR","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SRSRA","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SRSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SRSRA","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SRSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SSHL","Bits":"0|1|0|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SSHL","Bits":"0|Q|0|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SSHLL, SSHLL2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SSHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias SXTL, SXTL2."},
+{"Name":"SSHLL, SSHLL2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SSHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias SXTL, SXTL2."},
+{"Name":"SSHR","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SSHR","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SSRA","Bits":"0|1|0|1|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"SSRA","Bits":"0|Q|0|0|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"SSUBL, SSUBL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SSUBL, SSUBL2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SSUBW, SSUBW2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"SSUBW, SSUBW2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SSUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0111:4|size:2|Rn:5|Rt:5","Arch":"No offset One register variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1010:4|size:2|Rn:5|Rt:5","Arch":"No offset Two registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0110:4|size:2|Rn:5|Rt:5","Arch":"No offset Three registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0010:4|size:2|Rn:5|Rt:5","Arch":"No offset Four registers variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, immediate offset variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0111:4|size:2|Rn:5|Rt:5","Arch":"Post-index One register, register offset variant","Syntax":"ST1 { <Vt>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|1010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Two registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0110:4|size:2|Rn:5|Rt:5","Arch":"Post-index Three registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, immediate offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST1 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0010:4|size:2|Rn:5|Rt:5","Arch":"Post-index Four registers, register offset variant","Syntax":"ST1 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>], #1","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST1 { <Vt>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST1 { <Vt>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST1 { <Vt>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"ST1 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST1 { <Vt>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST2 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|1|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST2 { <Vt>.<T>, <Vt2>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|000:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|010:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|100:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|100:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], #2","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|000:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST2 { <Vt>.B, <Vt2>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|010:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST2 { <Vt>.H, <Vt2>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|100:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST2 { <Vt>.S, <Vt2>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"ST2 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|100:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST2 { <Vt>.D, <Vt2>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|0|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], #3","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], #6","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST3 { <Vt>.H, <Vt2>.H, <Vt3>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], #12","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST3 { <Vt>.S, <Vt2>.S, <Vt3>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], #24","Code":"","Alias":""},
+{"Name":"ST3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|0|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST3 { <Vt>.D, <Vt2>.D, <Vt3>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|0|0|0|0|0|0|0|0|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"No offset No offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|11111:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Immediate offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>","Code":"","Alias":""},
+{"Name":"ST4 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|0|0|Rm:5|0|0|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|011:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 16-bit variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|101:3|S|00:2|Rn:5|Rt:5","Arch":"No offset 32-bit variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|0|1|0|0|0|0|0|101:3|0|01:2|Rn:5|Rt:5","Arch":"No offset 64-bit variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>]","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, immediate offset variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], #4","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|001:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 8-bit, register offset variant","Syntax":"ST4 { <Vt>.B, <Vt2>.B, <Vt3>.B, <Vt4>.B }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, immediate offset variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], #8","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|011:3|S|size:2|Rn:5|Rt:5","Arch":"Post-index 16-bit, register offset variant","Syntax":"ST4 { <Vt>.H, <Vt2>.H, <Vt3>.H, <Vt4>.H }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, immediate offset variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], #16","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|101:3|S|00:2|Rn:5|Rt:5","Arch":"Post-index 32-bit, register offset variant","Syntax":"ST4 { <Vt>.S, <Vt2>.S, <Vt3>.S, <Vt4>.S }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|11111:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, immediate offset variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], #32","Code":"","Alias":""},
+{"Name":"ST4 (single structure)","Bits":"0|Q|0|0|1|1|0|1|1|0|1|Rm:5|101:3|0|01:2|Rn:5|Rt:5","Arch":"Post-index 64-bit, register offset variant","Syntax":"ST4 { <Vt>.D, <Vt2>.D, <Vt3>.D, <Vt4>.D }[<index>], [<Xn|SP>], <Xm>","Code":"","Alias":""},
+{"Name":"STNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STNP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|0|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|1|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 32-bit variant","Syntax":"STP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 64-bit variant","Syntax":"STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STP (SIMD&FP)","Bits":"10:2|1|0|1|1|0|1|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"Signed offset 128-bit variant","Syntax":"STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 32-bit variant","Syntax":"STR <St>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 32-bit variant","Syntax":"STR <St>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"01:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"10:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 32-bit variant","Syntax":"STR <St>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"11:2|1|1|1|1|0|1|00:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (immediate, SIMD&FP)","Bits":"00:2|1|1|1|1|0|1|10:2|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset 128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STR <Bt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"STR <Ht>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STR <St>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STR <Dt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STR (register, SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STR <Qt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"8-bit variant","Syntax":"STUR <Bt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"01:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"16-bit variant","Syntax":"STUR <Ht>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"10:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STUR <St>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"11:2|1|1|1|1|0|0|00:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STUR <Dt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"STUR (SIMD&FP)","Bits":"00:2|1|1|1|1|0|0|10:2|0|imm9:9|0|0|Rn:5|Rt:5","Arch":"128-bit variant","Syntax":"STUR <Qt>, [<Xn|SP>{, #<simm>}]","Code":"","Alias":""},
+{"Name":"SUB (vector)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"SUB (vector)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"SUBHN, SUBHN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SUBHN <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"SUBHN, SUBHN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"SUBHN2 <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"SUQADD","Bits":"0|1|0|1|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"SUQADD <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"SUQADD","Bits":"0|Q|0|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"SUQADD <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"SXTL, SXTL2","Bits":"0|0|0|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SXTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the SSHLL, SSHLL2 instruction."},
+{"Name":"SXTL, SXTL2","Bits":"0|1|0|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"SXTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the SSHLL, SSHLL2 instruction."},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|01:2|0|0|0|Rn:5|Rd:5","Arch":"Two register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|10:2|0|0|0|Rn:5|Rd:5","Arch":"Three register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|11:2|0|0|0|Rn:5|Rd:5","Arch":"Four register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBL","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|00:2|0|0|0|Rn:5|Rd:5","Arch":"Single register table variant","Syntax":"TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|01:2|1|0|0|Rn:5|Rd:5","Arch":"Two register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|10:2|1|0|0|Rn:5|Rd:5","Arch":"Three register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|11:2|1|0|0|Rn:5|Rd:5","Arch":"Four register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TBX","Bits":"0|Q|0|0|1|1|1|0|0|0|0|Rm:5|0|00:2|1|0|0|Rn:5|Rd:5","Arch":"Single register table variant","Syntax":"TBX <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>","Code":"","Alias":""},
+{"Name":"TRN1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"TRN2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UABA","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UABA <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UABAL, UABAL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UABAL, UABAL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UABD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UABDL, UABDL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UABDL, UABDL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UABDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADALP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|1|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UADALP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDL, UADDL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDL, UADDL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDLP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UADDLP <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDLV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UADDLV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UADDW, UADDW2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UADDW, UADDW2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UADDW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UCVTF (vector, fixed-point)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UCVTF <V><d>, <V><n>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (vector, fixed-point)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|1|1|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UCVTF (vector, integer)","Bits":"0|1|1|1|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UCVTF <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"UCVTF (vector, integer)","Bits":"0|Q|1|0|1|1|1|0|0|sz|1|0|0|0|0|1|1|1|0|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UCVTF <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|00:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"0|0|0|1|1|1|1|0|01:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Wn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|00:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|0|0|0|1|1|scale:6|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Xn>, #<fbits>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Wn>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Wn>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|00:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to single-precision variant","Syntax":"UCVTF <Sd>, <Xn>","Code":"","Alias":""},
+{"Name":"UCVTF (scalar, integer)","Bits":"1|0|0|1|1|1|1|0|01:2|1|0|0|0|1|1|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit to double-precision variant","Syntax":"UCVTF <Dd>, <Xn>","Code":"","Alias":""},
+{"Name":"UHADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UHSUB","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMAX","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMAXP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMAXV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|0|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMAXV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UMIN","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMINP","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|1|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"UMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UMINV","Bits":"0|Q|1|0|1|1|1|0|size:2|1|1|0|0|0|1|1|0|1|0|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UMINV <V><d>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|0|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMLAL, UMLAL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|0|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|0|1|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLSL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMLSL, UMLSL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMLSL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMOV","Bits":"0|0|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"UMOV <Wd>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (to general)."},
+{"Name":"UMOV","Bits":"0|1|0|0|1|1|1|0|0|0|0|imm5:5|0|0|1|1|1|1|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"UMOV <Xd>, <Vn>.<Ts>[<index>]","Code":"","Alias":"This instruction is used by the alias MOV (to general)."},
+{"Name":"UMULL, UMULL2 (by element)","Bits":"0|0|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMULL, UMULL2 (by element)","Bits":"0|1|1|0|1|1|1|1|size:2|L|M|Rm:4|1|0|1|0|H|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]","Code":"","Alias":""},
+{"Name":"UMULL, UMULL2 (vector)","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UMULL, UMULL2 (vector)","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|1|1|0|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"UMULL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UQADD","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQADD <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQRSHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQRSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQRSHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQRSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQRSHRN, UQRSHRN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQRSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSHL (immediate)","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHL <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"UQSHL (immediate)","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|1|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHL <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSHL (register)","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQSHL (register)","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQSHRN, UQSHRN2","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSHRN <Vb><d>, <Va><n>, #<shift>","Code":"","Alias":""},
+{"Name":"UQSHRN, UQSHRN2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSHRN, UQSHRN2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSHRN2 <Vd>.<Tb>, <Vn>.<Ta>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"UQSUB","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQSUB <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"UQSUB","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|1|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UQXTN, UQXTN2","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"UQXTN <Vb><d>, <Va><n>","Code":"","Alias":""},
+{"Name":"UQXTN, UQXTN2","Bits":"0|0|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQXTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"UQXTN, UQXTN2","Bits":"0|1|1|0|1|1|1|0|size:2|1|0|0|0|0|1|0|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"UQXTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"URECPE","Bits":"0|Q|0|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"URECPE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"URHADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Three registers of the same type variant","Syntax":"URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"URSHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"URSHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"URSHR","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"URSHR","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"URSQRTE","Bits":"0|Q|1|0|1|1|1|0|1|sz|1|0|0|0|0|1|1|1|0|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"URSQRTE <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"URSRA","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"URSRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"URSRA","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|1|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"URSRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"USHL","Bits":"0|1|1|1|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USHL <V><d>, <V><n>, <V><m>","Code":"","Alias":""},
+{"Name":"USHL","Bits":"0|Q|1|0|1|1|1|0|size:2|1|Rm:5|0|1|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"USHLL, USHLL2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"USHLL <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias UXTL, UXTL2."},
+{"Name":"USHLL, USHLL2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|immb:3|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"USHLL2 <Vd>.<Ta>, <Vn>.<Tb>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":"This instruction is used by the alias UXTL, UXTL2."},
+{"Name":"USHR","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USHR <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"USHR","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|0|0|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USHR <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"USQADD","Bits":"0|1|1|1|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USQADD <V><d>, <V><n>","Code":"","Alias":""},
+{"Name":"USQADD","Bits":"0|Q|1|0|1|1|1|0|size:2|1|0|0|0|0|0|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USQADD <Vd>.<T>, <Vn>.<T>","Code":"","Alias":""},
+{"Name":"USRA","Bits":"0|1|1|1|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Scalar Scalar variant","Syntax":"USRA <V><d>, <V><n>, #<shift>","Code":"","Alias":""},
+{"Name":"USRA","Bits":"0|Q|1|0|1|1|1|1|0|immh:4|immb:3|0|0|0|1|0|1|Rn:5|Rd:5","Arch":"Vector Vector variant","Syntax":"USRA <Vd>.<T>, <Vn>.<T>, #<shift>","Code":"if immh == '0000' then SEE \"Advanced SIMD modified immediate\";","Alias":""},
+{"Name":"USUBL, USUBL2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"USUBL, USUBL2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"USUBW, USUBW2","Bits":"0|0|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBW <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"USUBW, USUBW2","Bits":"0|1|1|0|1|1|1|0|size:2|1|Rm:5|0|0|1|1|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"USUBW2 <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>","Code":"","Alias":""},
+{"Name":"UXTL, UXTL2","Bits":"0|0|1|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UXTL <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the USHLL, USHLL2 instruction."},
+{"Name":"UXTL, UXTL2","Bits":"0|1|1|0|1|1|1|1|0|immh:4|0|0|0|1|0|1|0|0|1|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"UXTL2 <Vd>.<Ta>, <Vn>.<Tb>","Code":"","Alias":"This instruction is an alias of the USHLL, USHLL2 instruction."},
+{"Name":"UZP1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"UZP2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|0|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"XTN, XTN2","Bits":"0|0|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"XTN <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"XTN, XTN2","Bits":"0|1|0|0|1|1|1|0|size:2|1|0|0|0|0|1|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Vector variant","Syntax":"XTN2 <Vd>.<Tb>, <Vn>.<Ta>","Code":"","Alias":""},
+{"Name":"ZIP1","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|0|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
+{"Name":"ZIP2","Bits":"0|Q|0|0|1|1|1|0|size:2|0|Rm:5|0|1|1|1|1|0|Rn:5|Rd:5","Arch":"Advanced SIMD variant","Syntax":"ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""}
+]
diff --git a/arm64/arm64asm/objdump_test.go b/arm64/arm64asm/objdump_test.go
new file mode 100644
index 0000000..c9df701
--- /dev/null
+++ b/arm64/arm64asm/objdump_test.go
@@ -0,0 +1,124 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+import (
+ "strings"
+ "testing"
+)
+
+func TestObjdumpARM64Testdata(t *testing.T) { testObjdumpARM64(t, testdataCases(t)) }
+func TestObjdumpARM64Manual(t *testing.T) { testObjdumpARM64(t, hexCases(t, objdumpManualTests)) }
+func TestObjdumpARM64Cond(t *testing.T) { testObjdumpARM64(t, condCases(t)) }
+func TestObjdumpARM64(t *testing.T) { testObjdumpARM64(t, JSONCases(t)) }
+
+// objdumpManualTests holds test cases that will be run by TestObjdumpARMManual.
+// If you are debugging a few cases that turned up in a longer run, it can be useful
+// to list them here and then use -run=Manual, particularly with tracing enabled.
+// Note that these are byte sequences, so they must be reversed from the usual
+// word presentation.
+var objdumpManualTests = `
+bf2003d5
+9f2003d5
+7f2003d5
+5f2003d5
+3f2003d5
+1f2003d5
+df4d03d5
+ff4d03d5
+28d91b14
+da6cb530
+15e5e514
+ff4603d5
+df4803d5
+bf4100d5
+9f3f03d5
+9f3e03d5
+9f3d03d5
+9f3b03d5
+9f3a03d5
+9f3903d5
+9f3703d5
+9f3603d5
+9f3503d5
+9f3303d5
+9f3203d5
+9f3103d5
+ff4603d5
+df4803d5
+bf4100d5
+a3681b53
+47dc78d3
+0500a012
+0500e092
+0500a052
+0500a0d2
+cd5a206e
+cd5a202e
+743d050e
+743d0a0e
+743d0c0e
+743d084e
+`
+
+// allowedMismatchObjdump reports whether the mismatch between text and dec
+// should be allowed by the test.
+func allowedMismatchObjdump(text string, inst *Inst, dec ExtInst) bool {
+ // Skip unsupported instructions
+ if hasPrefix(dec.text, todo...) {
+ return true
+ }
+ // GNU objdump has incorrect alias conditions for following instructions
+ if inst.Enc&0x000003ff == 0x000003ff && hasPrefix(dec.text, "negs") && hasPrefix(text, "cmp") {
+ return true
+ }
+ // GNU objdump "NV" is equal to our "AL"
+ if strings.HasSuffix(dec.text, " nv") && strings.HasSuffix(text, " al") {
+ return true
+ }
+ if strings.HasPrefix(dec.text, "b.nv") && strings.HasPrefix(text, "b.al") {
+ return true
+ }
+ // GNU objdump recognizes invalid binaries as following instructions
+ if hasPrefix(dec.text, "hint", "mrs", "msr", "bfc", "orr", "mov") {
+ return true
+ }
+ if strings.HasPrefix(text, "hint") {
+ return true
+ }
+ // GNU objdump recognizes reserved valuse as valid ones
+ if strings.Contains(text, "unknown instruction") && hasPrefix(dec.text, "fmla", "fmul", "fmulx", "fcvtzs", "fcvtzu", "fmls", "fmov", "scvtf", "ucvtf") {
+ return true
+ }
+ // GNU objdump misses spaces between operands for some instructions (e.g., "ld1 {v10.2s, v11.2s}, [x23],#16")
+ if strings.Replace(text, " ", "", -1) == strings.Replace(dec.text, " ", "", -1) {
+ return true
+ }
+ return false
+}
+
+// TODO: system instruction.
+var todo = strings.Fields(`
+ sys
+ dc
+ at
+ tlbi
+ ic
+ hvc
+ smc
+`)
+
+// Following instructions can't be covered because they are just aliases to another instructions which are always preferred
+var Ncover = strings.Fields(`
+ sbfm
+ asrv
+ bfm
+ ubfm
+ lslv
+ lsrv
+ rorv
+ ins
+ dup
+`)
diff --git a/arm64/arm64asm/objdumpext_test.go b/arm64/arm64asm/objdumpext_test.go
new file mode 100644
index 0000000..b430f98
--- /dev/null
+++ b/arm64/arm64asm/objdumpext_test.go
@@ -0,0 +1,299 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Copied and simplified from ../../arm/armasm/objdumpext_test.go.
+
+package arm64asm
+
+import (
+ "bytes"
+ "debug/elf"
+ "encoding/binary"
+ "fmt"
+ "io"
+ "log"
+ "os"
+ "os/exec"
+ "strconv"
+ "strings"
+ "testing"
+)
+
+const objdumpPath = "/usr/bin/objdump"
+
+func testObjdumpARM64(t *testing.T, generate func(func([]byte))) {
+ testObjdumpArch(t, generate, ModeARM64)
+}
+
+func testObjdumpArch(t *testing.T, generate func(func([]byte)), arch Mode) {
+ if _, err := os.Stat(objdumpPath); err != nil {
+ t.Skip(err)
+ }
+ // Check objdump can disassemble elf64-aarch64.
+ if test := objdumpinfo(); test == false {
+ t.Skip("Skip the test if installed objdump doesn't support aarch64 elf format")
+ }
+ testExtDis(t, "gnu", arch, objdump, generate, allowedMismatchObjdump)
+ testExtDis(t, "plan9", arch, objdump, generate, allowedMismatchObjdump)
+}
+
+func objdumpinfo() bool {
+ var i = []byte("aarch64")
+ out, err := exec.Command(objdumpPath, "-i").Output()
+ if err != nil {
+ log.Fatal(err)
+ }
+ if bytes.Contains(out, i) {
+ return true
+ }
+ return false
+}
+
+func objdump(ext *ExtDis) error {
+ // File already written with instructions; add ELF header.
+ if ext.Arch == ModeARM64 {
+ if err := writeELF64(ext.File, ext.Size); err != nil {
+ return err
+ }
+ } else {
+ panic("unknown arch")
+ }
+
+ b, err := ext.Run(objdumpPath, "-d", "-z", ext.File.Name())
+ if err != nil {
+ return err
+ }
+
+ var (
+ nmatch int
+ reading bool
+ next uint64 = start
+ addr uint64
+ encbuf [4]byte
+ enc []byte
+ text string
+ )
+ flush := func() {
+ if addr == next {
+ // PC-relative addresses are translated to absolute addresses based on PC by GNU objdump
+ // Following logical rewrites the absolute addresses back to PC-relative ones for comparing
+ // with our disassembler output which are PC-relative
+
+ if m := pcrelprfmim.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ if m := pcrelprfm.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ if m := pcrelim.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ if m := pcrelimzr.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ if m := pcrelr.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ if strings.Contains(m[1], "adrp") {
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr&0xfffff000)))
+ } else {
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ }
+ if m := pcrelrzr.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ if strings.Contains(m[1], "adrp") {
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr&0xfffff000)))
+ } else {
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ }
+ if m := pcrel.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ text = fmt.Sprintf("%s .%+#x", m[1], uint64(targ-uint64(addr)))
+ }
+ if strings.HasPrefix(text, "mov") && strings.Contains(text, "//") {
+ s := strings.Split(text, " //")
+ text = s[0]
+ }
+ text = strings.Replace(text, "#0.0", "#0", -1)
+ if text == "undefined" && len(enc) == 4 {
+ text = "error: unknown instruction"
+ enc = nil
+ }
+ if len(enc) == 4 {
+ // prints as word but we want to record bytes
+ enc[0], enc[3] = enc[3], enc[0]
+ enc[1], enc[2] = enc[2], enc[1]
+ }
+ ext.Dec <- ExtInst{addr, encbuf, len(enc), text}
+ encbuf = [4]byte{}
+ enc = nil
+ next += 4
+ }
+ }
+ var textangle = []byte("<.text>:")
+ for {
+ line, err := b.ReadSlice('\n')
+ if err != nil {
+ if err == io.EOF {
+ break
+ }
+ return fmt.Errorf("reading objdump output: %v", err)
+ }
+ if bytes.Contains(line, textangle) {
+ reading = true
+ continue
+ }
+ if !reading {
+ continue
+ }
+ if debug {
+ os.Stdout.Write(line)
+ }
+ if enc1 := parseContinuation(line, encbuf[:len(enc)]); enc1 != nil {
+ enc = enc1
+ continue
+ }
+ flush()
+ nmatch++
+ addr, enc, text = parseLine(line, encbuf[:0])
+ if addr > next {
+ return fmt.Errorf("address out of sync expected <= %#x at %q in:\n%s", next, line, line)
+ }
+ }
+ flush()
+ if next != start+uint64(ext.Size) {
+ return fmt.Errorf("not enough results found [%d %d]", next, start+ext.Size)
+ }
+ if err := ext.Wait(); err != nil {
+ return fmt.Errorf("exec: %v", err)
+ }
+
+ return nil
+}
+
+var (
+ undefined = []byte("undefined")
+ unpredictable = []byte("unpredictable")
+)
+
+func parseLine(line []byte, encstart []byte) (addr uint64, enc []byte, text string) {
+ ok := false
+ oline := line
+ i := index(line, ":\t")
+ if i < 0 {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ x, err := strconv.ParseUint(string(bytes.TrimSpace(line[:i])), 16, 32)
+ if err != nil {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ addr = uint64(x)
+ line = line[i+2:]
+ i = bytes.IndexByte(line, '\t')
+ if i < 0 {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ enc, ok = parseHex(line[:i], encstart)
+ if !ok {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ line = bytes.TrimSpace(line[i:])
+ if bytes.Contains(line, undefined) {
+ text = "undefined"
+ return
+ }
+ if false && bytes.Contains(line, unpredictable) {
+ text = "unpredictable"
+ return
+ }
+ if i := bytes.IndexByte(line, ';'); i >= 0 {
+ line = bytes.TrimSpace(line[:i])
+ }
+ text = string(fixSpace(line))
+ return
+}
+
+func parseContinuation(line []byte, enc []byte) []byte {
+ i := index(line, ":\t")
+ if i < 0 {
+ return nil
+ }
+ line = line[i+1:]
+ enc, _ = parseHex(line, enc)
+ return enc
+}
+
+// writeELF64 writes an ELF64 header to the file, describing a text
+// segment that starts at start (0x8000) and extends for size bytes.
+func writeELF64(f *os.File, size int) error {
+ f.Seek(0, 0)
+ var hdr elf.Header64
+ var prog elf.Prog64
+ var sect elf.Section64
+ var buf bytes.Buffer
+ binary.Write(&buf, binary.LittleEndian, &hdr)
+ off1 := buf.Len()
+ binary.Write(&buf, binary.LittleEndian, &prog)
+ off2 := buf.Len()
+ binary.Write(&buf, binary.LittleEndian, §)
+ off3 := buf.Len()
+ buf.Reset()
+ data := byte(elf.ELFDATA2LSB)
+ hdr = elf.Header64{
+ Ident: [16]byte{0x7F, 'E', 'L', 'F', 2, data, 1},
+ Type: 2,
+ Machine: uint16(elf.EM_AARCH64),
+ Version: 1,
+ Entry: start,
+ Phoff: uint64(off1),
+ Shoff: uint64(off2),
+ Flags: 0x05000002,
+ Ehsize: uint16(off1),
+ Phentsize: uint16(off2 - off1),
+ Phnum: 1,
+ Shentsize: uint16(off3 - off2),
+ Shnum: 3,
+ Shstrndx: 2,
+ }
+ binary.Write(&buf, binary.LittleEndian, &hdr)
+ prog = elf.Prog64{
+ Type: 1,
+ Off: start,
+ Vaddr: start,
+ Paddr: start,
+ Filesz: uint64(size),
+ Memsz: uint64(size),
+ Flags: 5,
+ Align: start,
+ }
+ binary.Write(&buf, binary.LittleEndian, &prog)
+ binary.Write(&buf, binary.LittleEndian, §) // NULL section
+ sect = elf.Section64{
+ Name: 1,
+ Type: uint32(elf.SHT_PROGBITS),
+ Addr: start,
+ Off: start,
+ Size: uint64(size),
+ Flags: uint64(elf.SHF_ALLOC | elf.SHF_EXECINSTR),
+ Addralign: 4,
+ }
+ binary.Write(&buf, binary.LittleEndian, §) // .text
+ sect = elf.Section64{
+ Name: uint32(len("\x00.text\x00")),
+ Type: uint32(elf.SHT_STRTAB),
+ Addr: 0,
+ Off: uint64(off2 + (off3-off2)*3),
+ Size: uint64(len("\x00.text\x00.shstrtab\x00")),
+ Addralign: 1,
+ }
+ binary.Write(&buf, binary.LittleEndian, §)
+ buf.WriteString("\x00.text\x00.shstrtab\x00")
+ f.Write(buf.Bytes())
+ return nil
+}
diff --git a/arm64/arm64asm/plan9x.go b/arm64/arm64asm/plan9x.go
new file mode 100644
index 0000000..e597276
--- /dev/null
+++ b/arm64/arm64asm/plan9x.go
@@ -0,0 +1,611 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+import (
+ "fmt"
+ "io"
+ "sort"
+ "strings"
+)
+
+// GoSyntax returns the Go assembler syntax for the instruction.
+// The syntax was originally defined by Plan 9.
+// The pc is the program counter of the instruction, used for
+// expanding PC-relative addresses into absolute ones.
+// The symname function queries the symbol table for the program
+// being disassembled. Given a target address it returns the name
+// and base address of the symbol containing the target, if any;
+// otherwise it returns "", 0.
+// The reader text should read from the text segment using text addresses
+// as offsets; it is used to display pc-relative loads as constant loads.
+func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string {
+ if symname == nil {
+ symname = func(uint64) (string, uint64) { return "", 0 }
+ }
+
+ var args []string
+ for _, a := range inst.Args {
+ if a == nil {
+ break
+ }
+ args = append(args, plan9Arg(&inst, pc, symname, a))
+ }
+
+ op := inst.Op.String()
+
+ switch inst.Op {
+ case LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW:
+ // Check for PC-relative load.
+ if offset, ok := inst.Args[1].(PCRel); ok {
+ addr := pc + uint64(offset)
+ if _, ok := inst.Args[0].(Reg); !ok {
+ break
+ }
+ if s, base := symname(addr); s != "" && addr == base {
+ args[1] = fmt.Sprintf("$%s(SB)", s)
+ }
+ }
+ }
+
+ // Move addressing mode into opcode suffix.
+ suffix := ""
+ switch inst.Op {
+ case LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH, STUR, STURB, STURH, LD1:
+ switch mem := inst.Args[1].(type) {
+ case MemImmediate:
+ switch mem.Mode {
+ case AddrOffset:
+ // no suffix
+ case AddrPreIndex:
+ suffix = ".W"
+ case AddrPostIndex, AddrPostReg:
+ suffix = ".P"
+ }
+ }
+
+ case STP, LDP:
+ switch mem := inst.Args[2].(type) {
+ case MemImmediate:
+ switch mem.Mode {
+ case AddrOffset:
+ // no suffix
+ case AddrPreIndex:
+ suffix = ".W"
+ case AddrPostIndex:
+ suffix = ".P"
+ }
+ }
+ }
+
+ switch inst.Op {
+ case BL:
+ return "CALL " + args[0]
+
+ case BLR:
+ r := inst.Args[0].(Reg)
+ regno := uint16(r) & 31
+ return fmt.Sprintf("CALL (R%d)", regno)
+
+ case RET:
+ if r, ok := inst.Args[0].(Reg); ok && r == X30 {
+ return "RET"
+ }
+
+ case B:
+ if cond, ok := inst.Args[0].(Cond); ok {
+ return "B" + cond.String() + " " + args[1]
+ }
+ return "JMP" + " " + args[0]
+
+ case BR:
+ r := inst.Args[0].(Reg)
+ regno := uint16(r) & 31
+ return fmt.Sprintf("JMP (R%d)", regno)
+
+ case MOV:
+ rno := -1
+ switch a := inst.Args[0].(type) {
+ case Reg:
+ rno = int(a)
+ case RegSP:
+ rno = int(a)
+ case RegisterWithArrangementAndIndex:
+ op = "VMOV"
+ }
+ if rno >= 0 && rno <= int(WZR) {
+ op = "MOVW"
+ } else if rno >= int(X0) && rno <= int(XZR) {
+ op = "MOVD"
+ }
+ if _, ok := inst.Args[1].(RegisterWithArrangementAndIndex); ok {
+ op = "VMOV"
+ }
+
+ case LDR:
+ var rno uint16
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno = uint16(r)
+ } else {
+ rno = uint16(inst.Args[0].(RegSP))
+ }
+ if rno <= uint16(WZR) {
+ op = "MOVWU" + suffix
+ } else {
+ op = "MOVD" + suffix
+ }
+
+ case LDRB:
+ op = "MOVBU" + suffix
+
+ case LDRH:
+ op = "MOVHU" + suffix
+
+ case LDRSW:
+ op = "MOVW" + suffix
+
+ case LDRSB:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op = "MOVBW" + suffix
+ } else {
+ op = "MOVB" + suffix
+ }
+ }
+ case LDRSH:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op = "MOVHW" + suffix
+ } else {
+ op = "MOVH" + suffix
+ }
+ }
+ case STR, STUR:
+ var rno uint16
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno = uint16(r)
+ } else {
+ rno = uint16(inst.Args[0].(RegSP))
+ }
+ if rno <= uint16(WZR) {
+ op = "MOVW" + suffix
+ } else {
+ op = "MOVD" + suffix
+ }
+ args[0], args[1] = args[1], args[0]
+
+ case STRB, STURB:
+ op = "MOVB" + suffix
+ args[0], args[1] = args[1], args[0]
+
+ case STRH, STURH:
+ op = "MOVH" + suffix
+ args[0], args[1] = args[1], args[0]
+
+ case TBNZ, TBZ:
+ args[0], args[1], args[2] = args[2], args[0], args[1]
+
+ case MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op += "W"
+ }
+ }
+ args[2], args[3] = args[3], args[2]
+ case STLR:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op += "W"
+ }
+ }
+ args[0], args[1] = args[1], args[0]
+
+ case STLRB, STLRH:
+ args[0], args[1] = args[1], args[0]
+
+ case STLXR, STXR:
+ if r, ok := inst.Args[1].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op += "W"
+ }
+ }
+ args[1], args[2] = args[2], args[1]
+
+ case STLXRB, STLXRH, STXRB, STXRH:
+ args[1], args[2] = args[2], args[1]
+
+ case BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op += "W"
+ }
+ }
+ args[1], args[2], args[3] = args[3], args[1], args[2]
+
+ case STP, LDP:
+ args[0] = fmt.Sprintf("(%s, %s)", args[0], args[1])
+ args[1] = args[2]
+ if op == "STP" {
+ op = op + suffix
+ return op + " " + args[0] + ", " + args[1]
+ } else if op == "LDP" {
+ op = op + suffix
+ return op + " " + args[1] + ", " + args[0]
+ }
+
+ case FCCMP, FCCMPE:
+ args[0], args[1] = args[1], args[0]
+ fallthrough
+
+ case FCMP, FCMPE:
+ if _, ok := inst.Args[1].(Imm); ok {
+ args[1] = "$(0.0)"
+ }
+ fallthrough
+
+ case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno >= uint16(S0) && rno <= uint16(S31) {
+ op = fmt.Sprintf("%sS", op)
+ } else if rno >= uint16(D0) && rno <= uint16(D31) {
+ op = fmt.Sprintf("%sD", op)
+ }
+ }
+
+ case FCVT:
+ for i := 1; i >= 0; i-- {
+ if r, ok := inst.Args[i].(Reg); ok {
+ rno := uint16(r)
+ if rno >= uint16(H0) && rno <= uint16(H31) {
+ op = fmt.Sprintf("%sH", op)
+ } else if rno >= uint16(S0) && rno <= uint16(S31) {
+ op = fmt.Sprintf("%sS", op)
+ } else if rno >= uint16(D0) && rno <= uint16(D31) {
+ op = fmt.Sprintf("%sD", op)
+ }
+ }
+ }
+
+ case FABS, FNEG, FSQRT, FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX, FRINTI:
+ if r, ok := inst.Args[1].(Reg); ok {
+ rno := uint16(r)
+ if rno >= uint16(S0) && rno <= uint16(S31) {
+ op = fmt.Sprintf("%sS", op)
+ } else if rno >= uint16(D0) && rno <= uint16(D31) {
+ op = fmt.Sprintf("%sD", op)
+ }
+ }
+
+ case FCVTZS, FCVTZU, SCVTF, UCVTF:
+ if _, ok := inst.Args[2].(Imm); !ok {
+ for i := 1; i >= 0; i-- {
+ if r, ok := inst.Args[i].(Reg); ok {
+ rno := uint16(r)
+ if rno >= uint16(S0) && rno <= uint16(S31) {
+ op = fmt.Sprintf("%sS", op)
+ } else if rno >= uint16(D0) && rno <= uint16(D31) {
+ op = fmt.Sprintf("%sD", op)
+ } else if rno <= uint16(WZR) {
+ op += "W"
+ }
+ }
+ }
+ }
+
+ case FMOV:
+ for i := 0; i <= 1; i++ {
+ if r, ok := inst.Args[i].(Reg); ok {
+ rno := uint16(r)
+ if rno >= uint16(S0) && rno <= uint16(S31) {
+ op = fmt.Sprintf("%sS", op)
+ break
+ } else if rno >= uint16(D0) && rno <= uint16(D31) {
+ op = fmt.Sprintf("%sD", op)
+ break
+ }
+ }
+ }
+
+ case SYSL:
+ op1 := int(inst.Args[1].(Imm).Imm)
+ cn := int(inst.Args[2].(Imm_c))
+ cm := int(inst.Args[3].(Imm_c))
+ op2 := int(inst.Args[4].(Imm).Imm)
+ sysregno := int32(op1<<16 | cn<<12 | cm<<8 | op2<<5)
+ args[1] = fmt.Sprintf("$%d", sysregno)
+ return op + " " + args[1] + ", " + args[0]
+
+ case CBNZ, CBZ:
+ if r, ok := inst.Args[0].(Reg); ok {
+ rno := uint16(r)
+ if rno <= uint16(WZR) {
+ op += "W"
+ }
+ }
+ args[0], args[1] = args[1], args[0]
+
+ case ADR, ADRP:
+ addr := int64(inst.Args[1].(PCRel))
+ args[1] = fmt.Sprintf("%d(PC)", addr)
+
+ default:
+ index := sort.SearchStrings(noSuffixOpSet, op)
+ if !(index < len(noSuffixOpSet) && noSuffixOpSet[index] == op) {
+ rno := -1
+ switch a := inst.Args[0].(type) {
+ case Reg:
+ rno = int(a)
+ case RegSP:
+ rno = int(a)
+ case RegisterWithArrangement:
+ op = fmt.Sprintf("V%s", op)
+ }
+
+ if rno >= 0 && rno <= int(WZR) {
+ // Add "w" to opcode suffix.
+ op += "W"
+ }
+ }
+ op = op + suffix
+ }
+
+ // conditional instructions, replace args.
+ if _, ok := inst.Args[3].(Cond); ok {
+ if _, ok := inst.Args[2].(Reg); ok {
+ args[1], args[2] = args[2], args[1]
+ } else {
+ args[0], args[2] = args[2], args[0]
+ }
+ }
+ // Reverse args, placing dest last.
+ for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 {
+ args[i], args[j] = args[j], args[i]
+ }
+
+ if args != nil {
+ op += " " + strings.Join(args, ", ")
+ }
+
+ return op
+}
+
+// No need add "W" to opcode suffix.
+// Opcode must be inserted in ascending order.
+var noSuffixOpSet = strings.Fields(`
+CRC32B
+CRC32CB
+CRC32CH
+CRC32CW
+CRC32CX
+CRC32H
+CRC32W
+CRC32X
+LDARB
+LDARH
+LDAXRB
+LDAXRH
+LDXRB
+LDXRH
+`)
+
+func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
+ switch a := arg.(type) {
+ case Imm:
+ return fmt.Sprintf("$%d", uint32(a.Imm))
+
+ case Imm64:
+ return fmt.Sprintf("$%d", int64(a.Imm))
+
+ case ImmShift:
+ if a.shift == 0 {
+ return fmt.Sprintf("$%d", a.imm)
+ }
+ return fmt.Sprintf("$(%d<<%d)", a.imm, a.shift)
+
+ case PCRel:
+ addr := int64(pc) + int64(a)
+ if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base {
+ return fmt.Sprintf("%s(SB)", s)
+ }
+ return fmt.Sprintf("%d(PC)", a/4)
+
+ case Reg:
+ regenum := uint16(a)
+ regno := uint16(a) & 31
+
+ if regenum >= uint16(B0) && regenum <= uint16(D31) {
+ // FP registers are the same ones as SIMD registers
+ // Print Fn for scalar variant to align with assembler (e.g., FCVT)
+ return fmt.Sprintf("F%d", regno)
+ } else if regenum >= uint16(Q0) && regenum <= uint16(Q31) {
+ // Print Vn to align with assembler (e.g., SHA256H)
+ return fmt.Sprintf("V%d", regno)
+ }
+
+ if regno == 31 {
+ return "ZR"
+ }
+ return fmt.Sprintf("R%d", regno)
+
+ case RegSP:
+ regno := uint16(a) & 31
+ if regno == 31 {
+ return "RSP"
+ }
+ return fmt.Sprintf("R%d", regno)
+
+ case RegExtshiftAmount:
+ reg := ""
+ regno := uint16(a.reg) & 31
+ if regno == 31 {
+ reg = "ZR"
+ } else {
+ reg = fmt.Sprintf("R%d", uint16(a.reg)&31)
+ }
+ extshift := ""
+ amount := ""
+ if a.extShift != ExtShift(0) {
+ switch a.extShift {
+ default:
+ extshift = "." + a.extShift.String()
+
+ case lsl:
+ extshift = "<<"
+ amount = fmt.Sprintf("%d", a.amount)
+ return reg + extshift + amount
+
+ case lsr:
+ extshift = ">>"
+ amount = fmt.Sprintf("%d", a.amount)
+ return reg + extshift + amount
+
+ case asr:
+ extshift = "->"
+ amount = fmt.Sprintf("%d", a.amount)
+ return reg + extshift + amount
+ case ror:
+ extshift = "@>"
+ amount = fmt.Sprintf("%d", a.amount)
+ return reg + extshift + amount
+ }
+ if a.amount != 0 {
+ amount = fmt.Sprintf("<<%d", a.amount)
+ }
+ }
+ return reg + extshift + amount
+
+ case MemImmediate:
+ off := ""
+ base := ""
+ regno := uint16(a.Base) & 31
+ if regno == 31 {
+ base = "(RSP)"
+ } else {
+ base = fmt.Sprintf("(R%d)", regno)
+ }
+ if a.imm != 0 && a.Mode != AddrPostReg {
+ off = fmt.Sprintf("%d", a.imm)
+ } else if a.Mode == AddrPostReg {
+ postR := fmt.Sprintf("(R%d)", a.imm)
+ return base + postR
+ }
+ return off + base
+
+ case MemExtend:
+ base := ""
+ index := ""
+ extend := ""
+ indexreg := ""
+ regno := uint16(a.Base) & 31
+ if regno == 31 {
+ base = "(RSP)"
+ } else {
+ base = fmt.Sprintf("(R%d)", regno)
+ }
+ regno = uint16(a.Index) & 31
+ if regno == 31 {
+ indexreg = "ZR"
+ } else {
+ indexreg = fmt.Sprintf("R%d", regno)
+ }
+ if a.Extend == lsl {
+ if a.Amount != 0 {
+ extend = fmt.Sprintf("<<%d", a.Amount)
+ }
+ } else {
+ extend = "unimplemented!"
+ }
+ index = indexreg + extend
+ return index + base
+
+ case Cond:
+ switch arg.String() {
+ case "CS":
+ return "HS"
+ case "CC":
+ return "LO"
+ }
+
+ case Imm_clrex:
+ return fmt.Sprintf("$%d", uint32(a))
+
+ case Imm_dcps:
+ return fmt.Sprintf("$%d", uint32(a))
+
+ case Imm_option:
+ return fmt.Sprintf("$%d", uint8(a))
+
+ case Imm_hint:
+ return fmt.Sprintf("$%d", uint8(a))
+
+ case Imm_fp:
+ var s, pre, numerator, denominator int16
+ var result float64
+ if a.s == 0 {
+ s = 1
+ } else {
+ s = -1
+ }
+ pre = s * int16(16+a.pre)
+ if a.exp > 0 {
+ numerator = (pre << uint8(a.exp))
+ denominator = 16
+ } else {
+ numerator = pre
+ denominator = (16 << uint8(-1*a.exp))
+ }
+ result = float64(numerator) / float64(denominator)
+ return strings.TrimRight(fmt.Sprintf("$%f", result), "0")
+
+ case RegisterWithArrangement:
+ result := a.r.String()
+ arrange := a.a.String()
+ c := []rune(arrange)
+ switch len(c) {
+ case 3:
+ c[1], c[2] = c[2], c[1] // .8B -> .B8
+ case 4:
+ c[1], c[2], c[3] = c[3], c[1], c[2] // 16B -> B16
+ }
+ arrange = string(c)
+ result += arrange
+ if a.cnt > 0 {
+ result = "[" + result
+ for i := 1; i < int(a.cnt); i++ {
+ cur := V0 + Reg((uint16(a.r)-uint16(V0)+uint16(i))&31)
+ result += ", " + cur.String() + arrange
+ }
+ result += "]"
+ }
+ return result
+
+ case RegisterWithArrangementAndIndex:
+ result := a.r.String()
+ arrange := a.a.String()
+ result += arrange
+ if a.cnt > 0 {
+ result = "[" + result
+ for i := 1; i < int(a.cnt); i++ {
+ cur := V0 + Reg((uint16(a.r)-uint16(V0)+uint16(i))&31)
+ result += ", " + cur.String() + arrange
+ }
+ result += "]"
+ }
+ return fmt.Sprintf("%s[%d]", result, a.index)
+
+ case Systemreg:
+ return fmt.Sprintf("$%d", uint32(a.op0&1)<<14|uint32(a.op1&7)<<11|uint32(a.cn&15)<<7|uint32(a.cm&15)<<3|uint32(a.op2)&7)
+
+ }
+
+ return strings.ToUpper(arg.String())
+}
diff --git a/arm64/arm64asm/tables.go b/arm64/arm64asm/tables.go
new file mode 100644
index 0000000..ef5237d
--- /dev/null
+++ b/arm64/arm64asm/tables.go
@@ -0,0 +1,3366 @@
+// Generated by ARM internal tool
+// DO NOT EDIT
+
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package arm64asm
+
+const (
+ _ Op = iota
+ ABS
+ ADC
+ ADCS
+ ADD
+ ADDHN
+ ADDHN2
+ ADDP
+ ADDS
+ ADDV
+ ADR
+ ADRP
+ AESD
+ AESE
+ AESIMC
+ AESMC
+ AND
+ ANDS
+ ASR
+ ASRV
+ AT
+ B
+ BFI
+ BFM
+ BFXIL
+ BIC
+ BICS
+ BIF
+ BIT
+ BL
+ BLR
+ BR
+ BRK
+ BSL
+ CBNZ
+ CBZ
+ CCMN
+ CCMP
+ CINC
+ CINV
+ CLREX
+ CLS
+ CLZ
+ CMEQ
+ CMGE
+ CMGT
+ CMHI
+ CMHS
+ CMLE
+ CMLT
+ CMN
+ CMP
+ CMTST
+ CNEG
+ CNT
+ CRC32B
+ CRC32CB
+ CRC32CH
+ CRC32CW
+ CRC32CX
+ CRC32H
+ CRC32W
+ CRC32X
+ CSEL
+ CSET
+ CSETM
+ CSINC
+ CSINV
+ CSNEG
+ DC
+ DCPS1
+ DCPS2
+ DCPS3
+ DMB
+ DRPS
+ DSB
+ DUP
+ EON
+ EOR
+ ERET
+ EXT
+ EXTR
+ FABD
+ FABS
+ FACGE
+ FACGT
+ FADD
+ FADDP
+ FCCMP
+ FCCMPE
+ FCMEQ
+ FCMGE
+ FCMGT
+ FCMLE
+ FCMLT
+ FCMP
+ FCMPE
+ FCSEL
+ FCVT
+ FCVTAS
+ FCVTAU
+ FCVTL
+ FCVTL2
+ FCVTMS
+ FCVTMU
+ FCVTN
+ FCVTN2
+ FCVTNS
+ FCVTNU
+ FCVTPS
+ FCVTPU
+ FCVTXN
+ FCVTXN2
+ FCVTZS
+ FCVTZU
+ FDIV
+ FMADD
+ FMAX
+ FMAXNM
+ FMAXNMP
+ FMAXNMV
+ FMAXP
+ FMAXV
+ FMIN
+ FMINNM
+ FMINNMP
+ FMINNMV
+ FMINP
+ FMINV
+ FMLA
+ FMLS
+ FMOV
+ FMSUB
+ FMUL
+ FMULX
+ FNEG
+ FNMADD
+ FNMSUB
+ FNMUL
+ FRECPE
+ FRECPS
+ FRECPX
+ FRINTA
+ FRINTI
+ FRINTM
+ FRINTN
+ FRINTP
+ FRINTX
+ FRINTZ
+ FRSQRTE
+ FRSQRTS
+ FSQRT
+ FSUB
+ HINT
+ HLT
+ HVC
+ IC
+ INS
+ ISB
+ LD1
+ LD1R
+ LD2
+ LD2R
+ LD3
+ LD3R
+ LD4
+ LD4R
+ LDAR
+ LDARB
+ LDARH
+ LDAXP
+ LDAXR
+ LDAXRB
+ LDAXRH
+ LDNP
+ LDP
+ LDPSW
+ LDR
+ LDRB
+ LDRH
+ LDRSB
+ LDRSH
+ LDRSW
+ LDTR
+ LDTRB
+ LDTRH
+ LDTRSB
+ LDTRSH
+ LDTRSW
+ LDUR
+ LDURB
+ LDURH
+ LDURSB
+ LDURSH
+ LDURSW
+ LDXP
+ LDXR
+ LDXRB
+ LDXRH
+ LSL
+ LSLV
+ LSR
+ LSRV
+ MADD
+ MLA
+ MLS
+ MNEG
+ MOV
+ MOVI
+ MOVK
+ MOVN
+ MOVZ
+ MRS
+ MSR
+ MSUB
+ MUL
+ MVN
+ MVNI
+ NEG
+ NEGS
+ NGC
+ NGCS
+ NOP
+ NOT
+ ORN
+ ORR
+ PMUL
+ PMULL
+ PMULL2
+ PRFM
+ PRFUM
+ RADDHN
+ RADDHN2
+ RBIT
+ RET
+ REV
+ REV16
+ REV32
+ REV64
+ ROR
+ RORV
+ RSHRN
+ RSHRN2
+ RSUBHN
+ RSUBHN2
+ SABA
+ SABAL
+ SABAL2
+ SABD
+ SABDL
+ SABDL2
+ SADALP
+ SADDL
+ SADDL2
+ SADDLP
+ SADDLV
+ SADDW
+ SADDW2
+ SBC
+ SBCS
+ SBFIZ
+ SBFM
+ SBFX
+ SCVTF
+ SDIV
+ SEV
+ SEVL
+ SHA1C
+ SHA1H
+ SHA1M
+ SHA1P
+ SHA1SU0
+ SHA1SU1
+ SHA256H
+ SHA256H2
+ SHA256SU0
+ SHA256SU1
+ SHADD
+ SHL
+ SHLL
+ SHLL2
+ SHRN
+ SHRN2
+ SHSUB
+ SLI
+ SMADDL
+ SMAX
+ SMAXP
+ SMAXV
+ SMC
+ SMIN
+ SMINP
+ SMINV
+ SMLAL
+ SMLAL2
+ SMLSL
+ SMLSL2
+ SMNEGL
+ SMOV
+ SMSUBL
+ SMULH
+ SMULL
+ SMULL2
+ SQABS
+ SQADD
+ SQDMLAL
+ SQDMLAL2
+ SQDMLSL
+ SQDMLSL2
+ SQDMULH
+ SQDMULL
+ SQDMULL2
+ SQNEG
+ SQRDMULH
+ SQRSHL
+ SQRSHRN
+ SQRSHRN2
+ SQRSHRUN
+ SQRSHRUN2
+ SQSHL
+ SQSHLU
+ SQSHRN
+ SQSHRN2
+ SQSHRUN
+ SQSHRUN2
+ SQSUB
+ SQXTN
+ SQXTN2
+ SQXTUN
+ SQXTUN2
+ SRHADD
+ SRI
+ SRSHL
+ SRSHR
+ SRSRA
+ SSHL
+ SSHLL
+ SSHLL2
+ SSHR
+ SSRA
+ SSUBL
+ SSUBL2
+ SSUBW
+ SSUBW2
+ ST1
+ ST2
+ ST3
+ ST4
+ STLR
+ STLRB
+ STLRH
+ STLXP
+ STLXR
+ STLXRB
+ STLXRH
+ STNP
+ STP
+ STR
+ STRB
+ STRH
+ STTR
+ STTRB
+ STTRH
+ STUR
+ STURB
+ STURH
+ STXP
+ STXR
+ STXRB
+ STXRH
+ SUB
+ SUBHN
+ SUBHN2
+ SUBS
+ SUQADD
+ SVC
+ SXTB
+ SXTH
+ SXTL
+ SXTL2
+ SXTW
+ SYS
+ SYSL
+ TBL
+ TBNZ
+ TBX
+ TBZ
+ TLBI
+ TRN1
+ TRN2
+ TST
+ UABA
+ UABAL
+ UABAL2
+ UABD
+ UABDL
+ UABDL2
+ UADALP
+ UADDL
+ UADDL2
+ UADDLP
+ UADDLV
+ UADDW
+ UADDW2
+ UBFIZ
+ UBFM
+ UBFX
+ UCVTF
+ UDIV
+ UHADD
+ UHSUB
+ UMADDL
+ UMAX
+ UMAXP
+ UMAXV
+ UMIN
+ UMINP
+ UMINV
+ UMLAL
+ UMLAL2
+ UMLSL
+ UMLSL2
+ UMNEGL
+ UMOV
+ UMSUBL
+ UMULH
+ UMULL
+ UMULL2
+ UQADD
+ UQRSHL
+ UQRSHRN
+ UQRSHRN2
+ UQSHL
+ UQSHRN
+ UQSHRN2
+ UQSUB
+ UQXTN
+ UQXTN2
+ URECPE
+ URHADD
+ URSHL
+ URSHR
+ URSQRTE
+ URSRA
+ USHL
+ USHLL
+ USHLL2
+ USHR
+ USQADD
+ USRA
+ USUBL
+ USUBL2
+ USUBW
+ USUBW2
+ UXTB
+ UXTH
+ UXTL
+ UXTL2
+ UZP1
+ UZP2
+ WFE
+ WFI
+ XTN
+ XTN2
+ YIELD
+ ZIP1
+ ZIP2
+)
+
+var opstr = [...]string{
+ ABS: "ABS",
+ ADC: "ADC",
+ ADCS: "ADCS",
+ ADD: "ADD",
+ ADDHN: "ADDHN",
+ ADDHN2: "ADDHN2",
+ ADDP: "ADDP",
+ ADDS: "ADDS",
+ ADDV: "ADDV",
+ ADR: "ADR",
+ ADRP: "ADRP",
+ AESD: "AESD",
+ AESE: "AESE",
+ AESIMC: "AESIMC",
+ AESMC: "AESMC",
+ AND: "AND",
+ ANDS: "ANDS",
+ ASR: "ASR",
+ ASRV: "ASRV",
+ AT: "AT",
+ B: "B",
+ BFI: "BFI",
+ BFM: "BFM",
+ BFXIL: "BFXIL",
+ BIC: "BIC",
+ BICS: "BICS",
+ BIF: "BIF",
+ BIT: "BIT",
+ BL: "BL",
+ BLR: "BLR",
+ BR: "BR",
+ BRK: "BRK",
+ BSL: "BSL",
+ CBNZ: "CBNZ",
+ CBZ: "CBZ",
+ CCMN: "CCMN",
+ CCMP: "CCMP",
+ CINC: "CINC",
+ CINV: "CINV",
+ CLREX: "CLREX",
+ CLS: "CLS",
+ CLZ: "CLZ",
+ CMEQ: "CMEQ",
+ CMGE: "CMGE",
+ CMGT: "CMGT",
+ CMHI: "CMHI",
+ CMHS: "CMHS",
+ CMLE: "CMLE",
+ CMLT: "CMLT",
+ CMN: "CMN",
+ CMP: "CMP",
+ CMTST: "CMTST",
+ CNEG: "CNEG",
+ CNT: "CNT",
+ CRC32B: "CRC32B",
+ CRC32CB: "CRC32CB",
+ CRC32CH: "CRC32CH",
+ CRC32CW: "CRC32CW",
+ CRC32CX: "CRC32CX",
+ CRC32H: "CRC32H",
+ CRC32W: "CRC32W",
+ CRC32X: "CRC32X",
+ CSEL: "CSEL",
+ CSET: "CSET",
+ CSETM: "CSETM",
+ CSINC: "CSINC",
+ CSINV: "CSINV",
+ CSNEG: "CSNEG",
+ DC: "DC",
+ DCPS1: "DCPS1",
+ DCPS2: "DCPS2",
+ DCPS3: "DCPS3",
+ DMB: "DMB",
+ DRPS: "DRPS",
+ DSB: "DSB",
+ DUP: "DUP",
+ EON: "EON",
+ EOR: "EOR",
+ ERET: "ERET",
+ EXT: "EXT",
+ EXTR: "EXTR",
+ FABD: "FABD",
+ FABS: "FABS",
+ FACGE: "FACGE",
+ FACGT: "FACGT",
+ FADD: "FADD",
+ FADDP: "FADDP",
+ FCCMP: "FCCMP",
+ FCCMPE: "FCCMPE",
+ FCMEQ: "FCMEQ",
+ FCMGE: "FCMGE",
+ FCMGT: "FCMGT",
+ FCMLE: "FCMLE",
+ FCMLT: "FCMLT",
+ FCMP: "FCMP",
+ FCMPE: "FCMPE",
+ FCSEL: "FCSEL",
+ FCVT: "FCVT",
+ FCVTAS: "FCVTAS",
+ FCVTAU: "FCVTAU",
+ FCVTL: "FCVTL",
+ FCVTL2: "FCVTL2",
+ FCVTMS: "FCVTMS",
+ FCVTMU: "FCVTMU",
+ FCVTN: "FCVTN",
+ FCVTN2: "FCVTN2",
+ FCVTNS: "FCVTNS",
+ FCVTNU: "FCVTNU",
+ FCVTPS: "FCVTPS",
+ FCVTPU: "FCVTPU",
+ FCVTXN: "FCVTXN",
+ FCVTXN2: "FCVTXN2",
+ FCVTZS: "FCVTZS",
+ FCVTZU: "FCVTZU",
+ FDIV: "FDIV",
+ FMADD: "FMADD",
+ FMAX: "FMAX",
+ FMAXNM: "FMAXNM",
+ FMAXNMP: "FMAXNMP",
+ FMAXNMV: "FMAXNMV",
+ FMAXP: "FMAXP",
+ FMAXV: "FMAXV",
+ FMIN: "FMIN",
+ FMINNM: "FMINNM",
+ FMINNMP: "FMINNMP",
+ FMINNMV: "FMINNMV",
+ FMINP: "FMINP",
+ FMINV: "FMINV",
+ FMLA: "FMLA",
+ FMLS: "FMLS",
+ FMOV: "FMOV",
+ FMSUB: "FMSUB",
+ FMUL: "FMUL",
+ FMULX: "FMULX",
+ FNEG: "FNEG",
+ FNMADD: "FNMADD",
+ FNMSUB: "FNMSUB",
+ FNMUL: "FNMUL",
+ FRECPE: "FRECPE",
+ FRECPS: "FRECPS",
+ FRECPX: "FRECPX",
+ FRINTA: "FRINTA",
+ FRINTI: "FRINTI",
+ FRINTM: "FRINTM",
+ FRINTN: "FRINTN",
+ FRINTP: "FRINTP",
+ FRINTX: "FRINTX",
+ FRINTZ: "FRINTZ",
+ FRSQRTE: "FRSQRTE",
+ FRSQRTS: "FRSQRTS",
+ FSQRT: "FSQRT",
+ FSUB: "FSUB",
+ HINT: "HINT",
+ HLT: "HLT",
+ HVC: "HVC",
+ IC: "IC",
+ INS: "INS",
+ ISB: "ISB",
+ LD1: "LD1",
+ LD1R: "LD1R",
+ LD2: "LD2",
+ LD2R: "LD2R",
+ LD3: "LD3",
+ LD3R: "LD3R",
+ LD4: "LD4",
+ LD4R: "LD4R",
+ LDAR: "LDAR",
+ LDARB: "LDARB",
+ LDARH: "LDARH",
+ LDAXP: "LDAXP",
+ LDAXR: "LDAXR",
+ LDAXRB: "LDAXRB",
+ LDAXRH: "LDAXRH",
+ LDNP: "LDNP",
+ LDP: "LDP",
+ LDPSW: "LDPSW",
+ LDR: "LDR",
+ LDRB: "LDRB",
+ LDRH: "LDRH",
+ LDRSB: "LDRSB",
+ LDRSH: "LDRSH",
+ LDRSW: "LDRSW",
+ LDTR: "LDTR",
+ LDTRB: "LDTRB",
+ LDTRH: "LDTRH",
+ LDTRSB: "LDTRSB",
+ LDTRSH: "LDTRSH",
+ LDTRSW: "LDTRSW",
+ LDUR: "LDUR",
+ LDURB: "LDURB",
+ LDURH: "LDURH",
+ LDURSB: "LDURSB",
+ LDURSH: "LDURSH",
+ LDURSW: "LDURSW",
+ LDXP: "LDXP",
+ LDXR: "LDXR",
+ LDXRB: "LDXRB",
+ LDXRH: "LDXRH",
+ LSL: "LSL",
+ LSLV: "LSLV",
+ LSR: "LSR",
+ LSRV: "LSRV",
+ MADD: "MADD",
+ MLA: "MLA",
+ MLS: "MLS",
+ MNEG: "MNEG",
+ MOV: "MOV",
+ MOVI: "MOVI",
+ MOVK: "MOVK",
+ MOVN: "MOVN",
+ MOVZ: "MOVZ",
+ MRS: "MRS",
+ MSR: "MSR",
+ MSUB: "MSUB",
+ MUL: "MUL",
+ MVN: "MVN",
+ MVNI: "MVNI",
+ NEG: "NEG",
+ NEGS: "NEGS",
+ NGC: "NGC",
+ NGCS: "NGCS",
+ NOP: "NOP",
+ NOT: "NOT",
+ ORN: "ORN",
+ ORR: "ORR",
+ PMUL: "PMUL",
+ PMULL: "PMULL",
+ PMULL2: "PMULL2",
+ PRFM: "PRFM",
+ PRFUM: "PRFUM",
+ RADDHN: "RADDHN",
+ RADDHN2: "RADDHN2",
+ RBIT: "RBIT",
+ RET: "RET",
+ REV: "REV",
+ REV16: "REV16",
+ REV32: "REV32",
+ REV64: "REV64",
+ ROR: "ROR",
+ RORV: "RORV",
+ RSHRN: "RSHRN",
+ RSHRN2: "RSHRN2",
+ RSUBHN: "RSUBHN",
+ RSUBHN2: "RSUBHN2",
+ SABA: "SABA",
+ SABAL: "SABAL",
+ SABAL2: "SABAL2",
+ SABD: "SABD",
+ SABDL: "SABDL",
+ SABDL2: "SABDL2",
+ SADALP: "SADALP",
+ SADDL: "SADDL",
+ SADDL2: "SADDL2",
+ SADDLP: "SADDLP",
+ SADDLV: "SADDLV",
+ SADDW: "SADDW",
+ SADDW2: "SADDW2",
+ SBC: "SBC",
+ SBCS: "SBCS",
+ SBFIZ: "SBFIZ",
+ SBFM: "SBFM",
+ SBFX: "SBFX",
+ SCVTF: "SCVTF",
+ SDIV: "SDIV",
+ SEV: "SEV",
+ SEVL: "SEVL",
+ SHA1C: "SHA1C",
+ SHA1H: "SHA1H",
+ SHA1M: "SHA1M",
+ SHA1P: "SHA1P",
+ SHA1SU0: "SHA1SU0",
+ SHA1SU1: "SHA1SU1",
+ SHA256H: "SHA256H",
+ SHA256H2: "SHA256H2",
+ SHA256SU0: "SHA256SU0",
+ SHA256SU1: "SHA256SU1",
+ SHADD: "SHADD",
+ SHL: "SHL",
+ SHLL: "SHLL",
+ SHLL2: "SHLL2",
+ SHRN: "SHRN",
+ SHRN2: "SHRN2",
+ SHSUB: "SHSUB",
+ SLI: "SLI",
+ SMADDL: "SMADDL",
+ SMAX: "SMAX",
+ SMAXP: "SMAXP",
+ SMAXV: "SMAXV",
+ SMC: "SMC",
+ SMIN: "SMIN",
+ SMINP: "SMINP",
+ SMINV: "SMINV",
+ SMLAL: "SMLAL",
+ SMLAL2: "SMLAL2",
+ SMLSL: "SMLSL",
+ SMLSL2: "SMLSL2",
+ SMNEGL: "SMNEGL",
+ SMOV: "SMOV",
+ SMSUBL: "SMSUBL",
+ SMULH: "SMULH",
+ SMULL: "SMULL",
+ SMULL2: "SMULL2",
+ SQABS: "SQABS",
+ SQADD: "SQADD",
+ SQDMLAL: "SQDMLAL",
+ SQDMLAL2: "SQDMLAL2",
+ SQDMLSL: "SQDMLSL",
+ SQDMLSL2: "SQDMLSL2",
+ SQDMULH: "SQDMULH",
+ SQDMULL: "SQDMULL",
+ SQDMULL2: "SQDMULL2",
+ SQNEG: "SQNEG",
+ SQRDMULH: "SQRDMULH",
+ SQRSHL: "SQRSHL",
+ SQRSHRN: "SQRSHRN",
+ SQRSHRN2: "SQRSHRN2",
+ SQRSHRUN: "SQRSHRUN",
+ SQRSHRUN2: "SQRSHRUN2",
+ SQSHL: "SQSHL",
+ SQSHLU: "SQSHLU",
+ SQSHRN: "SQSHRN",
+ SQSHRN2: "SQSHRN2",
+ SQSHRUN: "SQSHRUN",
+ SQSHRUN2: "SQSHRUN2",
+ SQSUB: "SQSUB",
+ SQXTN: "SQXTN",
+ SQXTN2: "SQXTN2",
+ SQXTUN: "SQXTUN",
+ SQXTUN2: "SQXTUN2",
+ SRHADD: "SRHADD",
+ SRI: "SRI",
+ SRSHL: "SRSHL",
+ SRSHR: "SRSHR",
+ SRSRA: "SRSRA",
+ SSHL: "SSHL",
+ SSHLL: "SSHLL",
+ SSHLL2: "SSHLL2",
+ SSHR: "SSHR",
+ SSRA: "SSRA",
+ SSUBL: "SSUBL",
+ SSUBL2: "SSUBL2",
+ SSUBW: "SSUBW",
+ SSUBW2: "SSUBW2",
+ ST1: "ST1",
+ ST2: "ST2",
+ ST3: "ST3",
+ ST4: "ST4",
+ STLR: "STLR",
+ STLRB: "STLRB",
+ STLRH: "STLRH",
+ STLXP: "STLXP",
+ STLXR: "STLXR",
+ STLXRB: "STLXRB",
+ STLXRH: "STLXRH",
+ STNP: "STNP",
+ STP: "STP",
+ STR: "STR",
+ STRB: "STRB",
+ STRH: "STRH",
+ STTR: "STTR",
+ STTRB: "STTRB",
+ STTRH: "STTRH",
+ STUR: "STUR",
+ STURB: "STURB",
+ STURH: "STURH",
+ STXP: "STXP",
+ STXR: "STXR",
+ STXRB: "STXRB",
+ STXRH: "STXRH",
+ SUB: "SUB",
+ SUBHN: "SUBHN",
+ SUBHN2: "SUBHN2",
+ SUBS: "SUBS",
+ SUQADD: "SUQADD",
+ SVC: "SVC",
+ SXTB: "SXTB",
+ SXTH: "SXTH",
+ SXTL: "SXTL",
+ SXTL2: "SXTL2",
+ SXTW: "SXTW",
+ SYS: "SYS",
+ SYSL: "SYSL",
+ TBL: "TBL",
+ TBNZ: "TBNZ",
+ TBX: "TBX",
+ TBZ: "TBZ",
+ TLBI: "TLBI",
+ TRN1: "TRN1",
+ TRN2: "TRN2",
+ TST: "TST",
+ UABA: "UABA",
+ UABAL: "UABAL",
+ UABAL2: "UABAL2",
+ UABD: "UABD",
+ UABDL: "UABDL",
+ UABDL2: "UABDL2",
+ UADALP: "UADALP",
+ UADDL: "UADDL",
+ UADDL2: "UADDL2",
+ UADDLP: "UADDLP",
+ UADDLV: "UADDLV",
+ UADDW: "UADDW",
+ UADDW2: "UADDW2",
+ UBFIZ: "UBFIZ",
+ UBFM: "UBFM",
+ UBFX: "UBFX",
+ UCVTF: "UCVTF",
+ UDIV: "UDIV",
+ UHADD: "UHADD",
+ UHSUB: "UHSUB",
+ UMADDL: "UMADDL",
+ UMAX: "UMAX",
+ UMAXP: "UMAXP",
+ UMAXV: "UMAXV",
+ UMIN: "UMIN",
+ UMINP: "UMINP",
+ UMINV: "UMINV",
+ UMLAL: "UMLAL",
+ UMLAL2: "UMLAL2",
+ UMLSL: "UMLSL",
+ UMLSL2: "UMLSL2",
+ UMNEGL: "UMNEGL",
+ UMOV: "UMOV",
+ UMSUBL: "UMSUBL",
+ UMULH: "UMULH",
+ UMULL: "UMULL",
+ UMULL2: "UMULL2",
+ UQADD: "UQADD",
+ UQRSHL: "UQRSHL",
+ UQRSHRN: "UQRSHRN",
+ UQRSHRN2: "UQRSHRN2",
+ UQSHL: "UQSHL",
+ UQSHRN: "UQSHRN",
+ UQSHRN2: "UQSHRN2",
+ UQSUB: "UQSUB",
+ UQXTN: "UQXTN",
+ UQXTN2: "UQXTN2",
+ URECPE: "URECPE",
+ URHADD: "URHADD",
+ URSHL: "URSHL",
+ URSHR: "URSHR",
+ URSQRTE: "URSQRTE",
+ URSRA: "URSRA",
+ USHL: "USHL",
+ USHLL: "USHLL",
+ USHLL2: "USHLL2",
+ USHR: "USHR",
+ USQADD: "USQADD",
+ USRA: "USRA",
+ USUBL: "USUBL",
+ USUBL2: "USUBL2",
+ USUBW: "USUBW",
+ USUBW2: "USUBW2",
+ UXTB: "UXTB",
+ UXTH: "UXTH",
+ UXTL: "UXTL",
+ UXTL2: "UXTL2",
+ UZP1: "UZP1",
+ UZP2: "UZP2",
+ WFE: "WFE",
+ WFI: "WFI",
+ XTN: "XTN",
+ XTN2: "XTN2",
+ YIELD: "YIELD",
+ ZIP1: "ZIP1",
+ ZIP2: "ZIP2",
+}
+
+var instFormats = [...]instFormat{
+ // ADC <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1a000000, ADC, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // ADC <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9a000000, ADC, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // ADCS <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x3a000000, ADCS, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // ADCS <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0xba000000, ADCS, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // ADD <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+ {0xffe00000, 0x0b200000, ADD, instArgs{arg_Wds, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // ADD <Xd|SP>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}}
+ {0xffe00000, 0x8b200000, ADD, instArgs{arg_Xds, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // MOV <Wd|WSP>, <Wn|WSP>
+ {0xfffffc00, 0x11000000, MOV, instArgs{arg_Wds, arg_Wns}, mov_add_32_addsub_imm_cond},
+ // ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
+ {0xff000000, 0x11000000, ADD, instArgs{arg_Wds, arg_Wns, arg_IAddSub}, nil},
+ // MOV <Xd|SP>, <Xn|SP>
+ {0xfffffc00, 0x91000000, MOV, instArgs{arg_Xds, arg_Xns}, mov_add_64_addsub_imm_cond},
+ // ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
+ {0xff000000, 0x91000000, ADD, instArgs{arg_Xds, arg_Xns, arg_IAddSub}, nil},
+ // ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x0b000000, ADD, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0x8b000000, ADD, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+ {0xffe0001f, 0x2b20001f, CMN, instArgs{arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+ {0xffe00000, 0x2b200000, ADDS, instArgs{arg_Wd, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // CMN <Xn|SP>, <R><m>{, <extend_1> {#<amount>}}
+ {0xffe0001f, 0xab20001f, CMN, instArgs{arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // ADDS <Xd>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}}
+ {0xffe00000, 0xab200000, ADDS, instArgs{arg_Xd, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // CMN <Wn|WSP>, #<imm>{, <shift>}
+ {0xff00001f, 0x3100001f, CMN, instArgs{arg_Wns, arg_IAddSub}, nil},
+ // ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
+ {0xff000000, 0x31000000, ADDS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil},
+ // CMN <Xn|SP>, #<imm>{, <shift>}
+ {0xff00001f, 0xb100001f, CMN, instArgs{arg_Xns, arg_IAddSub}, nil},
+ // ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}
+ {0xff000000, 0xb1000000, ADDS, instArgs{arg_Xd, arg_Xns, arg_IAddSub}, nil},
+ // CMN <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff20801f, 0x2b00001f, CMN, instArgs{arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x2b000000, ADDS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // CMN <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff20001f, 0xab00001f, CMN, instArgs{arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xab000000, ADDS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // ADR <Xd>, <label>
+ {0x9f000000, 0x10000000, ADR, instArgs{arg_Xd, arg_slabel_immhi_immlo_0}, nil},
+ // ADRP <Xd>, <label>
+ {0x9f000000, 0x90000000, ADRP, instArgs{arg_Xd, arg_slabel_immhi_immlo_12}, nil},
+ // AND <Wd|WSP>, <Wn>, #<imm>
+ {0xffc00000, 0x12000000, AND, instArgs{arg_Wds, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil},
+ // AND <Xd|SP>, <Xn>, #<imm>
+ {0xff800000, 0x92000000, AND, instArgs{arg_Xds, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},
+ // AND <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x0a000000, AND, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // AND <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0x8a000000, AND, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // TST <Wn>, #<imm>
+ {0xffc0001f, 0x7200001f, TST, instArgs{arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil},
+ // ANDS <Wd>, <Wn>, #<imm>
+ {0xffc00000, 0x72000000, ANDS, instArgs{arg_Wd, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil},
+ // TST <Xn>, #<imm>
+ {0xff80001f, 0xf200001f, TST, instArgs{arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},
+ // ANDS <Xd>, <Xn>, #<imm>
+ {0xff800000, 0xf2000000, ANDS, instArgs{arg_Xd, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},
+ // TST <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff20801f, 0x6a00001f, TST, instArgs{arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x6a000000, ANDS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // TST <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff20001f, 0xea00001f, TST, instArgs{arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xea000000, ANDS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // ASR <Wd>, <Wn>, #<shift>
+ {0xffc0fc00, 0x13007c00, ASR, instArgs{arg_Wd, arg_Wn, arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr}, nil},
+ // SBFIZ <Wd>, <Wn>, #<lsb>, #<width>
+ {0xffc00000, 0x13000000, SBFIZ, instArgs{arg_Wd, arg_Wn, arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr, arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms}, sbfiz_sbfm_32m_bitfield_cond},
+ // SBFX <Wd>, <Wn>, #<lsb>, #<width>
+ {0xffc00000, 0x13000000, SBFX, instArgs{arg_Wd, arg_Wn, arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr, arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms}, sbfx_sbfm_32m_bitfield_cond},
+ // SXTB <Wd>, <Wn>
+ {0xfffffc00, 0x13001c00, SXTB, instArgs{arg_Wd, arg_Wn}, nil},
+ // SXTH <Wd>, <Wn>
+ {0xfffffc00, 0x13003c00, SXTH, instArgs{arg_Wd, arg_Wn}, nil},
+ // SBFM <Wd>, <Wn>, #<immr>, #<imms>
+ {0xffc00000, 0x13000000, SBFM, instArgs{arg_Wd, arg_Wn, arg_immediate_0_31_immr, arg_immediate_0_31_imms}, nil},
+ // ASR <Xd>, <Xn>, #<shift>
+ {0xffc0fc00, 0x9340fc00, ASR, instArgs{arg_Xd, arg_Xn, arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr}, nil},
+ // SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
+ {0xffc00000, 0x93400000, SBFIZ, instArgs{arg_Xd, arg_Xn, arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr, arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms}, sbfiz_sbfm_64m_bitfield_cond},
+ // SBFX <Xd>, <Xn>, #<lsb>, #<width>
+ {0xffc00000, 0x93400000, SBFX, instArgs{arg_Xd, arg_Xn, arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr, arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms}, sbfx_sbfm_64m_bitfield_cond},
+ // SXTB <Xd>, <Wn>
+ {0xfffffc00, 0x93401c00, SXTB, instArgs{arg_Xd, arg_Wn}, nil},
+ // SXTH <Xd>, <Wn>
+ {0xfffffc00, 0x93403c00, SXTH, instArgs{arg_Xd, arg_Wn}, nil},
+ // SXTW <Xd>, <Wn>
+ {0xfffffc00, 0x93407c00, SXTW, instArgs{arg_Xd, arg_Wn}, nil},
+ // SBFM <Xd>, <Xn>, #<immr>, #<imms>
+ {0xffc00000, 0x93400000, SBFM, instArgs{arg_Xd, arg_Xn, arg_immediate_0_63_immr, arg_immediate_0_63_imms}, nil},
+ // ASR <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02800, ASR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // ASRV <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02800, ASRV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // ASR <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02800, ASR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // ASRV <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02800, ASRV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // AT <at>, <Xt>
+ {0xfff8ff00, 0xd5087800, AT, instArgs{arg_sysop_AT_SYS_CR_system}, at_sys_cr_system_cond},
+ // DC <dc>, <Xt>
+ {0xfff8f000, 0xd5087000, DC, instArgs{arg_sysop_DC_SYS_CR_system}, dc_sys_cr_system_cond},
+ // IC <ic>, {<Xt>}
+ {0xfff8f000, 0xd5087000, IC, instArgs{arg_sysop_IC_SYS_CR_system}, ic_sys_cr_system_cond},
+ // TLBI <tlbi>, {<Xt>}
+ {0xfff8f000, 0xd5088000, TLBI, instArgs{arg_sysop_TLBI_SYS_CR_system}, tlbi_sys_cr_system_cond},
+ // SYS #<op1>, <Cn>, <Cm>, <op>, {<Xt>}
+ {0xfff80000, 0xd5080000, SYS, instArgs{arg_immediate_0_7_op1, arg_Cn, arg_Cm, arg_sysop_SYS_CR_system}, nil},
+ // B <label>
+ {0xfc000000, 0x14000000, B, instArgs{arg_slabel_imm26_2}, nil},
+ // B<c> <label>
+ {0xff000010, 0x54000000, B, instArgs{arg_conditional, arg_slabel_imm19_2}, nil},
+ // BFI <Wd>, <Wn>, #<lsb>, #<width>
+ {0xffc00000, 0x33000000, BFI, instArgs{arg_Wd, arg_Wn, arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr, arg_immediate_BFI_BFM_32M_bitfield_width_32_imms}, bfi_bfm_32m_bitfield_cond},
+ // BFXIL <Wd>, <Wn>, #<lsb>, #<width>
+ {0xffc00000, 0x33000000, BFXIL, instArgs{arg_Wd, arg_Wn, arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr, arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms}, bfxil_bfm_32m_bitfield_cond},
+ // BFM <Wd>, <Wn>, #<immr>, #<imms>
+ {0xffc00000, 0x33000000, BFM, instArgs{arg_Wd, arg_Wn, arg_immediate_0_31_immr, arg_immediate_0_31_imms}, nil},
+ // BFI <Xd>, <Xn>, #<lsb>, #<width>
+ {0xffc00000, 0xb3400000, BFI, instArgs{arg_Xd, arg_Xn, arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr, arg_immediate_BFI_BFM_64M_bitfield_width_64_imms}, bfi_bfm_64m_bitfield_cond},
+ // BFXIL <Xd>, <Xn>, #<lsb>, #<width>
+ {0xffc00000, 0xb3400000, BFXIL, instArgs{arg_Xd, arg_Xn, arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr, arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms}, bfxil_bfm_64m_bitfield_cond},
+ // BFM <Xd>, <Xn>, #<immr>, #<imms>
+ {0xffc00000, 0xb3400000, BFM, instArgs{arg_Xd, arg_Xn, arg_immediate_0_63_immr, arg_immediate_0_63_imms}, nil},
+ // BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x0a200000, BIC, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0x8a200000, BIC, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x6a200000, BICS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xea200000, BICS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // BL <label>
+ {0xfc000000, 0x94000000, BL, instArgs{arg_slabel_imm26_2}, nil},
+ // BLR <Xn>
+ {0xfffffc1f, 0xd63f0000, BLR, instArgs{arg_Xn}, nil},
+ // BR <Xn>
+ {0xfffffc1f, 0xd61f0000, BR, instArgs{arg_Xn}, nil},
+ // BRK #<imm>
+ {0xffe0001f, 0xd4200000, BRK, instArgs{arg_immediate_0_65535_imm16}, nil},
+ // CBNZ <Wt>, <label>
+ {0xff000000, 0x35000000, CBNZ, instArgs{arg_Wt, arg_slabel_imm19_2}, nil},
+ // CBNZ <Xt>, <label>
+ {0xff000000, 0xb5000000, CBNZ, instArgs{arg_Xt, arg_slabel_imm19_2}, nil},
+ // CBZ <Wt>, <label>
+ {0xff000000, 0x34000000, CBZ, instArgs{arg_Wt, arg_slabel_imm19_2}, nil},
+ // CBZ <Xt>, <label>
+ {0xff000000, 0xb4000000, CBZ, instArgs{arg_Xt, arg_slabel_imm19_2}, nil},
+ // CCMN <Wn>, #<imm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x3a400800, CCMN, instArgs{arg_Wn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMN <Xn>, #<imm>, #<nzcv>, <cond>
+ {0xffe00c10, 0xba400800, CCMN, instArgs{arg_Xn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMN <Wn>, <Wm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x3a400000, CCMN, instArgs{arg_Wn, arg_Wm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMN <Xn>, <Xm>, #<nzcv>, <cond>
+ {0xffe00c10, 0xba400000, CCMN, instArgs{arg_Xn, arg_Xm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMP <Wn>, #<imm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x7a400800, CCMP, instArgs{arg_Wn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMP <Xn>, #<imm>, #<nzcv>, <cond>
+ {0xffe00c10, 0xfa400800, CCMP, instArgs{arg_Xn, arg_immediate_0_31_imm5, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMP <Wn>, <Wm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x7a400000, CCMP, instArgs{arg_Wn, arg_Wm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CCMP <Xn>, <Xm>, #<nzcv>, <cond>
+ {0xffe00c10, 0xfa400000, CCMP, instArgs{arg_Xn, arg_Xm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // CINC <Wd>, <Wn>, <cond>
+ {0xffe00c00, 0x1a800400, CINC, instArgs{arg_Wd, arg_Wn, arg_cond_NotAllowALNV_Invert}, cinc_csinc_32_condsel_cond},
+ // CSET <Wd>, <cond>
+ {0xffff0fe0, 0x1a9f07e0, CSET, instArgs{arg_Wd, arg_cond_NotAllowALNV_Invert}, csinc_general_cond},
+ // CSINC <Wd>, <Wn>, <Wm>, <cond>
+ {0xffe00c00, 0x1a800400, CSINC, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil},
+ // CINC <Xd>, <Xn>, <cond>
+ {0xffe00c00, 0x9a800400, CINC, instArgs{arg_Xd, arg_Xn, arg_cond_NotAllowALNV_Invert}, cinc_csinc_64_condsel_cond},
+ // CSET <Xd>, <cond>
+ {0xffff0fe0, 0x9a9f07e0, CSET, instArgs{arg_Xd, arg_cond_NotAllowALNV_Invert}, csinc_general_cond},
+ // CSINC <Xd>, <Xn>, <Xm>, <cond>
+ {0xffe00c00, 0x9a800400, CSINC, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil},
+ // CINV <Wd>, <Wn>, <cond>
+ {0xffe00c00, 0x5a800000, CINV, instArgs{arg_Wd, arg_Wn, arg_cond_NotAllowALNV_Invert}, cinv_csinv_32_condsel_cond},
+ // CSETM <Wd>, <cond>
+ {0xffff0fe0, 0x5a9f03e0, CSETM, instArgs{arg_Wd, arg_cond_NotAllowALNV_Invert}, csinv_general_cond},
+ // CSINV <Wd>, <Wn>, <Wm>, <cond>
+ {0xffe00c00, 0x5a800000, CSINV, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil},
+ // CINV <Xd>, <Xn>, <cond>
+ {0xffe00c00, 0xda800000, CINV, instArgs{arg_Xd, arg_Xn, arg_cond_NotAllowALNV_Invert}, cinv_csinv_64_condsel_cond},
+ // CSETM <Xd>, <cond>
+ {0xffff0fe0, 0xda9f03e0, CSETM, instArgs{arg_Xd, arg_cond_NotAllowALNV_Invert}, csinv_general_cond},
+ // CSINV <Xd>, <Xn>, <Xm>, <cond>
+ {0xffe00c00, 0xda800000, CSINV, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil},
+ // CLREX {#<imm>}
+ {0xfffff0ff, 0xd503305f, CLREX, instArgs{arg_immediate_optional_0_15_CRm}, nil},
+ // CLS <Wd>, <Wn>
+ {0xfffffc00, 0x5ac01400, CLS, instArgs{arg_Wd, arg_Wn}, nil},
+ // CLS <Xd>, <Xn>
+ {0xfffffc00, 0xdac01400, CLS, instArgs{arg_Xd, arg_Xn}, nil},
+ // CLZ <Wd>, <Wn>
+ {0xfffffc00, 0x5ac01000, CLZ, instArgs{arg_Wd, arg_Wn}, nil},
+ // CLZ <Xd>, <Xn>
+ {0xfffffc00, 0xdac01000, CLZ, instArgs{arg_Xd, arg_Xn}, nil},
+ // CMP <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+ {0xffe0001f, 0x6b20001f, CMP, instArgs{arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+ {0xffe00000, 0x6b200000, SUBS, instArgs{arg_Wd, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // CMP <Xn|SP>, <R><m>{, <extend_1> {#<amount>}}
+ {0xffe0001f, 0xeb20001f, CMP, instArgs{arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // SUBS <Xd>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}}
+ {0xffe00000, 0xeb200000, SUBS, instArgs{arg_Xd, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // CMP <Wn|WSP>, #<imm>{, <shift>}
+ {0xff00001f, 0x7100001f, CMP, instArgs{arg_Wns, arg_IAddSub}, nil},
+ // SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
+ {0xff000000, 0x71000000, SUBS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil},
+ // CMP <Xn|SP>, #<imm>{, <shift>}
+ {0xff00001f, 0xf100001f, CMP, instArgs{arg_Xns, arg_IAddSub}, nil},
+ // SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}
+ {0xff000000, 0xf1000000, SUBS, instArgs{arg_Xd, arg_Xns, arg_IAddSub}, nil},
+ // CMP <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff20801f, 0x6b00001f, CMP, instArgs{arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // NEGS <Wd>, <Wm> {, <shift> #<amount> }
+ {0xff2003e0, 0x6b0003e0, NEGS, instArgs{arg_Wd, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x6b000000, SUBS, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // CMP <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff20001f, 0xeb00001f, CMP, instArgs{arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // NEGS <Xd>, <Xm> {, <shift> #<amount> }
+ {0xff2003e0, 0xeb0003e0, NEGS, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xeb000000, SUBS, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // CNEG <Wd>, <Wn>, <cond>
+ {0xffe00c00, 0x5a800400, CNEG, instArgs{arg_Wd, arg_Wn, arg_cond_NotAllowALNV_Invert}, cneg_csneg_32_condsel_cond},
+ // CSNEG <Wd>, <Wn>, <Wm>, <cond>
+ {0xffe00c00, 0x5a800400, CSNEG, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil},
+ // CNEG <Xd>, <Xn>, <cond>
+ {0xffe00c00, 0xda800400, CNEG, instArgs{arg_Xd, arg_Xn, arg_cond_NotAllowALNV_Invert}, cneg_csneg_64_condsel_cond},
+ // CSNEG <Xd>, <Xn>, <Xm>, <cond>
+ {0xffe00c00, 0xda800400, CSNEG, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil},
+ // CRC32B <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac04000, CRC32B, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // CRC32H <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac04400, CRC32H, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // CRC32W <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac04800, CRC32W, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // CRC32X <Wd>, <Wn>, <Xm>
+ {0xffe0fc00, 0x9ac04c00, CRC32X, instArgs{arg_Wd, arg_Wn, arg_Xm}, nil},
+ // CRC32CB <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac05000, CRC32CB, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // CRC32CH <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac05400, CRC32CH, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // CRC32CW <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac05800, CRC32CW, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // CRC32CX <Wd>, <Wn>, <Xm>
+ {0xffe0fc00, 0x9ac05c00, CRC32CX, instArgs{arg_Wd, arg_Wn, arg_Xm}, nil},
+ // CSEL <Wd>, <Wn>, <Wm>, <cond>
+ {0xffe00c00, 0x1a800000, CSEL, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil},
+ // CSEL <Xd>, <Xn>, <Xm>, <cond>
+ {0xffe00c00, 0x9a800000, CSEL, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil},
+ // DCPS1 {#<imm>}
+ {0xffe0001f, 0xd4a00001, DCPS1, instArgs{arg_immediate_optional_0_65535_imm16}, nil},
+ // DCPS2 {#<imm>}
+ {0xffe0001f, 0xd4a00002, DCPS2, instArgs{arg_immediate_optional_0_65535_imm16}, nil},
+ // DCPS3 {#<imm>}
+ {0xffe0001f, 0xd4a00003, DCPS3, instArgs{arg_immediate_optional_0_65535_imm16}, nil},
+ // DMB <option>|<imm>
+ {0xfffff0ff, 0xd50330bf, DMB, instArgs{arg_option_DMB_BO_system_CRm}, nil},
+ // DRPS
+ {0xffffffff, 0xd6bf03e0, DRPS, instArgs{}, nil},
+ // DSB <option>|<imm>
+ {0xfffff0ff, 0xd503309f, DSB, instArgs{arg_option_DSB_BO_system_CRm}, nil},
+ // EON <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x4a200000, EON, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // EON <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xca200000, EON, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // EOR <Wd|WSP>, <Wn>, #<imm>
+ {0xffc00000, 0x52000000, EOR, instArgs{arg_Wds, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil},
+ // EOR <Xd|SP>, <Xn>, #<imm>
+ {0xff800000, 0xd2000000, EOR, instArgs{arg_Xds, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},
+ // EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x4a000000, EOR, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // EOR <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xca000000, EOR, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // ERET
+ {0xffffffff, 0xd69f03e0, ERET, instArgs{}, nil},
+ // ROR <Wd>, <Ws>, #<shift>
+ {0xffe08000, 0x13800000, ROR, instArgs{arg_Wd, arg_Ws, arg_immediate_0_31_imms}, ror_extr_32_extract_cond},
+ // EXTR <Wd>, <Wn>, <Wm>, #<lsb>
+ {0xffe08000, 0x13800000, EXTR, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_immediate_0_31_imms}, nil},
+ // ROR <Xd>, <Xs>, #<shift>
+ {0xffe00000, 0x93c00000, ROR, instArgs{arg_Xd, arg_Xs, arg_immediate_0_63_imms}, ror_extr_64_extract_cond},
+ // EXTR <Xd>, <Xn>, <Xm>, #<lsb>
+ {0xffe00000, 0x93c00000, EXTR, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_immediate_0_63_imms}, nil},
+ // NOP
+ {0xffffffff, 0xd503201f, NOP, instArgs{}, nil},
+ // SEV
+ {0xffffffff, 0xd503209f, SEV, instArgs{}, nil},
+ // SEVL
+ {0xffffffff, 0xd50320bf, SEVL, instArgs{}, nil},
+ // WFE
+ {0xffffffff, 0xd503205f, WFE, instArgs{}, nil},
+ // WFI
+ {0xffffffff, 0xd503207f, WFI, instArgs{}, nil},
+ // YIELD
+ {0xffffffff, 0xd503203f, YIELD, instArgs{}, nil},
+ // HINT #<imm>
+ {0xfffff01f, 0xd503201f, HINT, instArgs{arg_immediate_0_127_CRm_op2}, nil},
+ // HLT #<imm>
+ {0xffe0001f, 0xd4400000, HLT, instArgs{arg_immediate_0_65535_imm16}, nil},
+ // ISB {<option>|<imm>}
+ {0xfffff0ff, 0xd50330df, ISB, instArgs{arg_option_ISB_BI_system_CRm}, nil},
+ // LDAR <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88c08000, LDAR, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDAR <Xt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8c08000, LDAR, instArgs{arg_Xt, arg_Xns_mem}, nil},
+ // LDARB <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x08c08000, LDARB, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDARH <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x48c08000, LDARH, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDAXP <Wt>, <Wt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88608000, LDAXP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem}, nil},
+ // LDAXP <Xt>, <Xt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8608000, LDAXP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem}, nil},
+ // LDAXR <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88408000, LDAXR, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDAXR <Xt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8408000, LDAXR, instArgs{arg_Xt, arg_Xns_mem}, nil},
+ // LDAXRB <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x08408000, LDAXRB, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDAXRH <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x48408000, LDAXRH, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDNP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x28400000, LDNP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // LDNP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_1>}]
+ {0xffc00000, 0xa8400000, LDNP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // LDP <Wt>, <Wt2>, [<Xn|SP>], #<imm_1>
+ {0xffc00000, 0x28c00000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_post_imm7_4_signed}, nil},
+ // LDP <Xt>, <Xt2>, [<Xn|SP>], #<imm_3>
+ {0xffc00000, 0xa8c00000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_8_signed}, nil},
+ // LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm_1>}]!
+ {0xffc00000, 0x29c00000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_wb_imm7_4_signed}, nil},
+ // LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_3>}]!
+ {0xffc00000, 0xa9c00000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_wb_imm7_8_signed}, nil},
+ // LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x29400000, LDP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_2>}]
+ {0xffc00000, 0xa9400000, LDP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // LDPSW <Xt>, <Xt2>, [<Xn|SP>], #<imm_1>
+ {0xffc00000, 0x68c00000, LDPSW, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_4_signed}, nil},
+ // LDPSW <Xt>, <Xt2>, [<Xn|SP>{, #<imm_1>}]!
+ {0xffc00000, 0x69c00000, LDPSW, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_wb_imm7_4_signed}, nil},
+ // LDPSW <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x69400000, LDPSW, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // LDR <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xb8400400, LDR, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <Xt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xf8400400, LDR, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xb8400c00, LDR, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <Xt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xf8400c00, LDR, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0xb9400000, LDR, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_4_unsigned}, nil},
+ // LDR <Xt>, [<Xn|SP>{, #<pimm_1>}]
+ {0xffc00000, 0xf9400000, LDR, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_8_unsigned}, nil},
+ // LDR <Wt>, <label>
+ {0xff000000, 0x18000000, LDR, instArgs{arg_Wt, arg_slabel_imm19_2}, nil},
+ // LDR <Xt>, <label>
+ {0xff000000, 0x58000000, LDR, instArgs{arg_Xt, arg_slabel_imm19_2}, nil},
+ // LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xb8600800, LDR, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil},
+ // LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xf8600800, LDR, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil},
+ // LDRB <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x38400400, LDRB, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRB <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x38400c00, LDRB, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRB <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x39400000, LDRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_1_unsigned}, nil},
+ // LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x38600800, LDRB, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil},
+ // LDRH <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x78400400, LDRH, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRH <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x78400c00, LDRH, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRH <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x79400000, LDRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_2_unsigned}, nil},
+ // LDRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x78600800, LDRH, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil},
+ // LDRSB <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x38c00400, LDRSB, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRSB <Xt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x38800400, LDRSB, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRSB <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x38c00c00, LDRSB, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRSB <Xt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x38800c00, LDRSB, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRSB <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x39c00000, LDRSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_1_unsigned}, nil},
+ // LDRSB <Xt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x39800000, LDRSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_1_unsigned}, nil},
+ // LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x38e00800, LDRSB, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil},
+ // LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x38a00800, LDRSB, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil},
+ // LDRSH <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x78c00400, LDRSH, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRSH <Xt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x78800400, LDRSH, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRSH <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x78c00c00, LDRSH, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRSH <Xt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x78800c00, LDRSH, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x79c00000, LDRSH, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_2_unsigned}, nil},
+ // LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x79800000, LDRSH, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_2_unsigned}, nil},
+ // LDRSH <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x78e00800, LDRSH, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil},
+ // LDRSH <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x78a00800, LDRSH, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil},
+ // LDRSW <Xt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xb8800400, LDRSW, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDRSW <Xt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xb8800c00, LDRSW, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0xb9800000, LDRSW, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_4_unsigned}, nil},
+ // LDRSW <Xt>, <label>
+ {0xff000000, 0x98000000, LDRSW, instArgs{arg_Xt, arg_slabel_imm19_2}, nil},
+ // LDRSW <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xb8a00800, LDRSW, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil},
+ // LDTR <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xb8400800, LDTR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTR <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xf8400800, LDTR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRB <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38400800, LDTRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRH <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78400800, LDTRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRSB <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38c00800, LDTRSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRSB <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38800800, LDTRSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRSH <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78c00800, LDTRSH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRSH <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78800800, LDTRSH, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDTRSW <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xb8800800, LDTRSW, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDUR <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xb8400000, LDUR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDUR <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xf8400000, LDUR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURB <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38400000, LDURB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURH <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78400000, LDURH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURSB <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38c00000, LDURSB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURSB <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38800000, LDURSB, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURSH <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78c00000, LDURSH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURSH <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78800000, LDURSH, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDURSW <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xb8800000, LDURSW, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDXP <Wt>, <Wt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88600000, LDXP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem}, nil},
+ // LDXP <Xt>, <Xt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8600000, LDXP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem}, nil},
+ // LDXR <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88400000, LDXR, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDXR <Xt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8400000, LDXR, instArgs{arg_Xt, arg_Xns_mem}, nil},
+ // LDXRB <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x08400000, LDXRB, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LDXRH <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x48400000, LDXRH, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // LSL <Wd>, <Wn>, #<shift>
+ {0xffc08000, 0x53000000, LSL, instArgs{arg_Wd, arg_Wn, arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr}, lsl_ubfm_32m_bitfield_cond},
+ // LSR <Wd>, <Wn>, #<shift>
+ {0xffc0fc00, 0x53007c00, LSR, instArgs{arg_Wd, arg_Wn, arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr}, nil},
+ // UBFIZ <Wd>, <Wn>, #<lsb>, #<width>
+ {0xffc00000, 0x53000000, UBFIZ, instArgs{arg_Wd, arg_Wn, arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr, arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms}, ubfiz_ubfm_32m_bitfield_cond},
+ // UBFX <Wd>, <Wn>, #<lsb>, #<width>
+ {0xffc00000, 0x53000000, UBFX, instArgs{arg_Wd, arg_Wn, arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr, arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms}, ubfx_ubfm_32m_bitfield_cond},
+ // UXTB <Wd>, <Wn>
+ {0xfffffc00, 0x53001c00, UXTB, instArgs{arg_Wd, arg_Wn}, nil},
+ // UXTH <Wd>, <Wn>
+ {0xfffffc00, 0x53003c00, UXTH, instArgs{arg_Wd, arg_Wn}, nil},
+ // UBFM <Wd>, <Wn>, #<immr>, #<imms>
+ {0xffc00000, 0x53000000, UBFM, instArgs{arg_Wd, arg_Wn, arg_immediate_0_31_immr, arg_immediate_0_31_imms}, nil},
+ // LSL <Xd>, <Xn>, #<shift>
+ {0xffc00000, 0xd3400000, LSL, instArgs{arg_Xd, arg_Xn, arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr}, lsl_ubfm_64m_bitfield_cond},
+ // LSR <Xd>, <Xn>, #<shift>
+ {0xffc0fc00, 0xd340fc00, LSR, instArgs{arg_Xd, arg_Xn, arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr}, nil},
+ // UBFIZ <Xd>, <Xn>, #<lsb>, #<width>
+ {0xffc00000, 0xd3400000, UBFIZ, instArgs{arg_Xd, arg_Xn, arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr, arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms}, ubfiz_ubfm_64m_bitfield_cond},
+ // UBFX <Xd>, <Xn>, #<lsb>, #<width>
+ {0xffc00000, 0xd3400000, UBFX, instArgs{arg_Xd, arg_Xn, arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr, arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms}, ubfx_ubfm_64m_bitfield_cond},
+ // UBFM <Xd>, <Xn>, #<immr>, #<imms>
+ {0xffc00000, 0xd3400000, UBFM, instArgs{arg_Xd, arg_Xn, arg_immediate_0_63_immr, arg_immediate_0_63_imms}, nil},
+ // LSL <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02000, LSL, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // LSLV <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02000, LSLV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // LSL <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02000, LSL, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // LSLV <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02000, LSLV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // LSR <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02400, LSR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // LSRV <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02400, LSRV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // LSR <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02400, LSR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // LSRV <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02400, LSRV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // MUL <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1b007c00, MUL, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // MADD <Wd>, <Wn>, <Wm>, <Wa>
+ {0xffe08000, 0x1b000000, MADD, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_Wa}, nil},
+ // MUL <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9b007c00, MUL, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // MADD <Xd>, <Xn>, <Xm>, <Xa>
+ {0xffe08000, 0x9b000000, MADD, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_Xa}, nil},
+ // MNEG <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1b00fc00, MNEG, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // MSUB <Wd>, <Wn>, <Wm>, <Wa>
+ {0xffe08000, 0x1b008000, MSUB, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_Wa}, nil},
+ // MNEG <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9b00fc00, MNEG, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // MSUB <Xd>, <Xn>, <Xm>, <Xa>
+ {0xffe08000, 0x9b008000, MSUB, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_Xa}, nil},
+ // MOV <Wd|WSP>, #<imm>
+ {0xffc003e0, 0x320003e0, MOV, instArgs{arg_Wds, arg_immediate_bitmask_32_imms_immr}, mov_orr_32_log_imm_cond},
+ // ORR <Wd|WSP>, <Wn>, #<imm>
+ {0xffc00000, 0x32000000, ORR, instArgs{arg_Wds, arg_Wn, arg_immediate_bitmask_32_imms_immr}, nil},
+ // MOV <Xd|SP>, #<imm>
+ {0xff8003e0, 0xb20003e0, MOV, instArgs{arg_Xds, arg_immediate_bitmask_64_N_imms_immr}, mov_orr_64_log_imm_cond},
+ // ORR <Xd|SP>, <Xn>, #<imm>
+ {0xff800000, 0xb2000000, ORR, instArgs{arg_Xds, arg_Xn, arg_immediate_bitmask_64_N_imms_immr}, nil},
+ // MOV <Wd>, #<imm>
+ {0xff800000, 0x12800000, MOV, instArgs{arg_Wd, arg_immediate_shift_32_implicit_inverse_imm16_hw}, mov_movn_32_movewide_cond},
+ // MOVN <Wd>, #<imm>{, LSL #<shift>}
+ {0xff800000, 0x12800000, MOVN, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil},
+ // MOV <Xd>, #<imm>
+ {0xff800000, 0x92800000, MOV, instArgs{arg_Xd, arg_immediate_shift_64_implicit_inverse_imm16_hw}, mov_movn_64_movewide_cond},
+ // MOVN <Xd>, #<imm>{, LSL #<shift>}
+ {0xff800000, 0x92800000, MOVN, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil},
+ // MOV <Wd>, <Wm>
+ {0xffe0ffe0, 0x2a0003e0, MOV, instArgs{arg_Wd, arg_Wm}, nil},
+ // ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x2a000000, ORR, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // MOV <Xd>, <Xm>
+ {0xffe0ffe0, 0xaa0003e0, MOV, instArgs{arg_Xd, arg_Xm}, nil},
+ // ORR <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xaa000000, ORR, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // MOV <Wd>, #<imm>
+ {0xff800000, 0x52800000, MOV, instArgs{arg_Wd, arg_immediate_shift_32_implicit_imm16_hw}, mov_movz_32_movewide_cond},
+ // MOVZ <Wd>, #<imm>{, LSL #<shift>}
+ {0xff800000, 0x52800000, MOVZ, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil},
+ // MOV <Xd>, #<imm>
+ {0xff800000, 0xd2800000, MOV, instArgs{arg_Xd, arg_immediate_shift_64_implicit_imm16_hw}, mov_movz_64_movewide_cond},
+ // MOVZ <Xd>, #<imm>{, LSL #<shift>}
+ {0xff800000, 0xd2800000, MOVZ, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil},
+ // MOVK <Wd>, #<imm>{, LSL #<shift>}
+ {0xff800000, 0x72800000, MOVK, instArgs{arg_Wd, arg_immediate_OptLSL_amount_16_0_16}, nil},
+ // MOVK <Xd>, #<imm>{, LSL #<shift>}
+ {0xff800000, 0xf2800000, MOVK, instArgs{arg_Xd, arg_immediate_OptLSL_amount_16_0_48}, nil},
+ // MRS <Xt>, <systemreg>
+ {0xfff00000, 0xd5300000, MRS, instArgs{arg_Xt, arg_sysreg_o0_op1_CRn_CRm_op2}, nil},
+ // MSR <pstatefield>, #<imm>
+ {0xfff8f01f, 0xd500401f, MSR, instArgs{arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37, arg_immediate_0_15_CRm}, nil},
+ // MSR <systemreg>, <Xt>
+ {0xfff00000, 0xd5100000, MSR, instArgs{arg_sysreg_o0_op1_CRn_CRm_op2, arg_Xt}, nil},
+ // MVN <Wd>, <Wm> {, <shift> #<amount> }
+ {0xff2003e0, 0x2a2003e0, MVN, instArgs{arg_Wd, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x2a200000, ORN, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31}, nil},
+ // MVN <Xd>, <Xm> {, <shift> #<amount> }
+ {0xff2003e0, 0xaa2003e0, MVN, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // ORN <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xaa200000, ORN, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63}, nil},
+ // NEG <Wd>, <Wm> {, <shift> #<amount> }
+ {0xff2003e0, 0x4b0003e0, NEG, instArgs{arg_Wd, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount> }
+ {0xff208000, 0x4b000000, SUB, instArgs{arg_Wd, arg_Wn, arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31}, nil},
+ // NEG <Xd>, <Xm> {, <shift> #<amount> }
+ {0xff2003e0, 0xcb0003e0, NEG, instArgs{arg_Xd, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // SUB <Xd>, <Xn>, <Xm> {, <shift> #<amount> }
+ {0xff200000, 0xcb000000, SUB, instArgs{arg_Xd, arg_Xn, arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63}, nil},
+ // NGC <Wd>, <Wm>
+ {0xffe0ffe0, 0x5a0003e0, NGC, instArgs{arg_Wd, arg_Wm}, nil},
+ // SBC <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x5a000000, SBC, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // NGC <Xd>, <Xm>
+ {0xffe0ffe0, 0xda0003e0, NGC, instArgs{arg_Xd, arg_Xm}, nil},
+ // SBC <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0xda000000, SBC, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // NGCS <Wd>, <Wm>
+ {0xffe0ffe0, 0x7a0003e0, NGCS, instArgs{arg_Wd, arg_Wm}, nil},
+ // SBCS <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x7a000000, SBCS, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // NGCS <Xd>, <Xm>
+ {0xffe0ffe0, 0xfa0003e0, NGCS, instArgs{arg_Xd, arg_Xm}, nil},
+ // SBCS <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0xfa000000, SBCS, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // PRFM <prfop>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0xf9800000, PRFM, instArgs{arg_prfop_Rt, arg_Xns_mem_optional_imm12_8_unsigned}, nil},
+ // PRFM <prfop>, <label>
+ {0xff000000, 0xd8000000, PRFM, instArgs{arg_prfop_Rt, arg_slabel_imm19_2}, nil},
+ // PRFM <prfop>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xf8a00800, PRFM, instArgs{arg_prfop_Rt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil},
+ // PRFUM <prfop>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xf8800000, PRFUM, instArgs{arg_prfop_Rt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // RBIT <Wd>, <Wn>
+ {0xfffffc00, 0x5ac00000, RBIT, instArgs{arg_Wd, arg_Wn}, nil},
+ // RBIT <Xd>, <Xn>
+ {0xfffffc00, 0xdac00000, RBIT, instArgs{arg_Xd, arg_Xn}, nil},
+ // RET {<Xn>}
+ {0xfffffc1f, 0xd65f0000, RET, instArgs{arg_Xn}, nil},
+ // REV <Wd>, <Wn>
+ {0xfffffc00, 0x5ac00800, REV, instArgs{arg_Wd, arg_Wn}, nil},
+ // REV <Xd>, <Xn>
+ {0xfffffc00, 0xdac00c00, REV, instArgs{arg_Xd, arg_Xn}, nil},
+ // REV16 <Wd>, <Wn>
+ {0xfffffc00, 0x5ac00400, REV16, instArgs{arg_Wd, arg_Wn}, nil},
+ // REV16 <Xd>, <Xn>
+ {0xfffffc00, 0xdac00400, REV16, instArgs{arg_Xd, arg_Xn}, nil},
+ // REV32 <Xd>, <Xn>
+ {0xfffffc00, 0xdac00800, REV32, instArgs{arg_Xd, arg_Xn}, nil},
+ // ROR <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02c00, ROR, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // RORV <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac02c00, RORV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // ROR <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02c00, ROR, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // RORV <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac02c00, RORV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // SDIV <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac00c00, SDIV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // SDIV <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac00c00, SDIV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // SMULL <Xd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x9b207c00, SMULL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil},
+ // SMADDL <Xd>, <Wn>, <Wm>, <Xa>
+ {0xffe08000, 0x9b200000, SMADDL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil},
+ // SMNEGL <Xd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x9b20fc00, SMNEGL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil},
+ // SMSUBL <Xd>, <Wn>, <Wm>, <Xa>
+ {0xffe08000, 0x9b208000, SMSUBL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil},
+ // SMULH <Xd>, <Xn>, <Xm>
+ {0xffe08000, 0x9b400000, SMULH, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // STLR <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88808000, STLR, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // STLR <Xt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8808000, STLR, instArgs{arg_Xt, arg_Xns_mem}, nil},
+ // STLRB <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x08808000, STLRB, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // STLRH <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x48808000, STLRH, instArgs{arg_Wt, arg_Xns_mem}, nil},
+ // STLXP <Ws>, <Wt>, <Wt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88208000, STLXP, instArgs{arg_Ws, arg_Wt, arg_Wt2, arg_Xns_mem}, nil},
+ // STLXP <Ws>, <Xt>, <Xt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8208000, STLXP, instArgs{arg_Ws, arg_Xt, arg_Xt2, arg_Xns_mem}, nil},
+ // STLXR <Ws>, <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88008000, STLXR, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
+ // STLXR <Ws>, <Xt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8008000, STLXR, instArgs{arg_Ws, arg_Xt, arg_Xns_mem}, nil},
+ // STLXRB <Ws>, <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x08008000, STLXRB, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
+ // STLXRH <Ws>, <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x48008000, STLXRH, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
+ // STNP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x28000000, STNP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // STNP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_1>}]
+ {0xffc00000, 0xa8000000, STNP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // STP <Wt>, <Wt2>, [<Xn|SP>], #<imm_1>
+ {0xffc00000, 0x28800000, STP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_post_imm7_4_signed}, nil},
+ // STP <Xt>, <Xt2>, [<Xn|SP>], #<imm_3>
+ {0xffc00000, 0xa8800000, STP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_post_imm7_8_signed}, nil},
+ // STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm_1>}]!
+ {0xffc00000, 0x29800000, STP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_wb_imm7_4_signed}, nil},
+ // STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_3>}]!
+ {0xffc00000, 0xa9800000, STP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_wb_imm7_8_signed}, nil},
+ // STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x29000000, STP, instArgs{arg_Wt, arg_Wt2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm_2>}]
+ {0xffc00000, 0xa9000000, STP, instArgs{arg_Xt, arg_Xt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // STR <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xb8000400, STR, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <Xt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xf8000400, STR, instArgs{arg_Xt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xb8000c00, STR, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <Xt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xf8000c00, STR, instArgs{arg_Xt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0xb9000000, STR, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_4_unsigned}, nil},
+ // STR <Xt>, [<Xn|SP>{, #<pimm_1>}]
+ {0xffc00000, 0xf9000000, STR, instArgs{arg_Xt, arg_Xns_mem_optional_imm12_8_unsigned}, nil},
+ // STR <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xb8200800, STR, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil},
+ // STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xf8200800, STR, instArgs{arg_Xt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil},
+ // STRB <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x38000400, STRB, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STRB <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x38000c00, STRB, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STRB <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x39000000, STRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_1_unsigned}, nil},
+ // STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x38200800, STRB, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil},
+ // STRH <Wt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x78000400, STRH, instArgs{arg_Wt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STRH <Wt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x78000c00, STRH, instArgs{arg_Wt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STRH <Wt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x79000000, STRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm12_2_unsigned}, nil},
+ // STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x78200800, STRH, instArgs{arg_Wt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil},
+ // STTR <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xb8000800, STTR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STTR <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xf8000800, STTR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STTRB <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38000800, STTRB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STTRH <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78000800, STTRH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STUR <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xb8000000, STUR, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STUR <Xt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xf8000000, STUR, instArgs{arg_Xt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STURB <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x38000000, STURB, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STURH <Wt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x78000000, STURH, instArgs{arg_Wt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STXP <Ws>, <Wt>, <Wt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88200000, STXP, instArgs{arg_Ws, arg_Wt, arg_Wt2, arg_Xns_mem}, nil},
+ // STXP <Ws>, <Xt>, <Xt2>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8200000, STXP, instArgs{arg_Ws, arg_Xt, arg_Xt2, arg_Xns_mem}, nil},
+ // STXR <Ws>, <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x88000000, STXR, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
+ // STXR <Ws>, <Xt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0xc8000000, STXR, instArgs{arg_Ws, arg_Xt, arg_Xns_mem}, nil},
+ // STXRB <Ws>, <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x08000000, STXRB, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
+ // STXRH <Ws>, <Wt>, [<Xn|SP>{, #0}]
+ {0xffe08000, 0x48000000, STXRH, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
+ // SUB <Wd|WSP>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}
+ {0xffe00000, 0x4b200000, SUB, instArgs{arg_Wds, arg_Wns, arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // SUB <Xd|SP>, <Xn|SP>, <R><m>{, <extend_1> {#<amount>}}
+ {0xffe00000, 0xcb200000, SUB, instArgs{arg_Xds, arg_Xns, arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4}, nil},
+ // SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}
+ {0xff000000, 0x51000000, SUB, instArgs{arg_Wds, arg_Wns, arg_IAddSub}, nil},
+ // SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
+ {0xff000000, 0xd1000000, SUB, instArgs{arg_Xds, arg_Xns, arg_IAddSub}, nil},
+ // SVC #<imm>
+ {0xffe0001f, 0xd4000001, SVC, instArgs{arg_immediate_0_65535_imm16}, nil},
+ // SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
+ {0xfff80000, 0xd5280000, SYSL, instArgs{arg_Xt, arg_immediate_0_7_op1, arg_Cn, arg_Cm, arg_immediate_0_7_op2}, nil},
+ // TBNZ <R><t>, #<imm>, <label>
+ {0x7f000000, 0x37000000, TBNZ, instArgs{arg_Rt_31_1__W_0__X_1, arg_immediate_0_63_b5_b40, arg_slabel_imm14_2}, nil},
+ // TBZ <R><t>, #<imm>, <label>
+ {0x7f000000, 0x36000000, TBZ, instArgs{arg_Rt_31_1__W_0__X_1, arg_immediate_0_63_b5_b40, arg_slabel_imm14_2}, nil},
+ // UDIV <Wd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x1ac00800, UDIV, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
+ // UDIV <Xd>, <Xn>, <Xm>
+ {0xffe0fc00, 0x9ac00800, UDIV, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // UMULL <Xd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x9ba07c00, UMULL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil},
+ // UMADDL <Xd>, <Wn>, <Wm>, <Xa>
+ {0xffe08000, 0x9ba00000, UMADDL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil},
+ // UMNEGL <Xd>, <Wn>, <Wm>
+ {0xffe0fc00, 0x9ba0fc00, UMNEGL, instArgs{arg_Xd, arg_Wn, arg_Wm}, nil},
+ // UMSUBL <Xd>, <Wn>, <Wm>, <Xa>
+ {0xffe08000, 0x9ba08000, UMSUBL, instArgs{arg_Xd, arg_Wn, arg_Wm, arg_Xa}, nil},
+ // UMULH <Xd>, <Xn>, <Xm>
+ {0xffe08000, 0x9bc00000, UMULH, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
+ // ABS <V><d>, <V><n>
+ {0xff3ffc00, 0x5e20b800, ABS, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3}, nil},
+ // ABS <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e20b800, ABS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // ADD <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e208400, ADD, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // ADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e208400, ADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // ADDHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x0e204000, ADDHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // ADDHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x4e204000, ADDHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // ADDP <V><d>, <Vn>.<t>
+ {0xff3ffc00, 0x5e31b800, ADDP, instArgs{arg_Vd_22_2__D_3, arg_Vn_arrangement_size___2D_3}, nil},
+ // ADDP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e20bc00, ADDP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // ADDV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e31b800, ADDV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // AESD <Vd>.16B, <Vn>.16B
+ {0xfffffc00, 0x4e285800, AESD, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil},
+ // AESE <Vd>.16B, <Vn>.16B
+ {0xfffffc00, 0x4e284800, AESE, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil},
+ // AESIMC <Vd>.16B, <Vn>.16B
+ {0xfffffc00, 0x4e287800, AESIMC, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil},
+ // AESMC <Vd>.16B, <Vn>.16B
+ {0xfffffc00, 0x4e286800, AESMC, instArgs{arg_Vd_arrangement_16B, arg_Vn_arrangement_16B}, nil},
+ // AND <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x0e201c00, AND, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // BIC <Vd>.<t>, #<imm8>{, LSL #<amount>}
+ {0xbff8dc00, 0x2f009400, BIC, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil},
+ // BIC <Vd>.<t_1>, #<imm8>{, LSL #<amount>}
+ {0xbff89c00, 0x2f001400, BIC, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil},
+ // BIC <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x0e601c00, BIC, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // BIF <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x2ee01c00, BIF, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // BIT <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x2ea01c00, BIT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // BSL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x2e601c00, BSL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // CLS <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e204800, CLS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // CLZ <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e204800, CLZ, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // CMEQ <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e208c00, CMEQ, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // CMEQ <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e208c00, CMEQ, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // CMEQ <V><d>, <V><n>, #0
+ {0xff3ffc00, 0x5e209800, CMEQ, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil},
+ // CMEQ <Vd>.<t>, <Vn>.<t>, #0
+ {0xbf3ffc00, 0x0e209800, CMEQ, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil},
+ // CMGE <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e203c00, CMGE, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // CMGE <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e203c00, CMGE, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // CMGE <V><d>, <V><n>, #0
+ {0xff3ffc00, 0x7e208800, CMGE, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil},
+ // CMGE <Vd>.<t>, <Vn>.<t>, #0
+ {0xbf3ffc00, 0x2e208800, CMGE, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil},
+ // CMGT <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e203400, CMGT, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // CMGT <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e203400, CMGT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // CMGT <V><d>, <V><n>, #0
+ {0xff3ffc00, 0x5e208800, CMGT, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil},
+ // CMGT <Vd>.<t>, <Vn>.<t>, #0
+ {0xbf3ffc00, 0x0e208800, CMGT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil},
+ // CMHI <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e203400, CMHI, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // CMHI <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e203400, CMHI, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // CMHS <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e203c00, CMHS, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // CMHS <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e203c00, CMHS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // CMLE <V><d>, <V><n>, #0
+ {0xff3ffc00, 0x7e209800, CMLE, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil},
+ // CMLE <Vd>.<t>, <Vn>.<t>, #0
+ {0xbf3ffc00, 0x2e209800, CMLE, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil},
+ // CMLT <V><d>, <V><n>, #0
+ {0xff3ffc00, 0x5e20a800, CMLT, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_immediate_zero}, nil},
+ // CMLT <Vd>.<t>, <Vn>.<t>, #0
+ {0xbf3ffc00, 0x0e20a800, CMLT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_immediate_zero}, nil},
+ // CMTST <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e208c00, CMTST, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // CMTST <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e208c00, CMTST, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // CNT <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e205800, CNT, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01, arg_Vn_arrangement_size_Q___8B_00__16B_01}, nil},
+ // MOV <V><d>, <Vn>.<t_1>[<index>]
+ {0xffe0fc00, 0x5e000400, MOV, instArgs{arg_Vd_16_5__B_1__H_2__S_4__D_8, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1}, nil},
+ // DUP <V><d>, <Vn>.<t_1>[<index>]
+ {0xffe0fc00, 0x5e000400, DUP, instArgs{arg_Vd_16_5__B_1__H_2__S_4__D_8, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1}, nil},
+ // DUP <Vd>.<t>, <Vn>.<ts>[<index>]
+ {0xbfe0fc00, 0x0e000400, DUP, instArgs{arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1}, nil},
+ // DUP <Vd>.<t>, <R><n>
+ {0xbfe0fc00, 0x0e000c00, DUP, instArgs{arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Rn_16_5__W_1__W_2__W_4__X_8}, nil},
+ // EOR <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x2e201c00, EOR, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // EXT <Vd>.<t>, <Vn>.<t>, <Vm>.<t>, #<index>
+ {0xbfe08400, 0x2e000000, EXT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1, arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10}, nil},
+ // FABD <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x7ea0d400, FABD, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FABD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2ea0d400, FABD, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FABS <Sd>, <Sn>
+ {0xfffffc00, 0x1e20c000, FABS, instArgs{arg_Sd, arg_Sn}, nil},
+ // FABS <Dd>, <Dn>
+ {0xfffffc00, 0x1e60c000, FABS, instArgs{arg_Dd, arg_Dn}, nil},
+ // FABS <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea0f800, FABS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FACGE <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x7e20ec00, FACGE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FACGE <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20ec00, FACGE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FACGT <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x7ea0ec00, FACGT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FACGT <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2ea0ec00, FACGT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FADD <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e202800, FADD, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FADD <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e602800, FADD, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20d400, FADD, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FADDP <V><d>, <Vn>.<t>
+ {0xffbffc00, 0x7e30d800, FADDP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil},
+ // FADDP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20d400, FADDP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCCMP <Sn>, <Sm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x1e200400, FCCMP, instArgs{arg_Sn, arg_Sm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // FCCMP <Dn>, <Dm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x1e600400, FCCMP, instArgs{arg_Dn, arg_Dm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // FCCMPE <Sn>, <Sm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x1e200410, FCCMPE, instArgs{arg_Sn, arg_Sm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // FCCMPE <Dn>, <Dm>, #<nzcv>, <cond>
+ {0xffe00c10, 0x1e600410, FCCMPE, instArgs{arg_Dn, arg_Dm, arg_immediate_0_15_nzcv, arg_cond_AllowALNV_Normal}, nil},
+ // FCMEQ <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x5e20e400, FCMEQ, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FCMEQ <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20e400, FCMEQ, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCMEQ <V><d>, <V><n>, #0.0
+ {0xffbffc00, 0x5ea0d800, FCMEQ, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil},
+ // FCMEQ <Vd>.<t>, <Vn>.<t>, #0.0
+ {0xbfbffc00, 0x0ea0d800, FCMEQ, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil},
+ // FCMGE <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x7e20e400, FCMGE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FCMGE <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20e400, FCMGE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCMGE <V><d>, <V><n>, #0.0
+ {0xffbffc00, 0x7ea0c800, FCMGE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil},
+ // FCMGE <Vd>.<t>, <Vn>.<t>, #0.0
+ {0xbfbffc00, 0x2ea0c800, FCMGE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil},
+ // FCMGT <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x7ea0e400, FCMGT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FCMGT <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2ea0e400, FCMGT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCMGT <V><d>, <V><n>, #0.0
+ {0xffbffc00, 0x5ea0c800, FCMGT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil},
+ // FCMGT <Vd>.<t>, <Vn>.<t>, #0.0
+ {0xbfbffc00, 0x0ea0c800, FCMGT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil},
+ // FCMLE <V><d>, <V><n>, #0.0
+ {0xffbffc00, 0x7ea0d800, FCMLE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil},
+ // FCMLE <Vd>.<t>, <Vn>.<t>, #0.0
+ {0xbfbffc00, 0x2ea0d800, FCMLE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil},
+ // FCMLT <V><d>, <V><n>, #0.0
+ {0xffbffc00, 0x5ea0e800, FCMLT, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_immediate_floatzero}, nil},
+ // FCMLT <Vd>.<t>, <Vn>.<t>, #0.0
+ {0xbfbffc00, 0x0ea0e800, FCMLT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_immediate_floatzero}, nil},
+ // FCMP <Sn>, <Sm>
+ {0xffe0fc1f, 0x1e202000, FCMP, instArgs{arg_Sn, arg_Sm}, nil},
+ // FCMP <Sn>, #0.0
+ {0xffe0fc1f, 0x1e202008, FCMP, instArgs{arg_Sn, arg_immediate_floatzero}, nil},
+ // FCMP <Dn>, <Dm>
+ {0xffe0fc1f, 0x1e602000, FCMP, instArgs{arg_Dn, arg_Dm}, nil},
+ // FCMP <Dn>, #0.0
+ {0xffe0fc1f, 0x1e602008, FCMP, instArgs{arg_Dn, arg_immediate_floatzero}, nil},
+ // FCMPE <Sn>, <Sm>
+ {0xffe0fc1f, 0x1e202010, FCMPE, instArgs{arg_Sn, arg_Sm}, nil},
+ // FCMPE <Sn>, #0.0
+ {0xffe0fc1f, 0x1e202018, FCMPE, instArgs{arg_Sn, arg_immediate_floatzero}, nil},
+ // FCMPE <Dn>, <Dm>
+ {0xffe0fc1f, 0x1e602010, FCMPE, instArgs{arg_Dn, arg_Dm}, nil},
+ // FCMPE <Dn>, #0.0
+ {0xffe0fc1f, 0x1e602018, FCMPE, instArgs{arg_Dn, arg_immediate_floatzero}, nil},
+ // FCSEL <Sd>, <Sn>, <Sm>, <cond>
+ {0xffe00c00, 0x1e200c00, FCSEL, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_cond_AllowALNV_Normal}, nil},
+ // FCSEL <Dd>, <Dn>, <Dm>, <cond>
+ {0xffe00c00, 0x1e600c00, FCSEL, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_cond_AllowALNV_Normal}, nil},
+ // FCVT <Sd>, <Hn>
+ {0xfffffc00, 0x1ee24000, FCVT, instArgs{arg_Sd, arg_Hn}, nil},
+ // FCVT <Dd>, <Hn>
+ {0xfffffc00, 0x1ee2c000, FCVT, instArgs{arg_Dd, arg_Hn}, nil},
+ // FCVT <Hd>, <Sn>
+ {0xfffffc00, 0x1e23c000, FCVT, instArgs{arg_Hd, arg_Sn}, nil},
+ // FCVT <Dd>, <Sn>
+ {0xfffffc00, 0x1e22c000, FCVT, instArgs{arg_Dd, arg_Sn}, nil},
+ // FCVT <Hd>, <Dn>
+ {0xfffffc00, 0x1e63c000, FCVT, instArgs{arg_Hd, arg_Dn}, nil},
+ // FCVT <Sd>, <Dn>
+ {0xfffffc00, 0x1e624000, FCVT, instArgs{arg_Sd, arg_Dn}, nil},
+ // FCVTAS <Wd>, <Sn>
+ {0xfffffc00, 0x1e240000, FCVTAS, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTAS <Xd>, <Sn>
+ {0xfffffc00, 0x9e240000, FCVTAS, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTAS <Wd>, <Dn>
+ {0xfffffc00, 0x1e640000, FCVTAS, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTAS <Xd>, <Dn>
+ {0xfffffc00, 0x9e640000, FCVTAS, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTAS <V><d>, <V><n>
+ {0xffbffc00, 0x5e21c800, FCVTAS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTAS <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0e21c800, FCVTAS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTAU <Wd>, <Sn>
+ {0xfffffc00, 0x1e250000, FCVTAU, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTAU <Xd>, <Sn>
+ {0xfffffc00, 0x9e250000, FCVTAU, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTAU <Wd>, <Dn>
+ {0xfffffc00, 0x1e650000, FCVTAU, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTAU <Xd>, <Dn>
+ {0xfffffc00, 0x9e650000, FCVTAU, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTAU <V><d>, <V><n>
+ {0xffbffc00, 0x7e21c800, FCVTAU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTAU <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2e21c800, FCVTAU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTL <Vd>.<ta>, <Vn>.<tb>
+ {0xffbffc00, 0x0e217800, FCVTL, instArgs{arg_Vd_arrangement_sz___4S_0__2D_1, arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11}, nil},
+ // FCVTL2 <Vd>.<ta>, <Vn>.<tb>
+ {0xffbffc00, 0x4e217800, FCVTL2, instArgs{arg_Vd_arrangement_sz___4S_0__2D_1, arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11}, nil},
+ // FCVTMS <Wd>, <Sn>
+ {0xfffffc00, 0x1e300000, FCVTMS, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTMS <Xd>, <Sn>
+ {0xfffffc00, 0x9e300000, FCVTMS, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTMS <Wd>, <Dn>
+ {0xfffffc00, 0x1e700000, FCVTMS, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTMS <Xd>, <Dn>
+ {0xfffffc00, 0x9e700000, FCVTMS, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTMS <V><d>, <V><n>
+ {0xffbffc00, 0x5e21b800, FCVTMS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTMS <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0e21b800, FCVTMS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTMU <Wd>, <Sn>
+ {0xfffffc00, 0x1e310000, FCVTMU, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTMU <Xd>, <Sn>
+ {0xfffffc00, 0x9e310000, FCVTMU, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTMU <Wd>, <Dn>
+ {0xfffffc00, 0x1e710000, FCVTMU, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTMU <Xd>, <Dn>
+ {0xfffffc00, 0x9e710000, FCVTMU, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTMU <V><d>, <V><n>
+ {0xffbffc00, 0x7e21b800, FCVTMU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTMU <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2e21b800, FCVTMU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTN <Vd>.<tb>, <Vn>.<ta>
+ {0xffbffc00, 0x0e216800, FCVTN, instArgs{arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11, arg_Vn_arrangement_sz___4S_0__2D_1}, nil},
+ // FCVTN2 <Vd>.<tb>, <Vn>.<ta>
+ {0xffbffc00, 0x4e216800, FCVTN2, instArgs{arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11, arg_Vn_arrangement_sz___4S_0__2D_1}, nil},
+ // FCVTNS <Wd>, <Sn>
+ {0xfffffc00, 0x1e200000, FCVTNS, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTNS <Xd>, <Sn>
+ {0xfffffc00, 0x9e200000, FCVTNS, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTNS <Wd>, <Dn>
+ {0xfffffc00, 0x1e600000, FCVTNS, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTNS <Xd>, <Dn>
+ {0xfffffc00, 0x9e600000, FCVTNS, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTNS <V><d>, <V><n>
+ {0xffbffc00, 0x5e21a800, FCVTNS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTNS <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0e21a800, FCVTNS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTNU <Wd>, <Sn>
+ {0xfffffc00, 0x1e210000, FCVTNU, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTNU <Xd>, <Sn>
+ {0xfffffc00, 0x9e210000, FCVTNU, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTNU <Wd>, <Dn>
+ {0xfffffc00, 0x1e610000, FCVTNU, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTNU <Xd>, <Dn>
+ {0xfffffc00, 0x9e610000, FCVTNU, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTNU <V><d>, <V><n>
+ {0xffbffc00, 0x7e21a800, FCVTNU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTNU <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2e21a800, FCVTNU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTPS <Wd>, <Sn>
+ {0xfffffc00, 0x1e280000, FCVTPS, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTPS <Xd>, <Sn>
+ {0xfffffc00, 0x9e280000, FCVTPS, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTPS <Wd>, <Dn>
+ {0xfffffc00, 0x1e680000, FCVTPS, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTPS <Xd>, <Dn>
+ {0xfffffc00, 0x9e680000, FCVTPS, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTPS <V><d>, <V><n>
+ {0xffbffc00, 0x5ea1a800, FCVTPS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTPS <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea1a800, FCVTPS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTPU <Wd>, <Sn>
+ {0xfffffc00, 0x1e290000, FCVTPU, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTPU <Xd>, <Sn>
+ {0xfffffc00, 0x9e290000, FCVTPU, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTPU <Wd>, <Dn>
+ {0xfffffc00, 0x1e690000, FCVTPU, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTPU <Xd>, <Dn>
+ {0xfffffc00, 0x9e690000, FCVTPU, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTPU <V><d>, <V><n>
+ {0xffbffc00, 0x7ea1a800, FCVTPU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTPU <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea1a800, FCVTPU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTXN <V><d>, <V><n>
+ {0xffbffc00, 0x7e216800, FCVTXN, instArgs{arg_Vd_22_1__S_1, arg_Vn_22_1__D_1}, nil},
+ // FCVTXN <Vd>.<tb>, <Vn>.<ta>
+ {0xffbffc00, 0x2e216800, FCVTXN, instArgs{arg_Vd_arrangement_sz_Q___2S_10__4S_11, arg_Vn_arrangement_sz___2D_1}, nil},
+ // FCVTXN2 <Vd>.<tb>, <Vn>.<ta>
+ {0xffbffc00, 0x6e216800, FCVTXN2, instArgs{arg_Vd_arrangement_sz_Q___2S_10__4S_11, arg_Vn_arrangement_sz___2D_1}, nil},
+ // FCVTZS <Wd>, <Sn>, #<fbits>
+ {0xffff0000, 0x1e180000, FCVTZS, instArgs{arg_Wd, arg_Sn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // FCVTZS <Xd>, <Sn>, #<fbits>
+ {0xffff0000, 0x9e180000, FCVTZS, instArgs{arg_Xd, arg_Sn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // FCVTZS <Wd>, <Dn>, #<fbits>
+ {0xffff0000, 0x1e580000, FCVTZS, instArgs{arg_Wd, arg_Dn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // FCVTZS <Xd>, <Dn>, #<fbits>
+ {0xffff0000, 0x9e580000, FCVTZS, instArgs{arg_Xd, arg_Dn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // FCVTZS <Wd>, <Sn>
+ {0xfffffc00, 0x1e380000, FCVTZS, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTZS <Xd>, <Sn>
+ {0xfffffc00, 0x9e380000, FCVTZS, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTZS <Wd>, <Dn>
+ {0xfffffc00, 0x1e780000, FCVTZS, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTZS <Xd>, <Dn>
+ {0xfffffc00, 0x9e780000, FCVTZS, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTZS <V><d>, <V><n>, #<fbits>
+ {0xff80fc00, 0x5f00fc00, FCVTZS, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzs_asisdshf_c_cond},
+ // FCVTZS <Vd>.<t>, <Vn>.<t>, #<fbits>
+ {0xbf80fc00, 0x0f00fc00, FCVTZS, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzs_asimdshf_c_cond},
+ // FCVTZS <V><d>, <V><n>
+ {0xffbffc00, 0x5ea1b800, FCVTZS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTZS <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea1b800, FCVTZS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FCVTZU <Wd>, <Sn>, #<fbits>
+ {0xffff0000, 0x1e190000, FCVTZU, instArgs{arg_Wd, arg_Sn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // FCVTZU <Xd>, <Sn>, #<fbits>
+ {0xffff0000, 0x9e190000, FCVTZU, instArgs{arg_Xd, arg_Sn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // FCVTZU <Wd>, <Dn>, #<fbits>
+ {0xffff0000, 0x1e590000, FCVTZU, instArgs{arg_Wd, arg_Dn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // FCVTZU <Xd>, <Dn>, #<fbits>
+ {0xffff0000, 0x9e590000, FCVTZU, instArgs{arg_Xd, arg_Dn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // FCVTZU <Wd>, <Sn>
+ {0xfffffc00, 0x1e390000, FCVTZU, instArgs{arg_Wd, arg_Sn}, nil},
+ // FCVTZU <Xd>, <Sn>
+ {0xfffffc00, 0x9e390000, FCVTZU, instArgs{arg_Xd, arg_Sn}, nil},
+ // FCVTZU <Wd>, <Dn>
+ {0xfffffc00, 0x1e790000, FCVTZU, instArgs{arg_Wd, arg_Dn}, nil},
+ // FCVTZU <Xd>, <Dn>
+ {0xfffffc00, 0x9e790000, FCVTZU, instArgs{arg_Xd, arg_Dn}, nil},
+ // FCVTZU <V><d>, <V><n>, #<fbits>
+ {0xff80fc00, 0x7f00fc00, FCVTZU, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzu_asisdshf_c_cond},
+ // FCVTZU <Vd>.<t>, <Vn>.<t>, #<fbits>
+ {0xbf80fc00, 0x2f00fc00, FCVTZU, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, fcvtzu_asimdshf_c_cond},
+ // FCVTZU <V><d>, <V><n>
+ {0xffbffc00, 0x7ea1b800, FCVTZU, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FCVTZU <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea1b800, FCVTZU, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FDIV <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e201800, FDIV, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FDIV <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e601800, FDIV, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FDIV <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20fc00, FDIV, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMADD <Sd>, <Sn>, <Sm>, <Sa>
+ {0xffe08000, 0x1f000000, FMADD, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil},
+ // FMADD <Dd>, <Dn>, <Dm>, <Da>
+ {0xffe08000, 0x1f400000, FMADD, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil},
+ // FMAX <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e204800, FMAX, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FMAX <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e604800, FMAX, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FMAX <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20f400, FMAX, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMAXNM <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e206800, FMAXNM, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FMAXNM <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e606800, FMAXNM, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FMAXNM <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20c400, FMAXNM, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMAXNMP <V><d>, <Vn>.<t>
+ {0xffbffc00, 0x7e30c800, FMAXNMP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil},
+ // FMAXNMP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20c400, FMAXNMP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMAXNMV <V><d>, <Vn>.<t>
+ {0xbfbffc00, 0x2e30c800, FMAXNMV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil},
+ // FMAXP <V><d>, <Vn>.<t>
+ {0xffbffc00, 0x7e30f800, FMAXP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil},
+ // FMAXP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20f400, FMAXP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMAXV <V><d>, <Vn>.<t>
+ {0xbfbffc00, 0x2e30f800, FMAXV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil},
+ // FMIN <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e205800, FMIN, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FMIN <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e605800, FMIN, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FMIN <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0ea0f400, FMIN, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMINNM <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e207800, FMINNM, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FMINNM <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e607800, FMINNM, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FMINNM <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0ea0c400, FMINNM, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMINNMP <V><d>, <Vn>.<t>
+ {0xffbffc00, 0x7eb0c800, FMINNMP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil},
+ // FMINNMP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2ea0c400, FMINNMP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMINNMV <V><d>, <Vn>.<t>
+ {0xbfbffc00, 0x2eb0c800, FMINNMV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil},
+ // FMINP <V><d>, <Vn>.<t>
+ {0xffbffc00, 0x7eb0f800, FMINP, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_arrangement_sz___2S_0__2D_1}, nil},
+ // FMINP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2ea0f400, FMINP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMINV <V><d>, <Vn>.<t>
+ {0xbfbffc00, 0x2eb0f800, FMINV, instArgs{arg_Vd_22_1__S_0, arg_Vn_arrangement_Q_sz___4S_10}, nil},
+ // FMLA <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff80f400, 0x5f801000, FMLA, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMLA <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf80f400, 0x0f801000, FMLA, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMLA <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20cc00, FMLA, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMLS <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff80f400, 0x5f805000, FMLS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMLS <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf80f400, 0x0f805000, FMLS, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMLS <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0ea0cc00, FMLS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMOV <Sd>, <Wn>
+ {0xfffffc00, 0x1e270000, FMOV, instArgs{arg_Sd, arg_Wn}, nil},
+ // FMOV <Wd>, <Sn>
+ {0xfffffc00, 0x1e260000, FMOV, instArgs{arg_Wd, arg_Sn}, nil},
+ // FMOV <Dd>, <Xn>
+ {0xfffffc00, 0x9e670000, FMOV, instArgs{arg_Dd, arg_Xn}, nil},
+ // FMOV <Vd>.D[1], <Xn>
+ {0xfffffc00, 0x9eaf0000, FMOV, instArgs{arg_Vd_arrangement_D_index__1, arg_Xn}, nil},
+ // FMOV <Xd>, <Dn>
+ {0xfffffc00, 0x9e660000, FMOV, instArgs{arg_Xd, arg_Dn}, nil},
+ // FMOV <Xd>, <Vn>.D[1]
+ {0xfffffc00, 0x9eae0000, FMOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__1}, nil},
+ // FMOV <Sd>, <Sn>
+ {0xfffffc00, 0x1e204000, FMOV, instArgs{arg_Sd, arg_Sn}, nil},
+ // FMOV <Dd>, <Dn>
+ {0xfffffc00, 0x1e604000, FMOV, instArgs{arg_Dd, arg_Dn}, nil},
+ // FMOV <Sd>, #<imm>
+ {0xffe01fe0, 0x1e201000, FMOV, instArgs{arg_Sd, arg_immediate_exp_3_pre_4_imm8}, nil},
+ // FMOV <Dd>, #<imm>
+ {0xffe01fe0, 0x1e601000, FMOV, instArgs{arg_Dd, arg_immediate_exp_3_pre_4_imm8}, nil},
+ // FMOV <Vd>.<t>, #<imm>
+ {0xbff8fc00, 0x0f00f400, FMOV, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h}, nil},
+ // FMOV <Vd>.2D, #<imm>
+ {0xfff8fc00, 0x6f00f400, FMOV, instArgs{arg_Vd_arrangement_2D, arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h}, nil},
+ // FMSUB <Sd>, <Sn>, <Sm>, <Sa>
+ {0xffe08000, 0x1f008000, FMSUB, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil},
+ // FMSUB <Dd>, <Dn>, <Dm>, <Da>
+ {0xffe08000, 0x1f408000, FMSUB, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil},
+ // FMUL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff80f400, 0x5f809000, FMUL, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf80f400, 0x0f809000, FMUL, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMUL <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e200800, FMUL, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FMUL <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e600800, FMUL, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x2e20dc00, FMUL, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMULX <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x5e20dc00, FMULX, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FMULX <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20dc00, FMULX, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FMULX <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff80f400, 0x7f809000, FMULX, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FMULX <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf80f400, 0x2f809000, FMULX, instArgs{arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11, arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1}, nil},
+ // FNEG <Sd>, <Sn>
+ {0xfffffc00, 0x1e214000, FNEG, instArgs{arg_Sd, arg_Sn}, nil},
+ // FNEG <Dd>, <Dn>
+ {0xfffffc00, 0x1e614000, FNEG, instArgs{arg_Dd, arg_Dn}, nil},
+ // FNEG <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea0f800, FNEG, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FNMADD <Sd>, <Sn>, <Sm>, <Sa>
+ {0xffe08000, 0x1f200000, FNMADD, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil},
+ // FNMADD <Dd>, <Dn>, <Dm>, <Da>
+ {0xffe08000, 0x1f600000, FNMADD, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil},
+ // FNMSUB <Sd>, <Sn>, <Sm>, <Sa>
+ {0xffe08000, 0x1f208000, FNMSUB, instArgs{arg_Sd, arg_Sn, arg_Sm, arg_Sa}, nil},
+ // FNMSUB <Dd>, <Dn>, <Dm>, <Da>
+ {0xffe08000, 0x1f608000, FNMSUB, instArgs{arg_Dd, arg_Dn, arg_Dm, arg_Da}, nil},
+ // FNMUL <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e208800, FNMUL, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FNMUL <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e608800, FNMUL, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FRECPE <V><d>, <V><n>
+ {0xffbffc00, 0x5ea1d800, FRECPE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FRECPE <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea1d800, FRECPE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRECPS <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x5e20fc00, FRECPS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FRECPS <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0e20fc00, FRECPS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRECPX <V><d>, <V><n>
+ {0xffbffc00, 0x5ea1f800, FRECPX, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FRINTA <Sd>, <Sn>
+ {0xfffffc00, 0x1e264000, FRINTA, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTA <Dd>, <Dn>
+ {0xfffffc00, 0x1e664000, FRINTA, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTA <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2e218800, FRINTA, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRINTI <Sd>, <Sn>
+ {0xfffffc00, 0x1e27c000, FRINTI, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTI <Dd>, <Dn>
+ {0xfffffc00, 0x1e67c000, FRINTI, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTI <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea19800, FRINTI, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRINTM <Sd>, <Sn>
+ {0xfffffc00, 0x1e254000, FRINTM, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTM <Dd>, <Dn>
+ {0xfffffc00, 0x1e654000, FRINTM, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTM <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0e219800, FRINTM, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRINTN <Sd>, <Sn>
+ {0xfffffc00, 0x1e244000, FRINTN, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTN <Dd>, <Dn>
+ {0xfffffc00, 0x1e644000, FRINTN, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTN <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0e218800, FRINTN, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRINTP <Sd>, <Sn>
+ {0xfffffc00, 0x1e24c000, FRINTP, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTP <Dd>, <Dn>
+ {0xfffffc00, 0x1e64c000, FRINTP, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTP <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea18800, FRINTP, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRINTX <Sd>, <Sn>
+ {0xfffffc00, 0x1e274000, FRINTX, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTX <Dd>, <Dn>
+ {0xfffffc00, 0x1e674000, FRINTX, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTX <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2e219800, FRINTX, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRINTZ <Sd>, <Sn>
+ {0xfffffc00, 0x1e25c000, FRINTZ, instArgs{arg_Sd, arg_Sn}, nil},
+ // FRINTZ <Dd>, <Dn>
+ {0xfffffc00, 0x1e65c000, FRINTZ, instArgs{arg_Dd, arg_Dn}, nil},
+ // FRINTZ <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea19800, FRINTZ, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRSQRTE <V><d>, <V><n>
+ {0xffbffc00, 0x7ea1d800, FRSQRTE, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // FRSQRTE <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea1d800, FRSQRTE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FRSQRTS <V><d>, <V><n>, <V><m>
+ {0xffa0fc00, 0x5ea0fc00, FRSQRTS, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1, arg_Vm_22_1__S_0__D_1}, nil},
+ // FRSQRTS <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0ea0fc00, FRSQRTS, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FSQRT <Sd>, <Sn>
+ {0xfffffc00, 0x1e21c000, FSQRT, instArgs{arg_Sd, arg_Sn}, nil},
+ // FSQRT <Dd>, <Dn>
+ {0xfffffc00, 0x1e61c000, FSQRT, instArgs{arg_Dd, arg_Dn}, nil},
+ // FSQRT <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea1f800, FSQRT, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // FSUB <Sd>, <Sn>, <Sm>
+ {0xffe0fc00, 0x1e203800, FSUB, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
+ // FSUB <Dd>, <Dn>, <Dm>
+ {0xffe0fc00, 0x1e603800, FSUB, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
+ // FSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfa0fc00, 0x0ea0d400, FSUB, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // MOV <Vd>.<ts>[<index1>], <Vn>.<ts>[<index2>]
+ {0xffe08400, 0x6e000400, MOV, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1}, nil},
+ // INS <Vd>.<ts>[<index1>], <Vn>.<ts>[<index2>]
+ {0xffe08400, 0x6e000400, INS, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1}, nil},
+ // MOV <Vd>.<ts>[<index>], <R><n>
+ {0xffe0fc00, 0x4e001c00, MOV, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Rn_16_5__W_1__W_2__W_4__X_8}, nil},
+ // INS <Vd>.<ts>[<index>], <R><n>
+ {0xffe0fc00, 0x4e001c00, INS, instArgs{arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1, arg_Rn_16_5__W_1__W_2__W_4__X_8}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c407000, LD1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c40a000, LD1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c406000, LD1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c402000, LD1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0cdf7000, LD1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__8_0__16_1}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc07000, LD1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<imm_1>
+ {0xbffff000, 0x0cdfa000, LD1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc0a000, LD1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<imm_2>
+ {0xbffff000, 0x0cdf6000, LD1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc06000, LD1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<imm_3>
+ {0xbffff000, 0x0cdf2000, LD1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil},
+ // LD1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc02000, LD1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d400000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d404000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d408000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d408400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // LD1 <Vt>.B[<index>], [<Xn|SP>], #1
+ {0xbfffe000, 0x0ddf0000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_1}, nil},
+ // LD1 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0dc00000, LD1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.H[<index_2>], [<Xn|SP>], #2
+ {0xbfffe400, 0x0ddf4000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil},
+ // LD1 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0dc04000, LD1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.S[<index_3>], [<Xn|SP>], #4
+ {0xbfffec00, 0x0ddf8000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_4}, nil},
+ // LD1 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0dc08000, LD1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // LD1 <Vt>.D[<index_1>], [<Xn|SP>], #8
+ {0xbffffc00, 0x0ddf8400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_8}, nil},
+ // LD1 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0dc08400, LD1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // LD1R <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0d40c000, LD1R, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD1R <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0ddfc000, LD1R, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__1_0__2_1__4_2__8_3}, nil},
+ // LD1R <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0dc0c000, LD1R, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD2 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c408000, LD2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil},
+ // LD2 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0cdf8000, LD2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil},
+ // LD2 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc08000, LD2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD2 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d600000, LD2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD2 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d604000, LD2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD2 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d608000, LD2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // LD2 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d608400, LD2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // LD2 <Vt>.B[<index>], [<Xn|SP>], #2
+ {0xbfffe000, 0x0dff0000, LD2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil},
+ // LD2 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0de00000, LD2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD2 <Vt>.H[<index_2>], [<Xn|SP>], #4
+ {0xbfffe400, 0x0dff4000, LD2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil},
+ // LD2 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0de04000, LD2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD2 <Vt>.S[<index_3>], [<Xn|SP>], #8
+ {0xbfffec00, 0x0dff8000, LD2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_8}, nil},
+ // LD2 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0de08000, LD2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // LD2 <Vt>.D[<index_1>], [<Xn|SP>], #16
+ {0xbffffc00, 0x0dff8400, LD2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_16}, nil},
+ // LD2 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0de08400, LD2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // LD2R <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0d60c000, LD2R, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD2R <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0dffc000, LD2R, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__2_0__4_1__8_2__16_3}, nil},
+ // LD2R <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0de0c000, LD2R, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD3 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c404000, LD3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil},
+ // LD3 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0cdf4000, LD3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil},
+ // LD3 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc04000, LD3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD3 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d402000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD3 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d406000, LD3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD3 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d40a000, LD3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // LD3 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d40a400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // LD3 <Vt>.B[<index>], [<Xn|SP>], #3
+ {0xbfffe000, 0x0ddf2000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_3}, nil},
+ // LD3 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0dc02000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD3 <Vt>.H[<index_2>], [<Xn|SP>], #6
+ {0xbfffe400, 0x0ddf6000, LD3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_6}, nil},
+ // LD3 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0dc06000, LD3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD3 <Vt>.S[<index_3>], [<Xn|SP>], #12
+ {0xbfffec00, 0x0ddfa000, LD3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_12}, nil},
+ // LD3 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0dc0a000, LD3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // LD3 <Vt>.D[<index_1>], [<Xn|SP>], #24
+ {0xbffffc00, 0x0ddfa400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_24}, nil},
+ // LD3 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0dc0a400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // LD3R <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0d40e000, LD3R, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD3R <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0ddfe000, LD3R, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__3_0__6_1__12_2__24_3}, nil},
+ // LD3R <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0dc0e000, LD3R, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD4 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c400000, LD4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil},
+ // LD4 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0cdf0000, LD4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil},
+ // LD4 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0cc00000, LD4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LD4 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d602000, LD4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD4 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d606000, LD4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // LD4 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d60a000, LD4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // LD4 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d60a400, LD4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // LD4 <Vt>.B[<index>], [<Xn|SP>], #4
+ {0xbfffe000, 0x0dff2000, LD4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil},
+ // LD4 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0de02000, LD4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD4 <Vt>.H[<index_2>], [<Xn|SP>], #8
+ {0xbfffe400, 0x0dff6000, LD4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_8}, nil},
+ // LD4 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0de06000, LD4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // LD4 <Vt>.S[<index_3>], [<Xn|SP>], #16
+ {0xbfffec00, 0x0dffa000, LD4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_16}, nil},
+ // LD4 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0de0a000, LD4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // LD4 <Vt>.D[<index_1>], [<Xn|SP>], #32
+ {0xbffffc00, 0x0dffa400, LD4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_32}, nil},
+ // LD4 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0de0a400, LD4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // LD4R <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0d60e000, LD4R, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // LD4R <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0dffe000, LD4R, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_size__4_0__8_1__16_2__32_3}, nil},
+ // LD4R <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0de0e000, LD4R, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // LDNP <St>, <St2>, [<Xn|SP>{, #<imm_2>}]
+ {0xffc00000, 0x2c400000, LDNP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // LDNP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x6c400000, LDNP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // LDNP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_1>}]
+ {0xffc00000, 0xac400000, LDNP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil},
+ // LDP <St>, <St2>, [<Xn|SP>], #<imm_5>
+ {0xffc00000, 0x2cc00000, LDP, instArgs{arg_St, arg_St2, arg_Xns_mem_post_imm7_4_signed}, nil},
+ // LDP <Dt>, <Dt2>, [<Xn|SP>], #<imm_1>
+ {0xffc00000, 0x6cc00000, LDP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_post_imm7_8_signed}, nil},
+ // LDP <Qt>, <Qt2>, [<Xn|SP>], #<imm_3>
+ {0xffc00000, 0xacc00000, LDP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_post_imm7_16_signed}, nil},
+ // LDP <St>, <St2>, [<Xn|SP>{, #<imm_5>}]!
+ {0xffc00000, 0x2dc00000, LDP, instArgs{arg_St, arg_St2, arg_Xns_mem_wb_imm7_4_signed}, nil},
+ // LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm_1>}]!
+ {0xffc00000, 0x6dc00000, LDP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_wb_imm7_8_signed}, nil},
+ // LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_3>}]!
+ {0xffc00000, 0xadc00000, LDP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_wb_imm7_16_signed}, nil},
+ // LDP <St>, <St2>, [<Xn|SP>{, #<imm_4>}]
+ {0xffc00000, 0x2d400000, LDP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x6d400000, LDP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_2>}]
+ {0xffc00000, 0xad400000, LDP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil},
+ // LDR <Bt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x3c400400, LDR, instArgs{arg_Bt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <Ht>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x7c400400, LDR, instArgs{arg_Ht, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <St>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xbc400400, LDR, instArgs{arg_St, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <Dt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xfc400400, LDR, instArgs{arg_Dt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <Qt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x3cc00400, LDR, instArgs{arg_Qt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // LDR <Bt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x3c400c00, LDR, instArgs{arg_Bt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <Ht>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x7c400c00, LDR, instArgs{arg_Ht, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <St>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xbc400c00, LDR, instArgs{arg_St, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <Dt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xfc400c00, LDR, instArgs{arg_Dt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <Qt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x3cc00c00, LDR, instArgs{arg_Qt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // LDR <Bt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x3d400000, LDR, instArgs{arg_Bt, arg_Xns_mem_optional_imm12_1_unsigned}, nil},
+ // LDR <Ht>, [<Xn|SP>{, #<pimm_2>}]
+ {0xffc00000, 0x7d400000, LDR, instArgs{arg_Ht, arg_Xns_mem_optional_imm12_2_unsigned}, nil},
+ // LDR <St>, [<Xn|SP>{, #<pimm_4>}]
+ {0xffc00000, 0xbd400000, LDR, instArgs{arg_St, arg_Xns_mem_optional_imm12_4_unsigned}, nil},
+ // LDR <Dt>, [<Xn|SP>{, #<pimm_1>}]
+ {0xffc00000, 0xfd400000, LDR, instArgs{arg_Dt, arg_Xns_mem_optional_imm12_8_unsigned}, nil},
+ // LDR <Qt>, [<Xn|SP>{, #<pimm_3>}]
+ {0xffc00000, 0x3dc00000, LDR, instArgs{arg_Qt, arg_Xns_mem_optional_imm12_16_unsigned}, nil},
+ // LDR <St>, <label>
+ {0xff000000, 0x1c000000, LDR, instArgs{arg_St, arg_slabel_imm19_2}, nil},
+ // LDR <Dt>, <label>
+ {0xff000000, 0x5c000000, LDR, instArgs{arg_Dt, arg_slabel_imm19_2}, nil},
+ // LDR <Qt>, <label>
+ {0xff000000, 0x9c000000, LDR, instArgs{arg_Qt, arg_slabel_imm19_2}, nil},
+ // LDR <Bt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x3c600800, LDR, instArgs{arg_Bt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil},
+ // LDR <Ht>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x7c600800, LDR, instArgs{arg_Ht, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil},
+ // LDR <St>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xbc600800, LDR, instArgs{arg_St, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil},
+ // LDR <Dt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xfc600800, LDR, instArgs{arg_Dt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil},
+ // LDR <Qt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x3ce00800, LDR, instArgs{arg_Qt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1}, nil},
+ // LDUR <Bt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x3c400000, LDUR, instArgs{arg_Bt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDUR <Ht>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x7c400000, LDUR, instArgs{arg_Ht, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDUR <St>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xbc400000, LDUR, instArgs{arg_St, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDUR <Dt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xfc400000, LDUR, instArgs{arg_Dt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // LDUR <Qt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x3cc00000, LDUR, instArgs{arg_Qt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // MLA <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf00f400, 0x2f000000, MLA, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // MLA <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e209400, MLA, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // MLS <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf00f400, 0x2f004000, MLS, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // MLS <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e209400, MLS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // MOV <Wd>, <Vn>.S[<index>]
+ {0xffe0fc00, 0x0e003c00, MOV, instArgs{arg_Wd, arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1}, mov_umov_asimdins_w_w_cond},
+ // UMOV <Wd>, <Vn>.<ts>[<index>]
+ {0xffe0fc00, 0x0e003c00, UMOV, instArgs{arg_Wd, arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1}, nil},
+ // MOV <Xd>, <Vn>.D[<index_1>]
+ {0xffe0fc00, 0x4e003c00, MOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__imm5_1}, mov_umov_asimdins_x_x_cond},
+ // UMOV <Xd>, <Vn>.<ts_1>[<index_1>]
+ {0xffe0fc00, 0x4e003c00, UMOV, instArgs{arg_Xd, arg_Vn_arrangement_imm5___D_8_index__imm5_1}, nil},
+ // MOV <Vd>.<t>, <Vn>.<t>
+ {0xbfe0fc00, 0x0ea01c00, MOV, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, mov_orr_asimdsame_only_cond},
+ // ORR <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x0ea01c00, ORR, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // MOVI <Vd>.<t_2>, #<imm8>{, LSL #0}
+ {0xbff8fc00, 0x0f00e400, MOVI, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h}, nil},
+ // MOVI <Vd>.<t>, #<imm8>{, LSL #<amount>}
+ {0xbff8dc00, 0x0f008400, MOVI, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil},
+ // MOVI <Vd>.<t_1>, #<imm8>{, LSL #<amount>}
+ {0xbff89c00, 0x0f000400, MOVI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil},
+ // MOVI <Vd>.<t_1>, #<imm8>, MSL #<amount>
+ {0xbff8ec00, 0x0f00c400, MOVI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1}, nil},
+ // MOVI <Dd>, #<imm>
+ {0xfff8fc00, 0x2f00e400, MOVI, instArgs{arg_Dd, arg_immediate_8x8_a_b_c_d_e_f_g_h}, nil},
+ // MOVI <Vd>.2D, #<imm>
+ {0xfff8fc00, 0x6f00e400, MOVI, instArgs{arg_Vd_arrangement_2D, arg_immediate_8x8_a_b_c_d_e_f_g_h}, nil},
+ // MUL <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf00f400, 0x0f008000, MUL, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // MUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e209c00, MUL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // MVN <Vd>.<t>, <Vn>.<t>
+ {0xbffffc00, 0x2e205800, MVN, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, nil},
+ // NOT <Vd>.<t>, <Vn>.<t>
+ {0xbffffc00, 0x2e205800, NOT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, nil},
+ // MVNI <Vd>.<t>, #<imm8>{, LSL #<amount>}
+ {0xbff8dc00, 0x2f008400, MVNI, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil},
+ // MVNI <Vd>.<t_1>, #<imm8>{, LSL #<amount>}
+ {0xbff89c00, 0x2f000400, MVNI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil},
+ // MVNI <Vd>.<t_1>, #<imm8>, MSL #<amount>
+ {0xbff8ec00, 0x2f00c400, MVNI, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1}, nil},
+ // NEG <V><d>, <V><n>
+ {0xff3ffc00, 0x7e20b800, NEG, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3}, nil},
+ // NEG <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e20b800, NEG, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // ORN <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbfe0fc00, 0x0ee01c00, ORN, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // ORR <Vd>.<t>, #<imm8>{, LSL #<amount>}
+ {0xbff8dc00, 0x0f009400, ORR, instArgs{arg_Vd_arrangement_Q___4H_0__8H_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1}, nil},
+ // ORR <Vd>.<t_1>, #<imm8>{, LSL #<amount>}
+ {0xbff89c00, 0x0f001400, ORR, instArgs{arg_Vd_arrangement_Q___2S_0__4S_1, arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3}, nil},
+ // PMUL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e209c00, PMUL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01, arg_Vn_arrangement_size_Q___8B_00__16B_01, arg_Vm_arrangement_size_Q___8B_00__16B_01}, nil},
+ // PMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e20e000, PMULL, instArgs{arg_Vd_arrangement_size___8H_0__1Q_3, arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31}, nil},
+ // PMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e20e000, PMULL2, instArgs{arg_Vd_arrangement_size___8H_0__1Q_3, arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31}, nil},
+ // RADDHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x2e204000, RADDHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // RADDHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x6e204000, RADDHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // RBIT <Vd>.<t>, <Vn>.<t>
+ {0xbffffc00, 0x2e605800, RBIT, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_arrangement_Q___8B_0__16B_1}, nil},
+ // REV16 <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e201800, REV16, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01, arg_Vn_arrangement_size_Q___8B_00__16B_01}, nil},
+ // REV32 <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e200800, REV32, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11}, nil},
+ // REV64 <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e200800, REV64, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // RSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x0f008c00, RSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, rshrn_asimdshf_n_cond},
+ // RSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x4f008c00, RSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, rshrn_asimdshf_n_cond},
+ // RSUBHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x2e206000, RSUBHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // RSUBHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x6e206000, RSUBHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SABA <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e207c00, SABA, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SABAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e205000, SABAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SABAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e205000, SABAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SABD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e207400, SABD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SABDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e207000, SABDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SABDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e207000, SABDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SADALP <Vd>.<ta>, <Vn>.<tb>
+ {0xbf3ffc00, 0x0e206800, SADALP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SADDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e200000, SADDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SADDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e200000, SADDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SADDLP <Vd>.<ta>, <Vn>.<tb>
+ {0xbf3ffc00, 0x0e202800, SADDLP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SADDLV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e303800, SADDLV, instArgs{arg_Vd_22_2__H_0__S_1__D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // SADDW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x0e201000, SADDW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SADDW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x4e201000, SADDW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SCVTF <Sd>, <Wn>, #<fbits>
+ {0xffff0000, 0x1e020000, SCVTF, instArgs{arg_Sd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // SCVTF <Dd>, <Wn>, #<fbits>
+ {0xffff0000, 0x1e420000, SCVTF, instArgs{arg_Dd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // SCVTF <Sd>, <Xn>, #<fbits>
+ {0xffff0000, 0x9e020000, SCVTF, instArgs{arg_Sd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // SCVTF <Dd>, <Xn>, #<fbits>
+ {0xffff0000, 0x9e420000, SCVTF, instArgs{arg_Dd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // SCVTF <Sd>, <Wn>
+ {0xfffffc00, 0x1e220000, SCVTF, instArgs{arg_Sd, arg_Wn}, nil},
+ // SCVTF <Dd>, <Wn>
+ {0xfffffc00, 0x1e620000, SCVTF, instArgs{arg_Dd, arg_Wn}, nil},
+ // SCVTF <Sd>, <Xn>
+ {0xfffffc00, 0x9e220000, SCVTF, instArgs{arg_Sd, arg_Xn}, nil},
+ // SCVTF <Dd>, <Xn>
+ {0xfffffc00, 0x9e620000, SCVTF, instArgs{arg_Dd, arg_Xn}, nil},
+ // SCVTF <V><d>, <V><n>, #<fbits>
+ {0xff80fc00, 0x5f00e400, SCVTF, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, scvtf_asisdshf_c_cond},
+ // SCVTF <Vd>.<t>, <Vn>.<t>, #<fbits>
+ {0xbf80fc00, 0x0f00e400, SCVTF, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, scvtf_asimdshf_c_cond},
+ // SCVTF <V><d>, <V><n>
+ {0xffbffc00, 0x5e21d800, SCVTF, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // SCVTF <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0e21d800, SCVTF, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // SHA1C <Qd>, <Sn>, <Vm>.4S
+ {0xffe0fc00, 0x5e000000, SHA1C, instArgs{arg_Qd, arg_Sn, arg_Vm_arrangement_4S}, nil},
+ // SHA1H <Sd>, <Sn>
+ {0xfffffc00, 0x5e280800, SHA1H, instArgs{arg_Sd, arg_Sn}, nil},
+ // SHA1M <Qd>, <Sn>, <Vm>.4S
+ {0xffe0fc00, 0x5e002000, SHA1M, instArgs{arg_Qd, arg_Sn, arg_Vm_arrangement_4S}, nil},
+ // SHA1P <Qd>, <Sn>, <Vm>.4S
+ {0xffe0fc00, 0x5e001000, SHA1P, instArgs{arg_Qd, arg_Sn, arg_Vm_arrangement_4S}, nil},
+ // SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S
+ {0xffe0fc00, 0x5e003000, SHA1SU0, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S, arg_Vm_arrangement_4S}, nil},
+ // SHA1SU1 <Vd>.4S, <Vn>.4S
+ {0xfffffc00, 0x5e281800, SHA1SU1, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S}, nil},
+ // SHA256H <Qd>, <Qn>, <Vm>.4S
+ {0xffe0fc00, 0x5e004000, SHA256H, instArgs{arg_Qd, arg_Qn, arg_Vm_arrangement_4S}, nil},
+ // SHA256H2 <Qd>, <Qn>, <Vm>.4S
+ {0xffe0fc00, 0x5e005000, SHA256H2, instArgs{arg_Qd, arg_Qn, arg_Vm_arrangement_4S}, nil},
+ // SHA256SU0 <Vd>.4S, <Vn>.4S
+ {0xfffffc00, 0x5e282800, SHA256SU0, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S}, nil},
+ // SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S
+ {0xffe0fc00, 0x5e006000, SHA256SU1, instArgs{arg_Vd_arrangement_4S, arg_Vn_arrangement_4S, arg_Vm_arrangement_4S}, nil},
+ // SHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e200400, SHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SHL <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f005400, SHL, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_0_63_immh_immb__UIntimmhimmb64_8}, shl_asisdshf_r_cond},
+ // SHL <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x0f005400, SHL, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, shl_asimdshf_r_cond},
+ // SHLL <Vd>.<ta>, <Vn>.<tb>, #<shift>
+ {0xff3ffc00, 0x2e213800, SHLL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_immediate_0_width_size__8_0__16_1__32_2}, nil},
+ // SHLL2 <Vd>.<ta>, <Vn>.<tb>, #<shift>
+ {0xff3ffc00, 0x6e213800, SHLL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_immediate_0_width_size__8_0__16_1__32_2}, nil},
+ // SHRN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x0f008400, SHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, shrn_asimdshf_n_cond},
+ // SHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x4f008400, SHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, shrn_asimdshf_n_cond},
+ // SHSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e202400, SHSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SLI <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f005400, SLI, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_0_63_immh_immb__UIntimmhimmb64_8}, sli_asisdshf_r_cond},
+ // SLI <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f005400, SLI, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sli_asimdshf_r_cond},
+ // SMAX <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e206400, SMAX, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMAXP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e20a400, SMAXP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMAXV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e30a800, SMAXV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // SMIN <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e206c00, SMIN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMINP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e20ac00, SMINP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMINV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e31a800, SMINV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // SMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x0f002000, SMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x4f002000, SMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e208000, SMLAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e208000, SMLAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x0f006000, SMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x4f006000, SMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e20a000, SMLSL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e20a000, SMLSL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMOV <Wd>, <Vn>.<ts>[<index>]
+ {0xffe0fc00, 0x0e002c00, SMOV, instArgs{arg_Wd, arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1}, nil},
+ // SMOV <Xd>, <Vn>.<ts_1>[<index_1>]
+ {0xffe0fc00, 0x4e002c00, SMOV, instArgs{arg_Xd, arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1}, nil},
+ // SMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x0f00a000, SMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x4f00a000, SMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e20c000, SMULL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e20c000, SMULL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQABS <V><d>, <V><n>
+ {0xff3ffc00, 0x5e207800, SQABS, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SQABS <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e207800, SQABS, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SQADD <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e200c00, SQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SQADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e200c00, SQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SQDMLAL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff00f400, 0x5f003000, SQDMLAL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x0f003000, SQDMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x4f003000, SQDMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMLAL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e209000, SQDMLAL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil},
+ // SQDMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e209000, SQDMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQDMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e209000, SQDMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQDMLSL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff00f400, 0x5f007000, SQDMLSL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x0f007000, SQDMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x4f007000, SQDMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMLSL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e20b000, SQDMLSL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil},
+ // SQDMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e20b000, SQDMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQDMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e20b000, SQDMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQDMULH <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff00f400, 0x5f00c000, SQDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf00f400, 0x0f00c000, SQDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMULH <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e20b400, SQDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil},
+ // SQDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e20b400, SQDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQDMULL <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff00f400, 0x5f00b000, SQDMULL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x0f00b000, SQDMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x4f00b000, SQDMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQDMULL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e20d000, SQDMULL, instArgs{arg_Vd_22_2__S_1__D_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil},
+ // SQDMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e20d000, SQDMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQDMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e20d000, SQDMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQNEG <V><d>, <V><n>
+ {0xff3ffc00, 0x7e207800, SQNEG, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SQNEG <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e207800, SQNEG, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SQRDMULH <V><d>, <V><n>, <Vm>.<ts_1>[<index_1>]
+ {0xff00f400, 0x5f00d000, SQRDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQRDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<ts>[<index>]
+ {0xbf00f400, 0x0f00d000, SQRDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // SQRDMULH <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e20b400, SQRDMULH, instArgs{arg_Vd_22_2__H_1__S_2, arg_Vn_22_2__H_1__S_2, arg_Vm_22_2__H_1__S_2}, nil},
+ // SQRDMULH <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e20b400, SQRDMULH, instArgs{arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21}, nil},
+ // SQRSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e205c00, SQRSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SQRSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e205c00, SQRSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SQRSHRN <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f009c00, SQRSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrn_asisdshf_n_cond},
+ // SQRSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x0f009c00, SQRSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrn_asimdshf_n_cond},
+ // SQRSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x4f009c00, SQRSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrn_asimdshf_n_cond},
+ // SQRSHRUN <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f008c00, SQRSHRUN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrun_asisdshf_n_cond},
+ // SQRSHRUN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x2f008c00, SQRSHRUN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrun_asimdshf_n_cond},
+ // SQRSHRUN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x6f008c00, SQRSHRUN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqrshrun_asimdshf_n_cond},
+ // SQSHL <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f007400, SQSHL, instArgs{arg_Vd_19_4__B_1__H_2__S_4__D_8, arg_Vn_19_4__B_1__H_2__S_4__D_8, arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshl_asisdshf_r_cond},
+ // SQSHL <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x0f007400, SQSHL, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshl_asimdshf_r_cond},
+ // SQSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e204c00, SQSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SQSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e204c00, SQSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SQSHLU <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f006400, SQSHLU, instArgs{arg_Vd_19_4__B_1__H_2__S_4__D_8, arg_Vn_19_4__B_1__H_2__S_4__D_8, arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshlu_asisdshf_r_cond},
+ // SQSHLU <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f006400, SQSHLU, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, sqshlu_asimdshf_r_cond},
+ // SQSHRN <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f009400, SQSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrn_asisdshf_n_cond},
+ // SQSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x0f009400, SQSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrn_asimdshf_n_cond},
+ // SQSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x4f009400, SQSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrn_asimdshf_n_cond},
+ // SQSHRUN <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f008400, SQSHRUN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrun_asisdshf_n_cond},
+ // SQSHRUN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x2f008400, SQSHRUN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrun_asimdshf_n_cond},
+ // SQSHRUN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x6f008400, SQSHRUN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, sqshrun_asimdshf_n_cond},
+ // SQSUB <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e202c00, SQSUB, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SQSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e202c00, SQSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SQXTN <V><d>, <V><n>
+ {0xff3ffc00, 0x5e214800, SQXTN, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_22_2__H_0__S_1__D_2}, nil},
+ // SQXTN <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x0e214800, SQXTN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SQXTN2 <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x4e214800, SQXTN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SQXTUN <V><d>, <V><n>
+ {0xff3ffc00, 0x7e212800, SQXTUN, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_22_2__H_0__S_1__D_2}, nil},
+ // SQXTUN <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x2e212800, SQXTUN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SQXTUN2 <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x6e212800, SQXTUN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SRHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e201400, SRHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SRI <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f004400, SRI, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, sri_asisdshf_r_cond},
+ // SRI <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f004400, SRI, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, sri_asimdshf_r_cond},
+ // SRSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e205400, SRSHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // SRSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e205400, SRSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SRSHR <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f002400, SRSHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, srshr_asisdshf_r_cond},
+ // SRSHR <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x0f002400, SRSHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, srshr_asimdshf_r_cond},
+ // SRSRA <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f003400, SRSRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, srsra_asisdshf_r_cond},
+ // SRSRA <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x0f003400, SRSRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, srsra_asimdshf_r_cond},
+ // SSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x5e204400, SSHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // SSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e204400, SSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SXTL <Vd>.<ta>, <Vn>.<tb>
+ {0xff87fc00, 0x0f00a400, SXTL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, sxtl_sshll_asimdshf_l_cond},
+ // SXTL2 <Vd>.<ta>, <Vn>.<tb>
+ {0xff87fc00, 0x4f00a400, SXTL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, sxtl_sshll_asimdshf_l_cond},
+ // SSHLL <Vd>.<ta>, <Vn>.<tb>, #<shift>
+ {0xff80fc00, 0x0f00a400, SSHLL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, sshll_asimdshf_l_cond},
+ // SSHLL2 <Vd>.<ta>, <Vn>.<tb>, #<shift>
+ {0xff80fc00, 0x4f00a400, SSHLL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, sshll_asimdshf_l_cond},
+ // SSHR <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f000400, SSHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, sshr_asisdshf_r_cond},
+ // SSHR <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x0f000400, SSHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, sshr_asimdshf_r_cond},
+ // SSRA <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x5f001400, SSRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, ssra_asisdshf_r_cond},
+ // SSRA <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x0f001400, SSRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, ssra_asimdshf_r_cond},
+ // SSUBL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x0e202000, SSUBL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SSUBL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x4e202000, SSUBL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SSUBW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x0e203000, SSUBW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // SSUBW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x4e203000, SSUBW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c007000, ST1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c00a000, ST1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c006000, ST1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c002000, ST1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0c9f7000, ST1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__8_0__16_1}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c807000, ST1, instArgs{arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<imm_1>
+ {0xbffff000, 0x0c9fa000, ST1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c80a000, ST1, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<imm_2>
+ {0xbffff000, 0x0c9f6000, ST1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c806000, ST1, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<imm_3>
+ {0xbffff000, 0x0c9f2000, ST1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil},
+ // ST1 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c802000, ST1, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d000000, ST1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d004000, ST1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d008000, ST1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d008400, ST1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // ST1 <Vt>.B[<index>], [<Xn|SP>], #1
+ {0xbfffe000, 0x0d9f0000, ST1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_1}, nil},
+ // ST1 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0d800000, ST1, instArgs{arg_Vt_1_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.H[<index_2>], [<Xn|SP>], #2
+ {0xbfffe400, 0x0d9f4000, ST1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil},
+ // ST1 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0d804000, ST1, instArgs{arg_Vt_1_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.S[<index_3>], [<Xn|SP>], #4
+ {0xbfffec00, 0x0d9f8000, ST1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_4}, nil},
+ // ST1 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0d808000, ST1, instArgs{arg_Vt_1_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // ST1 <Vt>.D[<index_1>], [<Xn|SP>], #8
+ {0xbffffc00, 0x0d9f8400, ST1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_8}, nil},
+ // ST1 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0d808400, ST1, instArgs{arg_Vt_1_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // ST2 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c008000, ST2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil},
+ // ST2 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0c9f8000, ST2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__16_0__32_1}, nil},
+ // ST2 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c808000, ST2, instArgs{arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST2 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d200000, ST2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST2 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d204000, ST2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST2 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d208000, ST2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // ST2 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d208400, ST2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // ST2 <Vt>.B[<index>], [<Xn|SP>], #2
+ {0xbfffe000, 0x0dbf0000, ST2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_2}, nil},
+ // ST2 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0da00000, ST2, instArgs{arg_Vt_2_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST2 <Vt>.H[<index_2>], [<Xn|SP>], #4
+ {0xbfffe400, 0x0dbf4000, ST2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil},
+ // ST2 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0da04000, ST2, instArgs{arg_Vt_2_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST2 <Vt>.S[<index_3>], [<Xn|SP>], #8
+ {0xbfffec00, 0x0dbf8000, ST2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_8}, nil},
+ // ST2 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0da08000, ST2, instArgs{arg_Vt_2_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // ST2 <Vt>.D[<index_1>], [<Xn|SP>], #16
+ {0xbffffc00, 0x0dbf8400, ST2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_16}, nil},
+ // ST2 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0da08400, ST2, instArgs{arg_Vt_2_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // ST3 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c004000, ST3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil},
+ // ST3 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0c9f4000, ST3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__24_0__48_1}, nil},
+ // ST3 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c804000, ST3, instArgs{arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST3 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d002000, ST3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST3 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d006000, ST3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST3 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d00a000, ST3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // ST3 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d00a400, ST3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // ST3 <Vt>.B[<index>], [<Xn|SP>], #3
+ {0xbfffe000, 0x0d9f2000, ST3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_3}, nil},
+ // ST3 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0d802000, ST3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST3 <Vt>.H[<index_2>], [<Xn|SP>], #6
+ {0xbfffe400, 0x0d9f6000, ST3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_6}, nil},
+ // ST3 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0d806000, ST3, instArgs{arg_Vt_3_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST3 <Vt>.S[<index_3>], [<Xn|SP>], #12
+ {0xbfffec00, 0x0d9fa000, ST3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_12}, nil},
+ // ST3 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0d80a000, ST3, instArgs{arg_Vt_3_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // ST3 <Vt>.D[<index_1>], [<Xn|SP>], #24
+ {0xbffffc00, 0x0d9fa400, ST3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_24}, nil},
+ // ST3 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0d80a400, ST3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // ST4 <Vt>.<t>, [<Xn|SP>]
+ {0xbffff000, 0x0c000000, ST4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_offset}, nil},
+ // ST4 <Vt>.<t>, [<Xn|SP>], #<imm>
+ {0xbffff000, 0x0c9f0000, ST4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Q__32_0__64_1}, nil},
+ // ST4 <Vt>.<t>, [<Xn|SP>], #<Xm>
+ {0xbfe0f000, 0x0c800000, ST4, instArgs{arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Xns_mem_post_Xm}, nil},
+ // ST4 <Vt>.B[<index>], [<Xn|SP>]
+ {0xbfffe000, 0x0d202000, ST4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST4 <Vt>.H[<index_2>], [<Xn|SP>]
+ {0xbfffe400, 0x0d206000, ST4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_offset}, nil},
+ // ST4 <Vt>.S[<index_3>], [<Xn|SP>]
+ {0xbfffec00, 0x0d20a000, ST4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_offset}, nil},
+ // ST4 <Vt>.D[<index_1>], [<Xn|SP>]
+ {0xbffffc00, 0x0d20a400, ST4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
+ // ST4 <Vt>.B[<index>], [<Xn|SP>], #4
+ {0xbfffe000, 0x0dbf2000, ST4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_4}, nil},
+ // ST4 <Vt>.B[<index>], [<Xn|SP>], #<Xm>
+ {0xbfe0e000, 0x0da02000, ST4, instArgs{arg_Vt_4_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST4 <Vt>.H[<index_2>], [<Xn|SP>], #8
+ {0xbfffe400, 0x0dbf6000, ST4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_8}, nil},
+ // ST4 <Vt>.H[<index_2>], [<Xn|SP>], #<Xm>
+ {0xbfe0e400, 0x0da06000, ST4, instArgs{arg_Vt_4_arrangement_H_index__Q_S_size_1, arg_Xns_mem_post_Xm}, nil},
+ // ST4 <Vt>.S[<index_3>], [<Xn|SP>], #16
+ {0xbfffec00, 0x0dbfa000, ST4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_fixedimm_16}, nil},
+ // ST4 <Vt>.S[<index_3>], [<Xn|SP>], #<Xm>
+ {0xbfe0ec00, 0x0da0a000, ST4, instArgs{arg_Vt_4_arrangement_S_index__Q_S_1, arg_Xns_mem_post_Xm}, nil},
+ // ST4 <Vt>.D[<index_1>], [<Xn|SP>], #32
+ {0xbffffc00, 0x0dbfa400, ST4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_fixedimm_32}, nil},
+ // ST4 <Vt>.D[<index_1>], [<Xn|SP>], #<Xm>
+ {0xbfe0fc00, 0x0da0a400, ST4, instArgs{arg_Vt_4_arrangement_D_index__Q_1, arg_Xns_mem_post_Xm}, nil},
+ // STNP <St>, <St2>, [<Xn|SP>{, #<imm_2>}]
+ {0xffc00000, 0x2c000000, STNP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // STNP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x6c000000, STNP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // STNP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_1>}]
+ {0xffc00000, 0xac000000, STNP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil},
+ // STP <St>, <St2>, [<Xn|SP>], #<imm_5>
+ {0xffc00000, 0x2c800000, STP, instArgs{arg_St, arg_St2, arg_Xns_mem_post_imm7_4_signed}, nil},
+ // STP <Dt>, <Dt2>, [<Xn|SP>], #<imm_1>
+ {0xffc00000, 0x6c800000, STP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_post_imm7_8_signed}, nil},
+ // STP <Qt>, <Qt2>, [<Xn|SP>], #<imm_3>
+ {0xffc00000, 0xac800000, STP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_post_imm7_16_signed}, nil},
+ // STP <St>, <St2>, [<Xn|SP>{, #<imm_5>}]!
+ {0xffc00000, 0x2d800000, STP, instArgs{arg_St, arg_St2, arg_Xns_mem_wb_imm7_4_signed}, nil},
+ // STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm_1>}]!
+ {0xffc00000, 0x6d800000, STP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_wb_imm7_8_signed}, nil},
+ // STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_3>}]!
+ {0xffc00000, 0xad800000, STP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_wb_imm7_16_signed}, nil},
+ // STP <St>, <St2>, [<Xn|SP>{, #<imm_4>}]
+ {0xffc00000, 0x2d000000, STP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil},
+ // STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]
+ {0xffc00000, 0x6d000000, STP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
+ // STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_2>}]
+ {0xffc00000, 0xad000000, STP, instArgs{arg_Qt, arg_Qt2, arg_Xns_mem_optional_imm7_16_signed}, nil},
+ // STR <Bt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x3c000400, STR, instArgs{arg_Bt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <Ht>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x7c000400, STR, instArgs{arg_Ht, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <St>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xbc000400, STR, instArgs{arg_St, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <Dt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0xfc000400, STR, instArgs{arg_Dt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <Qt>, [<Xn|SP>], #<simm>
+ {0xffe00c00, 0x3c800400, STR, instArgs{arg_Qt, arg_Xns_mem_post_imm9_1_signed}, nil},
+ // STR <Bt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x3c000c00, STR, instArgs{arg_Bt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <Ht>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x7c000c00, STR, instArgs{arg_Ht, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <St>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xbc000c00, STR, instArgs{arg_St, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <Dt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0xfc000c00, STR, instArgs{arg_Dt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <Qt>, [<Xn|SP>{, #<simm>}]!
+ {0xffe00c00, 0x3c800c00, STR, instArgs{arg_Qt, arg_Xns_mem_wb_imm9_1_signed}, nil},
+ // STR <Bt>, [<Xn|SP>{, #<pimm>}]
+ {0xffc00000, 0x3d000000, STR, instArgs{arg_Bt, arg_Xns_mem_optional_imm12_1_unsigned}, nil},
+ // STR <Ht>, [<Xn|SP>{, #<pimm_2>}]
+ {0xffc00000, 0x7d000000, STR, instArgs{arg_Ht, arg_Xns_mem_optional_imm12_2_unsigned}, nil},
+ // STR <St>, [<Xn|SP>{, #<pimm_4>}]
+ {0xffc00000, 0xbd000000, STR, instArgs{arg_St, arg_Xns_mem_optional_imm12_4_unsigned}, nil},
+ // STR <Dt>, [<Xn|SP>{, #<pimm_1>}]
+ {0xffc00000, 0xfd000000, STR, instArgs{arg_Dt, arg_Xns_mem_optional_imm12_8_unsigned}, nil},
+ // STR <Qt>, [<Xn|SP>{, #<pimm_3>}]
+ {0xffc00000, 0x3d800000, STR, instArgs{arg_Qt, arg_Xns_mem_optional_imm12_16_unsigned}, nil},
+ // STR <Bt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x3c200800, STR, instArgs{arg_Bt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1}, nil},
+ // STR <Ht>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x7c200800, STR, instArgs{arg_Ht, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1}, nil},
+ // STR <St>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xbc200800, STR, instArgs{arg_St, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1}, nil},
+ // STR <Dt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0xfc200800, STR, instArgs{arg_Dt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1}, nil},
+ // STR <Qt>, [<Xn|SP>, (<Wm>|<Xm>) {, <extend> {<amount>}}]
+ {0xffe00c00, 0x3ca00800, STR, instArgs{arg_Qt, arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1}, nil},
+ // STUR <Bt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x3c000000, STUR, instArgs{arg_Bt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STUR <Ht>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x7c000000, STUR, instArgs{arg_Ht, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STUR <St>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xbc000000, STUR, instArgs{arg_St, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STUR <Dt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0xfc000000, STUR, instArgs{arg_Dt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // STUR <Qt>, [<Xn|SP>{, #<simm>}]
+ {0xffe00c00, 0x3c800000, STUR, instArgs{arg_Qt, arg_Xns_mem_optional_imm9_1_signed}, nil},
+ // SUB <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e208400, SUB, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // SUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e208400, SUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // SUBHN <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x0e206000, SUBHN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SUBHN2 <Vd>.<tb>, <Vn>.<ta>, <Vm>.<ta>
+ {0xff20fc00, 0x4e206000, SUBHN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // SUQADD <V><d>, <V><n>
+ {0xff3ffc00, 0x5e203800, SUQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil},
+ // SUQADD <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x0e203800, SUQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e002000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_2_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e004000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_3_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e006000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_4_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBL <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e000000, TBL, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_1_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e003000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_2_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e005000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_3_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e007000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_4_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TBX <Vd>.<ta>, <Vn>.16B, <Vm>.<ta>
+ {0xbfe0fc00, 0x0e001000, TBX, instArgs{arg_Vd_arrangement_Q___8B_0__16B_1, arg_Vn_1_arrangement_16B, arg_Vm_arrangement_Q___8B_0__16B_1}, nil},
+ // TRN1 <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e002800, TRN1, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // TRN2 <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e006800, TRN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UABA <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e207c00, UABA, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UABAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e205000, UABAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UABAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e205000, UABAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UABD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e207400, UABD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UABDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e207000, UABDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UABDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e207000, UABDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UADALP <Vd>.<ta>, <Vn>.<tb>
+ {0xbf3ffc00, 0x2e206800, UADALP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UADDL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e200000, UADDL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UADDL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e200000, UADDL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UADDLP <Vd>.<ta>, <Vn>.<tb>
+ {0xbf3ffc00, 0x2e202800, UADDLP, instArgs{arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UADDLV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e303800, UADDLV, instArgs{arg_Vd_22_2__H_0__S_1__D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // UADDW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x2e201000, UADDW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UADDW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x6e201000, UADDW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UCVTF <Sd>, <Wn>, #<fbits>
+ {0xffff0000, 0x1e030000, UCVTF, instArgs{arg_Sd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // UCVTF <Dd>, <Wn>, #<fbits>
+ {0xffff0000, 0x1e430000, UCVTF, instArgs{arg_Dd, arg_Wn, arg_immediate_fbits_min_1_max_32_sub_64_scale}, nil},
+ // UCVTF <Sd>, <Xn>, #<fbits>
+ {0xffff0000, 0x9e030000, UCVTF, instArgs{arg_Sd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // UCVTF <Dd>, <Xn>, #<fbits>
+ {0xffff0000, 0x9e430000, UCVTF, instArgs{arg_Dd, arg_Xn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
+ // UCVTF <Sd>, <Wn>
+ {0xfffffc00, 0x1e230000, UCVTF, instArgs{arg_Sd, arg_Wn}, nil},
+ // UCVTF <Dd>, <Wn>
+ {0xfffffc00, 0x1e630000, UCVTF, instArgs{arg_Dd, arg_Wn}, nil},
+ // UCVTF <Sd>, <Xn>
+ {0xfffffc00, 0x9e230000, UCVTF, instArgs{arg_Sd, arg_Xn}, nil},
+ // UCVTF <Dd>, <Xn>
+ {0xfffffc00, 0x9e630000, UCVTF, instArgs{arg_Dd, arg_Xn}, nil},
+ // UCVTF <V><d>, <V><n>, #<fbits>
+ {0xff80fc00, 0x7f00e400, UCVTF, instArgs{arg_Vd_19_4__S_4__D_8, arg_Vn_19_4__S_4__D_8, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8}, ucvtf_asisdshf_c_cond},
+ // UCVTF <Vd>.<t>, <Vn>.<t>, #<fbits>
+ {0xbf80fc00, 0x2f00e400, UCVTF, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81, arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8}, ucvtf_asimdshf_c_cond},
+ // UCVTF <V><d>, <V><n>
+ {0xffbffc00, 0x7e21d800, UCVTF, instArgs{arg_Vd_22_1__S_0__D_1, arg_Vn_22_1__S_0__D_1}, nil},
+ // UCVTF <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2e21d800, UCVTF, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11, arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11}, nil},
+ // UHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e200400, UHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UHSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e202400, UHSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMAX <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e206400, UMAX, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMAXP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e20a400, UMAXP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMAXV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e30a800, UMAXV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // UMIN <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e206c00, UMIN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMINP <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e20ac00, UMINP, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMINV <V><d>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e31a800, UMINV, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21}, nil},
+ // UMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x2f002000, UMLAL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // UMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x6f002000, UMLAL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // UMLAL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e208000, UMLAL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMLAL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e208000, UMLAL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x2f006000, UMLSL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // UMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x6f006000, UMLSL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // UMLSL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e20a000, UMLSL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMLSL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e20a000, UMLSL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x2f00a000, UMULL, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // UMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<ts>[<index>]
+ {0xff00f400, 0x6f00a000, UMULL2, instArgs{arg_Vd_arrangement_size___4S_1__2D_2, arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1}, nil},
+ // UMULL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e20c000, UMULL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UMULL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e20c000, UMULL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UQADD <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e200c00, UQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // UQADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e200c00, UQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UQRSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e205c00, UQRSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // UQRSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e205c00, UQRSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UQRSHRN <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f009c00, UQRSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqrshrn_asisdshf_n_cond},
+ // UQRSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x2f009c00, UQRSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqrshrn_asimdshf_n_cond},
+ // UQRSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x6f009c00, UQRSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqrshrn_asimdshf_n_cond},
+ // UQSHL <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f007400, UQSHL, instArgs{arg_Vd_19_4__B_1__H_2__S_4__D_8, arg_Vn_19_4__B_1__H_2__S_4__D_8, arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, uqshl_asisdshf_r_cond},
+ // UQSHL <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f007400, UQSHL, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8}, uqshl_asimdshf_r_cond},
+ // UQSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e204c00, UQSHL, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // UQSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e204c00, UQSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UQSHRN <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f009400, UQSHRN, instArgs{arg_Vd_19_4__B_1__H_2__S_4, arg_Vn_19_4__H_1__S_2__D_4, arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqshrn_asisdshf_n_cond},
+ // UQSHRN <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x2f009400, UQSHRN, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqshrn_asimdshf_n_cond},
+ // UQSHRN2 <Vd>.<tb>, <Vn>.<ta>, #<shift>
+ {0xff80fc00, 0x6f009400, UQSHRN2, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4}, uqshrn_asimdshf_n_cond},
+ // UQSUB <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e202c00, UQSUB, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3, arg_Vm_22_2__B_0__H_1__S_2__D_3}, nil},
+ // UQSUB <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e202c00, UQSUB, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UQXTN <V><d>, <V><n>
+ {0xff3ffc00, 0x7e214800, UQXTN, instArgs{arg_Vd_22_2__B_0__H_1__S_2, arg_Vn_22_2__H_0__S_1__D_2}, nil},
+ // UQXTN <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x2e214800, UQXTN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // UQXTN2 <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x6e214800, UQXTN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // URECPE <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x0ea1c800, URECPE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01, arg_Vn_arrangement_sz_Q___2S_00__4S_01}, nil},
+ // URHADD <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e201400, URHADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // URSHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e205400, URSHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // URSHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e205400, URSHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // URSHR <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f002400, URSHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, urshr_asisdshf_r_cond},
+ // URSHR <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f002400, URSHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, urshr_asimdshf_r_cond},
+ // URSQRTE <Vd>.<t>, <Vn>.<t>
+ {0xbfbffc00, 0x2ea1c800, URSQRTE, instArgs{arg_Vd_arrangement_sz_Q___2S_00__4S_01, arg_Vn_arrangement_sz_Q___2S_00__4S_01}, nil},
+ // URSRA <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f003400, URSRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, ursra_asisdshf_r_cond},
+ // URSRA <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f003400, URSRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, ursra_asimdshf_r_cond},
+ // USHL <V><d>, <V><n>, <V><m>
+ {0xff20fc00, 0x7e204400, USHL, instArgs{arg_Vd_22_2__D_3, arg_Vn_22_2__D_3, arg_Vm_22_2__D_3}, nil},
+ // USHL <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x2e204400, USHL, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UXTL <Vd>.<ta>, <Vn>.<tb>
+ {0xff87fc00, 0x2f00a400, UXTL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, uxtl_ushll_asimdshf_l_cond},
+ // UXTL2 <Vd>.<ta>, <Vn>.<tb>
+ {0xff87fc00, 0x6f00a400, UXTL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41}, uxtl_ushll_asimdshf_l_cond},
+ // USHLL <Vd>.<ta>, <Vn>.<tb>, #<shift>
+ {0xff80fc00, 0x2f00a400, USHLL, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, ushll_asimdshf_l_cond},
+ // USHLL2 <Vd>.<ta>, <Vn>.<tb>, #<shift>
+ {0xff80fc00, 0x6f00a400, USHLL2, instArgs{arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41, arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4}, ushll_asimdshf_l_cond},
+ // USHR <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f000400, USHR, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, ushr_asisdshf_r_cond},
+ // USHR <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f000400, USHR, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, ushr_asimdshf_r_cond},
+ // USQADD <V><d>, <V><n>
+ {0xff3ffc00, 0x7e203800, USQADD, instArgs{arg_Vd_22_2__B_0__H_1__S_2__D_3, arg_Vn_22_2__B_0__H_1__S_2__D_3}, nil},
+ // USQADD <Vd>.<t>, <Vn>.<t>
+ {0xbf3ffc00, 0x2e203800, USQADD, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // USRA <V><d>, <V><n>, #<shift>
+ {0xff80fc00, 0x7f001400, USRA, instArgs{arg_Vd_19_4__D_8, arg_Vn_19_4__D_8, arg_immediate_1_64_immh_immb__128UIntimmhimmb_8}, usra_asisdshf_r_cond},
+ // USRA <Vd>.<t>, <Vn>.<t>, #<shift>
+ {0xbf80fc00, 0x2f001400, USRA, instArgs{arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81, arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8}, usra_asimdshf_r_cond},
+ // USUBL <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x2e202000, USUBL, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // USUBL2 <Vd>.<ta>, <Vn>.<tb>, <Vm>.<tb>
+ {0xff20fc00, 0x6e202000, USUBL2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // USUBW <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x2e203000, USUBW, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // USUBW2 <Vd>.<ta>, <Vn>.<ta>, <Vm>.<tb>
+ {0xff20fc00, 0x6e203000, USUBW2, instArgs{arg_Vd_arrangement_size___8H_0__4S_1__2D_2, arg_Vn_arrangement_size___8H_0__4S_1__2D_2, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21}, nil},
+ // UZP1 <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e001800, UZP1, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // UZP2 <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e005800, UZP2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // XTN <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x0e212800, XTN, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // XTN2 <Vd>.<tb>, <Vn>.<ta>
+ {0xff3ffc00, 0x4e212800, XTN2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21, arg_Vn_arrangement_size___8H_0__4S_1__2D_2}, nil},
+ // ZIP1 <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e003800, ZIP1, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+ // ZIP2 <Vd>.<t>, <Vn>.<t>, <Vm>.<t>
+ {0xbf20fc00, 0x0e007800, ZIP2, instArgs{arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31, arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31}, nil},
+}
diff --git a/arm64/arm64asm/testdata/Makefile b/arm64/arm64asm/testdata/Makefile
new file mode 100644
index 0000000..914a9a0
--- /dev/null
+++ b/arm64/arm64asm/testdata/Makefile
@@ -0,0 +1,7 @@
+go test command:
+ cd ..; go test -run 'ObjdumpARM64Cond' -v -timeout 10h -long 2>&1 | tee log
+ cd ..; go test -run 'ObjdumpARM64Testdata' -v -timeout 10h -long 2>&1 | tee -a log
+ cd ..; go test -run 'ObjdumpARM64' -v -timeout 10h -long 2>&1 | tee -a log
+ cd ..; go test -run 'ObjdumpARM64Manual' -v -timeout 10h -long 2>&1 | tee -a log
+ cd ..; go test -run 'TestDecode'
+ cd ..; go test -run '.*'
diff --git a/arm64/arm64asm/testdata/cases.txt b/arm64/arm64asm/testdata/cases.txt
new file mode 100644
index 0000000..57795dd
--- /dev/null
+++ b/arm64/arm64asm/testdata/cases.txt
@@ -0,0 +1,9203 @@
+0a011f1a| gnu adc w10, w8, wzr
+4c00009a| gnu adc x12, x2, x0
+a602093a| gnu adcs w6, w21, w9
+d60217ba| gnu adcs x22, x22, x23
+0921250b| gnu add w9, w8, w5, uxth
+ee9e288b| gnu add x14, x23, w8, sxtb #7
+23123011| gnu add w3, w17, #0xc04
+2ba32391| gnu add x11, x25, #0x8e8
+67158d0b| gnu add w7, w11, w13, asr #5
+30da198b| gnu add x16, x17, x25, lsl #54
+a7e72c2b| gnu adds w7, w29, w12, sxtx #1
+357338ab| gnu adds x21, x25, x24, uxtx #4
+6b147731| gnu adds w11, w3, #0xdc5, lsl #12
+cd59872b| gnu adds w13, w14, w7, asr #22
+e41f4eab| gnu adds x4, xzr, x14, lsr #7
+b7dd8470| gnu adr x23, .+0xfffffffffff09bb7
+0f4996d0| gnu adrp x15, .+0xffffffff2c922000
+a2432412| gnu and w2, w29, #0xf0001fff
+93910e92| gnu and x19, x12, #0x7c007c007c007c
+7a1ec98a| gnu and x26, x19, x9, ror #7
+1ff32972| gnu tst w24, #0xaaaaaaaa
+458051f2| gnu ands x5, x2, #0xffff80000000ffff
+af629a6a| gnu ands w15, w21, w26, asr #24
+7ab0dfea| gnu ands x26, x3, xzr, ror #44
+792bcc1a| gnu asr w25, w27, w12
+872bce9a| gnu asr x7, x28, x14
+99ff4b93| gnu asr x25, x28, #11
+1628c91a| gnu asr w22, w0, w9
+4e2acf9a| gnu asr x14, x18, x15
+4be5a454| gnu b.lt .+0xfffffffffff49ca8
+53257114| gnu b .+0x1c4954c
+dbb557b3| gnu bfxil x27, x14, #23, #23
+70e861b3| gnu bfxil x16, x3, #33, #26
+88a75ab3| gnu bfxil x8, x28, #26, #16
+b03ce70a| gnu bic w16, w5, w7, ror #15
+9235ec8a| gnu bic x18, x12, x12, ror #13
+7450b96a| gnu bics w20, w3, w25, asr #20
+3730b3ea| gnu bics x23, x1, x19, asr #12
+9b897797| gnu bl .+0xfffffffffdde266c
+e0013fd6| gnu blr x15
+a0031fd6| gnu br x29
+e08c31d4| gnu brk #0x8c67
+027eb435| gnu cbnz w2, .+0xfffffffffff68fc0
+c7eb42b5| gnu cbnz x7, .+0x85d78
+8f1d4c34| gnu cbz w15, .+0x983b0
+e1c5abb4| gnu cbz x1, .+0xfffffffffff578bc
+4bfb543a| gnu ccmn w26, #0x14, #0xb, al
+015b46ba| gnu ccmn x24, #0x6, #0x1, pl
+8602463a| gnu ccmn w20, w6, #0x6, eq
+c6d34cba| gnu ccmn x30, x12, #0x6, le
+a76b4f7a| gnu ccmp w29, #0xf, #0x7, vs
+e3d853fa| gnu ccmp x7, #0x13, #0x3, le
+4022467a| gnu ccmp w18, w6, #0x0, cs
+c7b346fa| gnu ccmp x30, x6, #0x7, lt
+ee279b1a| gnu csinc w14, wzr, w27, cs
+4174819a| gnu csinc x1, x2, x1, vc
+5100955a| gnu csinv w17, w2, w21, eq
+573093da| gnu csinv x23, x2, x19, cc
+5f3403d5| gnu clrex #0x4
+e615c05a| gnu cls w6, w15
+ff15c0da| gnu cls xzr, x15
+2e10c05a| gnu clz w14, w1
+a912c0da| gnu clz x9, x21
+ff11352b| gnu cmn w15, w21, uxtb #4
+1f5220ab| gnu cmn x16, w0, uxtw #4
+ff02266b| gnu cmp w23, w6, uxtb
+5fb739eb| gnu cmp x26, w25, sxth #5
+bfa73bf1| gnu cmp x29, #0xee9
+7f5c47eb| gnu cmp x3, x7, lsr #23
+2e458e5a| gnu csneg w14, w9, w14, mi
+c3559cda| gnu csneg x3, x14, x28, pl
+1041d11a| gnu crc32b w16, w8, w17
+bb46c31a| gnu crc32h w27, w21, w3
+c94bd61a| gnu crc32w w9, w30, w22
+8f4cd49a| gnu crc32x w15, w4, x20
+7653d21a| gnu crc32cb w22, w27, w18
+1454d51a| gnu crc32ch w20, w0, w21
+7c58c91a| gnu crc32cw w28, w3, w9
+185ccb9a| gnu crc32cx w24, w0, x11
+8c30941a| gnu csel w12, w4, w20, cc
+0ea08c9a| gnu csel x14, x0, x12, ge
+e3b79f1a| gnu cset w3, ge
+fea79f9a| gnu cset x30, lt
+e5639f5a| gnu csetm w5, vc
+e4739fda| gnu csetm x4, vs
+bad4981a| gnu csinc w26, w5, w24, le
+5167909a| gnu csinc x17, x26, x16, vs
+65e3955a| gnu csinv w5, w27, w21, al
+8e338bda| gnu csinv x14, x28, x11, cc
+0a269d5a| gnu csneg w10, w16, w29, cs
+ab1692da| gnu csneg x11, x21, x18, ne
+418ea5d4| gnu dcps1 #0x2c72
+6239a5d4| gnu dcps2 #0x29cb
+e3ebabd4| gnu dcps3 #0x5f5f
+bf3a03d5| gnu dmb ishst
+e003bfd6| gnu drps
+9f3003d5| gnu dsb #0x00
+c974354a| gnu eon w9, w6, w21, lsl #29
+89b86eca| gnu eon x9, x4, x14, lsr #46
+76e343d2| gnu eor x22, x27, #0xe03fffffffffffff
+536d8c4a| gnu eor w19, w10, w12, asr #27
+d1ef1cca| gnu eor x17, x30, x28, lsl #59
+e0039fd6| gnu eret
+591d8813| gnu extr w25, w10, w8, #7
+888dd693| gnu extr x8, x12, x22, #35
+bf2003d5| gnu sevl
+df2003d5| gnu hint #0x6
+a0fc5fd4| gnu hlt #0xffe5
+df3103d5| gnu isb #0x1
+9dfddf88| gnu ldar w29, [x12]
+76ffdfc8| gnu ldar x22, [x27]
+36ffdf08| gnu ldarb w22, [x25]
+bcfcdf48| gnu ldarh w28, [x5]
+54c17f88| gnu ldaxp w20, w16, [x10]
+3eaf7fc8| gnu ldaxp x30, x11, [x25]
+e2fd5f88| gnu ldaxr w2, [x15]
+f5fd5fc8| gnu ldaxr x21, [x15]
+70fe5f08| gnu ldaxrb w16, [x19]
+bcfc5f48| gnu ldaxrh w28, [x5]
+ecff5928| gnu ldnp w12, wzr, [sp,#204]
+852744a8| gnu ldnp x5, x9, [x28,#64]
+1286d728| gnu ldp w18, w1, [x16],#188
+7668e8a8| gnu ldp x22, x26, [x3],#-384
+6d8bc729| gnu ldp w13, w2, [x27,#60]!
+1cadd1a9| gnu ldp x28, x11, [x8,#280]!
+bf4e7e29| gnu ldp wzr, w19, [x21,#-16]
+61695fa9| gnu ldp x1, x26, [x11,#496]
+4c00e668| gnu ldpsw x12, x0, [x2],#-208
+85a0cb69| gnu ldpsw x5, x8, [x4,#92]!
+9b894d69| gnu ldpsw x27, x2, [x12,#108]
+e9955ab8| gnu ldr w9, [x15],#-87
+5c255df8| gnu ldr x28, [x10],#-46
+703c57b8| gnu ldr w16, [x3,#-141]!
+1dac57f8| gnu ldr x29, [x0,#-134]!
+393c50b9| gnu ldr w25, [x1,#4156]
+498d5cf9| gnu ldr x9, [x10,#14616]
+841fe218| gnu ldr w4, .+0xfffffffffffc43f0
+cce88858| gnu ldr x12, .+0xfffffffffff11d18
+72fa72b8| gnu ldr w18, [x19,x18,sxtx #2]
+daeb66f8| gnu ldr x26, [x30,x6,sxtx]
+8ca74238| gnu ldrb w12, [x28],#42
+4e5c5e38| gnu ldrb w14, [x2,#-27]!
+03936d39| gnu ldrb w3, [x24,#2916]
+577a6e38| gnu ldrb w23, [x18,x14,lsl #0]
+adb54678| gnu ldrh w13, [x13],#107
+820f4c78| gnu ldrh w2, [x28,#192]!
+92787579| gnu ldrh w18, [x4,#6844]
+4bd6c438| gnu ldrsb w11, [x18],#77
+fb478238| gnu ldrsb x27, [sp],#36
+4d7edc38| gnu ldrsb w13, [x18,#-57]!
+18ee9438| gnu ldrsb x24, [x16,#-178]!
+16b9c639| gnu ldrsb w22, [x8,#430]
+37958f39| gnu ldrsb x23, [x9,#997]
+af7ae238| gnu ldrsb w15, [x21,x2,lsl #0]
+1568fa38| gnu ldrsb w21, [x0,x26]
+744bbf38| gnu ldrsb x20, [x27,wzr,uxtw]
+f069a538| gnu ldrsb x16, [x15,x5]
+d9a6cd78| gnu ldrsh w25, [x22],#218
+ff368b78| gnu ldrsh xzr, [x23],#179
+5b8cc878| gnu ldrsh w27, [x2,#136]!
+361f9c78| gnu ldrsh x22, [x25,#-63]!
+359bec79| gnu ldrsh w21, [x25,#5708]
+4d6c8079| gnu ldrsh x13, [x2,#54]
+9deae578| gnu ldrsh w29, [x20,x5,sxtx]
+f2fab878| gnu ldrsh x18, [x23,x24,sxtx #1]
+02669cb8| gnu ldrsw x2, [x16],#-58
+5c8e92b8| gnu ldrsw x28, [x18,#-216]!
+ea9e92b9| gnu ldrsw x10, [x23,#4764]
+6e280c98| gnu ldrsw x14, .+0x1850c
+49dabcb8| gnu ldrsw x9, [x18,w28,sxtw #2]
+64285eb8| gnu ldtr w4, [x3,#-30]
+6ab851f8| gnu ldtr x10, [x3,#-229]
+aa094f38| gnu ldtrb w10, [x13,#240]
+b7894e78| gnu ldtrh w23, [x13,#232]
+85cadd38| gnu ldtrsb w5, [x20,#-36]
+2db99838| gnu ldtrsb x13, [x9,#-117]
+7ef8ce78| gnu ldtrsh w30, [x3,#239]
+786a8978| gnu ldtrsh x24, [x19,#150]
+c5eb81b8| gnu ldtrsw x5, [x30,#30]
+a1f14bb8| gnu ldur w1, [x13,#191]
+c3425cf8| gnu ldur x3, [x22,#-60]
+2e125038| gnu ldurb w14, [x17,#-255]
+26004878| gnu ldurh w6, [x1,#128]
+c3e3cd38| gnu ldursb w3, [x30,#222]
+27618938| gnu ldursb x7, [x9,#150]
+7c71db78| gnu ldursh w28, [x11,#-73]
+1d109e78| gnu ldursh x29, [x0,#-31]
+d48084b8| gnu ldursw x20, [x6,#72]
+172f7f88| gnu ldxp w23, w11, [x24]
+10347fc8| gnu ldxp x16, x13, [x0]
+fe7f5f88| gnu ldxr w30, [sp]
+6c7f5fc8| gnu ldxr x12, [x27]
+047c5f08| gnu ldxrb w4, [x0]
+9a7d5f48| gnu ldxrh w26, [x12]
+4f21cb1a| gnu lsl w15, w10, w11
+1523db9a| gnu lsl x21, x24, x27
+81c74fd3| gnu ubfx x1, x28, #15, #35
+c922c81a| gnu lsl w9, w22, w8
+fd22dc9a| gnu lsl x29, x23, x28
+4226dd1a| gnu lsr w2, w18, w29
+a224ca9a| gnu lsr x2, x5, x10
+707c0153| gnu lsr w16, w3, #1
+34fc4cd3| gnu lsr x20, x1, #12
+6c24c91a| gnu lsr w12, w3, w9
+8527c89a| gnu lsr x5, x28, x8
+ea36171b| gnu madd w10, w23, w23, w13
+e47a0a9b| gnu madd x4, x23, x10, x30
+35fd001b| gnu mneg w21, w9, w0
+77ff0e9b| gnu mneg x23, x27, x14
+38030011| gnu add w24, w25, #0x0
+37030091| gnu add x23, x25, #0x0
+94b8ad12| gnu mov w20, #0x923bffff
+fff29892| gnu mov xzr, #0xffffffffffff3868
+d4adb252| gnu mov w20, #0x956e0000
+8747e2d2| gnu mov x7, #0x123c000000000000
+f5132d32| gnu orr w21, wzr, #0xf80000
+eb7f34b2| gnu mov x11, #0xffffffffffffffff
+f503092a| gnu mov w21, w9
+e7031eaa| gnu mov x7, x30
+35e8c1f2| gnu movk x21, #0xf41, lsl #32
+44629512| gnu mov w4, #0xffff54ed
+cc0dd392| gnu mov x12, #0xffff6791ffffffff
+cbfb9152| gnu mov w11, #0x8fde
+3d25ebd2| gnu mov x29, #0x5929000000000000
+e67a3fd5| gnu mrs x6, s3_7_c7_c10_7
+f9dd15d5| gnu msr s2_5_c13_c13_7, x25
+25840c1b| gnu msub w5, w1, w12, w1
+02ce1a9b| gnu msub x2, x16, x26, x19
+b67c1a1b| gnu mul w22, w5, w26
+607c049b| gnu mul x0, x3, x4
+e97f6daa| gnu mvn x9, x13, lsr #31
+fe071f6b| gnu negs w30, wzr, lsl #1
+f68f14eb| gnu negs x22, x20, lsl #35
+e8030d5a| gnu ngc w8, w13
+fe031eda| gnu ngc x30, x30
+e5030a7a| gnu ngcs w5, w10
+f00318fa| gnu ngcs x16, x24
+1f2003d5| gnu nop
+032ee42a| gnu orn w3, w16, w4, ror #11
+634cf6aa| gnu orn x3, x3, x22, ror #19
+f8492d32| gnu orr w24, w15, #0xfff8003f
+96f542b2| gnu orr x22, x12, #0xcfffffffffffffff
+1c110d2a| gnu orr w28, w8, w13, lsl #4
+c65b1eaa| gnu orr x6, x30, x30, lsl #22
+f300b2f9| gnu prfm pstl2strm, [x7,#25600]
+2aa196d8| gnu prfm plil2keep, .+0xfffffffffff2d424
+2ad8bef8| gnu prfm plil2keep, [x1,w30,sxtw #3]
+c62184f8| gnu prfum #0x06, [x14,#66]
+3601c05a| gnu rbit w22, w9
+6401c0da| gnu rbit x4, x11
+e0035fd6| gnu ret xzr
+0a09c05a| gnu rev w10, w8
+220cc0da| gnu rev x2, x1
+b206c05a| gnu rev16 w18, w21
+2407c0da| gnu rev16 x4, x25
+7e0bc0da| gnu rev32 x30, x27
+ae0ec0da| gnu rev x14, x21
+336f8413| gnu extr w19, w25, w4, #27
+af47ca93| gnu extr x15, x29, x10, #17
+bc2cdb1a| gnu ror w28, w5, w27
+e52fdd9a| gnu ror x5, xzr, x29
+832dc31a| gnu ror w3, w12, w3
+e22ec09a| gnu ror x2, x23, x0
+1801045a| gnu sbc w24, w8, w4
+5a0119da| gnu sbc x26, x10, x25
+52021b7a| gnu sbcs w18, w18, w27
+250105fa| gnu sbcs x5, x9, x5
+fc430b13| gnu sbfx w28, wzr, #11, #6
+a0574093| gnu sbfx x0, x29, #0, #22
+8b3b7a93| gnu sbfiz x11, x28, #6, #15
+fc310513| gnu sbfx w28, w15, #5, #8
+fbdc4293| gnu sbfx x27, x7, #2, #54
+c90dd61a| gnu sdiv w9, w14, w22
+a90ecd9a| gnu sdiv x9, x21, x13
+9f2003d5| gnu sev
+bf2003d5| gnu sevl
+d27f229b| gnu smull x18, w30, w2
+efff3a9b| gnu smnegl x15, wzr, w26
+7d963f9b| gnu smsubl x29, w19, wzr, x5
+b57e519b| gnu smulh x21, x21, x17
+a07c209b| gnu smull x0, w5, w0
+d0fe9f88| gnu stlr w16, [x22]
+03ff9fc8| gnu stlr x3, [x24]
+8bff9f08| gnu stlrb w11, [x28]
+f0fe9f48| gnu stlrh w16, [x23]
+c6ae3588| gnu stlxp w21, w6, w11, [x22]
+c6fa22c8| gnu stlxp w2, x6, x30, [x22]
+affd0e88| gnu stlxr w14, w15, [x13]
+67ff1cc8| gnu stlxr w28, x7, [x27]
+17ff1c08| gnu stlxrb w28, w23, [x24]
+7bfe0b48| gnu stlxrh w11, w27, [x19]
+2a8c0528| gnu stnp w10, w3, [x1,#44]
+67fc10a8| gnu stnp x7, xzr, [x3,#264]
+5559bd28| gnu stp w21, w22, [x10],#-24
+166c96a8| gnu stp x22, x27, [x0],#352
+3d4a8729| gnu stp w29, w18, [x17,#56]!
+912f86a9| gnu stp x17, x11, [x28,#96]!
+c40d3029| gnu stp w4, w3, [x14,#-128]
+f73f39a9| gnu stp x23, x15, [sp,#-112]
+34441eb8| gnu str w20, [x1],#-28
+11f60bf8| gnu str x17, [x16],#191
+c15d15b8| gnu str w1, [x14,#-171]!
+ae4d12f8| gnu str x14, [x13,#-220]!
+03ef39b9| gnu str w3, [x24,#14828]
+208228f9| gnu str x0, [x17,#20736]
+734823f8| gnu str x19, [x3,w3,uxtw]
+ffb41838| gnu strb wzr, [x7],#-117
+bb0d1a38| gnu strb w27, [x13,#-96]!
+b1612239| gnu strb w17, [x13,#2200]
+92682038| gnu strb w18, [x4,x0]
+81682638| gnu strb w1, [x4,x6]
+87841b78| gnu strh w7, [x4],#-72
+cc3d1878| gnu strh w12, [x14,#-125]!
+53cf1c79| gnu strh w19, [x26,#3686]
+63792d78| gnu strh w3, [x11,x13,lsl #1]
+9d7803b8| gnu sttr w29, [x4,#55]
+b9c807f8| gnu sttr x25, [x5,#124]
+f04a1e38| gnu sttrb w16, [x23,#-28]
+52990078| gnu sttrh w18, [x10,#9]
+152002b8| gnu stur w21, [x0,#34]
+397217f8| gnu stur x25, [x17,#-137]
+8f320138| gnu sturb w15, [x20,#19]
+eb021b78| gnu sturh w11, [x23,#-80]
+854a3f88| gnu stxp wzr, w5, w18, [x20]
+d12620c8| gnu stxp w0, x17, x9, [x22]
+537e0288| gnu stxr w2, w19, [x18]
+af7d15c8| gnu stxr w21, x15, [x13]
+e97c1d08| gnu stxrb w29, w9, [x7]
+837d1b48| gnu stxrh w27, w3, [x12]
+f25e344b| gnu sub w18, w23, w20, uxtw #7
+3ac825cb| gnu sub x26, x1, w5, sxtw #2
+e8f40ccb| gnu sub x8, x7, x12, lsl #61
+a6ad226b| gnu subs w6, w13, w2, sxth #3
+647735eb| gnu subs x4, x27, x21, uxtx #5
+c770566b| gnu subs w7, w6, w22, lsr #28
+d03c1aeb| gnu subs x16, x6, x26, lsl #15
+a17f03d4| gnu svc #0x1bfd
+991f0013| gnu sxtb w25, w28
+a91d4093| gnu sxtb x9, w13
+083d0013| gnu sxth w8, w8
+393e4093| gnu sxth x25, w17
+1b7c4093| gnu sxtw x27, w0
+0c5b2cd5| gnu sysl x12, #4, C5, C11, #0
+09868bb7| gnu tbnz x9, #49, .+0x70c0
+8c2e6836| gnu tbz w12, #13, .+0x5d0
+3f0d0172| gnu tst w9, #0x80000007
+df6f7cf2| gnu tst x30, #0xfffffff0
+1f2f11ea| gnu tst x24, x17, lsl #11
+9ced71d3| gnu ubfx x28, x12, #49, #11
+1cbb7fd3| gnu ubfiz x28, x24, #1, #47
+25e661d3| gnu ubfx x5, x17, #33, #25
+af0adc1a| gnu udiv w15, w21, w28
+550ac29a| gnu udiv x21, x18, x2
+9102b19b| gnu umaddl x17, w20, w17, x0
+41fea39b| gnu umnegl x1, w18, w3
+87d8a39b| gnu umsubl x7, w4, w3, x22
+987ed89b| gnu umulh x24, x20, x24
+d37eb29b| gnu umull x19, w22, w18
+461c0053| gnu uxtb w6, w2
+f43c0053| gnu uxth w20, w7
+5f2003d5| gnu wfe
+7f2003d5| gnu wfi
+3f2003d5| gnu yield
+e5bb200e| gnu abs v5.8b, v31.8b
+c9842d0e| gnu add v9.8b, v6.8b, v13.8b
+f4bd394e| gnu addp v20.16b, v15.16b, v25.16b
+b3b8b14e| gnu addv s19, v5.4s
+cd5b284e| gnu aesd v13.16b, v30.16b
+4b4b284e| gnu aese v11.16b, v26.16b
+2879284e| gnu aesimc v8.16b, v9.16b
+fe68284e| gnu aesmc v30.16b, v7.16b
+f61e334e| gnu and v22.16b, v23.16b, v19.16b
+88a4002f| gnu mvni v8.4h, #0x4, lsl #8
+1877076f| gnu bic v24.4s, #0xf8, lsl #24
+0d1e6c0e| gnu bic v13.8b, v16.8b, v12.8b
+b81ce26e| gnu bif v24.16b, v5.16b, v2.16b
+381cbf2e| gnu bit v24.8b, v1.8b, v31.8b
+cd1f6c6e| gnu bsl v13.16b, v30.16b, v12.16b
+8d48a00e| gnu cls v13.2s, v4.2s
+324ba02e| gnu clz v18.2s, v25.2s
+c88f2b2e| gnu cmeq v8.8b, v30.8b, v11.8b
+a799e05e| gnu cmeq d7, d13, #0
+dc9be04e| gnu cmeq v28.2d, v30.2d, #0
+623f2d4e| gnu cmge v2.16b, v27.16b, v13.16b
+e889e06e| gnu cmge v8.2d, v15.2d, #0
+cb37e55e| gnu cmgt d11, d30, d5
+8e37b00e| gnu cmgt v14.2s, v28.2s, v16.2s
+1a8be04e| gnu cmgt v26.2d, v24.2d, #0
+7f37eb7e| gnu cmhi d31, d27, d11
+333d356e| gnu cmhs v19.16b, v9.16b, v21.16b
+bd9ae07e| gnu cmle d29, d21, #0
+8999602e| gnu cmle v9.4h, v12.4h, #0
+aca9e05e| gnu cmlt d12, d13, #0
+7fa8204e| gnu cmlt v31.16b, v3.16b, #0
+588db20e| gnu cmtst v24.2s, v10.2s, v18.2s
+cc051d5e| gnu mov b12, v14.b[14]
+4c06050e| gnu dup v12.8b, v18.b[2]
+790c020e| gnu dup v25.4h, w3
+391d286e| gnu eor v25.16b, v9.16b, v8.16b
+4b30156e| gnu ext v11.16b, v2.16b, v21.16b, #6
+44d6bf7e| gnu fabd s4, s18, s31
+17fba00e| gnu fabs v23.2s, v24.2s
+90c2201e| gnu fabs s16, s20
+62c2601e| gnu fabs d2, d19
+eeef3f7e| gnu facge s14, s31, s31
+09efa07e| gnu facgt s9, s24, s0
+72edae6e| gnu facgt v18.4s, v11.4s, v14.4s
+61d5394e| gnu fadd v1.4s, v11.4s, v25.4s
+0d2a3d1e| gnu fadd s13, s16, s29
+4b296f1e| gnu fadd d11, d10, d15
+78d8307e| gnu faddp s24, v3.2s
+e7d7322e| gnu faddp v7.2s, v31.2s, v18.2s
+e8253c1e| gnu fccmp s15, s28, #0x8, cs
+e8857f1e| gnu fccmp d15, d31, #0x8, hi
+5714291e| gnu fccmpe s2, s9, #0x7, ne
+b484631e| gnu fccmpe d5, d3, #0x4, hi
+3ce5685e| gnu fcmeq d28, d9, d8
+50e6214e| gnu fcmeq v16.4s, v18.4s, v1.4s
+9ddae05e| gnu fcmeq d29, d20, #0
+b3e62b7e| gnu fcmge s19, s21, s11
+0ce4396e| gnu fcmge v12.4s, v0.4s, v25.4s
+a6c9e07e| gnu fcmge d6, d13, #0
+ede6bd7e| gnu fcmgt s13, s23, s29
+13e6ae2e| gnu fcmgt v19.2s, v16.2s, v14.2s
+4cc9e05e| gnu fcmgt d12, d10, #0
+41cba04e| gnu fcmgt v1.4s, v26.4s, #0
+96d8e07e| gnu fcmle d22, d4, #0
+0be9a05e| gnu fcmlt s11, s8, #0
+dfe9a04e| gnu fcmlt v31.4s, v14.4s, #0
+a023301e| gnu fcmp s29, s16
+68213e1e| gnu fcmp s11, #0
+20236d1e| gnu fcmp d25, d13
+68216b1e| gnu fcmp d11, #0
+3023351e| gnu fcmpe s25, s21
+78203e1e| gnu fcmpe s3, #0
+b022721e| gnu fcmpe d21, d18
+f8226f1e| gnu fcmpe d23, #0
+b54e271e| gnu fcsel s21, s21, s7, mi
+319f611e| gnu fcsel d17, d25, d1, ls
+2142e21e| gnu fcvt s1, h17
+cfc3e21e| gnu fcvt d15, h30
+01c1231e| gnu fcvt h1, s8
+4fc0221e| gnu fcvt d15, s2
+f9c0631e| gnu fcvt h25, d7
+2b43621e| gnu fcvt s11, d25
+f1c8615e| gnu fcvtas d17, d7
+ea01241e| gnu fcvtas w10, s15
+0c02249e| gnu fcvtas x12, s16
+e702641e| gnu fcvtas w7, d23
+f501649e| gnu fcvtas x21, d15
+45ca217e| gnu fcvtau s5, s18
+66c9212e| gnu fcvtau v6.2s, v11.2s
+b302251e| gnu fcvtau w19, s21
+e102259e| gnu fcvtau x1, s23
+5703651e| gnu fcvtau w23, d26
+2c01659e| gnu fcvtau x12, d9
+2c7b210e| gnu fcvtl v12.4s, v25.4h
+f478214e| gnu fcvtl2 v20.4s, v7.8h
+d1b8615e| gnu fcvtms d17, d6
+a2ba614e| gnu fcvtms v2.2d, v21.2d
+ee01301e| gnu fcvtms w14, s15
+de01309e| gnu fcvtms x30, s14
+8401701e| gnu fcvtms w4, d12
+c502709e| gnu fcvtms x5, d22
+44b8617e| gnu fcvtmu d4, d2
+5601311e| gnu fcvtmu w22, s10
+4602319e| gnu fcvtmu x6, s18
+1003711e| gnu fcvtmu w16, d24
+e602719e| gnu fcvtmu x6, d23
+c16b210e| gnu fcvtn v1.4h, v30.4s
+4d6b614e| gnu fcvtn2 v13.4s, v26.2d
+95ab215e| gnu fcvtns s21, s28
+65a9614e| gnu fcvtns v5.2d, v11.2d
+8a02201e| gnu fcvtns w10, s20
+bc03209e| gnu fcvtns x28, s29
+fc01601e| gnu fcvtns w28, d15
+9800609e| gnu fcvtns x24, d4
+b1aa617e| gnu fcvtnu d17, d21
+80a9216e| gnu fcvtnu v0.4s, v12.4s
+3201211e| gnu fcvtnu w18, s9
+e101219e| gnu fcvtnu x1, s15
+ae00611e| gnu fcvtnu w14, d5
+9503619e| gnu fcvtnu x21, d28
+3faae15e| gnu fcvtps d31, d17
+c4a8e14e| gnu fcvtps v4.2d, v6.2d
+ab01281e| gnu fcvtps w11, s13
+5800289e| gnu fcvtps x24, s2
+9b02681e| gnu fcvtps w27, d20
+de03689e| gnu fcvtps x30, d30
+d8aaa17e| gnu fcvtpu s24, s22
+e203291e| gnu fcvtpu w2, s31
+5302299e| gnu fcvtpu x19, s18
+5302691e| gnu fcvtpu w19, d18
+8501699e| gnu fcvtpu x5, d12
+93ff735f| gnu fcvtzs d19, d28, #13
+b7fd504f| gnu fcvtzs v23.2d, v13.2d, #48
+7ebba15e| gnu fcvtzs s30, s27
+d49f181e| gnu fcvtzs w20, s30, #25
+538d189e| gnu fcvtzs x19, s10, #29
+7e74589e| gnu fcvtzs x30, d3, #35
+4300381e| gnu fcvtzs w3, s2
+bc03389e| gnu fcvtzs x28, s29
+c702781e| gnu fcvtzs w7, d22
+0401789e| gnu fcvtzs x4, d8
+d1ff2e7f| gnu fcvtzu s17, s30, #18
+d0fd3b2f| gnu fcvtzu v16.2s, v14.2s, #5
+70bae17e| gnu fcvtzu d16, d19
+3ef6191e| gnu fcvtzu w30, s17, #3
+cae7199e| gnu fcvtzu x10, s30, #7
+cffb599e| gnu fcvtzu x15, d30, #2
+e402391e| gnu fcvtzu w4, s23
+1a03399e| gnu fcvtzu x26, s24
+0401791e| gnu fcvtzu w4, d8
+c200799e| gnu fcvtzu x2, d6
+ebfe346e| gnu fdiv v11.4s, v23.4s, v20.4s
+c918371e| gnu fdiv s9, s6, s23
+911a7f1e| gnu fdiv d17, d20, d31
+a81f0c1f| gnu fmadd s8, s29, s12, s7
+d0404a1f| gnu fmadd d16, d6, d10, d16
+7ff6324e| gnu fmax v31.4s, v19.4s, v18.4s
+b84b351e| gnu fmax s24, s29, s21
+d64b621e| gnu fmax d22, d30, d2
+016b241e| gnu fmaxnm s1, s24, s4
+5b69781e| gnu fmaxnm d27, d10, d24
+f1c8707e| gnu fmaxnmp d17, v7.2d
+27c5306e| gnu fmaxnmp v7.4s, v9.4s, v16.4s
+aef8707e| gnu fmaxp d14, v5.2d
+53f6202e| gnu fmaxp v19.2s, v18.2s, v0.2s
+78fb306e| gnu fmaxv s24, v27.4s
+5af4ec4e| gnu fmin v26.2d, v2.2d, v12.2d
+505a3c1e| gnu fmin s16, s18, s28
+4858661e| gnu fmin d8, d2, d6
+a9c6e04e| gnu fminnm v9.2d, v21.2d, v0.2d
+987b311e| gnu fminnm s24, s28, s17
+95796f1e| gnu fminnm d21, d12, d15
+f5cbb07e| gnu fminnmp s21, v31.2s
+b0f8f07e| gnu fminp d16, v5.2d
+8bf5a42e| gnu fminp v11.2s, v12.2s, v4.2s
+87cd384e| gnu fmla v7.4s, v12.4s, v24.4s
+fd50db5f| gnu fmls d29, d7, v27.d[0]
+d1ccb44e| gnu fmls v17.4s, v6.4s, v20.4s
+ebf5064f| gnu fmov v11.4s, #-2.421875000000000000e-01
+49f4056f| gnu fmov v9.2d, #-9.000000000000000000e+00
+0940201e| gnu fmov s9, s0
+db43601e| gnu fmov d27, d30
+a901271e| gnu fmov s9, w13
+3702261e| gnu fmov w23, s17
+4d02679e| gnu fmov d13, x18
+9d02af9e| gnu fmov v29.d[1], x20
+ef03669e| gnu fmov x15, d31
+7101ae9e| gnu fmov x17, v11.d[1]
+0e103d1e| gnu fmov s14, #-7.500000000000000000e-01
+1e50761e| gnu fmov d30, #-1.800000000000000000e+01
+d2b4121f| gnu fmsub s18, s6, s18, s13
+0a9c4c1f| gnu fmsub d10, d0, d12, d7
+0d99b35f| gnu fmul s13, s8, v19.s[3]
+a89b9b0f| gnu fmul v8.2s, v29.2s, v27.s[2]
+75dc376e| gnu fmul v21.4s, v3.4s, v23.4s
+7909241e| gnu fmul s25, s11, s4
+d7096b1e| gnu fmul d23, d14, d11
+2999ab7f| gnu fmulx s9, s9, v11.s[3]
+35dd6d5e| gnu fmulx d21, d9, d13
+c8dc284e| gnu fmulx v8.4s, v6.4s, v8.4s
+c043211e| gnu fneg s0, s30
+4742611e| gnu fneg d7, d18
+9c51251f| gnu fnmadd s28, s12, s5, s20
+e407771f| gnu fnmadd d4, d31, d23, d1
+fbfa3a1f| gnu fnmsub s27, s23, s26, s30
+bbb0691f| gnu fnmsub d27, d5, d9, d12
+6a8b3f1e| gnu fnmul s10, s27, s31
+1a8b751e| gnu fnmul d26, d24, d21
+57d8e15e| gnu frecpe d23, d2
+62dba14e| gnu frecpe v2.4s, v27.4s
+81fd325e| gnu frecps s1, s12, s18
+31fe224e| gnu frecps v17.4s, v17.4s, v2.4s
+ecf9e15e| gnu frecpx d12, d15
+c18b216e| gnu frinta v1.4s, v30.4s
+0240261e| gnu frinta s2, s0
+8041661e| gnu frinta d0, d12
+c89ba12e| gnu frinti v8.2s, v30.2s
+2ec2271e| gnu frinti s14, s17
+5cc0671e| gnu frinti d28, d2
+3898210e| gnu frintm v24.2s, v1.2s
+9843251e| gnu frintm s24, s28
+5b40651e| gnu frintm d27, d2
+2189614e| gnu frintn v1.2d, v9.2d
+7e42241e| gnu frintn s30, s19
+5d40641e| gnu frintn d29, d2
+85c3241e| gnu frintp s5, s28
+46c2641e| gnu frintp d6, d18
+c39b216e| gnu frintx v3.4s, v30.4s
+a243271e| gnu frintx s2, s29
+1d41671e| gnu frintx d29, d8
+5499e14e| gnu frintz v20.2d, v10.2d
+92c2251e| gnu frintz s18, s20
+75c2651e| gnu frintz d21, d19
+ddd9e17e| gnu frsqrte d29, d14
+60fff85e| gnu frsqrts d0, d27, d24
+dafffb4e| gnu frsqrts v26.2d, v30.2d, v27.2d
+1ff9a12e| gnu fsqrt v31.2s, v8.2s
+2dc3211e| gnu fsqrt s13, s25
+72c0611e| gnu fsqrt d18, d3
+7d3a3e1e| gnu fsub s29, s19, s30
+3f38771e| gnu fsub d31, d1, d23
+185e016e| gnu mov v24.b[0], v16.b[11]
+911d0d4e| gnu mov v17.b[6], w12
+2877400c| gnu ld1 {v8.4h}, [x25]
+8ea8404c| gnu ld1 {v14.4s, v15.4s}, [x4]
+0f62404c| gnu ld1 {v15.16b-v17.16b}, [x16]
+0f27400c| gnu ld1 {v15.4h-v18.4h}, [x24]
+4c75df0c| gnu ld1 {v12.4h}, [x10],#8
+2f7bd04c| gnu ld1 {v15.4s}, [x25], x16
+eaaadf0c| gnu ld1 {v10.2s, v11.2s}, [x23],#16
+eca7cc4c| gnu ld1 {v12.8h, v13.8h}, [sp], x12
+cd60df4c| gnu ld1 {v13.16b-v15.16b}, [x6],#48
+9163df0c| gnu ld1 {v17.8b-v19.8b}, [x28],#24
+152ddf4c| gnu ld1 {v21.2d-v24.2d}, [x8],#64
+0725c04c| gnu ld1 {v7.8h-v10.8h}, [x8], x0
+7c04404d| gnu ld1 {v28.b}[9], [x3]
+6d49404d| gnu ld1 {v13.h}[5], [x11]
+9e81400d| gnu ld1 {v30.s}[0], [x12]
+d384404d| gnu ld1 {v19.d}[1], [x6]
+b20ddf4d| gnu ld1 {v18.b}[11], [x13],#1
+f114cd4d| gnu ld1 {v17.b}[13], [x7], x13
+bb92df4d| gnu ld1 {v27.s}[3], [x21],#4
+a883d64d| gnu ld1 {v8.s}[2], [x29], x22
+f584df4d| gnu ld1 {v21.d}[1], [x7],#8
+0284c80d| gnu ld1 {v2.d}[0], [x0], x8
+91c3400d| gnu ld1r {v17.8b}, [x28]
+71c9df0d| gnu ld1r {v17.2s}, [x11],#4
+e7c4db0d| gnu ld1r {v7.4h}, [x7], x27
+b787404c| gnu ld2 {v23.8h, v24.8h}, [x29]
+1280df0c| gnu ld2 {v18.8b, v19.8b}, [x0],#16
+2f88c10c| gnu ld2 {v15.2s, v16.2s}, [x1], x1
+a01e604d| gnu ld2 {v0.b, v1.b}[15], [x21]
+eb82604d| gnu ld2 {v11.s, v12.s}[2], [x23]
+f985600d| gnu ld2 {v25.d, v26.d}[0], [x15]
+e315ff0d| gnu ld2 {v3.b, v4.b}[5], [x15],#2
+1c11f24d| gnu ld2 {v28.b, v29.b}[12], [x8], x18
+f341ef4d| gnu ld2 {v19.h, v20.h}[4], [x15], x15
+5a80ff4d| gnu ld2 {v26.s, v27.s}[2], [x2],#8
+d781fd0d| gnu ld2 {v23.s, v24.s}[0], [x14], x29
+c885ff0d| gnu ld2 {v8.d, v9.d}[0], [x14],#16
+1286f34d| gnu ld2 {v18.d, v19.d}[1], [x16], x19
+06c2600d| gnu ld2r {v6.8b, v7.8b}, [x16]
+95c7ff4d| gnu ld2r {v21.8h, v22.8h}, [x28],#4
+d4c1e14d| gnu ld2r {v20.16b, v21.16b}, [x14], x1
+eb4bdf4c| gnu ld3 {v11.4s-v13.4s}, [sp],#48
+ce4fc24c| gnu ld3 {v14.2d-v16.2d}, [x30], x2
+db23400d| gnu ld3 {v27.b-v29.b}[0], [x30]
+26b3400d| gnu ld3 {v6.s-v8.s}[1], [x25]
+37a4400d| gnu ld3 {v23.d-v25.d}[0], [x1]
+052edf4d| gnu ld3 {v5.b-v7.b}[11], [x16],#3
+8c3ccd0d| gnu ld3 {v12.b-v14.b}[7], [x4], x13
+74b0df4d| gnu ld3 {v20.s-v22.s}[3], [x3],#12
+b7b1c84d| gnu ld3 {v23.s-v25.s}[3], [x13], x8
+e6a5df4d| gnu ld3 {v6.d-v8.d}[1], [x15],#24
+42a5c80d| gnu ld3 {v2.d-v4.d}[0], [x10], x8
+9ceb400d| gnu ld3r {v28.2s-v30.2s}, [x28]
+6aeadf4d| gnu ld3r {v10.4s-v12.4s}, [x19],#12
+65ebce4d| gnu ld3r {v5.4s-v7.4s}, [x27], x14
+ea05400c| gnu ld4 {v10.4h-v13.4h}, [x15]
+1f03df0c| gnu ld4 {v31.8b, v0.8b, v1.8b, v2.8b}, [x24],#32
+ae09c90c| gnu ld4 {v14.2s-v17.2s}, [x13], x9
+fd3a604d| gnu ld4 {v29.b, v30.b, v31.b, v0.b}[14], [x23]
+d8a0604d| gnu ld4 {v24.s-v27.s}[2], [x6]
+62a4604d| gnu ld4 {v2.d-v5.d}[1], [x3]
+712fff0d| gnu ld4 {v17.b-v20.b}[3], [x27],#4
+aa27f40d| gnu ld4 {v10.b-v13.b}[1], [x29], x20
+be71ff4d| gnu ld4 {v30.h, v31.h, v0.h, v1.h}[6], [x13],#8
+e360ee4d| gnu ld4 {v3.h-v6.h}[4], [x7], x14
+c0a0ff0d| gnu ld4 {v0.s-v3.s}[0], [x6],#16
+d3a3e00d| gnu ld4 {v19.s-v22.s}[0], [x30], x0
+95a7ff0d| gnu ld4 {v21.d-v24.d}[0], [x28],#32
+32a6e14d| gnu ld4 {v18.d-v21.d}[1], [x17], x1
+56e0604d| gnu ld4r {v22.16b-v25.16b}, [x2]
+dce7ff0d| gnu ld4r {v28.4h-v31.4h}, [x30],#8
+14e8ef0d| gnu ld4r {v20.2s-v23.2s}, [x0], x15
+7776732c| gnu ldnp s23, s29, [x19,#-104]
+23dd746c| gnu ldnp d3, d23, [x9,#-184]
+383e48ac| gnu ldnp q24, q15, [x17,#256]
+0d10c12c| gnu ldp s13, s4, [x0],#8
+fe3ae66c| gnu ldp d30, d14, [x23],#-416
+f627f9ac| gnu ldp q22, q9, [sp],#-224
+918cd82d| gnu ldp s17, s3, [x4,#196]!
+986be46d| gnu ldp d24, d26, [x28,#-448]!
+ebd8f8ad| gnu ldp q11, q22, [x7,#-240]!
+3c905c2d| gnu ldp s28, s4, [x1,#228]
+5887536d| gnu ldp d24, d1, [x26,#312]
+08957cad| gnu ldp q8, q5, [x8,#-112]
+c5e5543c| gnu ldr b5, [x14],#-178
+4ff5417c| gnu ldr h15, [x10],#31
+72e54bbc| gnu ldr s18, [x11],#190
+16b55dfc| gnu ldr d22, [x8],#-37
+9e24db3c| gnu ldr q30, [x4],#-78
+d20c503c| gnu ldr b18, [x6,#-256]!
+1f1c4d7c| gnu ldr h31, [x0,#209]!
+2fbf4dbc| gnu ldr s15, [x25,#219]!
+a06c59fc| gnu ldr d0, [x5,#-106]!
+886ddd3c| gnu ldr q8, [x12,#-42]!
+58f64e3d| gnu ldr b24, [x18,#957]
+f5c3547d| gnu ldr h21, [sp,#2656]
+8e8a7bbd| gnu ldr s14, [x20,#15240]
+8e3c7afd| gnu ldr d14, [x4,#29816]
+f2aeff3d| gnu ldr q18, [x23,#65200]
+92831b1c| gnu ldr s18, .+0x37070
+3e01b55c| gnu ldr d30, .+0xfffffffffff6a024
+fdee3b9c| gnu ldr q29, .+0x77ddc
+1d78793c| gnu ldr b29, [x0,x25,lsl #0]
+b8f15d3c| gnu ldur b24, [x13,#-33]
+95635c7c| gnu ldur h21, [x28,#-58]
+27d046bc| gnu ldur s7, [x1,#109]
+21624efc| gnu ldur d1, [x17,#230]
+6dd2d83c| gnu ldur q13, [x19,#-115]
+dc09be6f| gnu mla v28.4s, v14.4s, v30.s[3]
+eb97af4e| gnu mla v11.4s, v31.4s, v15.4s
+0495722e| gnu mls v4.4h, v8.4h, v18.4h
+21070a5e| gnu mov h1, v25.h[2]
+92471b6e| gnu mov v18.b[13], v28.b[8]
+7a1e134e| gnu mov v26.b[9], w19
+761fa30e| gnu orr v22.8b, v27.8b, v3.8b
+f23d070e| gnu umov w18, v15.b[3]
+a5e6064f| gnu movi v5.16b, #0xd5
+63c5064f| gnu movi v3.4s, #0xcb, msl #8
+bca7014f| gnu movi v28.8h, #0x3d, lsl #8
+95e4040f| gnu movi v21.8b, #0x84
+fce4072f| gnu movi d28, #0xffffff0000ffffff
+24e6036f| gnu movi v4.2d, #0xffffff000000ff
+429d6a4e| gnu mul v2.8h, v10.8h, v10.8h
+e558202e| gnu mvn v5.8b, v7.8b
+fe65012f| gnu mvni v30.2s, #0x2f, lsl #24
+2b16046f| gnu bic v11.4s, #0x91
+7756016f| gnu bic v23.4s, #0x33, lsl #16
+e159202e| gnu mvn v1.8b, v15.8b
+da1cf14e| gnu orn v26.16b, v6.16b, v17.16b
+ca04014f| gnu movi v10.4s, #0x26
+14a6020f| gnu movi v20.4h, #0x50, lsl #8
+2f1fbf0e| gnu orr v15.8b, v25.8b, v31.8b
+74e2f20e| gnu pmull v20.1q, v19.1d, v18.1d
+2740262e| gnu raddhn v7.8b, v1.8h, v6.8h
+17412e6e| gnu raddhn2 v23.16b, v8.8h, v14.8h
+da59602e| gnu rbit v26.8b, v14.8b
+230a604e| gnu rev64 v3.8h, v17.8h
+178d210f| gnu rshrn v23.2s, v8.2d, #31
+6b8d2c4f| gnu rshrn2 v11.4s, v11.2d, #20
+b57c2a0e| gnu saba v21.8b, v5.8b, v10.8b
+71533d0e| gnu sabal v17.8h, v27.8b, v29.8b
+1c50774e| gnu sabal2 v28.4s, v0.8h, v23.8h
+1974be4e| gnu sabd v25.4s, v0.4s, v30.4s
+6b71ad0e| gnu sabdl v11.2d, v11.2s, v13.2s
+5270324e| gnu sabdl2 v18.8h, v2.16b, v18.16b
+366b200e| gnu sadalp v22.4h, v25.8b
+1802680e| gnu saddl v24.4s, v16.4h, v8.4h
+022b604e| gnu saddlp v2.4s, v24.8h
+413ab04e| gnu saddlv d1, v18.4s
+4013750e| gnu saddw v0.4s, v26.4s, v21.4h
+4412744e| gnu saddw2 v4.4s, v18.4s, v20.8h
+2ee6255f| gnu scvtf s14, s17, #27
+dce75f4f| gnu scvtf v28.2d, v30.2d, #33
+5bdb615e| gnu scvtf d27, d26
+3ad9210e| gnu scvtf v26.2s, v9.2s
+1ceb421e| gnu scvtf d28, w24, #6
+9dde029e| gnu scvtf s29, x20, #9
+57d1429e| gnu scvtf d23, x10, #12
+d600221e| gnu scvtf s22, w6
+c503621e| gnu scvtf d5, w30
+3303229e| gnu scvtf s19, x25
+0003629e| gnu scvtf d0, x24
+6f01075e| gnu sha1c q15, s11, v7.4s
+9308285e| gnu sha1h s19, s4
+b420105e| gnu sha1m q20, s5, v16.4s
+f4131f5e| gnu sha1p q20, s31, v31.4s
+dc311f5e| gnu sha1su0 v28.4s, v14.4s, v31.4s
+bb1a285e| gnu sha1su1 v27.4s, v21.4s
+2753075e| gnu sha256h2 q7, q25, v7.4s
+3141065e| gnu sha256h q17, q9, v6.4s
+172b285e| gnu sha256su0 v23.4s, v24.4s
+bb621b5e| gnu sha256su1 v27.4s, v21.4s, v27.4s
+7005644e| gnu shadd v16.8h, v11.8h, v4.8h
+2d870e0f| gnu shrn v13.8b, v25.8h, #2
+ac86024f| gnu movi v12.8h, #0x55
+1c26a50e| gnu shsub v28.2s, v16.2s, v5.2s
+db576b6f| gnu sli v27.2d, v30.2d, #43
+c3652c4e| gnu smax v3.16b, v14.16b, v12.16b
+b5a7ab0e| gnu smaxp v21.2s, v29.2s, v11.2s
+f1aeb34e| gnu sminp v17.4s, v23.4s, v19.4s
+87a8b14e| gnu sminv s7, v4.4s
+1e21bc4f| gnu smlal2 v30.2d, v8.4s, v28.s[1]
+50a33a0e| gnu smlsl v16.8h, v26.8b, v26.8b
+4e2d1a0e| gnu smov w14, v10.h[6]
+9ba9b30f| gnu smull v27.2d, v12.2s, v19.s[3]
+417a205e| gnu sqabs b1, b18
+9f78a04e| gnu sqabs v31.4s, v4.4s
+580d2e5e| gnu sqadd b24, b10, b14
+3d30764f| gnu sqdmlal2 v29.4s, v1.8h, v6.h[3]
+9591b25e| gnu sqdmlal d21, s12, s18
+0d92670e| gnu sqdmlal v13.4s, v16.4h, v7.4h
+90b1765e| gnu sqdmlsl s16, h12, h22
+83c2ad5f| gnu sqdmulh s3, s20, v13.s[1]
+bbb7aa5e| gnu sqdmulh s27, s29, s10
+c8b99a5f| gnu sqdmull d8, s14, v26.s[2]
+75b3920f| gnu sqdmull v21.2d, v27.2s, v18.s[0]
+86d1b75e| gnu sqdmull d6, s12, s23
+edd06f4e| gnu sqdmull2 v13.4s, v7.8h, v15.8h
+0f7ae07e| gnu sqneg d15, d16
+e87b602e| gnu sqneg v8.4h, v31.4h
+ecb5a92e| gnu sqrdmulh v12.2s, v15.2s, v9.2s
+d75fba5e| gnu sqrshl s23, s30, s26
+f75f324e| gnu sqrshl v23.16b, v31.16b, v18.16b
+af9c114f| gnu sqrshrn2 v15.8h, v5.4s, #15
+318d2f6f| gnu sqrshrun2 v17.4s, v9.2d, #17
+b3757c5f| gnu sqshl d19, d13, #60
+0c776f4f| gnu sqshl v12.2d, v24.2d, #47
+d84c2a5e| gnu sqshl b24, b6, b10
+ae4e704e| gnu sqshl v14.8h, v21.8h, v16.8h
+b566727f| gnu sqshlu d21, d21, #50
+4566596f| gnu sqshlu v5.2d, v18.2d, #25
+d595140f| gnu sqshrn v21.4h, v14.4s, #12
+00940b4f| gnu sqshrn2 v0.16b, v0.8h, #5
+5384352f| gnu sqshrun v19.2s, v2.2d, #11
+1a2e3d5e| gnu sqsub b26, b16, b29
+b02e6b4e| gnu sqsub v16.8h, v21.8h, v11.8h
+1249a15e| gnu sqxtn s18, d8
+eb49610e| gnu sqxtn v11.4h, v15.4s
+cb4a614e| gnu sqxtn2 v11.8h, v22.4s
+102b217e| gnu sqxtun b16, h24
+492a212e| gnu sqxtun v9.8b, v18.8h
+112a616e| gnu sqxtun2 v17.8h, v16.4s
+6c16ae4e| gnu srhadd v12.4s, v19.4s, v14.4s
+5946467f| gnu sri d25, d18, #58
+21460a2f| gnu sri v1.8b, v17.8b, #6
+9f56b10e| gnu srshl v31.2s, v20.2s, v17.2s
+e724635f| gnu srshr d7, d7, #29
+e8266b4f| gnu srshr v8.2d, v23.2d, #21
+2b37180f| gnu srsra v11.4h, v25.4h, #8
+1644f95e| gnu sshl d22, d0, d25
+3644fc4e| gnu sshl v22.2d, v1.2d, v28.2d
+d9a61f4f| gnu sshll2 v25.4s, v22.8h, #15
+9b075e5f| gnu sshr d27, d28, #34
+2c044c4f| gnu sshr v12.2d, v1.2d, #52
+d915324f| gnu ssra v25.4s, v14.4s, #14
+de21260e| gnu ssubl v30.8h, v14.8b, v6.8b
+c720254e| gnu ssubl2 v7.8h, v6.16b, v5.16b
+9d33b90e| gnu ssubw v29.2d, v28.2d, v25.2s
+7e71000c| gnu st1 {v30.8b}, [x11]
+cca6000c| gnu st1 {v12.4h, v13.4h}, [x22]
+5467000c| gnu st1 {v20.4h-v22.4h}, [x26]
+cc28004c| gnu st1 {v12.4s-v15.4s}, [x6]
+9e7e9f4c| gnu st1 {v30.2d}, [x20],#16
+4b769d0c| gnu st1 {v11.4h}, [x18], x29
+adaa9f0c| gnu st1 {v13.2s, v14.2s}, [x21],#16
+bca7844c| gnu st1 {v28.8h, v29.8h}, [x29], x4
+b5659f0c| gnu st1 {v21.4h-v23.4h}, [x13],#24
+e669874c| gnu st1 {v6.4s-v8.4s}, [x15], x7
+9b2a9f0c| gnu st1 {v27.2s-v30.2s}, [x20],#32
+14278b0c| gnu st1 {v20.4h-v23.4h}, [x24], x11
+d002004d| gnu st1 {v16.b}[8], [x22]
+9780004d| gnu st1 {v23.s}[2], [x4]
+7787004d| gnu st1 {v23.d}[1], [x27]
+850d9f0d| gnu st1 {v5.b}[3], [x12],#1
+7b1f8f0d| gnu st1 {v27.b}[7], [x27], x15
+7a5a9f4d| gnu st1 {v26.h}[7], [x19],#2
+e14b9e4d| gnu st1 {v1.h}[5], [sp], x30
+dd819f4d| gnu st1 {v29.s}[2], [x14],#4
+a281910d| gnu st1 {v2.s}[0], [x13], x17
+b2849f0d| gnu st1 {v18.d}[0], [x5],#8
+c484964d| gnu st1 {v4.d}[1], [x6], x22
+f686004c| gnu st2 {v22.8h, v23.8h}, [x23]
+2e869f0c| gnu st2 {v14.4h, v15.4h}, [x17],#16
+d200200d| gnu st2 {v18.b, v19.b}[0], [x6]
+ab58200d| gnu st2 {v11.h, v12.h}[3], [x5]
+c491204d| gnu st2 {v4.s, v5.s}[3], [x14]
+5a85204d| gnu st2 {v26.d, v27.d}[1], [x10]
+f217bf0d| gnu st2 {v18.b, v19.b}[5], [sp],#2
+2b0ea04d| gnu st2 {v11.b, v12.b}[11], [x17], x0
+4042bf0d| gnu st2 {v0.h, v1.h}[0], [x18],#4
+9342af4d| gnu st2 {v19.h, v20.h}[4], [x20], x15
+9b91bf4d| gnu st2 {v27.s, v28.s}[3], [x12],#8
+7480a10d| gnu st2 {v20.s, v21.s}[0], [x3], x1
+c884bf0d| gnu st2 {v8.d, v9.d}[0], [x6],#16
+ae86ac4d| gnu st2 {v14.d, v15.d}[1], [x21], x12
+614d004c| gnu st3 {v1.2d-v3.2d}, [x11]
+324b9f4c| gnu st3 {v18.4s-v20.4s}, [x25],#48
+7340870c| gnu st3 {v19.8b-v21.8b}, [x3], x7
+ac24004d| gnu st3 {v12.b-v14.b}[9], [x5]
+a161004d| gnu st3 {v1.h-v3.h}[4], [x13]
+09b1004d| gnu st3 {v9.s-v11.s}[3], [x8]
+78a7004d| gnu st3 {v24.d-v26.d}[1], [x27]
+4f349f0d| gnu st3 {v15.b-v17.b}[5], [x2],#3
+643d840d| gnu st3 {v4.b-v6.b}[7], [x11], x4
+48699f0d| gnu st3 {v8.h-v10.h}[1], [x10],#6
+85b19f4d| gnu st3 {v5.s-v7.s}[3], [x12],#12
+60a18a0d| gnu st3 {v0.s-v2.s}[0], [x11], x10
+69a49f0d| gnu st3 {v9.d-v11.d}[0], [x3],#24
+ada7814d| gnu st3 {v13.d-v15.d}[1], [x29], x1
+760c004c| gnu st4 {v22.2d-v25.2d}, [x3]
+ee0d9f4c| gnu st4 {v14.2d-v17.2d}, [x15],#64
+7800970c| gnu st4 {v24.8b-v27.8b}, [x3], x23
+a221200d| gnu st4 {v2.b-v5.b}[0], [x13]
+9a69204d| gnu st4 {v26.h-v29.h}[5], [x12]
+02a1204d| gnu st4 {v2.s-v5.s}[2], [x8]
+3fa6200d| gnu st4 {v31.d, v0.d, v1.d, v2.d}[0], [x17]
+943abf0d| gnu st4 {v20.b-v23.b}[6], [x20],#4
+bf26a60d| gnu st4 {v31.b, v0.b, v1.b, v2.b}[1], [x21], x6
+55b3bf4d| gnu st4 {v21.s-v24.s}[3], [x26],#16
+dda1b04d| gnu st4 {v29.s, v30.s, v31.s, v0.s}[2], [x14], x16
+6aa5bf0d| gnu st4 {v10.d-v13.d}[0], [x11],#32
+e7a7ac0d| gnu st4 {v7.d-v10.d}[0], [sp], x12
+f9c9202c| gnu stnp s25, s18, [x15,#-252]
+18b8316c| gnu stnp d24, d14, [x0,#-232]
+409c1cac| gnu stnp q0, q7, [x2,#912]
+73f0812c| gnu stp s19, s28, [x3],#12
+28d0826c| gnu stp d8, d20, [x1],#40
+9bf5bfac| gnu stp q27, q29, [x12],#-16
+885ead2d| gnu stp s8, s23, [x20,#-152]!
+b0de926d| gnu stp d16, d23, [x21,#296]!
+713387ad| gnu stp q17, q12, [x27,#224]!
+52130a2d| gnu stp s18, s4, [x26,#80]
+b63a236d| gnu stp d22, d14, [x21,#-464]
+6d5424ad| gnu stp q13, q21, [x3,#-896]
+afb60f3c| gnu str b15, [x21],#251
+81e7077c| gnu str h1, [x28],#126
+203713bc| gnu str s0, [x25],#-205
+60c61ffc| gnu str d0, [x19],#-4
+d256813c| gnu str q18, [x22],#21
+ffce083c| gnu str b31, [x23,#140]!
+6d3d017c| gnu str h13, [x11,#19]!
+52ed01bc| gnu str s18, [x10,#30]!
+fafd11fc| gnu str d26, [x15,#-225]!
+663e9b3c| gnu str q6, [x19,#-77]!
+7d0c393d| gnu str b29, [x3,#3651]
+8f50067d| gnu str h15, [x4,#808]
+94680dbd| gnu str s20, [x4,#3432]
+b7673bfd| gnu str d23, [x29,#30408]
+fed3a63d| gnu str q30, [sp,#39744]
+8a6a243c| gnu str b10, [x20,x4]
+29493fbc| gnu str s9, [x9,wzr,uxtw]
+8bd93bfc| gnu str d11, [x12,w27,sxtw #3]
+c768a93c| gnu str q7, [x6,x9]
+a7b00a3c| gnu stur b7, [x5,#171]
+40e3107c| gnu stur h0, [x26,#-242]
+18911fbc| gnu stur s24, [x8,#-7]
+fcc007fc| gnu stur d28, [x7,#124]
+db12893c| gnu stur q27, [x22,#145]
+1686716e| gnu sub v22.8h, v16.8h, v17.8h
+5362320e| gnu subhn v19.8b, v18.8h, v18.8h
+6163bf4e| gnu subhn2 v1.4s, v27.2d, v31.2d
+a73be05e| gnu suqadd d7, d29
+21a4100f| gnu sxtl v1.4s, v1.4h
+8b23164e| gnu tbl v11.16b, {v28.16b, v29.16b}, v22.16b
+3642120e| gnu tbl v22.8b, {v17.16b-v19.16b}, v18.8b
+cf611f0e| gnu tbl v15.8b, {v14.16b-v17.16b}, v31.8b
+0b020e4e| gnu tbl v11.16b, {v16.16b}, v14.16b
+9830014e| gnu tbx v24.16b, {v4.16b, v5.16b}, v1.16b
+1452044e| gnu tbx v20.16b, {v16.16b-v18.16b}, v4.16b
+b4711a0e| gnu tbx v20.8b, {v13.16b-v16.16b}, v26.8b
+f911140e| gnu tbx v25.8b, {v15.16b}, v20.8b
+9f28500e| gnu trn1 v31.4h, v4.4h, v16.4h
+2e69c64e| gnu trn2 v14.2d, v9.2d, v6.2d
+c752756e| gnu uabal2 v7.4s, v22.8h, v21.8h
+8675696e| gnu uabd v6.8h, v12.8h, v9.8h
+a973ab6e| gnu uabdl2 v9.2d, v29.4s, v11.4s
+fa006c2e| gnu uaddl v26.4s, v7.4h, v12.4h
+da00236e| gnu uaddl2 v26.8h, v6.16b, v3.16b
+ab3a306e| gnu uaddlv h11, v21.16b
+a312746e| gnu uaddw2 v3.4s, v21.4s, v20.8h
+cee55e7f| gnu ucvtf d14, d14, #34
+8edb617e| gnu ucvtf d14, d28
+ab8f431e| gnu ucvtf d11, w29, #29
+68b3039e| gnu ucvtf s8, x27, #20
+7686439e| gnu ucvtf d22, x19, #31
+2a03231e| gnu ucvtf s10, w25
+9f01631e| gnu ucvtf d31, w12
+a800239e| gnu ucvtf s8, x5
+0302639e| gnu ucvtf d3, x16
+df65a42e| gnu umax v31.2s, v14.2s, v4.2s
+29ab702e| gnu umaxv h9, v25.4h
+6f6e2e6e| gnu umin v15.16b, v19.16b, v14.16b
+fdada32e| gnu uminp v29.2s, v15.2s, v3.2s
+07289a6f| gnu umlal2 v7.2d, v0.4s, v26.s[2]
+aa80ad2e| gnu umlal v10.2d, v5.2s, v13.2s
+d66b462f| gnu umlsl v22.4s, v30.4h, v6.h[4]
+12a3b62e| gnu umlsl v18.2d, v24.2s, v22.2s
+583e0d0e| gnu umov w24, v18.b[6]
+20c3b52e| gnu umull v0.2d, v25.2s, v21.2s
+20c2616e| gnu umull2 v0.4s, v17.8h, v1.8h
+2f0f6d7e| gnu uqadd h15, h25, h13
+a60c272e| gnu uqadd v6.8b, v5.8b, v7.8b
+5b5da27e| gnu uqrshl s27, s10, s2
+195c786e| gnu uqrshl v25.8h, v0.8h, v24.8h
+209e282f| gnu uqrshrn v0.2s, v17.2d, #24
+e89e3b6f| gnu uqrshrn2 v8.4s, v23.2d, #5
+4f75147f| gnu uqshl h15, h10, #4
+d2767d6f| gnu uqshl v18.2d, v22.2d, #61
+bb4cfe7e| gnu uqshl d27, d5, d30
+794ea42e| gnu uqshl v25.2s, v19.2s, v4.2s
+51960b7f| gnu uqshrn b17, h18, #5
+642ce77e| gnu uqsub d4, d3, d7
+6149617e| gnu uqxtn h1, s11
+4e48a12e| gnu uqxtn v14.2s, v2.2d
+9cc8a14e| gnu urecpe v28.4s, v4.4s
+2f15a52e| gnu urhadd v15.2s, v9.2s, v5.2s
+5757fb7e| gnu urshl d23, d26, d27
+2756706e| gnu urshl v7.8h, v17.8h, v16.8h
+a424487f| gnu urshr d4, d5, #56
+b926796f| gnu urshr v25.2d, v21.2d, #7
+1336076f| gnu bic v19.4s, #0xf0, lsl #8
+e347e06e| gnu ushl v3.2d, v31.2d, v0.2d
+f7a5272f| gnu ushll v23.2d, v15.2s, #7
+9ba63d6f| gnu ushll2 v27.2d, v20.4s, #29
+d405737f| gnu ushr d20, d14, #13
+3a05116f| gnu ushr v26.8h, v9.8h, #15
+1d39607e| gnu usqadd h29, h8
+0e39e06e| gnu usqadd v14.2d, v8.2d
+8022b02e| gnu usubl v0.2d, v20.2s, v16.2s
+9a20786e| gnu usubl2 v26.4s, v4.8h, v24.8h
+df33692e| gnu usubw v31.4s, v30.4s, v9.4h
+92a5102f| gnu uxtl v18.4s, v12.4h
+0e19464e| gnu uzp1 v14.8h, v8.8h, v6.8h
+7629610e| gnu xtn v22.4h, v11.4s
+7338504e| gnu zip1 v19.8h, v3.8h, v16.8h
+357bd64e| gnu zip2 v21.2d, v25.2d, v22.2d
+63020f1a| gnu adc w3, w19, w15
+1f03159a| gnu adc xzr, x24, x21
+d300103a| gnu adcs w19, w6, w16
+1b0010ba| gnu adcs x27, x0, x16
+dd133f0b| gnu add w29, w30, wzr, uxtb #4
+89c42f8b| gnu add x9, x4, w15, sxtw #1
+4e242a11| gnu add w14, w2, #0xa89
+e1c12f2b| gnu adds w1, w15, w15, sxtw
+733421ab| gnu adds x19, x3, w1, uxth #5
+0ccc5aab| gnu adds x12, x0, x26, lsr #51
+51354470| gnu adr x17, .+0x886ab
+ef6796d0| gnu adrp x15, .+0xffffffff2ccfe000
+2e122612| gnu and w14, w17, #0x7c000000
+5e4c2992| gnu and x30, x2, #0xff8007ffff8007ff
+2805410a| gnu and w8, w9, w1, lsr #1
+ede1938a| gnu and x13, x15, x19, asr #56
+e7c10f72| gnu ands w7, w15, #0x2020202
+23ed55f2| gnu ands x3, x9, #0xfffff87fffffffff
+e6935bea| gnu ands x6, xzr, x27, lsr #36
+0e2ac61a| gnu asr w14, w16, w6
+802ad59a| gnu asr x0, x20, x21
+7cfd7793| gnu asr x28, x11, #55
+f028cd1a| gnu asr w16, w7, w13
+132bd29a| gnu asr x19, x24, x18
+c2560e54| gnu b.cs .+0x1cad8
+83516b17| gnu b .+0xfffffffffdad460c
+7a571233| gnu bfxil w26, w27, #18, #4
+71b858b3| gnu bfxil x17, x3, #24, #23
+c3964bb3| gnu bfxil x3, x22, #11, #27
+eb561233| gnu bfxil w11, w23, #18, #4
+063f5db3| gnu bfi x6, x24, #35, #16
+0a337a0a| gnu bic w10, w24, w26, lsr #12
+2a71e28a| gnu bic x10, x9, x2, ror #28
+c168bf6a| gnu bics w1, w6, wzr, asr #26
+d8bb3cea| gnu bics x24, x30, x28, lsl #46
+82e81795| gnu bl .+0x45fa208
+40033fd6| gnu blr x26
+c0011fd6| gnu br x14
+00dd31d4| gnu brk #0x8ee8
+7267db35| gnu cbnz w18, .+0xfffffffffffb6cec
+e44c7fb5| gnu cbnz x4, .+0xfe99c
+9dc4c334| gnu cbz w29, .+0xfffffffffff87890
+376eceb4| gnu cbz x23, .+0xfffffffffff9cdc4
+a6cb563a| gnu ccmn w29, #0x16, #0x6, gt
+87db55ba| gnu ccmn x28, #0x15, #0x7, le
+a042493a| gnu ccmn w21, w9, #0x0, mi
+6a0040ba| gnu ccmn x3, x0, #0xa, eq
+46bb5c7a| gnu ccmp w26, #0x1c, #0x6, lt
+c72942fa| gnu ccmp x14, #0x2, #0x7, cs
+cda1427a| gnu ccmp w14, w2, #0xd, ge
+a1314dfa| gnu ccmp x13, x13, #0x1, cc
+8706931a| gnu csinc w7, w20, w19, eq
+3ae69a9a| gnu csinc x26, x17, x26, al
+9e51945a| gnu csinv w30, w12, w20, pl
+d5e386da| gnu csinv x21, x30, x6, al
+5f3503d5| gnu clrex #0x5
+e515c05a| gnu cls w5, w15
+a815c0da| gnu cls x8, x13
+4a12c05a| gnu clz w10, w18
+3c10c0da| gnu clz x28, x1
+ff70252b| gnu cmn w7, w5, uxtx #4
+9fa133ab| gnu cmn x12, w19, sxth
+3f3a822b| gnu cmn w17, w2, asr #14
+df1d44ab| gnu cmn x14, x4, lsr #7
+3f95386b| gnu cmp w9, w24, sxtb #5
+9f653feb| gnu cmp x12, xzr, uxtx #1
+1626915a| gnu csneg w22, w16, w17, cs
+b4d587da| gnu csneg x20, x13, x7, le
+9841d41a| gnu crc32b w24, w12, w20
+ec45d01a| gnu crc32h w12, w15, w16
+8048ca1a| gnu crc32w w0, w4, w10
+d44ec19a| gnu crc32x w20, w22, x1
+1552d31a| gnu crc32cb w21, w16, w19
+4b54c71a| gnu crc32ch w11, w2, w7
+245ad41a| gnu crc32cw w4, w17, w20
+c35cc89a| gnu crc32cx w3, w6, x8
+14219f1a| gnu csel w20, w8, wzr, cs
+9c73979a| gnu csel x28, x28, x23, vc
+e7279f1a| gnu cset w7, cc
+ec579f9a| gnu cset x12, mi
+e5f39f5a| gnu csinv w5, wzr, wzr, al
+e8639fda| gnu csetm x8, vc
+ea76971a| gnu cinc w10, w23, vs
+78a7859a| gnu csinc x24, x27, x5, ge
+b590845a| gnu csinv w21, w5, w4, ls
+b4029eda| gnu csinv x20, x21, x30, eq
+b3969b5a| gnu csneg w19, w21, w27, ls
+938591da| gnu csneg x19, x12, x17, hi
+016ea8d4| gnu dcps1 #0x4370
+0275a4d4| gnu dcps2 #0x23a8
+a3e9a6d4| gnu dcps3 #0x374d
+bf3903d5| gnu dmb ishld
+e003bfd6| gnu drps
+9f3e03d5| gnu dsb st
+50b1a0ca| gnu eon x16, x10, x0, asr #44
+c0b02f52| gnu eor w0, w6, #0x3ffe3ffe
+4b0c1ed2| gnu eor x11, x2, #0x3c0000003c
+693c074a| gnu eor w9, w3, w7, lsl #15
+113e1aca| gnu eor x17, x16, x26, lsl #15
+e0039fd6| gnu eret
+fef8c693| gnu extr x30, x7, x6, #62
+3f2003d5| gnu yield
+3f2403d5| gnu hint #0x21
+c0425ad4| gnu hlt #0xd216
+df3003d5| gnu isb #0x0
+f7fddf88| gnu ldar w23, [x15]
+96fedfc8| gnu ldar x22, [x20]
+11fedf08| gnu ldarb w17, [x16]
+c2fedf48| gnu ldarh w2, [x22]
+2d927f88| gnu ldaxp w13, w4, [x17]
+198f7fc8| gnu ldaxp x25, x3, [x24]
+46ff5f88| gnu ldaxr w6, [x26]
+81fe5fc8| gnu ldaxr x1, [x20]
+86fe5f08| gnu ldaxrb w6, [x20]
+78ff5f48| gnu ldaxrh w24, [x27]
+35864a28| gnu ldnp w21, w1, [x17,#84]
+6da05fa8| gnu ldnp x13, x8, [x3,#504]
+a8f9f428| gnu ldp w8, w30, [x13],#-92
+b749e3a8| gnu ldp x23, x18, [x13],#-464
+bdedd929| gnu ldp w29, w27, [x13,#204]!
+c8e5c6a9| gnu ldp x8, x25, [x14,#104]!
+c0857f29| gnu ldp w0, w1, [x14,#-4]
+388a6ca9| gnu ldp x24, x2, [x17,#-312]
+086be468| gnu ldpsw x8, x26, [x24],#-224
+d107d269| gnu ldpsw x17, x1, [x30,#144]!
+738e4e69| gnu ldpsw x19, x3, [x19,#116]
+6ee55fb8| gnu ldr w14, [x11],#-2
+233459f8| gnu ldr x3, [x1],#-109
+919f44b8| gnu ldr w17, [x28,#73]!
+acdd45f8| gnu ldr x12, [x13,#93]!
+e1cd51b9| gnu ldr w1, [x15,#4556]
+95e27bf9| gnu ldr x21, [x20,#30656]
+09c4fa18| gnu ldr w9, .+0xffffffffffff5880
+f528ad58| gnu ldr x21, .+0xfffffffffff5a51c
+0c554b38| gnu ldrb w12, [x8],#181
+054f5938| gnu ldrb w5, [x24,#-108]!
+1f206539| gnu ldrb wzr, [x0,#2376]
+73796a38| gnu ldrb w19, [x11,x10,lsl #0]
+a8b74f78| gnu ldrh w8, [x29],#251
+021e5e78| gnu ldrh w2, [x16,#-31]!
+ec126b79| gnu ldrh w12, [x23,#5512]
+fc5a6178| gnu ldrh w28, [x23,w1,uxtw #1]
+eaf6c238| gnu ldrsb w10, [x23],#47
+87679838| gnu ldrsb x7, [x28],#-122
+567fdb38| gnu ldrsb w22, [x26,#-73]!
+3b2e8138| gnu ldrsb x27, [x17,#18]!
+7d74c039| gnu ldrsb w29, [x3,#29]
+7d1f8539| gnu ldrsb x29, [x27,#327]
+225bff38| gnu ldrsb w2, [x25,wzr,uxtw #0]
+6a7bed38| gnu ldrsb w10, [x27,x13,lsl #0]
+0f69b538| gnu ldrsb x15, [x8,x21]
+c796cc78| gnu ldrsh w7, [x22],#201
+50268e78| gnu ldrsh x16, [x18],#226
+229ddb78| gnu ldrsh w2, [x9,#-71]!
+0f4f9178| gnu ldrsh x15, [x24,#-236]!
+59ecc379| gnu ldrsh w25, [x2,#502]
+83d49679| gnu ldrsh x3, [x4,#2922]
+986be878| gnu ldrsh w24, [x28,x8]
+cad8bf78| gnu ldrsh x10, [x6,wzr,sxtw #1]
+6b4693b8| gnu ldrsw x11, [x19],#-204
+cb9e81b8| gnu ldrsw x11, [x22,#25]!
+280d9eb9| gnu ldrsw x8, [x9,#7692]
+93dec198| gnu ldrsw x19, .+0xfffffffffff83bd0
+1a68b8b8| gnu ldrsw x26, [x0,x24]
+35b955b8| gnu ldtr w21, [x9,#-165]
+658b57f8| gnu ldtr x5, [x27,#-136]
+b3594038| gnu ldtrb w19, [x13,#5]
+5ac95d78| gnu ldtrh w26, [x10,#-36]
+2c3ade38| gnu ldtrsb w12, [x17,#-29]
+4de99038| gnu ldtrsb x13, [x10,#-242]
+e178c378| gnu ldtrsh w1, [x7,#55]
+a77a8778| gnu ldtrsh x7, [x21,#119]
+cde982b8| gnu ldtrsw x13, [x14,#46]
+04d15bb8| gnu ldur w4, [x8,#-67]
+02a256f8| gnu ldur x2, [x16,#-150]
+97405438| gnu ldurb w23, [x4,#-188]
+99b14b78| gnu ldurh w25, [x12,#187]
+f9a1cf38| gnu ldursb w25, [x15,#250]
+c0218c38| gnu ldursb x0, [x14,#194]
+5790d278| gnu ldursh w23, [x2,#-215]
+a3808278| gnu ldursh x3, [x5,#40]
+a9b08fb8| gnu ldursw x9, [x5,#251]
+98217f88| gnu ldxp w24, w8, [x12]
+4d6a7fc8| gnu ldxp x13, x26, [x18]
+9c7e5f88| gnu ldxr w28, [x20]
+0e7c5fc8| gnu ldxr x14, [x0]
+507c5f08| gnu ldxrb w16, [x2]
+ea7f5f48| gnu ldxrh w10, [sp]
+5523dd1a| gnu lsl w21, w26, w29
+9721ca9a| gnu lsl x23, x12, x10
+75665bd3| gnu ubfiz x21, x19, #37, #26
+0a20df1a| gnu lsl w10, w0, wzr
+5222c99a| gnu lsl x18, x18, x9
+5124df1a| gnu lsr w17, w2, wzr
+6b26d69a| gnu lsr x11, x19, x22
+9a7c0753| gnu lsr w26, w4, #7
+7bfd53d3| gnu lsr x27, x11, #19
+5f26d91a| gnu lsr wzr, w18, w25
+3625d89a| gnu lsr x22, x9, x24
+9d76001b| gnu madd w29, w20, w0, w29
+822f0e9b| gnu madd x2, x28, x14, x11
+e8fe101b| gnu mneg w8, w23, w16
+88fc099b| gnu mneg x8, x4, x9
+dd030011| gnu add w29, w30, #0x0
+db010091| gnu add x27, x14, #0x0
+0c6db012| gnu mov w12, #0x7c97ffff
+3ff5aa92| gnu mov xzr, #0xffffffffa856ffff
+87f0f6d2| gnu mov x7, #0xb784000000000000
+f3571132| gnu orr w19, wzr, #0xffff801f
+f3bb0bb2| gnu mov x19, #0xffefffefffefffef
+f103082a| gnu mov w17, w8
+ef031faa| gnu mov x15, xzr
+4a6bf5f2| gnu movk x10, #0xab5a, lsl #48
+383b9312| gnu mov w24, #0xffff6626
+f5fb9092| gnu mov x21, #0xffffffffffff7820
+d5b4b052| gnu mov w21, #0x85a60000
+fdc5eed2| gnu mov x29, #0x762f000000000000
+c58435d5| gnu mrs x5, s2_5_c8_c4_6
+1a0f13d5| gnu msr s2_3_c0_c15_0, x26
+52d5181b| gnu msub w18, w10, w24, w21
+c4f81d9b| gnu msub x4, x6, x29, x30
+a57c1b1b| gnu mul w5, w5, w27
+8f7f0a9b| gnu mul x15, x28, x10
+e75361aa| gnu mvn x7, x1, lsr #20
+e0cb15cb| gnu neg x0, x21, lsl #50
+ffdb49eb| gnu cmp xzr, x9, lsr #54
+f5031c5a| gnu ngc w21, w28
+e6031eda| gnu ngc x6, x30
+e103077a| gnu ngcs w1, w7
+f20301fa| gnu ngcs x18, x1
+1f2003d5| gnu nop
+9347722a| gnu orn w19, w28, w18, lsr #17
+0591e1aa| gnu orn x5, x8, x1, ror #36
+7ba82a32| gnu orr w27, w3, #0xffc1ffc1
+ae087db2| gnu orr x14, x5, #0x38
+9608472a| gnu orr w22, w4, w7, lsr #2
+c40dc5aa| gnu orr x4, x14, x5, ror #3
+9d83bcf9| gnu prfm #0x1d, [x28,#30976]
+78ab03d8| gnu prfm #0x18, .+0x756c
+6e9186f8| gnu prfum #0x0e, [x11,#105]
+c001c05a| gnu rbit w0, w14
+4203c0da| gnu rbit x2, x26
+c0035fd6| gnu ret
+9b08c05a| gnu rev w27, w4
+740cc0da| gnu rev x20, x3
+0205c05a| gnu rev16 w2, w8
+dd07c0da| gnu rev16 x29, x30
+020bc0da| gnu rev32 x2, x24
+780cc0da| gnu rev x24, x3
+9b7f9513| gnu extr w27, w28, w21, #31
+5243dd93| gnu extr x18, x26, x29, #16
+822eca1a| gnu ror w2, w20, w10
+f02ddb9a| gnu ror x16, x15, x27
+082ed81a| gnu ror w8, w16, w24
+7b2cc39a| gnu ror x27, x3, x3
+3b030b5a| gnu sbc w27, w25, w11
+f2021dda| gnu sbc x18, x23, x29
+e600127a| gnu sbcs w6, w7, w18
+cf030ffa| gnu sbcs x15, x30, x15
+3a797793| gnu sbfiz x26, x9, #9, #31
+4a305193| gnu sbfiz x10, x2, #47, #13
+a1c74493| gnu sbfx x1, x29, #4, #46
+a00fc01a| gnu sdiv w0, w29, w0
+f10edd9a| gnu sdiv x17, x23, x29
+9f2003d5| gnu sev
+bf2003d5| gnu sevl
+a52d319b| gnu smaddl x5, w13, w17, x11
+b4fc399b| gnu smnegl x20, w5, w25
+579e369b| gnu smsubl x23, w18, w22, x7
+ea7e429b| gnu smulh x10, x23, x2
+eb7f219b| gnu smull x11, wzr, w1
+f1fe9f88| gnu stlr w17, [x23]
+edff9fc8| gnu stlr x13, [sp]
+bffe9f08| gnu stlrb wzr, [x21]
+9cfd9f48| gnu stlrh w28, [x12]
+41bf2688| gnu stlxp w6, w1, w15, [x26]
+01e93cc8| gnu stlxp w28, x1, x26, [x8]
+e0fd1f88| gnu stlxr wzr, w0, [x15]
+12fe17c8| gnu stlxr w23, x18, [x16]
+d4fc1008| gnu stlxrb w16, w20, [x6]
+befc0048| gnu stlxrh w0, w30, [x5]
+76613728| gnu stnp w22, w24, [x11,#-72]
+c7523ba8| gnu stnp x7, x20, [x22,#-80]
+8e3a9f28| gnu stp w14, w14, [x20],#248
+aa1fa6a8| gnu stp x10, x7, [x29],#-416
+fbae8d29| gnu stp w27, w11, [x23,#108]!
+f63c80a9| gnu stp x22, x15, [x7,#0]!
+43d73629| gnu stp w3, w21, [x26,#-76]
+1ae01ba9| gnu stp x26, x24, [x0,#440]
+8f650cb8| gnu str w15, [x12],#198
+aad503f8| gnu str x10, [x13],#61
+ec4d00b8| gnu str w12, [x15,#4]!
+7dbc1df8| gnu str x29, [x3,#-37]!
+9b0226b9| gnu str w27, [x20,#9728]
+91691af9| gnu str x17, [x12,#13520]
+20840838| gnu strb w0, [x1],#136
+060c1f38| gnu strb w6, [x0,#-16]!
+2b213a39| gnu strb w11, [x9,#3720]
+ab6b3438| gnu strb w11, [x29,x20]
+50e51e78| gnu strh w16, [x10],#-18
+5d5d1878| gnu strh w29, [x10,#-123]!
+ea862379| gnu strh w10, [x23,#4546]
+d65a2778| gnu strh w22, [x22,w7,uxtw #1]
+d5ca12b8| gnu sttr w21, [x22,#-212]
+001b18f8| gnu sttr x0, [x24,#-127]
+290a1e38| gnu sttrb w9, [x17,#-32]
+0b381078| gnu sttrh w11, [x0,#-253]
+c78101b8| gnu stur w7, [x14,#24]
+c0b217f8| gnu stur x0, [x22,#-133]
+f8401e38| gnu sturb w24, [x7,#-28]
+5e911a78| gnu sturh w30, [x10,#-87]
+b7622d88| gnu stxp w13, w23, w24, [x21]
+233d37c8| gnu stxp w23, x3, x15, [x9]
+847d0088| gnu stxr w0, w4, [x12]
+a27d0bc8| gnu stxr w11, x2, [x13]
+f27f1e08| gnu stxrb w30, w18, [sp]
+3a7d1848| gnu stxrh w24, w26, [x9]
+d4dc204b| gnu sub w20, w6, w0, sxtw #7
+874023cb| gnu sub x7, x4, w3, uxtw
+44eb4f51| gnu sub w4, w26, #0x3fa, lsl #12
+17b012cb| gnu sub x23, x0, x18, lsl #44
+ac1e376b| gnu subs w12, w21, w23, uxtb #7
+b0483beb| gnu subs x16, x5, w27, uxtw #2
+d1f994eb| gnu subs x17, x14, x20, asr #62
+61d513d4| gnu svc #0x9eab
+591d0013| gnu sxtb w25, w10
+9f1f4093| gnu sxtb xzr, w28
+773f0013| gnu sxth w23, w27
+453c4093| gnu sxth x5, w2
+b77c4093| gnu sxtw x23, w5
+743628d5| gnu sysl x20, #0, C3, C6, #3
+6fd248b7| gnu tbnz x15, #41, .+0x1a4c
+5afe3036| gnu tbz w26, #6, .+0x1fc8
+9f613672| gnu tst w12, #0xfffffc07
+1f8d22f2| gnu tst x8, #0xc003c003c003c003
+ff6e93ea| gnu tst x23, x19, asr #27
+06997ed3| gnu ubfiz x6, x8, #2, #39
+5dd054d3| gnu ubfx x29, x2, #20, #33
+a54273d3| gnu ubfiz x5, x21, #13, #17
+7d08d11a| gnu udiv w29, w3, w17
+120acf9a| gnu udiv x18, x16, x15
+1401a89b| gnu umaddl x20, w8, w8, x0
+08feb29b| gnu umnegl x8, w16, w18
+eeb0b99b| gnu umsubl x14, w7, w25, x12
+967fdd9b| gnu umulh x22, x28, x29
+947eb59b| gnu umull x20, w20, w21
+7e1f0053| gnu uxtb w30, w27
+983c0053| gnu uxth w24, w4
+5f2003d5| gnu wfe
+7f2003d5| gnu wfi
+3f2003d5| gnu yield
+02bb200e| gnu abs v2.8b, v24.8b
+0686ec4e| gnu add v6.2d, v16.2d, v12.2d
+ea42ac0e| gnu addhn v10.2s, v23.2d, v12.2d
+7d43624e| gnu addhn2 v29.8h, v27.4s, v2.4s
+2cbd710e| gnu addp v12.4h, v9.4h, v17.4h
+f5bab14e| gnu addv s21, v23.4s
+8158284e| gnu aesd v1.16b, v4.16b
+ba48284e| gnu aese v26.16b, v5.16b
+0c7a284e| gnu aesimc v12.16b, v16.16b
+3e6a284e| gnu aesmc v30.16b, v17.16b
+091f384e| gnu and v9.16b, v24.16b, v24.16b
+07b6046f| gnu bic v7.8h, #0x90, lsl #8
+00c5006f| gnu mvni v0.4s, #0x8, msl #8
+f81e6c0e| gnu bic v24.8b, v23.8b, v12.8b
+6f1ced2e| gnu bif v15.8b, v3.8b, v13.8b
+e31da16e| gnu bit v3.16b, v15.16b, v1.16b
+6a1d7c6e| gnu bsl v10.16b, v11.16b, v28.16b
+284a600e| gnu cls v8.4h, v17.4h
+9a49202e| gnu clz v26.8b, v12.8b
+d78f706e| gnu cmeq v23.8h, v30.8h, v16.8h
+7798e05e| gnu cmeq d23, d3, #0
+739a200e| gnu cmeq v19.8b, v19.8b, #0
+ff3f2b4e| gnu cmge v31.16b, v31.16b, v11.16b
+5337370e| gnu cmgt v19.8b, v26.8b, v23.8b
+3489604e| gnu cmgt v20.8h, v9.8h, #0
+083d782e| gnu cmhs v8.4h, v8.4h, v24.4h
+c899e07e| gnu cmle d8, d14, #0
+3498a06e| gnu cmle v20.4s, v1.4s, #0
+ebaa200e| gnu cmlt v11.8b, v23.8b, #0
+408dfe4e| gnu cmtst v0.2d, v10.2d, v30.2d
+0e06085e| gnu mov d14, v16.d[0]
+1e0d0d0e| gnu dup v30.8b, w8
+8e1d3a6e| gnu eor v14.16b, v12.16b, v26.16b
+632a086e| gnu ext v3.16b, v19.16b, v8.16b, #5
+97d7e57e| gnu fabd d23, d28, d5
+6bd4a82e| gnu fabd v11.2s, v3.2s, v8.2s
+f7faa00e| gnu fabs v23.2s, v23.2s
+54c2201e| gnu fabs s20, s18
+3ec3601e| gnu fabs d30, d25
+2aee317e| gnu facge s10, s17, s17
+2fed392e| gnu facge v15.2s, v9.2s, v25.2s
+2befe97e| gnu facgt d11, d25, d9
+65eced6e| gnu facgt v5.2d, v3.2d, v13.2d
+55d53c4e| gnu fadd v21.4s, v10.4s, v28.4s
+8b283f1e| gnu fadd s11, s4, s31
+d828601e| gnu fadd d24, d6, d0
+e9d8307e| gnu faddp s9, v7.2s
+4084391e| gnu fccmp s2, s25, #0x0, hi
+ef046d1e| gnu fccmp d7, d13, #0xf, eq
+d7a4241e| gnu fccmpe s6, s4, #0x7, ge
+dbf5601e| gnu fccmpe d14, d0, #0xb, al
+77e7625e| gnu fcmeq d23, d27, d2
+2de67f4e| gnu fcmeq v13.2d, v17.2d, v31.2d
+59daa05e| gnu fcmeq s25, s18, #0
+add9a00e| gnu fcmeq v13.2s, v13.2s, #0
+dce42d7e| gnu fcmge s28, s6, s13
+62e6776e| gnu fcmge v2.2d, v19.2d, v23.2d
+f9cae07e| gnu fcmge d25, d23, #0
+18e5ab7e| gnu fcmgt s24, s8, s11
+84e7ae6e| gnu fcmgt v4.4s, v28.4s, v14.4s
+a0c8e05e| gnu fcmgt d0, d5, #0
+c6cae04e| gnu fcmgt v6.2d, v22.2d, #0
+4fdaa07e| gnu fcmle s15, s18, #0
+e1d9a02e| gnu fcmle v1.2s, v15.2s, #0
+1ee9a05e| gnu fcmlt s30, s8, #0
+23eaa04e| gnu fcmlt v3.4s, v17.4s, #0
+6023321e| gnu fcmp s27, s18
+2823391e| gnu fcmp s25, #0
+00236d1e| gnu fcmp d24, d13
+e820601e| gnu fcmp d7, #0
+3022381e| gnu fcmpe s17, s24
+f8233e1e| gnu fcmpe s31, #0
+b0206a1e| gnu fcmpe d5, d10
+3820691e| gnu fcmpe d1, #0
+d85f271e| gnu fcsel s24, s30, s7, pl
+ed8f7a1e| gnu fcsel d13, d31, d26, hi
+0042e21e| gnu fcvt s0, h16
+efc1e21e| gnu fcvt d15, h15
+edc1231e| gnu fcvt h13, s15
+0ac0221e| gnu fcvt d10, s0
+39c3631e| gnu fcvt h25, d25
+da43621e| gnu fcvt s26, d30
+10cb615e| gnu fcvtas d16, d24
+f400241e| gnu fcvtas w20, s7
+2f00249e| gnu fcvtas x15, s1
+1d02641e| gnu fcvtas w29, d16
+9303649e| gnu fcvtas x19, d28
+02ca217e| gnu fcvtau s2, s16
+afc8212e| gnu fcvtau v15.2s, v5.2s
+6e02251e| gnu fcvtau w14, s19
+fd02259e| gnu fcvtau x29, s23
+8603651e| gnu fcvtau w6, d28
+4001659e| gnu fcvtau x0, d10
+1f78210e| gnu fcvtl v31.4s, v0.4h
+d179214e| gnu fcvtl2 v17.4s, v14.8h
+fdbb615e| gnu fcvtms d29, d31
+9601301e| gnu fcvtms w22, s12
+f403309e| gnu fcvtms x20, s31
+6b02701e| gnu fcvtms w11, d19
+4802709e| gnu fcvtms x8, d18
+84ba217e| gnu fcvtmu s4, s20
+ae01311e| gnu fcvtmu w14, s13
+8402319e| gnu fcvtmu x4, s20
+7403711e| gnu fcvtmu w20, d27
+2a03719e| gnu fcvtmu x10, d25
+a36b210e| gnu fcvtn v3.4h, v29.4s
+5c6a214e| gnu fcvtn2 v28.8h, v18.4s
+78a9215e| gnu fcvtns s24, s11
+b1ab614e| gnu fcvtns v17.2d, v29.2d
+0c01201e| gnu fcvtns w12, s8
+b303209e| gnu fcvtns x19, s29
+c401601e| gnu fcvtns w4, d14
+5200609e| gnu fcvtns x18, d2
+c2a8617e| gnu fcvtnu d2, d6
+daab616e| gnu fcvtnu v26.2d, v30.2d
+d001211e| gnu fcvtnu w16, s14
+0402219e| gnu fcvtnu x4, s16
+7800611e| gnu fcvtnu w24, d3
+e602619e| gnu fcvtnu x6, d23
+74aaa15e| gnu fcvtps s20, s19
+c801281e| gnu fcvtps w8, s14
+8f02289e| gnu fcvtps x15, s20
+6d02681e| gnu fcvtps w13, d19
+bc00689e| gnu fcvtps x28, d5
+43aba17e| gnu fcvtpu s3, s26
+cda9a12e| gnu fcvtpu v13.2s, v14.2s
+c102291e| gnu fcvtpu w1, s22
+9103299e| gnu fcvtpu x17, s28
+7602691e| gnu fcvtpu w22, d19
+4501699e| gnu fcvtpu x5, d10
+976a616e| gnu fcvtxn2 v23.4s, v20.2d
+d5fc575f| gnu fcvtzs d21, d6, #41
+babaa15e| gnu fcvtzs s26, s21
+7aa6181e| gnu fcvtzs w26, s19, #23
+c410189e| gnu fcvtzs x4, s6, #60
+4db5589e| gnu fcvtzs x13, d10, #19
+9000381e| gnu fcvtzs w16, s4
+1702389e| gnu fcvtzs x23, s16
+8a03781e| gnu fcvtzs w10, d28
+d501789e| gnu fcvtzs x21, d14
+eefd2d7f| gnu fcvtzu s14, s15, #19
+4dfc3c6f| gnu fcvtzu v13.4s, v2.4s, #4
+96bbe17e| gnu fcvtzu d22, d28
+30b8e16e| gnu fcvtzu v16.2d, v1.2d
+fdef191e| gnu fcvtzu w29, s31, #5
+1d7b199e| gnu fcvtzu x29, s24, #34
+b8f5591e| gnu fcvtzu w24, d13, #3
+5080599e| gnu fcvtzu x16, d2, #32
+d002391e| gnu fcvtzu w16, s22
+9b03399e| gnu fcvtzu x27, s28
+7501791e| gnu fcvtzu w21, d11
+7603799e| gnu fcvtzu x22, d27
+06fe3c6e| gnu fdiv v6.4s, v16.4s, v28.4s
+c41b201e| gnu fdiv s4, s30, s0
+1618781e| gnu fdiv d22, d0, d24
+507b0d1f| gnu fmadd s16, s26, s13, s30
+8803491f| gnu fmadd d8, d28, d9, d0
+75f7394e| gnu fmax v21.4s, v27.4s, v25.4s
+804b3c1e| gnu fmax s0, s28, s28
+c1496c1e| gnu fmax d1, d14, d12
+5b69371e| gnu fmaxnm s27, s10, s23
+1468711e| gnu fmaxnm d20, d0, d17
+a4c8707e| gnu fmaxnmp d4, v5.2d
+89f9707e| gnu fmaxp d9, v12.2d
+4af63e2e| gnu fmaxp v10.2s, v18.2s, v30.2s
+25fa306e| gnu fmaxv s5, v17.4s
+01f4e04e| gnu fmin v1.2d, v0.2d, v0.2d
+59592a1e| gnu fmin s25, s10, s10
+3959611e| gnu fmin d25, d9, d1
+73c7ba4e| gnu fminnm v19.4s, v27.4s, v26.4s
+1279391e| gnu fminnm s18, s8, s25
+75796c1e| gnu fminnm d21, d11, d12
+90cbb07e| gnu fminnmp s16, v28.2s
+c5c8b06e| gnu fminnmv s5, v6.4s
+cdfbf07e| gnu fminp d13, v30.2d
+edf6f66e| gnu fminp v13.2d, v23.2d, v22.2d
+6513b85f| gnu fmla s5, s27, v24.s[1]
+ee18984f| gnu fmla v14.4s, v7.4s, v24.s[2]
+b85ab75f| gnu fmls s24, s21, v23.s[3]
+a3f5030f| gnu fmov v3.2s, #9.062500000000000000e-01
+eaf7056f| gnu fmov v10.2d, #-3.100000000000000000e+01
+3b41201e| gnu fmov s27, s9
+0d41601e| gnu fmov d13, d8
+9700271e| gnu fmov s23, w4
+ad03261e| gnu fmov w13, s29
+2302679e| gnu fmov d3, x17
+e101af9e| gnu fmov v1.d[1], x15
+f301669e| gnu fmov x19, d15
+1103ae9e| gnu fmov x17, v24.d[1]
+0230321e| gnu fmov s2, #-4.250000000000000000e+00
+18b0751e| gnu fmov d24, #-1.450000000000000000e+01
+92bc1b1f| gnu fmsub s18, s4, s27, s15
+f8e14a1f| gnu fmsub d24, d15, d10, d24
+ef91d35f| gnu fmul d15, d15, v19.d[0]
+d293c24f| gnu fmul v18.2d, v30.2d, v2.d[0]
+18dd2b2e| gnu fmul v24.2s, v8.2s, v11.2s
+a4093d1e| gnu fmul s4, s13, s29
+94096f1e| gnu fmul d20, d12, d15
+fe918e7f| gnu fmulx s30, s15, v14.s[0]
+7199c56f| gnu fmulx v17.2d, v11.2d, v5.d[1]
+32dc695e| gnu fmulx d18, d1, d9
+c8f9e06e| gnu fneg v8.2d, v14.2d
+9c41211e| gnu fneg s28, s12
+c443611e| gnu fneg d4, d30
+e77f301f| gnu fnmadd s7, s31, s16, s31
+9f326c1f| gnu fnmadd d31, d20, d12, d12
+d9e92f1f| gnu fnmsub s25, s14, s15, s26
+00ad711f| gnu fnmsub d0, d8, d17, d11
+c889211e| gnu fnmul s8, s14, s1
+528b761e| gnu fnmul d18, d26, d22
+01d8e15e| gnu frecpe d1, d0
+9aff7e5e| gnu frecps d26, d28, d30
+78fe2a4e| gnu frecps v24.4s, v19.4s, v10.4s
+01f9e15e| gnu frecpx d1, d8
+128b216e| gnu frinta v18.4s, v24.4s
+b241261e| gnu frinta s18, s13
+a841661e| gnu frinta d8, d13
+799aa16e| gnu frinti v25.4s, v19.4s
+1cc2271e| gnu frinti s28, s16
+93c2671e| gnu frinti d19, d20
+1a40251e| gnu frintm s26, s0
+ac42651e| gnu frintm d12, d21
+5889214e| gnu frintn v24.4s, v10.4s
+5740241e| gnu frintn s23, s2
+9443641e| gnu frintn d20, d28
+4b89a10e| gnu frintp v11.2s, v10.2s
+a0c1241e| gnu frintp s0, s13
+93c2641e| gnu frintp d19, d20
+d49b216e| gnu frintx v20.4s, v30.4s
+df41271e| gnu frintx s31, s14
+8d41671e| gnu frintx d13, d12
+3998a10e| gnu frintz v25.2s, v1.2s
+fdc2251e| gnu frintz s29, s23
+abc2651e| gnu frintz d11, d21
+10dba17e| gnu frsqrte s16, s24
+edd9e16e| gnu frsqrte v13.2d, v15.2d
+75ffe35e| gnu frsqrts d21, d27, d3
+b4fdbe4e| gnu frsqrts v20.4s, v13.4s, v30.4s
+24f8a16e| gnu fsqrt v4.4s, v1.4s
+b6c1211e| gnu fsqrt s22, s13
+c1c3611e| gnu fsqrt d1, d30
+ffd5b44e| gnu fsub v31.4s, v15.4s, v20.4s
+d438331e| gnu fsub s20, s6, s19
+f038771e| gnu fsub d16, d7, d23
+675e1a6e| gnu mov v7.h[6], v19.h[5]
+2a1c0a4e| gnu mov v10.h[2], w1
+de7f400c| gnu ld1 {v30.1d}, [x30]
+4aa7404c| gnu ld1 {v10.8h, v11.8h}, [x26]
+5d61400c| gnu ld1 {v29.8b-v31.8b}, [x10]
+af21404c| gnu ld1 {v15.16b-v18.16b}, [x13]
+737edf0c| gnu ld1 {v19.1d}, [x19],#8
+757dd10c| gnu ld1 {v21.1d}, [x11], x17
+5ca3df4c| gnu ld1 {v28.16b, v29.16b}, [x26],#32
+93a1ce0c| gnu ld1 {v19.8b, v20.8b}, [x12], x14
+1c65df0c| gnu ld1 {v28.4h-v30.4h}, [x8],#24
+4461d34c| gnu ld1 {v4.16b-v6.16b}, [x10], x19
+b22edf4c| gnu ld1 {v18.2d-v21.2d}, [x21],#64
+c12fcc4c| gnu ld1 {v1.2d-v4.2d}, [x30], x12
+5a03400d| gnu ld1 {v26.b}[0], [x26]
+8d93404d| gnu ld1 {v13.s}[3], [x28]
+2186404d| gnu ld1 {v1.d}[1], [x17]
+9604df4d| gnu ld1 {v22.b}[9], [x4],#1
+4a1dc94d| gnu ld1 {v10.b}[15], [x10], x9
+4852df4d| gnu ld1 {v8.h}[6], [x18],#2
+2582df4d| gnu ld1 {v5.s}[2], [x17],#4
+2191c84d| gnu ld1 {v1.s}[3], [x9], x8
+c284df4d| gnu ld1 {v2.d}[1], [x6],#8
+8f85ce0d| gnu ld1 {v15.d}[0], [x12], x14
+87cd400d| gnu ld1r {v7.1d}, [x12]
+3bc8df4d| gnu ld1r {v27.4s}, [x1],#4
+77c4dd4d| gnu ld1r {v23.8h}, [x3], x29
+5384404c| gnu ld2 {v19.8h, v20.8h}, [x2]
+ca87df0c| gnu ld2 {v10.4h, v11.4h}, [x30],#16
+1280d70c| gnu ld2 {v18.8b, v19.8b}, [x0], x23
+4c0a604d| gnu ld2 {v12.b, v13.b}[10], [x18]
+3080600d| gnu ld2 {v16.s, v17.s}[0], [x1]
+6686600d| gnu ld2 {v6.d, v7.d}[0], [x19]
+061eff0d| gnu ld2 {v6.b, v7.b}[7], [x16],#2
+db05fa0d| gnu ld2 {v27.b, v28.b}[1], [x14], x26
+8a49ff4d| gnu ld2 {v10.h, v11.h}[5], [x12],#4
+bb59ec4d| gnu ld2 {v27.h, v28.h}[7], [x13], x12
+5a82ff0d| gnu ld2 {v26.s, v27.s}[0], [x18],#8
+6180e30d| gnu ld2 {v1.s, v2.s}[0], [x3], x3
+6485ff0d| gnu ld2 {v4.d, v5.d}[0], [x11],#16
+7c86ed4d| gnu ld2 {v28.d, v29.d}[1], [x19], x13
+54c0604d| gnu ld2r {v20.16b, v21.16b}, [x2]
+fdcaff0d| gnu ld2r {v29.2s, v30.2s}, [x23],#8
+7bc5e40d| gnu ld2r {v27.4h, v28.4h}, [x11], x4
+b349404c| gnu ld3 {v19.4s-v21.4s}, [x13]
+cf46df4c| gnu ld3 {v15.8h-v17.8h}, [x22],#48
+934acc4c| gnu ld3 {v19.4s-v21.4s}, [x20], x12
+2c33404d| gnu ld3 {v12.b-v14.b}[12], [x25]
+897a400d| gnu ld3 {v9.h-v11.h}[3], [x20]
+f9b2400d| gnu ld3 {v25.s-v27.s}[1], [x23]
+4aa7404d| gnu ld3 {v10.d-v12.d}[1], [x26]
+4e25df4d| gnu ld3 {v14.b-v16.b}[9], [x10],#3
+7827c40d| gnu ld3 {v24.b-v26.b}[1], [x27], x4
+c4a3df4d| gnu ld3 {v4.s-v6.s}[2], [x30],#12
+f0a1cf0d| gnu ld3 {v16.s-v18.s}[0], [x15], x15
+1ba7df0d| gnu ld3 {v27.d-v29.d}[0], [x24],#24
+f7a7d50d| gnu ld3 {v23.d-v25.d}[0], [sp], x21
+a9ed404d| gnu ld3r {v9.2d-v11.2d}, [x13]
+5aecdf4d| gnu ld3r {v26.2d-v28.2d}, [x2],#24
+bae9c74d| gnu ld3r {v26.4s-v28.4s}, [x13], x7
+5904404c| gnu ld4 {v25.8h-v28.8h}, [x2]
+743b604d| gnu ld4 {v20.b-v23.b}[14], [x27]
+bda1600d| gnu ld4 {v29.s, v30.s, v31.s, v0.s}[0], [x13]
+a3a4600d| gnu ld4 {v3.d-v6.d}[0], [x5]
+2f3aff4d| gnu ld4 {v15.b-v18.b}[14], [x17],#4
+e73bef4d| gnu ld4 {v7.b-v10.b}[14], [sp], x15
+5d78ef0d| gnu ld4 {v29.h, v30.h, v31.h, v0.h}[3], [x2], x15
+acb3ff0d| gnu ld4 {v12.s-v15.s}[1], [x29],#16
+a8b2f04d| gnu ld4 {v8.s-v11.s}[3], [x21], x16
+75a7ff4d| gnu ld4 {v21.d-v24.d}[1], [x27],#32
+75a6ee4d| gnu ld4 {v21.d-v24.d}[1], [x19], x14
+d8e3604d| gnu ld4r {v24.16b-v27.16b}, [x30]
+49e9ff0d| gnu ld4r {v9.2s-v12.2s}, [x10],#16
+81effc0d| gnu ld4r {v1.1d-v4.1d}, [x28], x28
+893e622c| gnu ldnp s9, s15, [x20,#-240]
+f90e626c| gnu ldnp d25, d3, [x23,#-480]
+b0224fac| gnu ldnp q16, q8, [x21,#480]
+9186de2c| gnu ldp s17, s1, [x20],#244
+e820d06c| gnu ldp d8, d8, [x7],#256
+417de8ac| gnu ldp q1, q31, [x10],#-768
+7969ed2d| gnu ldp s25, s26, [x11,#-152]!
+70c8c36d| gnu ldp d16, d18, [x3,#56]!
+30b4c4ad| gnu ldp q16, q13, [x1,#144]!
+a1857f2d| gnu ldp s1, s1, [x13,#-4]
+f4ae786d| gnu ldp d20, d11, [x23,#-120]
+998366ad| gnu ldp q25, q0, [x28,#-816]
+7535453c| gnu ldr b21, [x11],#83
+5465477c| gnu ldr h20, [x10],#118
+a2b44bbc| gnu ldr s2, [x5],#187
+ab045bfc| gnu ldr d11, [x5],#-80
+0515d43c| gnu ldr q5, [x8],#-191
+43ad413c| gnu ldr b3, [x10,#26]!
+22cd4f7c| gnu ldr h2, [x9,#252]!
+5fad44bc| gnu ldr s31, [x10,#74]!
+db7d5afc| gnu ldr d27, [x14,#-89]!
+15ccd63c| gnu ldr q21, [x0,#-148]!
+95c34b3d| gnu ldr b21, [x28,#752]
+f5885e7d| gnu ldr h21, [x7,#3908]
+54db66bd| gnu ldr s20, [x26,#9944]
+46ee78fd| gnu ldr d6, [x18,#29144]
+0cc4e93d| gnu ldr q12, [x0,#42768]
+e1c4211c| gnu ldr s1, .+0x4389c
+2071c35c| gnu ldr d0, .+0xfffffffffff86e24
+4765789c| gnu ldr q7, .+0xf0ca8
+ae79703c| gnu ldr b14, [x13,x16,lsl #0]
+38fb67bc| gnu ldr s24, [x25,x7,sxtx #2]
+3e6b6dfc| gnu ldr d30, [x25,x13]
+a278ff3c| gnu ldr q2, [x5,xzr,lsl #4]
+ed02563c| gnu ldur b13, [x23,#-160]
+01c0507c| gnu ldur h1, [x0,#-244]
+7fd24ebc| gnu ldur s31, [x19,#237]
+7a734ffc| gnu ldur d26, [x27,#247]
+d4a3dd3c| gnu ldur q20, [x30,#-38]
+1c97250e| gnu mla v28.8b, v24.8b, v5.8b
+af97a12e| gnu mls v15.2s, v29.2s, v1.2s
+2b061f5e| gnu mov b11, v17.b[15]
+805e086e| gnu mov v0.d[0], v20.d[1]
+d91fbc4e| gnu orr v25.16b, v30.16b, v28.16b
+a43f040e| gnu mov w4, v29.s[0]
+fbe6054f| gnu movi v27.16b, #0xb7
+9b75024f| gnu orr v27.4s, #0x4c, lsl #24
+8436020f| gnu orr v4.2s, #0x54, lsl #8
+19f5010f| gnu fmov v25.2s, #1.200000000000000000e+01
+02e5062f| gnu movi d2, #0xffff0000ff000000
+d6e5066f| gnu movi v22.2d, #0xffff0000ffffff00
+be9c240e| gnu mul v30.8b, v5.8b, v4.8b
+2659202e| gnu mvn v6.8b, v9.8b
+f394046f| gnu bic v19.8h, #0x87
+d856056f| gnu bic v24.4s, #0xb6, lsl #16
+2f85022f| gnu mvni v15.4h, #0x49
+24baa02e| gnu neg v4.2s, v17.2s
+145b206e| gnu mvn v20.16b, v24.16b
+191fff4e| gnu orn v25.16b, v24.16b, v31.16b
+6f96004f| gnu orr v15.8h, #0x13
+a564020f| gnu movi v5.2s, #0x45, lsl #24
+ae1ead0e| gnu orr v14.8b, v21.8b, v13.8b
+f2e1e00e| gnu pmull v18.1q, v15.1d, v0.1d
+0d426e2e| gnu raddhn v13.4h, v16.4s, v14.4s
+4443246e| gnu raddhn2 v4.16b, v26.8h, v4.8h
+015b602e| gnu rbit v1.8b, v24.8b
+4209202e| gnu rev32 v2.8b, v10.8b
+d109a04e| gnu rev64 v17.4s, v14.4s
+5a8e380f| gnu rshrn v26.2s, v18.2d, #8
+438d234f| gnu rshrn2 v3.4s, v10.2d, #29
+a861716e| gnu rsubhn2 v8.8h, v13.4s, v17.4s
+017c2f0e| gnu saba v1.8b, v0.8b, v15.8b
+5d51a90e| gnu sabal v29.2d, v10.2s, v9.2s
+c076a04e| gnu sabd v0.4s, v22.4s, v0.4s
+2d722e0e| gnu sabdl v13.8h, v17.8b, v14.8b
+1f732e4e| gnu sabdl2 v31.8h, v24.16b, v14.16b
+c628604e| gnu saddlp v6.4s, v6.8h
+103b704e| gnu saddlv s16, v24.8h
+8f122f0e| gnu saddw v15.8h, v20.8h, v15.8b
+30e6755f| gnu scvtf d16, d17, #11
+73e7544f| gnu scvtf v19.2d, v27.2d, #44
+51d9615e| gnu scvtf d17, d10
+fad9210e| gnu scvtf v26.2s, v15.2s
+96c0421e| gnu scvtf d22, w4, #16
+76e1029e| gnu scvtf s22, x11, #8
+a791429e| gnu scvtf d7, x13, #28
+f100221e| gnu scvtf s17, w7
+e101621e| gnu scvtf d1, w15
+6e03229e| gnu scvtf s14, x27
+0b01629e| gnu scvtf d11, x8
+2401025e| gnu sha1c q4, s9, v2.4s
+5d08285e| gnu sha1h s29, s2
+65210d5e| gnu sha1m q5, s11, v13.4s
+29131a5e| gnu sha1p q9, s25, v26.4s
+2b311a5e| gnu sha1su0 v11.4s, v9.4s, v26.4s
+0919285e| gnu sha1su1 v9.4s, v8.4s
+f052035e| gnu sha256h2 q16, q23, v3.4s
+fe401e5e| gnu sha256h q30, q7, v30.4s
+7529285e| gnu sha256su0 v21.4s, v11.4s
+cc60195e| gnu sha256su1 v12.4s, v6.4s, v25.4s
+8b56060f| gnu orr v11.2s, #0xd4, lsl #16
+3f3aa16e| gnu shll2 v31.2d, v17.4s, #32
+0986394f| gnu shrn2 v9.4s, v16.2d, #7
+35276e4e| gnu shsub v21.8h, v25.8h, v14.8h
+e2556d7f| gnu sli d2, d15, #45
+f7541e6f| gnu sli v23.8h, v7.8h, #14
+3167630e| gnu smax v17.4h, v25.4h, v3.4h
+68a6230e| gnu smaxp v8.8b, v19.8b, v3.8b
+a4aa304e| gnu smaxv b4, v21.16b
+2520440f| gnu smlal v5.4s, v1.4h, v4.h[0]
+8c286f4f| gnu smlal2 v12.4s, v4.8h, v15.h[6]
+3a82660e| gnu smlal v26.4s, v17.4h, v6.4h
+d92f1f0e| gnu smov w25, v30.b[15]
+912d114e| gnu smov x17, v12.b[8]
+b87ae05e| gnu sqabs d24, d21
+2d7b200e| gnu sqabs v13.8b, v25.8b
+560f645e| gnu sqadd h22, h26, h4
+4f0da54e| gnu sqadd v15.4s, v10.4s, v5.4s
+5992ba5e| gnu sqdmlal d25, s18, s26
+b892684e| gnu sqdmlal2 v24.4s, v21.8h, v8.8h
+63786e5f| gnu sqdmlsl s3, h3, v14.h[6]
+0c79a10f| gnu sqdmlsl v12.2d, v8.2s, v1.s[3]
+1d73504f| gnu sqdmlsl2 v29.4s, v24.8h, v0.h[1]
+6cb36c5e| gnu sqdmlsl s12, h27, h12
+82b36e4e| gnu sqdmlsl2 v2.4s, v28.8h, v14.8h
+8dca5d4f| gnu sqdmulh v13.8h, v20.8h, v13.h[5]
+fcb6b64e| gnu sqdmulh v28.4s, v23.4s, v22.4s
+d6b0974f| gnu sqdmull2 v22.2d, v6.4s, v23.s[0]
+afd0b84e| gnu sqdmull2 v15.2d, v5.4s, v24.4s
+067b207e| gnu sqneg b6, b24
+9979606e| gnu sqneg v25.8h, v12.8h
+bfdbae0f| gnu sqrdmulh v31.2s, v29.2s, v14.s[3]
+c3b7a07e| gnu sqrdmulh s3, s30, s0
+845d3d5e| gnu sqrshl b4, b12, b29
+495dba0e| gnu sqrshl v9.2s, v10.2s, v26.2s
+fa8e0d7f| gnu sqrshrun b26, h23, #3
+cf75185f| gnu sqshl h15, h14, #8
+a975250f| gnu sqshl v9.2s, v13.2s, #5
+424da05e| gnu sqshl s2, s10, s0
+464db90e| gnu sqshl v6.2s, v10.2s, v25.2s
+af656d7f| gnu sqshlu d15, d13, #45
+e564436f| gnu sqshlu v5.2d, v7.2d, #3
+c1973b5f| gnu sqshrn s1, d30, #5
+d586036f| gnu mvni v21.8h, #0x76
+4c2ea95e| gnu sqsub s12, s18, s9
+df2efe4e| gnu sqsub v31.2d, v22.2d, v30.2d
+c149a10e| gnu sqxtn v1.2s, v14.2d
+712a217e| gnu sqxtun b17, h19
+9a29a12e| gnu sqxtun v26.2s, v12.2d
+6a166e0e| gnu srhadd v10.4h, v19.4h, v14.4h
+0445647f| gnu sri d4, d8, #28
+6f44172f| gnu sri v15.4h, v3.4h, #9
+cd56f94e| gnu srshl v13.2d, v22.2d, v25.2d
+12345b5f| gnu srsra d18, d0, #37
+f746fa5e| gnu sshl d23, d23, d26
+89476c4e| gnu sshl v9.8h, v28.8h, v12.8h
+0da60e0f| gnu sshll v13.8h, v16.8b, #6
+a504585f| gnu sshr d5, d5, #40
+3b07544f| gnu sshr v27.2d, v25.2d, #44
+3417350f| gnu ssra v20.2s, v25.2s, #11
+1a213f0e| gnu ssubl v26.8h, v8.8b, v31.8b
+1322a34e| gnu ssubl2 v19.2d, v16.4s, v3.4s
+e931b84e| gnu ssubw2 v9.2d, v15.2d, v24.4s
+dd7d004c| gnu st1 {v29.2d}, [x14]
+cea4000c| gnu st1 {v14.4h, v15.4h}, [x6]
+5a64000c| gnu st1 {v26.4h-v28.4h}, [x2]
+2b2c004c| gnu st1 {v11.2d-v14.2d}, [x1]
+39719f0c| gnu st1 {v25.8b}, [x9],#8
+b771874c| gnu st1 {v23.16b}, [x13], x7
+1da39f0c| gnu st1 {v29.8b, v30.8b}, [x24],#16
+20a0800c| gnu st1 {v0.8b, v1.8b}, [x1], x0
+5a6a9f4c| gnu st1 {v26.4s-v28.4s}, [x18],#48
+0d69994c| gnu st1 {v13.4s-v15.4s}, [x8], x25
+7e239f0c| gnu st1 {v30.8b, v31.8b, v0.8b, v1.8b}, [x27],#32
+9a2d8e0c| gnu st1 {v26.1d-v29.1d}, [x12], x14
+fd0b004d| gnu st1 {v29.b}[10], [sp]
+1058004d| gnu st1 {v16.h}[7], [x0]
+0593000d| gnu st1 {v5.s}[1], [x24]
+3d87000d| gnu st1 {v29.d}[0], [x25]
+1a079f0d| gnu st1 {v26.b}[1], [x24],#1
+421b8f4d| gnu st1 {v2.b}[14], [x26], x15
+54489f4d| gnu st1 {v20.h}[5], [x2],#2
+c4809f4d| gnu st1 {v4.s}[2], [x6],#4
+0481840d| gnu st1 {v4.s}[0], [x8], x4
+6b859f0d| gnu st1 {v11.d}[0], [x11],#8
+f7878e4d| gnu st1 {v23.d}[1], [sp], x14
+e788004c| gnu st2 {v7.4s, v8.4s}, [x7]
+79889f0c| gnu st2 {v25.2s, v26.2s}, [x3],#16
+a502204d| gnu st2 {v5.b, v6.b}[8], [x21]
+0e50204d| gnu st2 {v14.h, v15.h}[6], [x0]
+6b93204d| gnu st2 {v11.s, v12.s}[3], [x27]
+0987200d| gnu st2 {v9.d, v10.d}[0], [x24]
+7003bf0d| gnu st2 {v16.b, v17.b}[0], [x27],#2
+1a09a94d| gnu st2 {v26.b, v27.b}[10], [x8], x9
+1e43b00d| gnu st2 {v30.h, v31.h}[0], [x24], x16
+1a82bf0d| gnu st2 {v26.s, v27.s}[0], [x16],#8
+9892a50d| gnu st2 {v24.s, v25.s}[1], [x20], x5
+5884bf0d| gnu st2 {v24.d, v25.d}[0], [x2],#16
+9e87a34d| gnu st2 {v30.d, v31.d}[1], [x28], x3
+4e47004c| gnu st3 {v14.8h-v16.8h}, [x26]
+76489f4c| gnu st3 {v22.4s-v24.4s}, [x3],#48
+3b48860c| gnu st3 {v27.2s-v29.2s}, [x1], x6
+e52a000d| gnu st3 {v5.b-v7.b}[2], [x23]
+6f73004d| gnu st3 {v15.h-v17.h}[6], [x27]
+9bb1004d| gnu st3 {v27.s-v29.s}[3], [x12]
+0ca7000d| gnu st3 {v12.d-v14.d}[0], [x24]
+2a259f0d| gnu st3 {v10.b-v12.b}[1], [x9],#3
+0524860d| gnu st3 {v5.b-v7.b}[1], [x0], x6
+94689a4d| gnu st3 {v20.h-v22.h}[5], [x4], x26
+c2a19f4d| gnu st3 {v2.s-v4.s}[2], [x14],#12
+5fb38c0d| gnu st3 {v31.s, v0.s, v1.s}[1], [x26], x12
+6da59f4d| gnu st3 {v13.d-v15.d}[1], [x11],#24
+32a7924d| gnu st3 {v18.d-v20.d}[1], [x25], x18
+5b03000c| gnu st4 {v27.8b-v30.8b}, [x26]
+cd059f0c| gnu st4 {v13.4h-v16.4h}, [x14],#32
+8601820c| gnu st4 {v6.8b-v9.8b}, [x12], x2
+7925200d| gnu st4 {v25.b-v28.b}[1], [x11]
+cd7a204d| gnu st4 {v13.h-v16.h}[7], [x22]
+dfb2204d| gnu st4 {v31.s, v0.s, v1.s, v2.s}[3], [x22]
+daa4200d| gnu st4 {v26.d-v29.d}[0], [x6]
+2135bf0d| gnu st4 {v1.b-v4.b}[5], [x9],#4
+7727a90d| gnu st4 {v23.b-v26.b}[1], [x27], x9
+b4a3bf0d| gnu st4 {v20.s-v23.s}[0], [x29],#16
+1ba3ae0d| gnu st4 {v27.s-v30.s}[0], [x24], x14
+93a4bf0d| gnu st4 {v19.d-v22.d}[0], [x4],#32
+50a6b80d| gnu st4 {v16.d-v19.d}[0], [x18], x24
+79b53d2c| gnu stnp s25, s13, [x11,#-20]
+d895326c| gnu stnp d24, d5, [x14,#-216]
+d1810dac| gnu stnp q17, q0, [x14,#432]
+08728c2c| gnu stp s8, s28, [x16],#96
+ac1ba16c| gnu stp d12, d6, [x29],#-496
+f4fab1ac| gnu stp q20, q30, [x23],#-464
+c15bbe2d| gnu stp s1, s22, [x30,#-16]!
+2422856d| gnu stp d4, d8, [x17,#80]!
+3d5282ad| gnu stp q29, q20, [x17,#64]!
+5df5352d| gnu stp s29, s29, [x10,#-84]
+5c54286d| gnu stp d28, d21, [x2,#-384]
+753c11ad| gnu stp q21, q15, [x3,#544]
+54e4033c| gnu str b20, [x2],#62
+aa54137c| gnu str h10, [x5],#-203
+c9d615bc| gnu str s9, [x22],#-163
+fc471efc| gnu str d28, [sp],#-28
+20f78d3c| gnu str q0, [x25],#223
+028d1b3c| gnu str b2, [x8,#-72]!
+35be037c| gnu str h21, [x17,#59]!
+b98c15bc| gnu str s25, [x5,#-168]!
+fd1e11fc| gnu str d29, [x23,#-239]!
+13ec9a3c| gnu str q19, [x0,#-82]!
+b12d123d| gnu str b17, [x13,#1163]
+d6500b7d| gnu str h22, [x6,#1448]
+d46e39bd| gnu str s20, [x22,#14700]
+b84f30fd| gnu str d24, [x29,#24728]
+3cee993d| gnu str q28, [x17,#26544]
+4348293c| gnu str b3, [x2,w9,uxtw]
+ed7b253c| gnu str b13, [sp,x5,lsl #0]
+8fc9357c| gnu str h15, [x12,w21,sxtw]
+87f832bc| gnu str s7, [x4,x18,sxtx #2]
+f1ea38fc| gnu str d17, [x23,x24,sxtx]
+1c68a43c| gnu str q28, [x0,x4]
+dcb1023c| gnu stur b28, [x14,#43]
+6701117c| gnu stur h7, [x11,#-240]
+85b11bbc| gnu stur s5, [x12,#-69]
+8ea10efc| gnu stur d14, [x12,#234]
+eab08f3c| gnu stur q10, [x7,#251]
+ca876a2e| gnu sub v10.4h, v30.4h, v10.4h
+603be05e| gnu suqadd d0, d27
+513a600e| gnu suqadd v17.4h, v18.4h
+25231c4e| gnu tbl v5.16b, {v25.16b, v26.16b}, v28.16b
+8c40100e| gnu tbl v12.8b, {v4.16b-v6.16b}, v16.8b
+0462040e| gnu tbl v4.8b, {v16.16b-v19.16b}, v4.8b
+34000f0e| gnu tbl v20.8b, {v1.16b}, v15.8b
+eb301f4e| gnu tbx v11.16b, {v7.16b, v8.16b}, v31.16b
+bb51124e| gnu tbx v27.16b, {v13.16b-v15.16b}, v18.16b
+cf701d0e| gnu tbx v15.8b, {v6.16b-v9.16b}, v29.8b
+4213080e| gnu tbx v2.8b, {v26.16b}, v8.8b
+2b2b114e| gnu trn1 v11.16b, v25.16b, v17.16b
+766ada4e| gnu trn2 v22.2d, v19.2d, v26.2d
+4152672e| gnu uabal v1.4s, v18.4h, v7.4h
+0953296e| gnu uabal2 v9.8h, v24.16b, v9.16b
+41756c6e| gnu uabd v1.8h, v10.8h, v12.8h
+3670ae2e| gnu uabdl v22.2d, v1.2s, v14.2s
+5401312e| gnu uaddl v20.8h, v10.8b, v17.8b
+d103286e| gnu uaddl2 v17.8h, v30.16b, v8.16b
+a92a206e| gnu uaddlp v9.8h, v21.16b
+b839706e| gnu uaddlv s24, v13.8h
+ea106d2e| gnu uaddw v10.4s, v7.4s, v13.4h
+c010726e| gnu uaddw2 v0.4s, v6.4s, v18.8h
+e7e5517f| gnu ucvtf d7, d15, #47
+49e7376f| gnu ucvtf v9.4s, v26.4s, #9
+4ada617e| gnu ucvtf d10, d18
+6b82431e| gnu ucvtf d11, w19, #32
+db84039e| gnu ucvtf s27, x6, #31
+1c72439e| gnu ucvtf d28, x16, #36
+f301231e| gnu ucvtf s19, w15
+3503631e| gnu ucvtf d21, w25
+e602239e| gnu ucvtf s6, x23
+d503639e| gnu ucvtf d21, x30
+ec04606e| gnu uhadd v12.8h, v7.8h, v0.8h
+3f65782e| gnu umax v31.4h, v9.4h, v24.4h
+afa6232e| gnu umaxp v15.8b, v21.8b, v3.8b
+cdaa706e| gnu umaxv h13, v22.8h
+736c236e| gnu umin v19.16b, v3.16b, v3.16b
+a0afa62e| gnu uminp v0.2s, v29.2s, v6.2s
+3c229e2f| gnu umlal v28.2d, v17.2s, v30.s[0]
+9d29a56f| gnu umlal2 v29.2d, v12.4s, v5.s[3]
+6c80392e| gnu umlal v12.8h, v3.8b, v25.8b
+4f60692f| gnu umlsl v15.4s, v2.4h, v9.h[2]
+61a1606e| gnu umlsl2 v1.4s, v11.8h, v0.8h
+183e0b0e| gnu umov w24, v16.b[5]
+c0a89b6f| gnu umull2 v0.2d, v6.4s, v27.s[2]
+36c0736e| gnu umull2 v22.4s, v1.8h, v19.8h
+120d757e| gnu uqadd h18, h8, h21
+3a0c2e2e| gnu uqadd v26.8b, v1.8b, v14.8b
+0d5d617e| gnu uqrshl h13, h8, h1
+4d5cb16e| gnu uqrshl v13.4s, v2.4s, v17.4s
+439c382f| gnu uqrshrn v3.2s, v2.2d, #8
+9d745c7f| gnu uqshl d29, d4, #28
+7b76656f| gnu uqshl v27.2d, v19.2d, #37
+774ef37e| gnu uqshl d23, d19, d19
+124eb32e| gnu uqshl v18.2s, v16.2s, v19.2s
+bc961f6f| gnu uqshrn2 v28.8h, v21.4s, #1
+a62ce07e| gnu uqsub d6, d5, d0
+0f2dae2e| gnu uqsub v15.2s, v8.2s, v14.2s
+b24b217e| gnu uqxtn b18, h29
+f148216e| gnu uqxtn2 v17.16b, v7.8h
+7d15a42e| gnu urhadd v29.2s, v11.2s, v4.2s
+9055fc6e| gnu urshl v16.2d, v12.2d, v28.2d
+eb275e7f| gnu urshr d11, d31, #34
+c0347c7f| gnu ursra d0, d6, #4
+fe44e97e| gnu ushl d30, d7, d9
+fa47e86e| gnu ushl v26.2d, v31.2d, v8.2d
+95a7262f| gnu ushll v21.2d, v28.2s, #6
+9ca7096f| gnu ushll2 v28.8h, v28.16b, #1
+8a07527f| gnu ushr d10, d28, #46
+c7076b6f| gnu ushr v7.2d, v30.2d, #21
+8d39e07e| gnu usqadd d13, d12
+f716727f| gnu usra d23, d23, #14
+3f14066f| gnu bic v31.4s, #0xc1
+b423ac2e| gnu usubl v20.2d, v29.2s, v12.2s
+7c22736e| gnu usubl2 v28.4s, v19.8h, v19.8h
+76317d2e| gnu usubw v22.4s, v11.4s, v29.4h
+8f302a6e| gnu usubw2 v15.8h, v4.8h, v10.16b
+c5a4286f| gnu ushll2 v5.2d, v6.4s, #8
+d3198c0e| gnu uzp1 v19.2s, v14.2s, v12.2s
+c05bdb4e| gnu uzp2 v0.2d, v30.2d, v27.2d
+362b610e| gnu xtn v22.4h, v25.4s
+0c29214e| gnu xtn2 v12.16b, v8.8h
+2b39c64e| gnu zip1 v11.2d, v9.2d, v6.2d
+9500091a| gnu adc w21, w4, w9
+c2001a9a| gnu adc x2, x6, x26
+6a02163a| gnu adcs w10, w19, w22
+0c0118ba| gnu adcs x12, x8, x24
+b1c42b0b| gnu add w17, w5, w11, sxtw #1
+bf15368b| gnu add sp, x13, w22, uxtb #5
+be1f468b| gnu add x30, x29, x6, lsr #7
+8f51352b| gnu adds w15, w12, w21, uxtw #4
+97043eab| gnu adds x23, x4, w30, uxtb #1
+09b00931| gnu adds w9, w0, #0x26c
+4de204ab| gnu adds x13, x18, x4, lsl #56
+bba87030| gnu adr x27, .+0xe1515
+a9bf40d0| gnu adrp x9, .+0x817f6000
+f6b60912| gnu and w22, w23, #0xff9fff9f
+a6d13b92| gnu and x6, x13, #0xe3e3e3e3e3e3e3e3
+1cc0138a| gnu and x28, x0, x19, lsl #48
+73882072| gnu ands w19, w3, #0x70007
+b5780af2| gnu ands x21, x5, #0xffdfffffffdfffff
+766c90ea| gnu ands x22, x3, x16, asr #27
+a72ac31a| gnu asr w7, w21, w3
+ff28d59a| gnu asr xzr, x7, x21
+3e7f0913| gnu asr w30, w25, #9
+bafd5493| gnu asr x26, x13, #20
+302ad21a| gnu asr w16, w17, w18
+602bd79a| gnu asr x0, x27, x23
+4fa4df54| gnu b.al .+0xfffffffffffbf488
+a2e9cf15| gnu b .+0x73fa688
+eff373b3| gnu bfxil x15, xzr, #51, #10
+9e3e7db3| gnu bfi x30, x20, #3, #16
+87fa41b3| gnu bfxil x7, x20, #1, #62
+b831f80a| gnu bic w24, w13, w24, ror #12
+ffe0ae8a| gnu bic xzr, x7, x14, asr #56
+7c2c276a| gnu bics w28, w3, w7, lsl #11
+ccf2fbea| gnu bics x12, x22, x27, ror #60
+722cd195| gnu bl .+0x744b1c8
+20003fd6| gnu blr x1
+e0021fd6| gnu br x23
+80db37d4| gnu brk #0xbedc
+f25a4335| gnu cbnz w18, .+0x86b5c
+5d5376b5| gnu cbnz x29, .+0xeca68
+5ce56834| gnu cbz w28, .+0xd1ca8
+29b08cb4| gnu cbz x9, .+0xfffffffffff19604
+e048533a| gnu ccmn w7, #0x13, #0x0, mi
+e7da4fba| gnu ccmn x23, #0xf, #0x7, le
+67f2583a| gnu ccmn w19, w24, #0x7, al
+60a05aba| gnu ccmn x3, x26, #0x0, ge
+6a3b517a| gnu ccmp w27, #0x11, #0xa, cc
+8a4b55fa| gnu ccmp x28, #0x15, #0xa, mi
+ed934b7a| gnu ccmp wzr, w11, #0xd, ls
+24414ffa| gnu ccmp x9, x15, #0x4, mi
+0e169c1a| gnu csinc w14, w16, w28, ne
+8264949a| gnu csinc x2, x4, x20, vs
+b363935a| gnu csinv w19, w29, w19, vs
+ff619dda| gnu csinv xzr, x15, x29, vs
+5f3703d5| gnu clrex #0x7
+0017c05a| gnu cls w0, w24
+8216c0da| gnu cls x2, x20
+3310c05a| gnu clz w19, w1
+6e13c0da| gnu clz x14, x27
+7fd02b2b| gnu cmn w3, w11, sxtw #4
+5f3928ab| gnu cmn x10, w8, uxth #6
+1fb92cb1| gnu cmn x8, #0xb2e
+ff164eab| gnu cmn x23, x14, lsr #5
+ff71256b| gnu cmp w15, w5, uxtx #4
+df6034eb| gnu cmp x6, x20, uxtx
+ff776af1| gnu cmp sp, #0xa9d, lsl #12
+80e4855a| gnu csneg w0, w4, w5, al
+da3490da| gnu csneg x26, x6, x16, cc
+af40c71a| gnu crc32b w15, w5, w7
+c546cf1a| gnu crc32h w5, w22, w15
+6148c01a| gnu crc32w w1, w3, w0
+0f4eda9a| gnu crc32x w15, w16, x26
+4950d01a| gnu crc32cb w9, w2, w16
+8155c31a| gnu crc32ch w1, w12, w3
+835ace1a| gnu crc32cw w3, w20, w14
+f05fc59a| gnu crc32cx w16, wzr, x5
+0ae3901a| gnu csel w10, w24, w16, al
+ed51969a| gnu csel x13, x15, x22, pl
+ee679f1a| gnu cset w14, vc
+ed579f9a| gnu cset x13, mi
+f2539f5a| gnu csetm w18, mi
+ffe39fda| gnu csinv xzr, xzr, xzr, al
+9d25941a| gnu csinc w29, w12, w20, cs
+afb7829a| gnu csinc x15, x29, x2, lt
+7602895a| gnu csinv w22, w19, w9, eq
+011394da| gnu csinv x1, x24, x20, ne
+68b7935a| gnu csneg w8, w27, w19, lt
+a32784da| gnu csneg x3, x29, x4, cs
+8159a6d4| gnu dcps1 #0x32cc
+c2d9aad4| gnu dcps2 #0x56ce
+63ceb7d4| gnu dcps3 #0xbe73
+bf3903d5| gnu dmb ishld
+e003bfd6| gnu drps
+9f3603d5| gnu dsb nshst
+fc76a9ca| gnu eon x28, x23, x9, asr #29
+540f2352| gnu eor w20, w26, #0xe0000001
+187e1ed2| gnu eor x24, x16, #0xffffffffffffffff
+fd37004a| gnu eor w29, wzr, w0, lsl #13
+b8c542ca| gnu eor x24, x13, x2, lsr #49
+e0039fd6| gnu eret
+5f26c193| gnu extr xzr, x18, x1, #9
+7f2003d5| gnu wfi
+ff2a03d5| gnu hint #0x57
+804a59d4| gnu hlt #0xca54
+df3003d5| gnu isb #0x0
+10fcdf88| gnu ldar w16, [x0]
+fafcdfc8| gnu ldar x26, [x7]
+30fedf08| gnu ldarb w16, [x17]
+63fedf48| gnu ldarh w3, [x19]
+82ba7f88| gnu ldaxp w2, w14, [x20]
+d6917fc8| gnu ldaxp x22, x4, [x14]
+59ff5f88| gnu ldaxr w25, [x26]
+fefe5fc8| gnu ldaxr x30, [x23]
+a0fc5f08| gnu ldaxrb w0, [x5]
+fafd5f48| gnu ldaxrh w26, [x15]
+b8804428| gnu ldnp w24, w0, [x5,#36]
+93e969a8| gnu ldnp x19, x26, [x12,#-360]
+caccef28| gnu ldp w10, w19, [x6],#-132
+7365c3a8| gnu ldp x19, x25, [x11],#48
+3106ca29| gnu ldp w17, w1, [x17,#80]!
+0c02f7a9| gnu ldp x12, x0, [x16,#-144]!
+41af6529| gnu ldp w1, w11, [x26,#-212]
+706b65a9| gnu ldp x16, x26, [x27,#-432]
+746ecf68| gnu ldpsw x20, x27, [x19],#120
+c051c669| gnu ldpsw x0, x20, [x14,#48]!
+aded5b69| gnu ldpsw x13, x27, [x13,#220]
+990457b8| gnu ldr w25, [x4],#-144
+bbd556f8| gnu ldr x27, [x13],#-147
+a45c51b8| gnu ldr w4, [x5,#-235]!
+344c41f8| gnu ldr x20, [x1,#20]!
+2d8755b9| gnu ldr w13, [x25,#5508]
+56e360f9| gnu ldr x22, [x26,#16832]
+1739b718| gnu ldr w23, .+0xfffffffffff6e720
+97b91c58| gnu ldr x23, .+0x39730
+3b264e38| gnu ldrb w27, [x17],#226
+898f5738| gnu ldrb w9, [x28,#-136]!
+c44e6839| gnu ldrb w4, [x22,#2579]
+2d687738| gnu ldrb w13, [x1,x23]
+4d475978| gnu ldrh w13, [x26],#-108
+39de5278| gnu ldrh w25, [x17,#-211]!
+9cc54879| gnu ldrh w28, [x12,#1122]
+87fb6978| gnu ldrh w7, [x28,x9,sxtx #1]
+3967cb38| gnu ldrsb w25, [x25],#182
+abf69438| gnu ldrsb x11, [x21],#-177
+159ed138| gnu ldrsb w21, [x16,#-231]!
+b63e8038| gnu ldrsb x22, [x21,#3]!
+4491c939| gnu ldrsb w4, [x10,#612]
+497e8039| gnu ldrsb x9, [x18,#31]
+7d6bf638| gnu ldrsb w29, [x27,x22]
+e578ba38| gnu ldrsb x5, [x7,x26,lsl #0]
+9f06ca78| gnu ldrsh wzr, [x20],#160
+15c59d78| gnu ldrsh x21, [x8],#-36
+c07fd278| gnu ldrsh w0, [x30,#-217]!
+bdec9278| gnu ldrsh x29, [x5,#-210]!
+10e2c979| gnu ldrsh w16, [x16,#1264]
+54d29d79| gnu ldrsh x20, [x18,#3816]
+eb9484b8| gnu ldrsw x11, [x7],#73
+ba2e8ab8| gnu ldrsw x26, [x21,#162]!
+ac7f8ab9| gnu ldrsw x12, [x29,#2684]
+9466e898| gnu ldrsw x20, .+0xfffffffffffd0cd0
+a359b3b8| gnu ldrsw x3, [x13,w19,uxtw #2]
+f8b941b8| gnu ldtr w24, [x15,#27]
+fc0a4ef8| gnu ldtr x28, [x23,#224]
+60d84638| gnu ldtrb w0, [x3,#109]
+44685978| gnu ldtrh w4, [x2,#-106]
+5379dc38| gnu ldtrsb w19, [x10,#-57]
+ade99538| gnu ldtrsb x13, [x13,#-162]
+905ac078| gnu ldtrsh w16, [x20,#5]
+10898478| gnu ldtrsh x16, [x8,#72]
+37188eb8| gnu ldtrsw x23, [x1,#225]
+992351b8| gnu ldur w25, [x28,#-238]
+c9f155f8| gnu ldur x9, [x14,#-161]
+76e14e38| gnu ldurb w22, [x11,#238]
+47b24478| gnu ldurh w7, [x18,#75]
+4020da38| gnu ldursb w0, [x2,#-94]
+0dd09e38| gnu ldursb x13, [x0,#-19]
+8f81d478| gnu ldursh w15, [x12,#-184]
+96918378| gnu ldursh x22, [x12,#57]
+b2e383b8| gnu ldursw x18, [x29,#62]
+d3717f88| gnu ldxp w19, w28, [x14]
+cb677fc8| gnu ldxp x11, x25, [x30]
+ed7c5f88| gnu ldxr w13, [x7]
+aa7d5fc8| gnu ldxr x10, [x13]
+1c7d5f08| gnu ldxrb w28, [x8]
+de7f5f48| gnu ldxrh w30, [x30]
+1622dc1a| gnu lsl w22, w16, w28
+cd20d59a| gnu lsl x13, x6, x21
+882957d3| gnu ubfiz x8, x12, #41, #11
+3320cc1a| gnu lsl w19, w1, w12
+7320de9a| gnu lsl x19, x3, x30
+af25d31a| gnu lsr w15, w13, w19
+e426c39a| gnu lsr x4, x23, x3
+e87f0653| gnu lsr w8, wzr, #6
+85fe5fd3| gnu lsr x5, x20, #31
+0025dc1a| gnu lsr w0, w8, w28
+6e27c79a| gnu lsr x14, x27, x7
+6d69111b| gnu madd w13, w11, w17, w26
+245d0d9b| gnu madd x4, x9, x13, x23
+85fe1f1b| gnu mneg w5, w20, wzr
+9bfc199b| gnu mneg x27, x4, x25
+13000011| gnu add w19, w0, #0x0
+e3000091| gnu add x3, x7, #0x0
+986c9e12| gnu mov w24, #0xffff0c9b
+cb24f092| gnu mov x11, #0x7ed9ffffffffffff
+3cbb88d2| gnu mov x28, #0x45d9
+e4170232| gnu mov w4, #0xc000000f
+fe636bb2| gnu mov x30, #0x3fffffe00000
+ed031b2a| gnu mov w13, w27
+fb0308aa| gnu mov x27, x8
+be3ed1f2| gnu movk x30, #0x89f5, lsl #32
+e0a08312| gnu mov w0, #0xffffe2f8
+a1a6e592| gnu mov x1, #0xd2caffffffffffff
+5260f0d2| gnu mov x18, #0x8302000000000000
+a60739d5| gnu mrs x6, s3_1_c0_c7_5
+281a1ed5| gnu msr s3_6_c1_c10_1, x8
+10f31b1b| gnu msub w16, w24, w27, w28
+46b41a9b| gnu msub x6, x2, x26, x13
+ec7f041b| gnu mul w12, wzr, w4
+147f009b| gnu mul x20, x24, x0
+f67f692a| gnu mvn w22, w9, lsr #31
+f2a3f7aa| gnu mvn x18, x23, ror #40
+fe8b0bcb| gnu neg x30, x11, lsl #34
+fef710eb| gnu negs x30, x16, lsl #61
+e0031b5a| gnu ngc w0, w27
+e0031dda| gnu ngc x0, x29
+f003167a| gnu ngcs w16, w22
+e60302fa| gnu ngcs x6, x2
+1f2003d5| gnu nop
+2f51732a| gnu orn w15, w9, w19, lsr #20
+9b0facaa| gnu orn x27, x28, x12, asr #3
+efa40032| gnu orr w15, w7, #0x3ff03ff
+3a0b19b2| gnu orr x26, x25, #0x38000000380
+4b9ec4aa| gnu orr x11, x18, x4, ror #39
+f5eaa2f9| gnu prfm pstl3strm, [x23,#17872]
+731df8d8| gnu prfm pstl2strm, .+0xffffffffffff03ac
+85c194f8| gnu prfum pldl3strm, [x12,#-180]
+c303c05a| gnu rbit w3, w30
+3000c0da| gnu rbit x16, x1
+20025fd6| gnu ret x17
+ec08c05a| gnu rev w12, w7
+180cc0da| gnu rev x24, x0
+4b07c05a| gnu rev16 w11, w26
+7805c0da| gnu rev16 x24, x11
+ea08c0da| gnu rev32 x10, x7
+a90fc0da| gnu rev x9, x29
+fd788213| gnu extr w29, w7, w2, #30
+e1a0cc93| gnu extr x1, x7, x12, #40
+792fdc1a| gnu ror w25, w27, w28
+2b2cc39a| gnu ror x11, x1, x3
+7e2ec71a| gnu ror w30, w19, w7
+392edd9a| gnu ror x25, x17, x29
+47020a5a| gnu sbc w7, w18, w10
+b7021dda| gnu sbc x23, x21, x29
+7800197a| gnu sbcs w24, w3, w25
+1e0203fa| gnu sbcs x30, x16, x3
+a6b07393| gnu sbfiz x6, x5, #13, #45
+94957d93| gnu sbfiz x20, x12, #3, #38
+ecff5e93| gnu asr x12, xzr, #30
+a50ddb1a| gnu sdiv w5, w13, w27
+7c0ec89a| gnu sdiv x28, x19, x8
+9f2003d5| gnu sev
+bf2003d5| gnu sevl
+5953349b| gnu smaddl x25, w26, w20, x20
+bafc399b| gnu smnegl x26, w5, w25
+a5cc289b| gnu smsubl x5, w5, w8, x19
+297c579b| gnu smulh x9, x1, x23
+5e7e299b| gnu smull x30, w18, w9
+29fd9f88| gnu stlr w9, [x9]
+fdff9fc8| gnu stlr x29, [sp]
+defe9f08| gnu stlrb w30, [x22]
+2ffc9f48| gnu stlrh w15, [x1]
+c1e12f88| gnu stlxp w15, w1, w24, [x14]
+62aa2ec8| gnu stlxp w14, x2, x10, [x19]
+b9fe1b88| gnu stlxr w27, w25, [x21]
+cbff14c8| gnu stlxr w20, x11, [x30]
+edfc0608| gnu stlxrb w6, w13, [x7]
+8dfe1048| gnu stlxrh w16, w13, [x20]
+1a323628| gnu stnp w26, w12, [x16,#-80]
+b3cb3da8| gnu stnp x19, x18, [x29,#-40]
+52398828| gnu stp w18, w14, [x10],#64
+434c95a8| gnu stp x3, x19, [x2],#336
+2badbd29| gnu stp w11, w11, [x9,#-20]!
+daeabaa9| gnu stp x26, x26, [x22,#-88]!
+9bc91529| gnu stp w27, w18, [x12,#172]
+eea024a9| gnu stp x14, x8, [x7,#-440]
+fec514b8| gnu str w30, [x15],#-180
+d21508f8| gnu str x18, [x14],#129
+7c5c0ab8| gnu str w28, [x3,#165]!
+6dec1ff8| gnu str x13, [x3,#-2]!
+35681eb9| gnu str w21, [x1,#7784]
+374d35f9| gnu str x23, [x9,#27288]
+1dd83df8| gnu str x29, [x0,w29,sxtw #3]
+1b441b38| gnu strb w27, [x0],#-76
+d69c0f38| gnu strb w22, [x6,#249]!
+b7ce0d39| gnu strb w23, [x21,#883]
+2b7b3938| gnu strb w11, [x25,x25,lsl #0]
+4e771d78| gnu strh w14, [x26],#-41
+64cc0b78| gnu strh w4, [x3,#188]!
+07b90279| gnu strh w7, [x8,#348]
+2eb91cb8| gnu sttr w14, [x9,#-53]
+373a1bf8| gnu sttr x23, [x17,#-77]
+d0881138| gnu sttrb w16, [x6,#-232]
+941a0e78| gnu sttrh w20, [x20,#225]
+da3000b8| gnu stur w26, [x6,#3]
+5e921cf8| gnu stur x30, [x18,#-55]
+09821e38| gnu sturb w9, [x16,#-24]
+67d21c78| gnu sturh w7, [x19,#-51]
+0c352188| gnu stxp w1, w12, w13, [x8]
+146d26c8| gnu stxp w6, x20, x27, [x8]
+837d1888| gnu stxr w24, w3, [x12]
+f17f1bc8| gnu stxr w27, x17, [sp]
+3b7d0f08| gnu stxrb w15, w27, [x9]
+6b7c1f48| gnu stxrh wzr, w11, [x3]
+70ab204b| gnu sub w16, w27, w0, sxth #2
+303b20cb| gnu sub x16, x25, w0, uxth #6
+69a909d1| gnu sub x9, x11, #0x26a
+87384e4b| gnu sub w7, w4, w14, lsr #14
+ec720ecb| gnu sub x12, x23, x14, lsl #28
+2b58256b| gnu subs w11, w1, w5, uxtw #6
+59e93ceb| gnu subs x25, x10, x28, sxtx #2
+9e7b6ff1| gnu subs x30, x28, #0xbde, lsl #12
+3e6d196b| gnu subs w30, w9, w25, lsl #27
+54029ceb| gnu subs x20, x18, x28, asr #0
+c1f91cd4| gnu svc #0xe7ce
+091e0013| gnu sxtb w9, w16
+7f1c4093| gnu sxtb xzr, w3
+b53c0013| gnu sxth w21, w5
+773e4093| gnu sxth x23, w19
+707f4093| gnu sxtw x16, w27
+df3a2dd5| gnu sysl xzr, #5, C3, C10, #6
+607f3137| gnu tbnz w0, #6, .+0x2fec
+3b700c36| gnu tbz w27, #1, .+0xffffffffffff8e04
+5f612972| gnu tst w10, #0xff80ffff
+bf2007f2| gnu tst x5, #0xfe000003fe000003
+1f11136a| gnu tst w8, w19, lsl #4
+5fd10dea| gnu tst x10, x13, lsl #52
+5c826bd3| gnu ubfiz x28, x18, #21, #33
+ad690c53| gnu ubfx w13, w13, #12, #15
+3a0f41d3| gnu ubfx x26, x25, #1, #3
+6a197dd3| gnu ubfiz x10, x11, #3, #7
+520aca1a| gnu udiv w18, w18, w10
+0809c89a| gnu udiv x8, x8, x8
+4e55a69b| gnu umaddl x14, w10, w6, x21
+99fda59b| gnu umnegl x25, w12, w5
+1adabb9b| gnu umsubl x26, w16, w27, x22
+177ddf9b| gnu umulh x23, x8, xzr
+1d7da49b| gnu umull x29, w8, w4
+5a1c0053| gnu uxtb w26, w2
+603c0053| gnu uxth w0, w3
+5f2003d5| gnu wfe
+7f2003d5| gnu wfi
+3f2003d5| gnu yield
+02b8600e| gnu abs v2.4h, v0.4h
+c886f94e| gnu add v8.2d, v22.2d, v25.2d
+5642740e| gnu addhn v22.4h, v18.4s, v20.4s
+3743294e| gnu addhn2 v23.16b, v25.8h, v9.8h
+2abef74e| gnu addp v10.2d, v17.2d, v23.2d
+18bbb14e| gnu addv s24, v24.4s
+1a59284e| gnu aesd v26.16b, v8.16b
+cf48284e| gnu aese v15.16b, v6.16b
+557a284e| gnu aesimc v21.16b, v18.16b
+2f6b284e| gnu aesmc v15.16b, v25.16b
+cf1c324e| gnu and v15.16b, v6.16b, v18.16b
+c9c6032f| gnu mvni v9.2s, #0x76, msl #8
+f1a7012f| gnu mvni v17.4h, #0x3f, lsl #8
+691d600e| gnu bic v9.8b, v11.8b, v0.8b
+c31dfe6e| gnu bif v3.16b, v14.16b, v30.16b
+c81cb66e| gnu bit v8.16b, v6.16b, v22.16b
+701f6b2e| gnu bsl v16.8b, v27.8b, v11.8b
+7c4b600e| gnu cls v28.4h, v27.4h
+ce4a602e| gnu clz v14.4h, v22.4h
+d08de37e| gnu cmeq d16, d14, d3
+e98db96e| gnu cmeq v9.4s, v15.4s, v25.4s
+6e99a00e| gnu cmeq v14.2s, v11.2s, #0
+933d304e| gnu cmge v19.16b, v12.16b, v16.16b
+0e88e07e| gnu cmge d14, d0, #0
+9b89202e| gnu cmge v27.8b, v12.8b, #0
+6a372f4e| gnu cmgt v10.16b, v27.16b, v15.16b
+128be05e| gnu cmgt d18, d24, #0
+9189a00e| gnu cmgt v17.2s, v12.2s, #0
+f734e67e| gnu cmhi d23, d7, d6
+4d36b82e| gnu cmhi v13.2s, v18.2s, v24.2s
+003e2b2e| gnu cmhs v0.8b, v16.8b, v11.8b
+729ae07e| gnu cmle d18, d19, #0
+3699206e| gnu cmle v22.16b, v9.16b, #0
+d1ab600e| gnu cmlt v17.4h, v30.4h, #0
+ad8e244e| gnu cmtst v13.16b, v21.16b, v4.16b
+ef06035e| gnu mov b15, v23.b[1]
+5007040e| gnu dup v16.2s, v26.s[0]
+890e0b4e| gnu dup v9.16b, w20
+951c276e| gnu eor v21.16b, v4.16b, v7.16b
+98d4bf7e| gnu fabd s24, s4, s31
+bcd4ad6e| gnu fabd v28.4s, v5.4s, v13.4s
+78f8e04e| gnu fabs v24.2d, v3.2d
+8cc0201e| gnu fabs s12, s4
+9ac1601e| gnu fabs d26, d12
+3aee307e| gnu facge s26, s17, s16
+41ed352e| gnu facge v1.2s, v10.2s, v21.2s
+35edaf7e| gnu facgt s21, s9, s15
+02efe36e| gnu facgt v2.2d, v24.2d, v3.2d
+21d6664e| gnu fadd v1.2d, v17.2d, v6.2d
+5e282e1e| gnu fadd s30, s2, s14
+4d2a621e| gnu fadd d13, d18, d2
+7cd8707e| gnu faddp d28, v3.2d
+5dd4386e| gnu faddp v29.4s, v2.4s, v24.4s
+69363e1e| gnu fccmp s19, s30, #0x9, cc
+c8b56a1e| gnu fccmp d14, d10, #0x8, lt
+d1f5271e| gnu fccmpe s14, s7, #0x1, al
+3645751e| gnu fccmpe d9, d21, #0x6, mi
+21e6735e| gnu fcmeq d1, d17, d19
+b6dba05e| gnu fcmeq s22, s29, #0
+49d8a04e| gnu fcmeq v9.4s, v2.4s, #0
+2ee5667e| gnu fcmge d14, d9, d6
+4ee7766e| gnu fcmge v14.2d, v26.2d, v22.2d
+4bcba07e| gnu fcmge s11, s26, #0
+11c9a02e| gnu fcmge v17.2s, v8.2s, #0
+81e4a97e| gnu fcmgt s1, s4, s9
+d3e4b56e| gnu fcmgt v19.4s, v6.4s, v21.4s
+efc8e05e| gnu fcmgt d15, d7, #0
+3ec9e04e| gnu fcmgt v30.2d, v9.2d, #0
+38d9a07e| gnu fcmle s24, s9, #0
+7dd9a02e| gnu fcmle v29.2s, v11.2s, #0
+bae8a05e| gnu fcmlt s26, s5, #0
+a2eaa04e| gnu fcmlt v2.4s, v21.4s, #0
+60212f1e| gnu fcmp s11, s15
+a8233a1e| gnu fcmp s29, #0
+a020641e| gnu fcmp d5, d4
+e820701e| gnu fcmp d7, #0
+b0203a1e| gnu fcmpe s5, s26
+78203d1e| gnu fcmpe s3, #0
+70226e1e| gnu fcmpe d19, d14
+3821601e| gnu fcmpe d9, #0
+06de241e| gnu fcsel s6, s16, s4, le
+51de761e| gnu fcsel d17, d18, d22, le
+5e42e21e| gnu fcvt s30, h18
+b9c1e21e| gnu fcvt d25, h13
+58c0231e| gnu fcvt h24, s2
+9bc2221e| gnu fcvt d27, s20
+2bc3631e| gnu fcvt h11, d25
+f640621e| gnu fcvt s22, d7
+caca215e| gnu fcvtas s10, s22
+5ec9210e| gnu fcvtas v30.2s, v10.2s
+0302241e| gnu fcvtas w3, s16
+c103249e| gnu fcvtas x1, s30
+3003641e| gnu fcvtas w16, d25
+6201649e| gnu fcvtas x2, d11
+d3c9217e| gnu fcvtau s19, s14
+3bc8212e| gnu fcvtau v27.2s, v1.2s
+0802251e| gnu fcvtau w8, s16
+5f02259e| gnu fcvtau xzr, s18
+2801651e| gnu fcvtau w8, d9
+f200659e| gnu fcvtau x18, d7
+d179610e| gnu fcvtl v17.2d, v14.2s
+347b614e| gnu fcvtl2 v20.2d, v25.4s
+08b9615e| gnu fcvtms d8, d8
+f000301e| gnu fcvtms w16, s7
+8002309e| gnu fcvtms x0, s20
+5202701e| gnu fcvtms w18, d18
+c803709e| gnu fcvtms x8, d30
+1cbb217e| gnu fcvtmu s28, s24
+d1b9212e| gnu fcvtmu v17.2s, v14.2s
+2e02311e| gnu fcvtmu w14, s17
+d003319e| gnu fcvtmu x16, s30
+ce03711e| gnu fcvtmu w14, d30
+0801719e| gnu fcvtmu x8, d8
+4c6b210e| gnu fcvtn v12.4h, v26.4s
+6869214e| gnu fcvtn2 v8.8h, v11.4s
+2faa615e| gnu fcvtns d15, d17
+33aa614e| gnu fcvtns v19.2d, v17.2d
+d303201e| gnu fcvtns w19, s30
+4001209e| gnu fcvtns x0, s10
+b202601e| gnu fcvtns w18, d21
+c603609e| gnu fcvtns x6, d30
+8ea8217e| gnu fcvtnu s14, s4
+cc01211e| gnu fcvtnu w12, s14
+3a00219e| gnu fcvtnu x26, s1
+2002611e| gnu fcvtnu w0, d17
+ff01619e| gnu fcvtnu xzr, d15
+1baba15e| gnu fcvtps s27, s24
+9d00281e| gnu fcvtps w29, s4
+eb02289e| gnu fcvtps x11, s23
+3503681e| gnu fcvtps w21, d25
+4301689e| gnu fcvtps x3, d10
+63aba17e| gnu fcvtpu s3, s27
+caa8a12e| gnu fcvtpu v10.2s, v6.2s
+7702291e| gnu fcvtpu w23, s19
+b503299e| gnu fcvtpu x21, s29
+2f03691e| gnu fcvtpu w15, d25
+5b01699e| gnu fcvtpu x27, d10
+7369617e| gnu fcvtxn s19, d11
+6b6b612e| gnu fcvtxn v11.2s, v27.2d
+f268616e| gnu fcvtxn2 v18.4s, v7.2d
+bcff7b5f| gnu fcvtzs d28, d29, #5
+19bbe15e| gnu fcvtzs d25, d24
+c6b9e14e| gnu fcvtzs v6.2d, v14.2d
+e9fc189e| gnu fcvtzs x9, s7, #1
+6661589e| gnu fcvtzs x6, d11, #40
+9702381e| gnu fcvtzs w23, s20
+ed00389e| gnu fcvtzs x13, s7
+3a01781e| gnu fcvtzs w26, d9
+8801789e| gnu fcvtzs x8, d12
+a5ff2e2f| gnu fcvtzu v5.2s, v29.2s, #18
+5bbbe17e| gnu fcvtzu d27, d26
+1a74199e| gnu fcvtzu x26, s0, #35
+e391599e| gnu fcvtzu x3, d15, #28
+b203391e| gnu fcvtzu w18, s29
+ed01399e| gnu fcvtzu x13, s15
+c200791e| gnu fcvtzu w2, d6
+5402799e| gnu fcvtzu x20, d18
+1aff2b6e| gnu fdiv v26.4s, v24.4s, v11.4s
+171a391e| gnu fdiv s23, s16, s25
+7d196b1e| gnu fdiv d29, d11, d11
+f9721f1f| gnu fmadd s25, s23, s31, s28
+7070551f| gnu fmadd d16, d3, d21, d28
+05f7624e| gnu fmax v5.2d, v24.2d, v2.2d
+88493d1e| gnu fmax s8, s12, s29
+4a496d1e| gnu fmax d10, d10, d13
+5068321e| gnu fmaxnm s16, s2, s18
+a66a761e| gnu fmaxnm d6, d21, d22
+0ccb707e| gnu fmaxnmp d12, v24.2d
+6ec66f6e| gnu fmaxnmp v14.2d, v19.2d, v15.2d
+41f8307e| gnu fmaxp s1, v2.2s
+05f72a6e| gnu fmaxp v5.4s, v24.4s, v10.4s
+aa5b231e| gnu fmin s10, s29, s3
+d6596a1e| gnu fmin d22, d14, d10
+15c4b24e| gnu fminnm v21.4s, v0.4s, v18.4s
+6279281e| gnu fminnm s2, s11, s8
+af7b6a1e| gnu fminnm d15, d29, d10
+7dc9f07e| gnu fminnmp d29, v11.2d
+dfc6bb6e| gnu fminnmp v31.4s, v22.4s, v27.4s
+56c8b06e| gnu fminnmv s22, v2.4s
+0ff8f07e| gnu fminp d15, v0.2d
+a211c55f| gnu fmla d2, d13, v5.d[0]
+0dce224e| gnu fmla v13.4s, v16.4s, v2.4s
+4c5ba15f| gnu fmls s12, s26, v1.s[3]
+8953ba0f| gnu fmls v9.2s, v28.2s, v26.s[1]
+09cdbd4e| gnu fmls v9.4s, v8.4s, v29.4s
+97f7044f| gnu fmov v23.4s, #-7.000000000000000000e+00
+dff4006f| gnu fmov v31.2d, #2.750000000000000000e+00
+c543201e| gnu fmov s5, s30
+1740601e| gnu fmov d23, d0
+a100271e| gnu fmov s1, w5
+f102261e| gnu fmov w17, s23
+b302679e| gnu fmov d19, x21
+4001af9e| gnu fmov v0.d[1], x10
+db01669e| gnu fmov x27, d14
+8300ae9e| gnu fmov x3, v4.d[1]
+1870331e| gnu fmov s24, #-6.750000000000000000e+00
+08507d1e| gnu fmov d8, #-8.125000000000000000e-01
+5cbf0c1f| gnu fmsub s28, s26, s12, s15
+89e3501f| gnu fmsub d9, d28, d16, d24
+3a93c95f| gnu fmul d26, d25, v9.d[0]
+5a90ae4f| gnu fmul v26.4s, v2.4s, v14.s[1]
+ba0a2f1e| gnu fmul s26, s21, s15
+5b0a7c1e| gnu fmul d27, d18, d28
+e991c07f| gnu fmulx d9, d15, v0.d[0]
+be989c6f| gnu fmulx v30.4s, v5.4s, v28.s[2]
+d3dc7a5e| gnu fmulx d19, d6, d26
+d4de7f4e| gnu fmulx v20.2d, v22.2d, v31.2d
+8e41211e| gnu fneg s14, s12
+dc42611e| gnu fneg d28, d22
+cb362e1f| gnu fnmadd s11, s22, s14, s13
+6441791f| gnu fnmadd d4, d11, d25, d16
+36ed291f| gnu fnmsub s22, s9, s9, s27
+35b27a1f| gnu fnmsub d21, d17, d26, d12
+9388301e| gnu fnmul s19, s4, s16
+c088711e| gnu fnmul d0, d6, d17
+e8daa15e| gnu frecpe s8, s23
+a9fc395e| gnu frecps s9, s5, s25
+49fe284e| gnu frecps v9.4s, v18.4s, v8.4s
+85f8a15e| gnu frecpx s5, s4
+ee43261e| gnu frinta s14, s31
+7042661e| gnu frinta d16, d19
+2b98a16e| gnu frinti v11.4s, v1.4s
+fac2271e| gnu frinti s26, s23
+76c3671e| gnu frinti d22, d27
+7942251e| gnu frintm s25, s19
+8742651e| gnu frintm d7, d20
+fc8a214e| gnu frintn v28.4s, v23.4s
+c041241e| gnu frintn s0, s14
+b241641e| gnu frintn d18, d13
+c588a14e| gnu frintp v5.4s, v6.4s
+6ec2241e| gnu frintp s14, s19
+ddc0641e| gnu frintp d29, d6
+1a9a616e| gnu frintx v26.2d, v16.2d
+7c41271e| gnu frintx s28, s11
+d243671e| gnu frintx d18, d30
+b49aa14e| gnu frintz v20.4s, v21.4s
+5bc0251e| gnu frintz s27, s2
+43c1651e| gnu frintz d3, d10
+3bdba17e| gnu frsqrte s27, s25
+9ddba12e| gnu frsqrte v29.2s, v28.2s
+1ffee65e| gnu frsqrts d31, d16, d6
+8bfdb54e| gnu frsqrts v11.4s, v12.4s, v21.4s
+33c1211e| gnu fsqrt s19, s9
+a5c0611e| gnu fsqrt d5, d5
+a2d7b74e| gnu fsub v2.4s, v29.4s, v23.4s
+a338301e| gnu fsub s3, s5, s16
+e139681e| gnu fsub d1, d15, d8
+96170e6e| gnu mov v22.h[3], v28.h[1]
+791c014e| gnu mov v25.b[0], w3
+cf79404c| gnu ld1 {v15.4s}, [x14]
+75a6404c| gnu ld1 {v21.8h, v22.8h}, [x19]
+ed62404c| gnu ld1 {v13.16b-v15.16b}, [x23]
+392a400c| gnu ld1 {v25.2s-v28.2s}, [x17]
+cd7cdf4c| gnu ld1 {v13.2d}, [x6],#16
+f677ce4c| gnu ld1 {v22.8h}, [sp], x14
+d4a3df0c| gnu ld1 {v20.8b, v21.8b}, [x30],#16
+8ba1d90c| gnu ld1 {v11.8b, v12.8b}, [x12], x25
+396fdf0c| gnu ld1 {v25.1d-v27.1d}, [x25],#24
+4c64db0c| gnu ld1 {v12.4h-v14.4h}, [x2], x27
+3f2adf4c| gnu ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [x17],#64
+b329ce4c| gnu ld1 {v19.4s-v22.4s}, [x13], x14
+aa02400d| gnu ld1 {v10.b}[0], [x21]
+7980404d| gnu ld1 {v25.s}[2], [x3]
+5884404d| gnu ld1 {v24.d}[1], [x2]
+f203df4d| gnu ld1 {v18.b}[8], [sp],#1
+3519c40d| gnu ld1 {v21.b}[6], [x9], x4
+ed59df0d| gnu ld1 {v13.h}[3], [x15],#2
+9e52d90d| gnu ld1 {v30.h}[2], [x20], x25
+cd93df4d| gnu ld1 {v13.s}[3], [x30],#4
+5982cb4d| gnu ld1 {v25.s}[2], [x18], x11
+4f84df4d| gnu ld1 {v15.d}[1], [x2],#8
+2d85d50d| gnu ld1 {v13.d}[0], [x9], x21
+33c2400d| gnu ld1r {v19.8b}, [x17]
+e2c8df4d| gnu ld1r {v2.4s}, [x7],#4
+83c2c44d| gnu ld1r {v3.16b}, [x20], x4
+5487400c| gnu ld2 {v20.4h, v21.4h}, [x26]
+e08adf0c| gnu ld2 {v0.2s, v1.2s}, [x23],#16
+768ac40c| gnu ld2 {v22.2s, v23.2s}, [x19], x4
+4c0f604d| gnu ld2 {v12.b, v13.b}[11], [x26]
+e043604d| gnu ld2 {v0.h, v1.h}[4], [sp]
+c281600d| gnu ld2 {v2.s, v3.s}[0], [x14]
+e585600d| gnu ld2 {v5.d, v6.d}[0], [x15]
+2c1aff4d| gnu ld2 {v12.b, v13.b}[14], [x17],#2
+820bfd4d| gnu ld2 {v2.b, v3.b}[10], [x28], x29
+d593ff0d| gnu ld2 {v21.s, v22.s}[1], [x30],#8
+6780ea0d| gnu ld2 {v7.s, v8.s}[0], [x3], x10
+3484ff4d| gnu ld2 {v20.d, v21.d}[1], [x1],#16
+6a86ee4d| gnu ld2 {v10.d, v11.d}[1], [x19], x14
+e4c7604d| gnu ld2r {v4.8h, v5.8h}, [sp]
+69c8ff0d| gnu ld2r {v9.2s, v10.2s}, [x3],#8
+52ccf30d| gnu ld2r {v18.1d, v19.1d}, [x2], x19
+9e4b404c| gnu ld3 {v30.4s, v31.4s, v0.4s}, [x28]
+0440df4c| gnu ld3 {v4.16b-v6.16b}, [x0],#48
+0f49cf0c| gnu ld3 {v15.2s-v17.2s}, [x8], x15
+b22e400d| gnu ld3 {v18.b-v20.b}[3], [x21]
+9473400d| gnu ld3 {v20.h-v22.h}[2], [x28]
+1da0404d| gnu ld3 {v29.s-v31.s}[2], [x0]
+21a5404d| gnu ld3 {v1.d-v3.d}[1], [x9]
+3b23df0d| gnu ld3 {v27.b-v29.b}[0], [x25],#3
+0937c60d| gnu ld3 {v9.b-v11.b}[5], [x24], x6
+926bcb4d| gnu ld3 {v18.h-v20.h}[5], [x28], x11
+f5a1df4d| gnu ld3 {v21.s-v23.s}[2], [x15],#12
+dba3c44d| gnu ld3 {v27.s-v29.s}[2], [x30], x4
+12a5df0d| gnu ld3 {v18.d-v20.d}[0], [x8],#24
+daa7d30d| gnu ld3 {v26.d-v28.d}[0], [x30], x19
+3beb400d| gnu ld3r {v27.2s-v29.2s}, [x25]
+cde4df4d| gnu ld3r {v13.8h-v15.8h}, [x6],#6
+a4efc44d| gnu ld3r {v4.2d-v6.2d}, [x29], x4
+fc0a400c| gnu ld4 {v28.2s-v31.2s}, [x23]
+ae05df0c| gnu ld4 {v14.4h-v17.4h}, [x13],#32
+cb07c84c| gnu ld4 {v11.8h-v14.8h}, [x30], x8
+1825604d| gnu ld4 {v24.b-v27.b}[9], [x8]
+2869604d| gnu ld4 {v8.h-v11.h}[5], [x9]
+07b2600d| gnu ld4 {v7.s-v10.s}[1], [x16]
+9fa4600d| gnu ld4 {v31.d, v0.d, v1.d, v2.d}[0], [x4]
+de22ff0d| gnu ld4 {v30.b, v31.b, v0.b, v1.b}[0], [x22],#4
+6a36ed4d| gnu ld4 {v10.b-v13.b}[13], [x19], x13
+23a2ff4d| gnu ld4 {v3.s-v6.s}[2], [x17],#16
+22a0fe4d| gnu ld4 {v2.s-v5.s}[2], [x1], x30
+7ca4ff4d| gnu ld4 {v28.d-v31.d}[1], [x3],#32
+03a7ec4d| gnu ld4 {v3.d-v6.d}[1], [x24], x12
+b9ee600d| gnu ld4r {v25.1d-v28.1d}, [x21]
+03e8ff0d| gnu ld4r {v3.2s-v6.2s}, [x0],#16
+e7e3f24d| gnu ld4r {v7.16b-v10.16b}, [sp], x18
+451a4e2c| gnu ldnp s5, s6, [x18,#112]
+01236f6c| gnu ldnp d1, d8, [x24,#-272]
+204041ac| gnu ldnp q0, q16, [x1,#32]
+1b21cc2c| gnu ldp s27, s8, [x8],#96
+41ccc06c| gnu ldp d1, d19, [x2],#8
+65b8e6ac| gnu ldp q5, q14, [x3],#-816
+a58bed2d| gnu ldp s5, s2, [x29,#-148]!
+d8a3c46d| gnu ldp d24, d8, [x30,#72]!
+dc82c0ad| gnu ldp q28, q0, [x22,#16]!
+eda7782d| gnu ldp s13, s9, [sp,#-60]
+041b6c6d| gnu ldp d4, d6, [x24,#-320]
+17ea6bad| gnu ldp q23, q26, [x16,#-656]
+4e14433c| gnu ldr b14, [x2],#49
+cd844e7c| gnu ldr h13, [x6],#232
+99945dbc| gnu ldr s25, [x4],#-39
+170556fc| gnu ldr d23, [x8],#-160
+3115d53c| gnu ldr q17, [x9],#-175
+3c6d403c| gnu ldr b28, [x9,#6]!
+f8fc527c| gnu ldr h24, [x7,#-209]!
+776c58bc| gnu ldr s23, [x3,#-122]!
+075f57fc| gnu ldr d7, [x24,#-139]!
+28cdc33c| gnu ldr q8, [x9,#60]!
+40a15f3d| gnu ldr b0, [x10,#2024]
+3b8c597d| gnu ldr h27, [x1,#3270]
+28f958bd| gnu ldr s8, [x9,#6392]
+852d6ffd| gnu ldr d5, [x12,#24152]
+e149ea3d| gnu ldr q1, [x15,#43296]
+807f7c1c| gnu ldr s0, .+0xf8ff0
+e7a61c5c| gnu ldr d7, .+0x394dc
+261ec59c| gnu ldr q6, .+0xfffffffffff8a3c4
+4bca773c| gnu ldr b11, [x18,w23,sxtw]
+8d69623c| gnu ldr b13, [x12,x2]
+cef8797c| gnu ldr h14, [x6,x25,sxtx #1]
+b7497bfc| gnu ldr d23, [x13,w27,uxtw]
+dbdbfc3c| gnu ldr q27, [x30,w28,sxtw #4]
+1a60553c| gnu ldur b26, [x0,#-170]
+74f3477c| gnu ldur h20, [x27,#127]
+f46249bc| gnu ldur s20, [x23,#150]
+b8015bfc| gnu ldur d24, [x13,#-80]
+3372de3c| gnu ldur q19, [x17,#-25]
+04972c0e| gnu mla v4.8b, v24.8b, v12.8b
+f0051b5e| gnu mov b16, v15.b[13]
+7f76146e| gnu mov v31.s[2], v19.s[3]
+6c1cb60e| gnu orr v12.8b, v3.8b, v22.8b
+ae3f1e0e| gnu umov w14, v29.h[7]
+f8e5004f| gnu movi v24.16b, #0xf
+0355010f| gnu orr v3.2s, #0x28, lsl #16
+4825020f| gnu movi v8.2s, #0x4a, lsl #8
+64d7040f| gnu movi v4.2s, #0x9b, msl #16
+46e6062f| gnu movi d6, #0xffff00ff0000ff00
+bde6056f| gnu movi v29.2d, #0xff00ffff00ff00ff
+789f350e| gnu mul v24.8b, v27.8b, v21.8b
+7b5b202e| gnu mvn v27.8b, v27.8b
+2dd4066f| gnu mvni v13.4s, #0xc1, msl #16
+8266012f| gnu mvni v2.2s, #0x34, lsl #24
+1025022f| gnu mvni v16.2s, #0x48, lsl #8
+eabba06e| gnu neg v10.4s, v31.4s
+7e5a206e| gnu mvn v30.16b, v19.16b
+6a1fea0e| gnu orn v10.8b, v27.8b, v10.8b
+b406010f| gnu movi v20.2s, #0x35
+f564040f| gnu movi v21.2s, #0x87, lsl #24
+b21cb80e| gnu orr v18.8b, v5.8b, v24.8b
+2b437a2e| gnu raddhn v11.4h, v25.4s, v26.4s
+6d402c6e| gnu raddhn2 v13.16b, v3.8h, v12.8h
+655a606e| gnu rbit v5.16b, v19.16b
+5108202e| gnu rev32 v17.8b, v2.8b
+750a200e| gnu rev64 v21.8b, v19.8b
+f88f0b0f| gnu rshrn v24.8b, v31.8h, #5
+8263236e| gnu rsubhn2 v2.16b, v28.8h, v3.8h
+787c320e| gnu saba v24.8b, v3.8b, v18.8b
+f551220e| gnu sabal v21.8h, v15.8b, v2.8b
+b5766d0e| gnu sabd v21.4h, v21.4h, v13.4h
+9270240e| gnu sabdl v18.8h, v4.8b, v4.8b
+4d71384e| gnu sabdl2 v13.8h, v10.16b, v24.16b
+8f6a600e| gnu sadalp v15.2s, v20.4h
+e501750e| gnu saddl v5.4s, v15.4h, v21.4h
+5202ab4e| gnu saddl2 v18.2d, v18.4s, v11.4s
+7029200e| gnu saddlp v16.4h, v11.8b
+3913710e| gnu saddw v25.4s, v25.4s, v17.4h
+d7e4575f| gnu scvtf d23, d6, #41
+c6db215e| gnu scvtf s6, s30
+17d8214e| gnu scvtf v23.4s, v0.4s
+62c4021e| gnu scvtf s2, w3, #15
+f5cd421e| gnu scvtf d21, w15, #13
+6128029e| gnu scvtf s1, x3, #54
+9a7c429e| gnu scvtf d26, x4, #33
+6102221e| gnu scvtf s1, w19
+0b03621e| gnu scvtf d11, w24
+ed01229e| gnu scvtf s13, x15
+6f02629e| gnu scvtf d15, x19
+ac03055e| gnu sha1c q12, s29, v5.4s
+e309285e| gnu sha1h s3, s15
+2a221b5e| gnu sha1m q10, s17, v27.4s
+a013185e| gnu sha1p q0, s29, v24.4s
+6032005e| gnu sha1su0 v0.4s, v19.4s, v0.4s
+f918285e| gnu sha1su1 v25.4s, v7.4s
+fb50035e| gnu sha256h2 q27, q7, v3.4s
+6d421c5e| gnu sha256h q13, q19, v28.4s
+c12b285e| gnu sha256su0 v1.4s, v30.4s
+6362095e| gnu sha256su1 v3.4s, v19.4s, v9.4s
+a805bb0e| gnu shadd v8.2s, v13.2s, v27.2s
+783b616e| gnu shll2 v24.4s, v27.8h, #16
+48841b0f| gnu shrn v8.4h, v2.4s, #5
+a924bc4e| gnu shsub v9.4s, v5.4s, v28.4s
+1557717f| gnu sli d21, d24, #49
+2a56456f| gnu sli v10.2d, v17.2d, #5
+7c663b0e| gnu smax v28.8b, v19.8b, v27.8b
+b5a7694e| gnu smaxp v21.8h, v29.8h, v9.8h
+8ea8b04e| gnu smaxv s14, v4.4s
+936cb44e| gnu smin v19.4s, v4.4s, v20.4s
+15af7e4e| gnu sminp v21.8h, v24.8h, v30.8h
+3e81694e| gnu smlal2 v30.4s, v9.8h, v9.8h
+29a26d0e| gnu smlsl v9.4s, v17.4h, v13.4h
+442e0b4e| gnu smov x4, v18.b[5]
+e1a0540f| gnu smull v1.4s, v7.4h, v4.h[1]
+5eaa604f| gnu smull2 v30.4s, v18.8h, v0.h[6]
+4cc32d4e| gnu smull2 v12.8h, v26.16b, v13.16b
+1e7a205e| gnu sqabs b30, b16
+e67ae04e| gnu sqabs v6.2d, v23.2d
+a80ded5e| gnu sqadd d8, d13, d13
+e60dae4e| gnu sqadd v6.4s, v15.4s, v14.4s
+fe33570f| gnu sqdmlal v30.4s, v31.4h, v7.h[1]
+ee90b64e| gnu sqdmlal2 v14.2d, v7.4s, v22.4s
+ce79a05f| gnu sqdmlsl d14, s14, v0.s[3]
+d5b2a14e| gnu sqdmlsl2 v21.2d, v22.4s, v1.4s
+51cb575f| gnu sqdmulh h17, h26, v7.h[5]
+0cb5b54e| gnu sqdmulh v12.4s, v8.4s, v21.4s
+95d0760e| gnu sqdmull v21.4s, v4.4h, v22.4h
+a1d37c4e| gnu sqdmull2 v1.4s, v29.8h, v28.8h
+d679e07e| gnu sqneg d22, d14
+3f78602e| gnu sqneg v31.4h, v1.4h
+80b4717e| gnu sqrdmulh h0, h4, h17
+4cb76e2e| gnu sqrdmulh v12.4h, v26.4h, v14.4h
+aa5ce95e| gnu sqrshl d10, d5, d9
+d25fb74e| gnu sqrshl v18.4s, v30.4s, v23.4s
+998c0c6f| gnu sqrshrun2 v25.16b, v4.8h, #4
+4375605f| gnu sqshl d3, d10, #32
+de743f0f| gnu sqshl v30.2s, v6.2s, #31
+a84d675e| gnu sqshl h8, h13, h7
+674dbe4e| gnu sqshl v7.4s, v11.4s, v30.4s
+5165587f| gnu sqshlu d17, d10, #24
+b464042f| gnu mvni v20.2s, #0x85, lsl #24
+2086207f| gnu sqshrun s0, d17, #32
+8a851a2f| gnu sqshrun v10.4h, v12.4s, #6
+652c255e| gnu sqsub b5, b3, b5
+632eb30e| gnu sqsub v3.2s, v19.2s, v19.2s
+104ba15e| gnu sqxtn s16, d24
+2249214e| gnu sqxtn2 v2.16b, v9.8h
+1c14360e| gnu srhadd v28.8b, v0.8b, v22.8b
+8044076f| gnu mvni v0.4s, #0xe4, lsl #16
+3a57ed5e| gnu srshl d26, d25, d13
+2c56ef4e| gnu srshl v12.2d, v17.2d, v15.2d
+9627140f| gnu srshr v22.4h, v28.4h, #12
+bd37565f| gnu srsra d29, d29, #42
+db34594f| gnu srsra v27.2d, v6.2d, #39
+4546a10e| gnu sshl v5.2s, v18.2s, v1.2s
+aca7020f| gnu movi v12.4h, #0x5d, lsl #8
+e004675f| gnu sshr d0, d7, #25
+e5057f4f| gnu sshr v5.2d, v15.2d, #1
+1b15595f| gnu ssra d27, d8, #39
+ba15250f| gnu ssra v26.2s, v13.2s, #27
+3620330e| gnu ssubl v22.8h, v1.8b, v19.8b
+c1316d4e| gnu ssubw2 v1.4s, v14.4s, v13.8h
+8a76000c| gnu st1 {v10.4h}, [x20]
+10a5004c| gnu st1 {v16.8h, v17.8h}, [x8]
+ab6b004c| gnu st1 {v11.4s-v13.4s}, [x29]
+8d2b004c| gnu st1 {v13.4s-v16.4s}, [x28]
+8d7d9f0c| gnu st1 {v13.1d}, [x12],#8
+eb73840c| gnu st1 {v11.8b}, [sp], x4
+48a69f4c| gnu st1 {v8.8h, v9.8h}, [x18],#32
+dca19b4c| gnu st1 {v28.16b, v29.16b}, [x14], x27
+7c699f4c| gnu st1 {v28.4s-v30.4s}, [x11],#48
+da6d870c| gnu st1 {v26.1d-v28.1d}, [x14], x7
+7f279f0c| gnu st1 {v31.4h, v0.4h, v1.4h, v2.4h}, [x27],#32
+4421810c| gnu st1 {v4.8b-v7.8b}, [x10], x1
+a615004d| gnu st1 {v6.b}[13], [x13]
+ce92000d| gnu st1 {v14.s}[1], [x22]
+c985000d| gnu st1 {v9.d}[0], [x14]
+380f9f0d| gnu st1 {v24.b}[3], [x25],#1
+de0b944d| gnu st1 {v30.b}[10], [x30], x20
+3141880d| gnu st1 {v17.h}[0], [x9], x8
+8e939f0d| gnu st1 {v14.s}[1], [x28],#4
+c890870d| gnu st1 {v8.s}[1], [x6], x7
+9f869f4d| gnu st1 {v31.d}[1], [x20],#8
+38879b4d| gnu st1 {v24.d}[1], [x25], x27
+4181004c| gnu st2 {v1.16b, v2.16b}, [x10]
+d6819f0c| gnu st2 {v22.8b, v23.8b}, [x14],#16
+bf808a0c| gnu st2 {v31.8b, v0.8b}, [x5], x10
+bd0e204d| gnu st2 {v29.b, v30.b}[11], [x21]
+4551204d| gnu st2 {v5.h, v6.h}[6], [x10]
+9982204d| gnu st2 {v25.s, v26.s}[2], [x20]
+ea86200d| gnu st2 {v10.d, v11.d}[0], [x23]
+7b02bf0d| gnu st2 {v27.b, v28.b}[0], [x19],#2
+c000a04d| gnu st2 {v0.b, v1.b}[8], [x6], x0
+fb59a40d| gnu st2 {v27.h, v28.h}[3], [x15], x4
+f880bf0d| gnu st2 {v24.s, v25.s}[0], [x7],#8
+f582ac4d| gnu st2 {v21.s, v22.s}[2], [x23], x12
+9c86bf4d| gnu st2 {v28.d, v29.d}[1], [x20],#16
+3386b14d| gnu st2 {v19.d, v20.d}[1], [x17], x17
+c0469f0c| gnu st3 {v0.4h-v2.4h}, [x22],#24
+2243820c| gnu st3 {v2.8b-v4.8b}, [x25], x2
+c629000d| gnu st3 {v6.b-v8.b}[2], [x14]
+4f6a004d| gnu st3 {v15.h-v17.h}[5], [x18]
+72a0004d| gnu st3 {v18.s-v20.s}[2], [x3]
+c1a4000d| gnu st3 {v1.d-v3.d}[0], [x6]
+312e9f0d| gnu st3 {v17.b-v19.b}[3], [x17],#3
+9a28934d| gnu st3 {v26.b-v28.b}[10], [x4], x19
+a1799f4d| gnu st3 {v1.h-v3.h}[7], [x13],#6
+3ba29f0d| gnu st3 {v27.s-v29.s}[0], [x17],#12
+80b2870d| gnu st3 {v0.s-v2.s}[1], [x20], x7
+f6a49f4d| gnu st3 {v22.d-v24.d}[1], [x7],#24
+8fa69a4d| gnu st3 {v15.d-v17.d}[1], [x20], x26
+ee09000c| gnu st4 {v14.2s-v17.2s}, [x15]
+1e07880c| gnu st4 {v30.4h, v31.4h, v0.4h, v1.4h}, [x24], x8
+6426204d| gnu st4 {v4.b-v7.b}[9], [x19]
+4ea2204d| gnu st4 {v14.s-v17.s}[2], [x18]
+05a6200d| gnu st4 {v5.d-v8.d}[0], [x16]
+5b21bf0d| gnu st4 {v27.b-v30.b}[0], [x10],#4
+ce28a00d| gnu st4 {v14.b-v17.b}[2], [x6], x0
+767bbf4d| gnu st4 {v22.h-v25.h}[7], [x27],#8
+747aa24d| gnu st4 {v20.h-v23.h}[7], [x19], x2
+24b0bf0d| gnu st4 {v4.s-v7.s}[1], [x1],#16
+c7b1a90d| gnu st4 {v7.s-v10.s}[1], [x14], x9
+9fa4bf4d| gnu st4 {v31.d, v0.d, v1.d, v2.d}[1], [x4],#32
+70a4ab4d| gnu st4 {v16.d-v19.d}[1], [x3], x11
+89fe2e2c| gnu stnp s9, s31, [x20,#-140]
+bfd31d6c| gnu stnp d31, d20, [x29,#472]
+ddf301ac| gnu stnp q29, q28, [x30,#48]
+14f6ac2c| gnu stp s20, s29, [x16],#-156
+251db76c| gnu stp d5, d7, [x9],#-144
+e51fb7ac| gnu stp q5, q7, [sp],#-288
+5c90852d| gnu stp s28, s4, [x2,#44]!
+4c51a56d| gnu stp d12, d20, [x10,#-432]!
+265d8aad| gnu stp q6, q23, [x9,#320]!
+9c0c392d| gnu stp s28, s3, [x4,#-56]
+b49e1e6d| gnu stp d20, d7, [x21,#488]
+55f105ad| gnu stp q21, q28, [x10,#176]
+4dd6003c| gnu str b13, [x18],#13
+e357067c| gnu str h3, [sp],#101
+f6841dbc| gnu str s22, [x7],#-40
+54b710fc| gnu str d20, [x26],#-245
+0d07833c| gnu str q13, [x24],#48
+393f003c| gnu str b25, [x25,#3]!
+1fac007c| gnu str h31, [x0,#10]!
+d41d13bc| gnu str s20, [x14,#-207]!
+908f0dfc| gnu str d16, [x28,#216]!
+5ded9d3c| gnu str q29, [x10,#-34]!
+6d72073d| gnu str b13, [x19,#476]
+68752d7d| gnu str h8, [x11,#5818]
+084728bd| gnu str s8, [x24,#10308]
+409503fd| gnu str d0, [x10,#1832]
+58a1963d| gnu str q24, [x10,#23168]
+51c8253c| gnu str b17, [x2,w5,sxtw]
+967b313c| gnu str b22, [x28,x17,lsl #0]
+b4683e7c| gnu str h20, [x5,x30]
+64d9a33c| gnu str q4, [x11,w3,sxtw #4]
+e5e1143c| gnu stur b5, [x15,#-178]
+99901e7c| gnu stur h25, [x4,#-23]
+bb0012bc| gnu stur s27, [x5,#-224]
+1d710cfc| gnu stur d29, [x8,#199]
+17e1873c| gnu stur q23, [x8,#126]
+ed84a26e| gnu sub v13.4s, v7.4s, v2.4s
+7761b80e| gnu subhn v23.2s, v11.2d, v24.2d
+f838205e| gnu suqadd b24, b7
+7739600e| gnu suqadd v23.4h, v11.4h
+26a5204f| gnu sxtl2 v6.2d, v9.4s
+5a201a4e| gnu tbl v26.16b, {v2.16b, v3.16b}, v26.16b
+c2400f0e| gnu tbl v2.8b, {v6.16b-v8.16b}, v15.8b
+7263024e| gnu tbl v18.16b, {v27.16b-v30.16b}, v2.16b
+bb010b4e| gnu tbl v27.16b, {v13.16b}, v11.16b
+5f31184e| gnu tbx v31.16b, {v10.16b, v11.16b}, v24.16b
+a952100e| gnu tbx v9.8b, {v21.16b-v23.16b}, v16.8b
+4872170e| gnu tbx v8.8b, {v18.16b-v21.16b}, v23.8b
+dc110e4e| gnu tbx v28.16b, {v14.16b}, v14.16b
+d7289a4e| gnu trn1 v23.4s, v6.4s, v26.4s
+cd6a924e| gnu trn2 v13.4s, v22.4s, v18.4s
+a552392e| gnu uabal v5.8h, v21.8b, v25.8b
+a653256e| gnu uabal2 v6.8h, v29.16b, v5.16b
+fb70b42e| gnu uabdl v27.2d, v7.2s, v20.2s
+3b6a202e| gnu uadalp v27.4h, v17.8b
+8a03b22e| gnu uaddl v10.2d, v28.2s, v18.2s
+262a206e| gnu uaddlp v6.8h, v17.16b
+8410312e| gnu uaddw v4.8h, v4.8h, v17.8b
+bf11ae6e| gnu uaddw2 v31.2d, v13.2d, v14.4s
+a7e65d7f| gnu ucvtf d7, d21, #35
+8bda617e| gnu ucvtf d11, d20
+7fb8431e| gnu ucvtf d31, w3, #18
+1c0f039e| gnu ucvtf s28, x24, #61
+2241439e| gnu ucvtf d2, x9, #48
+d701231e| gnu ucvtf s23, w14
+9600631e| gnu ucvtf d22, w4
+8b01239e| gnu ucvtf s11, x12
+7202639e| gnu ucvtf d18, x19
+3406b82e| gnu uhadd v20.2s, v17.2s, v24.2s
+9264612e| gnu umax v18.4h, v4.4h, v1.4h
+d9a5772e| gnu umaxp v25.4h, v14.4h, v23.4h
+74a8b06e| gnu umaxv s20, v3.4s
+24a8312e| gnu uminv b4, v1.8b
+c5218e2f| gnu umlal v5.2d, v14.2s, v14.s[0]
+3d20a76f| gnu umlal2 v29.2d, v1.4s, v7.s[1]
+90817e6e| gnu umlal2 v16.4s, v12.8h, v30.8h
+0f69a46f| gnu umlsl2 v15.2d, v8.4s, v4.s[3]
+4aa27c2e| gnu umlsl v10.4s, v18.4h, v28.4h
+48a27b6e| gnu umlsl2 v8.4s, v18.8h, v27.8h
+833c0d0e| gnu umov w3, v4.b[6]
+e2a1b22f| gnu umull v2.2d, v15.2s, v18.s[1]
+07c06f2e| gnu umull v7.4s, v0.4h, v15.4h
+470e367e| gnu uqadd b7, b18, b22
+490e252e| gnu uqadd v9.8b, v18.8b, v5.8b
+bf5eaa7e| gnu uqrshl s31, s21, s10
+c49c347f| gnu uqrshrn s4, d6, #12
+b4757a7f| gnu uqshl d20, d13, #58
+d14f777e| gnu uqshl h17, h30, h23
+9e2d7a7e| gnu uqsub h30, h12, h26
+a62c296e| gnu uqsub v6.16b, v5.16b, v9.16b
+5d4ba17e| gnu uqxtn s29, d26
+454b212e| gnu uqxtn v5.8b, v26.8h
+1c48a16e| gnu uqxtn2 v28.4s, v0.2d
+4157736e| gnu urshl v1.8h, v26.8h, v19.8h
+2d26797f| gnu urshr d13, d17, #7
+bd27466f| gnu urshr v29.2d, v29.2d, #58
+bcc8a12e| gnu ursqrte v28.2s, v5.2s
+f5345d7f| gnu ursra d21, d7, #35
+f8353a6f| gnu ursra v24.4s, v15.4s, #6
+85a6342f| gnu ushll v5.2d, v20.2s, #20
+e7a70e6f| gnu ushll2 v7.8h, v31.16b, #6
+ed04787f| gnu ushr d13, d7, #8
+8f07362f| gnu ushr v15.2s, v28.2s, #10
+963a607e| gnu usqadd h22, h20
+383a206e| gnu usqadd v24.16b, v17.16b
+ef16596f| gnu usra v15.2d, v23.2d, #39
+f222ab2e| gnu usubl v18.2d, v23.2s, v11.2s
+9220696e| gnu usubl2 v18.4s, v4.8h, v9.8h
+0130312e| gnu usubw v1.8h, v0.8h, v17.8b
+a932a06e| gnu usubw2 v9.2d, v21.2d, v0.4s
+9a19910e| gnu uzp1 v26.2s, v12.2s, v17.2s
+a379ca4e| gnu zip2 v3.2d, v13.2d, v10.2d
+1202011a| gnu adc w18, w16, w1
+6900199a| gnu adc x9, x3, x25
+01010f3a| gnu adcs w1, w8, w15
+13010fba| gnu adcs x19, x8, x15
+55ed280b| gnu add w21, w10, w8, sxtx #3
+2077268b| gnu add x0, x25, x6, uxtx #5
+7f40560b| gnu add wzr, w3, w22, lsr #16
+3a16282b| gnu adds w26, w17, w8, uxtb #5
+f8a336ab| gnu adds x24, sp, w22, sxth
+000e6d31| gnu adds w0, w16, #0xb43, lsl #12
+b48e49b1| gnu adds x20, x21, #0x263, lsl #12
+7e174e2b| gnu adds w30, w27, w14, lsr #5
+25e2f250| gnu adr x5, .+0xfffffffffffe5c46
+294079f0| gnu adrp x9, .+0xf2807000
+3aa13f12| gnu and w26, w9, #0x3fe03fe
+32a23592| gnu and x18, x17, #0xf80ff80ff80ff80f
+b478070a| gnu and w20, w5, w7, lsl #30
+dd1f988a| gnu and x29, x30, x24, asr #7
+a7351b72| gnu ands w7, w13, #0x7ffe0
+1c056ef2| gnu ands x28, x8, #0xc0000
+defd52ea| gnu ands x30, x14, x18, lsr #63
+8c28d01a| gnu asr w12, w4, w16
+582ac09a| gnu asr x24, x18, x0
+647d1813| gnu asr w4, w11, #24
+d1fe5b93| gnu asr x17, x22, #27
+2329c31a| gnu asr w3, w9, w3
+d929d69a| gnu asr x25, x14, x22
+aefa5354| gnu b.al .+0xa7f54
+76ad3917| gnu b .+0xfffffffffce6b5d8
+de320f33| gnu bfi w30, w22, #17, #13
+af144db3| gnu bfi x15, x5, #51, #6
+161c7eb3| gnu bfi x22, x0, #2, #8
+f9791733| gnu bfxil w25, w15, #23, #8
+781577b3| gnu bfi x24, x11, #9, #6
+0f65f98a| gnu bic x15, x8, x25, ror #25
+2c37e16a| gnu bics w12, w25, w1, ror #13
+a6f473ea| gnu bics x6, x5, x19, lsr #61
+f064ad96| gnu bl .+0xfffffffffab593c0
+80023fd6| gnu blr x20
+00001fd6| gnu br x0
+80de3ed4| gnu brk #0xf6f4
+08276a35| gnu cbnz w8, .+0xd44e0
+acd1c0b5| gnu cbnz x12, .+0xfffffffffff81a34
+ef50bf34| gnu cbz w15, .+0xfffffffffff7ea1c
+4bd681b4| gnu cbz x11, .+0xfffffffffff03ac8
+4e2a483a| gnu ccmn w18, #0x8, #0xe, cs
+4a3a4eba| gnu ccmn x18, #0xe, #0xa, cc
+0143553a| gnu ccmn w24, w21, #0x1, mi
+c09359ba| gnu ccmn x30, x25, #0x0, ls
+020a567a| gnu ccmp w16, #0x16, #0x2, eq
+a6985afa| gnu ccmp x5, #0x1a, #0x6, ls
+6fc0487a| gnu ccmp w3, w8, #0xf, gt
+21d14bfa| gnu ccmp x9, x11, #0x1, le
+75f5991a| gnu csinc w21, w11, w25, al
+5a25919a| gnu csinc x26, x10, x17, cs
+6a938c5a| gnu csinv w10, w27, w12, ls
+6a408eda| gnu csinv x10, x3, x14, mi
+5f3603d5| gnu clrex #0x6
+a017c05a| gnu cls w0, w29
+2616c0da| gnu cls x6, x17
+9411c05a| gnu clz w20, w12
+c611c0da| gnu clz x6, x14
+9fc3322b| gnu cmn w28, w18, sxtw
+3f9638ab| gnu cmn x17, w24, sxtb #5
+3f681db1| gnu cmn x1, #0x75a
+bfd15bab| gnu cmn x13, x27, lsr #52
+ff723b6b| gnu cmp w23, w27, uxtx #4
+1f5234eb| gnu cmp x16, w20, uxtw #4
+9fb22a71| gnu cmp w20, #0xaac
+df2478f1| gnu cmp x6, #0xe09, lsl #12
+bf07026b| gnu cmp w29, w2, lsl #1
+bfc514eb| gnu cmp x13, x20, lsl #49
+d494975a| gnu csneg w20, w6, w23, ls
+763591da| gnu csneg x22, x11, x17, cc
+b440c91a| gnu crc32b w20, w5, w9
+5745cd1a| gnu crc32h w23, w10, w13
+684ad01a| gnu crc32w w8, w19, w16
+884fd59a| gnu crc32x w8, w28, x21
+ea50c61a| gnu crc32cb w10, w7, w6
+1357cf1a| gnu crc32ch w19, w24, w15
+9859c21a| gnu crc32cw w24, w12, w2
+6e5fde9a| gnu crc32cx w14, w27, x30
+9340941a| gnu csel w19, w4, w20, mi
+dd42839a| gnu csel x29, x22, x3, mi
+fe779f1a| gnu cset w30, vs
+f1279f9a| gnu cset x17, cc
+eb839f5a| gnu csetm w11, ls
+e3139fda| gnu csetm x3, eq
+a986841a| gnu csinc w9, w21, w4, hi
+19b78b9a| gnu csinc x25, x24, x11, lt
+4643835a| gnu csinv w6, w26, w3, mi
+5ee38cda| gnu csinv x30, x26, x12, al
+d166945a| gnu csneg w17, w22, w20, vs
+55f793da| gnu csneg x21, x26, x19, al
+0158add4| gnu dcps1 #0x6ac0
+82ceb2d4| gnu dcps2 #0x9674
+a31eb3d4| gnu dcps3 #0x98f5
+bf3203d5| gnu dmb oshst
+e003bfd6| gnu drps
+9f3403d5| gnu dsb #0x04
+2e2faeca| gnu eon x14, x25, x14, asr #11
+de6b0152| gnu eor w30, w30, #0x83ffffff
+4a7714d2| gnu eor x10, x26, #0xfffff3fffffff3ff
+2cea0dca| gnu eor x12, x17, x13, lsl #58
+e0039fd6| gnu eret
+834cce93| gnu extr x3, x4, x14, #19
+5f2003d5| gnu wfe
+bf2e03d5| gnu hint #0x75
+e0f055d4| gnu hlt #0xaf87
+df3403d5| gnu isb #0x4
+22fcdf88| gnu ldar w2, [x1]
+78fedfc8| gnu ldar x24, [x19]
+cffcdf08| gnu ldarb w15, [x6]
+34fedf48| gnu ldarh w20, [x17]
+17bb7f88| gnu ldaxp w23, w14, [x24]
+6ffe7fc8| gnu ldaxp x15, xzr, [x19]
+acfe5f88| gnu ldaxr w12, [x21]
+cafe5fc8| gnu ldaxr x10, [x22]
+ddfd5f08| gnu ldaxrb w29, [x14]
+0efd5f48| gnu ldaxrh w14, [x8]
+66445128| gnu ldnp w6, w17, [x3,#136]
+3fa77fa8| gnu ldnp xzr, x9, [x25,#-8]
+1e04eb28| gnu ldp w30, w1, [x0],#-168
+0da6c0a8| gnu ldp x13, x9, [x16],#8
+7d00d429| gnu ldp w29, w0, [x3,#160]!
+d26ae1a9| gnu ldp x18, x26, [x22,#-496]!
+d0ca6829| gnu ldp w16, w18, [x22,#-188]
+a5e34fa9| gnu ldp x5, x24, [x29,#248]
+3e44d168| gnu ldpsw x30, x17, [x1],#136
+5f08e169| gnu ldpsw xzr, x2, [x2,#-248]!
+430d6769| gnu ldpsw x3, x3, [x10,#-200]
+2c555bb8| gnu ldr w12, [x9],#-75
+83c557f8| gnu ldr x3, [x12],#-132
+f36e47b8| gnu ldr w19, [x23,#118]!
+6b1f48f8| gnu ldr x11, [x27,#129]!
+f5d64ab9| gnu ldr w21, [x23,#2772]
+872d7cf9| gnu ldr x7, [x12,#30808]
+f23e8c18| gnu ldr w18, .+0xfffffffffff187dc
+a7e72a58| gnu ldr x7, .+0x55cf4
+82a75438| gnu ldrb w2, [x28],#-182
+a7fd5738| gnu ldrb w7, [x13,#-129]!
+c83d4239| gnu ldrb w8, [x14,#143]
+58c96438| gnu ldrb w24, [x10,w4,sxtw]
+8e687e38| gnu ldrb w14, [x4,x30]
+70575378| gnu ldrh w16, [x27],#-203
+015f5078| gnu ldrh w1, [x24,#-251]!
+7add5c79| gnu ldrh w26, [x11,#3694]
+2fcb7778| gnu ldrh w15, [x25,w23,sxtw]
+c474c338| gnu ldrsb w4, [x6],#55
+28869638| gnu ldrsb x8, [x17],#-152
+fe3fd438| gnu ldrsb w30, [sp,#-189]!
+da0f9938| gnu ldrsb x26, [x30,#-112]!
+5b3ac739| gnu ldrsb w27, [x18,#462]
+2c579e39| gnu ldrsb x12, [x25,#1941]
+54faf838| gnu ldrsb w20, [x18,x24,sxtx #0]
+fb68f238| gnu ldrsb w27, [x7,x18]
+f26aad38| gnu ldrsb x18, [x23,x13]
+17e4c978| gnu ldrsh w23, [x0],#158
+a2759f78| gnu ldrsh x2, [x13],#-9
+9c6ec478| gnu ldrsh w28, [x20,#70]!
+fd6f8278| gnu ldrsh x29, [sp,#38]!
+a82bc279| gnu ldrsh w8, [x29,#276]
+9d89b979| gnu ldrsh x29, [x12,#7364]
+962685b8| gnu ldrsw x22, [x20],#82
+76ae8bb8| gnu ldrsw x22, [x19,#186]!
+fc2193b9| gnu ldrsw x28, [x15,#4896]
+7561fa98| gnu ldrsw x21, .+0xffffffffffff4c2c
+e34842b8| gnu ldtr w3, [x7,#36]
+4ff84df8| gnu ldtr x15, [x2,#223]
+d9e84f38| gnu ldtrb w25, [x6,#254]
+397b5378| gnu ldtrh w25, [x25,#-201]
+c4c9d138| gnu ldtrsb w4, [x14,#-228]
+02789638| gnu ldtrsb x2, [x0,#-153]
+a988cb78| gnu ldtrsh w9, [x5,#184]
+03888978| gnu ldtrsh x3, [x0,#152]
+ccb99fb8| gnu ldtrsw x12, [x14,#-5]
+efb154b8| gnu ldur w15, [x15,#-181]
+fc2051f8| gnu ldur x28, [x7,#-238]
+86d04438| gnu ldurb w6, [x4,#77]
+73405d78| gnu ldurh w19, [x3,#-44]
+7a81d538| gnu ldursb w26, [x11,#-168]
+b0b28038| gnu ldursb x16, [x21,#11]
+b4a1d278| gnu ldursh w20, [x13,#-214]
+3ed18078| gnu ldursh x30, [x9,#13]
+09628eb8| gnu ldursw x9, [x16,#230]
+c07e7f88| gnu ldxp w0, wzr, [x22]
+3e167fc8| gnu ldxp x30, x5, [x17]
+727c5f88| gnu ldxr w18, [x3]
+487c5fc8| gnu ldxr x8, [x2]
+867d5f08| gnu ldxrb w6, [x12]
+747f5f48| gnu ldxrh w20, [x27]
+d920d71a| gnu lsl w25, w6, w23
+b920c59a| gnu lsl x25, x5, x5
+4da947d3| gnu ubfx x13, x10, #7, #36
+be23ca1a| gnu lsl w30, w29, w10
+cc20d19a| gnu lsl x12, x6, x17
+ae26c31a| gnu lsr w14, w21, w3
+fc27cb9a| gnu lsr x28, xzr, x11
+2b7e1053| gnu lsr w11, w17, #16
+cefe75d3| gnu lsr x14, x22, #53
+3b25d01a| gnu lsr w27, w9, w16
+e826d79a| gnu lsr x8, x23, x23
+5504031b| gnu madd w21, w2, w3, w1
+9e5c109b| gnu madd x30, x4, x16, x23
+00fe1f1b| gnu mneg w0, w16, wzr
+6efe179b| gnu mneg x14, x19, x23
+31020011| gnu add w17, w17, #0x0
+21000091| gnu add x1, x1, #0x0
+39f1bf12| gnu mov w25, #0x76ffff
+53b3e992| gnu mov x19, #0xb265ffffffffffff
+c0fd9552| gnu mov w0, #0xafee
+f16b97d2| gnu mov x17, #0xbb5f
+e8972232| gnu mov w8, #0xc00fc00f
+e27323b2| gnu mov x2, #0xe3ffffffe3ffffff
+e9030e2a| gnu mov w9, w14
+fb0310aa| gnu mov x27, x16
+d0e48472| gnu movk w16, #0x2726
+432dbcf2| gnu movk x3, #0xe16a, lsl #16
+4b679612| gnu mov w11, #0xffff4cc5
+9121e492| gnu mov x17, #0xdef3ffffffffffff
+00be90d2| gnu mov x0, #0x85f0
+91d730d5| gnu mrs x17, s2_0_c13_c7_4
+cf301fd5| gnu msr s3_7_c3_c0_6, x15
+daea181b| gnu msub w26, w22, w24, w26
+e1a7109b| gnu msub x1, xzr, x16, x9
+477f0d1b| gnu mul w7, w26, w13
+a17d1c9b| gnu mul x1, x13, x28
+fc9b79aa| gnu mvn x28, x25, lsr #38
+f71b904b| gnu neg w23, w16, asr #6
+e3df4acb| gnu neg x3, x10, lsr #55
+f0334e6b| gnu negs w16, w14, lsr #12
+e6031f5a| gnu ngc w6, wzr
+f40302da| gnu ngc x20, x2
+ee03137a| gnu ngcs w14, w19
+ee0303fa| gnu ngcs x14, x3
+1f2003d5| gnu nop
+ab14e92a| gnu orn w11, w5, w9, ror #5
+185c3faa| gnu orn x24, x0, xzr, lsl #23
+a8850c32| gnu orr w8, w13, #0x300030
+cad023b2| gnu orr x10, x6, #0xe3e3e3e3e3e3e3e3
+5487ccaa| gnu orr x20, x26, x12, ror #33
+293783f9| gnu prfm plil1strm, [x25,#1640]
+501010d8| gnu prfm pstl1keep, .+0x20208
+bc7389f8| gnu prfum #0x1c, [x29,#151]
+9203c05a| gnu rbit w18, w28
+0501c0da| gnu rbit x5, x8
+40005fd6| gnu ret x2
+940ac05a| gnu rev w20, w20
+ca0fc0da| gnu rev x10, x30
+7807c05a| gnu rev16 w24, w27
+fb06c0da| gnu rev16 x27, x23
+dc0ac0da| gnu rev32 x28, x22
+970dc0da| gnu rev x23, x12
+42408813| gnu extr w2, w2, w8, #16
+5a96db93| gnu extr x26, x18, x27, #37
+782cc41a| gnu ror w24, w3, w4
+8c2ec69a| gnu ror x12, x20, x6
+372ec61a| gnu ror w23, w17, w6
+b72ddc9a| gnu ror x23, x13, x28
+e501185a| gnu sbc w5, w15, w24
+ac0011da| gnu sbc x12, x5, x17
+7a03067a| gnu sbcs w26, w27, w6
+310008fa| gnu sbcs x17, x1, x8
+65837f93| gnu sbfiz x5, x27, #1, #33
+5c1b4793| gnu sbfiz x28, x26, #57, #7
+a71f5b93| gnu sbfiz x7, x29, #37, #8
+640ede1a| gnu sdiv w4, w19, w30
+2a0dd99a| gnu sdiv x10, x9, x25
+9f2003d5| gnu sev
+bf2003d5| gnu sevl
+045c389b| gnu smaddl x4, w0, w24, x23
+6efe3e9b| gnu smnegl x14, w19, w30
+ebac239b| gnu smsubl x11, w7, w3, x11
+947f459b| gnu smulh x20, x28, x5
+d67e3e9b| gnu smull x22, w22, w30
+6dff9f88| gnu stlr w13, [x27]
+1ffd9fc8| gnu stlr xzr, [x8]
+a8fe9f08| gnu stlrb w8, [x21]
+abfd9f48| gnu stlrh w11, [x13]
+2ec02888| gnu stlxp w8, w14, w16, [x1]
+11993ec8| gnu stlxp w30, x17, x6, [x8]
+bbfe0f88| gnu stlxr w15, w27, [x21]
+e9fc09c8| gnu stlxr w9, x9, [x7]
+c6fe0708| gnu stlxrb w7, w6, [x22]
+c6fe0c48| gnu stlxrh w12, w6, [x22]
+b3283028| gnu stnp w19, w10, [x5,#-128]
+252e26a8| gnu stnp x5, x11, [x17,#-416]
+9fb18c28| gnu stp wzr, w12, [x12],#100
+9ce5aba8| gnu stp x28, x25, [x12],#-328
+e5d08229| gnu stp w5, w20, [x7,#20]!
+d6e79ea9| gnu stp x22, x25, [x30,#488]!
+9eef2029| gnu stp w30, w27, [x28,#-252]
+57b314a9| gnu stp x23, x12, [x26,#328]
+eda503b8| gnu str w13, [x15],#58
+62241df8| gnu str x2, [x3],#-46
+d2bd18b8| gnu str w18, [x14,#-117]!
+542d12f8| gnu str x20, [x10,#-222]!
+e92c3bb9| gnu str w9, [x7,#15148]
+de4804f9| gnu str x30, [x6,#2192]
+cce40b38| gnu strb w12, [x6],#190
+eafd1238| gnu strb w10, [x15,#-209]!
+7fcb0639| gnu strb wzr, [x27,#434]
+03f82738| gnu strb w3, [x0,x7,sxtx #0]
+5c6a3e38| gnu strb w28, [x18,x30]
+a8551978| gnu strh w8, [x13],#-107
+9e6c0c78| gnu strh w30, [x4,#198]!
+c83d0e79| gnu strh w8, [x14,#1822]
+502a1db8| gnu sttr w16, [x18,#-46]
+ae180af8| gnu sttr x14, [x5,#161]
+ea1a0138| gnu sttrb w10, [x23,#17]
+416b0278| gnu sttrh w1, [x26,#38]
+659107b8| gnu stur w5, [x11,#121]
+6b611ff8| gnu stur x11, [x11,#-10]
+99a01c38| gnu sturb w25, [x4,#-54]
+99421e78| gnu sturh w25, [x20,#-28]
+3e2a2688| gnu stxp w6, w30, w10, [x17]
+2f6a2cc8| gnu stxp w12, x15, x26, [x17]
+7d7f1b88| gnu stxr w27, w29, [x27]
+6e7e1bc8| gnu stxr w27, x14, [x19]
+ec7c0208| gnu stxrb w2, w12, [x7]
+ee7f0648| gnu stxrh w6, w14, [sp]
+2f8d204b| gnu sub w15, w9, w0, sxtb #3
+1fbe3acb| gnu sub sp, x16, w26, sxth #7
+5af778d1| gnu sub x26, x26, #0xe3d, lsl #12
+6729034b| gnu sub w7, w11, w3, lsl #10
+ae683f6b| gnu subs w14, w5, wzr, uxtx #2
+2f993deb| gnu subs x15, x9, w29, sxtb #6
+db0d5f71| gnu subs w27, w14, #0x7c3, lsl #12
+3aec1ff1| gnu subs x26, x1, #0x7fb
+1f24016b| gnu cmp w0, w1, lsl #9
+a1ae1bd4| gnu svc #0xdd75
+a61e0013| gnu sxtb w6, w21
+441c4093| gnu sxtb x4, w2
+0c3c0013| gnu sxth w12, w0
+b33f4093| gnu sxth x19, w29
+407f4093| gnu sxtw x0, w26
+455929d5| gnu sysl x5, #1, C5, C9, #2
+d1005b37| gnu tbnz w17, #11, .+0x6018
+798eaeb6| gnu tbz x25, #53, .+0xffffffffffffd1cc
+bf8c1f72| gnu tst w5, #0x1e001e
+ff10836a| gnu tst w7, w3, asr #4
+dfc5daea| gnu tst x14, x26, ror #49
+aa6e43d3| gnu ubfx x10, x21, #3, #25
+46181a53| gnu ubfiz w6, w2, #6, #7
+43294bd3| gnu lsl x3, x10, #53
+77787dd3| gnu ubfiz x23, x3, #3, #31
+1a0bd61a| gnu udiv w26, w24, w22
+9308c19a| gnu udiv x19, x4, x1
+755aa19b| gnu umaddl x21, w19, w1, x22
+1ffdbe9b| gnu umnegl xzr, w8, w30
+cbaaba9b| gnu umsubl x11, w22, w26, x10
+0c7fdb9b| gnu umulh x12, x24, x27
+cc7da79b| gnu umull x12, w14, w7
+3d1c0053| gnu uxtb w29, w1
+0e3f0053| gnu uxth w14, w24
+5f2003d5| gnu wfe
+7f2003d5| gnu wfi
+3f2003d5| gnu yield
+71b9604e| gnu abs v17.8h, v11.8h
+5186f65e| gnu add d17, d18, d22
+4986f34e| gnu add v9.2d, v18.2d, v19.2d
+1243720e| gnu addhn v18.4h, v24.4s, v18.4s
+0640354e| gnu addhn2 v6.16b, v0.8h, v21.8h
+d9bdfa4e| gnu addp v25.2d, v14.2d, v26.2d
+4c59284e| gnu aesd v12.16b, v10.16b
+8c48284e| gnu aese v12.16b, v4.16b
+f47a284e| gnu aesimc v20.16b, v23.16b
+c56b284e| gnu aesmc v5.16b, v30.16b
+bf1c3b0e| gnu and v31.8b, v5.8b, v27.8b
+6444026f| gnu mvni v4.4s, #0x43, lsl #16
+1357032f| gnu bic v19.2s, #0x78, lsl #16
+561d6a0e| gnu bic v22.8b, v10.8b, v10.8b
+cd1ff06e| gnu bif v13.16b, v30.16b, v16.16b
+f31ebd6e| gnu bit v19.16b, v23.16b, v29.16b
+6f1d6c2e| gnu bsl v15.8b, v11.8b, v12.8b
+1e48600e| gnu cls v30.4h, v0.4h
+6948202e| gnu clz v9.8b, v3.8b
+968efd7e| gnu cmeq d22, d20, d29
+e58f6d6e| gnu cmeq v5.8h, v31.8h, v13.8h
+8f98600e| gnu cmeq v15.4h, v4.4h, #0
+4f3db84e| gnu cmge v15.4s, v10.4s, v24.4s
+2788a02e| gnu cmge v7.2s, v1.2s, #0
+bf35714e| gnu cmgt v31.8h, v13.8h, v17.8h
+4a89604e| gnu cmgt v10.8h, v10.8h, #0
+9635252e| gnu cmhi v22.8b, v12.8b, v5.8b
+d83eff6e| gnu cmhs v24.2d, v22.2d, v31.2d
+cb99206e| gnu cmle v11.16b, v14.16b, #0
+29a9604e| gnu cmlt v9.8h, v9.8h, #0
+d18eea5e| gnu cmtst d17, d22, d10
+d18ea94e| gnu cmtst v17.4s, v22.4s, v9.4s
+4a04075e| gnu mov b10, v2.b[3]
+0504040e| gnu dup v5.2s, v0.s[0]
+b20e1f4e| gnu dup v18.16b, w21
+2a1f3e6e| gnu eor v10.16b, v25.16b, v30.16b
+0bd5aa7e| gnu fabd s11, s8, s10
+12d7b96e| gnu fabd v18.4s, v24.4s, v25.4s
+a1f9a04e| gnu fabs v1.4s, v13.4s
+1ac3201e| gnu fabs s26, s24
+d8c3601e| gnu fabs d24, d30
+95ee267e| gnu facge s21, s20, s6
+2bee262e| gnu facge v11.2s, v17.2s, v6.2s
+1aedec7e| gnu facgt d26, d8, d12
+74effa6e| gnu facgt v20.2d, v27.2d, v26.2d
+7ed4260e| gnu fadd v30.2s, v3.2s, v6.2s
+4528251e| gnu fadd s5, s2, s5
+262b661e| gnu fadd d6, d25, d6
+84d8707e| gnu faddp d4, v4.2d
+71d4276e| gnu faddp v17.4s, v3.4s, v7.4s
+a5f43f1e| gnu fccmp s5, s31, #0x5, al
+20e5601e| gnu fccmp d9, d0, #0x0, al
+52d4331e| gnu fccmpe s2, s19, #0x2, le
+1e66761e| gnu fccmpe d16, d22, #0xe, vs
+d7e6695e| gnu fcmeq d23, d22, d9
+e7d9a05e| gnu fcmeq s7, s15, #0
+dadaa04e| gnu fcmeq v26.4s, v22.4s, #0
+28e5737e| gnu fcmge d8, d9, d19
+a2e73a6e| gnu fcmge v2.4s, v29.4s, v26.4s
+4fcba07e| gnu fcmge s15, s26, #0
+43c8a02e| gnu fcmge v3.2s, v2.2s, #0
+ffe5a67e| gnu fcmgt s31, s15, s6
+7ee7bd2e| gnu fcmgt v30.2s, v27.2s, v29.2s
+5bc8e05e| gnu fcmgt d27, d2, #0
+3dc9a04e| gnu fcmgt v29.4s, v9.4s, #0
+38daa07e| gnu fcmle s24, s17, #0
+8fdaa02e| gnu fcmle v15.2s, v20.2s, #0
+93e8e05e| gnu fcmlt d19, d4, #0
+9fe9a04e| gnu fcmlt v31.4s, v12.4s, #0
+a023201e| gnu fcmp s29, s0
+c822231e| gnu fcmp s22, #0
+a022651e| gnu fcmp d21, d5
+a8227d1e| gnu fcmp d21, #0
+70203e1e| gnu fcmpe s3, s30
+38232b1e| gnu fcmpe s25, #0
+70206c1e| gnu fcmpe d3, d12
+b823731e| gnu fcmpe d29, #0
+3e6f331e| gnu fcsel s30, s25, s19, vs
+a64f6d1e| gnu fcsel d6, d29, d13, mi
+0d41e21e| gnu fcvt s13, h8
+cbc0e21e| gnu fcvt d11, h6
+18c0231e| gnu fcvt h24, s0
+a7c0221e| gnu fcvt d7, s5
+e7c3631e| gnu fcvt h7, d31
+9f43621e| gnu fcvt s31, d28
+a0c8215e| gnu fcvtas s0, s5
+4dc8210e| gnu fcvtas v13.2s, v2.2s
+0300241e| gnu fcvtas w3, s0
+fd03249e| gnu fcvtas x29, s31
+ef01641e| gnu fcvtas w15, d15
+4c01649e| gnu fcvtas x12, d10
+9ac8617e| gnu fcvtau d26, d4
+b802251e| gnu fcvtau w24, s21
+2a03259e| gnu fcvtau x10, s25
+ea00651e| gnu fcvtau w10, d7
+0102659e| gnu fcvtau x1, d16
+0d7a610e| gnu fcvtl v13.2d, v16.2s
+ed79214e| gnu fcvtl2 v13.4s, v15.8h
+43bb615e| gnu fcvtms d3, d26
+c000301e| gnu fcvtms w0, s6
+9202309e| gnu fcvtms x18, s20
+0800701e| gnu fcvtms w8, d0
+6603709e| gnu fcvtms x6, d27
+f0b9217e| gnu fcvtmu s16, s15
+3bba212e| gnu fcvtmu v27.2s, v17.2s
+5900311e| gnu fcvtmu w25, s2
+9a03319e| gnu fcvtmu x26, s28
+fa01711e| gnu fcvtmu w26, d15
+6f01719e| gnu fcvtmu x15, d11
+1968210e| gnu fcvtn v25.4h, v0.4s
+3d69214e| gnu fcvtn2 v29.8h, v9.4s
+87aa615e| gnu fcvtns d7, d20
+e301201e| gnu fcvtns w3, s15
+6002209e| gnu fcvtns x0, s19
+1600601e| gnu fcvtns w22, d0
+8503609e| gnu fcvtns x5, d28
+f5ab617e| gnu fcvtnu d21, d31
+2b02211e| gnu fcvtnu w11, s17
+f902219e| gnu fcvtnu x25, s23
+0702611e| gnu fcvtnu w7, d16
+9d03619e| gnu fcvtnu x29, d28
+dcaba15e| gnu fcvtps s28, s30
+b4a8a10e| gnu fcvtps v20.2s, v5.2s
+5302281e| gnu fcvtps w19, s18
+e003289e| gnu fcvtps x0, s31
+9501681e| gnu fcvtps w21, d12
+6703689e| gnu fcvtps x7, d27
+68a8a17e| gnu fcvtpu s8, s3
+dcaba12e| gnu fcvtpu v28.2s, v30.2s
+9d03291e| gnu fcvtpu w29, s28
+5f01299e| gnu fcvtpu xzr, s10
+e101691e| gnu fcvtpu w1, d15
+3f00699e| gnu fcvtpu xzr, d1
+ee6b612e| gnu fcvtxn v14.2s, v31.2d
+b1fd215f| gnu fcvtzs s17, s13, #31
+bafd2c0f| gnu fcvtzs v26.2s, v13.2s, #20
+47b8e15e| gnu fcvtzs d7, d2
+dcbbe14e| gnu fcvtzs v28.2d, v30.2d
+56f8181e| gnu fcvtzs w22, s2, #2
+9265189e| gnu fcvtzs x18, s12, #39
+d3ad581e| gnu fcvtzs w19, d14, #21
+3d9b589e| gnu fcvtzs x29, d25, #26
+1a00381e| gnu fcvtzs w26, s0
+d302389e| gnu fcvtzs x19, s22
+5303781e| gnu fcvtzs w19, d26
+8f01789e| gnu fcvtzs x15, d12
+57fe537f| gnu fcvtzu d23, d18, #45
+beff796f| gnu fcvtzu v30.2d, v29.2d, #7
+08b9e17e| gnu fcvtzu d8, d8
+cdbbe16e| gnu fcvtzu v13.2d, v30.2d
+2126199e| gnu fcvtzu x1, s17, #55
+70a9591e| gnu fcvtzu w16, d11, #22
+8c25599e| gnu fcvtzu x12, d12, #55
+1201391e| gnu fcvtzu w18, s8
+0800399e| gnu fcvtzu x8, s0
+da00791e| gnu fcvtzu w26, d6
+2903799e| gnu fcvtzu x9, d25
+56fd3f2e| gnu fdiv v22.2s, v10.2s, v31.2s
+1f182e1e| gnu fdiv s31, s0, s14
+ce1b741e| gnu fdiv d14, d30, d20
+0d61021f| gnu fmadd s13, s8, s2, s24
+03205e1f| gnu fmadd d3, d0, d30, d8
+72f6654e| gnu fmax v18.2d, v19.2d, v5.2d
+1849281e| gnu fmax s24, s8, s8
+8e4a6e1e| gnu fmax d14, d20, d14
+54c7304e| gnu fmaxnm v20.4s, v26.4s, v16.4s
+91683a1e| gnu fmaxnm s17, s4, s26
+f56a721e| gnu fmaxnm d21, d23, d18
+c8cb307e| gnu fmaxnmp s8, v30.2s
+06c9306e| gnu fmaxnmv s6, v8.4s
+b6fb707e| gnu fmaxp d22, v29.2d
+1759341e| gnu fmin s23, s8, s20
+675b721e| gnu fmin d7, d27, d18
+69792d1e| gnu fminnm s9, s11, s13
+ab786b1e| gnu fminnm d11, d5, d11
+0fcab07e| gnu fminnmp s15, v16.2s
+d2c6b26e| gnu fminnmp v18.4s, v22.4s, v18.4s
+22fab07e| gnu fminp s2, v17.2s
+f5f5f56e| gnu fminp v21.2d, v15.2d, v21.2d
+bc13c95f| gnu fmla d28, d29, v9.d[0]
+5d51a85f| gnu fmls s29, s10, v8.s[1]
+d3ccb94e| gnu fmls v19.4s, v6.4s, v25.4s
+5bf4014f| gnu fmov v27.4s, #9.000000000000000000e+00
+5bf5026f| gnu fmov v27.2d, #2.031250000000000000e-01
+6541201e| gnu fmov s5, s11
+b742601e| gnu fmov d23, d21
+6002271e| gnu fmov s0, w19
+5301261e| gnu fmov w19, s10
+c103679e| gnu fmov d1, x30
+3301af9e| gnu fmov v19.d[1], x9
+bd00669e| gnu fmov x29, d5
+ee02ae9e| gnu fmov x14, v23.d[1]
+0ff0251e| gnu fmov s15, #1.550000000000000000e+01
+16506a1e| gnu fmov d22, #2.812500000000000000e-01
+d1c20e1f| gnu fmsub s17, s22, s14, s16
+fdae491f| gnu fmsub d29, d23, d9, d11
+a4989d4f| gnu fmul v4.4s, v5.4s, v29.s[2]
+efde706e| gnu fmul v15.2d, v23.2d, v16.2d
+190a291e| gnu fmul s25, s16, s9
+430a671e| gnu fmul d3, d18, d7
+21919e7f| gnu fmulx s1, s9, v30.s[0]
+5298c76f| gnu fmulx v18.2d, v2.2d, v7.d[1]
+1ddf3c5e| gnu fmulx s29, s24, s28
+a2fba06e| gnu fneg v2.4s, v29.4s
+7a40211e| gnu fneg s26, s3
+f843611e| gnu fneg d24, d31
+326b381f| gnu fnmadd s18, s25, s24, s26
+4b636a1f| gnu fnmadd d11, d26, d10, d24
+48fa201f| gnu fnmsub s8, s18, s0, s30
+04d87f1f| gnu fnmsub d4, d0, d31, d22
+0289371e| gnu fnmul s2, s8, s23
+0e8a691e| gnu fnmul d14, d16, d9
+05dba15e| gnu frecpe s5, s24
+42d9a14e| gnu frecpe v2.4s, v10.4s
+2eff655e| gnu frecps d14, d25, d5
+03fe774e| gnu frecps v3.2d, v16.2d, v23.2d
+b4fba15e| gnu frecpx s20, s29
+9d41261e| gnu frinta s29, s12
+ea42661e| gnu frinta d10, d23
+e399a16e| gnu frinti v3.4s, v15.4s
+6ec3271e| gnu frinti s14, s27
+ecc1671e| gnu frinti d12, d15
+4543251e| gnu frintm s5, s26
+f242651e| gnu frintm d18, d23
+898a214e| gnu frintn v9.4s, v20.4s
+1641241e| gnu frintn s22, s8
+5341641e| gnu frintn d19, d10
+248be14e| gnu frintp v4.2d, v25.2d
+35c2241e| gnu frintp s21, s17
+6fc3641e| gnu frintp d15, d27
+0940271e| gnu frintx s9, s0
+4643671e| gnu frintx d6, d26
+749aa14e| gnu frintz v20.4s, v19.4s
+8bc0251e| gnu frintz s11, s4
+7cc1651e| gnu frintz d28, d11
+dedbe17e| gnu frsqrte d30, d30
+04daa16e| gnu frsqrte v4.4s, v16.4s
+cdfce45e| gnu frsqrts d13, d6, d4
+d9fda04e| gnu frsqrts v25.4s, v14.4s, v0.4s
+c5c1211e| gnu fsqrt s5, s14
+67c1611e| gnu fsqrt d7, d11
+a4d6b14e| gnu fsub v4.4s, v21.4s, v17.4s
+6138351e| gnu fsub s1, s3, s21
+be3b6a1e| gnu fsub d30, d29, d10
+4d2f016e| gnu mov v13.b[0], v26.b[5]
+741e174e| gnu mov v20.b[11], w19
+e170404c| gnu ld1 {v1.16b}, [x7]
+7aa9404c| gnu ld1 {v26.4s, v27.4s}, [x11]
+4b6d400c| gnu ld1 {v11.1d-v13.1d}, [x10]
+582b400c| gnu ld1 {v24.2s-v27.2s}, [x26]
+8f7cdf4c| gnu ld1 {v15.2d}, [x4],#16
+0a76ce4c| gnu ld1 {v10.8h}, [x16], x14
+2aa6df0c| gnu ld1 {v10.4h, v11.4h}, [x17],#16
+35a7d70c| gnu ld1 {v21.4h, v22.4h}, [x25], x23
+ae6ddf4c| gnu ld1 {v14.2d-v16.2d}, [x13],#48
+b362d74c| gnu ld1 {v19.16b-v21.16b}, [x21], x23
+6d22df0c| gnu ld1 {v13.8b-v16.8b}, [x19],#32
+6722c90c| gnu ld1 {v7.8b-v10.8b}, [x19], x9
+c71f404d| gnu ld1 {v7.b}[15], [x30]
+f55a400d| gnu ld1 {v21.h}[3], [x23]
+f080400d| gnu ld1 {v16.s}[0], [x7]
+ed84404d| gnu ld1 {v13.d}[1], [x7]
+fd0bdf4d| gnu ld1 {v29.b}[10], [sp],#1
+c811dc0d| gnu ld1 {v8.b}[4], [x14], x28
+6548cb4d| gnu ld1 {v5.h}[5], [x3], x11
+9882df4d| gnu ld1 {v24.s}[2], [x20],#4
+f482c74d| gnu ld1 {v20.s}[2], [x23], x7
+0d87df0d| gnu ld1 {v13.d}[0], [x24],#8
+1b85db0d| gnu ld1 {v27.d}[0], [x8], x27
+58c3404d| gnu ld1r {v24.16b}, [x26]
+c0c6df4d| gnu ld1r {v0.8h}, [x22],#2
+a6cec90d| gnu ld1r {v6.1d}, [x21], x9
+e68a400c| gnu ld2 {v6.2s, v7.2s}, [x23]
+4007604d| gnu ld2 {v0.b, v1.b}[9], [x26]
+8c49604d| gnu ld2 {v12.h, v13.h}[5], [x12]
+4f92600d| gnu ld2 {v15.s, v16.s}[1], [x18]
+b186600d| gnu ld2 {v17.d, v18.d}[0], [x21]
+631aff0d| gnu ld2 {v3.b, v4.b}[6], [x19],#2
+330ceb4d| gnu ld2 {v19.b, v20.b}[11], [x1], x11
+454bff4d| gnu ld2 {v5.h, v6.h}[5], [x26],#4
+0792ff0d| gnu ld2 {v7.s, v8.s}[1], [x16],#8
+3b91fd0d| gnu ld2 {v27.s, v28.s}[1], [x9], x29
+b086ff4d| gnu ld2 {v16.d, v17.d}[1], [x21],#16
+da86e30d| gnu ld2 {v26.d, v27.d}[0], [x22], x3
+e7cf604d| gnu ld2r {v7.2d, v8.2d}, [sp]
+5ac8ff0d| gnu ld2r {v26.2s, v27.2s}, [x2],#8
+13c1f10d| gnu ld2r {v19.8b, v20.8b}, [x8], x17
+0947404c| gnu ld3 {v9.8h-v11.8h}, [x24]
+8043df0c| gnu ld3 {v0.8b-v2.8b}, [x28],#24
+6344d50c| gnu ld3 {v3.4h-v5.4h}, [x3], x21
+663d400d| gnu ld3 {v6.b-v8.b}[7], [x11]
+5b6b400d| gnu ld3 {v27.h-v29.h}[1], [x26]
+02a0404d| gnu ld3 {v2.s-v4.s}[2], [x0]
+e1a5404d| gnu ld3 {v1.d-v3.d}[1], [x15]
+b53edf0d| gnu ld3 {v21.b-v23.b}[7], [x21],#3
+f625d10d| gnu ld3 {v22.b-v24.b}[1], [x15], x17
+3d7bda4d| gnu ld3 {v29.h-v31.h}[7], [x25], x26
+6ea0df0d| gnu ld3 {v14.s-v16.s}[0], [x3],#12
+d9a0c60d| gnu ld3 {v25.s-v27.s}[0], [x6], x6
+b6a7df0d| gnu ld3 {v22.d-v24.d}[0], [x29],#24
+dfa6d94d| gnu ld3 {v31.d, v0.d, v1.d}[1], [x22], x25
+7de9404d| gnu ld3r {v29.4s-v31.4s}, [x11]
+2fe6df4d| gnu ld3r {v15.8h-v17.8h}, [x17],#6
+cae7c84d| gnu ld3r {v10.8h-v12.8h}, [x30], x8
+9a0b400c| gnu ld4 {v26.2s-v29.2s}, [x28]
+4b03df0c| gnu ld4 {v11.8b-v14.8b}, [x26],#32
+8e0bcc4c| gnu ld4 {v14.4s-v17.4s}, [x28], x12
+182c604d| gnu ld4 {v24.b-v27.b}[11], [x0]
+feb2600d| gnu ld4 {v30.s, v31.s, v0.s, v1.s}[1], [x23]
+59a4604d| gnu ld4 {v25.d-v28.d}[1], [x2]
+9b25ff4d| gnu ld4 {v27.b-v30.b}[9], [x12],#4
+1f35e84d| gnu ld4 {v31.b, v0.b, v1.b, v2.b}[13], [x8], x8
+91b2ff4d| gnu ld4 {v17.s-v20.s}[3], [x20],#16
+88b3ed4d| gnu ld4 {v8.s-v11.s}[3], [x28], x13
+9aa5ff4d| gnu ld4 {v26.d-v29.d}[1], [x12],#32
+efa5e10d| gnu ld4 {v15.d-v18.d}[0], [x15], x1
+07ed604d| gnu ld4r {v7.2d-v10.2d}, [x8]
+0defff0d| gnu ld4r {v13.1d-v16.1d}, [x24],#32
+43e1f14d| gnu ld4r {v3.16b-v6.16b}, [x10], x17
+136e682c| gnu ldnp s19, s27, [x16,#-192]
+cc67676c| gnu ldnp d12, d25, [x30,#-400]
+e6dd4eac| gnu ldnp q6, q23, [x15,#464]
+b7e9c22c| gnu ldp s23, s26, [x13],#20
+92c3fe6c| gnu ldp d18, d16, [x28],#-24
+f281e6ac| gnu ldp q18, q0, [x15],#-816
+4f06cd2d| gnu ldp s15, s1, [x18,#104]!
+0f6fdc6d| gnu ldp d15, d27, [x24,#448]!
+170ccbad| gnu ldp q23, q3, [x0,#352]!
+71ea7a2d| gnu ldp s17, s26, [x19,#-44]
+c8816c6d| gnu ldp d8, d0, [x14,#-312]
+da6540ad| gnu ldp q26, q25, [x14]
+92064c3c| gnu ldr b18, [x20],#192
+94d4577c| gnu ldr h20, [x4],#-131
+39055fbc| gnu ldr s25, [x9],#-16
+989551fc| gnu ldr d24, [x12],#-231
+4764c23c| gnu ldr q7, [x2],#38
+c15e4e3c| gnu ldr b1, [x22,#229]!
+c8ce487c| gnu ldr h8, [x22,#140]!
+ca5d5bbc| gnu ldr s10, [x14,#-75]!
+34fd56fc| gnu ldr d20, [x9,#-145]!
+bd0dd53c| gnu ldr q29, [x13,#-176]!
+ab65443d| gnu ldr b11, [x13,#281]
+cb57537d| gnu ldr h11, [x30,#2474]
+f2606fbd| gnu ldr s18, [x7,#12128]
+088b67fd| gnu ldr d8, [x24,#20240]
+0173ce3d| gnu ldr q1, [x24,#14784]
+ba112c1c| gnu ldr s26, .+0x58234
+e489c25c| gnu ldr d4, .+0xfffffffffff8513c
+42458d9c| gnu ldr q2, .+0xfffffffffff1a8a8
+3cdb753c| gnu ldr b28, [x25,w21,sxtw #0]
+726b733c| gnu ldr b18, [x27,x19]
+395b627c| gnu ldr h25, [x25,w2,uxtw #1]
+9b486cbc| gnu ldr s27, [x4,w12,uxtw]
+1cda7efc| gnu ldr d28, [x16,w30,sxtw #3]
+365bf33c| gnu ldr q22, [x25,w19,uxtw #4]
+43a1413c| gnu ldur b3, [x10,#26]
+c7034f7c| gnu ldur h7, [x30,#240]
+ad8350bc| gnu ldur s13, [x29,#-248]
+07a350fc| gnu ldur d7, [x24,#-246]
+0212c63c| gnu ldur q2, [x16,#97]
+6f0a7a2f| gnu mla v15.4h, v19.4h, v10.h[7]
+fe95294e| gnu mla v30.16b, v15.16b, v9.16b
+f24a4f2f| gnu mls v18.4h, v23.4h, v15.h[4]
+26947e2e| gnu mls v6.4h, v1.4h, v30.4h
+6606115e| gnu mov b6, v19.b[8]
+0866116e| gnu mov v8.b[8], v16.b[12]
+6e1d0f4e| gnu mov v14.b[7], w11
+6d1fa10e| gnu orr v13.8b, v27.8b, v1.8b
+b93f1a0e| gnu umov w25, v29.h[6]
+74e7020f| gnu movi v20.8b, #0x5b
+0ff4040f| gnu fmov v15.2s, #-2.000000000000000000e+00
+4c47060f| gnu movi v12.2s, #0xda, lsl #16
+aa06064f| gnu movi v10.4s, #0xd5
+8de4042f| gnu movi d13, #0xff00000000ff0000
+b1e6046f| gnu movi v17.2d, #0xff0000ff00ff00ff
+609f214e| gnu mul v0.16b, v27.16b, v1.16b
+9f5a206e| gnu mvn v31.16b, v20.16b
+da65032f| gnu mvni v26.2s, #0x6e, lsl #24
+4d36036f| gnu bic v13.4s, #0x72, lsl #8
+4d66052f| gnu mvni v13.2s, #0xb2, lsl #24
+a4bbe06e| gnu neg v4.2d, v29.2d
+bf5a206e| gnu mvn v31.16b, v21.16b
+2b1fe24e| gnu orn v11.16b, v25.16b, v2.16b
+22e4024f| gnu movi v2.16b, #0x41
+3086050f| gnu movi v16.4h, #0xb1
+051db80e| gnu orr v5.8b, v8.8b, v24.8b
+48e2290e| gnu pmull v8.8h, v18.8b, v9.8b
+7341652e| gnu raddhn v19.4h, v11.4s, v5.4s
+1b417f6e| gnu raddhn2 v27.8h, v8.4s, v31.4s
+e158606e| gnu rbit v1.16b, v7.16b
+f418200e| gnu rev16 v20.8b, v7.8b
+228d2a0f| gnu rshrn v2.2s, v9.2d, #22
+a861aa2e| gnu rsubhn v8.2s, v13.2d, v10.2d
+7160786e| gnu rsubhn2 v17.8h, v3.4s, v24.4s
+cc7f314e| gnu saba v12.16b, v30.16b, v17.16b
+1350644e| gnu sabal2 v19.4s, v0.8h, v4.8h
+a1757d4e| gnu sabd v1.8h, v13.8h, v29.8h
+0971a00e| gnu sabdl v9.2d, v8.2s, v0.2s
+af70214e| gnu sabdl2 v15.8h, v5.16b, v1.16b
+626ba04e| gnu sadalp v2.2d, v27.4s
+1503374e| gnu saddl2 v21.8h, v24.16b, v23.16b
+592b204e| gnu saddlp v25.8h, v26.16b
+d813600e| gnu saddw v24.4s, v30.4s, v0.4h
+31e5210f| gnu scvtf v17.2s, v9.2s, #31
+aeda215e| gnu scvtf s14, s21
+f0e9021e| gnu scvtf s16, w15, #6
+42b4421e| gnu scvtf d2, w2, #19
+8b10029e| gnu scvtf s11, x4, #60
+59e6429e| gnu scvtf d25, x18, #7
+cf01221e| gnu scvtf s15, w14
+2d03621e| gnu scvtf d13, w25
+af00229e| gnu scvtf s15, x5
+bf00629e| gnu scvtf d31, x5
+2a02025e| gnu sha1c q10, s17, v2.4s
+8b0b285e| gnu sha1h s11, s28
+11201f5e| gnu sha1m q17, s0, v31.4s
+f110115e| gnu sha1p q17, s7, v17.4s
+b732115e| gnu sha1su0 v23.4s, v21.4s, v17.4s
+cf18285e| gnu sha1su1 v15.4s, v6.4s
+2e520f5e| gnu sha256h2 q14, q17, v15.4s
+77401a5e| gnu sha256h q23, q3, v26.4s
+b92a285e| gnu sha256su0 v25.4s, v21.4s
+7e63175e| gnu sha256su1 v30.4s, v27.4s, v23.4s
+d504ab0e| gnu shadd v21.2s, v6.2s, v11.2s
+5a54734f| gnu shl v26.2d, v2.2d, #51
+0638212e| gnu shll v6.8h, v0.8b, #8
+a238216e| gnu shll2 v2.8h, v5.16b, #8
+f5863e0f| gnu shrn v21.2s, v23.2d, #2
+f187234f| gnu shrn2 v17.4s, v31.2d, #29
+e124b04e| gnu shsub v1.4s, v7.4s, v16.4s
+3657252f| gnu sli v22.2s, v25.2s, #5
+c266aa4e| gnu smax v2.4s, v22.4s, v10.4s
+2c6ca74e| gnu smin v12.4s, v1.4s, v7.4s
+4aae390e| gnu sminp v10.8b, v18.8b, v25.8b
+1a82ba0e| gnu smlal v26.2d, v16.2s, v26.2s
+2381ad4e| gnu smlal2 v3.2d, v9.4s, v13.4s
+0da17a4e| gnu smlsl2 v13.4s, v8.8h, v26.8h
+4f2e0d4e| gnu smov x15, v18.b[6]
+e4a0980f| gnu smull v4.2d, v7.2s, v24.s[0]
+51c2220e| gnu smull v17.8h, v18.8b, v2.8b
+01c26d4e| gnu smull2 v1.4s, v16.8h, v13.8h
+f978205e| gnu sqabs b25, b7
+760cef5e| gnu sqadd d22, d3, d15
+390c224e| gnu sqadd v25.16b, v1.16b, v2.16b
+5439455f| gnu sqdmlal s20, h10, v5.h[4]
+8391765e| gnu sqdmlal s3, h12, h22
+c9907a4e| gnu sqdmlal2 v9.4s, v6.8h, v26.8h
+0b73445f| gnu sqdmlsl s11, h24, v4.h[0]
+8e728d0f| gnu sqdmlsl v14.2d, v20.2s, v13.s[0]
+fe787d4f| gnu sqdmlsl2 v30.4s, v7.8h, v13.h[7]
+bdb2b55e| gnu sqdmlsl d29, s21, s21
+d0c9be4f| gnu sqdmulh v16.4s, v14.4s, v30.s[3]
+89b77c5e| gnu sqdmulh h9, h28, h28
+c9bb515f| gnu sqdmull s9, h30, v1.h[5]
+5379e07e| gnu sqneg d19, d10
+4b7aa06e| gnu sqneg v11.4s, v18.4s
+1bd1750f| gnu sqrdmulh v27.4h, v8.4h, v5.h[3]
+f55e755e| gnu sqrshl h21, h23, h21
+ba5fbd4e| gnu sqrshl v26.4s, v29.4s, v29.4s
+ba9d1e0f| gnu sqrshrn v26.4h, v13.4s, #2
+3d9c284f| gnu sqrshrn2 v29.4s, v1.2d, #24
+8a8f2c6f| gnu sqrshrun2 v10.4s, v28.2d, #20
+eb760b5f| gnu sqshl b11, b23, #3
+4a77220f| gnu sqshl v10.2s, v26.2s, #2
+6c4cfb5e| gnu sqshl d12, d3, d27
+ad4eba4e| gnu sqshl v13.4s, v21.4s, v26.4s
+9364257f| gnu sqshlu s19, s4, #5
+b267392f| gnu sqshlu v18.2s, v29.2s, #25
+c085042f| gnu mvni v0.4h, #0x8e
+7584326f| gnu sqshrun2 v21.4s, v3.2d, #14
+3a2fe25e| gnu sqsub d26, d25, d2
+2c2ca34e| gnu sqsub v12.4s, v1.4s, v3.4s
+484ba15e| gnu sqxtn s8, d26
+824b210e| gnu sqxtn v2.8b, v28.8h
+5b48214e| gnu sqxtn2 v27.16b, v2.8h
+e228a16e| gnu sqxtun2 v2.4s, v7.2d
+1c44416f| gnu sri v28.2d, v0.2d, #63
+1e56eb5e| gnu srshl d30, d16, d11
+bb56fe4e| gnu srshl v27.2d, v21.2d, v30.2d
+c6262d0f| gnu srshr v6.2s, v22.2s, #19
+0c366c5f| gnu srsra d12, d16, #20
+13376e4f| gnu srsra v19.2d, v24.2d, #18
+7ba5040f| gnu movi v27.4h, #0x8b, lsl #8
+9c076f5f| gnu sshr d28, d28, #17
+2804434f| gnu sshr v8.2d, v1.2d, #61
+b717535f| gnu ssra d23, d29, #45
+c2160f0f| gnu ssra v2.8b, v22.8b, #1
+8a333a4e| gnu ssubw2 v10.8h, v28.8h, v26.16b
+3a70000c| gnu st1 {v26.8b}, [x1]
+1bab004c| gnu st1 {v27.4s, v28.4s}, [x24]
+8d69004c| gnu st1 {v13.4s-v15.4s}, [x12]
+9c26004c| gnu st1 {v28.8h-v31.8h}, [x20]
+c87a9f0c| gnu st1 {v8.2s}, [x22],#8
+5a7f800c| gnu st1 {v26.1d}, [x26], x0
+eea99f4c| gnu st1 {v14.4s, v15.4s}, [x15],#32
+11af9d4c| gnu st1 {v17.2d, v18.2d}, [x24], x29
+ec689f0c| gnu st1 {v12.2s-v14.2s}, [x7],#24
+8662900c| gnu st1 {v6.8b-v8.8b}, [x20], x16
+0b249f4c| gnu st1 {v11.8h-v14.8h}, [x0],#64
+6b2d8b4c| gnu st1 {v11.2d-v14.2d}, [x11], x11
+3212004d| gnu st1 {v18.b}[12], [x17]
+3392004d| gnu st1 {v19.s}[3], [x17]
+0284000d| gnu st1 {v2.d}[0], [x0]
+340f9f0d| gnu st1 {v20.b}[3], [x25],#1
+0d069a4d| gnu st1 {v13.b}[9], [x16], x26
+2e51950d| gnu st1 {v14.h}[2], [x9], x21
+3f839f0d| gnu st1 {v31.s}[0], [x25],#4
+1492844d| gnu st1 {v20.s}[3], [x16], x4
+dd869f4d| gnu st1 {v29.d}[1], [x22],#8
+2e869b4d| gnu st1 {v14.d}[1], [x17], x27
+1e87000c| gnu st2 {v30.4h, v31.4h}, [x24]
+07829f0c| gnu st2 {v7.8b, v8.8b}, [x16],#16
+d38a884c| gnu st2 {v19.4s, v20.4s}, [x22], x8
+541c204d| gnu st2 {v20.b, v21.b}[15], [x2]
+9180200d| gnu st2 {v17.s, v18.s}[0], [x4]
+2585204d| gnu st2 {v5.d, v6.d}[1], [x9]
+2f06bf4d| gnu st2 {v15.b, v16.b}[9], [x17],#2
+3b08b44d| gnu st2 {v27.b, v28.b}[10], [x1], x20
+805bbf0d| gnu st2 {v0.h, v1.h}[3], [x28],#4
+fb80bf0d| gnu st2 {v27.s, v28.s}[0], [x7],#8
+6290a80d| gnu st2 {v2.s, v3.s}[1], [x3], x8
+b587bf4d| gnu st2 {v21.d, v22.d}[1], [x29],#16
+2c84b64d| gnu st2 {v12.d, v13.d}[1], [x1], x22
+22469f0c| gnu st3 {v2.4h-v4.4h}, [x17],#24
+0e30004d| gnu st3 {v14.b-v16.b}[12], [x0]
+62a1004d| gnu st3 {v2.s-v4.s}[2], [x11]
+54a4000d| gnu st3 {v20.d-v22.d}[0], [x2]
+84259f4d| gnu st3 {v4.b-v6.b}[9], [x12],#3
+693c9d4d| gnu st3 {v9.b-v11.b}[15], [x3], x29
+5b709f0d| gnu st3 {v27.h-v29.h}[2], [x2],#6
+e47a960d| gnu st3 {v4.h-v6.h}[3], [x23], x22
+a0a39f0d| gnu st3 {v0.s-v2.s}[0], [x29],#12
+37b0890d| gnu st3 {v23.s-v25.s}[1], [x1], x9
+9aa59f4d| gnu st3 {v26.d-v28.d}[1], [x12],#24
+26a5924d| gnu st3 {v6.d-v8.d}[1], [x9], x18
+3e05000c| gnu st4 {v30.4h, v31.4h, v0.4h, v1.4h}, [x9]
+a8039f0c| gnu st4 {v8.8b-v11.8b}, [x29],#32
+4126204d| gnu st4 {v1.b-v4.b}[9], [x18]
+3b71204d| gnu st4 {v27.h-v30.h}[6], [x9]
+f2b3204d| gnu st4 {v18.s-v21.s}[3], [sp]
+7fa4200d| gnu st4 {v31.d, v0.d, v1.d, v2.d}[0], [x3]
+562ebf4d| gnu st4 {v22.b-v25.b}[11], [x18],#4
+563cae0d| gnu st4 {v22.b-v25.b}[7], [x2], x14
+1271bf4d| gnu st4 {v18.h-v21.h}[6], [x8],#8
+e7a1bf0d| gnu st4 {v7.s-v10.s}[0], [x15],#16
+f3b2a30d| gnu st4 {v19.s-v22.s}[1], [x23], x3
+eca5bf4d| gnu st4 {v12.d-v15.d}[1], [x15],#32
+4ca7bb0d| gnu st4 {v12.d-v15.d}[0], [x26], x27
+4f5b182c| gnu stnp s15, s22, [x26,#192]
+e05e0b6c| gnu stnp d0, d23, [x23,#176]
+77be2eac| gnu stnp q23, q15, [x19,#-560]
+bb3fa72c| gnu stp s27, s15, [x29],#-200
+ef18bb6c| gnu stp d15, d6, [x7],#-80
+777d84ac| gnu stp q23, q31, [x11],#128
+d0f9952d| gnu stp s16, s30, [x14,#172]!
+125ca26d| gnu stp d18, d23, [x0,#-480]!
+33bbbfad| gnu stp q19, q14, [x25,#-16]!
+6ebb322d| gnu stp s14, s14, [x27,#-108]
+cb92096d| gnu stp d11, d4, [x22,#152]
+f2871dad| gnu stp q18, q1, [sp,#944]
+f676003c| gnu str b22, [x23],#7
+50f50d7c| gnu str h16, [x10],#223
+0d251ebc| gnu str s13, [x8],#-30
+1f3510fc| gnu str d31, [x8],#-253
+05a4883c| gnu str q5, [x0],#138
+800e063c| gnu str b0, [x20,#96]!
+668d157c| gnu str h6, [x11,#-168]!
+1f3d11bc| gnu str s31, [x8,#-237]!
+71bf06fc| gnu str d17, [x27,#107]!
+f50c843c| gnu str q21, [x7,#64]!
+f186013d| gnu str b17, [x23,#97]
+f0e5357d| gnu str h16, [x15,#6898]
+938d3bbd| gnu str s19, [x12,#15244]
+aeb813fd| gnu str d14, [x5,#10096]
+2cc4943d| gnu str q12, [x1,#21264]
+e2f8263c| gnu str b2, [x7,x6,sxtx #0]
+1d79373c| gnu str b29, [x8,x23,lsl #0]
+bc70003c| gnu stur b28, [x5,#7]
+7190157c| gnu stur h17, [x3,#-167]
+073309bc| gnu stur s7, [x24,#147]
+298100fc| gnu stur d9, [x9,#8]
+e8c1843c| gnu stur q8, [x15,#76]
+3384266e| gnu sub v19.16b, v1.16b, v6.16b
+9163750e| gnu subhn v17.4h, v28.4s, v21.4s
+f3627d4e| gnu subhn2 v19.8h, v23.4s, v29.4s
+1939205e| gnu suqadd b25, b8
+0638604e| gnu suqadd v6.8h, v0.8h
+81a4284f| gnu sshll2 v1.2d, v4.4s, #8
+f920030e| gnu tbl v25.8b, {v7.16b, v8.16b}, v3.8b
+71400e4e| gnu tbl v17.16b, {v3.16b-v5.16b}, v14.16b
+bc630d4e| gnu tbl v28.16b, {v29.16b, v30.16b, v31.16b, v0.16b}, v13.16b
+6803030e| gnu tbl v8.8b, {v27.16b}, v3.8b
+4b32124e| gnu tbx v11.16b, {v18.16b, v19.16b}, v18.16b
+8f50170e| gnu tbx v15.8b, {v4.16b-v6.16b}, v23.8b
+5673020e| gnu tbx v22.8b, {v26.16b-v29.16b}, v2.8b
+f2130f4e| gnu tbx v18.16b, {v31.16b}, v15.16b
+9e29c34e| gnu trn1 v30.2d, v12.2d, v3.2d
+9b6bcf4e| gnu trn2 v27.2d, v28.2d, v15.2d
+157cb02e| gnu uaba v21.2s, v0.2s, v16.2s
+28513c2e| gnu uabal v8.8h, v9.8b, v28.8b
+f950a26e| gnu uabal2 v25.2d, v7.4s, v2.4s
+a776b26e| gnu uabd v7.4s, v21.4s, v18.4s
+da726b2e| gnu uabdl v26.4s, v22.4h, v11.4h
+9473746e| gnu uabdl2 v20.4s, v28.8h, v20.8h
+aa6b602e| gnu uadalp v10.2s, v29.4h
+ac013d2e| gnu uaddl v12.8h, v13.8b, v29.8b
+e500a86e| gnu uaddl2 v5.2d, v7.4s, v8.4s
+9c28a02e| gnu uaddlp v28.1d, v4.2s
+4c3a302e| gnu uaddlv h12, v18.8b
+2810b62e| gnu uaddw v8.2d, v1.2d, v22.2s
+f2132d6e| gnu uaddw2 v18.8h, v31.8h, v13.16b
+b3e67f7f| gnu ucvtf d19, d21, #1
+ece5676f| gnu ucvtf v12.2d, v15.2d, #25
+d7d8217e| gnu ucvtf s23, s6
+cdd9212e| gnu ucvtf v13.2s, v14.2s
+5788031e| gnu ucvtf s23, w2, #30
+c7ac431e| gnu ucvtf d7, w6, #21
+0777039e| gnu ucvtf s7, x24, #35
+e4f4439e| gnu ucvtf d4, x7, #3
+9100231e| gnu ucvtf s17, w4
+e202631e| gnu ucvtf d2, w23
+3903239e| gnu ucvtf s25, x25
+2001639e| gnu ucvtf d0, x9
+2a07b76e| gnu uhadd v10.4s, v25.4s, v23.4s
+dc25372e| gnu uhsub v28.8b, v14.8b, v23.8b
+de646f2e| gnu umax v30.4h, v6.4h, v15.4h
+4ba6766e| gnu umaxp v11.8h, v18.8h, v22.8h
+e26db42e| gnu umin v2.2s, v15.2s, v20.2s
+a7ae712e| gnu uminp v7.4h, v21.4h, v17.4h
+afaa716e| gnu uminv h15, v21.8h
+42298c2f| gnu umlal v2.2d, v10.2s, v12.s[2]
+0a826e2e| gnu umlal v10.4s, v16.4h, v14.4h
+2681a06e| gnu umlal2 v6.2d, v9.4s, v0.4s
+2860bd6f| gnu umlsl2 v8.2d, v1.4s, v29.s[1]
+19a26b6e| gnu umlsl2 v25.4s, v16.8h, v11.8h
+8a3d140e| gnu mov w10, v12.s[2]
+22a1ba6f| gnu umull2 v2.2d, v9.4s, v26.s[1]
+15c0712e| gnu umull v21.4s, v0.4h, v17.4h
+2ec0296e| gnu umull2 v14.8h, v1.16b, v9.16b
+6e0fba7e| gnu uqadd s14, s27, s26
+db0fe06e| gnu uqadd v27.2d, v30.2d, v0.2d
+535e6c7e| gnu uqrshl h19, h18, h12
+7c5cfe6e| gnu uqrshl v28.2d, v3.2d, v30.2d
+9a9e327f| gnu uqrshrn s26, d20, #14
+339f0b2f| gnu uqrshrn v19.8b, v25.8h, #5
+7e77337f| gnu uqshl s30, s27, #19
+8b4d657e| gnu uqshl h11, h12, h5
+414c622e| gnu uqshl v1.4h, v2.4h, v2.4h
+95942b2f| gnu uqshrn v21.2s, v4.2d, #21
+d396246f| gnu uqshrn2 v19.4s, v22.2d, #28
+b22ff27e| gnu uqsub d18, d29, d18
+b32e756e| gnu uqsub v19.8h, v21.8h, v21.8h
+0e4b616e| gnu uqxtn2 v14.8h, v24.4s
+ca16236e| gnu urhadd v10.16b, v22.16b, v3.16b
+1f57a26e| gnu urshl v31.4s, v24.4s, v2.4s
+8324777f| gnu urshr d3, d4, #9
+37caa16e| gnu ursqrte v23.4s, v17.4s
+b735517f| gnu ursra d23, d13, #47
+0a47f67e| gnu ushl d10, d24, d22
+e7a71c2f| gnu ushll v7.4s, v31.4h, #12
+9c38607e| gnu usqadd h28, h4
+dc39206e| gnu usqadd v28.16b, v14.16b
+dc145d7f| gnu usra d28, d6, #35
+d720752e| gnu usubl v23.4s, v6.4h, v21.4h
+2c236f6e| gnu usubl2 v12.4s, v25.8h, v15.8h
+ed32222e| gnu usubw v13.8h, v23.8h, v2.8b
+72332d6e| gnu usubw2 v18.8h, v27.8h, v13.16b
+655a1c4e| gnu uzp2 v5.16b, v19.16b, v28.16b
+972a210e| gnu xtn v23.8b, v20.8h
+5f2aa14e| gnu xtn2 v31.4s, v18.2d
+9a38910e| gnu zip1 v26.2s, v4.2s, v17.2s
+d979990e| gnu zip2 v25.2s, v14.2s, v25.2s
+41e5a454| gnu b.ne .+0xfffffffffff49ca8
+ea1b543a| gnu ccmn wzr, #0x14, #0xa, ne
+681946ba| gnu ccmn x11, #0x6, #0x8, ne
+2410463a| gnu ccmn w1, w6, #0x4, ne
+6e134cba| gnu ccmn x27, x12, #0xe, ne
+ad194f7a| gnu ccmp w13, #0xf, #0xd, ne
+471b53fa| gnu ccmp x26, #0x13, #0x7, ne
+a210467a| gnu ccmp w5, w6, #0x2, ne
+ee1246fa| gnu ccmp x23, x6, #0xe, ne
+be149b1a| gnu csinc w30, w5, w27, ne
+c415819a| gnu csinc x4, x14, x1, ne
+0510955a| gnu csinv w5, w0, w21, ne
+c51093da| gnu csinv x5, x6, x19, ne
+12158e5a| gnu csneg w18, w8, w14, ne
+5c159cda| gnu csneg x28, x10, x28, ne
+c810941a| gnu csel w8, w6, w20, ne
+80128c9a| gnu csel x0, x20, x12, ne
+f6179f1a| gnu cset w22, eq
+f5179f9a| gnu cset x21, eq
+ec139f5a| gnu csetm w12, eq
+ee139fda| gnu csetm x14, eq
+4b17981a| gnu csinc w11, w26, w24, ne
+b515909a| gnu csinc x21, x13, x16, ne
+b613955a| gnu csinv w22, w29, w21, ne
+f8108bda| gnu csinv x24, x7, x11, ne
+a0149d5a| gnu csneg w0, w5, w29, ne
+6a1492da| gnu csneg x10, x3, x18, ne
+8f143c1e| gnu fccmp s4, s28, #0xf, ne
+0f167f1e| gnu fccmp d16, d31, #0xf, ne
+5214291e| gnu fccmpe s2, s9, #0x2, ne
+1516631e| gnu fccmpe d16, d3, #0x5, ne
+2b1d271e| gnu fcsel s11, s9, s7, ne
+731e611e| gnu fcsel d19, d19, d1, ne
+c2560e54| gnu b.cs .+0x1cad8
+2d2b563a| gnu ccmn w25, #0x16, #0xd, cs
+6c2b55ba| gnu ccmn x27, #0x15, #0xc, cs
+2521493a| gnu ccmn w9, w9, #0x5, cs
+032040ba| gnu ccmn x0, x0, #0x3, cs
+ea2a5c7a| gnu ccmp w23, #0x1c, #0xa, cs
+8e2842fa| gnu ccmp x4, #0x2, #0xe, cs
+8e22427a| gnu ccmp w20, w2, #0xe, cs
+cd204dfa| gnu ccmp x6, x13, #0xd, cs
+2824931a| gnu csinc w8, w1, w19, cs
+a3279a9a| gnu csinc x3, x29, x26, cs
+5921945a| gnu csinv w25, w10, w20, cs
+bd2386da| gnu csinv x29, x29, x6, cs
+a124915a| gnu csneg w1, w5, w17, cs
+5b2787da| gnu csneg x27, x26, x7, cs
+91209f1a| gnu csel w17, w4, wzr, cs
+f921979a| gnu csel x25, x15, x23, cs
+e4279f1a| gnu cset w4, cc
+ea279f9a| gnu cset x10, cc
+fe239f5a| gnu csetm w30, cc
+ec239fda| gnu csetm x12, cc
+ee25971a| gnu csinc w14, w15, w23, cs
+b726859a| gnu csinc x23, x21, x5, cs
+4b22845a| gnu csinv w11, w18, w4, cs
+2b209eda| gnu csinv x11, x1, x30, cs
+6b269b5a| gnu csneg w11, w19, w27, cs
+192691da| gnu csneg x25, x16, x17, cs
+0226391e| gnu fccmp s16, s25, #0x2, cs
+07246d1e| gnu fccmp d0, d13, #0x7, cs
+9626241e| gnu fccmpe s20, s4, #0x6, cs
+de27601e| gnu fccmpe d30, d0, #0xe, cs
+7d2d271e| gnu fcsel s29, s11, s7, cs
+3e2e7a1e| gnu fcsel d30, d17, d26, cs
+43a4df54| gnu b.cc .+0xfffffffffffbf488
+0739533a| gnu ccmn w8, #0x13, #0x7, cc
+673b4fba| gnu ccmn x27, #0xf, #0x7, cc
+e333583a| gnu ccmn wzr, w24, #0x3, cc
+83325aba| gnu ccmn x20, x26, #0x3, cc
+eb38517a| gnu ccmp w7, #0x11, #0xb, cc
+2c3955fa| gnu ccmp x9, #0x15, #0xc, cc
+6f324b7a| gnu ccmp w19, w11, #0xf, cc
+09314ffa| gnu ccmp x8, x15, #0x9, cc
+60349c1a| gnu csinc w0, w3, w28, cc
+8835949a| gnu csinc x8, x12, x20, cc
+bb31935a| gnu csinv w27, w13, w19, cc
+9f319dda| gnu csinv xzr, x12, x29, cc
+8837855a| gnu csneg w8, w28, w5, cc
+cd3490da| gnu csneg x13, x6, x16, cc
+b033901a| gnu csel w16, w29, w16, cc
+5e31969a| gnu csel x30, x10, x22, cc
+ec379f1a| gnu cset w12, cs
+ea379f9a| gnu cset x10, cs
+eb339f5a| gnu csetm w11, cs
+fd339fda| gnu csetm x29, cs
+9934941a| gnu csinc w25, w4, w20, cc
+fa36829a| gnu csinc x26, x23, x2, cc
+2730895a| gnu csinv w7, w1, w9, cc
+703094da| gnu csinv x16, x3, x20, cc
+f636935a| gnu csneg w22, w23, w19, cc
+ba3484da| gnu csneg x26, x5, x4, cc
+e3343e1e| gnu fccmp s7, s30, #0x3, cc
+ce366a1e| gnu fccmp d22, d10, #0xe, cc
+de37271e| gnu fccmpe s30, s7, #0xe, cc
+1935751e| gnu fccmpe d8, d21, #0x9, cc
+603f241e| gnu fcsel s0, s27, s4, cc
+653f761e| gnu fcsel d5, d27, d22, cc
+a4fa5354| gnu b.mi .+0xa7f54
+a248483a| gnu ccmn w5, #0x8, #0x2, mi
+e2484eba| gnu ccmn x7, #0xe, #0x2, mi
+2841553a| gnu ccmn w9, w21, #0x8, mi
+6e4259ba| gnu ccmn x19, x25, #0xe, mi
+2048567a| gnu ccmp w1, #0x16, #0x0, mi
+454a5afa| gnu ccmp x18, #0x1a, #0x5, mi
+0343487a| gnu ccmp w24, w8, #0x3, mi
+49434bfa| gnu ccmp x26, x11, #0x9, mi
+d747991a| gnu csinc w23, w30, w25, mi
+9544919a| gnu csinc x21, x4, x17, mi
+76428c5a| gnu csinv w22, w19, w12, mi
+06418eda| gnu csinv x6, x8, x14, mi
+4d46975a| gnu csneg w13, w18, w23, mi
+d74491da| gnu csneg x23, x6, x17, mi
+0941941a| gnu csel w9, w8, w20, mi
+2d41839a| gnu csel x13, x9, x3, mi
+ef479f1a| gnu cset w15, pl
+e5479f9a| gnu cset x5, pl
+f0439f5a| gnu csetm w16, pl
+e2439fda| gnu csetm x2, pl
+2a46841a| gnu csinc w10, w17, w4, mi
+f1468b9a| gnu csinc x17, x23, x11, mi
+3441835a| gnu csinv w20, w9, w3, mi
+b5438cda| gnu csinv x21, x29, x12, mi
+ad45945a| gnu csneg w13, w13, w20, mi
+f54793da| gnu csneg x21, xzr, x19, mi
+c5473f1e| gnu fccmp s30, s31, #0x5, mi
+8947601e| gnu fccmp d28, d0, #0x9, mi
+5247331e| gnu fccmpe s26, s19, #0x2, mi
+b045761e| gnu fccmpe d13, d22, #0x0, mi
+b34d331e| gnu fcsel s19, s13, s19, mi
+3a4d6d1e| gnu fcsel d26, d9, d13, mi
+a5497054| gnu b.pl .+0xe0934
+eb5a493a| gnu ccmn w23, #0x9, #0xb, pl
+0a5941ba| gnu ccmn x8, #0x1, #0xa, pl
+0452523a| gnu ccmn w16, w18, #0x4, pl
+e55053ba| gnu ccmn x7, x19, #0x5, pl
+a45b407a| gnu ccmp w29, #0x0, #0x4, pl
+ca5b4efa| gnu ccmp x30, #0xe, #0xa, pl
+ab514e7a| gnu ccmp w13, w14, #0xb, pl
+ce5349fa| gnu ccmp x30, x9, #0xe, pl
+8555971a| gnu csinc w5, w12, w23, pl
+4b569e9a| gnu csinc x11, x18, x30, pl
+90538f5a| gnu csinv w16, w28, w15, pl
+c3508bda| gnu csinv x3, x6, x11, pl
+1f55955a| gnu csneg wzr, w8, w21, pl
+52568eda| gnu csneg x18, x18, x14, pl
+a750851a| gnu csel w7, w5, w5, pl
+b252899a| gnu csel x18, x21, x9, pl
+eb579f1a| gnu cset w11, mi
+e6579f9a| gnu cset x6, mi
+fd539f5a| gnu csetm w29, mi
+e1539fda| gnu csetm x1, mi
+33579e1a| gnu csinc w19, w25, w30, pl
+b5558c9a| gnu csinc x21, x13, x12, pl
+ec53885a| gnu csinv w12, wzr, w8, pl
+ec5196da| gnu csinv x12, x15, x22, pl
+ae57945a| gnu csneg w14, w29, w20, pl
+64578bda| gnu csneg x4, x27, x11, pl
+2657241e| gnu fccmp s25, s4, #0x6, pl
+2357761e| gnu fccmp d25, d22, #0x3, pl
+f255361e| gnu fccmpe s15, s22, #0x2, pl
+3756781e| gnu fccmpe d17, d24, #0x7, pl
+985c3f1e| gnu fcsel s24, s4, s31, pl
+5b5d621e| gnu fcsel d27, d10, d2, pl
+c6d26454| gnu b.vs .+0xc9a58
+6c6a4f3a| gnu ccmn w19, #0xf, #0xc, vs
+2f694cba| gnu ccmn x9, #0xc, #0xf, vs
+e962583a| gnu ccmn w23, w24, #0x9, vs
+80615fba| gnu ccmn x12, xzr, #0x0, vs
+4b6b497a| gnu ccmp w26, #0x9, #0xb, vs
+cc6a48fa| gnu ccmp x22, #0x8, #0xc, vs
+4e61567a| gnu ccmp w10, w22, #0xe, vs
+476054fa| gnu ccmp x2, x20, #0x7, vs
+c965911a| gnu csinc w9, w14, w17, vs
+41668f9a| gnu csinc x1, x18, x15, vs
+db608f5a| gnu csinv w27, w6, w15, vs
+896097da| gnu csinv x9, x4, x23, vs
+1867915a| gnu csneg w24, w24, w17, vs
+49678eda| gnu csneg x9, x26, x14, vs
+3162881a| gnu csel w17, w17, w8, vs
+db608f9a| gnu csel x27, x6, x15, vs
+f9679f1a| gnu cset w25, vc
+f9679f9a| gnu cset x25, vc
+f7639f5a| gnu csetm w23, vc
+e1639fda| gnu csetm x1, vc
+f4678a1a| gnu csinc w20, wzr, w10, vs
+3e65879a| gnu csinc x30, x9, x7, vs
+6c63975a| gnu csinv w12, w27, w23, vs
+806191da| gnu csinv x0, x12, x17, vs
+7f679f5a| gnu csneg wzr, w27, wzr, vs
+3b6488da| gnu csneg x27, x1, x8, vs
+0565301e| gnu fccmp s8, s16, #0x5, vs
+e266621e| gnu fccmp d23, d2, #0x2, vs
+b7653a1e| gnu fccmpe s13, s26, #0x7, vs
+d866791e| gnu fccmpe d22, d25, #0x8, vs
+326d3d1e| gnu fcsel s18, s9, s29, vs
+f66e7b1e| gnu fcsel d22, d23, d27, vs
+e774fd54| gnu b.vc .+0xffffffffffffae9c
+0479483a| gnu ccmn w8, #0x8, #0x4, vc
+897b56ba| gnu ccmn x28, #0x16, #0x9, vc
+8b70513a| gnu ccmn w4, w17, #0xb, vc
+ca7150ba| gnu ccmn x14, x16, #0xa, vc
+46794f7a| gnu ccmp w10, #0xf, #0x6, vc
+057948fa| gnu ccmp x8, #0x8, #0x5, vc
+0373417a| gnu ccmp w24, w1, #0x3, vc
+ca705ffa| gnu ccmp x6, xzr, #0xa, vc
+d3769f1a| gnu csinc w19, w22, wzr, vc
+1076899a| gnu csinc x16, x16, x9, vc
+c8718e5a| gnu cinv w8, w14, vs
+06729eda| gnu csinv x6, x16, x30, vc
+6076895a| gnu csneg w0, w19, w9, vc
+b87589da| gnu csneg x24, x13, x9, vc
+3b72891a| gnu csel w27, w17, w9, vc
+fd70899a| gnu csel x29, x7, x9, vc
+e3779f1a| gnu cset w3, vs
+f4779f9a| gnu cset x20, vs
+fc739f5a| gnu csetm w28, vs
+ea739fda| gnu csetm x10, vs
+ab75891a| gnu csinc w11, w13, w9, vc
+6177859a| gnu csinc x1, x27, x5, vc
+3272945a| gnu csinv w18, w17, w20, vc
+7a729dda| gnu csinv x26, x19, x29, vc
+b5779e5a| gnu csneg w21, w29, w30, vc
+fe748eda| gnu csneg x30, x7, x14, vc
+ed76231e| gnu fccmp s23, s3, #0xd, vc
+cf74791e| gnu fccmp d6, d25, #0xf, vc
+b4763e1e| gnu fccmpe s21, s30, #0x4, vc
+59766e1e| gnu fccmpe d18, d14, #0x9, vc
+ce7c271e| gnu fcsel s14, s6, s7, vc
+be7c651e| gnu fcsel d30, d5, d5, vc
+88f29d54| gnu b.hi .+0xfffffffffff3be50
+8f8b513a| gnu ccmn w28, #0x11, #0xf, hi
+6f8b5cba| gnu ccmn x27, #0x1c, #0xf, hi
+8780463a| gnu ccmn w4, w6, #0x7, hi
+4f8348ba| gnu ccmn x26, x8, #0xf, hi
+48884d7a| gnu ccmp w2, #0xd, #0x8, hi
+088957fa| gnu ccmp x8, #0x17, #0x8, hi
+0180517a| gnu ccmp w0, w17, #0x1, hi
+ce805efa| gnu ccmp x6, x30, #0xe, hi
+1d868e1a| gnu csinc w29, w16, w14, hi
+0785889a| gnu cinc x7, x8, ls
+4782935a| gnu csinv w7, w18, w19, hi
+118197da| gnu csinv x17, x8, x23, hi
+00868a5a| gnu csneg w0, w16, w10, hi
+128585da| gnu csneg x18, x8, x5, hi
+4c808f1a| gnu csel w12, w2, w15, hi
+7783909a| gnu csel x23, x27, x16, hi
+e5879f1a| gnu cset w5, ls
+f3879f9a| gnu cset x19, ls
+f9839f5a| gnu csetm w25, ls
+eb839fda| gnu csetm x11, ls
+b3869e1a| gnu csinc w19, w21, w30, hi
+f086909a| gnu csinc x16, x23, x16, hi
+34839c5a| gnu csinv w20, w25, w28, hi
+ea8294da| gnu csinv x10, x23, x20, hi
+8e84895a| gnu csneg w14, w4, w9, hi
+c48695da| gnu csneg x4, x22, x21, hi
+cc84361e| gnu fccmp s6, s22, #0xc, hi
+8086781e| gnu fccmp d20, d24, #0x0, hi
+7187341e| gnu fccmpe s27, s20, #0x1, hi
+30867e1e| gnu fccmpe d17, d30, #0x0, hi
+b98e361e| gnu fcsel s25, s21, s22, hi
+2c8c651e| gnu fcsel d12, d1, d5, hi
+69888c54| gnu b.ls .+0xfffffffffff1910c
+0e9b523a| gnu ccmn w24, #0x12, #0xe, ls
+679854ba| gnu ccmn x3, #0x14, #0x7, ls
+0492563a| gnu ccmn w16, w22, #0x4, ls
+42924dba| gnu ccmn x18, x13, #0x2, ls
+2198417a| gnu ccmp w1, #0x1, #0x1, ls
+c89a54fa| gnu ccmp x22, #0x14, #0x8, ls
+0f905e7a| gnu ccmp w0, w30, #0xf, ls
+c59342fa| gnu ccmp x30, x2, #0x5, ls
+0d958c1a| gnu csinc w13, w8, w12, ls
+7596879a| gnu csinc x21, x19, x7, ls
+1791905a| gnu csinv w23, w8, w16, ls
+5e9186da| gnu csinv x30, x10, x6, ls
+23969e5a| gnu csneg w3, w17, w30, ls
+619493da| gnu csneg x1, x3, x19, ls
+b5918e1a| gnu csel w21, w13, w14, ls
+b393819a| gnu csel x19, x29, x1, ls
+f9979f1a| gnu cset w25, hi
+ee979f9a| gnu cset x14, hi
+eb939f5a| gnu csetm w11, hi
+ea939fda| gnu csetm x10, hi
+f497871a| gnu csinc w20, wzr, w7, ls
+c4949d9a| gnu csinc x4, x6, x29, ls
+e892895a| gnu csinv w8, w23, w9, ls
+6c908eda| gnu csinv x12, x3, x14, ls
+26949f5a| gnu csneg w6, w1, wzr, ls
+329498da| gnu csneg x18, x1, x24, ls
+81952d1e| gnu fccmp s12, s13, #0x1, ls
+60967f1e| gnu fccmp d19, d31, #0x0, ls
+1794321e| gnu fccmpe s0, s18, #0x7, ls
+3f97641e| gnu fccmpe d25, d4, #0xf, ls
+089c2d1e| gnu fcsel s8, s0, s13, ls
+699f631e| gnu fcsel d9, d27, d3, ls
+8afbfe54| gnu b.ge .+0xffffffffffffdf70
+44aa573a| gnu ccmn w18, #0x17, #0x4, ge
+00a84fba| gnu ccmn x0, #0xf, #0x0, ge
+c9a04d3a| gnu ccmn w6, w13, #0x9, ge
+88a041ba| gnu ccmn x4, x1, #0x8, ge
+caaa467a| gnu ccmp w22, #0x6, #0xa, ge
+85a85cfa| gnu ccmp x4, #0x1c, #0x5, ge
+47a35f7a| gnu ccmp w26, wzr, #0x7, ge
+0aa34dfa| gnu ccmp x24, x13, #0xa, ge
+dea7981a| gnu csinc w30, w30, w24, ge
+c6a5909a| gnu csinc x6, x14, x16, ge
+8aa1965a| gnu csinv w10, w12, w22, ge
+e3a392da| gnu csinv x3, xzr, x18, ge
+20a5845a| gnu csneg w0, w9, w4, ge
+fba694da| gnu csneg x27, x23, x20, ge
+faa1851a| gnu csel w26, w15, w5, ge
+25a3959a| gnu csel x5, x25, x21, ge
+e2a79f1a| gnu cset w2, lt
+fda79f9a| gnu cset x29, lt
+eea39f5a| gnu csetm w14, lt
+e2a39fda| gnu csetm x2, lt
+efa6951a| gnu csinc w15, w23, w21, ge
+4ca69e9a| gnu csinc x12, x18, x30, ge
+22a2885a| gnu csinv w2, w17, w8, ge
+53a089da| gnu csinv x19, x2, x9, ge
+f9a6875a| gnu csneg w25, w23, w7, ge
+c9a795da| gnu csneg x9, x30, x21, ge
+24a73e1e| gnu fccmp s25, s30, #0x4, ge
+6da5651e| gnu fccmp d11, d5, #0xd, ge
+bda52e1e| gnu fccmpe s13, s14, #0xd, ge
+f6a7651e| gnu fccmpe d31, d5, #0x6, ge
+e3ac251e| gnu fcsel s3, s7, s5, ge
+b3ae781e| gnu fcsel d19, d21, d24, ge
+ab621754| gnu b.lt .+0x2ec54
+e1b84c3a| gnu ccmn w7, #0xc, #0x1, lt
+89ba4eba| gnu ccmn x20, #0xe, #0x9, lt
+88b14a3a| gnu ccmn w12, w10, #0x8, lt
+89b145ba| gnu ccmn x12, x5, #0x9, lt
+47b9547a| gnu ccmp w10, #0x14, #0x7, lt
+07b95bfa| gnu ccmp x8, #0x1b, #0x7, lt
+4ab2407a| gnu ccmp w18, w0, #0xa, lt
+8ab144fa| gnu ccmp x12, x4, #0xa, lt
+79b5821a| gnu csinc w25, w11, w2, lt
+8bb4919a| gnu csinc x11, x4, x17, lt
+c9b19f5a| gnu csinv w9, w14, wzr, lt
+10b28bda| gnu csinv x16, x16, x11, lt
+d8b4925a| gnu csneg w24, w6, w18, lt
+3ab69fda| gnu csneg x26, x17, xzr, lt
+2cb3841a| gnu csel w12, w25, w4, lt
+77b0969a| gnu csel x23, x3, x22, lt
+e2b79f1a| gnu cset w2, ge
+e9b79f9a| gnu cset x9, ge
+f4b39f5a| gnu csetm w20, ge
+f2b39fda| gnu csetm x18, ge
+87b59a1a| gnu csinc w7, w12, w26, lt
+70b69c9a| gnu csinc x16, x19, x28, lt
+17b08f5a| gnu csinv w23, w0, w15, lt
+cab288da| gnu csinv x10, x22, x8, lt
+bab7905a| gnu csneg w26, w29, w16, lt
+08b796da| gnu csneg x8, x24, x22, lt
+2eb73e1e| gnu fccmp s25, s30, #0xe, lt
+86b7671e| gnu fccmp d28, d7, #0x6, lt
+f0b6211e| gnu fccmpe s23, s1, #0x0, lt
+b2b76b1e| gnu fccmpe d29, d11, #0x2, lt
+e8bf241e| gnu fcsel s8, s31, s4, lt
+9ebd7d1e| gnu fcsel d30, d12, d29, lt
+cc87d354| gnu b.gt .+0xfffffffffffa70f8
+43c8563a| gnu ccmn w2, #0x16, #0x3, gt
+c5c94dba| gnu ccmn x14, #0xd, #0x5, gt
+6fc0533a| gnu ccmn w3, w19, #0xf, gt
+06c351ba| gnu ccmn x24, x17, #0x6, gt
+c3c95c7a| gnu ccmp w14, #0x1c, #0x3, gt
+29cb52fa| gnu ccmp x25, #0x12, #0x9, gt
+8bc25a7a| gnu ccmp w20, w26, #0xb, gt
+45c14dfa| gnu ccmp x10, x13, #0x5, gt
+80c7841a| gnu csinc w0, w28, w4, gt
+40c4919a| gnu csinc x0, x2, x17, gt
+04c2805a| gnu csinv w4, w16, w0, gt
+55c086da| gnu csinv x21, x2, x6, gt
+32c7935a| gnu csneg w18, w25, w19, gt
+31c59fda| gnu csneg x17, x9, xzr, gt
+6cc2921a| gnu csel w12, w19, w18, gt
+37c08d9a| gnu csel x23, x1, x13, gt
+eec79f1a| gnu cset w14, le
+eec79f9a| gnu cset x14, le
+f4c39f5a| gnu csetm w20, le
+f6c39fda| gnu csetm x22, le
+31c5971a| gnu csinc w17, w9, w23, gt
+76c7899a| gnu csinc x22, x27, x9, gt
+bbc1805a| gnu csinv w27, w13, w0, gt
+e8c384da| gnu csinv x8, xzr, x4, gt
+83c5955a| gnu csneg w3, w12, w21, gt
+77c790da| gnu csneg x23, x27, x16, gt
+e9c5251e| gnu fccmp s15, s5, #0x9, gt
+a3c4671e| gnu fccmp d5, d7, #0x3, gt
+71c72e1e| gnu fccmpe s27, s14, #0x1, gt
+3dc4781e| gnu fccmpe d1, d24, #0xd, gt
+57cf3d1e| gnu fcsel s23, s26, s29, gt
+8fcc7e1e| gnu fcsel d15, d4, d30, gt
+8d1ec054| gnu b.le .+0xfffffffffff803d0
+4bdb5b3a| gnu ccmn w26, #0x1b, #0xb, le
+47d94fba| gnu ccmn x10, #0xf, #0x7, le
+4dd1443a| gnu ccmn w10, w4, #0xd, le
+82d353ba| gnu ccmn x28, x19, #0x2, le
+e8d9527a| gnu ccmp w15, #0x12, #0x8, le
+00db45fa| gnu ccmp x24, #0x5, #0x0, le
+c5d1437a| gnu ccmp w14, w3, #0x5, le
+e4d041fa| gnu ccmp x7, x1, #0x4, le
+0bd6941a| gnu csinc w11, w16, w20, le
+57d6929a| gnu cinc x23, x18, gt
+3dd29a5a| gnu csinv w29, w17, w26, le
+ded085da| gnu csinv x30, x6, x5, le
+27d5985a| gnu csneg w7, w9, w24, le
+7fd59ada| gnu csneg xzr, x11, x26, le
+b7d0911a| gnu csel w23, w5, w17, le
+a4d3879a| gnu csel x4, x29, x7, le
+e6d79f1a| gnu cset w6, gt
+f1d79f9a| gnu cset x17, gt
+f3d39f5a| gnu csetm w19, gt
+f9d39fda| gnu csetm x25, gt
+42d78d1a| gnu csinc w2, w26, w13, le
+88d58a9a| gnu csinc x8, x12, x10, le
+ccd3805a| gnu csinv w12, w30, w0, le
+0fd085da| gnu csinv x15, x0, x5, le
+55d5975a| gnu csneg w21, w10, w23, le
+3fd699da| gnu csneg xzr, x17, x25, le
+60d4251e| gnu fccmp s3, s5, #0x0, le
+6dd6601e| gnu fccmp d19, d0, #0xd, le
+bdd5221e| gnu fccmpe s13, s2, #0xd, le
+f4d67d1e| gnu fccmpe d23, d29, #0x4, le
+0cdd381e| gnu fcsel s12, s8, s24, le
+70de7e1e| gnu fcsel d16, d19, d30, le
+8e585454| gnu b.al .+0xa8b10
+41eb483a| gnu ccmn w26, #0x8, #0x1, al
+8aeb42ba| gnu ccmn x28, #0x2, #0xa, al
+c8e3473a| gnu ccmn w30, w7, #0x8, al
+ade059ba| gnu ccmn x5, x25, #0xd, al
+67eb5b7a| gnu ccmp w27, #0x1b, #0x7, al
+05e849fa| gnu ccmp x0, #0x9, #0x5, al
+42e3407a| gnu ccmp w26, w0, #0x2, al
+03e053fa| gnu ccmp x0, x19, #0x3, al
+9ce4931a| gnu csinc w28, w4, w19, al
+8ee69d9a| gnu csinc x14, x20, x29, al
+68e0835a| gnu csinv w8, w3, w3, al
+20e381da| gnu csinv x0, x25, x1, al
+e0e58d5a| gnu csneg w0, w15, w13, al
+9ae589da| gnu csneg x26, x12, x9, al
+6ee0941a| gnu csel w14, w3, w20, al
+77e38a9a| gnu csel x23, x27, x10, al
+efe79f1a| gnu csinc w15, wzr, wzr, al
+e5e79f9a| gnu csinc x5, xzr, xzr, al
+f2e39f5a| gnu csinv w18, wzr, wzr, al
+fae39fda| gnu csinv x26, xzr, xzr, al
+ede7861a| gnu csinc w13, wzr, w6, al
+0ce58a9a| gnu csinc x12, x8, x10, al
+75e2835a| gnu csinv w21, w19, w3, al
+38e391da| gnu csinv x24, x25, x17, al
+fee4845a| gnu csneg w30, w7, w4, al
+09e49bda| gnu csneg x9, x0, x27, al
+a8e6271e| gnu fccmp s21, s7, #0x8, al
+ede67d1e| gnu fccmp d23, d29, #0xd, al
+bbe53b1e| gnu fccmpe s13, s27, #0xb, al
+70e6661e| gnu fccmpe d19, d6, #0x0, al
+01ee3b1e| gnu fcsel s1, s16, s27, al
+15ec651e| gnu fcsel d21, d0, d5, al
+4f462554| gnu b.al .+0x4a8c8
+eef9493a| gnu ccmn w15, #0x9, #0xe, al
+88fa53ba| gnu ccmn x20, #0x13, #0x8, al
+c0f25f3a| gnu ccmn w22, wzr, #0x0, al
+c6f05cba| gnu ccmn x6, x28, #0x6, al
+45f84c7a| gnu ccmp w2, #0xc, #0x5, al
+a3fa4afa| gnu ccmp x21, #0xa, #0x3, al
+caf3517a| gnu ccmp w30, w17, #0xa, al
+81f055fa| gnu ccmp x4, x21, #0x1, al
+cbf69e1a| gnu csinc w11, w22, w30, al
+01f48e9a| gnu csinc x1, x0, x14, al
+61f1845a| gnu csinv w1, w11, w4, al
+11f397da| gnu csinv x17, x24, x23, al
+7bf69f5a| gnu csneg w27, w19, wzr, al
+b1f686da| gnu csneg x17, x21, x6, al
+69f39e1a| gnu csel w9, w27, w30, al
+79f2859a| gnu csel x25, x19, x5, al
+e1f79f1a| gnu csinc w1, wzr, wzr, al
+e6f79f9a| gnu csinc x6, xzr, xzr, al
+fcf39f5a| gnu csinv w28, wzr, wzr, al
+fbf39fda| gnu csinv x27, xzr, xzr, al
+2ef4831a| gnu csinc w14, w1, w3, al
+55f6859a| gnu csinc x21, x18, x5, al
+4ff0905a| gnu csinv w15, w2, w16, al
+81f393da| gnu csinv x1, x28, x19, al
+8bf68d5a| gnu csneg w11, w20, w13, al
+c2f48fda| gnu csneg x2, x6, x15, al
+e9f6391e| gnu fccmp s23, s25, #0x9, al
+27f46f1e| gnu fccmp d1, d15, #0x7, al
+72f6301e| gnu fccmpe s19, s16, #0x2, al
+37f57a1e| gnu fccmpe d9, d26, #0x7, al
+fcfe3a1e| gnu fcsel s28, s23, s26, al
+80fd701e| gnu fcsel d0, d12, d16, al
+40946454| gnu b.eq .+0xc9288
+8b09473a| gnu ccmn w12, #0x7, #0xb, eq
+c50a5eba| gnu ccmn x22, #0x1e, #0x5, eq
+05005a3a| gnu ccmn w0, w26, #0x5, eq
+cf024bba| gnu ccmn x22, x11, #0xf, eq
+8a084f7a| gnu ccmp w4, #0xf, #0xa, eq
+e20a41fa| gnu ccmp x23, #0x1, #0x2, eq
+8c015f7a| gnu ccmp w12, wzr, #0xc, eq
+e4015cfa| gnu ccmp x15, x28, #0x4, eq
+42078e1a| gnu csinc w2, w26, w14, eq
+2005879a| gnu csinc x0, x9, x7, eq
+f003955a| gnu csinv w16, wzr, w21, eq
+dc019dda| gnu csinv x28, x14, x29, eq
+4607885a| gnu csneg w6, w26, w8, eq
+26069eda| gnu csneg x6, x17, x30, eq
+72018a1a| gnu csel w18, w11, w10, eq
+8003849a| gnu csel x0, x28, x4, eq
+f1079f1a| gnu cset w17, ne
+fb079f9a| gnu cset x27, ne
+ef039f5a| gnu csetm w15, ne
+e1039fda| gnu csetm x1, ne
+5307881a| gnu csinc w19, w26, w8, eq
+8a06969a| gnu csinc x10, x20, x22, eq
+ab00955a| gnu csinv w11, w5, w21, eq
+c3039bda| gnu csinv x3, x30, x27, eq
+8005875a| gnu csneg w0, w12, w7, eq
+740694da| gnu csneg x20, x19, x20, eq
+e207281e| gnu fccmp s31, s8, #0x2, eq
+2b056a1e| gnu fccmp d9, d10, #0xb, eq
+7e063f1e| gnu fccmpe s19, s31, #0xe, eq
+3c05671e| gnu fccmpe d9, d7, #0xc, eq
+830f271e| gnu fcsel s3, s28, s7, eq
+4d0d621e| gnu fcsel d13, d10, d2, eq
+bf2003d5| gnu sevl
+9f2003d5| gnu sev
+7f2003d5| gnu wfi
+5f2003d5| gnu wfe
+3f2003d5| gnu yield
+1f2003d5| gnu nop
+df4d03d5| gnu msr daifset, #0xd
+ff4d03d5| gnu msr daifclr, #0xd
+28d91b14| gnu b .+0x6f64a0
+da6cb530| gnu adr x26, .+0xfffffffffff6ad99
+15e5e514| gnu b .+0x3979454
+ff4603d5| gnu msr daifclr, #0x6
+df4803d5| gnu msr daifset, #0x8
+bf4100d5| gnu msr spsel, #0x1
+9f3f03d5| gnu dsb sy
+9f3e03d5| gnu dsb st
+9f3d03d5| gnu dsb ld
+9f3b03d5| gnu dsb ish
+9f3a03d5| gnu dsb ishst
+9f3903d5| gnu dsb ishld
+9f3703d5| gnu dsb nsh
+9f3603d5| gnu dsb nshst
+9f3503d5| gnu dsb nshld
+9f3303d5| gnu dsb osh
+9f3203d5| gnu dsb oshst
+9f3103d5| gnu dsb oshld
+ff4603d5| gnu msr daifclr, #0x6
+df4803d5| gnu msr daifset, #0x8
+bf4100d5| gnu msr spsel, #0x1
+a3681b53| gnu lsl w3, w5, #5
+47dc78d3| gnu lsl x7, x2, #8
+0500a012| gnu movn w5, #0x0, lsl #16
+0500e092| gnu movn x5, #0x0, lsl #48
+0500a052| gnu movz w5, #0x0, lsl #16
+0500a0d2| gnu movz x5, #0x0, lsl #16
+cd5a206e| gnu mvn v13.16b, v22.16b
+cd5a202e| gnu mvn v13.8b, v22.8b
+743d050e| gnu umov w20, v11.b[2]
+743d0a0e| gnu umov w20, v11.h[2]
+743d0c0e| gnu mov w20, v11.s[1]
+743d084e| gnu mov x20, v11.d[0]
+0a011f1a| plan9 ADCW ZR, R8, R10
+4c00009a| plan9 ADC R0, R2, R12
+a602093a| plan9 ADCSW R9, R21, R6
+d60217ba| plan9 ADCS R23, R22, R22
+0921250b| plan9 ADDW R5.UXTH, R8, R9
+ee9e288b| plan9 ADD R8.SXTB<<7, R23, R14
+23123011| plan9 ADDW $3076, R17, R3
+2ba32391| plan9 ADD $2280, R25, R11
+67158d0b| plan9 ADDW R13->5, R11, R7
+30da198b| plan9 ADD R25<<54, R17, R16
+a7e72c2b| plan9 ADDSW R12.SXTX<<1, R29, R7
+357338ab| plan9 ADDS R24.UXTX<<4, R25, R21
+6b147731| plan9 ADDSW $(3525<<12), R3, R11
+cd59872b| plan9 ADDSW R7->22, R14, R13
+e41f4eab| plan9 ADDS R14>>7, ZR, R4
+a2432412| plan9 ANDW $4026540031, R29, R2
+93910e92| plan9 AND $34903429696192636, R12, R19
+7a1ec98a| plan9 AND R9@>7, R19, R26
+1ff32972| plan9 TSTW $2863311530, R24
+458051f2| plan9 ANDS $-140737488289793, R2, R5
+af629a6a| plan9 ANDSW R26->24, R21, R15
+7ab0dfea| plan9 ANDS ZR@>44, R3, R26
+792bcc1a| plan9 ASRW R12, R27, R25
+872bce9a| plan9 ASR R14, R28, R7
+99ff4b93| plan9 ASR $11, R28, R25
+1628c91a| plan9 ASRW R9, R0, R22
+4e2acf9a| plan9 ASR R15, R18, R14
+4be5a454| plan9 BLT -186582(PC)
+53257114| plan9 JMP 7415123(PC)
+dbb557b3| plan9 BFXIL $23, R14, $23, R27
+70e861b3| plan9 BFXIL $33, R3, $26, R16
+88a75ab3| plan9 BFXIL $26, R28, $16, R8
+b03ce70a| plan9 BICW R7@>15, R5, R16
+9235ec8a| plan9 BIC R12@>13, R12, R18
+7450b96a| plan9 BICSW R25->20, R3, R20
+3730b3ea| plan9 BICS R19->12, R1, R23
+9b897797| plan9 CALL -8943205(PC)
+e0013fd6| plan9 CALL (R15)
+a0031fd6| plan9 JMP (R29)
+e08c31d4| plan9 BRK $35943
+4bfb543a| plan9 CCMNW AL, R26, $20, $11
+015b46ba| plan9 CCMN PL, R24, $6, $1
+8602463a| plan9 CCMNW EQ, R20, R6, $6
+c6d34cba| plan9 CCMN LE, R30, R12, $6
+a76b4f7a| plan9 CCMPW VS, R29, $15, $7
+e3d853fa| plan9 CCMP LE, R7, $19, $3
+4022467a| plan9 CCMPW HS, R18, R6, $0
+c7b346fa| plan9 CCMP LT, R30, R6, $7
+ee279b1a| plan9 CSINCW HS, ZR, R27, R14
+4174819a| plan9 CSINC VC, R2, R1, R1
+5100955a| plan9 CSINVW EQ, R2, R21, R17
+573093da| plan9 CSINV LO, R2, R19, R23
+5f3403d5| plan9 CLREX $4
+e615c05a| plan9 CLSW R15, R6
+ff15c0da| plan9 CLS R15, ZR
+2e10c05a| plan9 CLZW R1, R14
+a912c0da| plan9 CLZ R21, R9
+ff11352b| plan9 CMNW R21.UXTB<<4, R15
+1f5220ab| plan9 CMN R0.UXTW<<4, R16
+ff02266b| plan9 CMPW R6.UXTB, R23
+5fb739eb| plan9 CMP R25.SXTH<<5, R26
+bfa73bf1| plan9 CMP $3817, R29
+7f5c47eb| plan9 CMP R7>>23, R3
+2e458e5a| plan9 CSNEGW MI, R9, R14, R14
+c3559cda| plan9 CSNEG PL, R14, R28, R3
+1041d11a| plan9 CRC32B R17, R8, R16
+bb46c31a| plan9 CRC32H R3, R21, R27
+c94bd61a| plan9 CRC32W R22, R30, R9
+8f4cd49a| plan9 CRC32X R20, R4, R15
+7653d21a| plan9 CRC32CB R18, R27, R22
+1454d51a| plan9 CRC32CH R21, R0, R20
+7c58c91a| plan9 CRC32CW R9, R3, R28
+185ccb9a| plan9 CRC32CX R11, R0, R24
+8c30941a| plan9 CSELW LO, R4, R20, R12
+0ea08c9a| plan9 CSEL GE, R0, R12, R14
+e3b79f1a| plan9 CSETW GE, R3
+fea79f9a| plan9 CSET LT, R30
+e5639f5a| plan9 CSETMW VC, R5
+e4739fda| plan9 CSETM VS, R4
+bad4981a| plan9 CSINCW LE, R5, R24, R26
+5167909a| plan9 CSINC VS, R26, R16, R17
+65e3955a| plan9 CSINVW AL, R27, R21, R5
+8e338bda| plan9 CSINV LO, R28, R11, R14
+0a269d5a| plan9 CSNEGW HS, R16, R29, R10
+ab1692da| plan9 CSNEG NE, R21, R18, R11
+418ea5d4| plan9 DCPS1 $11378
+6239a5d4| plan9 DCPS2 $10699
+e3ebabd4| plan9 DCPS3 $24415
+bf3a03d5| plan9 DMB $10
+e003bfd6| plan9 DRPS
+9f3003d5| plan9 DSB $0
+c974354a| plan9 EONW R21<<29, R6, R9
+89b86eca| plan9 EON R14>>46, R4, R9
+76e343d2| plan9 EOR $-2287828610704211969, R27, R22
+536d8c4a| plan9 EORW R12->27, R10, R19
+d1ef1cca| plan9 EOR R28<<59, R30, R17
+e0039fd6| plan9 ERET
+591d8813| plan9 EXTRW $7, R8, R10, R25
+888dd693| plan9 EXTR $35, R22, R12, R8
+bf2003d5| plan9 SEVL
+df2003d5| plan9 HINT $6
+a0fc5fd4| plan9 HLT $65509
+df3103d5| plan9 ISB $1
+9dfddf88| plan9 LDARW (R12), R29
+76ffdfc8| plan9 LDAR (R27), R22
+36ffdf08| plan9 LDARB (R25), R22
+bcfcdf48| plan9 LDARH (R5), R28
+54c17f88| plan9 LDAXPW (R10), R16, R20
+3eaf7fc8| plan9 LDAXP (R25), R11, R30
+e2fd5f88| plan9 LDAXRW (R15), R2
+f5fd5fc8| plan9 LDAXR (R15), R21
+70fe5f08| plan9 LDAXRB (R19), R16
+bcfc5f48| plan9 LDAXRH (R5), R28
+ecff5928| plan9 LDNPW 204(RSP), ZR, R12
+852744a8| plan9 LDNP 64(R28), R9, R5
+1286d728| plan9 LDP.P 188(R16), (R18, R1)
+7668e8a8| plan9 LDP.P -384(R3), (R22, R26)
+6d8bc729| plan9 LDP.W 60(R27), (R13, R2)
+1cadd1a9| plan9 LDP.W 280(R8), (R28, R11)
+bf4e7e29| plan9 LDP -16(R21), (ZR, R19)
+61695fa9| plan9 LDP 496(R11), (R1, R26)
+4c00e668| plan9 LDPSW -208(R2), R0, R12
+85a0cb69| plan9 LDPSW 92(R4), R8, R5
+9b894d69| plan9 LDPSW 108(R12), R2, R27
+e9955ab8| plan9 MOVWU.P -87(R15), R9
+5c255df8| plan9 MOVD.P -46(R10), R28
+703c57b8| plan9 MOVWU.W -141(R3), R16
+1dac57f8| plan9 MOVD.W -134(R0), R29
+393c50b9| plan9 MOVWU 4156(R1), R25
+498d5cf9| plan9 MOVD 14616(R10), R9
+8ca74238| plan9 MOVBU.P 42(R28), R12
+4e5c5e38| plan9 MOVBU.W -27(R2), R14
+03936d39| plan9 MOVBU 2916(R24), R3
+577a6e38| plan9 MOVBU R14<<1(R18), R23
+adb54678| plan9 MOVHU.P 107(R13), R13
+820f4c78| plan9 MOVHU.W 192(R28), R2
+92787579| plan9 MOVHU 6844(R4), R18
+4bd6c438| plan9 MOVBW.P 77(R18), R11
+fb478238| plan9 MOVB.P 36(RSP), R27
+4d7edc38| plan9 MOVBW.W -57(R18), R13
+18ee9438| plan9 MOVB.W -178(R16), R24
+16b9c639| plan9 MOVBW 430(R8), R22
+37958f39| plan9 MOVB 997(R9), R23
+af7ae238| plan9 MOVBW R2<<1(R21), R15
+1568fa38| plan9 MOVBW R26(R0), R21
+f069a538| plan9 MOVB R5(R15), R16
+d9a6cd78| plan9 MOVHW.P 218(R22), R25
+ff368b78| plan9 MOVH.P 179(R23), ZR
+5b8cc878| plan9 MOVHW.W 136(R2), R27
+361f9c78| plan9 MOVH.W -63(R25), R22
+359bec79| plan9 MOVHW 5708(R25), R21
+4d6c8079| plan9 MOVH 54(R2), R13
+02669cb8| plan9 MOVW.P -58(R16), R2
+5c8e92b8| plan9 MOVW.W -216(R18), R28
+ea9e92b9| plan9 MOVW 4764(R23), R10
+64285eb8| plan9 LDTRW -30(R3), R4
+6ab851f8| plan9 LDTR -229(R3), R10
+aa094f38| plan9 LDTRBW 240(R13), R10
+b7894e78| plan9 LDTRHW 232(R13), R23
+85cadd38| plan9 LDTRSBW -36(R20), R5
+2db99838| plan9 LDTRSB -117(R9), R13
+7ef8ce78| plan9 LDTRSHW 239(R3), R30
+786a8978| plan9 LDTRSH 150(R19), R24
+c5eb81b8| plan9 LDTRSW 30(R30), R5
+a1f14bb8| plan9 LDURW 191(R13), R1
+c3425cf8| plan9 LDUR -60(R22), R3
+2e125038| plan9 LDURBW -255(R17), R14
+26004878| plan9 LDURHW 128(R1), R6
+c3e3cd38| plan9 LDURSBW 222(R30), R3
+27618938| plan9 LDURSB 150(R9), R7
+7c71db78| plan9 LDURSHW -73(R11), R28
+1d109e78| plan9 LDURSH -31(R0), R29
+d48084b8| plan9 LDURSW 72(R6), R20
+172f7f88| plan9 LDXPW (R24), R11, R23
+10347fc8| plan9 LDXP (R0), R13, R16
+fe7f5f88| plan9 LDXRW (RSP), R30
+6c7f5fc8| plan9 LDXR (R27), R12
+047c5f08| plan9 LDXRB (R0), R4
+9a7d5f48| plan9 LDXRH (R12), R26
+4f21cb1a| plan9 LSLW R11, R10, R15
+1523db9a| plan9 LSL R27, R24, R21
+81c74fd3| plan9 UBFX $15, R28, $35, R1
+c922c81a| plan9 LSLW R8, R22, R9
+fd22dc9a| plan9 LSL R28, R23, R29
+4226dd1a| plan9 LSRW R29, R18, R2
+a224ca9a| plan9 LSR R10, R5, R2
+707c0153| plan9 LSRW $1, R3, R16
+34fc4cd3| plan9 LSR $12, R1, R20
+6c24c91a| plan9 LSRW R9, R3, R12
+8527c89a| plan9 LSR R8, R28, R5
+ea36171b| plan9 MADDW R23, R13, R23, R10
+e47a0a9b| plan9 MADD R10, R30, R23, R4
+35fd001b| plan9 MNEGW R0, R9, R21
+77ff0e9b| plan9 MNEG R14, R27, R23
+38030011| plan9 ADDW $0, R25, R24
+37030091| plan9 ADD $0, R25, R23
+94b8ad12| plan9 MOVW $2453405695, R20
+fff29892| plan9 MOVD $-51096, ZR
+d4adb252| plan9 MOVW $2507014144, R20
+8747e2d2| plan9 MOVD $1313925191285342208, R7
+f5132d32| plan9 ORRW $16252928, ZR, R21
+eb7f34b2| plan9 MOVD $-1, R11
+f503092a| plan9 MOVW R9, R21
+e7031eaa| plan9 MOVD R30, R7
+35e8c1f2| plan9 MOVK $(3905<<32), R21
+44629512| plan9 MOVW $4294923501, R4
+cc0dd392| plan9 MOVD $-167598213824513, R12
+cbfb9152| plan9 MOVW $36830, R11
+3d25ebd2| plan9 MOVD $6424666343420723200, R29
+e67a3fd5| plan9 MRS $31703, R6
+f9dd15d5| plan9 MSR R25, $12015
+25840c1b| plan9 MSUBW R12, R1, R1, R5
+02ce1a9b| plan9 MSUB R26, R19, R16, R2
+b67c1a1b| plan9 MULW R26, R5, R22
+607c049b| plan9 MUL R4, R3, R0
+e97f6daa| plan9 MVN R13>>31, R9
+fe071f6b| plan9 NEGSW ZR<<1, R30
+f68f14eb| plan9 NEGS R20<<35, R22
+e8030d5a| plan9 NGCW R13, R8
+fe031eda| plan9 NGC R30, R30
+e5030a7a| plan9 NGCSW R10, R5
+f00318fa| plan9 NGCS R24, R16
+1f2003d5| plan9 NOP
+032ee42a| plan9 ORNW R4@>11, R16, R3
+634cf6aa| plan9 ORN R22@>19, R3, R3
+f8492d32| plan9 ORRW $4294443071, R15, R24
+96f542b2| plan9 ORR $-3458764513820540929, R12, R22
+1c110d2a| plan9 ORRW R13<<4, R8, R28
+c65b1eaa| plan9 ORR R30<<22, R30, R6
+f300b2f9| plan9 PRFM 25600(R7), PSTL2STRM
+c62184f8| plan9 PRFUM 66(R14), #0X06
+3601c05a| plan9 RBITW R9, R22
+6401c0da| plan9 RBIT R11, R4
+e0035fd6| plan9 RET ZR
+0a09c05a| plan9 REVW R8, R10
+220cc0da| plan9 REV R1, R2
+b206c05a| plan9 REV16W R21, R18
+2407c0da| plan9 REV16 R25, R4
+7e0bc0da| plan9 REV32 R27, R30
+ae0ec0da| plan9 REV R21, R14
+336f8413| plan9 EXTRW $27, R4, R25, R19
+af47ca93| plan9 EXTR $17, R10, R29, R15
+bc2cdb1a| plan9 RORW R27, R5, R28
+e52fdd9a| plan9 ROR R29, ZR, R5
+832dc31a| plan9 RORW R3, R12, R3
+e22ec09a| plan9 ROR R0, R23, R2
+1801045a| plan9 SBCW R4, R8, R24
+5a0119da| plan9 SBC R25, R10, R26
+52021b7a| plan9 SBCSW R27, R18, R18
+250105fa| plan9 SBCS R5, R9, R5
+fc430b13| plan9 SBFXW $11, ZR, $6, R28
+a0574093| plan9 SBFX $0, R29, $22, R0
+8b3b7a93| plan9 SBFIZ $6, R28, $15, R11
+fc310513| plan9 SBFXW $5, R15, $8, R28
+fbdc4293| plan9 SBFX $2, R7, $54, R27
+c90dd61a| plan9 SDIVW R22, R14, R9
+a90ecd9a| plan9 SDIV R13, R21, R9
+9f2003d5| plan9 SEV
+bf2003d5| plan9 SEVL
+d27f229b| plan9 SMULL R2, R30, R18
+efff3a9b| plan9 SMNEGL R26, ZR, R15
+7d963f9b| plan9 SMSUBL ZR, R5, R19, R29
+b57e519b| plan9 SMULH R17, R21, R21
+a07c209b| plan9 SMULL R0, R5, R0
+d0fe9f88| plan9 STLRW R16, (R22)
+03ff9fc8| plan9 STLR R3, (R24)
+8bff9f08| plan9 STLRB R11, (R28)
+f0fe9f48| plan9 STLRH R16, (R23)
+c6ae3588| plan9 STLXPW (R22), R11, R6, R21
+c6fa22c8| plan9 STLXPW (R22), R30, R6, R2
+affd0e88| plan9 STLXRW R15, (R13), R14
+67ff1cc8| plan9 STLXR R7, (R27), R28
+17ff1c08| plan9 STLXRB R23, (R24), R28
+7bfe0b48| plan9 STLXRH R27, (R19), R11
+2a8c0528| plan9 STNPW 44(R1), R3, R10
+67fc10a8| plan9 STNP 264(R3), ZR, R7
+5559bd28| plan9 STP.P (R21, R22), -24(R10)
+166c96a8| plan9 STP.P (R22, R27), 352(R0)
+3d4a8729| plan9 STP.W (R29, R18), 56(R17)
+912f86a9| plan9 STP.W (R17, R11), 96(R28)
+c40d3029| plan9 STP (R4, R3), -128(R14)
+f73f39a9| plan9 STP (R23, R15), -112(RSP)
+34441eb8| plan9 MOVW.P R20, -28(R1)
+11f60bf8| plan9 MOVD.P R17, 191(R16)
+c15d15b8| plan9 MOVW.W R1, -171(R14)
+ae4d12f8| plan9 MOVD.W R14, -220(R13)
+03ef39b9| plan9 MOVW R3, 14828(R24)
+208228f9| plan9 MOVD R0, 20736(R17)
+ffb41838| plan9 MOVB.P ZR, -117(R7)
+bb0d1a38| plan9 MOVB.W R27, -96(R13)
+b1612239| plan9 MOVB R17, 2200(R13)
+92682038| plan9 MOVB R18, R0(R4)
+81682638| plan9 MOVB R1, R6(R4)
+87841b78| plan9 MOVH.P R7, -72(R4)
+cc3d1878| plan9 MOVH.W R12, -125(R14)
+53cf1c79| plan9 MOVH R19, 3686(R26)
+63792d78| plan9 MOVH R3, R13<<1(R11)
+9d7803b8| plan9 STTRW 55(R4), R29
+b9c807f8| plan9 STTR 124(R5), R25
+f04a1e38| plan9 STTRBW -28(R23), R16
+52990078| plan9 STTRHW 9(R10), R18
+152002b8| plan9 MOVW R21, 34(R0)
+397217f8| plan9 MOVD R25, -137(R17)
+8f320138| plan9 MOVB R15, 19(R20)
+eb021b78| plan9 MOVH R11, -80(R23)
+854a3f88| plan9 STXPW (R20), R18, R5, ZR
+d12620c8| plan9 STXPW (R22), R9, R17, R0
+537e0288| plan9 STXRW R19, (R18), R2
+af7d15c8| plan9 STXR R15, (R13), R21
+e97c1d08| plan9 STXRB R9, (R7), R29
+837d1b48| plan9 STXRH R3, (R12), R27
+f25e344b| plan9 SUBW R20.UXTW<<7, R23, R18
+3ac825cb| plan9 SUB R5.SXTW<<2, R1, R26
+e8f40ccb| plan9 SUB R12<<61, R7, R8
+a6ad226b| plan9 SUBSW R2.SXTH<<3, R13, R6
+647735eb| plan9 SUBS R21.UXTX<<5, R27, R4
+c770566b| plan9 SUBSW R22>>28, R6, R7
+d03c1aeb| plan9 SUBS R26<<15, R6, R16
+a17f03d4| plan9 SVC $7165
+991f0013| plan9 SXTBW R28, R25
+a91d4093| plan9 SXTB R13, R9
+083d0013| plan9 SXTHW R8, R8
+393e4093| plan9 SXTH R17, R25
+1b7c4093| plan9 SXTW R0, R27
+0c5b2cd5| plan9 SYSL $285440, R12
+3f0d0172| plan9 TSTW $2147483655, R9
+df6f7cf2| plan9 TST $4294967280, R30
+1f2f11ea| plan9 TST R17<<11, R24
+9ced71d3| plan9 UBFX $49, R12, $11, R28
+1cbb7fd3| plan9 UBFIZ $1, R24, $47, R28
+25e661d3| plan9 UBFX $33, R17, $25, R5
+af0adc1a| plan9 UDIVW R28, R21, R15
+550ac29a| plan9 UDIV R2, R18, R21
+9102b19b| plan9 UMADDL R17, R0, R20, R17
+41fea39b| plan9 UMNEGL R3, R18, R1
+87d8a39b| plan9 UMSUBL R3, R22, R4, R7
+987ed89b| plan9 UMULH R24, R20, R24
+d37eb29b| plan9 UMULL R18, R22, R19
+461c0053| plan9 UXTBW R2, R6
+f43c0053| plan9 UXTHW R7, R20
+5f2003d5| plan9 WFE
+7f2003d5| plan9 WFI
+3f2003d5| plan9 YIELD
+e5bb200e| plan9 VABS V31.B8, V5.B8
+c9842d0e| plan9 VADD V13.B8, V6.B8, V9.B8
+f4bd394e| plan9 VADDP V25.B16, V15.B16, V20.B16
+b3b8b14e| plan9 ADDV V5.S4, F19
+cd5b284e| plan9 VAESD V30.B16, V13.B16
+4b4b284e| plan9 VAESE V26.B16, V11.B16
+2879284e| plan9 VAESIMC V9.B16, V8.B16
+fe68284e| plan9 VAESMC V7.B16, V30.B16
+f61e334e| plan9 VAND V19.B16, V23.B16, V22.B16
+88a4002f| plan9 VMVNI $(4<<8), V8.H4
+1877076f| plan9 VBIC $(248<<24), V24.S4
+0d1e6c0e| plan9 VBIC V12.B8, V16.B8, V13.B8
+b81ce26e| plan9 VBIF V2.B16, V5.B16, V24.B16
+381cbf2e| plan9 VBIT V31.B8, V1.B8, V24.B8
+cd1f6c6e| plan9 VBSL V12.B16, V30.B16, V13.B16
+8d48a00e| plan9 VCLS V4.S2, V13.S2
+324ba02e| plan9 VCLZ V25.S2, V18.S2
+c88f2b2e| plan9 VCMEQ V11.B8, V30.B8, V8.B8
+a799e05e| plan9 CMEQ $0, F13, F7
+dc9be04e| plan9 VCMEQ $0, V30.D2, V28.D2
+623f2d4e| plan9 VCMGE V13.B16, V27.B16, V2.B16
+e889e06e| plan9 VCMGE $0, V15.D2, V8.D2
+cb37e55e| plan9 CMGT F5, F30, F11
+8e37b00e| plan9 VCMGT V16.S2, V28.S2, V14.S2
+1a8be04e| plan9 VCMGT $0, V24.D2, V26.D2
+7f37eb7e| plan9 CMHI F11, F27, F31
+333d356e| plan9 VCMHS V21.B16, V9.B16, V19.B16
+bd9ae07e| plan9 CMLE $0, F21, F29
+8999602e| plan9 VCMLE $0, V12.H4, V9.H4
+aca9e05e| plan9 CMLT $0, F13, F12
+7fa8204e| plan9 VCMLT $0, V3.B16, V31.B16
+588db20e| plan9 VCMTST V18.S2, V10.S2, V24.S2
+cc051d5e| plan9 VMOV V14.B[14], F12
+4c06050e| plan9 VDUP V18.B[2], V12.B8
+790c020e| plan9 VDUP R3, V25.H4
+391d286e| plan9 VEOR V8.B16, V9.B16, V25.B16
+4b30156e| plan9 VEXT $6, V21.B16, V2.B16, V11.B16
+44d6bf7e| plan9 FABD F31, F18, F4
+17fba00e| plan9 FABS V24.S2, V23.S2
+90c2201e| plan9 FABSS F20, F16
+62c2601e| plan9 FABSD F19, F2
+eeef3f7e| plan9 FACGE F31, F31, F14
+09efa07e| plan9 FACGT F0, F24, F9
+72edae6e| plan9 VFACGT V14.S4, V11.S4, V18.S4
+61d5394e| plan9 FADD V25.S4, V11.S4, V1.S4
+0d2a3d1e| plan9 FADDS F29, F16, F13
+4b296f1e| plan9 FADDD F15, F10, F11
+78d8307e| plan9 FADDP V3.S2, F24
+e7d7322e| plan9 VFADDP V18.S2, V31.S2, V7.S2
+e8253c1e| plan9 FCCMPS HS, F28, F15, $8
+e8857f1e| plan9 FCCMPD HI, F31, F15, $8
+5714291e| plan9 FCCMPES NE, F9, F2, $7
+b484631e| plan9 FCCMPED HI, F3, F5, $4
+3ce5685e| plan9 FCMEQ F8, F9, F28
+50e6214e| plan9 VFCMEQ V1.S4, V18.S4, V16.S4
+9ddae05e| plan9 FCMEQ $0, F20, F29
+b3e62b7e| plan9 FCMGE F11, F21, F19
+0ce4396e| plan9 VFCMGE V25.S4, V0.S4, V12.S4
+a6c9e07e| plan9 FCMGE $0, F13, F6
+ede6bd7e| plan9 FCMGT F29, F23, F13
+13e6ae2e| plan9 VFCMGT V14.S2, V16.S2, V19.S2
+4cc9e05e| plan9 FCMGT $0, F10, F12
+41cba04e| plan9 VFCMGT $0, V26.S4, V1.S4
+96d8e07e| plan9 FCMLE $0, F4, F22
+0be9a05e| plan9 FCMLT $0, F8, F11
+dfe9a04e| plan9 VFCMLT $0, V14.S4, V31.S4
+a023301e| plan9 FCMPS F16, F29
+68213e1e| plan9 FCMPS $(0.0), F11
+20236d1e| plan9 FCMPD F13, F25
+68216b1e| plan9 FCMPD $(0.0), F11
+3023351e| plan9 FCMPES F21, F25
+78203e1e| plan9 FCMPES $(0.0), F3
+b022721e| plan9 FCMPED F18, F21
+f8226f1e| plan9 FCMPED $(0.0), F23
+b54e271e| plan9 FCSELS MI, F21, F7, F21
+319f611e| plan9 FCSELD LS, F25, F1, F17
+2142e21e| plan9 FCVTHS F17, F1
+cfc3e21e| plan9 FCVTHD F30, F15
+01c1231e| plan9 FCVTSH F8, F1
+4fc0221e| plan9 FCVTSD F2, F15
+f9c0631e| plan9 FCVTDH F7, F25
+2b43621e| plan9 FCVTDS F25, F11
+f1c8615e| plan9 FCVTAS F7, F17
+ea01241e| plan9 FCVTASW F15, R10
+0c02249e| plan9 FCVTAS F16, R12
+e702641e| plan9 FCVTASW F23, R7
+f501649e| plan9 FCVTAS F15, R21
+45ca217e| plan9 FCVTAU F18, F5
+66c9212e| plan9 VFCVTAU V11.S2, V6.S2
+b302251e| plan9 FCVTAUW F21, R19
+e102259e| plan9 FCVTAU F23, R1
+5703651e| plan9 FCVTAUW F26, R23
+2c01659e| plan9 FCVTAU F9, R12
+2c7b210e| plan9 VFCVTL V25.H4, V12.S4
+f478214e| plan9 VFCVTL2 V7.H8, V20.S4
+d1b8615e| plan9 FCVTMS F6, F17
+a2ba614e| plan9 VFCVTMS V21.D2, V2.D2
+ee01301e| plan9 FCVTMSW F15, R14
+de01309e| plan9 FCVTMS F14, R30
+8401701e| plan9 FCVTMSW F12, R4
+c502709e| plan9 FCVTMS F22, R5
+44b8617e| plan9 FCVTMU F2, F4
+5601311e| plan9 FCVTMUW F10, R22
+4602319e| plan9 FCVTMU F18, R6
+1003711e| plan9 FCVTMUW F24, R16
+e602719e| plan9 FCVTMU F23, R6
+c16b210e| plan9 VFCVTN V30.S4, V1.H4
+4d6b614e| plan9 VFCVTN2 V26.D2, V13.S4
+95ab215e| plan9 FCVTNS F28, F21
+65a9614e| plan9 VFCVTNS V11.D2, V5.D2
+8a02201e| plan9 FCVTNSW F20, R10
+bc03209e| plan9 FCVTNS F29, R28
+fc01601e| plan9 FCVTNSW F15, R28
+9800609e| plan9 FCVTNS F4, R24
+b1aa617e| plan9 FCVTNU F21, F17
+80a9216e| plan9 VFCVTNU V12.S4, V0.S4
+3201211e| plan9 FCVTNUW F9, R18
+e101219e| plan9 FCVTNU F15, R1
+ae00611e| plan9 FCVTNUW F5, R14
+9503619e| plan9 FCVTNU F28, R21
+3faae15e| plan9 FCVTPS F17, F31
+c4a8e14e| plan9 VFCVTPS V6.D2, V4.D2
+ab01281e| plan9 FCVTPSW F13, R11
+5800289e| plan9 FCVTPS F2, R24
+9b02681e| plan9 FCVTPSW F20, R27
+de03689e| plan9 FCVTPS F30, R30
+d8aaa17e| plan9 FCVTPU F22, F24
+e203291e| plan9 FCVTPUW F31, R2
+5302299e| plan9 FCVTPU F18, R19
+5302691e| plan9 FCVTPUW F18, R19
+8501699e| plan9 FCVTPU F12, R5
+93ff735f| plan9 FCVTZS $13, F28, F19
+b7fd504f| plan9 FCVTZS $48, V13.D2, V23.D2
+7ebba15e| plan9 FCVTZSSS F27, F30
+d49f181e| plan9 FCVTZS $25, F30, R20
+538d189e| plan9 FCVTZS $29, F10, R19
+7e74589e| plan9 FCVTZS $35, F3, R30
+4300381e| plan9 FCVTZSSW F2, R3
+bc03389e| plan9 FCVTZSS F29, R28
+c702781e| plan9 FCVTZSDW F22, R7
+0401789e| plan9 FCVTZSD F8, R4
+d1ff2e7f| plan9 FCVTZU $18, F30, F17
+d0fd3b2f| plan9 FCVTZU $5, V14.S2, V16.S2
+70bae17e| plan9 FCVTZUDD F19, F16
+3ef6191e| plan9 FCVTZU $3, F17, R30
+cae7199e| plan9 FCVTZU $7, F30, R10
+cffb599e| plan9 FCVTZU $2, F30, R15
+e402391e| plan9 FCVTZUSW F23, R4
+1a03399e| plan9 FCVTZUS F24, R26
+0401791e| plan9 FCVTZUDW F8, R4
+c200799e| plan9 FCVTZUD F6, R2
+ebfe346e| plan9 FDIV V20.S4, V23.S4, V11.S4
+c918371e| plan9 FDIVS F23, F6, F9
+911a7f1e| plan9 FDIVD F31, F20, F17
+a81f0c1f| plan9 FMADD F7, F12, F29, F8
+d0404a1f| plan9 FMADD F16, F10, F6, F16
+7ff6324e| plan9 FMAX V18.S4, V19.S4, V31.S4
+b84b351e| plan9 FMAXS F21, F29, F24
+d64b621e| plan9 FMAXD F2, F30, F22
+016b241e| plan9 FMAXNMS F4, F24, F1
+5b69781e| plan9 FMAXNMD F24, F10, F27
+f1c8707e| plan9 FMAXNMP V7.D2, F17
+27c5306e| plan9 VFMAXNMP V16.S4, V9.S4, V7.S4
+aef8707e| plan9 FMAXP V5.D2, F14
+53f6202e| plan9 VFMAXP V0.S2, V18.S2, V19.S2
+78fb306e| plan9 FMAXV V27.S4, F24
+5af4ec4e| plan9 FMIN V12.D2, V2.D2, V26.D2
+505a3c1e| plan9 FMINS F28, F18, F16
+4858661e| plan9 FMIND F6, F2, F8
+a9c6e04e| plan9 FMINNM V0.D2, V21.D2, V9.D2
+987b311e| plan9 FMINNMS F17, F28, F24
+95796f1e| plan9 FMINNMD F15, F12, F21
+f5cbb07e| plan9 FMINNMP V31.S2, F21
+b0f8f07e| plan9 FMINP V5.D2, F16
+8bf5a42e| plan9 VFMINP V4.S2, V12.S2, V11.S2
+87cd384e| plan9 VFMLA V24.S4, V12.S4, V7.S4
+fd50db5f| plan9 FMLS V27.D[0], F7, F29
+d1ccb44e| plan9 VFMLS V20.S4, V6.S4, V17.S4
+ebf5064f| plan9 FMOV $-0.242188, V11.S4
+49f4056f| plan9 FMOV $-9., V9.D2
+0940201e| plan9 FMOVS F0, F9
+db43601e| plan9 FMOVD F30, F27
+a901271e| plan9 FMOVS R13, F9
+3702261e| plan9 FMOVS F17, R23
+4d02679e| plan9 FMOVD R18, F13
+9d02af9e| plan9 FMOV R20, V29.D[1]
+ef03669e| plan9 FMOVD F31, R15
+7101ae9e| plan9 FMOV V11.D[1], R17
+0e103d1e| plan9 FMOVS $-0.75, F14
+1e50761e| plan9 FMOVD $-18., F30
+d2b4121f| plan9 FMSUB F13, F18, F6, F18
+0a9c4c1f| plan9 FMSUB F7, F12, F0, F10
+0d99b35f| plan9 FMULS V19.S[3], F8, F13
+a89b9b0f| plan9 FMUL V27.S[2], V29.S2, V8.S2
+75dc376e| plan9 FMUL V23.S4, V3.S4, V21.S4
+7909241e| plan9 FMULS F4, F11, F25
+d7096b1e| plan9 FMULD F11, F14, F23
+2999ab7f| plan9 FMULX V11.S[3], F9, F9
+35dd6d5e| plan9 FMULX F13, F9, F21
+c8dc284e| plan9 VFMULX V8.S4, V6.S4, V8.S4
+c043211e| plan9 FNEGS F30, F0
+4742611e| plan9 FNEGD F18, F7
+9c51251f| plan9 FNMADD F20, F5, F12, F28
+e407771f| plan9 FNMADD F1, F23, F31, F4
+fbfa3a1f| plan9 FNMSUB F30, F26, F23, F27
+bbb0691f| plan9 FNMSUB F12, F9, F5, F27
+6a8b3f1e| plan9 FNMULS F31, F27, F10
+1a8b751e| plan9 FNMULD F21, F24, F26
+57d8e15e| plan9 FRECPE F2, F23
+62dba14e| plan9 VFRECPE V27.S4, V2.S4
+81fd325e| plan9 FRECPS F18, F12, F1
+31fe224e| plan9 VFRECPS V2.S4, V17.S4, V17.S4
+ecf9e15e| plan9 FRECPX F15, F12
+c18b216e| plan9 FRINTA V30.S4, V1.S4
+0240261e| plan9 FRINTAS F0, F2
+8041661e| plan9 FRINTAD F12, F0
+c89ba12e| plan9 FRINTI V30.S2, V8.S2
+2ec2271e| plan9 FRINTIS F17, F14
+5cc0671e| plan9 FRINTID F2, F28
+3898210e| plan9 FRINTM V1.S2, V24.S2
+9843251e| plan9 FRINTMS F28, F24
+5b40651e| plan9 FRINTMD F2, F27
+2189614e| plan9 FRINTN V9.D2, V1.D2
+7e42241e| plan9 FRINTNS F19, F30
+5d40641e| plan9 FRINTND F2, F29
+85c3241e| plan9 FRINTPS F28, F5
+46c2641e| plan9 FRINTPD F18, F6
+c39b216e| plan9 FRINTX V30.S4, V3.S4
+a243271e| plan9 FRINTXS F29, F2
+1d41671e| plan9 FRINTXD F8, F29
+5499e14e| plan9 FRINTZ V10.D2, V20.D2
+92c2251e| plan9 FRINTZS F20, F18
+75c2651e| plan9 FRINTZD F19, F21
+ddd9e17e| plan9 FRSQRTE F14, F29
+60fff85e| plan9 FRSQRTS F24, F27, F0
+dafffb4e| plan9 VFRSQRTS V27.D2, V30.D2, V26.D2
+1ff9a12e| plan9 FSQRT V8.S2, V31.S2
+2dc3211e| plan9 FSQRTS F25, F13
+72c0611e| plan9 FSQRTD F3, F18
+7d3a3e1e| plan9 FSUBS F30, F19, F29
+3f38771e| plan9 FSUBD F23, F1, F31
+185e016e| plan9 VMOV V16.B[11], V24.B[0]
+911d0d4e| plan9 VMOV R12, V17.B[6]
+2877400c| plan9 VLD1 (R25), [V8.H4]
+8ea8404c| plan9 VLD1 (R4), [V14.S4, V15.S4]
+0f62404c| plan9 VLD1 (R16), [V15.B16, V16.B16, V17.B16]
+0f27400c| plan9 VLD1 (R24), [V15.H4, V16.H4, V17.H4, V18.H4]
+4c75df0c| plan9 VLD1.P 8(R10), [V12.H4]
+2f7bd04c| plan9 VLD1.P (R25)(R16), [V15.S4]
+eaaadf0c| plan9 VLD1.P 16(R23), [V10.S2, V11.S2]
+eca7cc4c| plan9 VLD1.P (RSP)(R12), [V12.H8, V13.H8]
+cd60df4c| plan9 VLD1.P 48(R6), [V13.B16, V14.B16, V15.B16]
+9163df0c| plan9 VLD1.P 24(R28), [V17.B8, V18.B8, V19.B8]
+152ddf4c| plan9 VLD1.P 64(R8), [V21.D2, V22.D2, V23.D2, V24.D2]
+0725c04c| plan9 VLD1.P (R8)(R0), [V7.H8, V8.H8, V9.H8, V10.H8]
+7c04404d| plan9 LD1 (R3), [V28.B][9]
+6d49404d| plan9 LD1 (R11), [V13.H][5]
+9e81400d| plan9 LD1 (R12), [V30.S][0]
+d384404d| plan9 LD1 (R6), [V19.D][1]
+b20ddf4d| plan9 LD1.P 1(R13), [V18.B][11]
+f114cd4d| plan9 LD1.P (R7)(R13), [V17.B][13]
+bb92df4d| plan9 LD1.P 4(R21), [V27.S][3]
+a883d64d| plan9 LD1.P (R29)(R22), [V8.S][2]
+f584df4d| plan9 LD1.P 8(R7), [V21.D][1]
+0284c80d| plan9 LD1.P (R0)(R8), [V2.D][0]
+91c3400d| plan9 VLD1R (R28), [V17.B8]
+71c9df0d| plan9 VLD1R 4(R11), [V17.S2]
+e7c4db0d| plan9 VLD1R (R7)(R27), [V7.H4]
+b787404c| plan9 VLD2 (R29), [V23.H8, V24.H8]
+1280df0c| plan9 VLD2 16(R0), [V18.B8, V19.B8]
+2f88c10c| plan9 VLD2 (R1)(R1), [V15.S2, V16.S2]
+a01e604d| plan9 LD2 (R21), [V0.B, V1.B][15]
+eb82604d| plan9 LD2 (R23), [V11.S, V12.S][2]
+f985600d| plan9 LD2 (R15), [V25.D, V26.D][0]
+e315ff0d| plan9 LD2 2(R15), [V3.B, V4.B][5]
+1c11f24d| plan9 LD2 (R8)(R18), [V28.B, V29.B][12]
+f341ef4d| plan9 LD2 (R15)(R15), [V19.H, V20.H][4]
+5a80ff4d| plan9 LD2 8(R2), [V26.S, V27.S][2]
+d781fd0d| plan9 LD2 (R14)(R29), [V23.S, V24.S][0]
+c885ff0d| plan9 LD2 16(R14), [V8.D, V9.D][0]
+1286f34d| plan9 LD2 (R16)(R19), [V18.D, V19.D][1]
+06c2600d| plan9 VLD2R (R16), [V6.B8, V7.B8]
+95c7ff4d| plan9 VLD2R 4(R28), [V21.H8, V22.H8]
+d4c1e14d| plan9 VLD2R (R14)(R1), [V20.B16, V21.B16]
+eb4bdf4c| plan9 VLD3 48(RSP), [V11.S4, V12.S4, V13.S4]
+ce4fc24c| plan9 VLD3 (R30)(R2), [V14.D2, V15.D2, V16.D2]
+db23400d| plan9 LD3 (R30), [V27.B, V28.B, V29.B][0]
+26b3400d| plan9 LD3 (R25), [V6.S, V7.S, V8.S][1]
+37a4400d| plan9 LD3 (R1), [V23.D, V24.D, V25.D][0]
+052edf4d| plan9 LD3 3(R16), [V5.B, V6.B, V7.B][11]
+8c3ccd0d| plan9 LD3 (R4)(R13), [V12.B, V13.B, V14.B][7]
+74b0df4d| plan9 LD3 12(R3), [V20.S, V21.S, V22.S][3]
+b7b1c84d| plan9 LD3 (R13)(R8), [V23.S, V24.S, V25.S][3]
+e6a5df4d| plan9 LD3 24(R15), [V6.D, V7.D, V8.D][1]
+42a5c80d| plan9 LD3 (R10)(R8), [V2.D, V3.D, V4.D][0]
+9ceb400d| plan9 VLD3R (R28), [V28.S2, V29.S2, V30.S2]
+6aeadf4d| plan9 VLD3R 12(R19), [V10.S4, V11.S4, V12.S4]
+65ebce4d| plan9 VLD3R (R27)(R14), [V5.S4, V6.S4, V7.S4]
+ea05400c| plan9 VLD4 (R15), [V10.H4, V11.H4, V12.H4, V13.H4]
+1f03df0c| plan9 VLD4 32(R24), [V31.B8, V0.B8, V1.B8, V2.B8]
+ae09c90c| plan9 VLD4 (R13)(R9), [V14.S2, V15.S2, V16.S2, V17.S2]
+fd3a604d| plan9 LD4 (R23), [V29.B, V30.B, V31.B, V0.B][14]
+d8a0604d| plan9 LD4 (R6), [V24.S, V25.S, V26.S, V27.S][2]
+62a4604d| plan9 LD4 (R3), [V2.D, V3.D, V4.D, V5.D][1]
+712fff0d| plan9 LD4 4(R27), [V17.B, V18.B, V19.B, V20.B][3]
+aa27f40d| plan9 LD4 (R29)(R20), [V10.B, V11.B, V12.B, V13.B][1]
+be71ff4d| plan9 LD4 8(R13), [V30.H, V31.H, V0.H, V1.H][6]
+e360ee4d| plan9 LD4 (R7)(R14), [V3.H, V4.H, V5.H, V6.H][4]
+c0a0ff0d| plan9 LD4 16(R6), [V0.S, V1.S, V2.S, V3.S][0]
+d3a3e00d| plan9 LD4 (R30)(R0), [V19.S, V20.S, V21.S, V22.S][0]
+95a7ff0d| plan9 LD4 32(R28), [V21.D, V22.D, V23.D, V24.D][0]
+32a6e14d| plan9 LD4 (R17)(R1), [V18.D, V19.D, V20.D, V21.D][1]
+56e0604d| plan9 VLD4R (R2), [V22.B16, V23.B16, V24.B16, V25.B16]
+dce7ff0d| plan9 VLD4R 8(R30), [V28.H4, V29.H4, V30.H4, V31.H4]
+14e8ef0d| plan9 VLD4R (R0)(R15), [V20.S2, V21.S2, V22.S2, V23.S2]
+7776732c| plan9 LDNP -104(R19), F29, F23
+23dd746c| plan9 LDNP -184(R9), F23, F3
+383e48ac| plan9 LDNP 256(R17), V15, V24
+0d10c12c| plan9 LDP.P 8(R0), (F13, F4)
+fe3ae66c| plan9 LDP.P -416(R23), (F30, F14)
+f627f9ac| plan9 LDP.P -224(RSP), (V22, V9)
+918cd82d| plan9 LDP.W 196(R4), (F17, F3)
+986be46d| plan9 LDP.W -448(R28), (F24, F26)
+ebd8f8ad| plan9 LDP.W -240(R7), (V11, V22)
+3c905c2d| plan9 LDP 228(R1), (F28, F4)
+5887536d| plan9 LDP 312(R26), (F24, F1)
+08957cad| plan9 LDP -112(R8), (V8, V5)
+c5e5543c| plan9 MOVD.P -178(R14), F5
+4ff5417c| plan9 MOVD.P 31(R10), F15
+72e54bbc| plan9 MOVD.P 190(R11), F18
+16b55dfc| plan9 MOVD.P -37(R8), F22
+9e24db3c| plan9 MOVD.P -78(R4), V30
+d20c503c| plan9 MOVD.W -256(R6), F18
+1f1c4d7c| plan9 MOVD.W 209(R0), F31
+2fbf4dbc| plan9 MOVD.W 219(R25), F15
+a06c59fc| plan9 MOVD.W -106(R5), F0
+886ddd3c| plan9 MOVD.W -42(R12), V8
+58f64e3d| plan9 MOVD 957(R18), F24
+f5c3547d| plan9 MOVD 2656(RSP), F21
+8e8a7bbd| plan9 MOVD 15240(R20), F14
+8e3c7afd| plan9 MOVD 29816(R4), F14
+f2aeff3d| plan9 MOVD 65200(R23), V18
+1d78793c| plan9 MOVD R25<<1(R0), F29
+b8f15d3c| plan9 LDUR -33(R13), F24
+95635c7c| plan9 LDUR -58(R28), F21
+27d046bc| plan9 LDUR 109(R1), F7
+21624efc| plan9 LDUR 230(R17), F1
+6dd2d83c| plan9 LDUR -115(R19), V13
+dc09be6f| plan9 VMLA V30.S[3], V14.S4, V28.S4
+eb97af4e| plan9 VMLA V15.S4, V31.S4, V11.S4
+0495722e| plan9 VMLS V18.H4, V8.H4, V4.H4
+21070a5e| plan9 VMOV V25.H[2], F1
+92471b6e| plan9 VMOV V28.B[8], V18.B[13]
+7a1e134e| plan9 VMOV R19, V26.B[9]
+761fa30e| plan9 VORR V3.B8, V27.B8, V22.B8
+f23d070e| plan9 UMOVW V15.B[3], R18
+a5e6064f| plan9 VMOVI $213, V5.B16
+63c5064f| plan9 VMOVI $(203<<136), V3.S4
+bca7014f| plan9 VMOVI $(61<<8), V28.H8
+95e4040f| plan9 VMOVI $132, V21.B8
+fce4072f| plan9 MOVI $-1099494850561, F28
+24e6036f| plan9 VMOVI $72057589742960895, V4.D2
+429d6a4e| plan9 VMUL V10.H8, V10.H8, V2.H8
+e558202e| plan9 VMVN V7.B8, V5.B8
+fe65012f| plan9 VMVNI $(47<<24), V30.S2
+2b16046f| plan9 VBIC $145, V11.S4
+7756016f| plan9 VBIC $(51<<16), V23.S4
+e159202e| plan9 VMVN V15.B8, V1.B8
+da1cf14e| plan9 VORN V17.B16, V6.B16, V26.B16
+ca04014f| plan9 VMOVI $38, V10.S4
+14a6020f| plan9 VMOVI $(80<<8), V20.H4
+2f1fbf0e| plan9 VORR V31.B8, V25.B8, V15.B8
+74e2f20e| plan9 VPMULL V18.D1, V19.D1, V20.Q1
+2740262e| plan9 VRADDHN V6.H8, V1.H8, V7.B8
+17412e6e| plan9 VRADDHN2 V14.H8, V8.H8, V23.B16
+da59602e| plan9 VRBIT V14.B8, V26.B8
+230a604e| plan9 VREV64 V17.H8, V3.H8
+178d210f| plan9 VRSHRN $31, V8.D2, V23.S2
+6b8d2c4f| plan9 VRSHRN2 $20, V11.D2, V11.S4
+b57c2a0e| plan9 VSABA V10.B8, V5.B8, V21.B8
+71533d0e| plan9 VSABAL V29.B8, V27.B8, V17.H8
+1c50774e| plan9 VSABAL2 V23.H8, V0.H8, V28.S4
+1974be4e| plan9 VSABD V30.S4, V0.S4, V25.S4
+6b71ad0e| plan9 VSABDL V13.S2, V11.S2, V11.D2
+5270324e| plan9 VSABDL2 V18.B16, V2.B16, V18.H8
+366b200e| plan9 VSADALP V25.B8, V22.H4
+1802680e| plan9 VSADDL V8.H4, V16.H4, V24.S4
+022b604e| plan9 VSADDLP V24.H8, V2.S4
+413ab04e| plan9 SADDLV V18.S4, F1
+4013750e| plan9 VSADDW V21.H4, V26.S4, V0.S4
+4412744e| plan9 VSADDW2 V20.H8, V18.S4, V4.S4
+2ee6255f| plan9 SCVTF $27, F17, F14
+dce75f4f| plan9 SCVTF $33, V30.D2, V28.D2
+5bdb615e| plan9 SCVTFDD F26, F27
+3ad9210e| plan9 SCVTF V9.S2, V26.S2
+1ceb421e| plan9 SCVTF $6, R24, F28
+9dde029e| plan9 SCVTF $9, R20, F29
+57d1429e| plan9 SCVTF $12, R10, F23
+d600221e| plan9 SCVTFWS R6, F22
+c503621e| plan9 SCVTFWD R30, F5
+3303229e| plan9 SCVTFS R25, F19
+0003629e| plan9 SCVTFD R24, F0
+6f01075e| plan9 SHA1C V7.S4, F11, V15
+9308285e| plan9 SHA1H F4, F19
+b420105e| plan9 SHA1M V16.S4, F5, V20
+f4131f5e| plan9 SHA1P V31.S4, F31, V20
+dc311f5e| plan9 VSHA1SU0 V31.S4, V14.S4, V28.S4
+bb1a285e| plan9 VSHA1SU1 V21.S4, V27.S4
+2753075e| plan9 SHA256H2 V7.S4, V25, V7
+3141065e| plan9 SHA256H V6.S4, V9, V17
+172b285e| plan9 VSHA256SU0 V24.S4, V23.S4
+bb621b5e| plan9 VSHA256SU1 V27.S4, V21.S4, V27.S4
+7005644e| plan9 VSHADD V4.H8, V11.H8, V16.H8
+2d870e0f| plan9 VSHRN $2, V25.H8, V13.B8
+ac86024f| plan9 VMOVI $85, V12.H8
+1c26a50e| plan9 VSHSUB V5.S2, V16.S2, V28.S2
+db576b6f| plan9 VSLI $43, V30.D2, V27.D2
+c3652c4e| plan9 VSMAX V12.B16, V14.B16, V3.B16
+b5a7ab0e| plan9 VSMAXP V11.S2, V29.S2, V21.S2
+f1aeb34e| plan9 VSMINP V19.S4, V23.S4, V17.S4
+87a8b14e| plan9 SMINV V4.S4, F7
+1e21bc4f| plan9 VSMLAL2 V28.S[1], V8.S4, V30.D2
+50a33a0e| plan9 VSMLSL V26.B8, V26.B8, V16.H8
+4e2d1a0e| plan9 SMOVW V10.H[6], R14
+9ba9b30f| plan9 VSMULL V19.S[3], V12.S2, V27.D2
+417a205e| plan9 SQABS F18, F1
+9f78a04e| plan9 VSQABS V4.S4, V31.S4
+580d2e5e| plan9 SQADD F14, F10, F24
+3d30764f| plan9 VSQDMLAL2 V6.H[3], V1.H8, V29.S4
+9591b25e| plan9 SQDMLAL F18, F12, F21
+0d92670e| plan9 VSQDMLAL V7.H4, V16.H4, V13.S4
+90b1765e| plan9 SQDMLSL F22, F12, F16
+83c2ad5f| plan9 SQDMULH V13.S[1], F20, F3
+bbb7aa5e| plan9 SQDMULH F10, F29, F27
+c8b99a5f| plan9 SQDMULL V26.S[2], F14, F8
+75b3920f| plan9 VSQDMULL V18.S[0], V27.S2, V21.D2
+86d1b75e| plan9 SQDMULL F23, F12, F6
+edd06f4e| plan9 VSQDMULL2 V15.H8, V7.H8, V13.S4
+0f7ae07e| plan9 SQNEG F16, F15
+e87b602e| plan9 VSQNEG V31.H4, V8.H4
+ecb5a92e| plan9 VSQRDMULH V9.S2, V15.S2, V12.S2
+d75fba5e| plan9 SQRSHL F26, F30, F23
+f75f324e| plan9 VSQRSHL V18.B16, V31.B16, V23.B16
+af9c114f| plan9 VSQRSHRN2 $15, V5.S4, V15.H8
+318d2f6f| plan9 VSQRSHRUN2 $17, V9.D2, V17.S4
+b3757c5f| plan9 SQSHL $60, F13, F19
+0c776f4f| plan9 VSQSHL $47, V24.D2, V12.D2
+d84c2a5e| plan9 SQSHL F10, F6, F24
+ae4e704e| plan9 VSQSHL V16.H8, V21.H8, V14.H8
+b566727f| plan9 SQSHLU $50, F21, F21
+4566596f| plan9 VSQSHLU $25, V18.D2, V5.D2
+d595140f| plan9 VSQSHRN $12, V14.S4, V21.H4
+00940b4f| plan9 VSQSHRN2 $5, V0.H8, V0.B16
+5384352f| plan9 VSQSHRUN $11, V2.D2, V19.S2
+1a2e3d5e| plan9 SQSUB F29, F16, F26
+b02e6b4e| plan9 VSQSUB V11.H8, V21.H8, V16.H8
+1249a15e| plan9 SQXTN F8, F18
+eb49610e| plan9 VSQXTN V15.S4, V11.H4
+cb4a614e| plan9 VSQXTN2 V22.S4, V11.H8
+102b217e| plan9 SQXTUN F24, F16
+492a212e| plan9 VSQXTUN V18.H8, V9.B8
+112a616e| plan9 VSQXTUN2 V16.S4, V17.H8
+6c16ae4e| plan9 VSRHADD V14.S4, V19.S4, V12.S4
+5946467f| plan9 SRI $58, F18, F25
+21460a2f| plan9 VSRI $6, V17.B8, V1.B8
+9f56b10e| plan9 VSRSHL V17.S2, V20.S2, V31.S2
+e724635f| plan9 SRSHR $29, F7, F7
+e8266b4f| plan9 VSRSHR $21, V23.D2, V8.D2
+2b37180f| plan9 VSRSRA $8, V25.H4, V11.H4
+1644f95e| plan9 SSHL F25, F0, F22
+3644fc4e| plan9 VSSHL V28.D2, V1.D2, V22.D2
+d9a61f4f| plan9 VSSHLL2 $15, V22.H8, V25.S4
+9b075e5f| plan9 SSHR $34, F28, F27
+2c044c4f| plan9 VSSHR $52, V1.D2, V12.D2
+d915324f| plan9 VSSRA $14, V14.S4, V25.S4
+de21260e| plan9 VSSUBL V6.B8, V14.B8, V30.H8
+c720254e| plan9 VSSUBL2 V5.B16, V6.B16, V7.H8
+9d33b90e| plan9 VSSUBW V25.S2, V28.D2, V29.D2
+7e71000c| plan9 VST1 (R11), [V30.B8]
+cca6000c| plan9 VST1 (R22), [V12.H4, V13.H4]
+5467000c| plan9 VST1 (R26), [V20.H4, V21.H4, V22.H4]
+cc28004c| plan9 VST1 (R6), [V12.S4, V13.S4, V14.S4, V15.S4]
+9e7e9f4c| plan9 VST1 16(R20), [V30.D2]
+4b769d0c| plan9 VST1 (R18)(R29), [V11.H4]
+adaa9f0c| plan9 VST1 16(R21), [V13.S2, V14.S2]
+bca7844c| plan9 VST1 (R29)(R4), [V28.H8, V29.H8]
+b5659f0c| plan9 VST1 24(R13), [V21.H4, V22.H4, V23.H4]
+e669874c| plan9 VST1 (R15)(R7), [V6.S4, V7.S4, V8.S4]
+9b2a9f0c| plan9 VST1 32(R20), [V27.S2, V28.S2, V29.S2, V30.S2]
+14278b0c| plan9 VST1 (R24)(R11), [V20.H4, V21.H4, V22.H4, V23.H4]
+d002004d| plan9 ST1 (R22), [V16.B][8]
+9780004d| plan9 ST1 (R4), [V23.S][2]
+7787004d| plan9 ST1 (R27), [V23.D][1]
+850d9f0d| plan9 ST1 1(R12), [V5.B][3]
+7b1f8f0d| plan9 ST1 (R27)(R15), [V27.B][7]
+7a5a9f4d| plan9 ST1 2(R19), [V26.H][7]
+e14b9e4d| plan9 ST1 (RSP)(R30), [V1.H][5]
+dd819f4d| plan9 ST1 4(R14), [V29.S][2]
+a281910d| plan9 ST1 (R13)(R17), [V2.S][0]
+b2849f0d| plan9 ST1 8(R5), [V18.D][0]
+c484964d| plan9 ST1 (R6)(R22), [V4.D][1]
+f686004c| plan9 VST2 (R23), [V22.H8, V23.H8]
+2e869f0c| plan9 VST2 16(R17), [V14.H4, V15.H4]
+d200200d| plan9 ST2 (R6), [V18.B, V19.B][0]
+ab58200d| plan9 ST2 (R5), [V11.H, V12.H][3]
+c491204d| plan9 ST2 (R14), [V4.S, V5.S][3]
+5a85204d| plan9 ST2 (R10), [V26.D, V27.D][1]
+f217bf0d| plan9 ST2 2(RSP), [V18.B, V19.B][5]
+2b0ea04d| plan9 ST2 (R17)(R0), [V11.B, V12.B][11]
+4042bf0d| plan9 ST2 4(R18), [V0.H, V1.H][0]
+9342af4d| plan9 ST2 (R20)(R15), [V19.H, V20.H][4]
+9b91bf4d| plan9 ST2 8(R12), [V27.S, V28.S][3]
+7480a10d| plan9 ST2 (R3)(R1), [V20.S, V21.S][0]
+c884bf0d| plan9 ST2 16(R6), [V8.D, V9.D][0]
+ae86ac4d| plan9 ST2 (R21)(R12), [V14.D, V15.D][1]
+614d004c| plan9 VST3 (R11), [V1.D2, V2.D2, V3.D2]
+324b9f4c| plan9 VST3 48(R25), [V18.S4, V19.S4, V20.S4]
+7340870c| plan9 VST3 (R3)(R7), [V19.B8, V20.B8, V21.B8]
+ac24004d| plan9 ST3 (R5), [V12.B, V13.B, V14.B][9]
+a161004d| plan9 ST3 (R13), [V1.H, V2.H, V3.H][4]
+09b1004d| plan9 ST3 (R8), [V9.S, V10.S, V11.S][3]
+78a7004d| plan9 ST3 (R27), [V24.D, V25.D, V26.D][1]
+4f349f0d| plan9 ST3 3(R2), [V15.B, V16.B, V17.B][5]
+643d840d| plan9 ST3 (R11)(R4), [V4.B, V5.B, V6.B][7]
+48699f0d| plan9 ST3 6(R10), [V8.H, V9.H, V10.H][1]
+85b19f4d| plan9 ST3 12(R12), [V5.S, V6.S, V7.S][3]
+60a18a0d| plan9 ST3 (R11)(R10), [V0.S, V1.S, V2.S][0]
+69a49f0d| plan9 ST3 24(R3), [V9.D, V10.D, V11.D][0]
+ada7814d| plan9 ST3 (R29)(R1), [V13.D, V14.D, V15.D][1]
+760c004c| plan9 VST4 (R3), [V22.D2, V23.D2, V24.D2, V25.D2]
+ee0d9f4c| plan9 VST4 64(R15), [V14.D2, V15.D2, V16.D2, V17.D2]
+7800970c| plan9 VST4 (R3)(R23), [V24.B8, V25.B8, V26.B8, V27.B8]
+a221200d| plan9 ST4 (R13), [V2.B, V3.B, V4.B, V5.B][0]
+9a69204d| plan9 ST4 (R12), [V26.H, V27.H, V28.H, V29.H][5]
+02a1204d| plan9 ST4 (R8), [V2.S, V3.S, V4.S, V5.S][2]
+3fa6200d| plan9 ST4 (R17), [V31.D, V0.D, V1.D, V2.D][0]
+943abf0d| plan9 ST4 4(R20), [V20.B, V21.B, V22.B, V23.B][6]
+bf26a60d| plan9 ST4 (R21)(R6), [V31.B, V0.B, V1.B, V2.B][1]
+55b3bf4d| plan9 ST4 16(R26), [V21.S, V22.S, V23.S, V24.S][3]
+dda1b04d| plan9 ST4 (R14)(R16), [V29.S, V30.S, V31.S, V0.S][2]
+6aa5bf0d| plan9 ST4 32(R11), [V10.D, V11.D, V12.D, V13.D][0]
+e7a7ac0d| plan9 ST4 (RSP)(R12), [V7.D, V8.D, V9.D, V10.D][0]
+f9c9202c| plan9 STNP -252(R15), F18, F25
+18b8316c| plan9 STNP -232(R0), F14, F24
+409c1cac| plan9 STNP 912(R2), V7, V0
+73f0812c| plan9 STP.P (F19, F28), 12(R3)
+28d0826c| plan9 STP.P (F8, F20), 40(R1)
+9bf5bfac| plan9 STP.P (V27, V29), -16(R12)
+885ead2d| plan9 STP.W (F8, F23), -152(R20)
+b0de926d| plan9 STP.W (F16, F23), 296(R21)
+713387ad| plan9 STP.W (V17, V12), 224(R27)
+52130a2d| plan9 STP (F18, F4), 80(R26)
+b63a236d| plan9 STP (F22, F14), -464(R21)
+6d5424ad| plan9 STP (V13, V21), -896(R3)
+afb60f3c| plan9 MOVD.P F15, 251(R21)
+81e7077c| plan9 MOVD.P F1, 126(R28)
+203713bc| plan9 MOVD.P F0, -205(R25)
+60c61ffc| plan9 MOVD.P F0, -4(R19)
+d256813c| plan9 MOVD.P V18, 21(R22)
+ffce083c| plan9 MOVD.W F31, 140(R23)
+6d3d017c| plan9 MOVD.W F13, 19(R11)
+52ed01bc| plan9 MOVD.W F18, 30(R10)
+fafd11fc| plan9 MOVD.W F26, -225(R15)
+663e9b3c| plan9 MOVD.W V6, -77(R19)
+7d0c393d| plan9 MOVD F29, 3651(R3)
+8f50067d| plan9 MOVD F15, 808(R4)
+94680dbd| plan9 MOVD F20, 3432(R4)
+b7673bfd| plan9 MOVD F23, 30408(R29)
+fed3a63d| plan9 MOVD V30, 39744(RSP)
+8a6a243c| plan9 MOVD F10, R4(R20)
+c768a93c| plan9 MOVD V7, R9(R6)
+a7b00a3c| plan9 MOVD F7, 171(R5)
+40e3107c| plan9 MOVD F0, -242(R26)
+18911fbc| plan9 MOVD F24, -7(R8)
+fcc007fc| plan9 MOVD F28, 124(R7)
+db12893c| plan9 MOVD V27, 145(R22)
+1686716e| plan9 VSUB V17.H8, V16.H8, V22.H8
+5362320e| plan9 VSUBHN V18.H8, V18.H8, V19.B8
+6163bf4e| plan9 VSUBHN2 V31.D2, V27.D2, V1.S4
+a73be05e| plan9 SUQADD F29, F7
+21a4100f| plan9 VSXTL V1.H4, V1.S4
+8b23164e| plan9 VTBL V22.B16, [V28.B16, V29.B16], V11.B16
+3642120e| plan9 VTBL V18.B8, [V17.B16, V18.B16, V19.B16], V22.B8
+cf611f0e| plan9 VTBL V31.B8, [V14.B16, V15.B16, V16.B16, V17.B16], V15.B8
+0b020e4e| plan9 VTBL V14.B16, [V16.B16], V11.B16
+9830014e| plan9 VTBX V1.B16, [V4.B16, V5.B16], V24.B16
+1452044e| plan9 VTBX V4.B16, [V16.B16, V17.B16, V18.B16], V20.B16
+b4711a0e| plan9 VTBX V26.B8, [V13.B16, V14.B16, V15.B16, V16.B16], V20.B8
+f911140e| plan9 VTBX V20.B8, [V15.B16], V25.B8
+9f28500e| plan9 VTRN1 V16.H4, V4.H4, V31.H4
+2e69c64e| plan9 VTRN2 V6.D2, V9.D2, V14.D2
+c752756e| plan9 VUABAL2 V21.H8, V22.H8, V7.S4
+8675696e| plan9 VUABD V9.H8, V12.H8, V6.H8
+a973ab6e| plan9 VUABDL2 V11.S4, V29.S4, V9.D2
+fa006c2e| plan9 VUADDL V12.H4, V7.H4, V26.S4
+da00236e| plan9 VUADDL2 V3.B16, V6.B16, V26.H8
+ab3a306e| plan9 UADDLV V21.B16, F11
+a312746e| plan9 VUADDW2 V20.H8, V21.S4, V3.S4
+cee55e7f| plan9 UCVTF $34, F14, F14
+8edb617e| plan9 UCVTFDD F28, F14
+ab8f431e| plan9 UCVTF $29, R29, F11
+68b3039e| plan9 UCVTF $20, R27, F8
+7686439e| plan9 UCVTF $31, R19, F22
+2a03231e| plan9 UCVTFWS R25, F10
+9f01631e| plan9 UCVTFWD R12, F31
+a800239e| plan9 UCVTFS R5, F8
+0302639e| plan9 UCVTFD R16, F3
+df65a42e| plan9 VUMAX V4.S2, V14.S2, V31.S2
+29ab702e| plan9 UMAXV V25.H4, F9
+6f6e2e6e| plan9 VUMIN V14.B16, V19.B16, V15.B16
+fdada32e| plan9 VUMINP V3.S2, V15.S2, V29.S2
+07289a6f| plan9 VUMLAL2 V26.S[2], V0.S4, V7.D2
+aa80ad2e| plan9 VUMLAL V13.S2, V5.S2, V10.D2
+d66b462f| plan9 VUMLSL V6.H[4], V30.H4, V22.S4
+12a3b62e| plan9 VUMLSL V22.S2, V24.S2, V18.D2
+583e0d0e| plan9 UMOVW V18.B[6], R24
+20c3b52e| plan9 VUMULL V21.S2, V25.S2, V0.D2
+20c2616e| plan9 VUMULL2 V1.H8, V17.H8, V0.S4
+2f0f6d7e| plan9 UQADD F13, F25, F15
+a60c272e| plan9 VUQADD V7.B8, V5.B8, V6.B8
+5b5da27e| plan9 UQRSHL F2, F10, F27
+195c786e| plan9 VUQRSHL V24.H8, V0.H8, V25.H8
+209e282f| plan9 VUQRSHRN $24, V17.D2, V0.S2
+e89e3b6f| plan9 VUQRSHRN2 $5, V23.D2, V8.S4
+4f75147f| plan9 UQSHL $4, F10, F15
+d2767d6f| plan9 VUQSHL $61, V22.D2, V18.D2
+bb4cfe7e| plan9 UQSHL F30, F5, F27
+794ea42e| plan9 VUQSHL V4.S2, V19.S2, V25.S2
+51960b7f| plan9 UQSHRN $5, F18, F17
+642ce77e| plan9 UQSUB F7, F3, F4
+6149617e| plan9 UQXTN F11, F1
+4e48a12e| plan9 VUQXTN V2.D2, V14.S2
+9cc8a14e| plan9 VURECPE V4.S4, V28.S4
+2f15a52e| plan9 VURHADD V5.S2, V9.S2, V15.S2
+5757fb7e| plan9 URSHL F27, F26, F23
+2756706e| plan9 VURSHL V16.H8, V17.H8, V7.H8
+a424487f| plan9 URSHR $56, F5, F4
+b926796f| plan9 VURSHR $7, V21.D2, V25.D2
+1336076f| plan9 VBIC $(240<<8), V19.S4
+e347e06e| plan9 VUSHL V0.D2, V31.D2, V3.D2
+f7a5272f| plan9 VUSHLL $7, V15.S2, V23.D2
+9ba63d6f| plan9 VUSHLL2 $29, V20.S4, V27.D2
+d405737f| plan9 USHR $13, F14, F20
+3a05116f| plan9 VUSHR $15, V9.H8, V26.H8
+1d39607e| plan9 USQADD F8, F29
+0e39e06e| plan9 VUSQADD V8.D2, V14.D2
+8022b02e| plan9 VUSUBL V16.S2, V20.S2, V0.D2
+9a20786e| plan9 VUSUBL2 V24.H8, V4.H8, V26.S4
+df33692e| plan9 VUSUBW V9.H4, V30.S4, V31.S4
+92a5102f| plan9 VUXTL V12.H4, V18.S4
+0e19464e| plan9 VUZP1 V6.H8, V8.H8, V14.H8
+7629610e| plan9 VXTN V11.S4, V22.H4
+7338504e| plan9 VZIP1 V16.H8, V3.H8, V19.H8
+357bd64e| plan9 VZIP2 V22.D2, V25.D2, V21.D2
+63020f1a| plan9 ADCW R15, R19, R3
+1f03159a| plan9 ADC R21, R24, ZR
+d300103a| plan9 ADCSW R16, R6, R19
+1b0010ba| plan9 ADCS R16, R0, R27
+dd133f0b| plan9 ADDW ZR.UXTB<<4, R30, R29
+89c42f8b| plan9 ADD R15.SXTW<<1, R4, R9
+4e242a11| plan9 ADDW $2697, R2, R14
+e1c12f2b| plan9 ADDSW R15.SXTW, R15, R1
+733421ab| plan9 ADDS R1.UXTH<<5, R3, R19
+0ccc5aab| plan9 ADDS R26>>51, R0, R12
+2e122612| plan9 ANDW $2080374784, R17, R14
+5e4c2992| plan9 AND $-36020000934328321, R2, R30
+2805410a| plan9 ANDW R1>>1, R9, R8
+ede1938a| plan9 AND R19->56, R15, R13
+e7c10f72| plan9 ANDSW $33686018, R15, R7
+23ed55f2| plan9 ANDS $-8246337208321, R9, R3
+e6935bea| plan9 ANDS R27>>36, ZR, R6
+0e2ac61a| plan9 ASRW R6, R16, R14
+802ad59a| plan9 ASR R21, R20, R0
+7cfd7793| plan9 ASR $55, R11, R28
+f028cd1a| plan9 ASRW R13, R7, R16
+132bd29a| plan9 ASR R18, R24, R19
+c2560e54| plan9 BCS 29366(PC)
+83516b17| plan9 JMP -9743997(PC)
+7a571233| plan9 BFXILW $18, R27, $4, R26
+71b858b3| plan9 BFXIL $24, R3, $23, R17
+c3964bb3| plan9 BFXIL $11, R22, $27, R3
+eb561233| plan9 BFXILW $18, R23, $4, R11
+063f5db3| plan9 BFI $35, R24, $16, R6
+0a337a0a| plan9 BICW R26>>12, R24, R10
+2a71e28a| plan9 BIC R2@>28, R9, R10
+c168bf6a| plan9 BICSW ZR->26, R6, R1
+d8bb3cea| plan9 BICS R28<<46, R30, R24
+82e81795| plan9 CALL 18344066(PC)
+40033fd6| plan9 CALL (R26)
+c0011fd6| plan9 JMP (R14)
+00dd31d4| plan9 BRK $36584
+a6cb563a| plan9 CCMNW GT, R29, $22, $6
+87db55ba| plan9 CCMN LE, R28, $21, $7
+a042493a| plan9 CCMNW MI, R21, R9, $0
+6a0040ba| plan9 CCMN EQ, R3, R0, $10
+46bb5c7a| plan9 CCMPW LT, R26, $28, $6
+c72942fa| plan9 CCMP HS, R14, $2, $7
+cda1427a| plan9 CCMPW GE, R14, R2, $13
+a1314dfa| plan9 CCMP LO, R13, R13, $1
+8706931a| plan9 CSINCW EQ, R20, R19, R7
+3ae69a9a| plan9 CSINC AL, R17, R26, R26
+9e51945a| plan9 CSINVW PL, R12, R20, R30
+d5e386da| plan9 CSINV AL, R30, R6, R21
+5f3503d5| plan9 CLREX $5
+e515c05a| plan9 CLSW R15, R5
+a815c0da| plan9 CLS R13, R8
+4a12c05a| plan9 CLZW R18, R10
+3c10c0da| plan9 CLZ R1, R28
+ff70252b| plan9 CMNW R5.UXTX<<4, R7
+9fa133ab| plan9 CMN R19.SXTH, R12
+3f3a822b| plan9 CMNW R2->14, R17
+df1d44ab| plan9 CMN R4>>7, R14
+3f95386b| plan9 CMPW R24.SXTB<<5, R9
+9f653feb| plan9 CMP ZR.UXTX<<1, R12
+1626915a| plan9 CSNEGW HS, R16, R17, R22
+b4d587da| plan9 CSNEG LE, R13, R7, R20
+9841d41a| plan9 CRC32B R20, R12, R24
+ec45d01a| plan9 CRC32H R16, R15, R12
+8048ca1a| plan9 CRC32W R10, R4, R0
+d44ec19a| plan9 CRC32X R1, R22, R20
+1552d31a| plan9 CRC32CB R19, R16, R21
+4b54c71a| plan9 CRC32CH R7, R2, R11
+245ad41a| plan9 CRC32CW R20, R17, R4
+c35cc89a| plan9 CRC32CX R8, R6, R3
+14219f1a| plan9 CSELW HS, R8, ZR, R20
+9c73979a| plan9 CSEL VC, R28, R23, R28
+e7279f1a| plan9 CSETW LO, R7
+ec579f9a| plan9 CSET MI, R12
+e5f39f5a| plan9 CSINVW AL, ZR, ZR, R5
+e8639fda| plan9 CSETM VC, R8
+ea76971a| plan9 CINCW VS, R23, R10
+78a7859a| plan9 CSINC GE, R27, R5, R24
+b590845a| plan9 CSINVW LS, R5, R4, R21
+b4029eda| plan9 CSINV EQ, R21, R30, R20
+b3969b5a| plan9 CSNEGW LS, R21, R27, R19
+938591da| plan9 CSNEG HI, R12, R17, R19
+016ea8d4| plan9 DCPS1 $17264
+0275a4d4| plan9 DCPS2 $9128
+a3e9a6d4| plan9 DCPS3 $14157
+bf3903d5| plan9 DMB $9
+e003bfd6| plan9 DRPS
+9f3e03d5| plan9 DSB $14
+50b1a0ca| plan9 EON R0->44, R10, R16
+c0b02f52| plan9 EORW $1073627134, R6, R0
+4b0c1ed2| plan9 EOR $257698037820, R2, R11
+693c074a| plan9 EORW R7<<15, R3, R9
+113e1aca| plan9 EOR R26<<15, R16, R17
+e0039fd6| plan9 ERET
+fef8c693| plan9 EXTR $62, R6, R7, R30
+3f2003d5| plan9 YIELD
+3f2403d5| plan9 HINT $33
+c0425ad4| plan9 HLT $53782
+df3003d5| plan9 ISB $0
+f7fddf88| plan9 LDARW (R15), R23
+96fedfc8| plan9 LDAR (R20), R22
+11fedf08| plan9 LDARB (R16), R17
+c2fedf48| plan9 LDARH (R22), R2
+2d927f88| plan9 LDAXPW (R17), R4, R13
+198f7fc8| plan9 LDAXP (R24), R3, R25
+46ff5f88| plan9 LDAXRW (R26), R6
+81fe5fc8| plan9 LDAXR (R20), R1
+86fe5f08| plan9 LDAXRB (R20), R6
+78ff5f48| plan9 LDAXRH (R27), R24
+35864a28| plan9 LDNPW 84(R17), R1, R21
+6da05fa8| plan9 LDNP 504(R3), R8, R13
+a8f9f428| plan9 LDP.P -92(R13), (R8, R30)
+b749e3a8| plan9 LDP.P -464(R13), (R23, R18)
+bdedd929| plan9 LDP.W 204(R13), (R29, R27)
+c8e5c6a9| plan9 LDP.W 104(R14), (R8, R25)
+c0857f29| plan9 LDP -4(R14), (R0, R1)
+388a6ca9| plan9 LDP -312(R17), (R24, R2)
+086be468| plan9 LDPSW -224(R24), R26, R8
+d107d269| plan9 LDPSW 144(R30), R1, R17
+738e4e69| plan9 LDPSW 116(R19), R3, R19
+6ee55fb8| plan9 MOVWU.P -2(R11), R14
+233459f8| plan9 MOVD.P -109(R1), R3
+919f44b8| plan9 MOVWU.W 73(R28), R17
+acdd45f8| plan9 MOVD.W 93(R13), R12
+e1cd51b9| plan9 MOVWU 4556(R15), R1
+95e27bf9| plan9 MOVD 30656(R20), R21
+0c554b38| plan9 MOVBU.P 181(R8), R12
+054f5938| plan9 MOVBU.W -108(R24), R5
+1f206539| plan9 MOVBU 2376(R0), ZR
+73796a38| plan9 MOVBU R10<<1(R11), R19
+a8b74f78| plan9 MOVHU.P 251(R29), R8
+021e5e78| plan9 MOVHU.W -31(R16), R2
+ec126b79| plan9 MOVHU 5512(R23), R12
+eaf6c238| plan9 MOVBW.P 47(R23), R10
+87679838| plan9 MOVB.P -122(R28), R7
+567fdb38| plan9 MOVBW.W -73(R26), R22
+3b2e8138| plan9 MOVB.W 18(R17), R27
+7d74c039| plan9 MOVBW 29(R3), R29
+7d1f8539| plan9 MOVB 327(R27), R29
+6a7bed38| plan9 MOVBW R13<<1(R27), R10
+0f69b538| plan9 MOVB R21(R8), R15
+c796cc78| plan9 MOVHW.P 201(R22), R7
+50268e78| plan9 MOVH.P 226(R18), R16
+229ddb78| plan9 MOVHW.W -71(R9), R2
+0f4f9178| plan9 MOVH.W -236(R24), R15
+59ecc379| plan9 MOVHW 502(R2), R25
+83d49679| plan9 MOVH 2922(R4), R3
+986be878| plan9 MOVHW R8(R28), R24
+6b4693b8| plan9 MOVW.P -204(R19), R11
+cb9e81b8| plan9 MOVW.W 25(R22), R11
+280d9eb9| plan9 MOVW 7692(R9), R8
+1a68b8b8| plan9 MOVW R24(R0), R26
+35b955b8| plan9 LDTRW -165(R9), R21
+658b57f8| plan9 LDTR -136(R27), R5
+b3594038| plan9 LDTRBW 5(R13), R19
+5ac95d78| plan9 LDTRHW -36(R10), R26
+2c3ade38| plan9 LDTRSBW -29(R17), R12
+4de99038| plan9 LDTRSB -242(R10), R13
+e178c378| plan9 LDTRSHW 55(R7), R1
+a77a8778| plan9 LDTRSH 119(R21), R7
+cde982b8| plan9 LDTRSW 46(R14), R13
+04d15bb8| plan9 LDURW -67(R8), R4
+02a256f8| plan9 LDUR -150(R16), R2
+97405438| plan9 LDURBW -188(R4), R23
+99b14b78| plan9 LDURHW 187(R12), R25
+f9a1cf38| plan9 LDURSBW 250(R15), R25
+c0218c38| plan9 LDURSB 194(R14), R0
+5790d278| plan9 LDURSHW -215(R2), R23
+a3808278| plan9 LDURSH 40(R5), R3
+a9b08fb8| plan9 LDURSW 251(R5), R9
+98217f88| plan9 LDXPW (R12), R8, R24
+4d6a7fc8| plan9 LDXP (R18), R26, R13
+9c7e5f88| plan9 LDXRW (R20), R28
+0e7c5fc8| plan9 LDXR (R0), R14
+507c5f08| plan9 LDXRB (R2), R16
+ea7f5f48| plan9 LDXRH (RSP), R10
+5523dd1a| plan9 LSLW R29, R26, R21
+9721ca9a| plan9 LSL R10, R12, R23
+75665bd3| plan9 UBFIZ $37, R19, $26, R21
+0a20df1a| plan9 LSLW ZR, R0, R10
+5222c99a| plan9 LSL R9, R18, R18
+5124df1a| plan9 LSRW ZR, R2, R17
+6b26d69a| plan9 LSR R22, R19, R11
+9a7c0753| plan9 LSRW $7, R4, R26
+7bfd53d3| plan9 LSR $19, R11, R27
+5f26d91a| plan9 LSRW R25, R18, ZR
+3625d89a| plan9 LSR R24, R9, R22
+9d76001b| plan9 MADDW R0, R29, R20, R29
+822f0e9b| plan9 MADD R14, R11, R28, R2
+e8fe101b| plan9 MNEGW R16, R23, R8
+88fc099b| plan9 MNEG R9, R4, R8
+dd030011| plan9 ADDW $0, R30, R29
+db010091| plan9 ADD $0, R14, R27
+0c6db012| plan9 MOVW $2090336255, R12
+3ff5aa92| plan9 MOVD $-1470693377, ZR
+87f0f6d2| plan9 MOVD $-5223049667842932736, R7
+f3571132| plan9 ORRW $4294934559, ZR, R19
+f3bb0bb2| plan9 MOVD $-4503668347895825, R19
+f103082a| plan9 MOVW R8, R17
+ef031faa| plan9 MOVD ZR, R15
+4a6bf5f2| plan9 MOVK $(43866<<48), R10
+383b9312| plan9 MOVW $4294927910, R24
+f5fb9092| plan9 MOVD $-34784, R21
+d5b4b052| plan9 MOVW $2242248704, R21
+fdc5eed2| plan9 MOVD $8516025420380897280, R29
+c58435d5| plan9 MRS $11302, R5
+1a0f13d5| plan9 MSR R26, $6264
+52d5181b| plan9 MSUBW R24, R21, R10, R18
+c4f81d9b| plan9 MSUB R29, R30, R6, R4
+a57c1b1b| plan9 MULW R27, R5, R5
+8f7f0a9b| plan9 MUL R10, R28, R15
+e75361aa| plan9 MVN R1>>20, R7
+e0cb15cb| plan9 NEG R21<<50, R0
+ffdb49eb| plan9 CMP R9>>54, ZR
+f5031c5a| plan9 NGCW R28, R21
+e6031eda| plan9 NGC R30, R6
+e103077a| plan9 NGCSW R7, R1
+f20301fa| plan9 NGCS R1, R18
+1f2003d5| plan9 NOP
+9347722a| plan9 ORNW R18>>17, R28, R19
+0591e1aa| plan9 ORN R1@>36, R8, R5
+7ba82a32| plan9 ORRW $4290904001, R3, R27
+ae087db2| plan9 ORR $56, R5, R14
+9608472a| plan9 ORRW R7>>2, R4, R22
+c40dc5aa| plan9 ORR R5@>3, R14, R4
+9d83bcf9| plan9 PRFM 30976(R28), #0X1D
+6e9186f8| plan9 PRFUM 105(R11), #0X0E
+c001c05a| plan9 RBITW R14, R0
+4203c0da| plan9 RBIT R26, R2
+c0035fd6| plan9 RET
+9b08c05a| plan9 REVW R4, R27
+740cc0da| plan9 REV R3, R20
+0205c05a| plan9 REV16W R8, R2
+dd07c0da| plan9 REV16 R30, R29
+020bc0da| plan9 REV32 R24, R2
+780cc0da| plan9 REV R3, R24
+9b7f9513| plan9 EXTRW $31, R21, R28, R27
+5243dd93| plan9 EXTR $16, R29, R26, R18
+822eca1a| plan9 RORW R10, R20, R2
+f02ddb9a| plan9 ROR R27, R15, R16
+082ed81a| plan9 RORW R24, R16, R8
+7b2cc39a| plan9 ROR R3, R3, R27
+3b030b5a| plan9 SBCW R11, R25, R27
+f2021dda| plan9 SBC R29, R23, R18
+e600127a| plan9 SBCSW R18, R7, R6
+cf030ffa| plan9 SBCS R15, R30, R15
+3a797793| plan9 SBFIZ $9, R9, $31, R26
+4a305193| plan9 SBFIZ $47, R2, $13, R10
+a1c74493| plan9 SBFX $4, R29, $46, R1
+a00fc01a| plan9 SDIVW R0, R29, R0
+f10edd9a| plan9 SDIV R29, R23, R17
+9f2003d5| plan9 SEV
+bf2003d5| plan9 SEVL
+a52d319b| plan9 SMADDL R17, R11, R13, R5
+b4fc399b| plan9 SMNEGL R25, R5, R20
+579e369b| plan9 SMSUBL R22, R7, R18, R23
+ea7e429b| plan9 SMULH R2, R23, R10
+eb7f219b| plan9 SMULL R1, ZR, R11
+f1fe9f88| plan9 STLRW R17, (R23)
+edff9fc8| plan9 STLR R13, (RSP)
+bffe9f08| plan9 STLRB ZR, (R21)
+9cfd9f48| plan9 STLRH R28, (R12)
+41bf2688| plan9 STLXPW (R26), R15, R1, R6
+01e93cc8| plan9 STLXPW (R8), R26, R1, R28
+e0fd1f88| plan9 STLXRW R0, (R15), ZR
+12fe17c8| plan9 STLXR R18, (R16), R23
+d4fc1008| plan9 STLXRB R20, (R6), R16
+befc0048| plan9 STLXRH R30, (R5), R0
+76613728| plan9 STNPW -72(R11), R24, R22
+c7523ba8| plan9 STNP -80(R22), R20, R7
+8e3a9f28| plan9 STP.P (R14, R14), 248(R20)
+aa1fa6a8| plan9 STP.P (R10, R7), -416(R29)
+fbae8d29| plan9 STP.W (R27, R11), 108(R23)
+f63c80a9| plan9 STP.W (R22, R15), (R7)
+43d73629| plan9 STP (R3, R21), -76(R26)
+1ae01ba9| plan9 STP (R26, R24), 440(R0)
+8f650cb8| plan9 MOVW.P R15, 198(R12)
+aad503f8| plan9 MOVD.P R10, 61(R13)
+ec4d00b8| plan9 MOVW.W R12, 4(R15)
+7dbc1df8| plan9 MOVD.W R29, -37(R3)
+9b0226b9| plan9 MOVW R27, 9728(R20)
+91691af9| plan9 MOVD R17, 13520(R12)
+20840838| plan9 MOVB.P R0, 136(R1)
+060c1f38| plan9 MOVB.W R6, -16(R0)
+2b213a39| plan9 MOVB R11, 3720(R9)
+ab6b3438| plan9 MOVB R11, R20(R29)
+50e51e78| plan9 MOVH.P R16, -18(R10)
+5d5d1878| plan9 MOVH.W R29, -123(R10)
+ea862379| plan9 MOVH R10, 4546(R23)
+d5ca12b8| plan9 STTRW -212(R22), R21
+001b18f8| plan9 STTR -127(R24), R0
+290a1e38| plan9 STTRBW -32(R17), R9
+0b381078| plan9 STTRHW -253(R0), R11
+c78101b8| plan9 MOVW R7, 24(R14)
+c0b217f8| plan9 MOVD R0, -133(R22)
+f8401e38| plan9 MOVB R24, -28(R7)
+5e911a78| plan9 MOVH R30, -87(R10)
+b7622d88| plan9 STXPW (R21), R24, R23, R13
+233d37c8| plan9 STXPW (R9), R15, R3, R23
+847d0088| plan9 STXRW R4, (R12), R0
+a27d0bc8| plan9 STXR R2, (R13), R11
+f27f1e08| plan9 STXRB R18, (RSP), R30
+3a7d1848| plan9 STXRH R26, (R9), R24
+d4dc204b| plan9 SUBW R0.SXTW<<7, R6, R20
+874023cb| plan9 SUB R3.UXTW, R4, R7
+44eb4f51| plan9 SUBW $(1018<<12), R26, R4
+17b012cb| plan9 SUB R18<<44, R0, R23
+ac1e376b| plan9 SUBSW R23.UXTB<<7, R21, R12
+b0483beb| plan9 SUBS R27.UXTW<<2, R5, R16
+d1f994eb| plan9 SUBS R20->62, R14, R17
+61d513d4| plan9 SVC $40619
+591d0013| plan9 SXTBW R10, R25
+9f1f4093| plan9 SXTB R28, ZR
+773f0013| plan9 SXTHW R27, R23
+453c4093| plan9 SXTH R2, R5
+b77c4093| plan9 SXTW R5, R23
+743628d5| plan9 SYSL $13920, R20
+9f613672| plan9 TSTW $4294966279, R12
+1f8d22f2| plan9 TST $-4610630471158349821, R8
+ff6e93ea| plan9 TST R19->27, R23
+06997ed3| plan9 UBFIZ $2, R8, $39, R6
+5dd054d3| plan9 UBFX $20, R2, $33, R29
+a54273d3| plan9 UBFIZ $13, R21, $17, R5
+7d08d11a| plan9 UDIVW R17, R3, R29
+120acf9a| plan9 UDIV R15, R16, R18
+1401a89b| plan9 UMADDL R8, R0, R8, R20
+08feb29b| plan9 UMNEGL R18, R16, R8
+eeb0b99b| plan9 UMSUBL R25, R12, R7, R14
+967fdd9b| plan9 UMULH R29, R28, R22
+947eb59b| plan9 UMULL R21, R20, R20
+7e1f0053| plan9 UXTBW R27, R30
+983c0053| plan9 UXTHW R4, R24
+5f2003d5| plan9 WFE
+7f2003d5| plan9 WFI
+3f2003d5| plan9 YIELD
+02bb200e| plan9 VABS V24.B8, V2.B8
+0686ec4e| plan9 VADD V12.D2, V16.D2, V6.D2
+ea42ac0e| plan9 VADDHN V12.D2, V23.D2, V10.S2
+7d43624e| plan9 VADDHN2 V2.S4, V27.S4, V29.H8
+2cbd710e| plan9 VADDP V17.H4, V9.H4, V12.H4
+f5bab14e| plan9 ADDV V23.S4, F21
+8158284e| plan9 VAESD V4.B16, V1.B16
+ba48284e| plan9 VAESE V5.B16, V26.B16
+0c7a284e| plan9 VAESIMC V16.B16, V12.B16
+3e6a284e| plan9 VAESMC V17.B16, V30.B16
+091f384e| plan9 VAND V24.B16, V24.B16, V9.B16
+07b6046f| plan9 VBIC $(144<<8), V7.H8
+00c5006f| plan9 VMVNI $(8<<136), V0.S4
+f81e6c0e| plan9 VBIC V12.B8, V23.B8, V24.B8
+6f1ced2e| plan9 VBIF V13.B8, V3.B8, V15.B8
+e31da16e| plan9 VBIT V1.B16, V15.B16, V3.B16
+6a1d7c6e| plan9 VBSL V28.B16, V11.B16, V10.B16
+284a600e| plan9 VCLS V17.H4, V8.H4
+9a49202e| plan9 VCLZ V12.B8, V26.B8
+d78f706e| plan9 VCMEQ V16.H8, V30.H8, V23.H8
+7798e05e| plan9 CMEQ $0, F3, F23
+739a200e| plan9 VCMEQ $0, V19.B8, V19.B8
+ff3f2b4e| plan9 VCMGE V11.B16, V31.B16, V31.B16
+5337370e| plan9 VCMGT V23.B8, V26.B8, V19.B8
+3489604e| plan9 VCMGT $0, V9.H8, V20.H8
+083d782e| plan9 VCMHS V24.H4, V8.H4, V8.H4
+c899e07e| plan9 CMLE $0, F14, F8
+3498a06e| plan9 VCMLE $0, V1.S4, V20.S4
+ebaa200e| plan9 VCMLT $0, V23.B8, V11.B8
+408dfe4e| plan9 VCMTST V30.D2, V10.D2, V0.D2
+0e06085e| plan9 VMOV V16.D[0], F14
+1e0d0d0e| plan9 VDUP R8, V30.B8
+8e1d3a6e| plan9 VEOR V26.B16, V12.B16, V14.B16
+632a086e| plan9 VEXT $5, V8.B16, V19.B16, V3.B16
+97d7e57e| plan9 FABD F5, F28, F23
+6bd4a82e| plan9 VFABD V8.S2, V3.S2, V11.S2
+f7faa00e| plan9 FABS V23.S2, V23.S2
+54c2201e| plan9 FABSS F18, F20
+3ec3601e| plan9 FABSD F25, F30
+2aee317e| plan9 FACGE F17, F17, F10
+2fed392e| plan9 VFACGE V25.S2, V9.S2, V15.S2
+2befe97e| plan9 FACGT F9, F25, F11
+65eced6e| plan9 VFACGT V13.D2, V3.D2, V5.D2
+55d53c4e| plan9 FADD V28.S4, V10.S4, V21.S4
+8b283f1e| plan9 FADDS F31, F4, F11
+d828601e| plan9 FADDD F0, F6, F24
+e9d8307e| plan9 FADDP V7.S2, F9
+4084391e| plan9 FCCMPS HI, F25, F2, $0
+ef046d1e| plan9 FCCMPD EQ, F13, F7, $15
+d7a4241e| plan9 FCCMPES GE, F4, F6, $7
+dbf5601e| plan9 FCCMPED AL, F0, F14, $11
+77e7625e| plan9 FCMEQ F2, F27, F23
+2de67f4e| plan9 VFCMEQ V31.D2, V17.D2, V13.D2
+59daa05e| plan9 FCMEQ $0, F18, F25
+add9a00e| plan9 VFCMEQ $0, V13.S2, V13.S2
+dce42d7e| plan9 FCMGE F13, F6, F28
+62e6776e| plan9 VFCMGE V23.D2, V19.D2, V2.D2
+f9cae07e| plan9 FCMGE $0, F23, F25
+18e5ab7e| plan9 FCMGT F11, F8, F24
+84e7ae6e| plan9 VFCMGT V14.S4, V28.S4, V4.S4
+a0c8e05e| plan9 FCMGT $0, F5, F0
+c6cae04e| plan9 VFCMGT $0, V22.D2, V6.D2
+4fdaa07e| plan9 FCMLE $0, F18, F15
+e1d9a02e| plan9 VFCMLE $0, V15.S2, V1.S2
+1ee9a05e| plan9 FCMLT $0, F8, F30
+23eaa04e| plan9 VFCMLT $0, V17.S4, V3.S4
+6023321e| plan9 FCMPS F18, F27
+2823391e| plan9 FCMPS $(0.0), F25
+00236d1e| plan9 FCMPD F13, F24
+e820601e| plan9 FCMPD $(0.0), F7
+3022381e| plan9 FCMPES F24, F17
+f8233e1e| plan9 FCMPES $(0.0), F31
+b0206a1e| plan9 FCMPED F10, F5
+3820691e| plan9 FCMPED $(0.0), F1
+d85f271e| plan9 FCSELS PL, F30, F7, F24
+ed8f7a1e| plan9 FCSELD HI, F31, F26, F13
+0042e21e| plan9 FCVTHS F16, F0
+efc1e21e| plan9 FCVTHD F15, F15
+edc1231e| plan9 FCVTSH F15, F13
+0ac0221e| plan9 FCVTSD F0, F10
+39c3631e| plan9 FCVTDH F25, F25
+da43621e| plan9 FCVTDS F30, F26
+10cb615e| plan9 FCVTAS F24, F16
+f400241e| plan9 FCVTASW F7, R20
+2f00249e| plan9 FCVTAS F1, R15
+1d02641e| plan9 FCVTASW F16, R29
+9303649e| plan9 FCVTAS F28, R19
+02ca217e| plan9 FCVTAU F16, F2
+afc8212e| plan9 VFCVTAU V5.S2, V15.S2
+6e02251e| plan9 FCVTAUW F19, R14
+fd02259e| plan9 FCVTAU F23, R29
+8603651e| plan9 FCVTAUW F28, R6
+4001659e| plan9 FCVTAU F10, R0
+1f78210e| plan9 VFCVTL V0.H4, V31.S4
+d179214e| plan9 VFCVTL2 V14.H8, V17.S4
+fdbb615e| plan9 FCVTMS F31, F29
+9601301e| plan9 FCVTMSW F12, R22
+f403309e| plan9 FCVTMS F31, R20
+6b02701e| plan9 FCVTMSW F19, R11
+4802709e| plan9 FCVTMS F18, R8
+84ba217e| plan9 FCVTMU F20, F4
+ae01311e| plan9 FCVTMUW F13, R14
+8402319e| plan9 FCVTMU F20, R4
+7403711e| plan9 FCVTMUW F27, R20
+2a03719e| plan9 FCVTMU F25, R10
+a36b210e| plan9 VFCVTN V29.S4, V3.H4
+5c6a214e| plan9 VFCVTN2 V18.S4, V28.H8
+78a9215e| plan9 FCVTNS F11, F24
+b1ab614e| plan9 VFCVTNS V29.D2, V17.D2
+0c01201e| plan9 FCVTNSW F8, R12
+b303209e| plan9 FCVTNS F29, R19
+c401601e| plan9 FCVTNSW F14, R4
+5200609e| plan9 FCVTNS F2, R18
+c2a8617e| plan9 FCVTNU F6, F2
+daab616e| plan9 VFCVTNU V30.D2, V26.D2
+d001211e| plan9 FCVTNUW F14, R16
+0402219e| plan9 FCVTNU F16, R4
+7800611e| plan9 FCVTNUW F3, R24
+e602619e| plan9 FCVTNU F23, R6
+74aaa15e| plan9 FCVTPS F19, F20
+c801281e| plan9 FCVTPSW F14, R8
+8f02289e| plan9 FCVTPS F20, R15
+6d02681e| plan9 FCVTPSW F19, R13
+bc00689e| plan9 FCVTPS F5, R28
+43aba17e| plan9 FCVTPU F26, F3
+cda9a12e| plan9 VFCVTPU V14.S2, V13.S2
+c102291e| plan9 FCVTPUW F22, R1
+9103299e| plan9 FCVTPU F28, R17
+7602691e| plan9 FCVTPUW F19, R22
+4501699e| plan9 FCVTPU F10, R5
+976a616e| plan9 VFCVTXN2 V20.D2, V23.S4
+d5fc575f| plan9 FCVTZS $41, F6, F21
+babaa15e| plan9 FCVTZSSS F21, F26
+7aa6181e| plan9 FCVTZS $23, F19, R26
+c410189e| plan9 FCVTZS $60, F6, R4
+4db5589e| plan9 FCVTZS $19, F10, R13
+9000381e| plan9 FCVTZSSW F4, R16
+1702389e| plan9 FCVTZSS F16, R23
+8a03781e| plan9 FCVTZSDW F28, R10
+d501789e| plan9 FCVTZSD F14, R21
+eefd2d7f| plan9 FCVTZU $19, F15, F14
+4dfc3c6f| plan9 FCVTZU $4, V2.S4, V13.S4
+96bbe17e| plan9 FCVTZUDD F28, F22
+30b8e16e| plan9 FCVTZU V1.D2, V16.D2
+fdef191e| plan9 FCVTZU $5, F31, R29
+1d7b199e| plan9 FCVTZU $34, F24, R29
+b8f5591e| plan9 FCVTZU $3, F13, R24
+5080599e| plan9 FCVTZU $32, F2, R16
+d002391e| plan9 FCVTZUSW F22, R16
+9b03399e| plan9 FCVTZUS F28, R27
+7501791e| plan9 FCVTZUDW F11, R21
+7603799e| plan9 FCVTZUD F27, R22
+06fe3c6e| plan9 FDIV V28.S4, V16.S4, V6.S4
+c41b201e| plan9 FDIVS F0, F30, F4
+1618781e| plan9 FDIVD F24, F0, F22
+507b0d1f| plan9 FMADD F30, F13, F26, F16
+8803491f| plan9 FMADD F0, F9, F28, F8
+75f7394e| plan9 FMAX V25.S4, V27.S4, V21.S4
+804b3c1e| plan9 FMAXS F28, F28, F0
+c1496c1e| plan9 FMAXD F12, F14, F1
+5b69371e| plan9 FMAXNMS F23, F10, F27
+1468711e| plan9 FMAXNMD F17, F0, F20
+a4c8707e| plan9 FMAXNMP V5.D2, F4
+89f9707e| plan9 FMAXP V12.D2, F9
+4af63e2e| plan9 VFMAXP V30.S2, V18.S2, V10.S2
+25fa306e| plan9 FMAXV V17.S4, F5
+01f4e04e| plan9 FMIN V0.D2, V0.D2, V1.D2
+59592a1e| plan9 FMINS F10, F10, F25
+3959611e| plan9 FMIND F1, F9, F25
+73c7ba4e| plan9 FMINNM V26.S4, V27.S4, V19.S4
+1279391e| plan9 FMINNMS F25, F8, F18
+75796c1e| plan9 FMINNMD F12, F11, F21
+90cbb07e| plan9 FMINNMP V28.S2, F16
+c5c8b06e| plan9 FMINNMV V6.S4, F5
+cdfbf07e| plan9 FMINP V30.D2, F13
+edf6f66e| plan9 VFMINP V22.D2, V23.D2, V13.D2
+6513b85f| plan9 FMLA V24.S[1], F27, F5
+ee18984f| plan9 VFMLA V24.S[2], V7.S4, V14.S4
+b85ab75f| plan9 FMLS V23.S[3], F21, F24
+a3f5030f| plan9 FMOV $0.90625, V3.S2
+eaf7056f| plan9 FMOV $-31., V10.D2
+3b41201e| plan9 FMOVS F9, F27
+0d41601e| plan9 FMOVD F8, F13
+9700271e| plan9 FMOVS R4, F23
+ad03261e| plan9 FMOVS F29, R13
+2302679e| plan9 FMOVD R17, F3
+e101af9e| plan9 FMOV R15, V1.D[1]
+f301669e| plan9 FMOVD F15, R19
+1103ae9e| plan9 FMOV V24.D[1], R17
+0230321e| plan9 FMOVS $-4.25, F2
+18b0751e| plan9 FMOVD $-14.5, F24
+92bc1b1f| plan9 FMSUB F15, F27, F4, F18
+f8e14a1f| plan9 FMSUB F24, F10, F15, F24
+ef91d35f| plan9 FMULD V19.D[0], F15, F15
+d293c24f| plan9 FMUL V2.D[0], V30.D2, V18.D2
+18dd2b2e| plan9 FMUL V11.S2, V8.S2, V24.S2
+a4093d1e| plan9 FMULS F29, F13, F4
+94096f1e| plan9 FMULD F15, F12, F20
+fe918e7f| plan9 FMULX V14.S[0], F15, F30
+7199c56f| plan9 VFMULX V5.D[1], V11.D2, V17.D2
+32dc695e| plan9 FMULX F9, F1, F18
+c8f9e06e| plan9 FNEG V14.D2, V8.D2
+9c41211e| plan9 FNEGS F12, F28
+c443611e| plan9 FNEGD F30, F4
+e77f301f| plan9 FNMADD F31, F16, F31, F7
+9f326c1f| plan9 FNMADD F12, F12, F20, F31
+d9e92f1f| plan9 FNMSUB F26, F15, F14, F25
+00ad711f| plan9 FNMSUB F11, F17, F8, F0
+c889211e| plan9 FNMULS F1, F14, F8
+528b761e| plan9 FNMULD F22, F26, F18
+01d8e15e| plan9 FRECPE F0, F1
+9aff7e5e| plan9 FRECPS F30, F28, F26
+78fe2a4e| plan9 VFRECPS V10.S4, V19.S4, V24.S4
+01f9e15e| plan9 FRECPX F8, F1
+128b216e| plan9 FRINTA V24.S4, V18.S4
+b241261e| plan9 FRINTAS F13, F18
+a841661e| plan9 FRINTAD F13, F8
+799aa16e| plan9 FRINTI V19.S4, V25.S4
+1cc2271e| plan9 FRINTIS F16, F28
+93c2671e| plan9 FRINTID F20, F19
+1a40251e| plan9 FRINTMS F0, F26
+ac42651e| plan9 FRINTMD F21, F12
+5889214e| plan9 FRINTN V10.S4, V24.S4
+5740241e| plan9 FRINTNS F2, F23
+9443641e| plan9 FRINTND F28, F20
+4b89a10e| plan9 FRINTP V10.S2, V11.S2
+a0c1241e| plan9 FRINTPS F13, F0
+93c2641e| plan9 FRINTPD F20, F19
+d49b216e| plan9 FRINTX V30.S4, V20.S4
+df41271e| plan9 FRINTXS F14, F31
+8d41671e| plan9 FRINTXD F12, F13
+3998a10e| plan9 FRINTZ V1.S2, V25.S2
+fdc2251e| plan9 FRINTZS F23, F29
+abc2651e| plan9 FRINTZD F21, F11
+10dba17e| plan9 FRSQRTE F24, F16
+edd9e16e| plan9 VFRSQRTE V15.D2, V13.D2
+75ffe35e| plan9 FRSQRTS F3, F27, F21
+b4fdbe4e| plan9 VFRSQRTS V30.S4, V13.S4, V20.S4
+24f8a16e| plan9 FSQRT V1.S4, V4.S4
+b6c1211e| plan9 FSQRTS F13, F22
+c1c3611e| plan9 FSQRTD F30, F1
+ffd5b44e| plan9 FSUB V20.S4, V15.S4, V31.S4
+d438331e| plan9 FSUBS F19, F6, F20
+f038771e| plan9 FSUBD F23, F7, F16
+675e1a6e| plan9 VMOV V19.H[5], V7.H[6]
+2a1c0a4e| plan9 VMOV R1, V10.H[2]
+de7f400c| plan9 VLD1 (R30), [V30.D1]
+4aa7404c| plan9 VLD1 (R26), [V10.H8, V11.H8]
+5d61400c| plan9 VLD1 (R10), [V29.B8, V30.B8, V31.B8]
+af21404c| plan9 VLD1 (R13), [V15.B16, V16.B16, V17.B16, V18.B16]
+737edf0c| plan9 VLD1.P 8(R19), [V19.D1]
+757dd10c| plan9 VLD1.P (R11)(R17), [V21.D1]
+5ca3df4c| plan9 VLD1.P 32(R26), [V28.B16, V29.B16]
+93a1ce0c| plan9 VLD1.P (R12)(R14), [V19.B8, V20.B8]
+1c65df0c| plan9 VLD1.P 24(R8), [V28.H4, V29.H4, V30.H4]
+4461d34c| plan9 VLD1.P (R10)(R19), [V4.B16, V5.B16, V6.B16]
+b22edf4c| plan9 VLD1.P 64(R21), [V18.D2, V19.D2, V20.D2, V21.D2]
+c12fcc4c| plan9 VLD1.P (R30)(R12), [V1.D2, V2.D2, V3.D2, V4.D2]
+5a03400d| plan9 LD1 (R26), [V26.B][0]
+8d93404d| plan9 LD1 (R28), [V13.S][3]
+2186404d| plan9 LD1 (R17), [V1.D][1]
+9604df4d| plan9 LD1.P 1(R4), [V22.B][9]
+4a1dc94d| plan9 LD1.P (R10)(R9), [V10.B][15]
+4852df4d| plan9 LD1.P 2(R18), [V8.H][6]
+2582df4d| plan9 LD1.P 4(R17), [V5.S][2]
+2191c84d| plan9 LD1.P (R9)(R8), [V1.S][3]
+c284df4d| plan9 LD1.P 8(R6), [V2.D][1]
+8f85ce0d| plan9 LD1.P (R12)(R14), [V15.D][0]
+87cd400d| plan9 VLD1R (R12), [V7.D1]
+3bc8df4d| plan9 VLD1R 4(R1), [V27.S4]
+77c4dd4d| plan9 VLD1R (R3)(R29), [V23.H8]
+5384404c| plan9 VLD2 (R2), [V19.H8, V20.H8]
+ca87df0c| plan9 VLD2 16(R30), [V10.H4, V11.H4]
+1280d70c| plan9 VLD2 (R0)(R23), [V18.B8, V19.B8]
+4c0a604d| plan9 LD2 (R18), [V12.B, V13.B][10]
+3080600d| plan9 LD2 (R1), [V16.S, V17.S][0]
+6686600d| plan9 LD2 (R19), [V6.D, V7.D][0]
+061eff0d| plan9 LD2 2(R16), [V6.B, V7.B][7]
+db05fa0d| plan9 LD2 (R14)(R26), [V27.B, V28.B][1]
+8a49ff4d| plan9 LD2 4(R12), [V10.H, V11.H][5]
+bb59ec4d| plan9 LD2 (R13)(R12), [V27.H, V28.H][7]
+5a82ff0d| plan9 LD2 8(R18), [V26.S, V27.S][0]
+6180e30d| plan9 LD2 (R3)(R3), [V1.S, V2.S][0]
+6485ff0d| plan9 LD2 16(R11), [V4.D, V5.D][0]
+7c86ed4d| plan9 LD2 (R19)(R13), [V28.D, V29.D][1]
+54c0604d| plan9 VLD2R (R2), [V20.B16, V21.B16]
+fdcaff0d| plan9 VLD2R 8(R23), [V29.S2, V30.S2]
+7bc5e40d| plan9 VLD2R (R11)(R4), [V27.H4, V28.H4]
+b349404c| plan9 VLD3 (R13), [V19.S4, V20.S4, V21.S4]
+cf46df4c| plan9 VLD3 48(R22), [V15.H8, V16.H8, V17.H8]
+934acc4c| plan9 VLD3 (R20)(R12), [V19.S4, V20.S4, V21.S4]
+2c33404d| plan9 LD3 (R25), [V12.B, V13.B, V14.B][12]
+897a400d| plan9 LD3 (R20), [V9.H, V10.H, V11.H][3]
+f9b2400d| plan9 LD3 (R23), [V25.S, V26.S, V27.S][1]
+4aa7404d| plan9 LD3 (R26), [V10.D, V11.D, V12.D][1]
+4e25df4d| plan9 LD3 3(R10), [V14.B, V15.B, V16.B][9]
+7827c40d| plan9 LD3 (R27)(R4), [V24.B, V25.B, V26.B][1]
+c4a3df4d| plan9 LD3 12(R30), [V4.S, V5.S, V6.S][2]
+f0a1cf0d| plan9 LD3 (R15)(R15), [V16.S, V17.S, V18.S][0]
+1ba7df0d| plan9 LD3 24(R24), [V27.D, V28.D, V29.D][0]
+f7a7d50d| plan9 LD3 (RSP)(R21), [V23.D, V24.D, V25.D][0]
+a9ed404d| plan9 VLD3R (R13), [V9.D2, V10.D2, V11.D2]
+5aecdf4d| plan9 VLD3R 24(R2), [V26.D2, V27.D2, V28.D2]
+bae9c74d| plan9 VLD3R (R13)(R7), [V26.S4, V27.S4, V28.S4]
+5904404c| plan9 VLD4 (R2), [V25.H8, V26.H8, V27.H8, V28.H8]
+743b604d| plan9 LD4 (R27), [V20.B, V21.B, V22.B, V23.B][14]
+bda1600d| plan9 LD4 (R13), [V29.S, V30.S, V31.S, V0.S][0]
+a3a4600d| plan9 LD4 (R5), [V3.D, V4.D, V5.D, V6.D][0]
+2f3aff4d| plan9 LD4 4(R17), [V15.B, V16.B, V17.B, V18.B][14]
+e73bef4d| plan9 LD4 (RSP)(R15), [V7.B, V8.B, V9.B, V10.B][14]
+5d78ef0d| plan9 LD4 (R2)(R15), [V29.H, V30.H, V31.H, V0.H][3]
+acb3ff0d| plan9 LD4 16(R29), [V12.S, V13.S, V14.S, V15.S][1]
+a8b2f04d| plan9 LD4 (R21)(R16), [V8.S, V9.S, V10.S, V11.S][3]
+75a7ff4d| plan9 LD4 32(R27), [V21.D, V22.D, V23.D, V24.D][1]
+75a6ee4d| plan9 LD4 (R19)(R14), [V21.D, V22.D, V23.D, V24.D][1]
+d8e3604d| plan9 VLD4R (R30), [V24.B16, V25.B16, V26.B16, V27.B16]
+49e9ff0d| plan9 VLD4R 16(R10), [V9.S2, V10.S2, V11.S2, V12.S2]
+81effc0d| plan9 VLD4R (R28)(R28), [V1.D1, V2.D1, V3.D1, V4.D1]
+893e622c| plan9 LDNP -240(R20), F15, F9
+f90e626c| plan9 LDNP -480(R23), F3, F25
+b0224fac| plan9 LDNP 480(R21), V8, V16
+9186de2c| plan9 LDP.P 244(R20), (F17, F1)
+e820d06c| plan9 LDP.P 256(R7), (F8, F8)
+417de8ac| plan9 LDP.P -768(R10), (V1, V31)
+7969ed2d| plan9 LDP.W -152(R11), (F25, F26)
+70c8c36d| plan9 LDP.W 56(R3), (F16, F18)
+30b4c4ad| plan9 LDP.W 144(R1), (V16, V13)
+a1857f2d| plan9 LDP -4(R13), (F1, F1)
+f4ae786d| plan9 LDP -120(R23), (F20, F11)
+998366ad| plan9 LDP -816(R28), (V25, V0)
+7535453c| plan9 MOVD.P 83(R11), F21
+5465477c| plan9 MOVD.P 118(R10), F20
+a2b44bbc| plan9 MOVD.P 187(R5), F2
+ab045bfc| plan9 MOVD.P -80(R5), F11
+0515d43c| plan9 MOVD.P -191(R8), V5
+43ad413c| plan9 MOVD.W 26(R10), F3
+22cd4f7c| plan9 MOVD.W 252(R9), F2
+5fad44bc| plan9 MOVD.W 74(R10), F31
+db7d5afc| plan9 MOVD.W -89(R14), F27
+15ccd63c| plan9 MOVD.W -148(R0), V21
+95c34b3d| plan9 MOVD 752(R28), F21
+f5885e7d| plan9 MOVD 3908(R7), F21
+54db66bd| plan9 MOVD 9944(R26), F20
+46ee78fd| plan9 MOVD 29144(R18), F6
+0cc4e93d| plan9 MOVD 42768(R0), V12
+ae79703c| plan9 MOVD R16<<1(R13), F14
+3e6b6dfc| plan9 MOVD R13(R25), F30
+a278ff3c| plan9 MOVD ZR<<4(R5), V2
+ed02563c| plan9 LDUR -160(R23), F13
+01c0507c| plan9 LDUR -244(R0), F1
+7fd24ebc| plan9 LDUR 237(R19), F31
+7a734ffc| plan9 LDUR 247(R27), F26
+d4a3dd3c| plan9 LDUR -38(R30), V20
+1c97250e| plan9 VMLA V5.B8, V24.B8, V28.B8
+af97a12e| plan9 VMLS V1.S2, V29.S2, V15.S2
+2b061f5e| plan9 VMOV V17.B[15], F11
+805e086e| plan9 VMOV V20.D[1], V0.D[0]
+d91fbc4e| plan9 VORR V28.B16, V30.B16, V25.B16
+a43f040e| plan9 VMOV V29.S[0], R4
+fbe6054f| plan9 VMOVI $183, V27.B16
+9b75024f| plan9 VORR $(76<<24), V27.S4
+8436020f| plan9 VORR $(84<<8), V4.S2
+19f5010f| plan9 FMOV $12., V25.S2
+02e5062f| plan9 MOVI $-281470698520576, F2
+d6e5066f| plan9 VMOVI $-281470681743616, V22.D2
+be9c240e| plan9 VMUL V4.B8, V5.B8, V30.B8
+2659202e| plan9 VMVN V9.B8, V6.B8
+f394046f| plan9 VBIC $135, V19.H8
+d856056f| plan9 VBIC $(182<<16), V24.S4
+2f85022f| plan9 VMVNI $73, V15.H4
+24baa02e| plan9 VNEG V17.S2, V4.S2
+145b206e| plan9 VMVN V24.B16, V20.B16
+191fff4e| plan9 VORN V31.B16, V24.B16, V25.B16
+6f96004f| plan9 VORR $19, V15.H8
+a564020f| plan9 VMOVI $(69<<24), V5.S2
+ae1ead0e| plan9 VORR V13.B8, V21.B8, V14.B8
+f2e1e00e| plan9 VPMULL V0.D1, V15.D1, V18.Q1
+0d426e2e| plan9 VRADDHN V14.S4, V16.S4, V13.H4
+4443246e| plan9 VRADDHN2 V4.H8, V26.H8, V4.B16
+015b602e| plan9 VRBIT V24.B8, V1.B8
+4209202e| plan9 VREV32 V10.B8, V2.B8
+d109a04e| plan9 VREV64 V14.S4, V17.S4
+5a8e380f| plan9 VRSHRN $8, V18.D2, V26.S2
+438d234f| plan9 VRSHRN2 $29, V10.D2, V3.S4
+a861716e| plan9 VRSUBHN2 V17.S4, V13.S4, V8.H8
+017c2f0e| plan9 VSABA V15.B8, V0.B8, V1.B8
+5d51a90e| plan9 VSABAL V9.S2, V10.S2, V29.D2
+c076a04e| plan9 VSABD V0.S4, V22.S4, V0.S4
+2d722e0e| plan9 VSABDL V14.B8, V17.B8, V13.H8
+1f732e4e| plan9 VSABDL2 V14.B16, V24.B16, V31.H8
+c628604e| plan9 VSADDLP V6.H8, V6.S4
+103b704e| plan9 SADDLV V24.H8, F16
+8f122f0e| plan9 VSADDW V15.B8, V20.H8, V15.H8
+30e6755f| plan9 SCVTF $11, F17, F16
+73e7544f| plan9 SCVTF $44, V27.D2, V19.D2
+51d9615e| plan9 SCVTFDD F10, F17
+fad9210e| plan9 SCVTF V15.S2, V26.S2
+96c0421e| plan9 SCVTF $16, R4, F22
+76e1029e| plan9 SCVTF $8, R11, F22
+a791429e| plan9 SCVTF $28, R13, F7
+f100221e| plan9 SCVTFWS R7, F17
+e101621e| plan9 SCVTFWD R15, F1
+6e03229e| plan9 SCVTFS R27, F14
+0b01629e| plan9 SCVTFD R8, F11
+2401025e| plan9 SHA1C V2.S4, F9, V4
+5d08285e| plan9 SHA1H F2, F29
+65210d5e| plan9 SHA1M V13.S4, F11, V5
+29131a5e| plan9 SHA1P V26.S4, F25, V9
+2b311a5e| plan9 VSHA1SU0 V26.S4, V9.S4, V11.S4
+0919285e| plan9 VSHA1SU1 V8.S4, V9.S4
+f052035e| plan9 SHA256H2 V3.S4, V23, V16
+fe401e5e| plan9 SHA256H V30.S4, V7, V30
+7529285e| plan9 VSHA256SU0 V11.S4, V21.S4
+cc60195e| plan9 VSHA256SU1 V25.S4, V6.S4, V12.S4
+8b56060f| plan9 VORR $(212<<16), V11.S2
+3f3aa16e| plan9 VSHLL2 $32, V17.S4, V31.D2
+0986394f| plan9 VSHRN2 $7, V16.D2, V9.S4
+35276e4e| plan9 VSHSUB V14.H8, V25.H8, V21.H8
+e2556d7f| plan9 SLI $45, F15, F2
+f7541e6f| plan9 VSLI $14, V7.H8, V23.H8
+3167630e| plan9 VSMAX V3.H4, V25.H4, V17.H4
+68a6230e| plan9 VSMAXP V3.B8, V19.B8, V8.B8
+a4aa304e| plan9 SMAXV V21.B16, F4
+2520440f| plan9 VSMLAL V4.H[0], V1.H4, V5.S4
+8c286f4f| plan9 VSMLAL2 V15.H[6], V4.H8, V12.S4
+3a82660e| plan9 VSMLAL V6.H4, V17.H4, V26.S4
+d92f1f0e| plan9 SMOVW V30.B[15], R25
+912d114e| plan9 SMOV V12.B[8], R17
+b87ae05e| plan9 SQABS F21, F24
+2d7b200e| plan9 VSQABS V25.B8, V13.B8
+560f645e| plan9 SQADD F4, F26, F22
+4f0da54e| plan9 VSQADD V5.S4, V10.S4, V15.S4
+5992ba5e| plan9 SQDMLAL F26, F18, F25
+b892684e| plan9 VSQDMLAL2 V8.H8, V21.H8, V24.S4
+63786e5f| plan9 SQDMLSL V14.H[6], F3, F3
+0c79a10f| plan9 VSQDMLSL V1.S[3], V8.S2, V12.D2
+1d73504f| plan9 VSQDMLSL2 V0.H[1], V24.H8, V29.S4
+6cb36c5e| plan9 SQDMLSL F12, F27, F12
+82b36e4e| plan9 VSQDMLSL2 V14.H8, V28.H8, V2.S4
+8dca5d4f| plan9 VSQDMULH V13.H[5], V20.H8, V13.H8
+fcb6b64e| plan9 VSQDMULH V22.S4, V23.S4, V28.S4
+d6b0974f| plan9 VSQDMULL2 V23.S[0], V6.S4, V22.D2
+afd0b84e| plan9 VSQDMULL2 V24.S4, V5.S4, V15.D2
+067b207e| plan9 SQNEG F24, F6
+9979606e| plan9 VSQNEG V12.H8, V25.H8
+bfdbae0f| plan9 VSQRDMULH V14.S[3], V29.S2, V31.S2
+c3b7a07e| plan9 SQRDMULH F0, F30, F3
+845d3d5e| plan9 SQRSHL F29, F12, F4
+495dba0e| plan9 VSQRSHL V26.S2, V10.S2, V9.S2
+fa8e0d7f| plan9 SQRSHRUN $3, F23, F26
+cf75185f| plan9 SQSHL $8, F14, F15
+a975250f| plan9 VSQSHL $5, V13.S2, V9.S2
+424da05e| plan9 SQSHL F0, F10, F2
+464db90e| plan9 VSQSHL V25.S2, V10.S2, V6.S2
+af656d7f| plan9 SQSHLU $45, F13, F15
+e564436f| plan9 VSQSHLU $3, V7.D2, V5.D2
+c1973b5f| plan9 SQSHRN $5, F30, F1
+d586036f| plan9 VMVNI $118, V21.H8
+4c2ea95e| plan9 SQSUB F9, F18, F12
+df2efe4e| plan9 VSQSUB V30.D2, V22.D2, V31.D2
+c149a10e| plan9 VSQXTN V14.D2, V1.S2
+712a217e| plan9 SQXTUN F19, F17
+9a29a12e| plan9 VSQXTUN V12.D2, V26.S2
+6a166e0e| plan9 VSRHADD V14.H4, V19.H4, V10.H4
+0445647f| plan9 SRI $28, F8, F4
+6f44172f| plan9 VSRI $9, V3.H4, V15.H4
+cd56f94e| plan9 VSRSHL V25.D2, V22.D2, V13.D2
+12345b5f| plan9 SRSRA $37, F0, F18
+f746fa5e| plan9 SSHL F26, F23, F23
+89476c4e| plan9 VSSHL V12.H8, V28.H8, V9.H8
+0da60e0f| plan9 VSSHLL $6, V16.B8, V13.H8
+a504585f| plan9 SSHR $40, F5, F5
+3b07544f| plan9 VSSHR $44, V25.D2, V27.D2
+3417350f| plan9 VSSRA $11, V25.S2, V20.S2
+1a213f0e| plan9 VSSUBL V31.B8, V8.B8, V26.H8
+1322a34e| plan9 VSSUBL2 V3.S4, V16.S4, V19.D2
+e931b84e| plan9 VSSUBW2 V24.S4, V15.D2, V9.D2
+dd7d004c| plan9 VST1 (R14), [V29.D2]
+cea4000c| plan9 VST1 (R6), [V14.H4, V15.H4]
+5a64000c| plan9 VST1 (R2), [V26.H4, V27.H4, V28.H4]
+2b2c004c| plan9 VST1 (R1), [V11.D2, V12.D2, V13.D2, V14.D2]
+39719f0c| plan9 VST1 8(R9), [V25.B8]
+b771874c| plan9 VST1 (R13)(R7), [V23.B16]
+1da39f0c| plan9 VST1 16(R24), [V29.B8, V30.B8]
+20a0800c| plan9 VST1 (R1)(R0), [V0.B8, V1.B8]
+5a6a9f4c| plan9 VST1 48(R18), [V26.S4, V27.S4, V28.S4]
+0d69994c| plan9 VST1 (R8)(R25), [V13.S4, V14.S4, V15.S4]
+7e239f0c| plan9 VST1 32(R27), [V30.B8, V31.B8, V0.B8, V1.B8]
+9a2d8e0c| plan9 VST1 (R12)(R14), [V26.D1, V27.D1, V28.D1, V29.D1]
+fd0b004d| plan9 ST1 (RSP), [V29.B][10]
+1058004d| plan9 ST1 (R0), [V16.H][7]
+0593000d| plan9 ST1 (R24), [V5.S][1]
+3d87000d| plan9 ST1 (R25), [V29.D][0]
+1a079f0d| plan9 ST1 1(R24), [V26.B][1]
+421b8f4d| plan9 ST1 (R26)(R15), [V2.B][14]
+54489f4d| plan9 ST1 2(R2), [V20.H][5]
+c4809f4d| plan9 ST1 4(R6), [V4.S][2]
+0481840d| plan9 ST1 (R8)(R4), [V4.S][0]
+6b859f0d| plan9 ST1 8(R11), [V11.D][0]
+f7878e4d| plan9 ST1 (RSP)(R14), [V23.D][1]
+e788004c| plan9 VST2 (R7), [V7.S4, V8.S4]
+79889f0c| plan9 VST2 16(R3), [V25.S2, V26.S2]
+a502204d| plan9 ST2 (R21), [V5.B, V6.B][8]
+0e50204d| plan9 ST2 (R0), [V14.H, V15.H][6]
+6b93204d| plan9 ST2 (R27), [V11.S, V12.S][3]
+0987200d| plan9 ST2 (R24), [V9.D, V10.D][0]
+7003bf0d| plan9 ST2 2(R27), [V16.B, V17.B][0]
+1a09a94d| plan9 ST2 (R8)(R9), [V26.B, V27.B][10]
+1e43b00d| plan9 ST2 (R24)(R16), [V30.H, V31.H][0]
+1a82bf0d| plan9 ST2 8(R16), [V26.S, V27.S][0]
+9892a50d| plan9 ST2 (R20)(R5), [V24.S, V25.S][1]
+5884bf0d| plan9 ST2 16(R2), [V24.D, V25.D][0]
+9e87a34d| plan9 ST2 (R28)(R3), [V30.D, V31.D][1]
+4e47004c| plan9 VST3 (R26), [V14.H8, V15.H8, V16.H8]
+76489f4c| plan9 VST3 48(R3), [V22.S4, V23.S4, V24.S4]
+3b48860c| plan9 VST3 (R1)(R6), [V27.S2, V28.S2, V29.S2]
+e52a000d| plan9 ST3 (R23), [V5.B, V6.B, V7.B][2]
+6f73004d| plan9 ST3 (R27), [V15.H, V16.H, V17.H][6]
+9bb1004d| plan9 ST3 (R12), [V27.S, V28.S, V29.S][3]
+0ca7000d| plan9 ST3 (R24), [V12.D, V13.D, V14.D][0]
+2a259f0d| plan9 ST3 3(R9), [V10.B, V11.B, V12.B][1]
+0524860d| plan9 ST3 (R0)(R6), [V5.B, V6.B, V7.B][1]
+94689a4d| plan9 ST3 (R4)(R26), [V20.H, V21.H, V22.H][5]
+c2a19f4d| plan9 ST3 12(R14), [V2.S, V3.S, V4.S][2]
+5fb38c0d| plan9 ST3 (R26)(R12), [V31.S, V0.S, V1.S][1]
+6da59f4d| plan9 ST3 24(R11), [V13.D, V14.D, V15.D][1]
+32a7924d| plan9 ST3 (R25)(R18), [V18.D, V19.D, V20.D][1]
+5b03000c| plan9 VST4 (R26), [V27.B8, V28.B8, V29.B8, V30.B8]
+cd059f0c| plan9 VST4 32(R14), [V13.H4, V14.H4, V15.H4, V16.H4]
+8601820c| plan9 VST4 (R12)(R2), [V6.B8, V7.B8, V8.B8, V9.B8]
+7925200d| plan9 ST4 (R11), [V25.B, V26.B, V27.B, V28.B][1]
+cd7a204d| plan9 ST4 (R22), [V13.H, V14.H, V15.H, V16.H][7]
+dfb2204d| plan9 ST4 (R22), [V31.S, V0.S, V1.S, V2.S][3]
+daa4200d| plan9 ST4 (R6), [V26.D, V27.D, V28.D, V29.D][0]
+2135bf0d| plan9 ST4 4(R9), [V1.B, V2.B, V3.B, V4.B][5]
+7727a90d| plan9 ST4 (R27)(R9), [V23.B, V24.B, V25.B, V26.B][1]
+b4a3bf0d| plan9 ST4 16(R29), [V20.S, V21.S, V22.S, V23.S][0]
+1ba3ae0d| plan9 ST4 (R24)(R14), [V27.S, V28.S, V29.S, V30.S][0]
+93a4bf0d| plan9 ST4 32(R4), [V19.D, V20.D, V21.D, V22.D][0]
+50a6b80d| plan9 ST4 (R18)(R24), [V16.D, V17.D, V18.D, V19.D][0]
+79b53d2c| plan9 STNP -20(R11), F13, F25
+d895326c| plan9 STNP -216(R14), F5, F24
+d1810dac| plan9 STNP 432(R14), V0, V17
+08728c2c| plan9 STP.P (F8, F28), 96(R16)
+ac1ba16c| plan9 STP.P (F12, F6), -496(R29)
+f4fab1ac| plan9 STP.P (V20, V30), -464(R23)
+c15bbe2d| plan9 STP.W (F1, F22), -16(R30)
+2422856d| plan9 STP.W (F4, F8), 80(R17)
+3d5282ad| plan9 STP.W (V29, V20), 64(R17)
+5df5352d| plan9 STP (F29, F29), -84(R10)
+5c54286d| plan9 STP (F28, F21), -384(R2)
+753c11ad| plan9 STP (V21, V15), 544(R3)
+54e4033c| plan9 MOVD.P F20, 62(R2)
+aa54137c| plan9 MOVD.P F10, -203(R5)
+c9d615bc| plan9 MOVD.P F9, -163(R22)
+fc471efc| plan9 MOVD.P F28, -28(RSP)
+20f78d3c| plan9 MOVD.P V0, 223(R25)
+028d1b3c| plan9 MOVD.W F2, -72(R8)
+35be037c| plan9 MOVD.W F21, 59(R17)
+b98c15bc| plan9 MOVD.W F25, -168(R5)
+fd1e11fc| plan9 MOVD.W F29, -239(R23)
+13ec9a3c| plan9 MOVD.W V19, -82(R0)
+b12d123d| plan9 MOVD F17, 1163(R13)
+d6500b7d| plan9 MOVD F22, 1448(R6)
+d46e39bd| plan9 MOVD F20, 14700(R22)
+b84f30fd| plan9 MOVD F24, 24728(R29)
+3cee993d| plan9 MOVD V28, 26544(R17)
+ed7b253c| plan9 MOVD F13, R5<<1(RSP)
+1c68a43c| plan9 MOVD V28, R4(R0)
+dcb1023c| plan9 MOVD F28, 43(R14)
+6701117c| plan9 MOVD F7, -240(R11)
+85b11bbc| plan9 MOVD F5, -69(R12)
+8ea10efc| plan9 MOVD F14, 234(R12)
+eab08f3c| plan9 MOVD V10, 251(R7)
+ca876a2e| plan9 VSUB V10.H4, V30.H4, V10.H4
+603be05e| plan9 SUQADD F27, F0
+513a600e| plan9 VSUQADD V18.H4, V17.H4
+25231c4e| plan9 VTBL V28.B16, [V25.B16, V26.B16], V5.B16
+8c40100e| plan9 VTBL V16.B8, [V4.B16, V5.B16, V6.B16], V12.B8
+0462040e| plan9 VTBL V4.B8, [V16.B16, V17.B16, V18.B16, V19.B16], V4.B8
+34000f0e| plan9 VTBL V15.B8, [V1.B16], V20.B8
+eb301f4e| plan9 VTBX V31.B16, [V7.B16, V8.B16], V11.B16
+bb51124e| plan9 VTBX V18.B16, [V13.B16, V14.B16, V15.B16], V27.B16
+cf701d0e| plan9 VTBX V29.B8, [V6.B16, V7.B16, V8.B16, V9.B16], V15.B8
+4213080e| plan9 VTBX V8.B8, [V26.B16], V2.B8
+2b2b114e| plan9 VTRN1 V17.B16, V25.B16, V11.B16
+766ada4e| plan9 VTRN2 V26.D2, V19.D2, V22.D2
+4152672e| plan9 VUABAL V7.H4, V18.H4, V1.S4
+0953296e| plan9 VUABAL2 V9.B16, V24.B16, V9.H8
+41756c6e| plan9 VUABD V12.H8, V10.H8, V1.H8
+3670ae2e| plan9 VUABDL V14.S2, V1.S2, V22.D2
+5401312e| plan9 VUADDL V17.B8, V10.B8, V20.H8
+d103286e| plan9 VUADDL2 V8.B16, V30.B16, V17.H8
+a92a206e| plan9 VUADDLP V21.B16, V9.H8
+b839706e| plan9 UADDLV V13.H8, F24
+ea106d2e| plan9 VUADDW V13.H4, V7.S4, V10.S4
+c010726e| plan9 VUADDW2 V18.H8, V6.S4, V0.S4
+e7e5517f| plan9 UCVTF $47, F15, F7
+49e7376f| plan9 UCVTF $9, V26.S4, V9.S4
+4ada617e| plan9 UCVTFDD F18, F10
+6b82431e| plan9 UCVTF $32, R19, F11
+db84039e| plan9 UCVTF $31, R6, F27
+1c72439e| plan9 UCVTF $36, R16, F28
+f301231e| plan9 UCVTFWS R15, F19
+3503631e| plan9 UCVTFWD R25, F21
+e602239e| plan9 UCVTFS R23, F6
+d503639e| plan9 UCVTFD R30, F21
+ec04606e| plan9 VUHADD V0.H8, V7.H8, V12.H8
+3f65782e| plan9 VUMAX V24.H4, V9.H4, V31.H4
+afa6232e| plan9 VUMAXP V3.B8, V21.B8, V15.B8
+cdaa706e| plan9 UMAXV V22.H8, F13
+736c236e| plan9 VUMIN V3.B16, V3.B16, V19.B16
+a0afa62e| plan9 VUMINP V6.S2, V29.S2, V0.S2
+3c229e2f| plan9 VUMLAL V30.S[0], V17.S2, V28.D2
+9d29a56f| plan9 VUMLAL2 V5.S[3], V12.S4, V29.D2
+6c80392e| plan9 VUMLAL V25.B8, V3.B8, V12.H8
+4f60692f| plan9 VUMLSL V9.H[2], V2.H4, V15.S4
+61a1606e| plan9 VUMLSL2 V0.H8, V11.H8, V1.S4
+183e0b0e| plan9 UMOVW V16.B[5], R24
+c0a89b6f| plan9 VUMULL2 V27.S[2], V6.S4, V0.D2
+36c0736e| plan9 VUMULL2 V19.H8, V1.H8, V22.S4
+120d757e| plan9 UQADD F21, F8, F18
+3a0c2e2e| plan9 VUQADD V14.B8, V1.B8, V26.B8
+0d5d617e| plan9 UQRSHL F1, F8, F13
+4d5cb16e| plan9 VUQRSHL V17.S4, V2.S4, V13.S4
+439c382f| plan9 VUQRSHRN $8, V2.D2, V3.S2
+9d745c7f| plan9 UQSHL $28, F4, F29
+7b76656f| plan9 VUQSHL $37, V19.D2, V27.D2
+774ef37e| plan9 UQSHL F19, F19, F23
+124eb32e| plan9 VUQSHL V19.S2, V16.S2, V18.S2
+bc961f6f| plan9 VUQSHRN2 $1, V21.S4, V28.H8
+a62ce07e| plan9 UQSUB F0, F5, F6
+0f2dae2e| plan9 VUQSUB V14.S2, V8.S2, V15.S2
+b24b217e| plan9 UQXTN F29, F18
+f148216e| plan9 VUQXTN2 V7.H8, V17.B16
+7d15a42e| plan9 VURHADD V4.S2, V11.S2, V29.S2
+9055fc6e| plan9 VURSHL V28.D2, V12.D2, V16.D2
+eb275e7f| plan9 URSHR $34, F31, F11
+c0347c7f| plan9 URSRA $4, F6, F0
+fe44e97e| plan9 USHL F9, F7, F30
+fa47e86e| plan9 VUSHL V8.D2, V31.D2, V26.D2
+95a7262f| plan9 VUSHLL $6, V28.S2, V21.D2
+9ca7096f| plan9 VUSHLL2 $1, V28.B16, V28.H8
+8a07527f| plan9 USHR $46, F28, F10
+c7076b6f| plan9 VUSHR $21, V30.D2, V7.D2
+8d39e07e| plan9 USQADD F12, F13
+f716727f| plan9 USRA $14, F23, F23
+3f14066f| plan9 VBIC $193, V31.S4
+b423ac2e| plan9 VUSUBL V12.S2, V29.S2, V20.D2
+7c22736e| plan9 VUSUBL2 V19.H8, V19.H8, V28.S4
+76317d2e| plan9 VUSUBW V29.H4, V11.S4, V22.S4
+8f302a6e| plan9 VUSUBW2 V10.B16, V4.H8, V15.H8
+c5a4286f| plan9 VUSHLL2 $8, V6.S4, V5.D2
+d3198c0e| plan9 VUZP1 V12.S2, V14.S2, V19.S2
+c05bdb4e| plan9 VUZP2 V27.D2, V30.D2, V0.D2
+362b610e| plan9 VXTN V25.S4, V22.H4
+0c29214e| plan9 VXTN2 V8.H8, V12.B16
+2b39c64e| plan9 VZIP1 V6.D2, V9.D2, V11.D2
+9500091a| plan9 ADCW R9, R4, R21
+c2001a9a| plan9 ADC R26, R6, R2
+6a02163a| plan9 ADCSW R22, R19, R10
+0c0118ba| plan9 ADCS R24, R8, R12
+b1c42b0b| plan9 ADDW R11.SXTW<<1, R5, R17
+bf15368b| plan9 ADD R22.UXTB<<5, R13, RSP
+be1f468b| plan9 ADD R6>>7, R29, R30
+8f51352b| plan9 ADDSW R21.UXTW<<4, R12, R15
+97043eab| plan9 ADDS R30.UXTB<<1, R4, R23
+09b00931| plan9 ADDSW $620, R0, R9
+4de204ab| plan9 ADDS R4<<56, R18, R13
+f6b60912| plan9 ANDW $4288675743, R23, R22
+a6d13b92| plan9 AND $-2025524839466146845, R13, R6
+1cc0138a| plan9 AND R19<<48, R0, R28
+73882072| plan9 ANDSW $458759, R3, R19
+b5780af2| plan9 ANDS $-9007199256838145, R5, R21
+766c90ea| plan9 ANDS R16->27, R3, R22
+a72ac31a| plan9 ASRW R3, R21, R7
+ff28d59a| plan9 ASR R21, R7, ZR
+3e7f0913| plan9 ASRW $9, R25, R30
+bafd5493| plan9 ASR $20, R13, R26
+302ad21a| plan9 ASRW R18, R17, R16
+602bd79a| plan9 ASR R23, R27, R0
+4fa4df54| plan9 BAL -66270(PC)
+a2e9cf15| plan9 JMP 30402978(PC)
+eff373b3| plan9 BFXIL $51, ZR, $10, R15
+9e3e7db3| plan9 BFI $3, R20, $16, R30
+87fa41b3| plan9 BFXIL $1, R20, $62, R7
+b831f80a| plan9 BICW R24@>12, R13, R24
+ffe0ae8a| plan9 BIC R14->56, R7, ZR
+7c2c276a| plan9 BICSW R7<<11, R3, R28
+ccf2fbea| plan9 BICS R27@>60, R22, R12
+722cd195| plan9 CALL 30485618(PC)
+20003fd6| plan9 CALL (R1)
+e0021fd6| plan9 JMP (R23)
+80db37d4| plan9 BRK $48860
+e048533a| plan9 CCMNW MI, R7, $19, $0
+e7da4fba| plan9 CCMN LE, R23, $15, $7
+67f2583a| plan9 CCMNW AL, R19, R24, $7
+60a05aba| plan9 CCMN GE, R3, R26, $0
+6a3b517a| plan9 CCMPW LO, R27, $17, $10
+8a4b55fa| plan9 CCMP MI, R28, $21, $10
+ed934b7a| plan9 CCMPW LS, ZR, R11, $13
+24414ffa| plan9 CCMP MI, R9, R15, $4
+0e169c1a| plan9 CSINCW NE, R16, R28, R14
+8264949a| plan9 CSINC VS, R4, R20, R2
+b363935a| plan9 CSINVW VS, R29, R19, R19
+ff619dda| plan9 CSINV VS, R15, R29, ZR
+5f3703d5| plan9 CLREX $7
+0017c05a| plan9 CLSW R24, R0
+8216c0da| plan9 CLS R20, R2
+3310c05a| plan9 CLZW R1, R19
+6e13c0da| plan9 CLZ R27, R14
+7fd02b2b| plan9 CMNW R11.SXTW<<4, R3
+5f3928ab| plan9 CMN R8.UXTH<<6, R10
+1fb92cb1| plan9 CMN $2862, R8
+ff164eab| plan9 CMN R14>>5, R23
+ff71256b| plan9 CMPW R5.UXTX<<4, R15
+df6034eb| plan9 CMP R20.UXTX, R6
+ff776af1| plan9 CMP $(2717<<12), RSP
+80e4855a| plan9 CSNEGW AL, R4, R5, R0
+da3490da| plan9 CSNEG LO, R6, R16, R26
+af40c71a| plan9 CRC32B R7, R5, R15
+c546cf1a| plan9 CRC32H R15, R22, R5
+6148c01a| plan9 CRC32W R0, R3, R1
+0f4eda9a| plan9 CRC32X R26, R16, R15
+4950d01a| plan9 CRC32CB R16, R2, R9
+8155c31a| plan9 CRC32CH R3, R12, R1
+835ace1a| plan9 CRC32CW R14, R20, R3
+f05fc59a| plan9 CRC32CX R5, ZR, R16
+0ae3901a| plan9 CSELW AL, R24, R16, R10
+ed51969a| plan9 CSEL PL, R15, R22, R13
+ee679f1a| plan9 CSETW VC, R14
+ed579f9a| plan9 CSET MI, R13
+f2539f5a| plan9 CSETMW MI, R18
+ffe39fda| plan9 CSINV AL, ZR, ZR, ZR
+9d25941a| plan9 CSINCW HS, R12, R20, R29
+afb7829a| plan9 CSINC LT, R29, R2, R15
+7602895a| plan9 CSINVW EQ, R19, R9, R22
+011394da| plan9 CSINV NE, R24, R20, R1
+68b7935a| plan9 CSNEGW LT, R27, R19, R8
+a32784da| plan9 CSNEG HS, R29, R4, R3
+8159a6d4| plan9 DCPS1 $13004
+c2d9aad4| plan9 DCPS2 $22222
+63ceb7d4| plan9 DCPS3 $48755
+bf3903d5| plan9 DMB $9
+e003bfd6| plan9 DRPS
+9f3603d5| plan9 DSB $6
+fc76a9ca| plan9 EON R9->29, R23, R28
+540f2352| plan9 EORW $3758096385, R26, R20
+187e1ed2| plan9 EOR $-1, R16, R24
+fd37004a| plan9 EORW R0<<13, ZR, R29
+b8c542ca| plan9 EOR R2>>49, R13, R24
+e0039fd6| plan9 ERET
+5f26c193| plan9 EXTR $9, R1, R18, ZR
+7f2003d5| plan9 WFI
+ff2a03d5| plan9 HINT $87
+804a59d4| plan9 HLT $51796
+df3003d5| plan9 ISB $0
+10fcdf88| plan9 LDARW (R0), R16
+fafcdfc8| plan9 LDAR (R7), R26
+30fedf08| plan9 LDARB (R17), R16
+63fedf48| plan9 LDARH (R19), R3
+82ba7f88| plan9 LDAXPW (R20), R14, R2
+d6917fc8| plan9 LDAXP (R14), R4, R22
+59ff5f88| plan9 LDAXRW (R26), R25
+fefe5fc8| plan9 LDAXR (R23), R30
+a0fc5f08| plan9 LDAXRB (R5), R0
+fafd5f48| plan9 LDAXRH (R15), R26
+b8804428| plan9 LDNPW 36(R5), R0, R24
+93e969a8| plan9 LDNP -360(R12), R26, R19
+caccef28| plan9 LDP.P -132(R6), (R10, R19)
+7365c3a8| plan9 LDP.P 48(R11), (R19, R25)
+3106ca29| plan9 LDP.W 80(R17), (R17, R1)
+0c02f7a9| plan9 LDP.W -144(R16), (R12, R0)
+41af6529| plan9 LDP -212(R26), (R1, R11)
+706b65a9| plan9 LDP -432(R27), (R16, R26)
+746ecf68| plan9 LDPSW 120(R19), R27, R20
+c051c669| plan9 LDPSW 48(R14), R20, R0
+aded5b69| plan9 LDPSW 220(R13), R27, R13
+990457b8| plan9 MOVWU.P -144(R4), R25
+bbd556f8| plan9 MOVD.P -147(R13), R27
+a45c51b8| plan9 MOVWU.W -235(R5), R4
+344c41f8| plan9 MOVD.W 20(R1), R20
+2d8755b9| plan9 MOVWU 5508(R25), R13
+56e360f9| plan9 MOVD 16832(R26), R22
+3b264e38| plan9 MOVBU.P 226(R17), R27
+898f5738| plan9 MOVBU.W -136(R28), R9
+c44e6839| plan9 MOVBU 2579(R22), R4
+2d687738| plan9 MOVBU R23(R1), R13
+4d475978| plan9 MOVHU.P -108(R26), R13
+39de5278| plan9 MOVHU.W -211(R17), R25
+9cc54879| plan9 MOVHU 1122(R12), R28
+3967cb38| plan9 MOVBW.P 182(R25), R25
+abf69438| plan9 MOVB.P -177(R21), R11
+159ed138| plan9 MOVBW.W -231(R16), R21
+b63e8038| plan9 MOVB.W 3(R21), R22
+4491c939| plan9 MOVBW 612(R10), R4
+497e8039| plan9 MOVB 31(R18), R9
+7d6bf638| plan9 MOVBW R22(R27), R29
+e578ba38| plan9 MOVB R26<<1(R7), R5
+9f06ca78| plan9 MOVHW.P 160(R20), ZR
+15c59d78| plan9 MOVH.P -36(R8), R21
+c07fd278| plan9 MOVHW.W -217(R30), R0
+bdec9278| plan9 MOVH.W -210(R5), R29
+10e2c979| plan9 MOVHW 1264(R16), R16
+54d29d79| plan9 MOVH 3816(R18), R20
+eb9484b8| plan9 MOVW.P 73(R7), R11
+ba2e8ab8| plan9 MOVW.W 162(R21), R26
+ac7f8ab9| plan9 MOVW 2684(R29), R12
+f8b941b8| plan9 LDTRW 27(R15), R24
+fc0a4ef8| plan9 LDTR 224(R23), R28
+60d84638| plan9 LDTRBW 109(R3), R0
+44685978| plan9 LDTRHW -106(R2), R4
+5379dc38| plan9 LDTRSBW -57(R10), R19
+ade99538| plan9 LDTRSB -162(R13), R13
+905ac078| plan9 LDTRSHW 5(R20), R16
+10898478| plan9 LDTRSH 72(R8), R16
+37188eb8| plan9 LDTRSW 225(R1), R23
+992351b8| plan9 LDURW -238(R28), R25
+c9f155f8| plan9 LDUR -161(R14), R9
+76e14e38| plan9 LDURBW 238(R11), R22
+47b24478| plan9 LDURHW 75(R18), R7
+4020da38| plan9 LDURSBW -94(R2), R0
+0dd09e38| plan9 LDURSB -19(R0), R13
+8f81d478| plan9 LDURSHW -184(R12), R15
+96918378| plan9 LDURSH 57(R12), R22
+b2e383b8| plan9 LDURSW 62(R29), R18
+d3717f88| plan9 LDXPW (R14), R28, R19
+cb677fc8| plan9 LDXP (R30), R25, R11
+ed7c5f88| plan9 LDXRW (R7), R13
+aa7d5fc8| plan9 LDXR (R13), R10
+1c7d5f08| plan9 LDXRB (R8), R28
+de7f5f48| plan9 LDXRH (R30), R30
+1622dc1a| plan9 LSLW R28, R16, R22
+cd20d59a| plan9 LSL R21, R6, R13
+882957d3| plan9 UBFIZ $41, R12, $11, R8
+3320cc1a| plan9 LSLW R12, R1, R19
+7320de9a| plan9 LSL R30, R3, R19
+af25d31a| plan9 LSRW R19, R13, R15
+e426c39a| plan9 LSR R3, R23, R4
+e87f0653| plan9 LSRW $6, ZR, R8
+85fe5fd3| plan9 LSR $31, R20, R5
+0025dc1a| plan9 LSRW R28, R8, R0
+6e27c79a| plan9 LSR R7, R27, R14
+6d69111b| plan9 MADDW R17, R26, R11, R13
+245d0d9b| plan9 MADD R13, R23, R9, R4
+85fe1f1b| plan9 MNEGW ZR, R20, R5
+9bfc199b| plan9 MNEG R25, R4, R27
+13000011| plan9 ADDW $0, R0, R19
+e3000091| plan9 ADD $0, R7, R3
+986c9e12| plan9 MOVW $4294904987, R24
+cb24f092| plan9 MOVD $9140618393701842943, R11
+3cbb88d2| plan9 MOVD $17881, R28
+e4170232| plan9 MOVW $3221225487, R4
+fe636bb2| plan9 MOVD $70368742080512, R30
+ed031b2a| plan9 MOVW R27, R13
+fb0308aa| plan9 MOVD R8, R27
+be3ed1f2| plan9 MOVK $(35317<<32), R30
+e0a08312| plan9 MOVW $4294959864, R0
+a1a6e592| plan9 MOVD $-3257509905472421889, R1
+5260f0d2| plan9 MOVD $-9006636304787570688, R18
+a60739d5| plan9 MRS $18493, R6
+281a1ed5| plan9 MSR R8, $28881
+10f31b1b| plan9 MSUBW R27, R28, R24, R16
+46b41a9b| plan9 MSUB R26, R13, R2, R6
+ec7f041b| plan9 MULW R4, ZR, R12
+147f009b| plan9 MUL R0, R24, R20
+f67f692a| plan9 MVNW R9>>31, R22
+f2a3f7aa| plan9 MVN R23@>40, R18
+fe8b0bcb| plan9 NEG R11<<34, R30
+fef710eb| plan9 NEGS R16<<61, R30
+e0031b5a| plan9 NGCW R27, R0
+e0031dda| plan9 NGC R29, R0
+f003167a| plan9 NGCSW R22, R16
+e60302fa| plan9 NGCS R2, R6
+1f2003d5| plan9 NOP
+2f51732a| plan9 ORNW R19>>20, R9, R15
+9b0facaa| plan9 ORN R12->3, R28, R27
+efa40032| plan9 ORRW $67044351, R7, R15
+3a0b19b2| plan9 ORR $3848290698112, R25, R26
+4b9ec4aa| plan9 ORR R4@>39, R18, R11
+f5eaa2f9| plan9 PRFM 17872(R23), PSTL3STRM
+85c194f8| plan9 PRFUM -180(R12), PLDL3STRM
+c303c05a| plan9 RBITW R30, R3
+3000c0da| plan9 RBIT R1, R16
+20025fd6| plan9 RET R17
+ec08c05a| plan9 REVW R7, R12
+180cc0da| plan9 REV R0, R24
+4b07c05a| plan9 REV16W R26, R11
+7805c0da| plan9 REV16 R11, R24
+ea08c0da| plan9 REV32 R7, R10
+a90fc0da| plan9 REV R29, R9
+fd788213| plan9 EXTRW $30, R2, R7, R29
+e1a0cc93| plan9 EXTR $40, R12, R7, R1
+792fdc1a| plan9 RORW R28, R27, R25
+2b2cc39a| plan9 ROR R3, R1, R11
+7e2ec71a| plan9 RORW R7, R19, R30
+392edd9a| plan9 ROR R29, R17, R25
+47020a5a| plan9 SBCW R10, R18, R7
+b7021dda| plan9 SBC R29, R21, R23
+7800197a| plan9 SBCSW R25, R3, R24
+1e0203fa| plan9 SBCS R3, R16, R30
+a6b07393| plan9 SBFIZ $13, R5, $45, R6
+94957d93| plan9 SBFIZ $3, R12, $38, R20
+ecff5e93| plan9 ASR $30, ZR, R12
+a50ddb1a| plan9 SDIVW R27, R13, R5
+7c0ec89a| plan9 SDIV R8, R19, R28
+9f2003d5| plan9 SEV
+bf2003d5| plan9 SEVL
+5953349b| plan9 SMADDL R20, R20, R26, R25
+bafc399b| plan9 SMNEGL R25, R5, R26
+a5cc289b| plan9 SMSUBL R8, R19, R5, R5
+297c579b| plan9 SMULH R23, R1, R9
+5e7e299b| plan9 SMULL R9, R18, R30
+29fd9f88| plan9 STLRW R9, (R9)
+fdff9fc8| plan9 STLR R29, (RSP)
+defe9f08| plan9 STLRB R30, (R22)
+2ffc9f48| plan9 STLRH R15, (R1)
+c1e12f88| plan9 STLXPW (R14), R24, R1, R15
+62aa2ec8| plan9 STLXPW (R19), R10, R2, R14
+b9fe1b88| plan9 STLXRW R25, (R21), R27
+cbff14c8| plan9 STLXR R11, (R30), R20
+edfc0608| plan9 STLXRB R13, (R7), R6
+8dfe1048| plan9 STLXRH R13, (R20), R16
+1a323628| plan9 STNPW -80(R16), R12, R26
+b3cb3da8| plan9 STNP -40(R29), R18, R19
+52398828| plan9 STP.P (R18, R14), 64(R10)
+434c95a8| plan9 STP.P (R3, R19), 336(R2)
+2badbd29| plan9 STP.W (R11, R11), -20(R9)
+daeabaa9| plan9 STP.W (R26, R26), -88(R22)
+9bc91529| plan9 STP (R27, R18), 172(R12)
+eea024a9| plan9 STP (R14, R8), -440(R7)
+fec514b8| plan9 MOVW.P R30, -180(R15)
+d21508f8| plan9 MOVD.P R18, 129(R14)
+7c5c0ab8| plan9 MOVW.W R28, 165(R3)
+6dec1ff8| plan9 MOVD.W R13, -2(R3)
+35681eb9| plan9 MOVW R21, 7784(R1)
+374d35f9| plan9 MOVD R23, 27288(R9)
+1b441b38| plan9 MOVB.P R27, -76(R0)
+d69c0f38| plan9 MOVB.W R22, 249(R6)
+b7ce0d39| plan9 MOVB R23, 883(R21)
+2b7b3938| plan9 MOVB R11, R25<<1(R25)
+4e771d78| plan9 MOVH.P R14, -41(R26)
+64cc0b78| plan9 MOVH.W R4, 188(R3)
+07b90279| plan9 MOVH R7, 348(R8)
+2eb91cb8| plan9 STTRW -53(R9), R14
+373a1bf8| plan9 STTR -77(R17), R23
+d0881138| plan9 STTRBW -232(R6), R16
+941a0e78| plan9 STTRHW 225(R20), R20
+da3000b8| plan9 MOVW R26, 3(R6)
+5e921cf8| plan9 MOVD R30, -55(R18)
+09821e38| plan9 MOVB R9, -24(R16)
+67d21c78| plan9 MOVH R7, -51(R19)
+0c352188| plan9 STXPW (R8), R13, R12, R1
+146d26c8| plan9 STXPW (R8), R27, R20, R6
+837d1888| plan9 STXRW R3, (R12), R24
+f17f1bc8| plan9 STXR R17, (RSP), R27
+3b7d0f08| plan9 STXRB R27, (R9), R15
+6b7c1f48| plan9 STXRH R11, (R3), ZR
+70ab204b| plan9 SUBW R0.SXTH<<2, R27, R16
+303b20cb| plan9 SUB R0.UXTH<<6, R25, R16
+69a909d1| plan9 SUB $618, R11, R9
+87384e4b| plan9 SUBW R14>>14, R4, R7
+ec720ecb| plan9 SUB R14<<28, R23, R12
+2b58256b| plan9 SUBSW R5.UXTW<<6, R1, R11
+59e93ceb| plan9 SUBS R28.SXTX<<2, R10, R25
+9e7b6ff1| plan9 SUBS $(3038<<12), R28, R30
+3e6d196b| plan9 SUBSW R25<<27, R9, R30
+54029ceb| plan9 SUBS R28->0, R18, R20
+c1f91cd4| plan9 SVC $59342
+091e0013| plan9 SXTBW R16, R9
+7f1c4093| plan9 SXTB R3, ZR
+b53c0013| plan9 SXTHW R5, R21
+773e4093| plan9 SXTH R19, R23
+707f4093| plan9 SXTW R27, R16
+df3a2dd5| plan9 SYSL $342720, ZR
+5f612972| plan9 TSTW $4286644223, R10
+bf2007f2| plan9 TST $-144115170929541117, R5
+1f11136a| plan9 TSTW R19<<4, R8
+5fd10dea| plan9 TST R13<<52, R10
+5c826bd3| plan9 UBFIZ $21, R18, $33, R28
+ad690c53| plan9 UBFXW $12, R13, $15, R13
+3a0f41d3| plan9 UBFX $1, R25, $3, R26
+6a197dd3| plan9 UBFIZ $3, R11, $7, R10
+520aca1a| plan9 UDIVW R10, R18, R18
+0809c89a| plan9 UDIV R8, R8, R8
+4e55a69b| plan9 UMADDL R6, R21, R10, R14
+99fda59b| plan9 UMNEGL R5, R12, R25
+1adabb9b| plan9 UMSUBL R27, R22, R16, R26
+177ddf9b| plan9 UMULH ZR, R8, R23
+1d7da49b| plan9 UMULL R4, R8, R29
+5a1c0053| plan9 UXTBW R2, R26
+603c0053| plan9 UXTHW R3, R0
+5f2003d5| plan9 WFE
+7f2003d5| plan9 WFI
+3f2003d5| plan9 YIELD
+02b8600e| plan9 VABS V0.H4, V2.H4
+c886f94e| plan9 VADD V25.D2, V22.D2, V8.D2
+5642740e| plan9 VADDHN V20.S4, V18.S4, V22.H4
+3743294e| plan9 VADDHN2 V9.H8, V25.H8, V23.B16
+2abef74e| plan9 VADDP V23.D2, V17.D2, V10.D2
+18bbb14e| plan9 ADDV V24.S4, F24
+1a59284e| plan9 VAESD V8.B16, V26.B16
+cf48284e| plan9 VAESE V6.B16, V15.B16
+557a284e| plan9 VAESIMC V18.B16, V21.B16
+2f6b284e| plan9 VAESMC V25.B16, V15.B16
+cf1c324e| plan9 VAND V18.B16, V6.B16, V15.B16
+c9c6032f| plan9 VMVNI $(118<<136), V9.S2
+f1a7012f| plan9 VMVNI $(63<<8), V17.H4
+691d600e| plan9 VBIC V0.B8, V11.B8, V9.B8
+c31dfe6e| plan9 VBIF V30.B16, V14.B16, V3.B16
+c81cb66e| plan9 VBIT V22.B16, V6.B16, V8.B16
+701f6b2e| plan9 VBSL V11.B8, V27.B8, V16.B8
+7c4b600e| plan9 VCLS V27.H4, V28.H4
+ce4a602e| plan9 VCLZ V22.H4, V14.H4
+d08de37e| plan9 CMEQ F3, F14, F16
+e98db96e| plan9 VCMEQ V25.S4, V15.S4, V9.S4
+6e99a00e| plan9 VCMEQ $0, V11.S2, V14.S2
+933d304e| plan9 VCMGE V16.B16, V12.B16, V19.B16
+0e88e07e| plan9 CMGE $0, F0, F14
+9b89202e| plan9 VCMGE $0, V12.B8, V27.B8
+6a372f4e| plan9 VCMGT V15.B16, V27.B16, V10.B16
+128be05e| plan9 CMGT $0, F24, F18
+9189a00e| plan9 VCMGT $0, V12.S2, V17.S2
+f734e67e| plan9 CMHI F6, F7, F23
+4d36b82e| plan9 VCMHI V24.S2, V18.S2, V13.S2
+003e2b2e| plan9 VCMHS V11.B8, V16.B8, V0.B8
+729ae07e| plan9 CMLE $0, F19, F18
+3699206e| plan9 VCMLE $0, V9.B16, V22.B16
+d1ab600e| plan9 VCMLT $0, V30.H4, V17.H4
+ad8e244e| plan9 VCMTST V4.B16, V21.B16, V13.B16
+ef06035e| plan9 VMOV V23.B[1], F15
+5007040e| plan9 VDUP V26.S[0], V16.S2
+890e0b4e| plan9 VDUP R20, V9.B16
+951c276e| plan9 VEOR V7.B16, V4.B16, V21.B16
+98d4bf7e| plan9 FABD F31, F4, F24
+bcd4ad6e| plan9 VFABD V13.S4, V5.S4, V28.S4
+78f8e04e| plan9 FABS V3.D2, V24.D2
+8cc0201e| plan9 FABSS F4, F12
+9ac1601e| plan9 FABSD F12, F26
+3aee307e| plan9 FACGE F16, F17, F26
+41ed352e| plan9 VFACGE V21.S2, V10.S2, V1.S2
+35edaf7e| plan9 FACGT F15, F9, F21
+02efe36e| plan9 VFACGT V3.D2, V24.D2, V2.D2
+21d6664e| plan9 FADD V6.D2, V17.D2, V1.D2
+5e282e1e| plan9 FADDS F14, F2, F30
+4d2a621e| plan9 FADDD F2, F18, F13
+7cd8707e| plan9 FADDP V3.D2, F28
+5dd4386e| plan9 VFADDP V24.S4, V2.S4, V29.S4
+69363e1e| plan9 FCCMPS LO, F30, F19, $9
+c8b56a1e| plan9 FCCMPD LT, F10, F14, $8
+d1f5271e| plan9 FCCMPES AL, F7, F14, $1
+3645751e| plan9 FCCMPED MI, F21, F9, $6
+21e6735e| plan9 FCMEQ F19, F17, F1
+b6dba05e| plan9 FCMEQ $0, F29, F22
+49d8a04e| plan9 VFCMEQ $0, V2.S4, V9.S4
+2ee5667e| plan9 FCMGE F6, F9, F14
+4ee7766e| plan9 VFCMGE V22.D2, V26.D2, V14.D2
+4bcba07e| plan9 FCMGE $0, F26, F11
+11c9a02e| plan9 VFCMGE $0, V8.S2, V17.S2
+81e4a97e| plan9 FCMGT F9, F4, F1
+d3e4b56e| plan9 VFCMGT V21.S4, V6.S4, V19.S4
+efc8e05e| plan9 FCMGT $0, F7, F15
+3ec9e04e| plan9 VFCMGT $0, V9.D2, V30.D2
+38d9a07e| plan9 FCMLE $0, F9, F24
+7dd9a02e| plan9 VFCMLE $0, V11.S2, V29.S2
+bae8a05e| plan9 FCMLT $0, F5, F26
+a2eaa04e| plan9 VFCMLT $0, V21.S4, V2.S4
+60212f1e| plan9 FCMPS F15, F11
+a8233a1e| plan9 FCMPS $(0.0), F29
+a020641e| plan9 FCMPD F4, F5
+e820701e| plan9 FCMPD $(0.0), F7
+b0203a1e| plan9 FCMPES F26, F5
+78203d1e| plan9 FCMPES $(0.0), F3
+70226e1e| plan9 FCMPED F14, F19
+3821601e| plan9 FCMPED $(0.0), F9
+06de241e| plan9 FCSELS LE, F16, F4, F6
+51de761e| plan9 FCSELD LE, F18, F22, F17
+5e42e21e| plan9 FCVTHS F18, F30
+b9c1e21e| plan9 FCVTHD F13, F25
+58c0231e| plan9 FCVTSH F2, F24
+9bc2221e| plan9 FCVTSD F20, F27
+2bc3631e| plan9 FCVTDH F25, F11
+f640621e| plan9 FCVTDS F7, F22
+caca215e| plan9 FCVTAS F22, F10
+5ec9210e| plan9 VFCVTAS V10.S2, V30.S2
+0302241e| plan9 FCVTASW F16, R3
+c103249e| plan9 FCVTAS F30, R1
+3003641e| plan9 FCVTASW F25, R16
+6201649e| plan9 FCVTAS F11, R2
+d3c9217e| plan9 FCVTAU F14, F19
+3bc8212e| plan9 VFCVTAU V1.S2, V27.S2
+0802251e| plan9 FCVTAUW F16, R8
+5f02259e| plan9 FCVTAU F18, ZR
+2801651e| plan9 FCVTAUW F9, R8
+f200659e| plan9 FCVTAU F7, R18
+d179610e| plan9 VFCVTL V14.S2, V17.D2
+347b614e| plan9 VFCVTL2 V25.S4, V20.D2
+08b9615e| plan9 FCVTMS F8, F8
+f000301e| plan9 FCVTMSW F7, R16
+8002309e| plan9 FCVTMS F20, R0
+5202701e| plan9 FCVTMSW F18, R18
+c803709e| plan9 FCVTMS F30, R8
+1cbb217e| plan9 FCVTMU F24, F28
+d1b9212e| plan9 VFCVTMU V14.S2, V17.S2
+2e02311e| plan9 FCVTMUW F17, R14
+d003319e| plan9 FCVTMU F30, R16
+ce03711e| plan9 FCVTMUW F30, R14
+0801719e| plan9 FCVTMU F8, R8
+4c6b210e| plan9 VFCVTN V26.S4, V12.H4
+6869214e| plan9 VFCVTN2 V11.S4, V8.H8
+2faa615e| plan9 FCVTNS F17, F15
+33aa614e| plan9 VFCVTNS V17.D2, V19.D2
+d303201e| plan9 FCVTNSW F30, R19
+4001209e| plan9 FCVTNS F10, R0
+b202601e| plan9 FCVTNSW F21, R18
+c603609e| plan9 FCVTNS F30, R6
+8ea8217e| plan9 FCVTNU F4, F14
+cc01211e| plan9 FCVTNUW F14, R12
+3a00219e| plan9 FCVTNU F1, R26
+2002611e| plan9 FCVTNUW F17, R0
+ff01619e| plan9 FCVTNU F15, ZR
+1baba15e| plan9 FCVTPS F24, F27
+9d00281e| plan9 FCVTPSW F4, R29
+eb02289e| plan9 FCVTPS F23, R11
+3503681e| plan9 FCVTPSW F25, R21
+4301689e| plan9 FCVTPS F10, R3
+63aba17e| plan9 FCVTPU F27, F3
+caa8a12e| plan9 VFCVTPU V6.S2, V10.S2
+7702291e| plan9 FCVTPUW F19, R23
+b503299e| plan9 FCVTPU F29, R21
+2f03691e| plan9 FCVTPUW F25, R15
+5b01699e| plan9 FCVTPU F10, R27
+7369617e| plan9 FCVTXN F11, F19
+6b6b612e| plan9 VFCVTXN V27.D2, V11.S2
+f268616e| plan9 VFCVTXN2 V7.D2, V18.S4
+bcff7b5f| plan9 FCVTZS $5, F29, F28
+19bbe15e| plan9 FCVTZSDD F24, F25
+c6b9e14e| plan9 FCVTZS V14.D2, V6.D2
+e9fc189e| plan9 FCVTZS $1, F7, R9
+6661589e| plan9 FCVTZS $40, F11, R6
+9702381e| plan9 FCVTZSSW F20, R23
+ed00389e| plan9 FCVTZSS F7, R13
+3a01781e| plan9 FCVTZSDW F9, R26
+8801789e| plan9 FCVTZSD F12, R8
+a5ff2e2f| plan9 FCVTZU $18, V29.S2, V5.S2
+5bbbe17e| plan9 FCVTZUDD F26, F27
+1a74199e| plan9 FCVTZU $35, F0, R26
+e391599e| plan9 FCVTZU $28, F15, R3
+b203391e| plan9 FCVTZUSW F29, R18
+ed01399e| plan9 FCVTZUS F15, R13
+c200791e| plan9 FCVTZUDW F6, R2
+5402799e| plan9 FCVTZUD F18, R20
+1aff2b6e| plan9 FDIV V11.S4, V24.S4, V26.S4
+171a391e| plan9 FDIVS F25, F16, F23
+7d196b1e| plan9 FDIVD F11, F11, F29
+f9721f1f| plan9 FMADD F28, F31, F23, F25
+7070551f| plan9 FMADD F28, F21, F3, F16
+05f7624e| plan9 FMAX V2.D2, V24.D2, V5.D2
+88493d1e| plan9 FMAXS F29, F12, F8
+4a496d1e| plan9 FMAXD F13, F10, F10
+5068321e| plan9 FMAXNMS F18, F2, F16
+a66a761e| plan9 FMAXNMD F22, F21, F6
+0ccb707e| plan9 FMAXNMP V24.D2, F12
+6ec66f6e| plan9 VFMAXNMP V15.D2, V19.D2, V14.D2
+41f8307e| plan9 FMAXP V2.S2, F1
+05f72a6e| plan9 VFMAXP V10.S4, V24.S4, V5.S4
+aa5b231e| plan9 FMINS F3, F29, F10
+d6596a1e| plan9 FMIND F10, F14, F22
+15c4b24e| plan9 FMINNM V18.S4, V0.S4, V21.S4
+6279281e| plan9 FMINNMS F8, F11, F2
+af7b6a1e| plan9 FMINNMD F10, F29, F15
+7dc9f07e| plan9 FMINNMP V11.D2, F29
+dfc6bb6e| plan9 VFMINNMP V27.S4, V22.S4, V31.S4
+56c8b06e| plan9 FMINNMV V2.S4, F22
+0ff8f07e| plan9 FMINP V0.D2, F15
+a211c55f| plan9 FMLA V5.D[0], F13, F2
+0dce224e| plan9 VFMLA V2.S4, V16.S4, V13.S4
+4c5ba15f| plan9 FMLS V1.S[3], F26, F12
+8953ba0f| plan9 VFMLS V26.S[1], V28.S2, V9.S2
+09cdbd4e| plan9 VFMLS V29.S4, V8.S4, V9.S4
+97f7044f| plan9 FMOV $-7., V23.S4
+dff4006f| plan9 FMOV $2.75, V31.D2
+c543201e| plan9 FMOVS F30, F5
+1740601e| plan9 FMOVD F0, F23
+a100271e| plan9 FMOVS R5, F1
+f102261e| plan9 FMOVS F23, R17
+b302679e| plan9 FMOVD R21, F19
+4001af9e| plan9 FMOV R10, V0.D[1]
+db01669e| plan9 FMOVD F14, R27
+8300ae9e| plan9 FMOV V4.D[1], R3
+1870331e| plan9 FMOVS $-6.75, F24
+08507d1e| plan9 FMOVD $-0.8125, F8
+5cbf0c1f| plan9 FMSUB F15, F12, F26, F28
+89e3501f| plan9 FMSUB F24, F16, F28, F9
+3a93c95f| plan9 FMULD V9.D[0], F25, F26
+5a90ae4f| plan9 FMUL V14.S[1], V2.S4, V26.S4
+ba0a2f1e| plan9 FMULS F15, F21, F26
+5b0a7c1e| plan9 FMULD F28, F18, F27
+e991c07f| plan9 FMULX V0.D[0], F15, F9
+be989c6f| plan9 VFMULX V28.S[2], V5.S4, V30.S4
+d3dc7a5e| plan9 FMULX F26, F6, F19
+d4de7f4e| plan9 VFMULX V31.D2, V22.D2, V20.D2
+8e41211e| plan9 FNEGS F12, F14
+dc42611e| plan9 FNEGD F22, F28
+cb362e1f| plan9 FNMADD F13, F14, F22, F11
+6441791f| plan9 FNMADD F16, F25, F11, F4
+36ed291f| plan9 FNMSUB F27, F9, F9, F22
+35b27a1f| plan9 FNMSUB F12, F26, F17, F21
+9388301e| plan9 FNMULS F16, F4, F19
+c088711e| plan9 FNMULD F17, F6, F0
+e8daa15e| plan9 FRECPE F23, F8
+a9fc395e| plan9 FRECPS F25, F5, F9
+49fe284e| plan9 VFRECPS V8.S4, V18.S4, V9.S4
+85f8a15e| plan9 FRECPX F4, F5
+ee43261e| plan9 FRINTAS F31, F14
+7042661e| plan9 FRINTAD F19, F16
+2b98a16e| plan9 FRINTI V1.S4, V11.S4
+fac2271e| plan9 FRINTIS F23, F26
+76c3671e| plan9 FRINTID F27, F22
+7942251e| plan9 FRINTMS F19, F25
+8742651e| plan9 FRINTMD F20, F7
+fc8a214e| plan9 FRINTN V23.S4, V28.S4
+c041241e| plan9 FRINTNS F14, F0
+b241641e| plan9 FRINTND F13, F18
+c588a14e| plan9 FRINTP V6.S4, V5.S4
+6ec2241e| plan9 FRINTPS F19, F14
+ddc0641e| plan9 FRINTPD F6, F29
+1a9a616e| plan9 FRINTX V16.D2, V26.D2
+7c41271e| plan9 FRINTXS F11, F28
+d243671e| plan9 FRINTXD F30, F18
+b49aa14e| plan9 FRINTZ V21.S4, V20.S4
+5bc0251e| plan9 FRINTZS F2, F27
+43c1651e| plan9 FRINTZD F10, F3
+3bdba17e| plan9 FRSQRTE F25, F27
+9ddba12e| plan9 VFRSQRTE V28.S2, V29.S2
+1ffee65e| plan9 FRSQRTS F6, F16, F31
+8bfdb54e| plan9 VFRSQRTS V21.S4, V12.S4, V11.S4
+33c1211e| plan9 FSQRTS F9, F19
+a5c0611e| plan9 FSQRTD F5, F5
+a2d7b74e| plan9 FSUB V23.S4, V29.S4, V2.S4
+a338301e| plan9 FSUBS F16, F5, F3
+e139681e| plan9 FSUBD F8, F15, F1
+96170e6e| plan9 VMOV V28.H[1], V22.H[3]
+791c014e| plan9 VMOV R3, V25.B[0]
+cf79404c| plan9 VLD1 (R14), [V15.S4]
+75a6404c| plan9 VLD1 (R19), [V21.H8, V22.H8]
+ed62404c| plan9 VLD1 (R23), [V13.B16, V14.B16, V15.B16]
+392a400c| plan9 VLD1 (R17), [V25.S2, V26.S2, V27.S2, V28.S2]
+cd7cdf4c| plan9 VLD1.P 16(R6), [V13.D2]
+f677ce4c| plan9 VLD1.P (RSP)(R14), [V22.H8]
+d4a3df0c| plan9 VLD1.P 16(R30), [V20.B8, V21.B8]
+8ba1d90c| plan9 VLD1.P (R12)(R25), [V11.B8, V12.B8]
+396fdf0c| plan9 VLD1.P 24(R25), [V25.D1, V26.D1, V27.D1]
+4c64db0c| plan9 VLD1.P (R2)(R27), [V12.H4, V13.H4, V14.H4]
+3f2adf4c| plan9 VLD1.P 64(R17), [V31.S4, V0.S4, V1.S4, V2.S4]
+b329ce4c| plan9 VLD1.P (R13)(R14), [V19.S4, V20.S4, V21.S4, V22.S4]
+aa02400d| plan9 LD1 (R21), [V10.B][0]
+7980404d| plan9 LD1 (R3), [V25.S][2]
+5884404d| plan9 LD1 (R2), [V24.D][1]
+f203df4d| plan9 LD1.P 1(RSP), [V18.B][8]
+3519c40d| plan9 LD1.P (R9)(R4), [V21.B][6]
+ed59df0d| plan9 LD1.P 2(R15), [V13.H][3]
+9e52d90d| plan9 LD1.P (R20)(R25), [V30.H][2]
+cd93df4d| plan9 LD1.P 4(R30), [V13.S][3]
+5982cb4d| plan9 LD1.P (R18)(R11), [V25.S][2]
+4f84df4d| plan9 LD1.P 8(R2), [V15.D][1]
+2d85d50d| plan9 LD1.P (R9)(R21), [V13.D][0]
+33c2400d| plan9 VLD1R (R17), [V19.B8]
+e2c8df4d| plan9 VLD1R 4(R7), [V2.S4]
+83c2c44d| plan9 VLD1R (R20)(R4), [V3.B16]
+5487400c| plan9 VLD2 (R26), [V20.H4, V21.H4]
+e08adf0c| plan9 VLD2 16(R23), [V0.S2, V1.S2]
+768ac40c| plan9 VLD2 (R19)(R4), [V22.S2, V23.S2]
+4c0f604d| plan9 LD2 (R26), [V12.B, V13.B][11]
+e043604d| plan9 LD2 (RSP), [V0.H, V1.H][4]
+c281600d| plan9 LD2 (R14), [V2.S, V3.S][0]
+e585600d| plan9 LD2 (R15), [V5.D, V6.D][0]
+2c1aff4d| plan9 LD2 2(R17), [V12.B, V13.B][14]
+820bfd4d| plan9 LD2 (R28)(R29), [V2.B, V3.B][10]
+d593ff0d| plan9 LD2 8(R30), [V21.S, V22.S][1]
+6780ea0d| plan9 LD2 (R3)(R10), [V7.S, V8.S][0]
+3484ff4d| plan9 LD2 16(R1), [V20.D, V21.D][1]
+6a86ee4d| plan9 LD2 (R19)(R14), [V10.D, V11.D][1]
+e4c7604d| plan9 VLD2R (RSP), [V4.H8, V5.H8]
+69c8ff0d| plan9 VLD2R 8(R3), [V9.S2, V10.S2]
+52ccf30d| plan9 VLD2R (R2)(R19), [V18.D1, V19.D1]
+9e4b404c| plan9 VLD3 (R28), [V30.S4, V31.S4, V0.S4]
+0440df4c| plan9 VLD3 48(R0), [V4.B16, V5.B16, V6.B16]
+0f49cf0c| plan9 VLD3 (R8)(R15), [V15.S2, V16.S2, V17.S2]
+b22e400d| plan9 LD3 (R21), [V18.B, V19.B, V20.B][3]
+9473400d| plan9 LD3 (R28), [V20.H, V21.H, V22.H][2]
+1da0404d| plan9 LD3 (R0), [V29.S, V30.S, V31.S][2]
+21a5404d| plan9 LD3 (R9), [V1.D, V2.D, V3.D][1]
+3b23df0d| plan9 LD3 3(R25), [V27.B, V28.B, V29.B][0]
+0937c60d| plan9 LD3 (R24)(R6), [V9.B, V10.B, V11.B][5]
+926bcb4d| plan9 LD3 (R28)(R11), [V18.H, V19.H, V20.H][5]
+f5a1df4d| plan9 LD3 12(R15), [V21.S, V22.S, V23.S][2]
+dba3c44d| plan9 LD3 (R30)(R4), [V27.S, V28.S, V29.S][2]
+12a5df0d| plan9 LD3 24(R8), [V18.D, V19.D, V20.D][0]
+daa7d30d| plan9 LD3 (R30)(R19), [V26.D, V27.D, V28.D][0]
+3beb400d| plan9 VLD3R (R25), [V27.S2, V28.S2, V29.S2]
+cde4df4d| plan9 VLD3R 6(R6), [V13.H8, V14.H8, V15.H8]
+a4efc44d| plan9 VLD3R (R29)(R4), [V4.D2, V5.D2, V6.D2]
+fc0a400c| plan9 VLD4 (R23), [V28.S2, V29.S2, V30.S2, V31.S2]
+ae05df0c| plan9 VLD4 32(R13), [V14.H4, V15.H4, V16.H4, V17.H4]
+cb07c84c| plan9 VLD4 (R30)(R8), [V11.H8, V12.H8, V13.H8, V14.H8]
+1825604d| plan9 LD4 (R8), [V24.B, V25.B, V26.B, V27.B][9]
+2869604d| plan9 LD4 (R9), [V8.H, V9.H, V10.H, V11.H][5]
+07b2600d| plan9 LD4 (R16), [V7.S, V8.S, V9.S, V10.S][1]
+9fa4600d| plan9 LD4 (R4), [V31.D, V0.D, V1.D, V2.D][0]
+de22ff0d| plan9 LD4 4(R22), [V30.B, V31.B, V0.B, V1.B][0]
+6a36ed4d| plan9 LD4 (R19)(R13), [V10.B, V11.B, V12.B, V13.B][13]
+23a2ff4d| plan9 LD4 16(R17), [V3.S, V4.S, V5.S, V6.S][2]
+22a0fe4d| plan9 LD4 (R1)(R30), [V2.S, V3.S, V4.S, V5.S][2]
+7ca4ff4d| plan9 LD4 32(R3), [V28.D, V29.D, V30.D, V31.D][1]
+03a7ec4d| plan9 LD4 (R24)(R12), [V3.D, V4.D, V5.D, V6.D][1]
+b9ee600d| plan9 VLD4R (R21), [V25.D1, V26.D1, V27.D1, V28.D1]
+03e8ff0d| plan9 VLD4R 16(R0), [V3.S2, V4.S2, V5.S2, V6.S2]
+e7e3f24d| plan9 VLD4R (RSP)(R18), [V7.B16, V8.B16, V9.B16, V10.B16]
+451a4e2c| plan9 LDNP 112(R18), F6, F5
+01236f6c| plan9 LDNP -272(R24), F8, F1
+204041ac| plan9 LDNP 32(R1), V16, V0
+1b21cc2c| plan9 LDP.P 96(R8), (F27, F8)
+41ccc06c| plan9 LDP.P 8(R2), (F1, F19)
+65b8e6ac| plan9 LDP.P -816(R3), (V5, V14)
+a58bed2d| plan9 LDP.W -148(R29), (F5, F2)
+d8a3c46d| plan9 LDP.W 72(R30), (F24, F8)
+dc82c0ad| plan9 LDP.W 16(R22), (V28, V0)
+eda7782d| plan9 LDP -60(RSP), (F13, F9)
+041b6c6d| plan9 LDP -320(R24), (F4, F6)
+17ea6bad| plan9 LDP -656(R16), (V23, V26)
+4e14433c| plan9 MOVD.P 49(R2), F14
+cd844e7c| plan9 MOVD.P 232(R6), F13
+99945dbc| plan9 MOVD.P -39(R4), F25
+170556fc| plan9 MOVD.P -160(R8), F23
+3115d53c| plan9 MOVD.P -175(R9), V17
+3c6d403c| plan9 MOVD.W 6(R9), F28
+f8fc527c| plan9 MOVD.W -209(R7), F24
+776c58bc| plan9 MOVD.W -122(R3), F23
+075f57fc| plan9 MOVD.W -139(R24), F7
+28cdc33c| plan9 MOVD.W 60(R9), V8
+40a15f3d| plan9 MOVD 2024(R10), F0
+3b8c597d| plan9 MOVD 3270(R1), F27
+28f958bd| plan9 MOVD 6392(R9), F8
+852d6ffd| plan9 MOVD 24152(R12), F5
+e149ea3d| plan9 MOVD 43296(R15), V1
+8d69623c| plan9 MOVD R2(R12), F13
+1a60553c| plan9 LDUR -170(R0), F26
+74f3477c| plan9 LDUR 127(R27), F20
+f46249bc| plan9 LDUR 150(R23), F20
+b8015bfc| plan9 LDUR -80(R13), F24
+3372de3c| plan9 LDUR -25(R17), V19
+04972c0e| plan9 VMLA V12.B8, V24.B8, V4.B8
+f0051b5e| plan9 VMOV V15.B[13], F16
+7f76146e| plan9 VMOV V19.S[3], V31.S[2]
+6c1cb60e| plan9 VORR V22.B8, V3.B8, V12.B8
+ae3f1e0e| plan9 UMOVW V29.H[7], R14
+f8e5004f| plan9 VMOVI $15, V24.B16
+0355010f| plan9 VORR $(40<<16), V3.S2
+4825020f| plan9 VMOVI $(74<<8), V8.S2
+64d7040f| plan9 VMOVI $(155<<144), V4.S2
+46e6062f| plan9 MOVI $-280379759984896, F6
+bde6056f| plan9 VMOVI $-71776123339472641, V29.D2
+789f350e| plan9 VMUL V21.B8, V27.B8, V24.B8
+7b5b202e| plan9 VMVN V27.B8, V27.B8
+2dd4066f| plan9 VMVNI $(193<<144), V13.S4
+8266012f| plan9 VMVNI $(52<<24), V2.S2
+1025022f| plan9 VMVNI $(72<<8), V16.S2
+eabba06e| plan9 VNEG V31.S4, V10.S4
+7e5a206e| plan9 VMVN V19.B16, V30.B16
+6a1fea0e| plan9 VORN V10.B8, V27.B8, V10.B8
+b406010f| plan9 VMOVI $53, V20.S2
+f564040f| plan9 VMOVI $(135<<24), V21.S2
+b21cb80e| plan9 VORR V24.B8, V5.B8, V18.B8
+2b437a2e| plan9 VRADDHN V26.S4, V25.S4, V11.H4
+6d402c6e| plan9 VRADDHN2 V12.H8, V3.H8, V13.B16
+655a606e| plan9 VRBIT V19.B16, V5.B16
+5108202e| plan9 VREV32 V2.B8, V17.B8
+750a200e| plan9 VREV64 V19.B8, V21.B8
+f88f0b0f| plan9 VRSHRN $5, V31.H8, V24.B8
+8263236e| plan9 VRSUBHN2 V3.H8, V28.H8, V2.B16
+787c320e| plan9 VSABA V18.B8, V3.B8, V24.B8
+f551220e| plan9 VSABAL V2.B8, V15.B8, V21.H8
+b5766d0e| plan9 VSABD V13.H4, V21.H4, V21.H4
+9270240e| plan9 VSABDL V4.B8, V4.B8, V18.H8
+4d71384e| plan9 VSABDL2 V24.B16, V10.B16, V13.H8
+8f6a600e| plan9 VSADALP V20.H4, V15.S2
+e501750e| plan9 VSADDL V21.H4, V15.H4, V5.S4
+5202ab4e| plan9 VSADDL2 V11.S4, V18.S4, V18.D2
+7029200e| plan9 VSADDLP V11.B8, V16.H4
+3913710e| plan9 VSADDW V17.H4, V25.S4, V25.S4
+d7e4575f| plan9 SCVTF $41, F6, F23
+c6db215e| plan9 SCVTFSS F30, F6
+17d8214e| plan9 SCVTF V0.S4, V23.S4
+62c4021e| plan9 SCVTF $15, R3, F2
+f5cd421e| plan9 SCVTF $13, R15, F21
+6128029e| plan9 SCVTF $54, R3, F1
+9a7c429e| plan9 SCVTF $33, R4, F26
+6102221e| plan9 SCVTFWS R19, F1
+0b03621e| plan9 SCVTFWD R24, F11
+ed01229e| plan9 SCVTFS R15, F13
+6f02629e| plan9 SCVTFD R19, F15
+ac03055e| plan9 SHA1C V5.S4, F29, V12
+e309285e| plan9 SHA1H F15, F3
+2a221b5e| plan9 SHA1M V27.S4, F17, V10
+a013185e| plan9 SHA1P V24.S4, F29, V0
+6032005e| plan9 VSHA1SU0 V0.S4, V19.S4, V0.S4
+f918285e| plan9 VSHA1SU1 V7.S4, V25.S4
+fb50035e| plan9 SHA256H2 V3.S4, V7, V27
+6d421c5e| plan9 SHA256H V28.S4, V19, V13
+c12b285e| plan9 VSHA256SU0 V30.S4, V1.S4
+6362095e| plan9 VSHA256SU1 V9.S4, V19.S4, V3.S4
+a805bb0e| plan9 VSHADD V27.S2, V13.S2, V8.S2
+783b616e| plan9 VSHLL2 $16, V27.H8, V24.S4
+48841b0f| plan9 VSHRN $5, V2.S4, V8.H4
+a924bc4e| plan9 VSHSUB V28.S4, V5.S4, V9.S4
+1557717f| plan9 SLI $49, F24, F21
+2a56456f| plan9 VSLI $5, V17.D2, V10.D2
+7c663b0e| plan9 VSMAX V27.B8, V19.B8, V28.B8
+b5a7694e| plan9 VSMAXP V9.H8, V29.H8, V21.H8
+8ea8b04e| plan9 SMAXV V4.S4, F14
+936cb44e| plan9 VSMIN V20.S4, V4.S4, V19.S4
+15af7e4e| plan9 VSMINP V30.H8, V24.H8, V21.H8
+3e81694e| plan9 VSMLAL2 V9.H8, V9.H8, V30.S4
+29a26d0e| plan9 VSMLSL V13.H4, V17.H4, V9.S4
+442e0b4e| plan9 SMOV V18.B[5], R4
+e1a0540f| plan9 VSMULL V4.H[1], V7.H4, V1.S4
+5eaa604f| plan9 VSMULL2 V0.H[6], V18.H8, V30.S4
+4cc32d4e| plan9 VSMULL2 V13.B16, V26.B16, V12.H8
+1e7a205e| plan9 SQABS F16, F30
+e67ae04e| plan9 VSQABS V23.D2, V6.D2
+a80ded5e| plan9 SQADD F13, F13, F8
+e60dae4e| plan9 VSQADD V14.S4, V15.S4, V6.S4
+fe33570f| plan9 VSQDMLAL V7.H[1], V31.H4, V30.S4
+ee90b64e| plan9 VSQDMLAL2 V22.S4, V7.S4, V14.D2
+ce79a05f| plan9 SQDMLSL V0.S[3], F14, F14
+d5b2a14e| plan9 VSQDMLSL2 V1.S4, V22.S4, V21.D2
+51cb575f| plan9 SQDMULH V7.H[5], F26, F17
+0cb5b54e| plan9 VSQDMULH V21.S4, V8.S4, V12.S4
+95d0760e| plan9 VSQDMULL V22.H4, V4.H4, V21.S4
+a1d37c4e| plan9 VSQDMULL2 V28.H8, V29.H8, V1.S4
+d679e07e| plan9 SQNEG F14, F22
+3f78602e| plan9 VSQNEG V1.H4, V31.H4
+80b4717e| plan9 SQRDMULH F17, F4, F0
+4cb76e2e| plan9 VSQRDMULH V14.H4, V26.H4, V12.H4
+aa5ce95e| plan9 SQRSHL F9, F5, F10
+d25fb74e| plan9 VSQRSHL V23.S4, V30.S4, V18.S4
+998c0c6f| plan9 VSQRSHRUN2 $4, V4.H8, V25.B16
+4375605f| plan9 SQSHL $32, F10, F3
+de743f0f| plan9 VSQSHL $31, V6.S2, V30.S2
+a84d675e| plan9 SQSHL F7, F13, F8
+674dbe4e| plan9 VSQSHL V30.S4, V11.S4, V7.S4
+5165587f| plan9 SQSHLU $24, F10, F17
+b464042f| plan9 VMVNI $(133<<24), V20.S2
+2086207f| plan9 SQSHRUN $32, F17, F0
+8a851a2f| plan9 VSQSHRUN $6, V12.S4, V10.H4
+652c255e| plan9 SQSUB F5, F3, F5
+632eb30e| plan9 VSQSUB V19.S2, V19.S2, V3.S2
+104ba15e| plan9 SQXTN F24, F16
+2249214e| plan9 VSQXTN2 V9.H8, V2.B16
+1c14360e| plan9 VSRHADD V22.B8, V0.B8, V28.B8
+8044076f| plan9 VMVNI $(228<<16), V0.S4
+3a57ed5e| plan9 SRSHL F13, F25, F26
+2c56ef4e| plan9 VSRSHL V15.D2, V17.D2, V12.D2
+9627140f| plan9 VSRSHR $12, V28.H4, V22.H4
+bd37565f| plan9 SRSRA $42, F29, F29
+db34594f| plan9 VSRSRA $39, V6.D2, V27.D2
+4546a10e| plan9 VSSHL V1.S2, V18.S2, V5.S2
+aca7020f| plan9 VMOVI $(93<<8), V12.H4
+e004675f| plan9 SSHR $25, F7, F0
+e5057f4f| plan9 VSSHR $1, V15.D2, V5.D2
+1b15595f| plan9 SSRA $39, F8, F27
+ba15250f| plan9 VSSRA $27, V13.S2, V26.S2
+3620330e| plan9 VSSUBL V19.B8, V1.B8, V22.H8
+c1316d4e| plan9 VSSUBW2 V13.H8, V14.S4, V1.S4
+8a76000c| plan9 VST1 (R20), [V10.H4]
+10a5004c| plan9 VST1 (R8), [V16.H8, V17.H8]
+ab6b004c| plan9 VST1 (R29), [V11.S4, V12.S4, V13.S4]
+8d2b004c| plan9 VST1 (R28), [V13.S4, V14.S4, V15.S4, V16.S4]
+8d7d9f0c| plan9 VST1 8(R12), [V13.D1]
+eb73840c| plan9 VST1 (RSP)(R4), [V11.B8]
+48a69f4c| plan9 VST1 32(R18), [V8.H8, V9.H8]
+dca19b4c| plan9 VST1 (R14)(R27), [V28.B16, V29.B16]
+7c699f4c| plan9 VST1 48(R11), [V28.S4, V29.S4, V30.S4]
+da6d870c| plan9 VST1 (R14)(R7), [V26.D1, V27.D1, V28.D1]
+7f279f0c| plan9 VST1 32(R27), [V31.H4, V0.H4, V1.H4, V2.H4]
+4421810c| plan9 VST1 (R10)(R1), [V4.B8, V5.B8, V6.B8, V7.B8]
+a615004d| plan9 ST1 (R13), [V6.B][13]
+ce92000d| plan9 ST1 (R22), [V14.S][1]
+c985000d| plan9 ST1 (R14), [V9.D][0]
+380f9f0d| plan9 ST1 1(R25), [V24.B][3]
+de0b944d| plan9 ST1 (R30)(R20), [V30.B][10]
+3141880d| plan9 ST1 (R9)(R8), [V17.H][0]
+8e939f0d| plan9 ST1 4(R28), [V14.S][1]
+c890870d| plan9 ST1 (R6)(R7), [V8.S][1]
+9f869f4d| plan9 ST1 8(R20), [V31.D][1]
+38879b4d| plan9 ST1 (R25)(R27), [V24.D][1]
+4181004c| plan9 VST2 (R10), [V1.B16, V2.B16]
+d6819f0c| plan9 VST2 16(R14), [V22.B8, V23.B8]
+bf808a0c| plan9 VST2 (R5)(R10), [V31.B8, V0.B8]
+bd0e204d| plan9 ST2 (R21), [V29.B, V30.B][11]
+4551204d| plan9 ST2 (R10), [V5.H, V6.H][6]
+9982204d| plan9 ST2 (R20), [V25.S, V26.S][2]
+ea86200d| plan9 ST2 (R23), [V10.D, V11.D][0]
+7b02bf0d| plan9 ST2 2(R19), [V27.B, V28.B][0]
+c000a04d| plan9 ST2 (R6)(R0), [V0.B, V1.B][8]
+fb59a40d| plan9 ST2 (R15)(R4), [V27.H, V28.H][3]
+f880bf0d| plan9 ST2 8(R7), [V24.S, V25.S][0]
+f582ac4d| plan9 ST2 (R23)(R12), [V21.S, V22.S][2]
+9c86bf4d| plan9 ST2 16(R20), [V28.D, V29.D][1]
+3386b14d| plan9 ST2 (R17)(R17), [V19.D, V20.D][1]
+c0469f0c| plan9 VST3 24(R22), [V0.H4, V1.H4, V2.H4]
+2243820c| plan9 VST3 (R25)(R2), [V2.B8, V3.B8, V4.B8]
+c629000d| plan9 ST3 (R14), [V6.B, V7.B, V8.B][2]
+4f6a004d| plan9 ST3 (R18), [V15.H, V16.H, V17.H][5]
+72a0004d| plan9 ST3 (R3), [V18.S, V19.S, V20.S][2]
+c1a4000d| plan9 ST3 (R6), [V1.D, V2.D, V3.D][0]
+312e9f0d| plan9 ST3 3(R17), [V17.B, V18.B, V19.B][3]
+9a28934d| plan9 ST3 (R4)(R19), [V26.B, V27.B, V28.B][10]
+a1799f4d| plan9 ST3 6(R13), [V1.H, V2.H, V3.H][7]
+3ba29f0d| plan9 ST3 12(R17), [V27.S, V28.S, V29.S][0]
+80b2870d| plan9 ST3 (R20)(R7), [V0.S, V1.S, V2.S][1]
+f6a49f4d| plan9 ST3 24(R7), [V22.D, V23.D, V24.D][1]
+8fa69a4d| plan9 ST3 (R20)(R26), [V15.D, V16.D, V17.D][1]
+ee09000c| plan9 VST4 (R15), [V14.S2, V15.S2, V16.S2, V17.S2]
+1e07880c| plan9 VST4 (R24)(R8), [V30.H4, V31.H4, V0.H4, V1.H4]
+6426204d| plan9 ST4 (R19), [V4.B, V5.B, V6.B, V7.B][9]
+4ea2204d| plan9 ST4 (R18), [V14.S, V15.S, V16.S, V17.S][2]
+05a6200d| plan9 ST4 (R16), [V5.D, V6.D, V7.D, V8.D][0]
+5b21bf0d| plan9 ST4 4(R10), [V27.B, V28.B, V29.B, V30.B][0]
+ce28a00d| plan9 ST4 (R6)(R0), [V14.B, V15.B, V16.B, V17.B][2]
+767bbf4d| plan9 ST4 8(R27), [V22.H, V23.H, V24.H, V25.H][7]
+747aa24d| plan9 ST4 (R19)(R2), [V20.H, V21.H, V22.H, V23.H][7]
+24b0bf0d| plan9 ST4 16(R1), [V4.S, V5.S, V6.S, V7.S][1]
+c7b1a90d| plan9 ST4 (R14)(R9), [V7.S, V8.S, V9.S, V10.S][1]
+9fa4bf4d| plan9 ST4 32(R4), [V31.D, V0.D, V1.D, V2.D][1]
+70a4ab4d| plan9 ST4 (R3)(R11), [V16.D, V17.D, V18.D, V19.D][1]
+89fe2e2c| plan9 STNP -140(R20), F31, F9
+bfd31d6c| plan9 STNP 472(R29), F20, F31
+ddf301ac| plan9 STNP 48(R30), V28, V29
+14f6ac2c| plan9 STP.P (F20, F29), -156(R16)
+251db76c| plan9 STP.P (F5, F7), -144(R9)
+e51fb7ac| plan9 STP.P (V5, V7), -288(RSP)
+5c90852d| plan9 STP.W (F28, F4), 44(R2)
+4c51a56d| plan9 STP.W (F12, F20), -432(R10)
+265d8aad| plan9 STP.W (V6, V23), 320(R9)
+9c0c392d| plan9 STP (F28, F3), -56(R4)
+b49e1e6d| plan9 STP (F20, F7), 488(R21)
+55f105ad| plan9 STP (V21, V28), 176(R10)
+4dd6003c| plan9 MOVD.P F13, 13(R18)
+e357067c| plan9 MOVD.P F3, 101(RSP)
+f6841dbc| plan9 MOVD.P F22, -40(R7)
+54b710fc| plan9 MOVD.P F20, -245(R26)
+0d07833c| plan9 MOVD.P V13, 48(R24)
+393f003c| plan9 MOVD.W F25, 3(R25)
+1fac007c| plan9 MOVD.W F31, 10(R0)
+d41d13bc| plan9 MOVD.W F20, -207(R14)
+908f0dfc| plan9 MOVD.W F16, 216(R28)
+5ded9d3c| plan9 MOVD.W V29, -34(R10)
+6d72073d| plan9 MOVD F13, 476(R19)
+68752d7d| plan9 MOVD F8, 5818(R11)
+084728bd| plan9 MOVD F8, 10308(R24)
+409503fd| plan9 MOVD F0, 1832(R10)
+58a1963d| plan9 MOVD V24, 23168(R10)
+967b313c| plan9 MOVD F22, R17<<1(R28)
+b4683e7c| plan9 MOVD F20, R30(R5)
+e5e1143c| plan9 MOVD F5, -178(R15)
+99901e7c| plan9 MOVD F25, -23(R4)
+bb0012bc| plan9 MOVD F27, -224(R5)
+1d710cfc| plan9 MOVD F29, 199(R8)
+17e1873c| plan9 MOVD V23, 126(R8)
+ed84a26e| plan9 VSUB V2.S4, V7.S4, V13.S4
+7761b80e| plan9 VSUBHN V24.D2, V11.D2, V23.S2
+f838205e| plan9 SUQADD F7, F24
+7739600e| plan9 VSUQADD V11.H4, V23.H4
+26a5204f| plan9 VSXTL2 V9.S4, V6.D2
+5a201a4e| plan9 VTBL V26.B16, [V2.B16, V3.B16], V26.B16
+c2400f0e| plan9 VTBL V15.B8, [V6.B16, V7.B16, V8.B16], V2.B8
+7263024e| plan9 VTBL V2.B16, [V27.B16, V28.B16, V29.B16, V30.B16], V18.B16
+bb010b4e| plan9 VTBL V11.B16, [V13.B16], V27.B16
+5f31184e| plan9 VTBX V24.B16, [V10.B16, V11.B16], V31.B16
+a952100e| plan9 VTBX V16.B8, [V21.B16, V22.B16, V23.B16], V9.B8
+4872170e| plan9 VTBX V23.B8, [V18.B16, V19.B16, V20.B16, V21.B16], V8.B8
+dc110e4e| plan9 VTBX V14.B16, [V14.B16], V28.B16
+d7289a4e| plan9 VTRN1 V26.S4, V6.S4, V23.S4
+cd6a924e| plan9 VTRN2 V18.S4, V22.S4, V13.S4
+a552392e| plan9 VUABAL V25.B8, V21.B8, V5.H8
+a653256e| plan9 VUABAL2 V5.B16, V29.B16, V6.H8
+fb70b42e| plan9 VUABDL V20.S2, V7.S2, V27.D2
+3b6a202e| plan9 VUADALP V17.B8, V27.H4
+8a03b22e| plan9 VUADDL V18.S2, V28.S2, V10.D2
+262a206e| plan9 VUADDLP V17.B16, V6.H8
+8410312e| plan9 VUADDW V17.B8, V4.H8, V4.H8
+bf11ae6e| plan9 VUADDW2 V14.S4, V13.D2, V31.D2
+a7e65d7f| plan9 UCVTF $35, F21, F7
+8bda617e| plan9 UCVTFDD F20, F11
+7fb8431e| plan9 UCVTF $18, R3, F31
+1c0f039e| plan9 UCVTF $61, R24, F28
+2241439e| plan9 UCVTF $48, R9, F2
+d701231e| plan9 UCVTFWS R14, F23
+9600631e| plan9 UCVTFWD R4, F22
+8b01239e| plan9 UCVTFS R12, F11
+7202639e| plan9 UCVTFD R19, F18
+3406b82e| plan9 VUHADD V24.S2, V17.S2, V20.S2
+9264612e| plan9 VUMAX V1.H4, V4.H4, V18.H4
+d9a5772e| plan9 VUMAXP V23.H4, V14.H4, V25.H4
+74a8b06e| plan9 UMAXV V3.S4, F20
+24a8312e| plan9 UMINV V1.B8, F4
+c5218e2f| plan9 VUMLAL V14.S[0], V14.S2, V5.D2
+3d20a76f| plan9 VUMLAL2 V7.S[1], V1.S4, V29.D2
+90817e6e| plan9 VUMLAL2 V30.H8, V12.H8, V16.S4
+0f69a46f| plan9 VUMLSL2 V4.S[3], V8.S4, V15.D2
+4aa27c2e| plan9 VUMLSL V28.H4, V18.H4, V10.S4
+48a27b6e| plan9 VUMLSL2 V27.H8, V18.H8, V8.S4
+833c0d0e| plan9 UMOVW V4.B[6], R3
+e2a1b22f| plan9 VUMULL V18.S[1], V15.S2, V2.D2
+07c06f2e| plan9 VUMULL V15.H4, V0.H4, V7.S4
+470e367e| plan9 UQADD F22, F18, F7
+490e252e| plan9 VUQADD V5.B8, V18.B8, V9.B8
+bf5eaa7e| plan9 UQRSHL F10, F21, F31
+c49c347f| plan9 UQRSHRN $12, F6, F4
+b4757a7f| plan9 UQSHL $58, F13, F20
+d14f777e| plan9 UQSHL F23, F30, F17
+9e2d7a7e| plan9 UQSUB F26, F12, F30
+a62c296e| plan9 VUQSUB V9.B16, V5.B16, V6.B16
+5d4ba17e| plan9 UQXTN F26, F29
+454b212e| plan9 VUQXTN V26.H8, V5.B8
+1c48a16e| plan9 VUQXTN2 V0.D2, V28.S4
+4157736e| plan9 VURSHL V19.H8, V26.H8, V1.H8
+2d26797f| plan9 URSHR $7, F17, F13
+bd27466f| plan9 VURSHR $58, V29.D2, V29.D2
+bcc8a12e| plan9 VURSQRTE V5.S2, V28.S2
+f5345d7f| plan9 URSRA $35, F7, F21
+f8353a6f| plan9 VURSRA $6, V15.S4, V24.S4
+85a6342f| plan9 VUSHLL $20, V20.S2, V5.D2
+e7a70e6f| plan9 VUSHLL2 $6, V31.B16, V7.H8
+ed04787f| plan9 USHR $8, F7, F13
+8f07362f| plan9 VUSHR $10, V28.S2, V15.S2
+963a607e| plan9 USQADD F20, F22
+383a206e| plan9 VUSQADD V17.B16, V24.B16
+ef16596f| plan9 VUSRA $39, V23.D2, V15.D2
+f222ab2e| plan9 VUSUBL V11.S2, V23.S2, V18.D2
+9220696e| plan9 VUSUBL2 V9.H8, V4.H8, V18.S4
+0130312e| plan9 VUSUBW V17.B8, V0.H8, V1.H8
+a932a06e| plan9 VUSUBW2 V0.S4, V21.D2, V9.D2
+9a19910e| plan9 VUZP1 V17.S2, V12.S2, V26.S2
+a379ca4e| plan9 VZIP2 V10.D2, V13.D2, V3.D2
+1202011a| plan9 ADCW R1, R16, R18
+6900199a| plan9 ADC R25, R3, R9
+01010f3a| plan9 ADCSW R15, R8, R1
+13010fba| plan9 ADCS R15, R8, R19
+55ed280b| plan9 ADDW R8.SXTX<<3, R10, R21
+2077268b| plan9 ADD R6.UXTX<<5, R25, R0
+7f40560b| plan9 ADDW R22>>16, R3, ZR
+3a16282b| plan9 ADDSW R8.UXTB<<5, R17, R26
+f8a336ab| plan9 ADDS R22.SXTH, RSP, R24
+000e6d31| plan9 ADDSW $(2883<<12), R16, R0
+b48e49b1| plan9 ADDS $(611<<12), R21, R20
+7e174e2b| plan9 ADDSW R14>>5, R27, R30
+3aa13f12| plan9 ANDW $66978814, R9, R26
+32a23592| plan9 AND $-571965880182769649, R17, R18
+b478070a| plan9 ANDW R7<<30, R5, R20
+dd1f988a| plan9 AND R24->7, R30, R29
+a7351b72| plan9 ANDSW $524256, R13, R7
+1c056ef2| plan9 ANDS $786432, R8, R28
+defd52ea| plan9 ANDS R18>>63, R14, R30
+8c28d01a| plan9 ASRW R16, R4, R12
+582ac09a| plan9 ASR R0, R18, R24
+647d1813| plan9 ASRW $24, R11, R4
+d1fe5b93| plan9 ASR $27, R22, R17
+2329c31a| plan9 ASRW R3, R9, R3
+d929d69a| plan9 ASR R22, R14, R25
+aefa5354| plan9 BAL 171989(PC)
+76ad3917| plan9 JMP -12997258(PC)
+de320f33| plan9 BFIW $17, R22, $13, R30
+af144db3| plan9 BFI $51, R5, $6, R15
+161c7eb3| plan9 BFI $2, R0, $8, R22
+f9791733| plan9 BFXILW $23, R15, $8, R25
+781577b3| plan9 BFI $9, R11, $6, R24
+0f65f98a| plan9 BIC R25@>25, R8, R15
+2c37e16a| plan9 BICSW R1@>13, R25, R12
+a6f473ea| plan9 BICS R19>>61, R5, R6
+f064ad96| plan9 CALL -22190864(PC)
+80023fd6| plan9 CALL (R20)
+00001fd6| plan9 JMP (R0)
+80de3ed4| plan9 BRK $63220
+4e2a483a| plan9 CCMNW HS, R18, $8, $14
+4a3a4eba| plan9 CCMN LO, R18, $14, $10
+0143553a| plan9 CCMNW MI, R24, R21, $1
+c09359ba| plan9 CCMN LS, R30, R25, $0
+020a567a| plan9 CCMPW EQ, R16, $22, $2
+a6985afa| plan9 CCMP LS, R5, $26, $6
+6fc0487a| plan9 CCMPW GT, R3, R8, $15
+21d14bfa| plan9 CCMP LE, R9, R11, $1
+75f5991a| plan9 CSINCW AL, R11, R25, R21
+5a25919a| plan9 CSINC HS, R10, R17, R26
+6a938c5a| plan9 CSINVW LS, R27, R12, R10
+6a408eda| plan9 CSINV MI, R3, R14, R10
+5f3603d5| plan9 CLREX $6
+a017c05a| plan9 CLSW R29, R0
+2616c0da| plan9 CLS R17, R6
+9411c05a| plan9 CLZW R12, R20
+c611c0da| plan9 CLZ R14, R6
+9fc3322b| plan9 CMNW R18.SXTW, R28
+3f9638ab| plan9 CMN R24.SXTB<<5, R17
+3f681db1| plan9 CMN $1882, R1
+bfd15bab| plan9 CMN R27>>52, R13
+ff723b6b| plan9 CMPW R27.UXTX<<4, R23
+1f5234eb| plan9 CMP R20.UXTW<<4, R16
+9fb22a71| plan9 CMPW $2732, R20
+df2478f1| plan9 CMP $(3593<<12), R6
+bf07026b| plan9 CMPW R2<<1, R29
+bfc514eb| plan9 CMP R20<<49, R13
+d494975a| plan9 CSNEGW LS, R6, R23, R20
+763591da| plan9 CSNEG LO, R11, R17, R22
+b440c91a| plan9 CRC32B R9, R5, R20
+5745cd1a| plan9 CRC32H R13, R10, R23
+684ad01a| plan9 CRC32W R16, R19, R8
+884fd59a| plan9 CRC32X R21, R28, R8
+ea50c61a| plan9 CRC32CB R6, R7, R10
+1357cf1a| plan9 CRC32CH R15, R24, R19
+9859c21a| plan9 CRC32CW R2, R12, R24
+6e5fde9a| plan9 CRC32CX R30, R27, R14
+9340941a| plan9 CSELW MI, R4, R20, R19
+dd42839a| plan9 CSEL MI, R22, R3, R29
+fe779f1a| plan9 CSETW VS, R30
+f1279f9a| plan9 CSET LO, R17
+eb839f5a| plan9 CSETMW LS, R11
+e3139fda| plan9 CSETM EQ, R3
+a986841a| plan9 CSINCW HI, R21, R4, R9
+19b78b9a| plan9 CSINC LT, R24, R11, R25
+4643835a| plan9 CSINVW MI, R26, R3, R6
+5ee38cda| plan9 CSINV AL, R26, R12, R30
+d166945a| plan9 CSNEGW VS, R22, R20, R17
+55f793da| plan9 CSNEG AL, R26, R19, R21
+0158add4| plan9 DCPS1 $27328
+82ceb2d4| plan9 DCPS2 $38516
+a31eb3d4| plan9 DCPS3 $39157
+bf3203d5| plan9 DMB $2
+e003bfd6| plan9 DRPS
+9f3403d5| plan9 DSB $4
+2e2faeca| plan9 EON R14->11, R25, R14
+de6b0152| plan9 EORW $2214592511, R30, R30
+4a7714d2| plan9 EOR $-13194139536385, R26, R10
+2cea0dca| plan9 EOR R13<<58, R17, R12
+e0039fd6| plan9 ERET
+834cce93| plan9 EXTR $19, R14, R4, R3
+5f2003d5| plan9 WFE
+bf2e03d5| plan9 HINT $117
+e0f055d4| plan9 HLT $44935
+df3403d5| plan9 ISB $4
+22fcdf88| plan9 LDARW (R1), R2
+78fedfc8| plan9 LDAR (R19), R24
+cffcdf08| plan9 LDARB (R6), R15
+34fedf48| plan9 LDARH (R17), R20
+17bb7f88| plan9 LDAXPW (R24), R14, R23
+6ffe7fc8| plan9 LDAXP (R19), ZR, R15
+acfe5f88| plan9 LDAXRW (R21), R12
+cafe5fc8| plan9 LDAXR (R22), R10
+ddfd5f08| plan9 LDAXRB (R14), R29
+0efd5f48| plan9 LDAXRH (R8), R14
+66445128| plan9 LDNPW 136(R3), R17, R6
+3fa77fa8| plan9 LDNP -8(R25), R9, ZR
+1e04eb28| plan9 LDP.P -168(R0), (R30, R1)
+0da6c0a8| plan9 LDP.P 8(R16), (R13, R9)
+7d00d429| plan9 LDP.W 160(R3), (R29, R0)
+d26ae1a9| plan9 LDP.W -496(R22), (R18, R26)
+d0ca6829| plan9 LDP -188(R22), (R16, R18)
+a5e34fa9| plan9 LDP 248(R29), (R5, R24)
+3e44d168| plan9 LDPSW 136(R1), R17, R30
+5f08e169| plan9 LDPSW -248(R2), R2, ZR
+430d6769| plan9 LDPSW -200(R10), R3, R3
+2c555bb8| plan9 MOVWU.P -75(R9), R12
+83c557f8| plan9 MOVD.P -132(R12), R3
+f36e47b8| plan9 MOVWU.W 118(R23), R19
+6b1f48f8| plan9 MOVD.W 129(R27), R11
+f5d64ab9| plan9 MOVWU 2772(R23), R21
+872d7cf9| plan9 MOVD 30808(R12), R7
+82a75438| plan9 MOVBU.P -182(R28), R2
+a7fd5738| plan9 MOVBU.W -129(R13), R7
+c83d4239| plan9 MOVBU 143(R14), R8
+8e687e38| plan9 MOVBU R30(R4), R14
+70575378| plan9 MOVHU.P -203(R27), R16
+015f5078| plan9 MOVHU.W -251(R24), R1
+7add5c79| plan9 MOVHU 3694(R11), R26
+c474c338| plan9 MOVBW.P 55(R6), R4
+28869638| plan9 MOVB.P -152(R17), R8
+fe3fd438| plan9 MOVBW.W -189(RSP), R30
+da0f9938| plan9 MOVB.W -112(R30), R26
+5b3ac739| plan9 MOVBW 462(R18), R27
+2c579e39| plan9 MOVB 1941(R25), R12
+fb68f238| plan9 MOVBW R18(R7), R27
+f26aad38| plan9 MOVB R13(R23), R18
+17e4c978| plan9 MOVHW.P 158(R0), R23
+a2759f78| plan9 MOVH.P -9(R13), R2
+9c6ec478| plan9 MOVHW.W 70(R20), R28
+fd6f8278| plan9 MOVH.W 38(RSP), R29
+a82bc279| plan9 MOVHW 276(R29), R8
+9d89b979| plan9 MOVH 7364(R12), R29
+962685b8| plan9 MOVW.P 82(R20), R22
+76ae8bb8| plan9 MOVW.W 186(R19), R22
+fc2193b9| plan9 MOVW 4896(R15), R28
+e34842b8| plan9 LDTRW 36(R7), R3
+4ff84df8| plan9 LDTR 223(R2), R15
+d9e84f38| plan9 LDTRBW 254(R6), R25
+397b5378| plan9 LDTRHW -201(R25), R25
+c4c9d138| plan9 LDTRSBW -228(R14), R4
+02789638| plan9 LDTRSB -153(R0), R2
+a988cb78| plan9 LDTRSHW 184(R5), R9
+03888978| plan9 LDTRSH 152(R0), R3
+ccb99fb8| plan9 LDTRSW -5(R14), R12
+efb154b8| plan9 LDURW -181(R15), R15
+fc2051f8| plan9 LDUR -238(R7), R28
+86d04438| plan9 LDURBW 77(R4), R6
+73405d78| plan9 LDURHW -44(R3), R19
+7a81d538| plan9 LDURSBW -168(R11), R26
+b0b28038| plan9 LDURSB 11(R21), R16
+b4a1d278| plan9 LDURSHW -214(R13), R20
+3ed18078| plan9 LDURSH 13(R9), R30
+09628eb8| plan9 LDURSW 230(R16), R9
+c07e7f88| plan9 LDXPW (R22), ZR, R0
+3e167fc8| plan9 LDXP (R17), R5, R30
+727c5f88| plan9 LDXRW (R3), R18
+487c5fc8| plan9 LDXR (R2), R8
+867d5f08| plan9 LDXRB (R12), R6
+747f5f48| plan9 LDXRH (R27), R20
+d920d71a| plan9 LSLW R23, R6, R25
+b920c59a| plan9 LSL R5, R5, R25
+4da947d3| plan9 UBFX $7, R10, $36, R13
+be23ca1a| plan9 LSLW R10, R29, R30
+cc20d19a| plan9 LSL R17, R6, R12
+ae26c31a| plan9 LSRW R3, R21, R14
+fc27cb9a| plan9 LSR R11, ZR, R28
+2b7e1053| plan9 LSRW $16, R17, R11
+cefe75d3| plan9 LSR $53, R22, R14
+3b25d01a| plan9 LSRW R16, R9, R27
+e826d79a| plan9 LSR R23, R23, R8
+5504031b| plan9 MADDW R3, R1, R2, R21
+9e5c109b| plan9 MADD R16, R23, R4, R30
+00fe1f1b| plan9 MNEGW ZR, R16, R0
+6efe179b| plan9 MNEG R23, R19, R14
+31020011| plan9 ADDW $0, R17, R17
+21000091| plan9 ADD $0, R1, R1
+39f1bf12| plan9 MOVW $7798783, R25
+53b3e992| plan9 MOVD $-5591781887333892097, R19
+c0fd9552| plan9 MOVW $45038, R0
+f16b97d2| plan9 MOVD $47967, R17
+e8972232| plan9 MOVW $3222257679, R8
+e27323b2| plan9 MOVD $-2017612633531744257, R2
+e9030e2a| plan9 MOVW R14, R9
+fb0310aa| plan9 MOVD R16, R27
+d0e48472| plan9 MOVKW $10022, R16
+432dbcf2| plan9 MOVK $(57706<<16), R3
+4b679612| plan9 MOVW $4294921413, R11
+9121e492| plan9 MOVD $-2381278302972149761, R17
+00be90d2| plan9 MOVD $34288, R0
+91d730d5| plan9 MRS $1724, R17
+cf301fd5| plan9 MSR R15, $31110
+daea181b| plan9 MSUBW R24, R26, R22, R26
+e1a7109b| plan9 MSUB R16, R9, ZR, R1
+477f0d1b| plan9 MULW R13, R26, R7
+a17d1c9b| plan9 MUL R28, R13, R1
+fc9b79aa| plan9 MVN R25>>38, R28
+f71b904b| plan9 NEGW R16->6, R23
+e3df4acb| plan9 NEG R10>>55, R3
+f0334e6b| plan9 NEGSW R14>>12, R16
+e6031f5a| plan9 NGCW ZR, R6
+f40302da| plan9 NGC R2, R20
+ee03137a| plan9 NGCSW R19, R14
+ee0303fa| plan9 NGCS R3, R14
+1f2003d5| plan9 NOP
+ab14e92a| plan9 ORNW R9@>5, R5, R11
+185c3faa| plan9 ORN ZR<<23, R0, R24
+a8850c32| plan9 ORRW $3145776, R13, R8
+cad023b2| plan9 ORR $-2025524839466146845, R6, R10
+5487ccaa| plan9 ORR R12@>33, R26, R20
+293783f9| plan9 PRFM 1640(R25), PLIL1STRM
+bc7389f8| plan9 PRFUM 151(R29), #0X1C
+9203c05a| plan9 RBITW R28, R18
+0501c0da| plan9 RBIT R8, R5
+40005fd6| plan9 RET R2
+940ac05a| plan9 REVW R20, R20
+ca0fc0da| plan9 REV R30, R10
+7807c05a| plan9 REV16W R27, R24
+fb06c0da| plan9 REV16 R23, R27
+dc0ac0da| plan9 REV32 R22, R28
+970dc0da| plan9 REV R12, R23
+42408813| plan9 EXTRW $16, R8, R2, R2
+5a96db93| plan9 EXTR $37, R27, R18, R26
+782cc41a| plan9 RORW R4, R3, R24
+8c2ec69a| plan9 ROR R6, R20, R12
+372ec61a| plan9 RORW R6, R17, R23
+b72ddc9a| plan9 ROR R28, R13, R23
+e501185a| plan9 SBCW R24, R15, R5
+ac0011da| plan9 SBC R17, R5, R12
+7a03067a| plan9 SBCSW R6, R27, R26
+310008fa| plan9 SBCS R8, R1, R17
+65837f93| plan9 SBFIZ $1, R27, $33, R5
+5c1b4793| plan9 SBFIZ $57, R26, $7, R28
+a71f5b93| plan9 SBFIZ $37, R29, $8, R7
+640ede1a| plan9 SDIVW R30, R19, R4
+2a0dd99a| plan9 SDIV R25, R9, R10
+9f2003d5| plan9 SEV
+bf2003d5| plan9 SEVL
+045c389b| plan9 SMADDL R24, R23, R0, R4
+6efe3e9b| plan9 SMNEGL R30, R19, R14
+ebac239b| plan9 SMSUBL R3, R11, R7, R11
+947f459b| plan9 SMULH R5, R28, R20
+d67e3e9b| plan9 SMULL R30, R22, R22
+6dff9f88| plan9 STLRW R13, (R27)
+1ffd9fc8| plan9 STLR ZR, (R8)
+a8fe9f08| plan9 STLRB R8, (R21)
+abfd9f48| plan9 STLRH R11, (R13)
+2ec02888| plan9 STLXPW (R1), R16, R14, R8
+11993ec8| plan9 STLXPW (R8), R6, R17, R30
+bbfe0f88| plan9 STLXRW R27, (R21), R15
+e9fc09c8| plan9 STLXR R9, (R7), R9
+c6fe0708| plan9 STLXRB R6, (R22), R7
+c6fe0c48| plan9 STLXRH R6, (R22), R12
+b3283028| plan9 STNPW -128(R5), R10, R19
+252e26a8| plan9 STNP -416(R17), R11, R5
+9fb18c28| plan9 STP.P (ZR, R12), 100(R12)
+9ce5aba8| plan9 STP.P (R28, R25), -328(R12)
+e5d08229| plan9 STP.W (R5, R20), 20(R7)
+d6e79ea9| plan9 STP.W (R22, R25), 488(R30)
+9eef2029| plan9 STP (R30, R27), -252(R28)
+57b314a9| plan9 STP (R23, R12), 328(R26)
+eda503b8| plan9 MOVW.P R13, 58(R15)
+62241df8| plan9 MOVD.P R2, -46(R3)
+d2bd18b8| plan9 MOVW.W R18, -117(R14)
+542d12f8| plan9 MOVD.W R20, -222(R10)
+e92c3bb9| plan9 MOVW R9, 15148(R7)
+de4804f9| plan9 MOVD R30, 2192(R6)
+cce40b38| plan9 MOVB.P R12, 190(R6)
+eafd1238| plan9 MOVB.W R10, -209(R15)
+7fcb0639| plan9 MOVB ZR, 434(R27)
+5c6a3e38| plan9 MOVB R28, R30(R18)
+a8551978| plan9 MOVH.P R8, -107(R13)
+9e6c0c78| plan9 MOVH.W R30, 198(R4)
+c83d0e79| plan9 MOVH R8, 1822(R14)
+502a1db8| plan9 STTRW -46(R18), R16
+ae180af8| plan9 STTR 161(R5), R14
+ea1a0138| plan9 STTRBW 17(R23), R10
+416b0278| plan9 STTRHW 38(R26), R1
+659107b8| plan9 MOVW R5, 121(R11)
+6b611ff8| plan9 MOVD R11, -10(R11)
+99a01c38| plan9 MOVB R25, -54(R4)
+99421e78| plan9 MOVH R25, -28(R20)
+3e2a2688| plan9 STXPW (R17), R10, R30, R6
+2f6a2cc8| plan9 STXPW (R17), R26, R15, R12
+7d7f1b88| plan9 STXRW R29, (R27), R27
+6e7e1bc8| plan9 STXR R14, (R19), R27
+ec7c0208| plan9 STXRB R12, (R7), R2
+ee7f0648| plan9 STXRH R14, (RSP), R6
+2f8d204b| plan9 SUBW R0.SXTB<<3, R9, R15
+1fbe3acb| plan9 SUB R26.SXTH<<7, R16, RSP
+5af778d1| plan9 SUB $(3645<<12), R26, R26
+6729034b| plan9 SUBW R3<<10, R11, R7
+ae683f6b| plan9 SUBSW ZR.UXTX<<2, R5, R14
+2f993deb| plan9 SUBS R29.SXTB<<6, R9, R15
+db0d5f71| plan9 SUBSW $(1987<<12), R14, R27
+3aec1ff1| plan9 SUBS $2043, R1, R26
+1f24016b| plan9 CMPW R1<<9, R0
+a1ae1bd4| plan9 SVC $56693
+a61e0013| plan9 SXTBW R21, R6
+441c4093| plan9 SXTB R2, R4
+0c3c0013| plan9 SXTHW R0, R12
+b33f4093| plan9 SXTH R29, R19
+407f4093| plan9 SXTW R26, R0
+455929d5| plan9 SYSL $88384, R5
+bf8c1f72| plan9 TSTW $1966110, R5
+ff10836a| plan9 TSTW R3->4, R7
+dfc5daea| plan9 TST R26@>49, R14
+aa6e43d3| plan9 UBFX $3, R21, $25, R10
+46181a53| plan9 UBFIZW $6, R2, $7, R6
+43294bd3| plan9 LSL $53, R10, R3
+77787dd3| plan9 UBFIZ $3, R3, $31, R23
+1a0bd61a| plan9 UDIVW R22, R24, R26
+9308c19a| plan9 UDIV R1, R4, R19
+755aa19b| plan9 UMADDL R1, R22, R19, R21
+1ffdbe9b| plan9 UMNEGL R30, R8, ZR
+cbaaba9b| plan9 UMSUBL R26, R10, R22, R11
+0c7fdb9b| plan9 UMULH R27, R24, R12
+cc7da79b| plan9 UMULL R7, R14, R12
+3d1c0053| plan9 UXTBW R1, R29
+0e3f0053| plan9 UXTHW R24, R14
+5f2003d5| plan9 WFE
+7f2003d5| plan9 WFI
+3f2003d5| plan9 YIELD
+71b9604e| plan9 VABS V11.H8, V17.H8
+5186f65e| plan9 ADD F22, F18, F17
+4986f34e| plan9 VADD V19.D2, V18.D2, V9.D2
+1243720e| plan9 VADDHN V18.S4, V24.S4, V18.H4
+0640354e| plan9 VADDHN2 V21.H8, V0.H8, V6.B16
+d9bdfa4e| plan9 VADDP V26.D2, V14.D2, V25.D2
+4c59284e| plan9 VAESD V10.B16, V12.B16
+8c48284e| plan9 VAESE V4.B16, V12.B16
+f47a284e| plan9 VAESIMC V23.B16, V20.B16
+c56b284e| plan9 VAESMC V30.B16, V5.B16
+bf1c3b0e| plan9 VAND V27.B8, V5.B8, V31.B8
+6444026f| plan9 VMVNI $(67<<16), V4.S4
+1357032f| plan9 VBIC $(120<<16), V19.S2
+561d6a0e| plan9 VBIC V10.B8, V10.B8, V22.B8
+cd1ff06e| plan9 VBIF V16.B16, V30.B16, V13.B16
+f31ebd6e| plan9 VBIT V29.B16, V23.B16, V19.B16
+6f1d6c2e| plan9 VBSL V12.B8, V11.B8, V15.B8
+1e48600e| plan9 VCLS V0.H4, V30.H4
+6948202e| plan9 VCLZ V3.B8, V9.B8
+968efd7e| plan9 CMEQ F29, F20, F22
+e58f6d6e| plan9 VCMEQ V13.H8, V31.H8, V5.H8
+8f98600e| plan9 VCMEQ $0, V4.H4, V15.H4
+4f3db84e| plan9 VCMGE V24.S4, V10.S4, V15.S4
+2788a02e| plan9 VCMGE $0, V1.S2, V7.S2
+bf35714e| plan9 VCMGT V17.H8, V13.H8, V31.H8
+4a89604e| plan9 VCMGT $0, V10.H8, V10.H8
+9635252e| plan9 VCMHI V5.B8, V12.B8, V22.B8
+d83eff6e| plan9 VCMHS V31.D2, V22.D2, V24.D2
+cb99206e| plan9 VCMLE $0, V14.B16, V11.B16
+29a9604e| plan9 VCMLT $0, V9.H8, V9.H8
+d18eea5e| plan9 CMTST F10, F22, F17
+d18ea94e| plan9 VCMTST V9.S4, V22.S4, V17.S4
+4a04075e| plan9 VMOV V2.B[3], F10
+0504040e| plan9 VDUP V0.S[0], V5.S2
+b20e1f4e| plan9 VDUP R21, V18.B16
+2a1f3e6e| plan9 VEOR V30.B16, V25.B16, V10.B16
+0bd5aa7e| plan9 FABD F10, F8, F11
+12d7b96e| plan9 VFABD V25.S4, V24.S4, V18.S4
+a1f9a04e| plan9 FABS V13.S4, V1.S4
+1ac3201e| plan9 FABSS F24, F26
+d8c3601e| plan9 FABSD F30, F24
+95ee267e| plan9 FACGE F6, F20, F21
+2bee262e| plan9 VFACGE V6.S2, V17.S2, V11.S2
+1aedec7e| plan9 FACGT F12, F8, F26
+74effa6e| plan9 VFACGT V26.D2, V27.D2, V20.D2
+7ed4260e| plan9 FADD V6.S2, V3.S2, V30.S2
+4528251e| plan9 FADDS F5, F2, F5
+262b661e| plan9 FADDD F6, F25, F6
+84d8707e| plan9 FADDP V4.D2, F4
+71d4276e| plan9 VFADDP V7.S4, V3.S4, V17.S4
+a5f43f1e| plan9 FCCMPS AL, F31, F5, $5
+20e5601e| plan9 FCCMPD AL, F0, F9, $0
+52d4331e| plan9 FCCMPES LE, F19, F2, $2
+1e66761e| plan9 FCCMPED VS, F22, F16, $14
+d7e6695e| plan9 FCMEQ F9, F22, F23
+e7d9a05e| plan9 FCMEQ $0, F15, F7
+dadaa04e| plan9 VFCMEQ $0, V22.S4, V26.S4
+28e5737e| plan9 FCMGE F19, F9, F8
+a2e73a6e| plan9 VFCMGE V26.S4, V29.S4, V2.S4
+4fcba07e| plan9 FCMGE $0, F26, F15
+43c8a02e| plan9 VFCMGE $0, V2.S2, V3.S2
+ffe5a67e| plan9 FCMGT F6, F15, F31
+7ee7bd2e| plan9 VFCMGT V29.S2, V27.S2, V30.S2
+5bc8e05e| plan9 FCMGT $0, F2, F27
+3dc9a04e| plan9 VFCMGT $0, V9.S4, V29.S4
+38daa07e| plan9 FCMLE $0, F17, F24
+8fdaa02e| plan9 VFCMLE $0, V20.S2, V15.S2
+93e8e05e| plan9 FCMLT $0, F4, F19
+9fe9a04e| plan9 VFCMLT $0, V12.S4, V31.S4
+a023201e| plan9 FCMPS F0, F29
+c822231e| plan9 FCMPS $(0.0), F22
+a022651e| plan9 FCMPD F5, F21
+a8227d1e| plan9 FCMPD $(0.0), F21
+70203e1e| plan9 FCMPES F30, F3
+38232b1e| plan9 FCMPES $(0.0), F25
+70206c1e| plan9 FCMPED F12, F3
+b823731e| plan9 FCMPED $(0.0), F29
+3e6f331e| plan9 FCSELS VS, F25, F19, F30
+a64f6d1e| plan9 FCSELD MI, F29, F13, F6
+0d41e21e| plan9 FCVTHS F8, F13
+cbc0e21e| plan9 FCVTHD F6, F11
+18c0231e| plan9 FCVTSH F0, F24
+a7c0221e| plan9 FCVTSD F5, F7
+e7c3631e| plan9 FCVTDH F31, F7
+9f43621e| plan9 FCVTDS F28, F31
+a0c8215e| plan9 FCVTAS F5, F0
+4dc8210e| plan9 VFCVTAS V2.S2, V13.S2
+0300241e| plan9 FCVTASW F0, R3
+fd03249e| plan9 FCVTAS F31, R29
+ef01641e| plan9 FCVTASW F15, R15
+4c01649e| plan9 FCVTAS F10, R12
+9ac8617e| plan9 FCVTAU F4, F26
+b802251e| plan9 FCVTAUW F21, R24
+2a03259e| plan9 FCVTAU F25, R10
+ea00651e| plan9 FCVTAUW F7, R10
+0102659e| plan9 FCVTAU F16, R1
+0d7a610e| plan9 VFCVTL V16.S2, V13.D2
+ed79214e| plan9 VFCVTL2 V15.H8, V13.S4
+43bb615e| plan9 FCVTMS F26, F3
+c000301e| plan9 FCVTMSW F6, R0
+9202309e| plan9 FCVTMS F20, R18
+0800701e| plan9 FCVTMSW F0, R8
+6603709e| plan9 FCVTMS F27, R6
+f0b9217e| plan9 FCVTMU F15, F16
+3bba212e| plan9 VFCVTMU V17.S2, V27.S2
+5900311e| plan9 FCVTMUW F2, R25
+9a03319e| plan9 FCVTMU F28, R26
+fa01711e| plan9 FCVTMUW F15, R26
+6f01719e| plan9 FCVTMU F11, R15
+1968210e| plan9 VFCVTN V0.S4, V25.H4
+3d69214e| plan9 VFCVTN2 V9.S4, V29.H8
+87aa615e| plan9 FCVTNS F20, F7
+e301201e| plan9 FCVTNSW F15, R3
+6002209e| plan9 FCVTNS F19, R0
+1600601e| plan9 FCVTNSW F0, R22
+8503609e| plan9 FCVTNS F28, R5
+f5ab617e| plan9 FCVTNU F31, F21
+2b02211e| plan9 FCVTNUW F17, R11
+f902219e| plan9 FCVTNU F23, R25
+0702611e| plan9 FCVTNUW F16, R7
+9d03619e| plan9 FCVTNU F28, R29
+dcaba15e| plan9 FCVTPS F30, F28
+b4a8a10e| plan9 VFCVTPS V5.S2, V20.S2
+5302281e| plan9 FCVTPSW F18, R19
+e003289e| plan9 FCVTPS F31, R0
+9501681e| plan9 FCVTPSW F12, R21
+6703689e| plan9 FCVTPS F27, R7
+68a8a17e| plan9 FCVTPU F3, F8
+dcaba12e| plan9 VFCVTPU V30.S2, V28.S2
+9d03291e| plan9 FCVTPUW F28, R29
+5f01299e| plan9 FCVTPU F10, ZR
+e101691e| plan9 FCVTPUW F15, R1
+3f00699e| plan9 FCVTPU F1, ZR
+ee6b612e| plan9 VFCVTXN V31.D2, V14.S2
+b1fd215f| plan9 FCVTZS $31, F13, F17
+bafd2c0f| plan9 FCVTZS $20, V13.S2, V26.S2
+47b8e15e| plan9 FCVTZSDD F2, F7
+dcbbe14e| plan9 FCVTZS V30.D2, V28.D2
+56f8181e| plan9 FCVTZS $2, F2, R22
+9265189e| plan9 FCVTZS $39, F12, R18
+d3ad581e| plan9 FCVTZS $21, F14, R19
+3d9b589e| plan9 FCVTZS $26, F25, R29
+1a00381e| plan9 FCVTZSSW F0, R26
+d302389e| plan9 FCVTZSS F22, R19
+5303781e| plan9 FCVTZSDW F26, R19
+8f01789e| plan9 FCVTZSD F12, R15
+57fe537f| plan9 FCVTZU $45, F18, F23
+beff796f| plan9 FCVTZU $7, V29.D2, V30.D2
+08b9e17e| plan9 FCVTZUDD F8, F8
+cdbbe16e| plan9 FCVTZU V30.D2, V13.D2
+2126199e| plan9 FCVTZU $55, F17, R1
+70a9591e| plan9 FCVTZU $22, F11, R16
+8c25599e| plan9 FCVTZU $55, F12, R12
+1201391e| plan9 FCVTZUSW F8, R18
+0800399e| plan9 FCVTZUS F0, R8
+da00791e| plan9 FCVTZUDW F6, R26
+2903799e| plan9 FCVTZUD F25, R9
+56fd3f2e| plan9 FDIV V31.S2, V10.S2, V22.S2
+1f182e1e| plan9 FDIVS F14, F0, F31
+ce1b741e| plan9 FDIVD F20, F30, F14
+0d61021f| plan9 FMADD F24, F2, F8, F13
+03205e1f| plan9 FMADD F8, F30, F0, F3
+72f6654e| plan9 FMAX V5.D2, V19.D2, V18.D2
+1849281e| plan9 FMAXS F8, F8, F24
+8e4a6e1e| plan9 FMAXD F14, F20, F14
+54c7304e| plan9 FMAXNM V16.S4, V26.S4, V20.S4
+91683a1e| plan9 FMAXNMS F26, F4, F17
+f56a721e| plan9 FMAXNMD F18, F23, F21
+c8cb307e| plan9 FMAXNMP V30.S2, F8
+06c9306e| plan9 FMAXNMV V8.S4, F6
+b6fb707e| plan9 FMAXP V29.D2, F22
+1759341e| plan9 FMINS F20, F8, F23
+675b721e| plan9 FMIND F18, F27, F7
+69792d1e| plan9 FMINNMS F13, F11, F9
+ab786b1e| plan9 FMINNMD F11, F5, F11
+0fcab07e| plan9 FMINNMP V16.S2, F15
+d2c6b26e| plan9 VFMINNMP V18.S4, V22.S4, V18.S4
+22fab07e| plan9 FMINP V17.S2, F2
+f5f5f56e| plan9 VFMINP V21.D2, V15.D2, V21.D2
+bc13c95f| plan9 FMLA V9.D[0], F29, F28
+5d51a85f| plan9 FMLS V8.S[1], F10, F29
+d3ccb94e| plan9 VFMLS V25.S4, V6.S4, V19.S4
+5bf4014f| plan9 FMOV $9., V27.S4
+5bf5026f| plan9 FMOV $0.203125, V27.D2
+6541201e| plan9 FMOVS F11, F5
+b742601e| plan9 FMOVD F21, F23
+6002271e| plan9 FMOVS R19, F0
+5301261e| plan9 FMOVS F10, R19
+c103679e| plan9 FMOVD R30, F1
+3301af9e| plan9 FMOV R9, V19.D[1]
+bd00669e| plan9 FMOVD F5, R29
+ee02ae9e| plan9 FMOV V23.D[1], R14
+0ff0251e| plan9 FMOVS $15.5, F15
+16506a1e| plan9 FMOVD $0.28125, F22
+d1c20e1f| plan9 FMSUB F16, F14, F22, F17
+fdae491f| plan9 FMSUB F11, F9, F23, F29
+a4989d4f| plan9 FMUL V29.S[2], V5.S4, V4.S4
+efde706e| plan9 FMUL V16.D2, V23.D2, V15.D2
+190a291e| plan9 FMULS F9, F16, F25
+430a671e| plan9 FMULD F7, F18, F3
+21919e7f| plan9 FMULX V30.S[0], F9, F1
+5298c76f| plan9 VFMULX V7.D[1], V2.D2, V18.D2
+1ddf3c5e| plan9 FMULX F28, F24, F29
+a2fba06e| plan9 FNEG V29.S4, V2.S4
+7a40211e| plan9 FNEGS F3, F26
+f843611e| plan9 FNEGD F31, F24
+326b381f| plan9 FNMADD F26, F24, F25, F18
+4b636a1f| plan9 FNMADD F24, F10, F26, F11
+48fa201f| plan9 FNMSUB F30, F0, F18, F8
+04d87f1f| plan9 FNMSUB F22, F31, F0, F4
+0289371e| plan9 FNMULS F23, F8, F2
+0e8a691e| plan9 FNMULD F9, F16, F14
+05dba15e| plan9 FRECPE F24, F5
+42d9a14e| plan9 VFRECPE V10.S4, V2.S4
+2eff655e| plan9 FRECPS F5, F25, F14
+03fe774e| plan9 VFRECPS V23.D2, V16.D2, V3.D2
+b4fba15e| plan9 FRECPX F29, F20
+9d41261e| plan9 FRINTAS F12, F29
+ea42661e| plan9 FRINTAD F23, F10
+e399a16e| plan9 FRINTI V15.S4, V3.S4
+6ec3271e| plan9 FRINTIS F27, F14
+ecc1671e| plan9 FRINTID F15, F12
+4543251e| plan9 FRINTMS F26, F5
+f242651e| plan9 FRINTMD F23, F18
+898a214e| plan9 FRINTN V20.S4, V9.S4
+1641241e| plan9 FRINTNS F8, F22
+5341641e| plan9 FRINTND F10, F19
+248be14e| plan9 FRINTP V25.D2, V4.D2
+35c2241e| plan9 FRINTPS F17, F21
+6fc3641e| plan9 FRINTPD F27, F15
+0940271e| plan9 FRINTXS F0, F9
+4643671e| plan9 FRINTXD F26, F6
+749aa14e| plan9 FRINTZ V19.S4, V20.S4
+8bc0251e| plan9 FRINTZS F4, F11
+7cc1651e| plan9 FRINTZD F11, F28
+dedbe17e| plan9 FRSQRTE F30, F30
+04daa16e| plan9 VFRSQRTE V16.S4, V4.S4
+cdfce45e| plan9 FRSQRTS F4, F6, F13
+d9fda04e| plan9 VFRSQRTS V0.S4, V14.S4, V25.S4
+c5c1211e| plan9 FSQRTS F14, F5
+67c1611e| plan9 FSQRTD F11, F7
+a4d6b14e| plan9 FSUB V17.S4, V21.S4, V4.S4
+6138351e| plan9 FSUBS F21, F3, F1
+be3b6a1e| plan9 FSUBD F10, F29, F30
+4d2f016e| plan9 VMOV V26.B[5], V13.B[0]
+741e174e| plan9 VMOV R19, V20.B[11]
+e170404c| plan9 VLD1 (R7), [V1.B16]
+7aa9404c| plan9 VLD1 (R11), [V26.S4, V27.S4]
+4b6d400c| plan9 VLD1 (R10), [V11.D1, V12.D1, V13.D1]
+582b400c| plan9 VLD1 (R26), [V24.S2, V25.S2, V26.S2, V27.S2]
+8f7cdf4c| plan9 VLD1.P 16(R4), [V15.D2]
+0a76ce4c| plan9 VLD1.P (R16)(R14), [V10.H8]
+2aa6df0c| plan9 VLD1.P 16(R17), [V10.H4, V11.H4]
+35a7d70c| plan9 VLD1.P (R25)(R23), [V21.H4, V22.H4]
+ae6ddf4c| plan9 VLD1.P 48(R13), [V14.D2, V15.D2, V16.D2]
+b362d74c| plan9 VLD1.P (R21)(R23), [V19.B16, V20.B16, V21.B16]
+6d22df0c| plan9 VLD1.P 32(R19), [V13.B8, V14.B8, V15.B8, V16.B8]
+6722c90c| plan9 VLD1.P (R19)(R9), [V7.B8, V8.B8, V9.B8, V10.B8]
+c71f404d| plan9 LD1 (R30), [V7.B][15]
+f55a400d| plan9 LD1 (R23), [V21.H][3]
+f080400d| plan9 LD1 (R7), [V16.S][0]
+ed84404d| plan9 LD1 (R7), [V13.D][1]
+fd0bdf4d| plan9 LD1.P 1(RSP), [V29.B][10]
+c811dc0d| plan9 LD1.P (R14)(R28), [V8.B][4]
+6548cb4d| plan9 LD1.P (R3)(R11), [V5.H][5]
+9882df4d| plan9 LD1.P 4(R20), [V24.S][2]
+f482c74d| plan9 LD1.P (R23)(R7), [V20.S][2]
+0d87df0d| plan9 LD1.P 8(R24), [V13.D][0]
+1b85db0d| plan9 LD1.P (R8)(R27), [V27.D][0]
+58c3404d| plan9 VLD1R (R26), [V24.B16]
+c0c6df4d| plan9 VLD1R 2(R22), [V0.H8]
+a6cec90d| plan9 VLD1R (R21)(R9), [V6.D1]
+e68a400c| plan9 VLD2 (R23), [V6.S2, V7.S2]
+4007604d| plan9 LD2 (R26), [V0.B, V1.B][9]
+8c49604d| plan9 LD2 (R12), [V12.H, V13.H][5]
+4f92600d| plan9 LD2 (R18), [V15.S, V16.S][1]
+b186600d| plan9 LD2 (R21), [V17.D, V18.D][0]
+631aff0d| plan9 LD2 2(R19), [V3.B, V4.B][6]
+330ceb4d| plan9 LD2 (R1)(R11), [V19.B, V20.B][11]
+454bff4d| plan9 LD2 4(R26), [V5.H, V6.H][5]
+0792ff0d| plan9 LD2 8(R16), [V7.S, V8.S][1]
+3b91fd0d| plan9 LD2 (R9)(R29), [V27.S, V28.S][1]
+b086ff4d| plan9 LD2 16(R21), [V16.D, V17.D][1]
+da86e30d| plan9 LD2 (R22)(R3), [V26.D, V27.D][0]
+e7cf604d| plan9 VLD2R (RSP), [V7.D2, V8.D2]
+5ac8ff0d| plan9 VLD2R 8(R2), [V26.S2, V27.S2]
+13c1f10d| plan9 VLD2R (R8)(R17), [V19.B8, V20.B8]
+0947404c| plan9 VLD3 (R24), [V9.H8, V10.H8, V11.H8]
+8043df0c| plan9 VLD3 24(R28), [V0.B8, V1.B8, V2.B8]
+6344d50c| plan9 VLD3 (R3)(R21), [V3.H4, V4.H4, V5.H4]
+663d400d| plan9 LD3 (R11), [V6.B, V7.B, V8.B][7]
+5b6b400d| plan9 LD3 (R26), [V27.H, V28.H, V29.H][1]
+02a0404d| plan9 LD3 (R0), [V2.S, V3.S, V4.S][2]
+e1a5404d| plan9 LD3 (R15), [V1.D, V2.D, V3.D][1]
+b53edf0d| plan9 LD3 3(R21), [V21.B, V22.B, V23.B][7]
+f625d10d| plan9 LD3 (R15)(R17), [V22.B, V23.B, V24.B][1]
+3d7bda4d| plan9 LD3 (R25)(R26), [V29.H, V30.H, V31.H][7]
+6ea0df0d| plan9 LD3 12(R3), [V14.S, V15.S, V16.S][0]
+d9a0c60d| plan9 LD3 (R6)(R6), [V25.S, V26.S, V27.S][0]
+b6a7df0d| plan9 LD3 24(R29), [V22.D, V23.D, V24.D][0]
+dfa6d94d| plan9 LD3 (R22)(R25), [V31.D, V0.D, V1.D][1]
+7de9404d| plan9 VLD3R (R11), [V29.S4, V30.S4, V31.S4]
+2fe6df4d| plan9 VLD3R 6(R17), [V15.H8, V16.H8, V17.H8]
+cae7c84d| plan9 VLD3R (R30)(R8), [V10.H8, V11.H8, V12.H8]
+9a0b400c| plan9 VLD4 (R28), [V26.S2, V27.S2, V28.S2, V29.S2]
+4b03df0c| plan9 VLD4 32(R26), [V11.B8, V12.B8, V13.B8, V14.B8]
+8e0bcc4c| plan9 VLD4 (R28)(R12), [V14.S4, V15.S4, V16.S4, V17.S4]
+182c604d| plan9 LD4 (R0), [V24.B, V25.B, V26.B, V27.B][11]
+feb2600d| plan9 LD4 (R23), [V30.S, V31.S, V0.S, V1.S][1]
+59a4604d| plan9 LD4 (R2), [V25.D, V26.D, V27.D, V28.D][1]
+9b25ff4d| plan9 LD4 4(R12), [V27.B, V28.B, V29.B, V30.B][9]
+1f35e84d| plan9 LD4 (R8)(R8), [V31.B, V0.B, V1.B, V2.B][13]
+91b2ff4d| plan9 LD4 16(R20), [V17.S, V18.S, V19.S, V20.S][3]
+88b3ed4d| plan9 LD4 (R28)(R13), [V8.S, V9.S, V10.S, V11.S][3]
+9aa5ff4d| plan9 LD4 32(R12), [V26.D, V27.D, V28.D, V29.D][1]
+efa5e10d| plan9 LD4 (R15)(R1), [V15.D, V16.D, V17.D, V18.D][0]
+07ed604d| plan9 VLD4R (R8), [V7.D2, V8.D2, V9.D2, V10.D2]
+0defff0d| plan9 VLD4R 32(R24), [V13.D1, V14.D1, V15.D1, V16.D1]
+43e1f14d| plan9 VLD4R (R10)(R17), [V3.B16, V4.B16, V5.B16, V6.B16]
+136e682c| plan9 LDNP -192(R16), F27, F19
+cc67676c| plan9 LDNP -400(R30), F25, F12
+e6dd4eac| plan9 LDNP 464(R15), V23, V6
+b7e9c22c| plan9 LDP.P 20(R13), (F23, F26)
+92c3fe6c| plan9 LDP.P -24(R28), (F18, F16)
+f281e6ac| plan9 LDP.P -816(R15), (V18, V0)
+4f06cd2d| plan9 LDP.W 104(R18), (F15, F1)
+0f6fdc6d| plan9 LDP.W 448(R24), (F15, F27)
+170ccbad| plan9 LDP.W 352(R0), (V23, V3)
+71ea7a2d| plan9 LDP -44(R19), (F17, F26)
+c8816c6d| plan9 LDP -312(R14), (F8, F0)
+da6540ad| plan9 LDP (R14), (V26, V25)
+92064c3c| plan9 MOVD.P 192(R20), F18
+94d4577c| plan9 MOVD.P -131(R4), F20
+39055fbc| plan9 MOVD.P -16(R9), F25
+989551fc| plan9 MOVD.P -231(R12), F24
+4764c23c| plan9 MOVD.P 38(R2), V7
+c15e4e3c| plan9 MOVD.W 229(R22), F1
+c8ce487c| plan9 MOVD.W 140(R22), F8
+ca5d5bbc| plan9 MOVD.W -75(R14), F10
+34fd56fc| plan9 MOVD.W -145(R9), F20
+bd0dd53c| plan9 MOVD.W -176(R13), V29
+ab65443d| plan9 MOVD 281(R13), F11
+cb57537d| plan9 MOVD 2474(R30), F11
+f2606fbd| plan9 MOVD 12128(R7), F18
+088b67fd| plan9 MOVD 20240(R24), F8
+0173ce3d| plan9 MOVD 14784(R24), V1
+726b733c| plan9 MOVD R19(R27), F18
+43a1413c| plan9 LDUR 26(R10), F3
+c7034f7c| plan9 LDUR 240(R30), F7
+ad8350bc| plan9 LDUR -248(R29), F13
+07a350fc| plan9 LDUR -246(R24), F7
+0212c63c| plan9 LDUR 97(R16), V2
+6f0a7a2f| plan9 VMLA V10.H[7], V19.H4, V15.H4
+fe95294e| plan9 VMLA V9.B16, V15.B16, V30.B16
+f24a4f2f| plan9 VMLS V15.H[4], V23.H4, V18.H4
+26947e2e| plan9 VMLS V30.H4, V1.H4, V6.H4
+6606115e| plan9 VMOV V19.B[8], F6
+0866116e| plan9 VMOV V16.B[12], V8.B[8]
+6e1d0f4e| plan9 VMOV R11, V14.B[7]
+6d1fa10e| plan9 VORR V1.B8, V27.B8, V13.B8
+b93f1a0e| plan9 UMOVW V29.H[6], R25
+74e7020f| plan9 VMOVI $91, V20.B8
+0ff4040f| plan9 FMOV $-2., V15.S2
+4c47060f| plan9 VMOVI $(218<<16), V12.S2
+aa06064f| plan9 VMOVI $213, V10.S4
+8de4042f| plan9 MOVI $-72057594021216256, F13
+b1e6046f| plan9 VMOVI $-72056498804555521, V17.D2
+609f214e| plan9 VMUL V1.B16, V27.B16, V0.B16
+9f5a206e| plan9 VMVN V20.B16, V31.B16
+da65032f| plan9 VMVNI $(110<<24), V26.S2
+4d36036f| plan9 VBIC $(114<<8), V13.S4
+4d66052f| plan9 VMVNI $(178<<24), V13.S2
+a4bbe06e| plan9 VNEG V29.D2, V4.D2
+bf5a206e| plan9 VMVN V21.B16, V31.B16
+2b1fe24e| plan9 VORN V2.B16, V25.B16, V11.B16
+22e4024f| plan9 VMOVI $65, V2.B16
+3086050f| plan9 VMOVI $177, V16.H4
+051db80e| plan9 VORR V24.B8, V8.B8, V5.B8
+48e2290e| plan9 VPMULL V9.B8, V18.B8, V8.H8
+7341652e| plan9 VRADDHN V5.S4, V11.S4, V19.H4
+1b417f6e| plan9 VRADDHN2 V31.S4, V8.S4, V27.H8
+e158606e| plan9 VRBIT V7.B16, V1.B16
+f418200e| plan9 VREV16 V7.B8, V20.B8
+228d2a0f| plan9 VRSHRN $22, V9.D2, V2.S2
+a861aa2e| plan9 VRSUBHN V10.D2, V13.D2, V8.S2
+7160786e| plan9 VRSUBHN2 V24.S4, V3.S4, V17.H8
+cc7f314e| plan9 VSABA V17.B16, V30.B16, V12.B16
+1350644e| plan9 VSABAL2 V4.H8, V0.H8, V19.S4
+a1757d4e| plan9 VSABD V29.H8, V13.H8, V1.H8
+0971a00e| plan9 VSABDL V0.S2, V8.S2, V9.D2
+af70214e| plan9 VSABDL2 V1.B16, V5.B16, V15.H8
+626ba04e| plan9 VSADALP V27.S4, V2.D2
+1503374e| plan9 VSADDL2 V23.B16, V24.B16, V21.H8
+592b204e| plan9 VSADDLP V26.B16, V25.H8
+d813600e| plan9 VSADDW V0.H4, V30.S4, V24.S4
+31e5210f| plan9 SCVTF $31, V9.S2, V17.S2
+aeda215e| plan9 SCVTFSS F21, F14
+f0e9021e| plan9 SCVTF $6, R15, F16
+42b4421e| plan9 SCVTF $19, R2, F2
+8b10029e| plan9 SCVTF $60, R4, F11
+59e6429e| plan9 SCVTF $7, R18, F25
+cf01221e| plan9 SCVTFWS R14, F15
+2d03621e| plan9 SCVTFWD R25, F13
+af00229e| plan9 SCVTFS R5, F15
+bf00629e| plan9 SCVTFD R5, F31
+2a02025e| plan9 SHA1C V2.S4, F17, V10
+8b0b285e| plan9 SHA1H F28, F11
+11201f5e| plan9 SHA1M V31.S4, F0, V17
+f110115e| plan9 SHA1P V17.S4, F7, V17
+b732115e| plan9 VSHA1SU0 V17.S4, V21.S4, V23.S4
+cf18285e| plan9 VSHA1SU1 V6.S4, V15.S4
+2e520f5e| plan9 SHA256H2 V15.S4, V17, V14
+77401a5e| plan9 SHA256H V26.S4, V3, V23
+b92a285e| plan9 VSHA256SU0 V21.S4, V25.S4
+7e63175e| plan9 VSHA256SU1 V23.S4, V27.S4, V30.S4
+d504ab0e| plan9 VSHADD V11.S2, V6.S2, V21.S2
+5a54734f| plan9 VSHL $51, V2.D2, V26.D2
+0638212e| plan9 VSHLL $8, V0.B8, V6.H8
+a238216e| plan9 VSHLL2 $8, V5.B16, V2.H8
+f5863e0f| plan9 VSHRN $2, V23.D2, V21.S2
+f187234f| plan9 VSHRN2 $29, V31.D2, V17.S4
+e124b04e| plan9 VSHSUB V16.S4, V7.S4, V1.S4
+3657252f| plan9 VSLI $5, V25.S2, V22.S2
+c266aa4e| plan9 VSMAX V10.S4, V22.S4, V2.S4
+2c6ca74e| plan9 VSMIN V7.S4, V1.S4, V12.S4
+4aae390e| plan9 VSMINP V25.B8, V18.B8, V10.B8
+1a82ba0e| plan9 VSMLAL V26.S2, V16.S2, V26.D2
+2381ad4e| plan9 VSMLAL2 V13.S4, V9.S4, V3.D2
+0da17a4e| plan9 VSMLSL2 V26.H8, V8.H8, V13.S4
+4f2e0d4e| plan9 SMOV V18.B[6], R15
+e4a0980f| plan9 VSMULL V24.S[0], V7.S2, V4.D2
+51c2220e| plan9 VSMULL V2.B8, V18.B8, V17.H8
+01c26d4e| plan9 VSMULL2 V13.H8, V16.H8, V1.S4
+f978205e| plan9 SQABS F7, F25
+760cef5e| plan9 SQADD F15, F3, F22
+390c224e| plan9 VSQADD V2.B16, V1.B16, V25.B16
+5439455f| plan9 SQDMLAL V5.H[4], F10, F20
+8391765e| plan9 SQDMLAL F22, F12, F3
+c9907a4e| plan9 VSQDMLAL2 V26.H8, V6.H8, V9.S4
+0b73445f| plan9 SQDMLSL V4.H[0], F24, F11
+8e728d0f| plan9 VSQDMLSL V13.S[0], V20.S2, V14.D2
+fe787d4f| plan9 VSQDMLSL2 V13.H[7], V7.H8, V30.S4
+bdb2b55e| plan9 SQDMLSL F21, F21, F29
+d0c9be4f| plan9 VSQDMULH V30.S[3], V14.S4, V16.S4
+89b77c5e| plan9 SQDMULH F28, F28, F9
+c9bb515f| plan9 SQDMULL V1.H[5], F30, F9
+5379e07e| plan9 SQNEG F10, F19
+4b7aa06e| plan9 VSQNEG V18.S4, V11.S4
+1bd1750f| plan9 VSQRDMULH V5.H[3], V8.H4, V27.H4
+f55e755e| plan9 SQRSHL F21, F23, F21
+ba5fbd4e| plan9 VSQRSHL V29.S4, V29.S4, V26.S4
+ba9d1e0f| plan9 VSQRSHRN $2, V13.S4, V26.H4
+3d9c284f| plan9 VSQRSHRN2 $24, V1.D2, V29.S4
+8a8f2c6f| plan9 VSQRSHRUN2 $20, V28.D2, V10.S4
+eb760b5f| plan9 SQSHL $3, F23, F11
+4a77220f| plan9 VSQSHL $2, V26.S2, V10.S2
+6c4cfb5e| plan9 SQSHL F27, F3, F12
+ad4eba4e| plan9 VSQSHL V26.S4, V21.S4, V13.S4
+9364257f| plan9 SQSHLU $5, F4, F19
+b267392f| plan9 VSQSHLU $25, V29.S2, V18.S2
+c085042f| plan9 VMVNI $142, V0.H4
+7584326f| plan9 VSQSHRUN2 $14, V3.D2, V21.S4
+3a2fe25e| plan9 SQSUB F2, F25, F26
+2c2ca34e| plan9 VSQSUB V3.S4, V1.S4, V12.S4
+484ba15e| plan9 SQXTN F26, F8
+824b210e| plan9 VSQXTN V28.H8, V2.B8
+5b48214e| plan9 VSQXTN2 V2.H8, V27.B16
+e228a16e| plan9 VSQXTUN2 V7.D2, V2.S4
+1c44416f| plan9 VSRI $63, V0.D2, V28.D2
+1e56eb5e| plan9 SRSHL F11, F16, F30
+bb56fe4e| plan9 VSRSHL V30.D2, V21.D2, V27.D2
+c6262d0f| plan9 VSRSHR $19, V22.S2, V6.S2
+0c366c5f| plan9 SRSRA $20, F16, F12
+13376e4f| plan9 VSRSRA $18, V24.D2, V19.D2
+7ba5040f| plan9 VMOVI $(139<<8), V27.H4
+9c076f5f| plan9 SSHR $17, F28, F28
+2804434f| plan9 VSSHR $61, V1.D2, V8.D2
+b717535f| plan9 SSRA $45, F29, F23
+c2160f0f| plan9 VSSRA $1, V22.B8, V2.B8
+8a333a4e| plan9 VSSUBW2 V26.B16, V28.H8, V10.H8
+3a70000c| plan9 VST1 (R1), [V26.B8]
+1bab004c| plan9 VST1 (R24), [V27.S4, V28.S4]
+8d69004c| plan9 VST1 (R12), [V13.S4, V14.S4, V15.S4]
+9c26004c| plan9 VST1 (R20), [V28.H8, V29.H8, V30.H8, V31.H8]
+c87a9f0c| plan9 VST1 8(R22), [V8.S2]
+5a7f800c| plan9 VST1 (R26)(R0), [V26.D1]
+eea99f4c| plan9 VST1 32(R15), [V14.S4, V15.S4]
+11af9d4c| plan9 VST1 (R24)(R29), [V17.D2, V18.D2]
+ec689f0c| plan9 VST1 24(R7), [V12.S2, V13.S2, V14.S2]
+8662900c| plan9 VST1 (R20)(R16), [V6.B8, V7.B8, V8.B8]
+0b249f4c| plan9 VST1 64(R0), [V11.H8, V12.H8, V13.H8, V14.H8]
+6b2d8b4c| plan9 VST1 (R11)(R11), [V11.D2, V12.D2, V13.D2, V14.D2]
+3212004d| plan9 ST1 (R17), [V18.B][12]
+3392004d| plan9 ST1 (R17), [V19.S][3]
+0284000d| plan9 ST1 (R0), [V2.D][0]
+340f9f0d| plan9 ST1 1(R25), [V20.B][3]
+0d069a4d| plan9 ST1 (R16)(R26), [V13.B][9]
+2e51950d| plan9 ST1 (R9)(R21), [V14.H][2]
+3f839f0d| plan9 ST1 4(R25), [V31.S][0]
+1492844d| plan9 ST1 (R16)(R4), [V20.S][3]
+dd869f4d| plan9 ST1 8(R22), [V29.D][1]
+2e869b4d| plan9 ST1 (R17)(R27), [V14.D][1]
+1e87000c| plan9 VST2 (R24), [V30.H4, V31.H4]
+07829f0c| plan9 VST2 16(R16), [V7.B8, V8.B8]
+d38a884c| plan9 VST2 (R22)(R8), [V19.S4, V20.S4]
+541c204d| plan9 ST2 (R2), [V20.B, V21.B][15]
+9180200d| plan9 ST2 (R4), [V17.S, V18.S][0]
+2585204d| plan9 ST2 (R9), [V5.D, V6.D][1]
+2f06bf4d| plan9 ST2 2(R17), [V15.B, V16.B][9]
+3b08b44d| plan9 ST2 (R1)(R20), [V27.B, V28.B][10]
+805bbf0d| plan9 ST2 4(R28), [V0.H, V1.H][3]
+fb80bf0d| plan9 ST2 8(R7), [V27.S, V28.S][0]
+6290a80d| plan9 ST2 (R3)(R8), [V2.S, V3.S][1]
+b587bf4d| plan9 ST2 16(R29), [V21.D, V22.D][1]
+2c84b64d| plan9 ST2 (R1)(R22), [V12.D, V13.D][1]
+22469f0c| plan9 VST3 24(R17), [V2.H4, V3.H4, V4.H4]
+0e30004d| plan9 ST3 (R0), [V14.B, V15.B, V16.B][12]
+62a1004d| plan9 ST3 (R11), [V2.S, V3.S, V4.S][2]
+54a4000d| plan9 ST3 (R2), [V20.D, V21.D, V22.D][0]
+84259f4d| plan9 ST3 3(R12), [V4.B, V5.B, V6.B][9]
+693c9d4d| plan9 ST3 (R3)(R29), [V9.B, V10.B, V11.B][15]
+5b709f0d| plan9 ST3 6(R2), [V27.H, V28.H, V29.H][2]
+e47a960d| plan9 ST3 (R23)(R22), [V4.H, V5.H, V6.H][3]
+a0a39f0d| plan9 ST3 12(R29), [V0.S, V1.S, V2.S][0]
+37b0890d| plan9 ST3 (R1)(R9), [V23.S, V24.S, V25.S][1]
+9aa59f4d| plan9 ST3 24(R12), [V26.D, V27.D, V28.D][1]
+26a5924d| plan9 ST3 (R9)(R18), [V6.D, V7.D, V8.D][1]
+3e05000c| plan9 VST4 (R9), [V30.H4, V31.H4, V0.H4, V1.H4]
+a8039f0c| plan9 VST4 32(R29), [V8.B8, V9.B8, V10.B8, V11.B8]
+4126204d| plan9 ST4 (R18), [V1.B, V2.B, V3.B, V4.B][9]
+3b71204d| plan9 ST4 (R9), [V27.H, V28.H, V29.H, V30.H][6]
+f2b3204d| plan9 ST4 (RSP), [V18.S, V19.S, V20.S, V21.S][3]
+7fa4200d| plan9 ST4 (R3), [V31.D, V0.D, V1.D, V2.D][0]
+562ebf4d| plan9 ST4 4(R18), [V22.B, V23.B, V24.B, V25.B][11]
+563cae0d| plan9 ST4 (R2)(R14), [V22.B, V23.B, V24.B, V25.B][7]
+1271bf4d| plan9 ST4 8(R8), [V18.H, V19.H, V20.H, V21.H][6]
+e7a1bf0d| plan9 ST4 16(R15), [V7.S, V8.S, V9.S, V10.S][0]
+f3b2a30d| plan9 ST4 (R23)(R3), [V19.S, V20.S, V21.S, V22.S][1]
+eca5bf4d| plan9 ST4 32(R15), [V12.D, V13.D, V14.D, V15.D][1]
+4ca7bb0d| plan9 ST4 (R26)(R27), [V12.D, V13.D, V14.D, V15.D][0]
+4f5b182c| plan9 STNP 192(R26), F22, F15
+e05e0b6c| plan9 STNP 176(R23), F23, F0
+77be2eac| plan9 STNP -560(R19), V15, V23
+bb3fa72c| plan9 STP.P (F27, F15), -200(R29)
+ef18bb6c| plan9 STP.P (F15, F6), -80(R7)
+777d84ac| plan9 STP.P (V23, V31), 128(R11)
+d0f9952d| plan9 STP.W (F16, F30), 172(R14)
+125ca26d| plan9 STP.W (F18, F23), -480(R0)
+33bbbfad| plan9 STP.W (V19, V14), -16(R25)
+6ebb322d| plan9 STP (F14, F14), -108(R27)
+cb92096d| plan9 STP (F11, F4), 152(R22)
+f2871dad| plan9 STP (V18, V1), 944(RSP)
+f676003c| plan9 MOVD.P F22, 7(R23)
+50f50d7c| plan9 MOVD.P F16, 223(R10)
+0d251ebc| plan9 MOVD.P F13, -30(R8)
+1f3510fc| plan9 MOVD.P F31, -253(R8)
+05a4883c| plan9 MOVD.P V5, 138(R0)
+800e063c| plan9 MOVD.W F0, 96(R20)
+668d157c| plan9 MOVD.W F6, -168(R11)
+1f3d11bc| plan9 MOVD.W F31, -237(R8)
+71bf06fc| plan9 MOVD.W F17, 107(R27)
+f50c843c| plan9 MOVD.W V21, 64(R7)
+f186013d| plan9 MOVD F17, 97(R23)
+f0e5357d| plan9 MOVD F16, 6898(R15)
+938d3bbd| plan9 MOVD F19, 15244(R12)
+aeb813fd| plan9 MOVD F14, 10096(R5)
+2cc4943d| plan9 MOVD V12, 21264(R1)
+1d79373c| plan9 MOVD F29, R23<<1(R8)
+bc70003c| plan9 MOVD F28, 7(R5)
+7190157c| plan9 MOVD F17, -167(R3)
+073309bc| plan9 MOVD F7, 147(R24)
+298100fc| plan9 MOVD F9, 8(R9)
+e8c1843c| plan9 MOVD V8, 76(R15)
+3384266e| plan9 VSUB V6.B16, V1.B16, V19.B16
+9163750e| plan9 VSUBHN V21.S4, V28.S4, V17.H4
+f3627d4e| plan9 VSUBHN2 V29.S4, V23.S4, V19.H8
+1939205e| plan9 SUQADD F8, F25
+0638604e| plan9 VSUQADD V0.H8, V6.H8
+81a4284f| plan9 VSSHLL2 $8, V4.S4, V1.D2
+f920030e| plan9 VTBL V3.B8, [V7.B16, V8.B16], V25.B8
+71400e4e| plan9 VTBL V14.B16, [V3.B16, V4.B16, V5.B16], V17.B16
+bc630d4e| plan9 VTBL V13.B16, [V29.B16, V30.B16, V31.B16, V0.B16], V28.B16
+6803030e| plan9 VTBL V3.B8, [V27.B16], V8.B8
+4b32124e| plan9 VTBX V18.B16, [V18.B16, V19.B16], V11.B16
+8f50170e| plan9 VTBX V23.B8, [V4.B16, V5.B16, V6.B16], V15.B8
+5673020e| plan9 VTBX V2.B8, [V26.B16, V27.B16, V28.B16, V29.B16], V22.B8
+f2130f4e| plan9 VTBX V15.B16, [V31.B16], V18.B16
+9e29c34e| plan9 VTRN1 V3.D2, V12.D2, V30.D2
+9b6bcf4e| plan9 VTRN2 V15.D2, V28.D2, V27.D2
+157cb02e| plan9 VUABA V16.S2, V0.S2, V21.S2
+28513c2e| plan9 VUABAL V28.B8, V9.B8, V8.H8
+f950a26e| plan9 VUABAL2 V2.S4, V7.S4, V25.D2
+a776b26e| plan9 VUABD V18.S4, V21.S4, V7.S4
+da726b2e| plan9 VUABDL V11.H4, V22.H4, V26.S4
+9473746e| plan9 VUABDL2 V20.H8, V28.H8, V20.S4
+aa6b602e| plan9 VUADALP V29.H4, V10.S2
+ac013d2e| plan9 VUADDL V29.B8, V13.B8, V12.H8
+e500a86e| plan9 VUADDL2 V8.S4, V7.S4, V5.D2
+9c28a02e| plan9 VUADDLP V4.S2, V28.D1
+4c3a302e| plan9 UADDLV V18.B8, F12
+2810b62e| plan9 VUADDW V22.S2, V1.D2, V8.D2
+f2132d6e| plan9 VUADDW2 V13.B16, V31.H8, V18.H8
+b3e67f7f| plan9 UCVTF $1, F21, F19
+ece5676f| plan9 UCVTF $25, V15.D2, V12.D2
+d7d8217e| plan9 UCVTFSS F6, F23
+cdd9212e| plan9 UCVTF V14.S2, V13.S2
+5788031e| plan9 UCVTF $30, R2, F23
+c7ac431e| plan9 UCVTF $21, R6, F7
+0777039e| plan9 UCVTF $35, R24, F7
+e4f4439e| plan9 UCVTF $3, R7, F4
+9100231e| plan9 UCVTFWS R4, F17
+e202631e| plan9 UCVTFWD R23, F2
+3903239e| plan9 UCVTFS R25, F25
+2001639e| plan9 UCVTFD R9, F0
+2a07b76e| plan9 VUHADD V23.S4, V25.S4, V10.S4
+dc25372e| plan9 VUHSUB V23.B8, V14.B8, V28.B8
+de646f2e| plan9 VUMAX V15.H4, V6.H4, V30.H4
+4ba6766e| plan9 VUMAXP V22.H8, V18.H8, V11.H8
+e26db42e| plan9 VUMIN V20.S2, V15.S2, V2.S2
+a7ae712e| plan9 VUMINP V17.H4, V21.H4, V7.H4
+afaa716e| plan9 UMINV V21.H8, F15
+42298c2f| plan9 VUMLAL V12.S[2], V10.S2, V2.D2
+0a826e2e| plan9 VUMLAL V14.H4, V16.H4, V10.S4
+2681a06e| plan9 VUMLAL2 V0.S4, V9.S4, V6.D2
+2860bd6f| plan9 VUMLSL2 V29.S[1], V1.S4, V8.D2
+19a26b6e| plan9 VUMLSL2 V11.H8, V16.H8, V25.S4
+8a3d140e| plan9 VMOV V12.S[2], R10
+22a1ba6f| plan9 VUMULL2 V26.S[1], V9.S4, V2.D2
+15c0712e| plan9 VUMULL V17.H4, V0.H4, V21.S4
+2ec0296e| plan9 VUMULL2 V9.B16, V1.B16, V14.H8
+6e0fba7e| plan9 UQADD F26, F27, F14
+db0fe06e| plan9 VUQADD V0.D2, V30.D2, V27.D2
+535e6c7e| plan9 UQRSHL F12, F18, F19
+7c5cfe6e| plan9 VUQRSHL V30.D2, V3.D2, V28.D2
+9a9e327f| plan9 UQRSHRN $14, F20, F26
+339f0b2f| plan9 VUQRSHRN $5, V25.H8, V19.B8
+7e77337f| plan9 UQSHL $19, F27, F30
+8b4d657e| plan9 UQSHL F5, F12, F11
+414c622e| plan9 VUQSHL V2.H4, V2.H4, V1.H4
+95942b2f| plan9 VUQSHRN $21, V4.D2, V21.S2
+d396246f| plan9 VUQSHRN2 $28, V22.D2, V19.S4
+b22ff27e| plan9 UQSUB F18, F29, F18
+b32e756e| plan9 VUQSUB V21.H8, V21.H8, V19.H8
+0e4b616e| plan9 VUQXTN2 V24.S4, V14.H8
+ca16236e| plan9 VURHADD V3.B16, V22.B16, V10.B16
+1f57a26e| plan9 VURSHL V2.S4, V24.S4, V31.S4
+8324777f| plan9 URSHR $9, F4, F3
+37caa16e| plan9 VURSQRTE V17.S4, V23.S4
+b735517f| plan9 URSRA $47, F13, F23
+0a47f67e| plan9 USHL F22, F24, F10
+e7a71c2f| plan9 VUSHLL $12, V31.H4, V7.S4
+9c38607e| plan9 USQADD F4, F28
+dc39206e| plan9 VUSQADD V14.B16, V28.B16
+dc145d7f| plan9 USRA $35, F6, F28
+d720752e| plan9 VUSUBL V21.H4, V6.H4, V23.S4
+2c236f6e| plan9 VUSUBL2 V15.H8, V25.H8, V12.S4
+ed32222e| plan9 VUSUBW V2.B8, V23.H8, V13.H8
+72332d6e| plan9 VUSUBW2 V13.B16, V27.H8, V18.H8
+655a1c4e| plan9 VUZP2 V28.B16, V19.B16, V5.B16
+972a210e| plan9 VXTN V20.H8, V23.B8
+5f2aa14e| plan9 VXTN2 V18.D2, V31.S4
+9a38910e| plan9 VZIP1 V17.S2, V4.S2, V26.S2
+d979990e| plan9 VZIP2 V25.S2, V14.S2, V25.S2
+41e5a454| plan9 BNE -186582(PC)
+ea1b543a| plan9 CCMNW NE, ZR, $20, $10
+681946ba| plan9 CCMN NE, R11, $6, $8
+2410463a| plan9 CCMNW NE, R1, R6, $4
+6e134cba| plan9 CCMN NE, R27, R12, $14
+ad194f7a| plan9 CCMPW NE, R13, $15, $13
+471b53fa| plan9 CCMP NE, R26, $19, $7
+a210467a| plan9 CCMPW NE, R5, R6, $2
+ee1246fa| plan9 CCMP NE, R23, R6, $14
+be149b1a| plan9 CSINCW NE, R5, R27, R30
+c415819a| plan9 CSINC NE, R14, R1, R4
+0510955a| plan9 CSINVW NE, R0, R21, R5
+c51093da| plan9 CSINV NE, R6, R19, R5
+12158e5a| plan9 CSNEGW NE, R8, R14, R18
+5c159cda| plan9 CSNEG NE, R10, R28, R28
+c810941a| plan9 CSELW NE, R6, R20, R8
+80128c9a| plan9 CSEL NE, R20, R12, R0
+f6179f1a| plan9 CSETW EQ, R22
+f5179f9a| plan9 CSET EQ, R21
+ec139f5a| plan9 CSETMW EQ, R12
+ee139fda| plan9 CSETM EQ, R14
+4b17981a| plan9 CSINCW NE, R26, R24, R11
+b515909a| plan9 CSINC NE, R13, R16, R21
+b613955a| plan9 CSINVW NE, R29, R21, R22
+f8108bda| plan9 CSINV NE, R7, R11, R24
+a0149d5a| plan9 CSNEGW NE, R5, R29, R0
+6a1492da| plan9 CSNEG NE, R3, R18, R10
+8f143c1e| plan9 FCCMPS NE, F28, F4, $15
+0f167f1e| plan9 FCCMPD NE, F31, F16, $15
+5214291e| plan9 FCCMPES NE, F9, F2, $2
+1516631e| plan9 FCCMPED NE, F3, F16, $5
+2b1d271e| plan9 FCSELS NE, F9, F7, F11
+731e611e| plan9 FCSELD NE, F19, F1, F19
+c2560e54| plan9 BCS 29366(PC)
+2d2b563a| plan9 CCMNW HS, R25, $22, $13
+6c2b55ba| plan9 CCMN HS, R27, $21, $12
+2521493a| plan9 CCMNW HS, R9, R9, $5
+032040ba| plan9 CCMN HS, R0, R0, $3
+ea2a5c7a| plan9 CCMPW HS, R23, $28, $10
+8e2842fa| plan9 CCMP HS, R4, $2, $14
+8e22427a| plan9 CCMPW HS, R20, R2, $14
+cd204dfa| plan9 CCMP HS, R6, R13, $13
+2824931a| plan9 CSINCW HS, R1, R19, R8
+a3279a9a| plan9 CSINC HS, R29, R26, R3
+5921945a| plan9 CSINVW HS, R10, R20, R25
+bd2386da| plan9 CSINV HS, R29, R6, R29
+a124915a| plan9 CSNEGW HS, R5, R17, R1
+5b2787da| plan9 CSNEG HS, R26, R7, R27
+91209f1a| plan9 CSELW HS, R4, ZR, R17
+f921979a| plan9 CSEL HS, R15, R23, R25
+e4279f1a| plan9 CSETW LO, R4
+ea279f9a| plan9 CSET LO, R10
+fe239f5a| plan9 CSETMW LO, R30
+ec239fda| plan9 CSETM LO, R12
+ee25971a| plan9 CSINCW HS, R15, R23, R14
+b726859a| plan9 CSINC HS, R21, R5, R23
+4b22845a| plan9 CSINVW HS, R18, R4, R11
+2b209eda| plan9 CSINV HS, R1, R30, R11
+6b269b5a| plan9 CSNEGW HS, R19, R27, R11
+192691da| plan9 CSNEG HS, R16, R17, R25
+0226391e| plan9 FCCMPS HS, F25, F16, $2
+07246d1e| plan9 FCCMPD HS, F13, F0, $7
+9626241e| plan9 FCCMPES HS, F4, F20, $6
+de27601e| plan9 FCCMPED HS, F0, F30, $14
+7d2d271e| plan9 FCSELS HS, F11, F7, F29
+3e2e7a1e| plan9 FCSELD HS, F17, F26, F30
+43a4df54| plan9 BCC -66270(PC)
+0739533a| plan9 CCMNW LO, R8, $19, $7
+673b4fba| plan9 CCMN LO, R27, $15, $7
+e333583a| plan9 CCMNW LO, ZR, R24, $3
+83325aba| plan9 CCMN LO, R20, R26, $3
+eb38517a| plan9 CCMPW LO, R7, $17, $11
+2c3955fa| plan9 CCMP LO, R9, $21, $12
+6f324b7a| plan9 CCMPW LO, R19, R11, $15
+09314ffa| plan9 CCMP LO, R8, R15, $9
+60349c1a| plan9 CSINCW LO, R3, R28, R0
+8835949a| plan9 CSINC LO, R12, R20, R8
+bb31935a| plan9 CSINVW LO, R13, R19, R27
+9f319dda| plan9 CSINV LO, R12, R29, ZR
+8837855a| plan9 CSNEGW LO, R28, R5, R8
+cd3490da| plan9 CSNEG LO, R6, R16, R13
+b033901a| plan9 CSELW LO, R29, R16, R16
+5e31969a| plan9 CSEL LO, R10, R22, R30
+ec379f1a| plan9 CSETW HS, R12
+ea379f9a| plan9 CSET HS, R10
+eb339f5a| plan9 CSETMW HS, R11
+fd339fda| plan9 CSETM HS, R29
+9934941a| plan9 CSINCW LO, R4, R20, R25
+fa36829a| plan9 CSINC LO, R23, R2, R26
+2730895a| plan9 CSINVW LO, R1, R9, R7
+703094da| plan9 CSINV LO, R3, R20, R16
+f636935a| plan9 CSNEGW LO, R23, R19, R22
+ba3484da| plan9 CSNEG LO, R5, R4, R26
+e3343e1e| plan9 FCCMPS LO, F30, F7, $3
+ce366a1e| plan9 FCCMPD LO, F10, F22, $14
+de37271e| plan9 FCCMPES LO, F7, F30, $14
+1935751e| plan9 FCCMPED LO, F21, F8, $9
+603f241e| plan9 FCSELS LO, F27, F4, F0
+653f761e| plan9 FCSELD LO, F27, F22, F5
+a4fa5354| plan9 BMI 171989(PC)
+a248483a| plan9 CCMNW MI, R5, $8, $2
+e2484eba| plan9 CCMN MI, R7, $14, $2
+2841553a| plan9 CCMNW MI, R9, R21, $8
+6e4259ba| plan9 CCMN MI, R19, R25, $14
+2048567a| plan9 CCMPW MI, R1, $22, $0
+454a5afa| plan9 CCMP MI, R18, $26, $5
+0343487a| plan9 CCMPW MI, R24, R8, $3
+49434bfa| plan9 CCMP MI, R26, R11, $9
+d747991a| plan9 CSINCW MI, R30, R25, R23
+9544919a| plan9 CSINC MI, R4, R17, R21
+76428c5a| plan9 CSINVW MI, R19, R12, R22
+06418eda| plan9 CSINV MI, R8, R14, R6
+4d46975a| plan9 CSNEGW MI, R18, R23, R13
+d74491da| plan9 CSNEG MI, R6, R17, R23
+0941941a| plan9 CSELW MI, R8, R20, R9
+2d41839a| plan9 CSEL MI, R9, R3, R13
+ef479f1a| plan9 CSETW PL, R15
+e5479f9a| plan9 CSET PL, R5
+f0439f5a| plan9 CSETMW PL, R16
+e2439fda| plan9 CSETM PL, R2
+2a46841a| plan9 CSINCW MI, R17, R4, R10
+f1468b9a| plan9 CSINC MI, R23, R11, R17
+3441835a| plan9 CSINVW MI, R9, R3, R20
+b5438cda| plan9 CSINV MI, R29, R12, R21
+ad45945a| plan9 CSNEGW MI, R13, R20, R13
+f54793da| plan9 CSNEG MI, ZR, R19, R21
+c5473f1e| plan9 FCCMPS MI, F31, F30, $5
+8947601e| plan9 FCCMPD MI, F0, F28, $9
+5247331e| plan9 FCCMPES MI, F19, F26, $2
+b045761e| plan9 FCCMPED MI, F22, F13, $0
+b34d331e| plan9 FCSELS MI, F13, F19, F19
+3a4d6d1e| plan9 FCSELD MI, F9, F13, F26
+a5497054| plan9 BPL 229965(PC)
+eb5a493a| plan9 CCMNW PL, R23, $9, $11
+0a5941ba| plan9 CCMN PL, R8, $1, $10
+0452523a| plan9 CCMNW PL, R16, R18, $4
+e55053ba| plan9 CCMN PL, R7, R19, $5
+a45b407a| plan9 CCMPW PL, R29, $0, $4
+ca5b4efa| plan9 CCMP PL, R30, $14, $10
+ab514e7a| plan9 CCMPW PL, R13, R14, $11
+ce5349fa| plan9 CCMP PL, R30, R9, $14
+8555971a| plan9 CSINCW PL, R12, R23, R5
+4b569e9a| plan9 CSINC PL, R18, R30, R11
+90538f5a| plan9 CSINVW PL, R28, R15, R16
+c3508bda| plan9 CSINV PL, R6, R11, R3
+1f55955a| plan9 CSNEGW PL, R8, R21, ZR
+52568eda| plan9 CSNEG PL, R18, R14, R18
+a750851a| plan9 CSELW PL, R5, R5, R7
+b252899a| plan9 CSEL PL, R21, R9, R18
+eb579f1a| plan9 CSETW MI, R11
+e6579f9a| plan9 CSET MI, R6
+fd539f5a| plan9 CSETMW MI, R29
+e1539fda| plan9 CSETM MI, R1
+33579e1a| plan9 CSINCW PL, R25, R30, R19
+b5558c9a| plan9 CSINC PL, R13, R12, R21
+ec53885a| plan9 CSINVW PL, ZR, R8, R12
+ec5196da| plan9 CSINV PL, R15, R22, R12
+ae57945a| plan9 CSNEGW PL, R29, R20, R14
+64578bda| plan9 CSNEG PL, R27, R11, R4
+2657241e| plan9 FCCMPS PL, F4, F25, $6
+2357761e| plan9 FCCMPD PL, F22, F25, $3
+f255361e| plan9 FCCMPES PL, F22, F15, $2
+3756781e| plan9 FCCMPED PL, F24, F17, $7
+985c3f1e| plan9 FCSELS PL, F4, F31, F24
+5b5d621e| plan9 FCSELD PL, F10, F2, F27
+c6d26454| plan9 BVS 206486(PC)
+6c6a4f3a| plan9 CCMNW VS, R19, $15, $12
+2f694cba| plan9 CCMN VS, R9, $12, $15
+e962583a| plan9 CCMNW VS, R23, R24, $9
+80615fba| plan9 CCMN VS, R12, ZR, $0
+4b6b497a| plan9 CCMPW VS, R26, $9, $11
+cc6a48fa| plan9 CCMP VS, R22, $8, $12
+4e61567a| plan9 CCMPW VS, R10, R22, $14
+476054fa| plan9 CCMP VS, R2, R20, $7
+c965911a| plan9 CSINCW VS, R14, R17, R9
+41668f9a| plan9 CSINC VS, R18, R15, R1
+db608f5a| plan9 CSINVW VS, R6, R15, R27
+896097da| plan9 CSINV VS, R4, R23, R9
+1867915a| plan9 CSNEGW VS, R24, R17, R24
+49678eda| plan9 CSNEG VS, R26, R14, R9
+3162881a| plan9 CSELW VS, R17, R8, R17
+db608f9a| plan9 CSEL VS, R6, R15, R27
+f9679f1a| plan9 CSETW VC, R25
+f9679f9a| plan9 CSET VC, R25
+f7639f5a| plan9 CSETMW VC, R23
+e1639fda| plan9 CSETM VC, R1
+f4678a1a| plan9 CSINCW VS, ZR, R10, R20
+3e65879a| plan9 CSINC VS, R9, R7, R30
+6c63975a| plan9 CSINVW VS, R27, R23, R12
+806191da| plan9 CSINV VS, R12, R17, R0
+7f679f5a| plan9 CSNEGW VS, R27, ZR, ZR
+3b6488da| plan9 CSNEG VS, R1, R8, R27
+0565301e| plan9 FCCMPS VS, F16, F8, $5
+e266621e| plan9 FCCMPD VS, F2, F23, $2
+b7653a1e| plan9 FCCMPES VS, F26, F13, $7
+d866791e| plan9 FCCMPED VS, F25, F22, $8
+326d3d1e| plan9 FCSELS VS, F9, F29, F18
+f66e7b1e| plan9 FCSELD VS, F23, F27, F22
+e774fd54| plan9 BVC -5209(PC)
+0479483a| plan9 CCMNW VC, R8, $8, $4
+897b56ba| plan9 CCMN VC, R28, $22, $9
+8b70513a| plan9 CCMNW VC, R4, R17, $11
+ca7150ba| plan9 CCMN VC, R14, R16, $10
+46794f7a| plan9 CCMPW VC, R10, $15, $6
+057948fa| plan9 CCMP VC, R8, $8, $5
+0373417a| plan9 CCMPW VC, R24, R1, $3
+ca705ffa| plan9 CCMP VC, R6, ZR, $10
+d3769f1a| plan9 CSINCW VC, R22, ZR, R19
+1076899a| plan9 CSINC VC, R16, R9, R16
+c8718e5a| plan9 CINVW VS, R14, R8
+06729eda| plan9 CSINV VC, R16, R30, R6
+6076895a| plan9 CSNEGW VC, R19, R9, R0
+b87589da| plan9 CSNEG VC, R13, R9, R24
+3b72891a| plan9 CSELW VC, R17, R9, R27
+fd70899a| plan9 CSEL VC, R7, R9, R29
+e3779f1a| plan9 CSETW VS, R3
+f4779f9a| plan9 CSET VS, R20
+fc739f5a| plan9 CSETMW VS, R28
+ea739fda| plan9 CSETM VS, R10
+ab75891a| plan9 CSINCW VC, R13, R9, R11
+6177859a| plan9 CSINC VC, R27, R5, R1
+3272945a| plan9 CSINVW VC, R17, R20, R18
+7a729dda| plan9 CSINV VC, R19, R29, R26
+b5779e5a| plan9 CSNEGW VC, R29, R30, R21
+fe748eda| plan9 CSNEG VC, R7, R14, R30
+ed76231e| plan9 FCCMPS VC, F3, F23, $13
+cf74791e| plan9 FCCMPD VC, F25, F6, $15
+b4763e1e| plan9 FCCMPES VC, F30, F21, $4
+59766e1e| plan9 FCCMPED VC, F14, F18, $9
+ce7c271e| plan9 FCSELS VC, F6, F7, F14
+be7c651e| plan9 FCSELD VC, F5, F5, F30
+88f29d54| plan9 BHI -200812(PC)
+8f8b513a| plan9 CCMNW HI, R28, $17, $15
+6f8b5cba| plan9 CCMN HI, R27, $28, $15
+8780463a| plan9 CCMNW HI, R4, R6, $7
+4f8348ba| plan9 CCMN HI, R26, R8, $15
+48884d7a| plan9 CCMPW HI, R2, $13, $8
+088957fa| plan9 CCMP HI, R8, $23, $8
+0180517a| plan9 CCMPW HI, R0, R17, $1
+ce805efa| plan9 CCMP HI, R6, R30, $14
+1d868e1a| plan9 CSINCW HI, R16, R14, R29
+0785889a| plan9 CINC LS, R8, R7
+4782935a| plan9 CSINVW HI, R18, R19, R7
+118197da| plan9 CSINV HI, R8, R23, R17
+00868a5a| plan9 CSNEGW HI, R16, R10, R0
+128585da| plan9 CSNEG HI, R8, R5, R18
+4c808f1a| plan9 CSELW HI, R2, R15, R12
+7783909a| plan9 CSEL HI, R27, R16, R23
+e5879f1a| plan9 CSETW LS, R5
+f3879f9a| plan9 CSET LS, R19
+f9839f5a| plan9 CSETMW LS, R25
+eb839fda| plan9 CSETM LS, R11
+b3869e1a| plan9 CSINCW HI, R21, R30, R19
+f086909a| plan9 CSINC HI, R23, R16, R16
+34839c5a| plan9 CSINVW HI, R25, R28, R20
+ea8294da| plan9 CSINV HI, R23, R20, R10
+8e84895a| plan9 CSNEGW HI, R4, R9, R14
+c48695da| plan9 CSNEG HI, R22, R21, R4
+cc84361e| plan9 FCCMPS HI, F22, F6, $12
+8086781e| plan9 FCCMPD HI, F24, F20, $0
+7187341e| plan9 FCCMPES HI, F20, F27, $1
+30867e1e| plan9 FCCMPED HI, F30, F17, $0
+b98e361e| plan9 FCSELS HI, F21, F22, F25
+2c8c651e| plan9 FCSELD HI, F1, F5, F12
+69888c54| plan9 BLS -236477(PC)
+0e9b523a| plan9 CCMNW LS, R24, $18, $14
+679854ba| plan9 CCMN LS, R3, $20, $7
+0492563a| plan9 CCMNW LS, R16, R22, $4
+42924dba| plan9 CCMN LS, R18, R13, $2
+2198417a| plan9 CCMPW LS, R1, $1, $1
+c89a54fa| plan9 CCMP LS, R22, $20, $8
+0f905e7a| plan9 CCMPW LS, R0, R30, $15
+c59342fa| plan9 CCMP LS, R30, R2, $5
+0d958c1a| plan9 CSINCW LS, R8, R12, R13
+7596879a| plan9 CSINC LS, R19, R7, R21
+1791905a| plan9 CSINVW LS, R8, R16, R23
+5e9186da| plan9 CSINV LS, R10, R6, R30
+23969e5a| plan9 CSNEGW LS, R17, R30, R3
+619493da| plan9 CSNEG LS, R3, R19, R1
+b5918e1a| plan9 CSELW LS, R13, R14, R21
+b393819a| plan9 CSEL LS, R29, R1, R19
+f9979f1a| plan9 CSETW HI, R25
+ee979f9a| plan9 CSET HI, R14
+eb939f5a| plan9 CSETMW HI, R11
+ea939fda| plan9 CSETM HI, R10
+f497871a| plan9 CSINCW LS, ZR, R7, R20
+c4949d9a| plan9 CSINC LS, R6, R29, R4
+e892895a| plan9 CSINVW LS, R23, R9, R8
+6c908eda| plan9 CSINV LS, R3, R14, R12
+26949f5a| plan9 CSNEGW LS, R1, ZR, R6
+329498da| plan9 CSNEG LS, R1, R24, R18
+81952d1e| plan9 FCCMPS LS, F13, F12, $1
+60967f1e| plan9 FCCMPD LS, F31, F19, $0
+1794321e| plan9 FCCMPES LS, F18, F0, $7
+3f97641e| plan9 FCCMPED LS, F4, F25, $15
+089c2d1e| plan9 FCSELS LS, F0, F13, F8
+699f631e| plan9 FCSELD LS, F27, F3, F9
+8afbfe54| plan9 BGE -2084(PC)
+44aa573a| plan9 CCMNW GE, R18, $23, $4
+00a84fba| plan9 CCMN GE, R0, $15, $0
+c9a04d3a| plan9 CCMNW GE, R6, R13, $9
+88a041ba| plan9 CCMN GE, R4, R1, $8
+caaa467a| plan9 CCMPW GE, R22, $6, $10
+85a85cfa| plan9 CCMP GE, R4, $28, $5
+47a35f7a| plan9 CCMPW GE, R26, ZR, $7
+0aa34dfa| plan9 CCMP GE, R24, R13, $10
+dea7981a| plan9 CSINCW GE, R30, R24, R30
+c6a5909a| plan9 CSINC GE, R14, R16, R6
+8aa1965a| plan9 CSINVW GE, R12, R22, R10
+e3a392da| plan9 CSINV GE, ZR, R18, R3
+20a5845a| plan9 CSNEGW GE, R9, R4, R0
+fba694da| plan9 CSNEG GE, R23, R20, R27
+faa1851a| plan9 CSELW GE, R15, R5, R26
+25a3959a| plan9 CSEL GE, R25, R21, R5
+e2a79f1a| plan9 CSETW LT, R2
+fda79f9a| plan9 CSET LT, R29
+eea39f5a| plan9 CSETMW LT, R14
+e2a39fda| plan9 CSETM LT, R2
+efa6951a| plan9 CSINCW GE, R23, R21, R15
+4ca69e9a| plan9 CSINC GE, R18, R30, R12
+22a2885a| plan9 CSINVW GE, R17, R8, R2
+53a089da| plan9 CSINV GE, R2, R9, R19
+f9a6875a| plan9 CSNEGW GE, R23, R7, R25
+c9a795da| plan9 CSNEG GE, R30, R21, R9
+24a73e1e| plan9 FCCMPS GE, F30, F25, $4
+6da5651e| plan9 FCCMPD GE, F5, F11, $13
+bda52e1e| plan9 FCCMPES GE, F14, F13, $13
+f6a7651e| plan9 FCCMPED GE, F5, F31, $6
+e3ac251e| plan9 FCSELS GE, F7, F5, F3
+b3ae781e| plan9 FCSELD GE, F21, F24, F19
+ab621754| plan9 BLT 47893(PC)
+e1b84c3a| plan9 CCMNW LT, R7, $12, $1
+89ba4eba| plan9 CCMN LT, R20, $14, $9
+88b14a3a| plan9 CCMNW LT, R12, R10, $8
+89b145ba| plan9 CCMN LT, R12, R5, $9
+47b9547a| plan9 CCMPW LT, R10, $20, $7
+07b95bfa| plan9 CCMP LT, R8, $27, $7
+4ab2407a| plan9 CCMPW LT, R18, R0, $10
+8ab144fa| plan9 CCMP LT, R12, R4, $10
+79b5821a| plan9 CSINCW LT, R11, R2, R25
+8bb4919a| plan9 CSINC LT, R4, R17, R11
+c9b19f5a| plan9 CSINVW LT, R14, ZR, R9
+10b28bda| plan9 CSINV LT, R16, R11, R16
+d8b4925a| plan9 CSNEGW LT, R6, R18, R24
+3ab69fda| plan9 CSNEG LT, R17, ZR, R26
+2cb3841a| plan9 CSELW LT, R25, R4, R12
+77b0969a| plan9 CSEL LT, R3, R22, R23
+e2b79f1a| plan9 CSETW GE, R2
+e9b79f9a| plan9 CSET GE, R9
+f4b39f5a| plan9 CSETMW GE, R20
+f2b39fda| plan9 CSETM GE, R18
+87b59a1a| plan9 CSINCW LT, R12, R26, R7
+70b69c9a| plan9 CSINC LT, R19, R28, R16
+17b08f5a| plan9 CSINVW LT, R0, R15, R23
+cab288da| plan9 CSINV LT, R22, R8, R10
+bab7905a| plan9 CSNEGW LT, R29, R16, R26
+08b796da| plan9 CSNEG LT, R24, R22, R8
+2eb73e1e| plan9 FCCMPS LT, F30, F25, $14
+86b7671e| plan9 FCCMPD LT, F7, F28, $6
+f0b6211e| plan9 FCCMPES LT, F1, F23, $0
+b2b76b1e| plan9 FCCMPED LT, F11, F29, $2
+e8bf241e| plan9 FCSELS LT, F31, F4, F8
+9ebd7d1e| plan9 FCSELD LT, F12, F29, F30
+cc87d354| plan9 BGT -91074(PC)
+43c8563a| plan9 CCMNW GT, R2, $22, $3
+c5c94dba| plan9 CCMN GT, R14, $13, $5
+6fc0533a| plan9 CCMNW GT, R3, R19, $15
+06c351ba| plan9 CCMN GT, R24, R17, $6
+c3c95c7a| plan9 CCMPW GT, R14, $28, $3
+29cb52fa| plan9 CCMP GT, R25, $18, $9
+8bc25a7a| plan9 CCMPW GT, R20, R26, $11
+45c14dfa| plan9 CCMP GT, R10, R13, $5
+80c7841a| plan9 CSINCW GT, R28, R4, R0
+40c4919a| plan9 CSINC GT, R2, R17, R0
+04c2805a| plan9 CSINVW GT, R16, R0, R4
+55c086da| plan9 CSINV GT, R2, R6, R21
+32c7935a| plan9 CSNEGW GT, R25, R19, R18
+31c59fda| plan9 CSNEG GT, R9, ZR, R17
+6cc2921a| plan9 CSELW GT, R19, R18, R12
+37c08d9a| plan9 CSEL GT, R1, R13, R23
+eec79f1a| plan9 CSETW LE, R14
+eec79f9a| plan9 CSET LE, R14
+f4c39f5a| plan9 CSETMW LE, R20
+f6c39fda| plan9 CSETM LE, R22
+31c5971a| plan9 CSINCW GT, R9, R23, R17
+76c7899a| plan9 CSINC GT, R27, R9, R22
+bbc1805a| plan9 CSINVW GT, R13, R0, R27
+e8c384da| plan9 CSINV GT, ZR, R4, R8
+83c5955a| plan9 CSNEGW GT, R12, R21, R3
+77c790da| plan9 CSNEG GT, R27, R16, R23
+e9c5251e| plan9 FCCMPS GT, F5, F15, $9
+a3c4671e| plan9 FCCMPD GT, F7, F5, $3
+71c72e1e| plan9 FCCMPES GT, F14, F27, $1
+3dc4781e| plan9 FCCMPED GT, F24, F1, $13
+57cf3d1e| plan9 FCSELS GT, F26, F29, F23
+8fcc7e1e| plan9 FCSELD GT, F4, F30, F15
+8d1ec054| plan9 BLE -130828(PC)
+4bdb5b3a| plan9 CCMNW LE, R26, $27, $11
+47d94fba| plan9 CCMN LE, R10, $15, $7
+4dd1443a| plan9 CCMNW LE, R10, R4, $13
+82d353ba| plan9 CCMN LE, R28, R19, $2
+e8d9527a| plan9 CCMPW LE, R15, $18, $8
+00db45fa| plan9 CCMP LE, R24, $5, $0
+c5d1437a| plan9 CCMPW LE, R14, R3, $5
+e4d041fa| plan9 CCMP LE, R7, R1, $4
+0bd6941a| plan9 CSINCW LE, R16, R20, R11
+57d6929a| plan9 CINC GT, R18, R23
+3dd29a5a| plan9 CSINVW LE, R17, R26, R29
+ded085da| plan9 CSINV LE, R6, R5, R30
+27d5985a| plan9 CSNEGW LE, R9, R24, R7
+7fd59ada| plan9 CSNEG LE, R11, R26, ZR
+b7d0911a| plan9 CSELW LE, R5, R17, R23
+a4d3879a| plan9 CSEL LE, R29, R7, R4
+e6d79f1a| plan9 CSETW GT, R6
+f1d79f9a| plan9 CSET GT, R17
+f3d39f5a| plan9 CSETMW GT, R19
+f9d39fda| plan9 CSETM GT, R25
+42d78d1a| plan9 CSINCW LE, R26, R13, R2
+88d58a9a| plan9 CSINC LE, R12, R10, R8
+ccd3805a| plan9 CSINVW LE, R30, R0, R12
+0fd085da| plan9 CSINV LE, R0, R5, R15
+55d5975a| plan9 CSNEGW LE, R10, R23, R21
+3fd699da| plan9 CSNEG LE, R17, R25, ZR
+60d4251e| plan9 FCCMPS LE, F5, F3, $0
+6dd6601e| plan9 FCCMPD LE, F0, F19, $13
+bdd5221e| plan9 FCCMPES LE, F2, F13, $13
+f4d67d1e| plan9 FCCMPED LE, F29, F23, $4
+0cdd381e| plan9 FCSELS LE, F8, F24, F12
+70de7e1e| plan9 FCSELD LE, F19, F30, F16
+8e585454| plan9 BAL 172740(PC)
+41eb483a| plan9 CCMNW AL, R26, $8, $1
+8aeb42ba| plan9 CCMN AL, R28, $2, $10
+c8e3473a| plan9 CCMNW AL, R30, R7, $8
+ade059ba| plan9 CCMN AL, R5, R25, $13
+67eb5b7a| plan9 CCMPW AL, R27, $27, $7
+05e849fa| plan9 CCMP AL, R0, $9, $5
+42e3407a| plan9 CCMPW AL, R26, R0, $2
+03e053fa| plan9 CCMP AL, R0, R19, $3
+9ce4931a| plan9 CSINCW AL, R4, R19, R28
+8ee69d9a| plan9 CSINC AL, R20, R29, R14
+68e0835a| plan9 CSINVW AL, R3, R3, R8
+20e381da| plan9 CSINV AL, R25, R1, R0
+e0e58d5a| plan9 CSNEGW AL, R15, R13, R0
+9ae589da| plan9 CSNEG AL, R12, R9, R26
+6ee0941a| plan9 CSELW AL, R3, R20, R14
+77e38a9a| plan9 CSEL AL, R27, R10, R23
+efe79f1a| plan9 CSINCW AL, ZR, ZR, R15
+e5e79f9a| plan9 CSINC AL, ZR, ZR, R5
+f2e39f5a| plan9 CSINVW AL, ZR, ZR, R18
+fae39fda| plan9 CSINV AL, ZR, ZR, R26
+ede7861a| plan9 CSINCW AL, ZR, R6, R13
+0ce58a9a| plan9 CSINC AL, R8, R10, R12
+75e2835a| plan9 CSINVW AL, R19, R3, R21
+38e391da| plan9 CSINV AL, R25, R17, R24
+fee4845a| plan9 CSNEGW AL, R7, R4, R30
+09e49bda| plan9 CSNEG AL, R0, R27, R9
+a8e6271e| plan9 FCCMPS AL, F7, F21, $8
+ede67d1e| plan9 FCCMPD AL, F29, F23, $13
+bbe53b1e| plan9 FCCMPES AL, F27, F13, $11
+70e6661e| plan9 FCCMPED AL, F6, F19, $0
+01ee3b1e| plan9 FCSELS AL, F16, F27, F1
+15ec651e| plan9 FCSELD AL, F0, F5, F21
+4f462554| plan9 BAL 76338(PC)
+eef9493a| plan9 CCMNW AL, R15, $9, $14
+88fa53ba| plan9 CCMN AL, R20, $19, $8
+c0f25f3a| plan9 CCMNW AL, R22, ZR, $0
+c6f05cba| plan9 CCMN AL, R6, R28, $6
+45f84c7a| plan9 CCMPW AL, R2, $12, $5
+a3fa4afa| plan9 CCMP AL, R21, $10, $3
+caf3517a| plan9 CCMPW AL, R30, R17, $10
+81f055fa| plan9 CCMP AL, R4, R21, $1
+cbf69e1a| plan9 CSINCW AL, R22, R30, R11
+01f48e9a| plan9 CSINC AL, R0, R14, R1
+61f1845a| plan9 CSINVW AL, R11, R4, R1
+11f397da| plan9 CSINV AL, R24, R23, R17
+7bf69f5a| plan9 CSNEGW AL, R19, ZR, R27
+b1f686da| plan9 CSNEG AL, R21, R6, R17
+69f39e1a| plan9 CSELW AL, R27, R30, R9
+79f2859a| plan9 CSEL AL, R19, R5, R25
+e1f79f1a| plan9 CSINCW AL, ZR, ZR, R1
+e6f79f9a| plan9 CSINC AL, ZR, ZR, R6
+fcf39f5a| plan9 CSINVW AL, ZR, ZR, R28
+fbf39fda| plan9 CSINV AL, ZR, ZR, R27
+2ef4831a| plan9 CSINCW AL, R1, R3, R14
+55f6859a| plan9 CSINC AL, R18, R5, R21
+4ff0905a| plan9 CSINVW AL, R2, R16, R15
+81f393da| plan9 CSINV AL, R28, R19, R1
+8bf68d5a| plan9 CSNEGW AL, R20, R13, R11
+c2f48fda| plan9 CSNEG AL, R6, R15, R2
+e9f6391e| plan9 FCCMPS AL, F25, F23, $9
+27f46f1e| plan9 FCCMPD AL, F15, F1, $7
+72f6301e| plan9 FCCMPES AL, F16, F19, $2
+37f57a1e| plan9 FCCMPED AL, F26, F9, $7
+fcfe3a1e| plan9 FCSELS AL, F23, F26, F28
+80fd701e| plan9 FCSELD AL, F12, F16, F0
+40946454| plan9 BEQ 205986(PC)
+8b09473a| plan9 CCMNW EQ, R12, $7, $11
+c50a5eba| plan9 CCMN EQ, R22, $30, $5
+05005a3a| plan9 CCMNW EQ, R0, R26, $5
+cf024bba| plan9 CCMN EQ, R22, R11, $15
+8a084f7a| plan9 CCMPW EQ, R4, $15, $10
+e20a41fa| plan9 CCMP EQ, R23, $1, $2
+8c015f7a| plan9 CCMPW EQ, R12, ZR, $12
+e4015cfa| plan9 CCMP EQ, R15, R28, $4
+42078e1a| plan9 CSINCW EQ, R26, R14, R2
+2005879a| plan9 CSINC EQ, R9, R7, R0
+f003955a| plan9 CSINVW EQ, ZR, R21, R16
+dc019dda| plan9 CSINV EQ, R14, R29, R28
+4607885a| plan9 CSNEGW EQ, R26, R8, R6
+26069eda| plan9 CSNEG EQ, R17, R30, R6
+72018a1a| plan9 CSELW EQ, R11, R10, R18
+8003849a| plan9 CSEL EQ, R28, R4, R0
+f1079f1a| plan9 CSETW NE, R17
+fb079f9a| plan9 CSET NE, R27
+ef039f5a| plan9 CSETMW NE, R15
+e1039fda| plan9 CSETM NE, R1
+5307881a| plan9 CSINCW EQ, R26, R8, R19
+8a06969a| plan9 CSINC EQ, R20, R22, R10
+ab00955a| plan9 CSINVW EQ, R5, R21, R11
+c3039bda| plan9 CSINV EQ, R30, R27, R3
+8005875a| plan9 CSNEGW EQ, R12, R7, R0
+740694da| plan9 CSNEG EQ, R19, R20, R20
+e207281e| plan9 FCCMPS EQ, F8, F31, $2
+2b056a1e| plan9 FCCMPD EQ, F10, F9, $11
+7e063f1e| plan9 FCCMPES EQ, F31, F19, $14
+3c05671e| plan9 FCCMPED EQ, F7, F9, $12
+830f271e| plan9 FCSELS EQ, F28, F7, F3
+4d0d621e| plan9 FCSELD EQ, F10, F2, F13
+bf2003d5| plan9 SEVL
+9f2003d5| plan9 SEV
+7f2003d5| plan9 WFI
+5f2003d5| plan9 WFE
+3f2003d5| plan9 YIELD
+1f2003d5| plan9 NOP
+df4d03d5| plan9 MSR $13, DAIFSET
+ff4d03d5| plan9 MSR $13, DAIFCLR
+28d91b14| plan9 JMP 1825064(PC)
+15e5e514| plan9 JMP 15066389(PC)
+ff4603d5| plan9 MSR $6, DAIFCLR
+df4803d5| plan9 MSR $8, DAIFSET
+bf4100d5| plan9 MSR $1, SPSEL
+9f3f03d5| plan9 DSB $15
+9f3e03d5| plan9 DSB $14
+9f3d03d5| plan9 DSB $13
+9f3b03d5| plan9 DSB $11
+9f3a03d5| plan9 DSB $10
+9f3903d5| plan9 DSB $9
+9f3703d5| plan9 DSB $7
+9f3603d5| plan9 DSB $6
+9f3503d5| plan9 DSB $5
+9f3303d5| plan9 DSB $3
+9f3203d5| plan9 DSB $2
+9f3103d5| plan9 DSB $1
+ff4603d5| plan9 MSR $6, DAIFCLR
+df4803d5| plan9 MSR $8, DAIFSET
+bf4100d5| plan9 MSR $1, SPSEL
+a3681b53| plan9 LSLW $5, R5, R3
+47dc78d3| plan9 LSL $8, R2, R7
+0500a012| plan9 MOVNW $(0<<16), R5
+0500e092| plan9 MOVN $(0<<48), R5
+0500a052| plan9 MOVZW $(0<<16), R5
+0500a0d2| plan9 MOVZ $(0<<16), R5
+cd5a206e| plan9 VMVN V22.B16, V13.B16
+cd5a202e| plan9 VMVN V22.B8, V13.B8
+743d050e| plan9 UMOVW V11.B[2], R20
+743d0a0e| plan9 UMOVW V11.H[2], R20
+743d0c0e| plan9 VMOV V11.S[1], R20
+743d084e| plan9 VMOV V11.D[0], R20
diff --git a/arm64/arm64spec/spec.go b/arm64/arm64spec/spec.go
new file mode 100644
index 0000000..ee784e5
--- /dev/null
+++ b/arm64/arm64spec/spec.go
@@ -0,0 +1,714 @@
+// Copyright 2017 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// arm64spec reads the ``ARMv8-A Reference Manual''
+// to collect instruction encoding details and writes those
+// details to standard output in JSON format.
+// usage: arm64spec file.pdf
+
+package main
+
+import (
+ "bufio"
+ "bytes"
+ "encoding/json"
+ "fmt"
+ "log"
+ "math"
+ "os"
+ "regexp"
+ "sort"
+ "strconv"
+ "strings"
+
+ "rsc.io/pdf"
+)
+
+type Inst struct {
+ Name string
+ Bits string
+ Arch string
+ Syntax string
+ Code string
+ Alias string
+}
+
+const debugPage = 0
+
+var stdout *bufio.Writer
+
+func check(e error) {
+ if e != nil {
+ panic(e)
+ }
+}
+
+func main() {
+ log.SetFlags(0)
+ log.SetPrefix("arm64spec: ")
+
+ if len(os.Args) != 2 {
+ fmt.Fprintf(os.Stderr, "usage: arm64spec file.pdf\n")
+ os.Exit(2)
+ }
+ f, err := pdf.Open(os.Args[1])
+ if err != nil {
+ log.Fatal(err)
+ }
+
+ // Find instruction set reference in outline, to build instruction list.
+ instList := instHeadings(f.Outline())
+ if debugPage == 0 {
+ fmt.Println("the number of instructions:", len(instList))
+ }
+ if len(instList) < 200 {
+ log.Fatalf("only found %d instructions in table of contents", len(instList))
+ }
+
+ file, err := os.Create("inst.json")
+ check(err)
+ w := bufio.NewWriter(file)
+ _, err = w.WriteString("[")
+ check(err)
+ numTable := 0
+ defer w.Flush()
+ defer file.Close()
+
+ // Scan document looking for instructions.
+ // Must find exactly the ones in the outline.
+ n := f.NumPage()
+PageLoop:
+ for pageNum := 435; pageNum <= n; pageNum++ {
+ if debugPage > 0 && pageNum != debugPage {
+ continue
+ }
+ if pageNum == 770 {
+ continue
+ }
+ if pageNum > 1495 {
+ break
+ }
+ p := f.Page(pageNum)
+ name, table := parsePage(pageNum, p, f)
+ if name == "" {
+ continue
+ }
+ if len(table) < 1 {
+ if false {
+ fmt.Fprintf(os.Stderr, "no encodings for instruction %q (page %d)\n", name, pageNum)
+ }
+ continue
+ }
+ for _, inst := range table {
+ if numTable > 0 {
+ _, err = w.WriteString(jsFix.Replace(","))
+ check(err)
+ _, err = w.WriteString("\n")
+ check(err)
+ }
+ numTable++
+ js, _ := json.Marshal(inst)
+ _, err = w.WriteString(jsFix.Replace(string(js)))
+ check(err)
+ }
+ for j, headline := range instList {
+ if name == headline {
+ instList[j] = ""
+ continue PageLoop
+ }
+ }
+ fmt.Fprintf(os.Stderr, "unexpected instruction %q (page %d)\n", name, pageNum)
+ }
+
+ _, err = w.WriteString("\n]\n")
+ check(err)
+ w.Flush()
+
+ if debugPage == 0 {
+ for _, headline := range instList {
+ if headline != "" {
+ fmt.Fprintf(os.Stderr, "missing instruction %q\n", headline)
+ }
+ }
+ }
+}
+
+func instHeadings(outline pdf.Outline) []string {
+ return appendInstHeadings(outline, nil)
+}
+
+var instRE = regexp.MustCompile(`C[\d.]+ Alphabetical list of A64 base instructions`)
+var instRE_A = regexp.MustCompile(`C[\d.]+ Alphabetical list of A64 floating-point and Advanced SIMD instructions`)
+var childRE = regexp.MustCompile(`C[\d.]+ (.+)`)
+var sectionRE = regexp.MustCompile(`^C[\d.]+$`)
+var bitRE = regexp.MustCompile(`^( |[01]|\([01]\))*$`)
+var IMMRE = regexp.MustCompile(`^imm[\d]+$`)
+
+func appendInstHeadings(outline pdf.Outline, list []string) []string {
+ if instRE.MatchString(outline.Title) || instRE_A.MatchString(outline.Title) {
+ for _, child := range outline.Child {
+ m := childRE.FindStringSubmatch(child.Title)
+ if m == nil {
+ fmt.Fprintf(os.Stderr, "cannot parse section title: %s\n", child.Title)
+ continue
+ }
+ list = append(list, m[1])
+ }
+ }
+ for _, child := range outline.Child {
+ list = appendInstHeadings(child, list)
+ }
+ return list
+}
+
+const inch = 72.0
+
+func parsePage(num int, p pdf.Page, f *pdf.Reader) (name string, table []Inst) {
+ content := p.Content()
+ var text []pdf.Text
+ CrossTwoPage := true
+ for _, t := range content.Text {
+ text = append(text, t)
+ }
+ text = findWords(text)
+ if !(instRE.MatchString(text[1].S) || instRE_A.MatchString(text[1].S)) || len(text) == 0 || !sectionRE.MatchString(text[2].S) {
+ return "", nil
+ }
+ // Check whether the content crosses the page.
+ for _, t := range text {
+ if match(t, "Arial,Bold", 10, "Assembler symbols") {
+ CrossTwoPage = false
+ break
+ }
+ }
+ // Deal with cross page issue. To the next page content.
+ var Ncontent pdf.Content
+ Npagebox := false
+ CrossThreePage := false
+ Noffset := ""
+ if CrossTwoPage == true {
+ Np := f.Page(num + 1)
+ Ncontent = Np.Content()
+ var Ntext []pdf.Text
+ for _, t := range Ncontent.Text {
+ Ntext = append(Ntext, t)
+ }
+ Ntext = findWords(Ntext)
+ if len(Ntext) == 0 || sectionRE.MatchString(Ntext[2].S) {
+ Ntext = text[:0]
+ } else {
+ for _, t := range Ntext {
+ if match(t, "Arial,Bold", 10, "offset") {
+ Noffset = t.S
+ Npagebox = true
+ }
+ // This istruction cross three pages.
+ if match(t, "Arial,Bold", 10, "Assembler symbols") {
+ CrossThreePage = false
+ } else {
+ CrossThreePage = true
+ }
+ text = append(text, t)
+ }
+ }
+ }
+ if CrossThreePage == true {
+ NNp := f.Page(num + 2)
+ NNcontent := NNp.Content()
+ var NNtext []pdf.Text
+ for _, t := range NNcontent.Text {
+ NNtext = append(NNtext, t)
+ }
+ NNtext = findWords(NNtext)
+ if len(NNtext) == 0 || sectionRE.MatchString(NNtext[2].S) {
+ NNtext = text[:0]
+ } else {
+ for _, t := range NNtext {
+ text = append(text, t)
+ }
+ }
+ }
+ // Get alias and remove text we should ignore.
+ out := text[:0]
+ alias := ""
+ for _, t := range text {
+ if strings.Contains(t.S, "instruction is used by the alias") || strings.Contains(t.S, "instruction is an alias of") {
+ alias_t := strings.SplitAfter(t.S, ".")
+ alias = alias_t[0]
+ }
+ // Skip page footer
+ if match(t, "Arial-ItalicMT", 8, "") || match(t, "ArialMT", 8, "") {
+ if debugPage > 0 {
+ fmt.Println("==the skip page footer is:==", t)
+ }
+ continue
+ }
+ // Skip the body text
+ if match(t, "TimesNewRoman", 9, "") || match(t, "TimesNewRomanPS-ItalicMT", 9, "") {
+ if debugPage > 0 {
+ fmt.Println("==the skip body text is:==", t)
+ }
+ continue
+ }
+ out = append(out, t)
+ }
+ text = out
+ // Page header must be child title.
+ if len(text) == 0 || !sectionRE.MatchString(text[0].S) {
+ return "", nil
+ }
+
+ name = text[1].S
+ inst := Inst{
+ Name: name,
+ Alias: alias,
+ }
+ text = text[2:]
+ // Skip body text before bits.
+ OffsetMark := false
+ k := 0
+ for k = 0; k < len(text); {
+ if !match(text[k], "Arial", 8, "31") {
+ k++
+ } else {
+ break
+ }
+ }
+ // Check offset.
+ if k > 0 && match(text[k-1], "Arial,Bold", 10, "") {
+ OffsetMark = true
+ text = text[k-1:]
+ } else {
+ text = text[k:]
+ }
+ // Encodings follow.
+ BitMark := false
+ bits := ""
+ // Find bits.
+ for i := 0; i < len(text); {
+ inst.Bits = ""
+ offset := ""
+ abits := ""
+ // Read bits only one time.
+ if OffsetMark == true {
+ for i < len(text) && !match(text[i], "Arial", 8, "") {
+ i++
+ }
+ if i < len(text) {
+ offset = text[i-1].S
+ BitMark = false
+ bits = ""
+ } else {
+ break
+ }
+ }
+ if BitMark == false {
+ if Npagebox == true && Noffset == offset {
+ bits, i = readBitBox(name, Ncontent, text, i)
+ } else {
+ bits, i = readBitBox(name, content, text, i)
+ }
+ BitMark = true
+ // Every time, get "then SEE" after get bits.
+ enc := false
+ if i < len(text)-1 {
+ m := i
+ for m < len(text)-1 && !match(text[m], "Arial-BoldItalicMT", 9, "encoding") {
+ m++
+ }
+ if match(text[m], "Arial-BoldItalicMT", 9, "encoding") && m < len(text) {
+ enc = true
+ m = m + 1
+ }
+ if enc == true {
+ for m < len(text) && !match(text[m], "Arial,Bold", 10, "") && match(text[m], "LucidaSansTypewriteX", 6.48, "") {
+ if strings.Contains(text[m].S, "then SEE") {
+ inst.Code = text[m].S
+ break
+ } else {
+ m++
+ }
+ }
+ }
+ }
+ }
+
+ // Possible subarchitecture notes.
+ ArchLoop:
+ for i < len(text) {
+ if !match(text[i], "Arial-BoldItalicMT", 9, "variant") || match(text[i], "Arial-BoldItalicMT", 9, "encoding") {
+ i++
+ continue
+ }
+ inst.Arch = ""
+ inst.Arch += offset
+ inst.Arch += " "
+ inst.Arch += text[i].S
+ inst.Arch = strings.TrimSpace(inst.Arch)
+ i++
+ // Encoding syntaxes.
+ sign := ""
+ SynMark := false
+ for i < len(text) && match(text[i], "LucidaSansTypewriteX", 6.48, "") && SynMark == false {
+ if (strings.Contains(text[i].S, "==") || strings.Contains(text[i].S, "!=")) && SynMark == false {
+ sign = text[i].S
+ i++
+ continue
+ }
+ // Avoid "equivalent to" another syntax.
+ if SynMark == false {
+ SynMark = true
+ inst.Syntax = ""
+ inst.Syntax = text[i].S
+ i++
+ }
+ }
+ abits = bits
+ // Analyse and replace some bits value.eg, sf==1
+ if strings.Contains(sign, "&&") {
+ split := strings.Split(sign, "&&")
+ for k := 0; k < len(split); {
+ if strings.Contains(split[k], "==") && !strings.Contains(split[k], "!") {
+ tmp := strings.Split(split[k], "==")
+ prefix := strings.TrimSpace(tmp[0])
+ value := strings.TrimSpace(tmp[1])
+ if strings.Contains(bits, prefix) && !strings.Contains(value, "x") {
+ abits = strings.Replace(abits, prefix, value, -1)
+ }
+ }
+ k++
+ }
+ } else if strings.Contains(sign, "==") && !strings.Contains(sign, "!") {
+ split := strings.Split(sign, "==")
+ prefix := strings.TrimSpace(split[0])
+ value := strings.TrimSpace(split[1])
+ if strings.Contains(bits, prefix) && !strings.Contains(value, "x") {
+ abits = strings.Replace(abits, prefix, value, -1)
+ }
+ }
+ // Deal with syntax contains {2}
+ if strings.Contains(inst.Syntax, "{2}") {
+ if !strings.Contains(abits, "Q") {
+ fmt.Fprintf(os.Stderr, "instruction%s - syntax%s: is wrong!!\n", name, inst.Syntax)
+ }
+ syn := inst.Syntax
+ bits := abits
+ for i := 0; i < 2; {
+ if i == 0 {
+ inst.Bits = strings.Replace(bits, "Q", "0", -1)
+ inst.Syntax = strings.Replace(syn, "{2}", "", -1)
+ table = append(table, inst)
+ }
+ if i == 1 {
+ inst.Bits = strings.Replace(bits, "Q", "1", -1)
+ inst.Syntax = strings.Replace(syn, "{2}", "2", -1)
+ table = append(table, inst)
+ }
+ i++
+ }
+ } else {
+ inst.Bits = abits
+ table = append(table, inst)
+ }
+
+ if OffsetMark == true && i < len(text) && match(text[i], "Arial-BoldItalicMT", 9, "variant") && !match(text[i], "Arial-BoldItalicMT", 9, "encoding") {
+ continue ArchLoop
+ } else {
+ break
+ }
+ }
+ }
+ return name, table
+}
+
+func readBitBox(name string, content pdf.Content, text []pdf.Text, i int) (string, int) {
+ // Bits headings
+ y3 := 0.0
+ x1 := 0.0
+ for i < len(text) && match(text[i], "Arial", 8, "") {
+ if y3 == 0 {
+ y3 = text[i].Y
+ }
+ if x1 == 0 {
+ x1 = text[i].X
+ }
+ if text[i].Y != y3 {
+ break
+ }
+ i++
+ }
+ // Bits fields in box
+ x2 := 0.0
+ y2 := 0.0
+ dy1 := 0.0
+ for i < len(text) && match(text[i], "Arial", 8, "") {
+ if x2 < text[i].X+text[i].W {
+ x2 = text[i].X + text[i].W
+ }
+ if y2 == 0 {
+ y2 = text[i].Y
+ }
+ if text[i].Y != y2 {
+ break
+ }
+ dy1 = text[i].FontSize
+ i++
+ }
+ // Bits fields below box
+ x3 := 0.0
+ y1 := 0.0
+ for i < len(text) && match(text[i], "Arial", 8, "") {
+ if x3 < text[i].X+text[i].W {
+ x3 = text[i].X + text[i].W
+ }
+ y1 = text[i].Y
+ if text[i].Y != y1 {
+ break
+ }
+ i++
+ }
+ //no bits fields below box
+ below_flag := true
+ if y1 == 0.0 {
+ below_flag = false
+ y1 = y2
+ }
+ // Encoding box
+ if debugPage > 0 {
+ fmt.Println("encoding box", x1, y3, x2, y1)
+ }
+
+ // Find lines (thin rectangles) separating bit fields.
+ var bottom, top pdf.Rect
+ const (
+ yMargin = 0.25 * 72
+ xMargin = 2 * 72
+ )
+ cont := 0
+ if below_flag == true {
+ for _, r := range content.Rect {
+ cont = cont + 1
+ if x1-xMargin < r.Min.X && r.Min.X < x1 && x2 < r.Max.X && r.Max.X < x2+xMargin {
+ if y1-yMargin < r.Min.Y && r.Min.Y < y2-dy1 {
+ bottom = r
+ }
+ if y2+dy1 < r.Min.Y && r.Min.Y < y3+yMargin {
+ top = r
+ }
+ }
+ }
+ } else {
+ for _, r := range content.Rect {
+ cont = cont + 1
+ if x1-xMargin < r.Min.X && r.Min.X < x1 && x2 < r.Max.X && r.Max.X < x2+xMargin {
+ if y1-yMargin-dy1 < r.Min.Y && r.Min.Y < y3-dy1 {
+ bottom = r
+ }
+ if y2+dy1 < r.Min.Y && r.Min.Y < y3+yMargin {
+ top = r
+ }
+ }
+ }
+ }
+
+ if debugPage > 0 {
+ fmt.Println("top", top, "bottom", bottom, "content.Rect number", cont)
+ }
+
+ const ε = 0.5 * 72
+ cont_1 := 0
+ var bars []pdf.Rect
+ for _, r := range content.Rect {
+ if math.Abs(r.Min.X-r.Max.X) < bottom.Max.X-bottom.Min.X-(ε/2) && math.Abs(r.Min.Y-bottom.Min.Y) < ε && math.Abs(r.Max.Y-top.Min.Y) < ε {
+ cont_1 = cont_1 + 1
+ bars = append(bars, r)
+ }
+ }
+ sort.Sort(RectHorizontal(bars))
+ if debugPage > 0 {
+ fmt.Println("==bars number==", cont_1)
+ }
+
+ // There are 16-bit and 32-bit encodings.
+ // In practice, they are about 2.65 and 5.3 inches wide, respectively.
+ // Use 4 inches as a cutoff.
+ nbit := 32
+ dx := top.Max.X - top.Min.X
+ if top.Max.X-top.Min.X < 4*72 {
+ nbit = 16
+ }
+
+ total := 0
+ var buf bytes.Buffer
+ for i := 0; i < len(bars); i++ {
+ if i > 0 {
+ fmt.Fprintf(&buf, "|")
+ }
+ var sub []pdf.Text
+ x1, x2 := bars[i].Min.X, bars[i].Max.X
+ for _, t := range content.Text {
+ tx := t.X + t.W/2
+ ty := t.Y
+ if x1 < tx && tx < x2 && y2-dy1 < ty && ty < y2+dy1 {
+ sub = append(sub, t)
+ }
+ }
+ var str []string
+ for _, t := range findWords(sub) {
+ str = append(str, t.S)
+ }
+ s := strings.Join(str, " ")
+ s = strings.Replace(s, ")(", ") (", -1)
+
+ // If bits contain "!" or "x", be replaced by the bits below it.
+ if strings.Contains(s, "!") || strings.Contains(s, "x") {
+ var sub1 []pdf.Text
+ for _, t := range content.Text {
+ tx := t.X + t.W/2
+ ty := t.Y
+ if x1 < tx && tx < x2 && y1-dy1 < ty && ty < y1+dy1 {
+ sub1 = append(sub1, t)
+ }
+
+ }
+ var str1 []string
+ for _, t := range findWords(sub1) {
+ str1 = append(str1, t.S)
+ }
+ s = strings.Join(str1, " ")
+ s = strings.Replace(s, ")(", ") (", -1)
+ }
+
+ n := len(strings.Fields(s))
+
+ var b int
+ if IMMRE.MatchString(s) {
+ bitNum := strings.TrimPrefix(s, "imm")
+ b, _ = strconv.Atoi(bitNum)
+ } else if s == "immhi" {
+ b = 19
+ } else {
+ b = int(float64(nbit)*(x2-x1)/dx + 0.5)
+ }
+ if n == b {
+ for k, f := range strings.Fields(s) {
+ if k > 0 {
+ fmt.Fprintf(&buf, "|")
+ }
+ fmt.Fprintf(&buf, "%s", f)
+ }
+ } else {
+ if n != 1 {
+ fmt.Fprintf(os.Stderr, "%s - multi-field %d-bit encoding: %s\n", name, n, s)
+ }
+ fmt.Fprintf(&buf, "%s:%d", s, b)
+ }
+ total += b
+ }
+
+ if total != nbit || total == 0 {
+ fmt.Fprintf(os.Stderr, "%s - %d-bit encoding\n", name, total)
+ }
+ return buf.String(), i
+}
+
+type RectHorizontal []pdf.Rect
+
+func (x RectHorizontal) Swap(i, j int) { x[i], x[j] = x[j], x[i] }
+func (x RectHorizontal) Less(i, j int) bool { return x[i].Min.X < x[j].Min.X }
+func (x RectHorizontal) Len() int { return len(x) }
+
+func checkNoEncodings(num int, text []pdf.Text) {
+ for _, t := range text {
+ if match(t, "Helvetica-Bold", 9, "Encoding") {
+ fmt.Fprintf(os.Stderr, "page %d: unexpected encoding: %s\n", num, t.S)
+ }
+ }
+}
+
+func match(t pdf.Text, font string, size float64, substr string) bool {
+ return t.Font == font && math.Abs(t.FontSize-size) < 0.1 && strings.Contains(t.S, substr)
+}
+
+func findWords(chars []pdf.Text) (words []pdf.Text) {
+ // Sort by Y coordinate and normalize.
+ const nudge = 1
+ sort.Sort(pdf.TextVertical(chars))
+ old := -100000.0
+ for i, c := range chars {
+ if c.Y != old && math.Abs(old-c.Y) < nudge {
+ chars[i].Y = old
+ } else {
+ old = c.Y
+ }
+ }
+
+ // Sort by Y coordinate, breaking ties with X.
+ // This will bring letters in a single word together.
+ sort.Sort(pdf.TextVertical(chars))
+
+ // Loop over chars.
+ for i := 0; i < len(chars); {
+ // Find all chars on line.
+ j := i + 1
+ for j < len(chars) && chars[j].Y == chars[i].Y {
+ j++
+ }
+ var end float64
+ // Split line into words (really, phrases).
+ for k := i; k < j; {
+ ck := &chars[k]
+ s := ck.S
+ end = ck.X + ck.W
+ charSpace := ck.FontSize / 6
+ wordSpace := ck.FontSize * 2 / 3
+ l := k + 1
+ for l < j {
+ // Grow word.
+ cl := &chars[l]
+ if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+charSpace {
+ s += cl.S
+ end = cl.X + cl.W
+ l++
+ continue
+ }
+ // Add space to phrase before next word.
+ if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+wordSpace {
+ s += " " + cl.S
+ end = cl.X + cl.W
+ l++
+ continue
+ }
+ break
+ }
+ f := ck.Font
+ f = strings.TrimSuffix(f, ",Italic")
+ f = strings.TrimSuffix(f, "-Italic")
+ words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end - ck.X, s})
+ k = l
+ }
+ i = j
+ }
+
+ return words
+}
+
+func sameFont(f1, f2 string) bool {
+ f1 = strings.TrimSuffix(f1, ",Italic")
+ f1 = strings.TrimSuffix(f1, "-Italic")
+ f2 = strings.TrimSuffix(f1, ",Italic")
+ f2 = strings.TrimSuffix(f1, "-Italic")
+ return strings.TrimSuffix(f1, ",Italic") == strings.TrimSuffix(f2, ",Italic") || f1 == "Symbol" || f2 == "Symbol" || f1 == "TimesNewRoman" || f2 == "TimesNewRoman"
+}
+
+var jsFix = strings.NewReplacer(
+ `\u003c`, `<`,
+ `\u003e`, `>`,
+ `\u0026`, `&`,
+ `\u0009`, `\t`,
+)
+
+func printTable(name string, table []Inst) {
+ _ = strconv.Atoi
+}
