blob: a725694b4c8371c2c8b8058454afc19db841db14 [file] [log] [blame]
// DO NOT EDIT
// generated by: ppc64map -fmt=decoder pp64.csv
package ppc64asm
const (
_ Op = iota
CNTLZW
CNTLZWCC
B
BA
BL
BLA
BC
BCA
BCL
BCLA
BCLR
BCLRL
BCCTR
BCCTRL
BCTAR
BCTARL
CRAND
CROR
CRNAND
CRXOR
CRNOR
CRANDC
MCRF
CREQV
CRORC
SC
CLRBHRB
MFBHRBE
LBZ
LBZU
LBZX
LBZUX
LHZ
LHZU
LHZX
LHZUX
LHA
LHAU
LHAX
LHAUX
LWZ
LWZU
LWZX
LWZUX
LWA
LWAX
LWAUX
LD
LDU
LDX
LDUX
STB
STBU
STBX
STBUX
STH
STHU
STHX
STHUX
STW
STWU
STWX
STWUX
STD
STDU
STDX
STDUX
LQ
STQ
LHBRX
LWBRX
STHBRX
STWBRX
LDBRX
STDBRX
LMW
STMW
LSWI
LSWX
STSWI
STSWX
LI
ADDI
LIS
ADDIS
ADD
ADDCC
ADDO
ADDOCC
ADDIC
SUBF
SUBFCC
SUBFO
SUBFOCC
ADDICCC
SUBFIC
ADDC
ADDCCC
ADDCO
ADDCOCC
SUBFC
SUBFCCC
SUBFCO
SUBFCOCC
ADDE
ADDECC
ADDEO
ADDEOCC
ADDME
ADDMECC
ADDMEO
ADDMEOCC
SUBFE
SUBFECC
SUBFEO
SUBFEOCC
SUBFME
SUBFMECC
SUBFMEO
SUBFMEOCC
ADDZE
ADDZECC
ADDZEO
ADDZEOCC
SUBFZE
SUBFZECC
SUBFZEO
SUBFZEOCC
NEG
NEGCC
NEGO
NEGOCC
MULLI
MULLW
MULLWCC
MULLWO
MULLWOCC
MULHW
MULHWCC
MULHWU
MULHWUCC
DIVW
DIVWCC
DIVWO
DIVWOCC
DIVWU
DIVWUCC
DIVWUO
DIVWUOCC
DIVWE
DIVWECC
DIVWEO
DIVWEOCC
DIVWEU
DIVWEUCC
DIVWEUO
DIVWEUOCC
MULLD
MULLDCC
MULLDO
MULLDOCC
MULHDU
MULHDUCC
MULHD
MULHDCC
DIVD
DIVDCC
DIVDO
DIVDOCC
DIVDU
DIVDUCC
DIVDUO
DIVDUOCC
DIVDE
DIVDECC
DIVDEO
DIVDEOCC
DIVDEU
DIVDEUCC
DIVDEUO
DIVDEUOCC
MODSD
MODUD
MODSW
MODUW
CMPWI
CMPDI
CMPI
CMPW
CMPD
CMP
CMPLWI
CMPLDI
CMPLI
CMPLW
CMPLD
CMPL
TWI
TW
TDI
ISEL
TD
ANDICC
ANDISCC
ORI
ORIS
XORI
XORIS
AND
ANDCC
XOR
XORCC
NAND
NANDCC
OR
ORCC
NOR
NORCC
ANDC
ANDCCC
EXTSB
EXTSBCC
EQV
EQVCC
ORC
ORCCC
EXTSH
EXTSHCC
CMPB
POPCNTB
POPCNTW
PRTYD
PRTYW
EXTSW
EXTSWCC
CNTLZD
CNTLZDCC
POPCNTD
BPERMD
RLWINM
RLWINMCC
RLWNM
RLWNMCC
RLWIMI
RLWIMICC
RLDICL
RLDICLCC
RLDICR
RLDICRCC
RLDIC
RLDICCC
RLDCL
RLDCLCC
RLDCR
RLDCRCC
RLDIMI
RLDIMICC
SLW
SLWCC
SRW
SRWCC
SRAWI
SRAWICC
SRAW
SRAWCC
SLD
SLDCC
SRD
SRDCC
SRADI
SRADICC
SRAD
SRADCC
CDTBCD
CBCDTD
ADDG6S
MTSPR
MFSPR
MTCRF
MFCR
MFVSRD
MFVSRWZ
MTVSRD
MTVSRWA
MTVSRWZ
MTOCRF
MFOCRF
LFS
LFSU
LFSX
LFSUX
LFD
LFDU
LFDX
LFDUX
LFIWAX
LFIWZX
STFS
STFSU
STFSX
STFSUX
STFD
STFDU
STFDX
STFDUX
STFIWX
LFDP
LFDPX
STFDP
STFDPX
FMR
FMRCC
FABS
FABSCC
FNABS
FNABSCC
FNEG
FNEGCC
FCPSGN
FCPSGNCC
FMRGEW
FMRGOW
FADD
FADDCC
FADDS
FADDSCC
FSUB
FSUBCC
FSUBS
FSUBSCC
FMUL
FMULCC
FMULS
FMULSCC
FDIV
FDIVCC
FDIVS
FDIVSCC
FSQRT
FSQRTCC
FSQRTS
FSQRTSCC
FRE
FRECC
FRES
FRESCC
FRSQRTE
FRSQRTECC
FRSQRTES
FRSQRTESCC
FTDIV
FTSQRT
FMADD
FMADDCC
FMADDS
FMADDSCC
FMSUB
FMSUBCC
FMSUBS
FMSUBSCC
FNMADD
FNMADDCC
FNMADDS
FNMADDSCC
FNMSUB
FNMSUBCC
FNMSUBS
FNMSUBSCC
FRSP
FRSPCC
FCTID
FCTIDCC
FCTIDZ
FCTIDZCC
FCTIDU
FCTIDUCC
FCTIDUZ
FCTIDUZCC
FCTIW
FCTIWCC
FCTIWZ
FCTIWZCC
FCTIWU
FCTIWUCC
FCTIWUZ
FCTIWUZCC
FCFID
FCFIDCC
FCFIDU
FCFIDUCC
FCFIDS
FCFIDSCC
FCFIDUS
FCFIDUSCC
FRIN
FRINCC
FRIZ
FRIZCC
FRIP
FRIPCC
FRIM
FRIMCC
FCMPU
FCMPO
FSEL
FSELCC
MFFS
MFFSCC
MCRFS
MTFSFI
MTFSFICC
MTFSF
MTFSFCC
MTFSB0
MTFSB0CC
MTFSB1
MTFSB1CC
LVEBX
LVEHX
LVEWX
LVX
LVXL
STVEBX
STVEHX
STVEWX
STVX
STVXL
LVSL
LVSR
VPKPX
VPKSDSS
VPKSDUS
VPKSHSS
VPKSHUS
VPKSWSS
VPKSWUS
VPKUDUM
VPKUDUS
VPKUHUM
VPKUHUS
VPKUWUM
VPKUWUS
VUPKHPX
VUPKLPX
VUPKHSB
VUPKHSH
VUPKHSW
VUPKLSB
VUPKLSH
VUPKLSW
VMRGHB
VMRGHH
VMRGLB
VMRGLH
VMRGHW
VMRGLW
VMRGEW
VMRGOW
VSPLTB
VSPLTH
VSPLTW
VSPLTISB
VSPLTISH
VSPLTISW
VPERM
VPERMR
VSEL
VSL
VSLDOI
VSLO
VSR
VSRO
VADDCUW
VADDSBS
VADDSHS
VADDSWS
VADDUBM
VADDUDM
VADDUHM
VADDUWM
VADDUBS
VADDUHS
VADDUWS
VADDUQM
VADDEUQM
VADDCUQ
VADDECUQ
VSUBCUW
VSUBSBS
VSUBSHS
VSUBSWS
VSUBUBM
VSUBUDM
VSUBUHM
VSUBUWM
VSUBUBS
VSUBUHS
VSUBUWS
VSUBUQM
VSUBEUQM
VSUBCUQ
VSUBECUQ
VMULESB
VMULEUB
VMULOSB
VMULOUB
VMULESH
VMULEUH
VMULOSH
VMULOUH
VMULESW
VMULEUW
VMULOSW
VMULOUW
VMULUWM
VMHADDSHS
VMHRADDSHS
VMLADDUHM
VMSUMUBM
VMSUMMBM
VMSUMSHM
VMSUMSHS
VMSUMUHM
VMSUMUHS
VMSUMUDM
VSUMSWS
VSUM2SWS
VSUM4SBS
VSUM4SHS
VSUM4UBS
VAVGSB
VAVGSH
VAVGSW
VAVGUB
VAVGUW
VAVGUH
VMAXSB
VMAXSD
VMAXUB
VMAXUD
VMAXSH
VMAXSW
VMAXUH
VMAXUW
VMINSB
VMINSD
VMINUB
VMINUD
VMINSH
VMINSW
VMINUH
VMINUW
VCMPEQUB
VCMPEQUBCC
VCMPEQUH
VCMPEQUHCC
VCMPEQUW
VCMPEQUWCC
VCMPEQUD
VCMPEQUDCC
VCMPNEB
VCMPNEBCC
VCMPNEZB
VCMPNEZBCC
VCMPNEH
VCMPNEHCC
VCMPNEZH
VCMPNEZHCC
VCMPNEW
VCMPNEWCC
VCMPNEZW
VCMPNEZWCC
VCMPGTSB
VCMPGTSBCC
VCMPGTSD
VCMPGTSDCC
VCMPGTSH
VCMPGTSHCC
VCMPGTSW
VCMPGTSWCC
VCMPGTUB
VCMPGTUBCC
VCMPGTUD
VCMPGTUDCC
VCMPGTUH
VCMPGTUHCC
VCMPGTUW
VCMPGTUWCC
VAND
VANDC
VEQV
VNAND
VORC
VNOR
VOR
VXOR
VRLB
VRLH
VRLW
VRLD
VSLB
VSLH
VSLW
VSLD
VSRB
VSRH
VSRW
VSRD
VSRAB
VSRAH
VSRAW
VSRAD
VADDFP
VSUBFP
VMADDFP
VNMSUBFP
VMAXFP
VMINFP
VCTSXS
VCTUXS
VCFSX
VCFUX
VRFIM
VRFIN
VRFIP
VRFIZ
VCMPBFP
VCMPBFPCC
VCMPEQFP
VCMPEQFPCC
VCMPGEFP
VCMPGEFPCC
VCMPGTFP
VCMPGTFPCC
VEXPTEFP
VLOGEFP
VREFP
VRSQRTEFP
VCIPHER
VCIPHERLAST
VNCIPHER
VNCIPHERLAST
VSBOX
VSHASIGMAD
VSHASIGMAW
VPMSUMB
VPMSUMD
VPMSUMH
VPMSUMW
VPERMXOR
VGBBD
VCLZB
VCLZH
VCLZW
VCLZD
VPOPCNTB
VPOPCNTD
VPOPCNTH
VPOPCNTW
VBPERMQ
VBPERMD
BCDADDCC
BCDSUBCC
MTVSCR
MFVSCR
DADD
DADDCC
DSUB
DSUBCC
DMUL
DMULCC
DDIV
DDIVCC
DCMPU
DCMPO
DTSTDC
DTSTDG
DTSTEX
DTSTSF
DQUAI
DQUAICC
DQUA
DQUACC
DRRND
DRRNDCC
DRINTX
DRINTXCC
DRINTN
DRINTNCC
DCTDP
DCTDPCC
DCTQPQ
DCTQPQCC
DRSP
DRSPCC
DRDPQ
DRDPQCC
DCFFIX
DCFFIXCC
DCFFIXQ
DCFFIXQCC
DCTFIX
DCTFIXCC
DDEDPD
DDEDPDCC
DENBCD
DENBCDCC
DXEX
DXEXCC
DIEX
DIEXCC
DSCLI
DSCLICC
DSCRI
DSCRICC
LXSDX
LXSIWAX
LXSIWZX
LXSSPX
LXVD2X
LXVDSX
LXVW4X
LXVH8X
LXVB16X
LXV
LXVL
LXVLL
LXVX
STXSDX
STXSIWX
STXSSPX
STXVD2X
STXVW4X
STXVH8X
STXVB16X
STXV
STXVL
STXVLL
STXVX
XSABSDP
XSADDDP
XSADDSP
XSCMPODP
XSCMPUDP
XSCPSGNDP
XSCVDPSP
XSCVDPSPN
XSCVDPSXDS
XSCVDPSXWS
XSCVDPUXDS
XSCVDPUXWS
XSCVSPDP
XSCVSPDPN
XSCVSXDDP
XSCVSXDSP
XSCVUXDDP
XSCVUXDSP
XSDIVDP
XSDIVSP
XSMADDADP
XSMADDASP
XSMAXDP
XSMINDP
XSMSUBADP
XSMSUBASP
XSMULDP
XSMULSP
XSNABSDP
XSNEGDP
XSNMADDADP
XSNMADDASP
XSNMSUBADP
XSNMSUBASP
XSRDPI
XSRDPIC
XSRDPIM
XSRDPIP
XSRDPIZ
XSREDP
XSRESP
XSRSP
XSRSQRTEDP
XSRSQRTESP
XSSQRTDP
XSSQRTSP
XSSUBDP
XSSUBSP
XSTDIVDP
XSTSQRTDP
XVABSDP
XVABSSP
XVADDDP
XVADDSP
XVCMPEQDP
XVCMPEQDPCC
XVCMPEQSP
XVCMPEQSPCC
XVCMPGEDP
XVCMPGEDPCC
XVCMPGESP
XVCMPGESPCC
XVCMPGTDP
XVCMPGTDPCC
XVCMPGTSP
XVCMPGTSPCC
XVCPSGNDP
XVCPSGNSP
XVCVDPSP
XVCVDPSXDS
XVCVDPSXWS
XVCVDPUXDS
XVCVDPUXWS
XVCVSPDP
XVCVSPSXDS
XVCVSPSXWS
XVCVSPUXDS
XVCVSPUXWS
XVCVSXDDP
XVCVSXDSP
XVCVSXWDP
XVCVSXWSP
XVCVUXDDP
XVCVUXDSP
XVCVUXWDP
XVCVUXWSP
XVDIVDP
XVDIVSP
XVMADDADP
XVMADDASP
XVMAXDP
XVMAXSP
XVMINDP
XVMINSP
XVMSUBADP
XVMSUBASP
XVMULDP
XVMULSP
XVNABSDP
XVNABSSP
XVNEGDP
XVNEGSP
XVNMADDADP
XVNMADDASP
XVNMSUBADP
XVNMSUBASP
XVRDPI
XVRDPIC
XVRDPIM
XVRDPIP
XVRDPIZ
XVREDP
XVRESP
XVRSPI
XVRSPIC
XVRSPIM
XVRSPIP
XVRSPIZ
XVRSQRTEDP
XVRSQRTESP
XVSQRTDP
XVSQRTSP
XVSUBDP
XVSUBSP
XVTDIVDP
XVTDIVSP
XVTSQRTDP
XVTSQRTSP
XXLAND
XXLANDC
XXLEQV
XXLNAND
XXLORC
XXLNOR
XXLOR
XXLXOR
XXMRGHW
XXMRGLW
XXPERMDI
XXPERM
XXSEL
XXSLDWI
XXSPLTW
XXBRD
XXBRW
XXBRH
ICBI
ICBT
DCBT
DCBTST
DCBZ
DCBST
DCBF
ISYNC
LBARX
LHARX
LWARX
STBCXCC
STHCXCC
STWCXCC
LDARX
STDCXCC
LQARX
STQCXCC
SYNC
EIEIO
WAIT
MFTB
RFEBB
RFID
HRFID
LBZCIX
LWZCIX
LHZCIX
LDCIX
STBCIX
STWCIX
STHCIX
STDCIX
MTMSR
MTMSRD
MFMSR
SLBIE
SLBIA
SLBMTE
SLBMFEV
SLBMFEE
SLBFEECC
TLBIE
TLBIEL
TLBSYNC
MSGSND
MSGCLR
MSGSNDP
MSGCLRP
ADDEX
DARN
MADDHD
MADDHDU
MADDLD
CMPRB
CMPEQB
EXTSWSLI
EXTSWSLICC
MFVSRLD
MTVSRDD
MTVSRWS
MCRXRX
COPY
PASTECC
BRD
BRH
BRW
CFUGED
CNTLZDM
CNTTZDM
DCFFIXQQ
DCTFIXQQ
LXVKQ
LXVP
LXVPX
LXVRBX
LXVRDX
LXVRHX
LXVRWX
MTVSRBM
MTVSRBMI
MTVSRDM
MTVSRHM
MTVSRQM
MTVSRWM
PDEPD
PEXTD
SETBC
SETBCR
SETNBC
SETNBCR
STXVP
STXVPX
STXVRBX
STXVRDX
STXVRHX
STXVRWX
VCFUGED
VCLRLB
VCLRRB
VCLZDM
VCMPEQUQ
VCMPEQUQCC
VCMPGTSQ
VCMPGTSQCC
VCMPGTUQ
VCMPGTUQCC
VCMPSQ
VCMPUQ
VCNTMBB
VCNTMBD
VCNTMBH
VCNTMBW
VCTZDM
VDIVESD
VDIVESQ
VDIVESW
VDIVEUD
VDIVEUQ
VDIVEUW
VDIVSD
VDIVSQ
VDIVSW
VDIVUD
VDIVUQ
VDIVUW
VEXPANDBM
VEXPANDDM
VEXPANDHM
VEXPANDQM
VEXPANDWM
VEXTDDVLX
VEXTDDVRX
VEXTDUBVLX
VEXTDUBVRX
VEXTDUHVLX
VEXTDUHVRX
VEXTDUWVLX
VEXTDUWVRX
VEXTRACTBM
VEXTRACTDM
VEXTRACTHM
VEXTRACTQM
VEXTRACTWM
VEXTSD2Q
VGNB
VINSBLX
VINSBRX
VINSBVLX
VINSBVRX
VINSD
VINSDLX
VINSDRX
VINSHLX
VINSHRX
VINSHVLX
VINSHVRX
VINSW
VINSWLX
VINSWRX
VINSWVLX
VINSWVRX
VMODSD
VMODSQ
VMODSW
VMODUD
VMODUQ
VMODUW
VMSUMCUD
VMULESD
VMULEUD
VMULHSD
VMULHSW
VMULHUD
VMULHUW
VMULLD
VMULOSD
VMULOUD
VPDEPD
VPEXTD
VRLQ
VRLQMI
VRLQNM
VSLDBI
VSLQ
VSRAQ
VSRDBI
VSRQ
VSTRIBL
VSTRIBLCC
VSTRIBR
VSTRIBRCC
VSTRIHL
VSTRIHLCC
VSTRIHR
VSTRIHRCC
XSCMPEQQP
XSCMPGEQP
XSCMPGTQP
XSCVQPSQZ
XSCVQPUQZ
XSCVSQQP
XSCVUQQP
XSMAXCQP
XSMINCQP
XVBF16GER2
XVBF16GER2NN
XVBF16GER2NP
XVBF16GER2PN
XVBF16GER2PP
XVCVBF16SPN
XVCVSPBF16
XVF16GER2
XVF16GER2NN
XVF16GER2NP
XVF16GER2PN
XVF16GER2PP
XVF32GER
XVF32GERNN
XVF32GERNP
XVF32GERPN
XVF32GERPP
XVF64GER
XVF64GERNN
XVF64GERNP
XVF64GERPN
XVF64GERPP
XVI16GER2
XVI16GER2PP
XVI16GER2S
XVI16GER2SPP
XVI4GER8
XVI4GER8PP
XVI8GER4
XVI8GER4PP
XVI8GER4SPP
XVTLSBB
XXGENPCVBM
XXGENPCVDM
XXGENPCVHM
XXGENPCVWM
XXMFACC
XXMTACC
XXSETACCZ
MSGCLRU
MSGSNDU
URFID
MFFSCDRN
MFFSCDRNI
MFFSCE
MFFSCRN
MFFSCRNI
MFFSL
SLBIAG
ADDPCIS
BCDCFNCC
BCDCFSQCC
BCDCFZCC
BCDCPSGNCC
BCDCTNCC
BCDCTSQCC
BCDCTZCC
BCDSCC
BCDSETSGNCC
BCDSRCC
BCDTRUNCCC
BCDUSCC
BCDUTRUNCCC
CNTTZD
CNTTZDCC
CNTTZW
CNTTZWCC
CPABORT
DTSTSFI
DTSTSFIQ
LDAT
LWAT
LXSD
LXSIBZX
LXSIHZX
LXSSP
LXVWSX
MSGSYNC
SETB
SLBIEG
SLBSYNC
STDAT
STOP
STWAT
STXSD
STXSIBX
STXSIHX
STXSSP
VABSDUB
VABSDUH
VABSDUW
VCLZLSBB
VCTZB
VCTZD
VCTZH
VCTZLSBB
VCTZW
VEXTRACTD
VEXTRACTUB
VEXTRACTUH
VEXTRACTUW
VEXTSB2D
VEXTSB2W
VEXTSH2D
VEXTSH2W
VEXTSW2D
VEXTUBLX
VEXTUBRX
VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX
VINSERTB
VINSERTD
VINSERTH
VINSERTW
VMUL10CUQ
VMUL10ECUQ
VMUL10EUQ
VMUL10UQ
VNEGD
VNEGW
VPRTYBD
VPRTYBQ
VPRTYBW
VRLDMI
VRLDNM
VRLWMI
VRLWNM
VSLV
VSRV
XSABSQP
XSADDQP
XSADDQPO
XSCMPEQDP
XSCMPEXPDP
XSCMPEXPQP
XSCMPGEDP
XSCMPGTDP
XSCMPOQP
XSCMPUQP
XSCPSGNQP
XSCVDPHP
XSCVDPQP
XSCVHPDP
XSCVQPDP
XSCVQPDPO
XSCVQPSDZ
XSCVQPSWZ
XSCVQPUDZ
XSCVQPUWZ
XSCVSDQP
XSCVUDQP
XSDIVQP
XSDIVQPO
XSIEXPDP
XSIEXPQP
XSMADDQP
XSMADDQPO
XSMAXCDP
XSMAXJDP
XSMINCDP
XSMINJDP
XSMSUBQP
XSMSUBQPO
XSMULQP
XSMULQPO
XSNABSQP
XSNEGQP
XSNMADDQP
XSNMADDQPO
XSNMSUBQP
XSNMSUBQPO
XSRQPI
XSRQPIX
XSRQPXP
XSSQRTQP
XSSQRTQPO
XSSUBQP
XSSUBQPO
XSTSTDCDP
XSTSTDCQP
XSTSTDCSP
XSXEXPDP
XSXEXPQP
XSXSIGDP
XSXSIGQP
XVCVHPSP
XVCVSPHP
XVIEXPDP
XVIEXPSP
XVTSTDCDP
XVTSTDCSP
XVXEXPDP
XVXEXPSP
XVXSIGDP
XVXSIGSP
XXBRQ
XXEXTRACTUW
XXINSERTW
XXPERMR
XXSPLTIB
XSMADDMSP
XSMSUBMSP
XSNMADDMSP
XSNMSUBMSP
XSMADDMDP
XSMSUBMDP
XSNMADDMDP
XSNMSUBMDP
XVMADDMDP
XVMADDMSP
XVMSUBMDP
XVMSUBMSP
XVNMADDMDP
XVNMADDMSP
XVNMSUBMDP
XVNMSUBMSP
DADDQ
DADDQCC
DCMPOQ
DCMPUQ
DCTFIXQ
DCTFIXQCC
DDEDPDQ
DDEDPDQCC
DDIVQ
DDIVQCC
DENBCDQ
DENBCDQCC
DIEXQCC
DIEXQ
DMULQ
DMULQCC
DQUAIQ
DQUAIQCC
DQUAQ
DQUAQCC
DRINTNQ
DRINTNQCC
DRINTXQ
DRINTXQCC
DRRNDQ
DRRNDQCC
DSCLIQ
DSCLIQCC
DSCRIQ
DSCRIQCC
DSUBQ
DSUBQCC
DTSTDCQ
DTSTDGQ
DTSTEXQ
DTSTSFQ
DXEXQ
DXEXQCC
RFSCV
SCV
)
var opstr = [...]string{
CNTLZW: "cntlzw",
CNTLZWCC: "cntlzw.",
B: "b",
BA: "ba",
BL: "bl",
BLA: "bla",
BC: "bc",
BCA: "bca",
BCL: "bcl",
BCLA: "bcla",
BCLR: "bclr",
BCLRL: "bclrl",
BCCTR: "bcctr",
BCCTRL: "bcctrl",
BCTAR: "bctar",
BCTARL: "bctarl",
CRAND: "crand",
CROR: "cror",
CRNAND: "crnand",
CRXOR: "crxor",
CRNOR: "crnor",
CRANDC: "crandc",
MCRF: "mcrf",
CREQV: "creqv",
CRORC: "crorc",
SC: "sc",
CLRBHRB: "clrbhrb",
MFBHRBE: "mfbhrbe",
LBZ: "lbz",
LBZU: "lbzu",
LBZX: "lbzx",
LBZUX: "lbzux",
LHZ: "lhz",
LHZU: "lhzu",
LHZX: "lhzx",
LHZUX: "lhzux",
LHA: "lha",
LHAU: "lhau",
LHAX: "lhax",
LHAUX: "lhaux",
LWZ: "lwz",
LWZU: "lwzu",
LWZX: "lwzx",
LWZUX: "lwzux",
LWA: "lwa",
LWAX: "lwax",
LWAUX: "lwaux",
LD: "ld",
LDU: "ldu",
LDX: "ldx",
LDUX: "ldux",
STB: "stb",
STBU: "stbu",
STBX: "stbx",
STBUX: "stbux",
STH: "sth",
STHU: "sthu",
STHX: "sthx",
STHUX: "sthux",
STW: "stw",
STWU: "stwu",
STWX: "stwx",
STWUX: "stwux",
STD: "std",
STDU: "stdu",
STDX: "stdx",
STDUX: "stdux",
LQ: "lq",
STQ: "stq",
LHBRX: "lhbrx",
LWBRX: "lwbrx",
STHBRX: "sthbrx",
STWBRX: "stwbrx",
LDBRX: "ldbrx",
STDBRX: "stdbrx",
LMW: "lmw",
STMW: "stmw",
LSWI: "lswi",
LSWX: "lswx",
STSWI: "stswi",
STSWX: "stswx",
LI: "li",
ADDI: "addi",
LIS: "lis",
ADDIS: "addis",
ADD: "add",
ADDCC: "add.",
ADDO: "addo",
ADDOCC: "addo.",
ADDIC: "addic",
SUBF: "subf",
SUBFCC: "subf.",
SUBFO: "subfo",
SUBFOCC: "subfo.",
ADDICCC: "addic.",
SUBFIC: "subfic",
ADDC: "addc",
ADDCCC: "addc.",
ADDCO: "addco",
ADDCOCC: "addco.",
SUBFC: "subfc",
SUBFCCC: "subfc.",
SUBFCO: "subfco",
SUBFCOCC: "subfco.",
ADDE: "adde",
ADDECC: "adde.",
ADDEO: "addeo",
ADDEOCC: "addeo.",
ADDME: "addme",
ADDMECC: "addme.",
ADDMEO: "addmeo",
ADDMEOCC: "addmeo.",
SUBFE: "subfe",
SUBFECC: "subfe.",
SUBFEO: "subfeo",
SUBFEOCC: "subfeo.",
SUBFME: "subfme",
SUBFMECC: "subfme.",
SUBFMEO: "subfmeo",
SUBFMEOCC: "subfmeo.",
ADDZE: "addze",
ADDZECC: "addze.",
ADDZEO: "addzeo",
ADDZEOCC: "addzeo.",
SUBFZE: "subfze",
SUBFZECC: "subfze.",
SUBFZEO: "subfzeo",
SUBFZEOCC: "subfzeo.",
NEG: "neg",
NEGCC: "neg.",
NEGO: "nego",
NEGOCC: "nego.",
MULLI: "mulli",
MULLW: "mullw",
MULLWCC: "mullw.",
MULLWO: "mullwo",
MULLWOCC: "mullwo.",
MULHW: "mulhw",
MULHWCC: "mulhw.",
MULHWU: "mulhwu",
MULHWUCC: "mulhwu.",
DIVW: "divw",
DIVWCC: "divw.",
DIVWO: "divwo",
DIVWOCC: "divwo.",
DIVWU: "divwu",
DIVWUCC: "divwu.",
DIVWUO: "divwuo",
DIVWUOCC: "divwuo.",
DIVWE: "divwe",
DIVWECC: "divwe.",
DIVWEO: "divweo",
DIVWEOCC: "divweo.",
DIVWEU: "divweu",
DIVWEUCC: "divweu.",
DIVWEUO: "divweuo",
DIVWEUOCC: "divweuo.",
MULLD: "mulld",
MULLDCC: "mulld.",
MULLDO: "mulldo",
MULLDOCC: "mulldo.",
MULHDU: "mulhdu",
MULHDUCC: "mulhdu.",
MULHD: "mulhd",
MULHDCC: "mulhd.",
DIVD: "divd",
DIVDCC: "divd.",
DIVDO: "divdo",
DIVDOCC: "divdo.",
DIVDU: "divdu",
DIVDUCC: "divdu.",
DIVDUO: "divduo",
DIVDUOCC: "divduo.",
DIVDE: "divde",
DIVDECC: "divde.",
DIVDEO: "divdeo",
DIVDEOCC: "divdeo.",
DIVDEU: "divdeu",
DIVDEUCC: "divdeu.",
DIVDEUO: "divdeuo",
DIVDEUOCC: "divdeuo.",
MODSD: "modsd",
MODUD: "modud",
MODSW: "modsw",
MODUW: "moduw",
CMPWI: "cmpwi",
CMPDI: "cmpdi",
CMPI: "cmpi",
CMPW: "cmpw",
CMPD: "cmpd",
CMP: "cmp",
CMPLWI: "cmplwi",
CMPLDI: "cmpldi",
CMPLI: "cmpli",
CMPLW: "cmplw",
CMPLD: "cmpld",
CMPL: "cmpl",
TWI: "twi",
TW: "tw",
TDI: "tdi",
ISEL: "isel",
TD: "td",
ANDICC: "andi.",
ANDISCC: "andis.",
ORI: "ori",
ORIS: "oris",
XORI: "xori",
XORIS: "xoris",
AND: "and",
ANDCC: "and.",
XOR: "xor",
XORCC: "xor.",
NAND: "nand",
NANDCC: "nand.",
OR: "or",
ORCC: "or.",
NOR: "nor",
NORCC: "nor.",
ANDC: "andc",
ANDCCC: "andc.",
EXTSB: "extsb",
EXTSBCC: "extsb.",
EQV: "eqv",
EQVCC: "eqv.",
ORC: "orc",
ORCCC: "orc.",
EXTSH: "extsh",
EXTSHCC: "extsh.",
CMPB: "cmpb",
POPCNTB: "popcntb",
POPCNTW: "popcntw",
PRTYD: "prtyd",
PRTYW: "prtyw",
EXTSW: "extsw",
EXTSWCC: "extsw.",
CNTLZD: "cntlzd",
CNTLZDCC: "cntlzd.",
POPCNTD: "popcntd",
BPERMD: "bpermd",
RLWINM: "rlwinm",
RLWINMCC: "rlwinm.",
RLWNM: "rlwnm",
RLWNMCC: "rlwnm.",
RLWIMI: "rlwimi",
RLWIMICC: "rlwimi.",
RLDICL: "rldicl",
RLDICLCC: "rldicl.",
RLDICR: "rldicr",
RLDICRCC: "rldicr.",
RLDIC: "rldic",
RLDICCC: "rldic.",
RLDCL: "rldcl",
RLDCLCC: "rldcl.",
RLDCR: "rldcr",
RLDCRCC: "rldcr.",
RLDIMI: "rldimi",
RLDIMICC: "rldimi.",
SLW: "slw",
SLWCC: "slw.",
SRW: "srw",
SRWCC: "srw.",
SRAWI: "srawi",
SRAWICC: "srawi.",
SRAW: "sraw",
SRAWCC: "sraw.",
SLD: "sld",
SLDCC: "sld.",
SRD: "srd",
SRDCC: "srd.",
SRADI: "sradi",
SRADICC: "sradi.",
SRAD: "srad",
SRADCC: "srad.",
CDTBCD: "cdtbcd",
CBCDTD: "cbcdtd",
ADDG6S: "addg6s",
MTSPR: "mtspr",
MFSPR: "mfspr",
MTCRF: "mtcrf",
MFCR: "mfcr",
MFVSRD: "mfvsrd",
MFVSRWZ: "mfvsrwz",
MTVSRD: "mtvsrd",
MTVSRWA: "mtvsrwa",
MTVSRWZ: "mtvsrwz",
MTOCRF: "mtocrf",
MFOCRF: "mfocrf",
LFS: "lfs",
LFSU: "lfsu",
LFSX: "lfsx",
LFSUX: "lfsux",
LFD: "lfd",
LFDU: "lfdu",
LFDX: "lfdx",
LFDUX: "lfdux",
LFIWAX: "lfiwax",
LFIWZX: "lfiwzx",
STFS: "stfs",
STFSU: "stfsu",
STFSX: "stfsx",
STFSUX: "stfsux",
STFD: "stfd",
STFDU: "stfdu",
STFDX: "stfdx",
STFDUX: "stfdux",
STFIWX: "stfiwx",
LFDP: "lfdp",
LFDPX: "lfdpx",
STFDP: "stfdp",
STFDPX: "stfdpx",
FMR: "fmr",
FMRCC: "fmr.",
FABS: "fabs",
FABSCC: "fabs.",
FNABS: "fnabs",
FNABSCC: "fnabs.",
FNEG: "fneg",
FNEGCC: "fneg.",
FCPSGN: "fcpsgn",
FCPSGNCC: "fcpsgn.",
FMRGEW: "fmrgew",
FMRGOW: "fmrgow",
FADD: "fadd",
FADDCC: "fadd.",
FADDS: "fadds",
FADDSCC: "fadds.",
FSUB: "fsub",
FSUBCC: "fsub.",
FSUBS: "fsubs",
FSUBSCC: "fsubs.",
FMUL: "fmul",
FMULCC: "fmul.",
FMULS: "fmuls",
FMULSCC: "fmuls.",
FDIV: "fdiv",
FDIVCC: "fdiv.",
FDIVS: "fdivs",
FDIVSCC: "fdivs.",
FSQRT: "fsqrt",
FSQRTCC: "fsqrt.",
FSQRTS: "fsqrts",
FSQRTSCC: "fsqrts.",
FRE: "fre",
FRECC: "fre.",
FRES: "fres",
FRESCC: "fres.",
FRSQRTE: "frsqrte",
FRSQRTECC: "frsqrte.",
FRSQRTES: "frsqrtes",
FRSQRTESCC: "frsqrtes.",
FTDIV: "ftdiv",
FTSQRT: "ftsqrt",
FMADD: "fmadd",
FMADDCC: "fmadd.",
FMADDS: "fmadds",
FMADDSCC: "fmadds.",
FMSUB: "fmsub",
FMSUBCC: "fmsub.",
FMSUBS: "fmsubs",
FMSUBSCC: "fmsubs.",
FNMADD: "fnmadd",
FNMADDCC: "fnmadd.",
FNMADDS: "fnmadds",
FNMADDSCC: "fnmadds.",
FNMSUB: "fnmsub",
FNMSUBCC: "fnmsub.",
FNMSUBS: "fnmsubs",
FNMSUBSCC: "fnmsubs.",
FRSP: "frsp",
FRSPCC: "frsp.",
FCTID: "fctid",
FCTIDCC: "fctid.",
FCTIDZ: "fctidz",
FCTIDZCC: "fctidz.",
FCTIDU: "fctidu",
FCTIDUCC: "fctidu.",
FCTIDUZ: "fctiduz",
FCTIDUZCC: "fctiduz.",
FCTIW: "fctiw",
FCTIWCC: "fctiw.",
FCTIWZ: "fctiwz",
FCTIWZCC: "fctiwz.",
FCTIWU: "fctiwu",
FCTIWUCC: "fctiwu.",
FCTIWUZ: "fctiwuz",
FCTIWUZCC: "fctiwuz.",
FCFID: "fcfid",
FCFIDCC: "fcfid.",
FCFIDU: "fcfidu",
FCFIDUCC: "fcfidu.",
FCFIDS: "fcfids",
FCFIDSCC: "fcfids.",
FCFIDUS: "fcfidus",
FCFIDUSCC: "fcfidus.",
FRIN: "frin",
FRINCC: "frin.",
FRIZ: "friz",
FRIZCC: "friz.",
FRIP: "frip",
FRIPCC: "frip.",
FRIM: "frim",
FRIMCC: "frim.",
FCMPU: "fcmpu",
FCMPO: "fcmpo",
FSEL: "fsel",
FSELCC: "fsel.",
MFFS: "mffs",
MFFSCC: "mffs.",
MCRFS: "mcrfs",
MTFSFI: "mtfsfi",
MTFSFICC: "mtfsfi.",
MTFSF: "mtfsf",
MTFSFCC: "mtfsf.",
MTFSB0: "mtfsb0",
MTFSB0CC: "mtfsb0.",
MTFSB1: "mtfsb1",
MTFSB1CC: "mtfsb1.",
LVEBX: "lvebx",
LVEHX: "lvehx",
LVEWX: "lvewx",
LVX: "lvx",
LVXL: "lvxl",
STVEBX: "stvebx",
STVEHX: "stvehx",
STVEWX: "stvewx",
STVX: "stvx",
STVXL: "stvxl",
LVSL: "lvsl",
LVSR: "lvsr",
VPKPX: "vpkpx",
VPKSDSS: "vpksdss",
VPKSDUS: "vpksdus",
VPKSHSS: "vpkshss",
VPKSHUS: "vpkshus",
VPKSWSS: "vpkswss",
VPKSWUS: "vpkswus",
VPKUDUM: "vpkudum",
VPKUDUS: "vpkudus",
VPKUHUM: "vpkuhum",
VPKUHUS: "vpkuhus",
VPKUWUM: "vpkuwum",
VPKUWUS: "vpkuwus",
VUPKHPX: "vupkhpx",
VUPKLPX: "vupklpx",
VUPKHSB: "vupkhsb",
VUPKHSH: "vupkhsh",
VUPKHSW: "vupkhsw",
VUPKLSB: "vupklsb",
VUPKLSH: "vupklsh",
VUPKLSW: "vupklsw",
VMRGHB: "vmrghb",
VMRGHH: "vmrghh",
VMRGLB: "vmrglb",
VMRGLH: "vmrglh",
VMRGHW: "vmrghw",
VMRGLW: "vmrglw",
VMRGEW: "vmrgew",
VMRGOW: "vmrgow",
VSPLTB: "vspltb",
VSPLTH: "vsplth",
VSPLTW: "vspltw",
VSPLTISB: "vspltisb",
VSPLTISH: "vspltish",
VSPLTISW: "vspltisw",
VPERM: "vperm",
VPERMR: "vpermr",
VSEL: "vsel",
VSL: "vsl",
VSLDOI: "vsldoi",
VSLO: "vslo",
VSR: "vsr",
VSRO: "vsro",
VADDCUW: "vaddcuw",
VADDSBS: "vaddsbs",
VADDSHS: "vaddshs",
VADDSWS: "vaddsws",
VADDUBM: "vaddubm",
VADDUDM: "vaddudm",
VADDUHM: "vadduhm",
VADDUWM: "vadduwm",
VADDUBS: "vaddubs",
VADDUHS: "vadduhs",
VADDUWS: "vadduws",
VADDUQM: "vadduqm",
VADDEUQM: "vaddeuqm",
VADDCUQ: "vaddcuq",
VADDECUQ: "vaddecuq",
VSUBCUW: "vsubcuw",
VSUBSBS: "vsubsbs",
VSUBSHS: "vsubshs",
VSUBSWS: "vsubsws",
VSUBUBM: "vsububm",
VSUBUDM: "vsubudm",
VSUBUHM: "vsubuhm",
VSUBUWM: "vsubuwm",
VSUBUBS: "vsububs",
VSUBUHS: "vsubuhs",
VSUBUWS: "vsubuws",
VSUBUQM: "vsubuqm",
VSUBEUQM: "vsubeuqm",
VSUBCUQ: "vsubcuq",
VSUBECUQ: "vsubecuq",
VMULESB: "vmulesb",
VMULEUB: "vmuleub",
VMULOSB: "vmulosb",
VMULOUB: "vmuloub",
VMULESH: "vmulesh",
VMULEUH: "vmuleuh",
VMULOSH: "vmulosh",
VMULOUH: "vmulouh",
VMULESW: "vmulesw",
VMULEUW: "vmuleuw",
VMULOSW: "vmulosw",
VMULOUW: "vmulouw",
VMULUWM: "vmuluwm",
VMHADDSHS: "vmhaddshs",
VMHRADDSHS: "vmhraddshs",
VMLADDUHM: "vmladduhm",
VMSUMUBM: "vmsumubm",
VMSUMMBM: "vmsummbm",
VMSUMSHM: "vmsumshm",
VMSUMSHS: "vmsumshs",
VMSUMUHM: "vmsumuhm",
VMSUMUHS: "vmsumuhs",
VMSUMUDM: "vmsumudm",
VSUMSWS: "vsumsws",
VSUM2SWS: "vsum2sws",
VSUM4SBS: "vsum4sbs",
VSUM4SHS: "vsum4shs",
VSUM4UBS: "vsum4ubs",
VAVGSB: "vavgsb",
VAVGSH: "vavgsh",
VAVGSW: "vavgsw",
VAVGUB: "vavgub",
VAVGUW: "vavguw",
VAVGUH: "vavguh",
VMAXSB: "vmaxsb",
VMAXSD: "vmaxsd",
VMAXUB: "vmaxub",
VMAXUD: "vmaxud",
VMAXSH: "vmaxsh",
VMAXSW: "vmaxsw",
VMAXUH: "vmaxuh",
VMAXUW: "vmaxuw",
VMINSB: "vminsb",
VMINSD: "vminsd",
VMINUB: "vminub",
VMINUD: "vminud",
VMINSH: "vminsh",
VMINSW: "vminsw",
VMINUH: "vminuh",
VMINUW: "vminuw",
VCMPEQUB: "vcmpequb",
VCMPEQUBCC: "vcmpequb.",
VCMPEQUH: "vcmpequh",
VCMPEQUHCC: "vcmpequh.",
VCMPEQUW: "vcmpequw",
VCMPEQUWCC: "vcmpequw.",
VCMPEQUD: "vcmpequd",
VCMPEQUDCC: "vcmpequd.",
VCMPNEB: "vcmpneb",
VCMPNEBCC: "vcmpneb.",
VCMPNEZB: "vcmpnezb",
VCMPNEZBCC: "vcmpnezb.",
VCMPNEH: "vcmpneh",
VCMPNEHCC: "vcmpneh.",
VCMPNEZH: "vcmpnezh",
VCMPNEZHCC: "vcmpnezh.",
VCMPNEW: "vcmpnew",
VCMPNEWCC: "vcmpnew.",
VCMPNEZW: "vcmpnezw",
VCMPNEZWCC: "vcmpnezw.",
VCMPGTSB: "vcmpgtsb",
VCMPGTSBCC: "vcmpgtsb.",
VCMPGTSD: "vcmpgtsd",
VCMPGTSDCC: "vcmpgtsd.",
VCMPGTSH: "vcmpgtsh",
VCMPGTSHCC: "vcmpgtsh.",
VCMPGTSW: "vcmpgtsw",
VCMPGTSWCC: "vcmpgtsw.",
VCMPGTUB: "vcmpgtub",
VCMPGTUBCC: "vcmpgtub.",
VCMPGTUD: "vcmpgtud",
VCMPGTUDCC: "vcmpgtud.",
VCMPGTUH: "vcmpgtuh",
VCMPGTUHCC: "vcmpgtuh.",
VCMPGTUW: "vcmpgtuw",
VCMPGTUWCC: "vcmpgtuw.",
VAND: "vand",
VANDC: "vandc",
VEQV: "veqv",
VNAND: "vnand",
VORC: "vorc",
VNOR: "vnor",
VOR: "vor",
VXOR: "vxor",
VRLB: "vrlb",
VRLH: "vrlh",
VRLW: "vrlw",
VRLD: "vrld",
VSLB: "vslb",
VSLH: "vslh",
VSLW: "vslw",
VSLD: "vsld",
VSRB: "vsrb",
VSRH: "vsrh",
VSRW: "vsrw",
VSRD: "vsrd",
VSRAB: "vsrab",
VSRAH: "vsrah",
VSRAW: "vsraw",
VSRAD: "vsrad",
VADDFP: "vaddfp",
VSUBFP: "vsubfp",
VMADDFP: "vmaddfp",
VNMSUBFP: "vnmsubfp",
VMAXFP: "vmaxfp",
VMINFP: "vminfp",
VCTSXS: "vctsxs",
VCTUXS: "vctuxs",
VCFSX: "vcfsx",
VCFUX: "vcfux",
VRFIM: "vrfim",
VRFIN: "vrfin",
VRFIP: "vrfip",
VRFIZ: "vrfiz",
VCMPBFP: "vcmpbfp",
VCMPBFPCC: "vcmpbfp.",
VCMPEQFP: "vcmpeqfp",
VCMPEQFPCC: "vcmpeqfp.",
VCMPGEFP: "vcmpgefp",
VCMPGEFPCC: "vcmpgefp.",
VCMPGTFP: "vcmpgtfp",
VCMPGTFPCC: "vcmpgtfp.",
VEXPTEFP: "vexptefp",
VLOGEFP: "vlogefp",
VREFP: "vrefp",
VRSQRTEFP: "vrsqrtefp",
VCIPHER: "vcipher",
VCIPHERLAST: "vcipherlast",
VNCIPHER: "vncipher",
VNCIPHERLAST: "vncipherlast",
VSBOX: "vsbox",
VSHASIGMAD: "vshasigmad",
VSHASIGMAW: "vshasigmaw",
VPMSUMB: "vpmsumb",
VPMSUMD: "vpmsumd",
VPMSUMH: "vpmsumh",
VPMSUMW: "vpmsumw",
VPERMXOR: "vpermxor",
VGBBD: "vgbbd",
VCLZB: "vclzb",
VCLZH: "vclzh",
VCLZW: "vclzw",
VCLZD: "vclzd",
VPOPCNTB: "vpopcntb",
VPOPCNTD: "vpopcntd",
VPOPCNTH: "vpopcnth",
VPOPCNTW: "vpopcntw",
VBPERMQ: "vbpermq",
VBPERMD: "vbpermd",
BCDADDCC: "bcdadd.",
BCDSUBCC: "bcdsub.",
MTVSCR: "mtvscr",
MFVSCR: "mfvscr",
DADD: "dadd",
DADDCC: "dadd.",
DSUB: "dsub",
DSUBCC: "dsub.",
DMUL: "dmul",
DMULCC: "dmul.",
DDIV: "ddiv",
DDIVCC: "ddiv.",
DCMPU: "dcmpu",
DCMPO: "dcmpo",
DTSTDC: "dtstdc",
DTSTDG: "dtstdg",
DTSTEX: "dtstex",
DTSTSF: "dtstsf",
DQUAI: "dquai",
DQUAICC: "dquai.",
DQUA: "dqua",
DQUACC: "dqua.",
DRRND: "drrnd",
DRRNDCC: "drrnd.",
DRINTX: "drintx",
DRINTXCC: "drintx.",
DRINTN: "drintn",
DRINTNCC: "drintn.",
DCTDP: "dctdp",
DCTDPCC: "dctdp.",
DCTQPQ: "dctqpq",
DCTQPQCC: "dctqpq.",
DRSP: "drsp",
DRSPCC: "drsp.",
DRDPQ: "drdpq",
DRDPQCC: "drdpq.",
DCFFIX: "dcffix",
DCFFIXCC: "dcffix.",
DCFFIXQ: "dcffixq",
DCFFIXQCC: "dcffixq.",
DCTFIX: "dctfix",
DCTFIXCC: "dctfix.",
DDEDPD: "ddedpd",
DDEDPDCC: "ddedpd.",
DENBCD: "denbcd",
DENBCDCC: "denbcd.",
DXEX: "dxex",
DXEXCC: "dxex.",
DIEX: "diex",
DIEXCC: "diex.",
DSCLI: "dscli",
DSCLICC: "dscli.",
DSCRI: "dscri",
DSCRICC: "dscri.",
LXSDX: "lxsdx",
LXSIWAX: "lxsiwax",
LXSIWZX: "lxsiwzx",
LXSSPX: "lxsspx",
LXVD2X: "lxvd2x",
LXVDSX: "lxvdsx",
LXVW4X: "lxvw4x",
LXVH8X: "lxvh8x",
LXVB16X: "lxvb16x",
LXV: "lxv",
LXVL: "lxvl",
LXVLL: "lxvll",
LXVX: "lxvx",
STXSDX: "stxsdx",
STXSIWX: "stxsiwx",
STXSSPX: "stxsspx",
STXVD2X: "stxvd2x",
STXVW4X: "stxvw4x",
STXVH8X: "stxvh8x",
STXVB16X: "stxvb16x",
STXV: "stxv",
STXVL: "stxvl",
STXVLL: "stxvll",
STXVX: "stxvx",
XSABSDP: "xsabsdp",
XSADDDP: "xsadddp",
XSADDSP: "xsaddsp",
XSCMPODP: "xscmpodp",
XSCMPUDP: "xscmpudp",
XSCPSGNDP: "xscpsgndp",
XSCVDPSP: "xscvdpsp",
XSCVDPSPN: "xscvdpspn",
XSCVDPSXDS: "xscvdpsxds",
XSCVDPSXWS: "xscvdpsxws",
XSCVDPUXDS: "xscvdpuxds",
XSCVDPUXWS: "xscvdpuxws",
XSCVSPDP: "xscvspdp",
XSCVSPDPN: "xscvspdpn",
XSCVSXDDP: "xscvsxddp",
XSCVSXDSP: "xscvsxdsp",
XSCVUXDDP: "xscvuxddp",
XSCVUXDSP: "xscvuxdsp",
XSDIVDP: "xsdivdp",
XSDIVSP: "xsdivsp",
XSMADDADP: "xsmaddadp",
XSMADDASP: "xsmaddasp",
XSMAXDP: "xsmaxdp",
XSMINDP: "xsmindp",
XSMSUBADP: "xsmsubadp",
XSMSUBASP: "xsmsubasp",
XSMULDP: "xsmuldp",
XSMULSP: "xsmulsp",
XSNABSDP: "xsnabsdp",
XSNEGDP: "xsnegdp",
XSNMADDADP: "xsnmaddadp",
XSNMADDASP: "xsnmaddasp",
XSNMSUBADP: "xsnmsubadp",
XSNMSUBASP: "xsnmsubasp",
XSRDPI: "xsrdpi",
XSRDPIC: "xsrdpic",
XSRDPIM: "xsrdpim",
XSRDPIP: "xsrdpip",
XSRDPIZ: "xsrdpiz",
XSREDP: "xsredp",
XSRESP: "xsresp",
XSRSP: "xsrsp",
XSRSQRTEDP: "xsrsqrtedp",
XSRSQRTESP: "xsrsqrtesp",
XSSQRTDP: "xssqrtdp",
XSSQRTSP: "xssqrtsp",
XSSUBDP: "xssubdp",
XSSUBSP: "xssubsp",
XSTDIVDP: "xstdivdp",
XSTSQRTDP: "xstsqrtdp",
XVABSDP: "xvabsdp",
XVABSSP: "xvabssp",
XVADDDP: "xvadddp",
XVADDSP: "xvaddsp",
XVCMPEQDP: "xvcmpeqdp",
XVCMPEQDPCC: "xvcmpeqdp.",
XVCMPEQSP: "xvcmpeqsp",
XVCMPEQSPCC: "xvcmpeqsp.",
XVCMPGEDP: "xvcmpgedp",
XVCMPGEDPCC: "xvcmpgedp.",
XVCMPGESP: "xvcmpgesp",
XVCMPGESPCC: "xvcmpgesp.",
XVCMPGTDP: "xvcmpgtdp",
XVCMPGTDPCC: "xvcmpgtdp.",
XVCMPGTSP: "xvcmpgtsp",
XVCMPGTSPCC: "xvcmpgtsp.",
XVCPSGNDP: "xvcpsgndp",
XVCPSGNSP: "xvcpsgnsp",
XVCVDPSP: "xvcvdpsp",
XVCVDPSXDS: "xvcvdpsxds",
XVCVDPSXWS: "xvcvdpsxws",
XVCVDPUXDS: "xvcvdpuxds",
XVCVDPUXWS: "xvcvdpuxws",
XVCVSPDP: "xvcvspdp",
XVCVSPSXDS: "xvcvspsxds",
XVCVSPSXWS: "xvcvspsxws",
XVCVSPUXDS: "xvcvspuxds",
XVCVSPUXWS: "xvcvspuxws",
XVCVSXDDP: "xvcvsxddp",
XVCVSXDSP: "xvcvsxdsp",
XVCVSXWDP: "xvcvsxwdp",
XVCVSXWSP: "xvcvsxwsp",
XVCVUXDDP: "xvcvuxddp",
XVCVUXDSP: "xvcvuxdsp",
XVCVUXWDP: "xvcvuxwdp",
XVCVUXWSP: "xvcvuxwsp",
XVDIVDP: "xvdivdp",
XVDIVSP: "xvdivsp",
XVMADDADP: "xvmaddadp",
XVMADDASP: "xvmaddasp",
XVMAXDP: "xvmaxdp",
XVMAXSP: "xvmaxsp",
XVMINDP: "xvmindp",
XVMINSP: "xvminsp",
XVMSUBADP: "xvmsubadp",
XVMSUBASP: "xvmsubasp",
XVMULDP: "xvmuldp",
XVMULSP: "xvmulsp",
XVNABSDP: "xvnabsdp",
XVNABSSP: "xvnabssp",
XVNEGDP: "xvnegdp",
XVNEGSP: "xvnegsp",
XVNMADDADP: "xvnmaddadp",
XVNMADDASP: "xvnmaddasp",
XVNMSUBADP: "xvnmsubadp",
XVNMSUBASP: "xvnmsubasp",
XVRDPI: "xvrdpi",
XVRDPIC: "xvrdpic",
XVRDPIM: "xvrdpim",
XVRDPIP: "xvrdpip",
XVRDPIZ: "xvrdpiz",
XVREDP: "xvredp",
XVRESP: "xvresp",
XVRSPI: "xvrspi",
XVRSPIC: "xvrspic",
XVRSPIM: "xvrspim",
XVRSPIP: "xvrspip",
XVRSPIZ: "xvrspiz",
XVRSQRTEDP: "xvrsqrtedp",
XVRSQRTESP: "xvrsqrtesp",
XVSQRTDP: "xvsqrtdp",
XVSQRTSP: "xvsqrtsp",
XVSUBDP: "xvsubdp",
XVSUBSP: "xvsubsp",
XVTDIVDP: "xvtdivdp",
XVTDIVSP: "xvtdivsp",
XVTSQRTDP: "xvtsqrtdp",
XVTSQRTSP: "xvtsqrtsp",
XXLAND: "xxland",
XXLANDC: "xxlandc",
XXLEQV: "xxleqv",
XXLNAND: "xxlnand",
XXLORC: "xxlorc",
XXLNOR: "xxlnor",
XXLOR: "xxlor",
XXLXOR: "xxlxor",
XXMRGHW: "xxmrghw",
XXMRGLW: "xxmrglw",
XXPERMDI: "xxpermdi",
XXPERM: "xxperm",
XXSEL: "xxsel",
XXSLDWI: "xxsldwi",
XXSPLTW: "xxspltw",
XXBRD: "xxbrd",
XXBRW: "xxbrw",
XXBRH: "xxbrh",
ICBI: "icbi",
ICBT: "icbt",
DCBT: "dcbt",
DCBTST: "dcbtst",
DCBZ: "dcbz",
DCBST: "dcbst",
DCBF: "dcbf",
ISYNC: "isync",
LBARX: "lbarx",
LHARX: "lharx",
LWARX: "lwarx",
STBCXCC: "stbcx.",
STHCXCC: "sthcx.",
STWCXCC: "stwcx.",
LDARX: "ldarx",
STDCXCC: "stdcx.",
LQARX: "lqarx",
STQCXCC: "stqcx.",
SYNC: "sync",
EIEIO: "eieio",
WAIT: "wait",
MFTB: "mftb",
RFEBB: "rfebb",
RFID: "rfid",
HRFID: "hrfid",
LBZCIX: "lbzcix",
LWZCIX: "lwzcix",
LHZCIX: "lhzcix",
LDCIX: "ldcix",
STBCIX: "stbcix",
STWCIX: "stwcix",
STHCIX: "sthcix",
STDCIX: "stdcix",
MTMSR: "mtmsr",
MTMSRD: "mtmsrd",
MFMSR: "mfmsr",
SLBIE: "slbie",
SLBIA: "slbia",
SLBMTE: "slbmte",
SLBMFEV: "slbmfev",
SLBMFEE: "slbmfee",
SLBFEECC: "slbfee.",
TLBIE: "tlbie",
TLBIEL: "tlbiel",
TLBSYNC: "tlbsync",
MSGSND: "msgsnd",
MSGCLR: "msgclr",
MSGSNDP: "msgsndp",
MSGCLRP: "msgclrp",
ADDEX: "addex",
DARN: "darn",
MADDHD: "maddhd",
MADDHDU: "maddhdu",
MADDLD: "maddld",
CMPRB: "cmprb",
CMPEQB: "cmpeqb",
EXTSWSLI: "extswsli",
EXTSWSLICC: "extswsli.",
MFVSRLD: "mfvsrld",
MTVSRDD: "mtvsrdd",
MTVSRWS: "mtvsrws",
MCRXRX: "mcrxrx",
COPY: "copy",
PASTECC: "paste.",
BRD: "brd",
BRH: "brh",
BRW: "brw",
CFUGED: "cfuged",
CNTLZDM: "cntlzdm",
CNTTZDM: "cnttzdm",
DCFFIXQQ: "dcffixqq",
DCTFIXQQ: "dctfixqq",
LXVKQ: "lxvkq",
LXVP: "lxvp",
LXVPX: "lxvpx",
LXVRBX: "lxvrbx",
LXVRDX: "lxvrdx",
LXVRHX: "lxvrhx",
LXVRWX: "lxvrwx",
MTVSRBM: "mtvsrbm",
MTVSRBMI: "mtvsrbmi",
MTVSRDM: "mtvsrdm",
MTVSRHM: "mtvsrhm",
MTVSRQM: "mtvsrqm",
MTVSRWM: "mtvsrwm",
PDEPD: "pdepd",
PEXTD: "pextd",
SETBC: "setbc",
SETBCR: "setbcr",
SETNBC: "setnbc",
SETNBCR: "setnbcr",
STXVP: "stxvp",
STXVPX: "stxvpx",
STXVRBX: "stxvrbx",
STXVRDX: "stxvrdx",
STXVRHX: "stxvrhx",
STXVRWX: "stxvrwx",
VCFUGED: "vcfuged",
VCLRLB: "vclrlb",
VCLRRB: "vclrrb",
VCLZDM: "vclzdm",
VCMPEQUQ: "vcmpequq",
VCMPEQUQCC: "vcmpequq.",
VCMPGTSQ: "vcmpgtsq",
VCMPGTSQCC: "vcmpgtsq.",
VCMPGTUQ: "vcmpgtuq",
VCMPGTUQCC: "vcmpgtuq.",
VCMPSQ: "vcmpsq",
VCMPUQ: "vcmpuq",
VCNTMBB: "vcntmbb",
VCNTMBD: "vcntmbd",
VCNTMBH: "vcntmbh",
VCNTMBW: "vcntmbw",
VCTZDM: "vctzdm",
VDIVESD: "vdivesd",
VDIVESQ: "vdivesq",
VDIVESW: "vdivesw",
VDIVEUD: "vdiveud",
VDIVEUQ: "vdiveuq",
VDIVEUW: "vdiveuw",
VDIVSD: "vdivsd",
VDIVSQ: "vdivsq",
VDIVSW: "vdivsw",
VDIVUD: "vdivud",
VDIVUQ: "vdivuq",
VDIVUW: "vdivuw",
VEXPANDBM: "vexpandbm",
VEXPANDDM: "vexpanddm",
VEXPANDHM: "vexpandhm",
VEXPANDQM: "vexpandqm",
VEXPANDWM: "vexpandwm",
VEXTDDVLX: "vextddvlx",
VEXTDDVRX: "vextddvrx",
VEXTDUBVLX: "vextdubvlx",
VEXTDUBVRX: "vextdubvrx",
VEXTDUHVLX: "vextduhvlx",
VEXTDUHVRX: "vextduhvrx",
VEXTDUWVLX: "vextduwvlx",
VEXTDUWVRX: "vextduwvrx",
VEXTRACTBM: "vextractbm",
VEXTRACTDM: "vextractdm",
VEXTRACTHM: "vextracthm",
VEXTRACTQM: "vextractqm",
VEXTRACTWM: "vextractwm",
VEXTSD2Q: "vextsd2q",
VGNB: "vgnb",
VINSBLX: "vinsblx",
VINSBRX: "vinsbrx",
VINSBVLX: "vinsbvlx",
VINSBVRX: "vinsbvrx",
VINSD: "vinsd",
VINSDLX: "vinsdlx",
VINSDRX: "vinsdrx",
VINSHLX: "vinshlx",
VINSHRX: "vinshrx",
VINSHVLX: "vinshvlx",
VINSHVRX: "vinshvrx",
VINSW: "vinsw",
VINSWLX: "vinswlx",
VINSWRX: "vinswrx",
VINSWVLX: "vinswvlx",
VINSWVRX: "vinswvrx",
VMODSD: "vmodsd",
VMODSQ: "vmodsq",
VMODSW: "vmodsw",
VMODUD: "vmodud",
VMODUQ: "vmoduq",
VMODUW: "vmoduw",
VMSUMCUD: "vmsumcud",
VMULESD: "vmulesd",
VMULEUD: "vmuleud",
VMULHSD: "vmulhsd",
VMULHSW: "vmulhsw",
VMULHUD: "vmulhud",
VMULHUW: "vmulhuw",
VMULLD: "vmulld",
VMULOSD: "vmulosd",
VMULOUD: "vmuloud",
VPDEPD: "vpdepd",
VPEXTD: "vpextd",
VRLQ: "vrlq",
VRLQMI: "vrlqmi",
VRLQNM: "vrlqnm",
VSLDBI: "vsldbi",
VSLQ: "vslq",
VSRAQ: "vsraq",
VSRDBI: "vsrdbi",
VSRQ: "vsrq",
VSTRIBL: "vstribl",
VSTRIBLCC: "vstribl.",
VSTRIBR: "vstribr",
VSTRIBRCC: "vstribr.",
VSTRIHL: "vstrihl",
VSTRIHLCC: "vstrihl.",
VSTRIHR: "vstrihr",
VSTRIHRCC: "vstrihr.",
XSCMPEQQP: "xscmpeqqp",
XSCMPGEQP: "xscmpgeqp",
XSCMPGTQP: "xscmpgtqp",
XSCVQPSQZ: "xscvqpsqz",
XSCVQPUQZ: "xscvqpuqz",
XSCVSQQP: "xscvsqqp",
XSCVUQQP: "xscvuqqp",
XSMAXCQP: "xsmaxcqp",
XSMINCQP: "xsmincqp",
XVBF16GER2: "xvbf16ger2",
XVBF16GER2NN: "xvbf16ger2nn",
XVBF16GER2NP: "xvbf16ger2np",
XVBF16GER2PN: "xvbf16ger2pn",
XVBF16GER2PP: "xvbf16ger2pp",
XVCVBF16SPN: "xvcvbf16spn",
XVCVSPBF16: "xvcvspbf16",
XVF16GER2: "xvf16ger2",
XVF16GER2NN: "xvf16ger2nn",
XVF16GER2NP: "xvf16ger2np",
XVF16GER2PN: "xvf16ger2pn",
XVF16GER2PP: "xvf16ger2pp",
XVF32GER: "xvf32ger",
XVF32GERNN: "xvf32gernn",
XVF32GERNP: "xvf32gernp",
XVF32GERPN: "xvf32gerpn",
XVF32GERPP: "xvf32gerpp",
XVF64GER: "xvf64ger",
XVF64GERNN: "xvf64gernn",
XVF64GERNP: "xvf64gernp",
XVF64GERPN: "xvf64gerpn",
XVF64GERPP: "xvf64gerpp",
XVI16GER2: "xvi16ger2",
XVI16GER2PP: "xvi16ger2pp",
XVI16GER2S: "xvi16ger2s",
XVI16GER2SPP: "xvi16ger2spp",
XVI4GER8: "xvi4ger8",
XVI4GER8PP: "xvi4ger8pp",
XVI8GER4: "xvi8ger4",
XVI8GER4PP: "xvi8ger4pp",
XVI8GER4SPP: "xvi8ger4spp",
XVTLSBB: "xvtlsbb",
XXGENPCVBM: "xxgenpcvbm",
XXGENPCVDM: "xxgenpcvdm",
XXGENPCVHM: "xxgenpcvhm",
XXGENPCVWM: "xxgenpcvwm",
XXMFACC: "xxmfacc",
XXMTACC: "xxmtacc",
XXSETACCZ: "xxsetaccz",
MSGCLRU: "msgclru",
MSGSNDU: "msgsndu",
URFID: "urfid",
MFFSCDRN: "mffscdrn",
MFFSCDRNI: "mffscdrni",
MFFSCE: "mffsce",
MFFSCRN: "mffscrn",
MFFSCRNI: "mffscrni",
MFFSL: "mffsl",
SLBIAG: "slbiag",
ADDPCIS: "addpcis",
BCDCFNCC: "bcdcfn.",
BCDCFSQCC: "bcdcfsq.",
BCDCFZCC: "bcdcfz.",
BCDCPSGNCC: "bcdcpsgn.",
BCDCTNCC: "bcdctn.",
BCDCTSQCC: "bcdctsq.",
BCDCTZCC: "bcdctz.",
BCDSCC: "bcds.",
BCDSETSGNCC: "bcdsetsgn.",
BCDSRCC: "bcdsr.",
BCDTRUNCCC: "bcdtrunc.",
BCDUSCC: "bcdus.",
BCDUTRUNCCC: "bcdutrunc.",
CNTTZD: "cnttzd",
CNTTZDCC: "cnttzd.",
CNTTZW: "cnttzw",
CNTTZWCC: "cnttzw.",
CPABORT: "cpabort",
DTSTSFI: "dtstsfi",
DTSTSFIQ: "dtstsfiq",
LDAT: "ldat",
LWAT: "lwat",
LXSD: "lxsd",
LXSIBZX: "lxsibzx",
LXSIHZX: "lxsihzx",
LXSSP: "lxssp",
LXVWSX: "lxvwsx",
MSGSYNC: "msgsync",
SETB: "setb",
SLBIEG: "slbieg",
SLBSYNC: "slbsync",
STDAT: "stdat",
STOP: "stop",
STWAT: "stwat",
STXSD: "stxsd",
STXSIBX: "stxsibx",
STXSIHX: "stxsihx",
STXSSP: "stxssp",
VABSDUB: "vabsdub",
VABSDUH: "vabsduh",
VABSDUW: "vabsduw",
VCLZLSBB: "vclzlsbb",
VCTZB: "vctzb",
VCTZD: "vctzd",
VCTZH: "vctzh",
VCTZLSBB: "vctzlsbb",
VCTZW: "vctzw",
VEXTRACTD: "vextractd",
VEXTRACTUB: "vextractub",
VEXTRACTUH: "vextractuh",
VEXTRACTUW: "vextractuw",
VEXTSB2D: "vextsb2d",
VEXTSB2W: "vextsb2w",
VEXTSH2D: "vextsh2d",
VEXTSH2W: "vextsh2w",
VEXTSW2D: "vextsw2d",
VEXTUBLX: "vextublx",
VEXTUBRX: "vextubrx",
VEXTUHLX: "vextuhlx",
VEXTUHRX: "vextuhrx",
VEXTUWLX: "vextuwlx",
VEXTUWRX: "vextuwrx",
VINSERTB: "vinsertb",
VINSERTD: "vinsertd",
VINSERTH: "vinserth",
VINSERTW: "vinsertw",
VMUL10CUQ: "vmul10cuq",
VMUL10ECUQ: "vmul10ecuq",
VMUL10EUQ: "vmul10euq",
VMUL10UQ: "vmul10uq",
VNEGD: "vnegd",
VNEGW: "vnegw",
VPRTYBD: "vprtybd",
VPRTYBQ: "vprtybq",
VPRTYBW: "vprtybw",
VRLDMI: "vrldmi",
VRLDNM: "vrldnm",
VRLWMI: "vrlwmi",
VRLWNM: "vrlwnm",
VSLV: "vslv",
VSRV: "vsrv",
XSABSQP: "xsabsqp",
XSADDQP: "xsaddqp",
XSADDQPO: "xsaddqpo",
XSCMPEQDP: "xscmpeqdp",
XSCMPEXPDP: "xscmpexpdp",
XSCMPEXPQP: "xscmpexpqp",
XSCMPGEDP: "xscmpgedp",
XSCMPGTDP: "xscmpgtdp",
XSCMPOQP: "xscmpoqp",
XSCMPUQP: "xscmpuqp",
XSCPSGNQP: "xscpsgnqp",
XSCVDPHP: "xscvdphp",
XSCVDPQP: "xscvdpqp",
XSCVHPDP: "xscvhpdp",
XSCVQPDP: "xscvqpdp",
XSCVQPDPO: "xscvqpdpo",
XSCVQPSDZ: "xscvqpsdz",
XSCVQPSWZ: "xscvqpswz",
XSCVQPUDZ: "xscvqpudz",
XSCVQPUWZ: "xscvqpuwz",
XSCVSDQP: "xscvsdqp",
XSCVUDQP: "xscvudqp",
XSDIVQP: "xsdivqp",
XSDIVQPO: "xsdivqpo",
XSIEXPDP: "xsiexpdp",
XSIEXPQP: "xsiexpqp",
XSMADDQP: "xsmaddqp",
XSMADDQPO: "xsmaddqpo",
XSMAXCDP: "xsmaxcdp",
XSMAXJDP: "xsmaxjdp",
XSMINCDP: "xsmincdp",
XSMINJDP: "xsminjdp",
XSMSUBQP: "xsmsubqp",
XSMSUBQPO: "xsmsubqpo",
XSMULQP: "xsmulqp",
XSMULQPO: "xsmulqpo",
XSNABSQP: "xsnabsqp",
XSNEGQP: "xsnegqp",
XSNMADDQP: "xsnmaddqp",
XSNMADDQPO: "xsnmaddqpo",
XSNMSUBQP: "xsnmsubqp",
XSNMSUBQPO: "xsnmsubqpo",
XSRQPI: "xsrqpi",
XSRQPIX: "xsrqpix",
XSRQPXP: "xsrqpxp",
XSSQRTQP: "xssqrtqp",
XSSQRTQPO: "xssqrtqpo",
XSSUBQP: "xssubqp",
XSSUBQPO: "xssubqpo",
XSTSTDCDP: "xststdcdp",
XSTSTDCQP: "xststdcqp",
XSTSTDCSP: "xststdcsp",
XSXEXPDP: "xsxexpdp",
XSXEXPQP: "xsxexpqp",
XSXSIGDP: "xsxsigdp",
XSXSIGQP: "xsxsigqp",
XVCVHPSP: "xvcvhpsp",
XVCVSPHP: "xvcvsphp",
XVIEXPDP: "xviexpdp",
XVIEXPSP: "xviexpsp",
XVTSTDCDP: "xvtstdcdp",
XVTSTDCSP: "xvtstdcsp",
XVXEXPDP: "xvxexpdp",
XVXEXPSP: "xvxexpsp",
XVXSIGDP: "xvxsigdp",
XVXSIGSP: "xvxsigsp",
XXBRQ: "xxbrq",
XXEXTRACTUW: "xxextractuw",
XXINSERTW: "xxinsertw",
XXPERMR: "xxpermr",
XXSPLTIB: "xxspltib",
XSMADDMSP: "xsmaddmsp",
XSMSUBMSP: "xsmsubmsp",
XSNMADDMSP: "xsnmaddmsp",
XSNMSUBMSP: "xsnmsubmsp",
XSMADDMDP: "xsmaddmdp",
XSMSUBMDP: "xsmsubmdp",
XSNMADDMDP: "xsnmaddmdp",
XSNMSUBMDP: "xsnmsubmdp",
XVMADDMDP: "xvmaddmdp",
XVMADDMSP: "xvmaddmsp",
XVMSUBMDP: "xvmsubmdp",
XVMSUBMSP: "xvmsubmsp",
XVNMADDMDP: "xvnmaddmdp",
XVNMADDMSP: "xvnmaddmsp",
XVNMSUBMDP: "xvnmsubmdp",
XVNMSUBMSP: "xvnmsubmsp",
DADDQ: "daddq",
DADDQCC: "daddq.",
DCMPOQ: "dcmpoq",
DCMPUQ: "dcmpuq",
DCTFIXQ: "dctfixq",
DCTFIXQCC: "dctfixq.",
DDEDPDQ: "ddedpdq",
DDEDPDQCC: "ddedpdq.",
DDIVQ: "ddivq",
DDIVQCC: "ddivq.",
DENBCDQ: "denbcdq",
DENBCDQCC: "denbcdq.",
DIEXQCC: "diexq.",
DIEXQ: "diexq",
DMULQ: "dmulq",
DMULQCC: "dmulq.",
DQUAIQ: "dquaiq",
DQUAIQCC: "dquaiq.",
DQUAQ: "dquaq",
DQUAQCC: "dquaq.",
DRINTNQ: "drintnq",
DRINTNQCC: "drintnq.",
DRINTXQ: "drintxq",
DRINTXQCC: "drintxq.",
DRRNDQ: "drrndq",
DRRNDQCC: "drrndq.",
DSCLIQ: "dscliq",
DSCLIQCC: "dscliq.",
DSCRIQ: "dscriq",
DSCRIQCC: "dscriq.",
DSUBQ: "dsubq",
DSUBQCC: "dsubq.",
DTSTDCQ: "dtstdcq",
DTSTDGQ: "dtstdgq",
DTSTEXQ: "dtstexq",
DTSTSFQ: "dtstsfq",
DXEXQ: "dxexq",
DXEXQCC: "dxexq.",
RFSCV: "rfscv",
SCV: "scv",
}
var (
ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}}
ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}}
ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}}
ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}}
ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}}
ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}}
ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}}
ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}}
ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}}
ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}}
ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}}
ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}}
ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}}
ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}}
ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}}
ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}}
ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}}
ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}}
ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}}
ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}}
ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_6_8 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 3}}}
ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}}
ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}}
ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}}
ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}}
ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}}
ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}}
ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}}
ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}}
ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}}
ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}}
ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}}
ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}}
ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}}
ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}}
ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}}
ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
ap_VecSReg_28_28_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {6, 5}}}
ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}}
ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}}
ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}}
ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}}
ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}}
ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}}
ap_ImmUnsigned_12_13 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 2}}}
ap_ImmUnsigned_14_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1}}}
ap_Reg_21_25 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5}}}
ap_VecSpReg_10_10_6_9 = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1}, {6, 4}}}
ap_ImmUnsigned_16_25_11_15_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 10}, {11, 5}, {31, 1}}}
ap_ImmUnsigned_23_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{23, 3}}}
ap_MMAReg_6_8 = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3}}}
ap_ImmUnsigned_18_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{18, 3}}}
ap_ImmSigned_16_25_11_15_31_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 10}, {11, 5}, {31, 1}}}
ap_ImmUnsigned_10_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 6}}}
ap_ImmUnsigned_9_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 7}}}
ap_ImmUnsigned_25_25_29_29_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{25, 1}, {29, 1}, {11, 5}}}
ap_ImmUnsigned_13_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 8}}}
)
var instFormats = [...]instFormat{
{CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CNTLZWCC, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr)
[5]*argField{ap_PCRel_6_29_shift2}},
{BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr)
[5]*argField{ap_Label_6_29_shift2}},
{BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr)
[5]*argField{ap_PCRel_6_29_shift2}},
{BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr)
[5]*argField{ap_Label_6_29_shift2}},
{BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
{BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
{BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
{BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
{BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH)
[5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
{CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA)
[5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
{CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB)
[5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
{SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
[5]*argField{ap_ImmUnsigned_20_26}},
{CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb)
[5]*argField{}},
{MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From BHRB XFX-form (mfbhrbe RT,BHRBE)
[5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
{LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
{STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA))
[5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
{LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
{STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI)
[5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
{ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT,SI)
[5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
{ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDCC, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDOCC, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-formy (addic RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFCC, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFOCC, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDICCC, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDCCC, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDCOCC, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFCCC, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFCOCC, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDECC, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDEOCC, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDMECC, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDMEOCC, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFECC, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFEOCC, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFMECC, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFMEOCC, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZECC, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{ADDZEOCC, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZECC, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{SUBFZEOCC, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEGCC, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{NEGOCC, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
{MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLWCC, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLWOCC, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHWCC, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHWUCC, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWCC, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWOCC, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWUCC, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWUOCC, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWECC, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEOCC, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEUCC, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVWEUOCC, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLDCC, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULLDOCC, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHDUCC, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MULHDCC, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDCC, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDOCC, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDUCC, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDUOCC, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDECC, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEOCC, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEUCC, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MODSD, 0xfc0007fe, 0x7c000612, 0x1, // Modulo Signed Doubleword X-form (modsd RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MODUD, 0xfc0007fe, 0x7c000212, 0x1, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MODSW, 0xfc0007fe, 0x7c000616, 0x1, // Modulo Signed Word X-form (modsw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MODUW, 0xfc0007fe, 0x7c000216, 0x1, // Modulo Unsigned Word X-form (moduw RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
{CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
{CMPI, 0xfc000000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpi BF,L,RA,SI)
[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMP, 0xfc0007fe, 0x7c000000, 0x400001, // Compare X-form (cmp BF,L,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
{CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
{CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
{CMPLI, 0xfc000000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmpli BF,L,RA,UI)
[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
{CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
{CMPL, 0xfc0007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmpl BF,L,RA,RB)
[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
{TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
{ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
{TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB)
[5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{ANDICC, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{ANDISCC, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
{AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ANDCC, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{XORCC, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NANDCC, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ORCC, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{NORCC, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ANDCCC, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSBCC, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{EQVCC, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{ORCCC, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSHCC, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{EXTSWCC, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CNTLZDCC, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWINMCC, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWNMCC, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLWIMICC, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
{RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICLCC, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICRCC, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDICCC, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCLCC, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDCRCC, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{RLDIMICC, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
{SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SLWCC, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRWCC, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
{SRAWICC, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
{SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRAWCC, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SLDCC, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRDCC, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
{SRADICC, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
{SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{SRADCC, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
{CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS)
[5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
{ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB)
[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
{MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
[5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
{MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT)
[5]*argField{ap_Reg_6_10}},
{MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
{MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
{MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword X-form (mtvsrd XT,RA)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
{MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
{MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA)
[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
{MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS)
[5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
{MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM)
[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
{LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word & Zero Indexed X-form (lfiwzx FRT,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
{STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA))
[5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
{STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB)
[5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FMRCC, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FABSCC, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNABSCC, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FNEGCC, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FCPSGNCC, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add A-form (fadd FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADDCC, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add A-form (fadd. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add Single A-form (fadds FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FADDSCC, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add Single A-form (fadds. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract A-form (fsub FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUBCC, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract A-form (fsub. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract Single A-form (fsubs FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSUBSCC, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract Single A-form (fsubs. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply A-form (fmul FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FMULCC, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply A-form (fmul. FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply Single A-form (fmuls FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FMULSCC, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply Single A-form (fmuls. FRT,FRA,FRC)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
{FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide A-form (fdiv FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FDIVCC, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide A-form (fdiv. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide Single A-form (fdivs FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FDIVSCC, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide Single A-form (fdivs. FRT,FRA,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root A-form (fsqrt FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FSQRTCC, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root A-form (fsqrt. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root Single A-form (fsqrts FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FSQRTSCC, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root Single A-form (fsqrts. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate A-form (fre FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRECC, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate A-form (fre. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate Single A-form (fres FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRESCC, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate Single A-form (fres. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate A-form (frsqrte FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTECC, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate A-form (frsqrte. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSQRTESCC, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
{FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
{FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add A-form (fmadd FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMADDCC, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add A-form (fmadd. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add Single A-form (fmadds FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMADDSCC, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add Single A-form (fmadds. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract A-form (fmsub FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUBCC, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract A-form (fmsub. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FMSUBSCC, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add A-form (fnmadd FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADDCC, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add A-form (fnmadd. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMADDSCC, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUBCC, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FNMSUBSCC, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRSPCC, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDCC, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDZCC, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDUCC, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIDUZCC, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWCC, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWZCC, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWUCC, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCTIWUZCC, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDCC, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDUCC, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDSCC, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCFIDUSCC, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRINCC, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIZCC, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIPCC, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FRIMCC, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
{FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
{FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB)
[5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
{FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{FSELCC, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
[5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
{MFFS, 0xfc1f07ff, 0xfc00048e, 0xf800, // Move From FPSCR X-form (mffs FRT)
[5]*argField{ap_FPReg_6_10}},
{MFFSCC, 0xfc1f07ff, 0xfc00048f, 0xf800, // Move From FPSCR X-form (mffs. FRT)
[5]*argField{ap_FPReg_6_10}},
{MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
[5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
{MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
[5]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
{MTFSFICC, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
[5]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
{MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
[5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
{MTFSFCC, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
[5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
{MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
[5]*argField{ap_ImmUnsigned_6_10}},
{MTFSB0CC, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
[5]*argField{ap_ImmUnsigned_6_10}},
{MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
[5]*argField{ap_ImmUnsigned_6_10}},
{MTFSB1CC, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
[5]*argField{ap_ImmUnsigned_6_10}},
{LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB)
[5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{