arm/armasm: fix wrong register order in SMLABT/SMLATB/SMLATT/SMLAD/SMLSD
SMLABT/SMLATB/SMLATT/SMLAD/SMLSD are MLA(mul&add) like instructions,
which need the third register to be the addend. But currently the addend
is placed in the first position in the decoded register list.
This patch fixes it and adds corresponding tests.
Change-Id: I57f3e96876c54497badf1a12ae7dae18fe6fcc11
Reviewed-on: https://go-review.googlesource.com/47890
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
diff --git a/arm/armasm/plan9x.go b/arm/armasm/plan9x.go
index dd426cd..cbae803 100644
--- a/arm/armasm/plan9x.go
+++ b/arm/armasm/plan9x.go
@@ -115,7 +115,7 @@
}
// For MLA-like instructions, the addend is the third operand.
switch inst.Op &^ 15 {
- case SMLAWT_EQ, SMLAWB_EQ, MLA_EQ, MLA_S_EQ, MLS_EQ, SMMLA_EQ, SMMLS_EQ, SMLABB_EQ:
+ case SMLAWT_EQ, SMLAWB_EQ, MLA_EQ, MLA_S_EQ, MLS_EQ, SMMLA_EQ, SMMLS_EQ, SMLABB_EQ, SMLATB_EQ, SMLABT_EQ, SMLATT_EQ, SMLAD_EQ, SMLAD_X_EQ, SMLSD_EQ, SMLSD_X_EQ:
args = []string{args[1], args[2], args[0], args[3]}
}
diff --git a/arm/armasm/testdata/decode.txt b/arm/armasm/testdata/decode.txt
index 4b3ea6e..3832b52 100644
--- a/arm/armasm/testdata/decode.txt
+++ b/arm/armasm/testdata/decode.txt
@@ -896,6 +896,13 @@
123154e7| 1 plan9 SMMLA R1, R2, R3, R4
d23154e7| 1 plan9 SMMLS R1, R2, R3, R4
823104e1| 1 plan9 SMLABB R1, R2, R3, R4
+a23104e1| 1 plan9 SMLATB R1, R2, R3, R4
+c23104e1| 1 plan9 SMLABT R1, R2, R3, R4
+e23104e1| 1 plan9 SMLATT R1, R2, R3, R4
+123104e7| 1 plan9 SMLAD R1, R2, R3, R4
+323104e7| 1 plan9 SMLAD.X R1, R2, R3, R4
+523104e7| 1 plan9 SMLSD R1, R2, R3, R4
+723104e7| 1 plan9 SMLSD.X R1, R2, R3, R4
9231e4e0| 1 plan9 SMLAL R1, R2, R4, R3
9231f4e0| 1 plan9 SMLAL.S R1, R2, R4, R3
9231a4e0| 1 plan9 UMLAL R1, R2, R4, R3
