diff --git a/ppc64/pp64.csv b/ppc64/pp64.csv
index 4f470e4..5df22bf 100644
--- a/ppc64/pp64.csv
+++ b/ppc64/pp64.csv
@@ -533,6 +533,7 @@
 "Load VSX Vector DQ-form","lxv XT,DQ(RA)","61@0|T@6|RA@11|DQ@16|TX@28|1@29|",""
 "Load VSX Vector with Length X-form","lxvl XT,RA,RB","31@0|T@6|RA@11|RB@16|269@21|TX@31|",""
 "Load VSX Vector Left-justified with Length X-form","lxvll XT,RA,RB","31@0|T@6|RA@11|RB@16|301@21|TX@31|",""
+"Load VSX Vector Indexed X-form","lxvx XT,RA,RB","31@0|T@6|RA@11|RB@16|268@21|TX@31|",""
 "Store VSX Scalar Doubleword Indexed XX1-form","stxsdx XS,RA,RB","31@0|S@6|RA@11|RB@16|716@21|SX@31|",""
 "Store VSX Scalar as Integer Word Indexed XX1-form","stxsiwx XS,RA,RB","31@0|S@6|RA@11|RB@16|140@21|SX@31|",""
 "Store VSX Scalar Single-Precision Indexed XX1-form","stxsspx XS,RA,RB","31@0|S@6|RA@11|RB@16|652@21|SX@31|",""
@@ -541,6 +542,7 @@
 "Store VSX Vector DQ-form","stxv XS,DQ(RA)","61@0|S@6|RA@11|DQ@16|SX@28|5@29|",""
 "Store VSX Vector with Length X-form","stxvl XS,RA,RB","31@0|S@6|RA@11|RB@16|397@21|SX@31|",""
 "Store VSX Vector Left-justified with Length X-form","stxvll XS,RA,RB","31@0|S@6|RA@11|RB@16|429@21|SX@31|",""
+"Store VSX Vector Indexed X-form","stxvx XS,RA,RB","31@0|S@6|RA@11|RB@16|396@21|SX@31|",""
 "VSX Scalar Absolute Value Double-Precision XX2-form","xsabsdp XT,XB","60@0|T@6|///@11|B@16|345@21|BX@30|TX@31|",""
 "VSX Scalar Add Double-Precision XX3-form","xsadddp XT,XA,XB","60@0|T@6|A@11|B@16|32@21|AX@29|BX@30|TX@31|",""
 "VSX Scalar Add Single-Precision XX3-form","xsaddsp XT,XA,XB","60@0|T@6|A@11|B@16|0@21|AX@29|BX@30|TX@31|",""
diff --git a/ppc64/ppc64asm/plan9.go b/ppc64/ppc64asm/plan9.go
index 858f9ac..9cb8c8c 100644
--- a/ppc64/ppc64asm/plan9.go
+++ b/ppc64/ppc64asm/plan9.go
@@ -112,7 +112,7 @@
 	case STDCXCC, STWCXCC, STHCXCC, STBCXCC:
 		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
-	case STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
+	case STXVX, STXVD2X, STXVW4X, STXSDX, STVX, STVXL, STVEBX, STVEHX, STVEWX, STXSIWX, STFDX, STFDUX, STFDPX, STFSX, STFSUX:
 		return op + " " + args[0] + ",(" + args[2] + ")(" + args[1] + ")"
 
 	case STXV:
@@ -127,7 +127,7 @@
 		}
 		return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
 
-	case LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
+	case LXVX, LXVD2X, LXVW4X, LVX, LVXL, LVSR, LVSL, LVEBX, LVEHX, LVEWX, LXSDX, LXSIWAX:
 		return op + " (" + args[2] + ")(" + args[1] + ")," + args[0]
 
 	case LXV:
diff --git a/ppc64/ppc64asm/tables.go b/ppc64/ppc64asm/tables.go
index 250d3b7..102f836 100644
--- a/ppc64/ppc64asm/tables.go
+++ b/ppc64/ppc64asm/tables.go
@@ -730,6 +730,7 @@
 	LXV
 	LXVL
 	LXVLL
+	LXVX
 	STXSDX
 	STXSIWX
 	STXSSPX
@@ -738,6 +739,7 @@
 	STXV
 	STXVL
 	STXVLL
+	STXVX
 	XSABSDP
 	XSADDDP
 	XSADDSP
@@ -2098,6 +2100,7 @@
 	LXV:           "lxv",
 	LXVL:          "lxvl",
 	LXVLL:         "lxvll",
+	LXVX:          "lxvx",
 	STXSDX:        "stxsdx",
 	STXSIWX:       "stxsiwx",
 	STXSSPX:       "stxsspx",
@@ -2106,6 +2109,7 @@
 	STXV:          "stxv",
 	STXVL:         "stxvl",
 	STXVLL:        "stxvll",
+	STXVX:         "stxvx",
 	XSABSDP:       "xsabsdp",
 	XSADDDP:       "xsadddp",
 	XSADDSP:       "xsaddsp",
@@ -4266,6 +4270,8 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{LXVLL, 0xfc0007fe, 0x7c00025a, 0x0, // Load VSX Vector Left-justified with Length X-form (lxvll XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{LXVX, 0xfc0007fe, 0x7c000218, 0x0, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB)
@@ -4282,6 +4288,8 @@
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STXVLL, 0xfc0007fe, 0x7c00035a, 0x0, // Store VSX Vector Left-justified with Length X-form (stxvll XS,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
+	{STXVX, 0xfc0007fe, 0x7c000318, 0x0, // Store VSX Vector Indexed X-form (stxvx XS,RA,RB)
+		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
 	{XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
diff --git a/ppc64/ppc64asm/testdata/decode.txt b/ppc64/ppc64asm/testdata/decode.txt
index e094383..5b8ae2f 100644
--- a/ppc64/ppc64asm/testdata/decode.txt
+++ b/ppc64/ppc64asm/testdata/decode.txt
@@ -420,11 +420,13 @@
 f4230011|	plan9	LXV 16(R3),VS1
 7c23221a|	plan9	LXVL R3,R4,VS1
 7c23225a|	plan9	LXVLL R3,R4,VS1
+7c241a18|	plan9	LXVX (R3)(R4),VS1
 7c241c98|	plan9	LXSDX (R3)(R4),VS1
 7c241f98|	plan9	STXVD2X VS1,(R3)(R4)
 f4230015|	plan9	STXV VS1,16(R3)
 7c23231a|	plan9	STXVL VS1,R3,R4
 7c23235a|	plan9	STXVLL VS1,R3,R4
+7c241b18|	plan9	STXVX VS1,(R3)(R4)
 7c241d98|	plan9	STXSDX VS1,(R3)(R4)
 7c241898|	plan9	LXSIWAX (R3)(R4),VS1
 7c241918|	plan9	STXSIWX VS1,(R3)(R4)
@@ -802,6 +804,8 @@
 7c23221a|	gnu	lxvl vs1,r3,r4
 7c23225a|	gnu	lxvll vs1,r3,r4
 7c241c98|	gnu	lxsdx vs1,r4,r3
+7c241a18|	gnu	lxvx vs1,r4,r3
+7c241b18|	gnu	stxvx vs1,r4,r3
 7c241f98|	gnu	stxvd2x vs1,r4,r3
 f4230015|	gnu	stxv vs1,16(r3)
 7c23231a|	gnu	stxvl vs1,r3,r4