ppc64/ppc64asm,ppc64map: fix BHRBE argument translation
BHRBE stands for "branch history rolling buffer entry". This is not
an SPR. Treat it as an unsigned immediate type argument.
Similarly, DCRN, SR, TMR, PMRN fields are no longer present in ISA 3.1,
they can be removed and nearby code simplified.
Fix ppc64map and update tables.go.
Change-Id: Ie779d24ae9d24541db6565ea169be0d80b893ff8
Reviewed-on: https://go-review.googlesource.com/c/arch/+/418858
Reviewed-by: Ian Lance Taylor <iant@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
Run-TryBot: Paul Murphy <murp@ibm.com>
diff --git a/ppc64/ppc64asm/tables.go b/ppc64/ppc64asm/tables.go
index 9e3b26f..8d0a243 100644
--- a/ppc64/ppc64asm/tables.go
+++ b/ppc64/ppc64asm/tables.go
@@ -2906,7 +2906,7 @@
ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4, 0}}}
ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1, 0}}}
- ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10, 0}}}
+ ap_ImmUnsigned_11_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10, 0}}}
ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1, 0}}}
ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1, 0}}}
ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4, 0}}}
@@ -3883,7 +3883,7 @@
{LXSSPX, 0xfc0007fe00000000, 0x7c00041800000000, 0x0, // Load VSX Scalar Single-Precision Indexed X-form (lxsspx XT,RA,RB)
[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
{MFBHRBE, 0xfc0007fe00000000, 0x7c00025c00000000, 0x100000000, // Move From BHRB XFX-form (mfbhrbe RT,BHRBE)
- [6]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
+ [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_20}},
{MFVSRD, 0xfc0007fe00000000, 0x7c00006600000000, 0xf80000000000, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
[6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
{MFVSRWZ, 0xfc0007fe00000000, 0x7c0000e600000000, 0xf80000000000, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
diff --git a/ppc64/ppc64map/map.go b/ppc64/ppc64map/map.go
index 8d34553..4f90ed9 100644
--- a/ppc64/ppc64map/map.go
+++ b/ppc64/ppc64map/map.go
@@ -5,12 +5,13 @@
// ppc64map constructs the ppc64 opcode map from the instruction set CSV file.
//
// Usage:
+//
// ppc64map [-fmt=format] ppc64.csv
//
// The known output formats are:
//
-// text (default) - print decoding tree in text form
-// decoder - print decoding tables for the ppc64asm package
+// text (default) - print decoding tree in text form
+// decoder - print decoding tables for the ppc64asm package
package main
import (
@@ -423,7 +424,7 @@
opr = "BD"
}
- case "XMSK", "YMSK", "PMSK", "IX":
+ case "XMSK", "YMSK", "PMSK", "IX", "BHRBE":
typ = asm.TypeImmUnsigned
case "IMM32":
@@ -559,12 +560,8 @@
case "VRA", "VRB", "VRC", "VRS", "VRT":
typ = asm.TypeVecReg
- case "SPR", "DCRN", "BHRBE", "TBR", "SR", "TMR", "PMRN": // Note: if you add to this list and the register field needs special handling, add it to switch statement below
+ case "SPR", "TBR":
typ = asm.TypeSpReg
- switch opr {
- case "DCRN":
- opr = "DCR"
- }
if n := strings.ToLower(opr); n != opr && args.Find(n) >= 0 {
opr = n // spr[5:9] || spr[0:4]
}
