|author||Paul E. Murphy <email@example.com>||Tue Dec 15 12:07:22 2020 -0600|
|committer||Lynn Boger <firstname.lastname@example.org>||Tue Apr 27 11:49:10 2021 +0000|
ppc64asm,ppc64map: enable prefixed insn decoding support ISA 3.1 introduces prefixed instructions. These are 64b instructions which look like 2 consecutive instructions. These allow 34 bit constant displancements and PC-relative addressing. When decoded into an Inst structure, we place the prefix inside the Enc field. The prefix opcode is unique, and thus cannot be confused with any existing ISA 3.1 instruction. The second instruction word (the "suffix") is placed into a new field named SuffixEnc. Rework the decoder table to use 64 bit instruction sizes, and shift the regular instructions into the upper 32 bits. Likewise, extend bitfield parsing to support 2 words and aggregate values beyond 32 bits (prefixed add and load generate 34 bit constants/displacements). Likewise, support nop extended mnemonic. These show up when fixing prefixed instructions to avoid crossing a 64B boundary. This happens in the generated decoding test cases. Likewise, handle pcrel and prefixed load address extended mnemonics to match objdump. Finally, fix some broken documentation propagated from the parser generation. YMSK should only be the upper two bits of the field described as 4 bits. These fixups have been backported to the ISA parser tool. Change-Id: I21e311f93014cf176f3f6b155849a7359af54763 Reviewed-on: https://go-review.googlesource.com/c/arch/+/307353 Run-TryBot: Paul Murphy <email@example.com> TryBot-Result: Go Bot <firstname.lastname@example.org> Reviewed-by: Carlos Eduardo Seo <email@example.com> Reviewed-by: Lynn Boger <firstname.lastname@example.org> Trust: Carlos Eduardo Seo <email@example.com>
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