riscv64: fix and update decoding of MOVD and MOVF
Change https://go-review.googlesource.com/c/go/+/703216 enhances
MOVD and MOVF so that they can be used to initialise a floating
point register to 0.0 and also to copy the binary representations
of floating point values between integer and floating point registers.
We update the riscv64 plan9 disassembler to recognise these cases
and output the appropriate MOVD/MOVF instructions.
We also fix a bug in the plan9 decoder which results in the
arguments for the MOVD and MOVF instructions that represent loads
and stores being output in the wrong order.
Change-Id: I5c3561437f5a0c936767497de6e22c976ce17cff
Reviewed-on: https://go-review.googlesource.com/c/arch/+/704195
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
diff --git a/riscv64/riscv64asm/plan9x.go b/riscv64/riscv64asm/plan9x.go
index f8af9ad..b68deb3 100644
--- a/riscv64/riscv64asm/plan9x.go
+++ b/riscv64/riscv64asm/plan9x.go
@@ -188,6 +188,22 @@
FNMSUB_D, FNMSUB_H, FNMSUB_Q, FNMSUB_S:
args[1], args[3] = args[3], args[1]
+ case FMV_W_X:
+ if inst.Args[1].(Reg) == X0 {
+ args[1] = "$(0.0)"
+ }
+ fallthrough
+ case FMV_X_W:
+ op = "MOVF"
+
+ case FMV_D_X:
+ if inst.Args[1].(Reg) == X0 {
+ args[1] = "$(0.0)"
+ }
+ fallthrough
+ case FMV_X_D:
+ op = "MOVD"
+
case FSGNJ_S:
if inst.Args[2] == inst.Args[1] {
op = "MOVF"
@@ -259,13 +275,13 @@
case FLW, FSW:
op = "MOVF"
- if inst.Op == FLW {
+ if inst.Op == FSW {
args[0], args[1] = args[1], args[0]
}
case FLD, FSD:
op = "MOVD"
- if inst.Op == FLD {
+ if inst.Op == FSD {
args[0], args[1] = args[1], args[0]
}
diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt
index 8131764..59022cd 100644
--- a/riscv64/riscv64asm/testdata/plan9cases.txt
+++ b/riscv64/riscv64asm/testdata/plan9cases.txt
@@ -163,7 +163,7 @@
d32210a4| FEQH F1, F0, X5
d32210a6| FEQQ F1, F0, X5
d32210a0| FEQS F1, F0, X5
-07b0f27f| MOVD F0, 2047(X5)
+07b0f27f| MOVD 2047(X5), F0
d30210a2| FLED F1, F0, X5
d30210a4| FLEH F1, F0, X5
d30210a6| FLEQ F1, F0, X5
@@ -174,7 +174,10 @@
d31210a4| FLTH F1, F0, X5
d31210a6| FLTQ F1, F0, X5
d31210a0| FLTS F1, F0, X5
-07a0f27f| MOVF F0, 2047(X5)
+07a0f27f| MOVF 2047(X5), F0
+d38100f0| MOVF X1, F3
+d38001e0| MOVF F3, X1
+d30100f0| MOVF $(0.0), F3
43f0201a| FMADDD F1, F2, F3, F0
43f0201c| FMADDH F1, F2, F3, F0
43f0201e| FMADDQ F1, F2, F3, F0
@@ -195,11 +198,8 @@
53f02014| FMULH F2, F1, F0
53f02016| FMULQ F2, F1, F0
53f02010| FMULS F2, F1, F0
-538002f2| FMVDX X5, F0
538002f4| FMVHX X5, F0
-d30200e2| FMVXD F0, X5
d30200e4| FMVXH F0, X5
-d30200e0| FMVXW F0, X5
4ff0201a| FNMADDD F1, F2, F3, F0
4ff0201c| FNMADDH F1, F2, F3, F0
4ff0201e| FNMADDQ F1, F2, F3, F0
@@ -208,7 +208,10 @@
4bf0201c| FNMSUBH F1, F2, F3, F0
4bf0201e| FNMSUBQ F1, F2, F3, F0
4bf02018| FNMSUBS F1, F2, F3, F0
-a7bf027e| MOVD 2047(X5), F0
+a7bf027e| MOVD F0, 2047(X5)
+d38001e2| MOVD F3, X1
+d38100f2| MOVD X1, F3
+d30100f2| MOVD $(0.0), F3
53902022| FSGNJND F2, F1, F0
53902024| FSGNJNH F2, F1, F0
53902026| FSGNJNQ F2, F1, F0
@@ -231,7 +234,7 @@
53f0200c| FSUBH F2, F1, F0
53f0200e| FSUBQ F2, F1, F0
53f02008| FSUBS F2, F1, F0
-a7af027e| MOVF 2047(X5), F0
+a7af027e| MOVF F0, 2047(X5)
6ff0dfcb| JMP -209(PC)
eff09fcb| CALL -210(PC)
eff25fcb| JAL X5, -211(PC)
