arm: move rsc.io/arm here
This code was reviewed on its way into rsc.io/arm:
https://codereview.appspot.com/104770047
https://codereview.appspot.com/106720044
https://codereview.appspot.com/101820043
https://codereview.appspot.com/101800044
https://codereview.appspot.com/101740045
https://codereview.appspot.com/93600044
Change-Id: I9076e024aa9a433bedfa2760315dc056bf5c66fc
Reviewed-on: https://go-review.googlesource.com/13971
Reviewed-by: Ian Lance Taylor <iant@golang.org>
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
diff --git a/arm/arm.csv b/arm/arm.csv
new file mode 100644
index 0000000..c40ade9
--- /dev/null
+++ b/arm/arm.csv
@@ -0,0 +1,454 @@
+# arm instruction description version 0.01.
+# https://golang.org/x/arch/arm
+#
+# This file contains a block of comment lines, each beginning with #,
+# followed by entries in CSV format. All the # comments are at the top
+# of the file, so a reader can skip past the comments and hand the
+# rest of the file to a standard CSV reader.
+#
+# Each line in the CSV section contains 5 fields:
+#
+# mask value mnemonic encoding tags
+#
+# The mnemonic and encoding correspond to the notation used in the
+# ARM Architecture Reference Manual.
+#
+# A particular instruction word w matches a line if w&mask == value.
+# The mask and value are computed from a combination of the encodings
+# and the additional pseudocode restrictions given in the manual
+# for each instruction.
+#
+# Multiple lines may match a particular instruction word.
+# The tags specify which line takes priority in these cases,
+# as a partial order. Eventually the plan is that a tag of the form
+# 'name:x' marks a line with the name x, and a tag of the form
+# 'except:x' says that the line on which the tag appears is of lower
+# priority than the ones marked with name x.
+# For now, however, a tag of the form 'SEE XXX' is taken from the
+# manual and is like 'except:x' but without a rigorous resolution for
+# the x. So far we've been able to just sort instructions into two classes:
+# those with SEE and those without.
+#
+# The tag 'pseudo' indicates that this instruction is an alternate name
+# for another encoding and should be ignored during disassembly.
+#
+# This file was generated by a program reading the PDF version of
+# the manual, but it was then hand edited to make corrections.
+# The eventual plan is for the generator to write the
+# file directly, using the PDF and a list of modifications, but
+# no hand editing. Then, when a new version of the manual comes out,
+# updating the list should be as easy as downloading the new PDF
+# and invoking the generator. However, we are not there yet.
+#
+"0x0fe00000","0x02a00000","ADC{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00a00010","ADC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00a00000","ADC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fe00000","0x02800000","ADD{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12","SEE ADR SEE ADD (SP plus immediate) SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00800010","ADD{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00800000","ADD{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions SEE ADD (SP plus register)"
+"0x0fef0000","0x028d0000","ADD{S}<c> <Rd>,SP,#<const>","cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fef0010","0x008d0000","ADD{S}<c> <Rd>,SP,<Rm>{,<shift>}","cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fff0000","0x028f0000","ADR<c> <Rd>,<label+12>","cond:4|0|0|1|0|1|0|0|0|1|1|1|1|Rd:4|imm12:12","pseudo"
+"0x0fff0000","0x024f0000","ADR<c> <Rd>,<label-12>","cond:4|0|0|1|0|0|1|0|0|1|1|1|1|Rd:4|imm12:12","pseudo"
+"0x0fe00000","0x02000000","AND{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00000010","AND{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00000000","AND{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fef0070","0x01a00040","ASR{S}<c> <Rd>,<Rm>,#<imm5_32>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4",""
+"0x0fef00f0","0x01a00050","ASR{S}<c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4",""
+"0x0f000000","0x0a000000","B<c> <label24>","cond:4|1|0|1|0|imm24:24",""
+"0x0fe0007f","0x07c0001f","BFC<c> <Rd>,#<lsb>,#<width>","cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1",""
+"0x0fe00070","0x07c00010","BFI<c> <Rd>,<Rn>,#<lsb>,#<width>","cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4","SEE BFC"
+"0x0fe00000","0x03c00000","BIC{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x01c00010","BIC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x01c00000","BIC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0ff000f0","0x01200070","BKPT<c> #<imm12+4>","cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4",""
+"0x0f000000","0x0b000000","BL<c> <label24>","cond:4|1|0|1|1|imm24:24",""
+"0xfe000000","0xfa000000","BLX <label24H>","1|1|1|1|1|0|1|H|imm24:24",""
+"0x0ffffff0","0x012fff30","BLX<c> <Rm>","cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0ffffff0","0x012fff10","BX<c> <Rm>","cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ffffff0","0x012fff20","BXJ<c> <Rm>","cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4",""
+"0xffffffff","0xf57ff01f","CLREX","1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1)",""
+"0x0fff0ff0","0x016f0f10","CLZ<c> <Rd>,<Rm>","cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff0f000","0x03700000","CMN<c> <Rn>,#<const>","cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12",""
+"0x0ff0f090","0x01700010","CMN<c> <Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4",""
+"0x0ff0f010","0x01700000","CMN<c> <Rn>,<Rm>{,<shift>}","cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4",""
+"0x0ff0f000","0x03500000","CMP<c> <Rn>,#<const>","cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12",""
+"0x0ff0f090","0x01500010","CMP<c> <Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4",""
+"0x0ff0f010","0x01500000","CMP<c> <Rn>,<Rm>{,<shift>}","cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4",""
+"0x0ffffff0","0x0320f0f0","DBG<c> #<option>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4",""
+"0xfffffff0","0xf57ff050","DMB #<option>","1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4",""
+"0xfffffff0","0xf57ff040","DSB #<option>","1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4",""
+"0x0fe00000","0x02200000","EOR{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00200010","EOR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00200000","EOR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0xfffffff0","0xf57ff060","ISB #<option>","1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4",""
+"0x0fd00000","0x08900000","LDM<c> <Rn>{!},<registers>","cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16","SEE POP"
+"0x0fd00000","0x08100000","LDMDA<c> <Rn>{!},<registers>","cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16",""
+"0x0fd00000","0x09100000","LDMDB<c> <Rn>{!},<registers>","cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16",""
+"0x0fd00000","0x09900000","LDMIB<c> <Rn>{!},<registers>","cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16",""
+"0x0f7f0000","0x051f0000","LDR<c> <Rt>,<label+/-12>","cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12",""
+"0x0e500010","0x06100000","LDR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!}","cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4","SEE LDRT"
+"0x0e500000","0x04100000","LDR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!}","cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12","SEE LDR (literal) SEE LDRT SEE POP"
+"0x0f7f0000","0x055f0000","LDRB<c> <Rt>,<label+/-12>","cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12",""
+"0x0e500010","0x06500000","LDRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!}","cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4","SEE LDRBT"
+"0x0e500000","0x04500000","LDRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!}","cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12","SEE LDRB (literal) SEE LDRBT"
+"0x0f700000","0x04700000","LDRBT<c> <Rt>,[<Rn>],#+/-<imm12>","cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12",""
+"0x0f700010","0x06700000","LDRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}","cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4",""
+"0x0f7f10f0","0x014f00d0","LDRD<c> <Rt1>,<Rt2>,<label+/-4+4>","cond:4|0|0|0|(1)|U|1|(0)|0|1|1|1|1|Rt:4|imm4H:4|1|1|0|1|imm4L:4","pseudo"
+"0x0e500ff0","0x000000d0","LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!}","cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4",""
+"0x0e5000f0","0x004000d0","LDRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!}","cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4","SEE LDRD (literal)"
+"0x0ff00fff","0x01900f9f","LDREX<c> <Rt>,[<Rn>]","cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)",""
+"0x0ff00fff","0x01d00f9f","LDREXB<c> <Rt>, [<Rn>]","cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)",""
+"0x0ff00fff","0x01b00f9f","LDREXD<c> <Rt1>,<Rt2>,[<Rn>]","cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)",""
+"0x0ff00fff","0x01f00f9f","LDREXH<c> <Rt>, [<Rn>]","cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)",""
+"0x0f7f00f0","0x015f00b0","LDRH<c> <Rt>,<label+/-4+4>","cond:4|0|0|0|1|U|1|0|1|1|1|1|1|Rt:4|imm4H:4|1|0|1|1|imm4L:4","pseudo"
+"0x0e500ff0","0x001000b0","LDRH<c> <Rt>,[<Rn>,+/-<Rm>]{!}","cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4","SEE LDRHT"
+"0x0e5000f0","0x005000b0","LDRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!}","cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4","SEE LDRH literal SEE LDRHT"
+"0x0f7000f0","0x007000b0","LDRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>}","cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4",""
+"0x0f700ff0","0x003000b0","LDRHT<c> <Rt>, [<Rn>], +/-<Rm>","cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4",""
+"0x0f7f00f0","0x015f00d0","LDRSB<c> <Rt>,<label+/-4+4>","cond:4|0|0|0|1|U|1|0|1|1|1|1|1|Rt:4|imm4H:4|1|1|0|1|imm4L:4","pseudo"
+"0x0e500ff0","0x001000d0","LDRSB<c> <Rt>,[<Rn>,+/-<Rm>]{!}","cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4","SEE LDRSBT"
+"0x0e5000f0","0x005000d0","LDRSB<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!}","cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4","SEE LDRSB literal SEE LDRSBT"
+"0x0f7000f0","0x007000d0","LDRSBT<c> <Rt>, [<Rn>] {,#+/-<imm8>}","cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4",""
+"0x0f700ff0","0x003000d0","LDRSBT<c> <Rt>, [<Rn>], +/-<Rm>","cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4",""
+"0x0f7f00f0","0x015f00f0","LDRSH<c> <Rt>,<label+/-4+4>","cond:4|0|0|0|1|U|1|0|1|1|1|1|1|Rt:4|imm4H:4|1|1|1|1|imm4L:4","pseudo"
+"0x0e500ff0","0x001000f0","LDRSH<c> <Rt>,[<Rn>,+/-<Rm>]{!}","cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4","SEE LDRSHT"
+"0x0e5000f0","0x005000f0","LDRSH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!}","cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4","SEE LDRSH literal SEE LDRSHT"
+"0x0f7000f0","0x007000f0","LDRSHT<c> <Rt>, [<Rn>] {,#+/-<imm8>}","cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4",""
+"0x0f700ff0","0x003000f0","LDRSHT<c> <Rt>, [<Rn>], +/-<Rm>","cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4",""
+"0x0f700000","0x04300000","LDRT<c> <Rt>, [<Rn>] {,#+/-<imm12>}","cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12",""
+"0x0f700010","0x06300000","LDRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}","cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4",""
+"0x0fef0070","0x01a00000","LSL{S}<c> <Rd>,<Rm>,#<imm5_nz>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4","SEE MOV register"
+"0x0fef00f0","0x01a00010","LSL{S}<c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4",""
+"0x0fef0070","0x01a00020","LSR{S}<c> <Rd>,<Rm>,#<imm5_32>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4",""
+"0x0fef00f0","0x01a00030","LSR{S}<c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4",""
+"0x0fe000f0","0x00200090","MLA{S}<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0ff000f0","0x00600090","MLS<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0ff00000","0x03400000","MOVT<c> <Rd>,#<imm12+4>","cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12",""
+"0x0ff00000","0x03000000","MOVW<c> <Rd>,#<imm12+4>","cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12",""
+"0x0fef0000","0x03a00000","MOV{S}<c> <Rd>,#<const>","cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fef0ff0","0x01a00000","MOV{S}<c> <Rd>,<Rm>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fff0fff","0x010f0000","MRS<c> <Rd>,APSR","cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0)",""
+"0x0fe0f0f0","0x00000090","MUL{S}<c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4",""
+"0x0fef0000","0x03e00000","MVN{S}<c> <Rd>,#<const>","cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fef0090","0x01e00010","MVN{S}<c> <Rd>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fef0010","0x01e00000","MVN{S}<c> <Rd>,<Rm>{,<shift>}","cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fffffff","0x0320f000","NOP<c>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0",""
+"0x0fe00000","0x03800000","ORR{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x01800010","ORR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x01800000","ORR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0ff00030","0x06800010","PKH<BT,TB><c> <Rd>,<Rn>,<Rm>{,LSL #<imm5>}","cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4",""
+"0xff7ff000","0xf55ff000","PLD <label+/-12>","1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12",""
+"0xff30f000","0xf510f000","PLD{W} [<Rn>,#+/-<imm12>]","1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12","SEE PLD (literal)"
+"0xff30f010","0xf710f000","PLD{W} [<Rn>,+/-<Rm>{, <shift>}]","1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4",""
+"0xff70f000","0xf450f000","PLI [<Rn>,#+/-<imm12>]","1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12",""
+"0xff70f010","0xf650f000","PLI [<Rn>,+/-<Rm>{, <shift>}]","1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4",""
+"0x0fff0000","0x08bd0000","POP<c> <registers2>","cond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16",""
+"0x0fff0fff","0x049d0004","POP<c> <registers1>","cond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0",""
+"0x0fff0000","0x092d0000","PUSH<c> <registers2>","cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16",""
+"0x0fff0fff","0x052d0004","PUSH<c> <registers1>","cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0",""
+"0x0ff00ff0","0x06200f10","QADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06200f90","QADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
+"0x0ff00ff0","0x01000050","QADD<c> <Rd>,<Rm>,<Rn>","cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06200f30","QASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0ff00ff0","0x01400050","QDADD<c> <Rd>,<Rm>,<Rn>","cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x01600050","QDSUB<c> <Rd>,<Rm>,<Rn>","cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06200f50","QSAX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06200f70","QSUB16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4",""
+"0x0ff00ff0","0x06200ff0","QSUB8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4",""
+"0x0ff00ff0","0x01200050","QSUB<c> <Rd>,<Rm>,<Rn>","cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4",""
+"0x0fff0ff0","0x06ff0f30","RBIT<c> <Rd>,<Rm>","cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0fff0ff0","0x06bf0fb0","REV16<c> <Rd>,<Rm>","cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4",""
+"0x0fff0ff0","0x06bf0f30","REV<c> <Rd>,<Rm>","cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0fff0ff0","0x06ff0fb0","REVSH<c> <Rd>,<Rm>","cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4",""
+"0x0fef0070","0x01a00060","ROR{S}<c> <Rd>,<Rm>,#<imm5>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4","SEE RRX"
+"0x0fef00f0","0x01a00070","ROR{S}<c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4",""
+"0x0fef0ff0","0x01a00060","RRX{S}<c> <Rd>,<Rm>","cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4",""
+"0x0fe00000","0x02600000","RSB{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00600010","RSB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00600000","RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fe00000","0x02e00000","RSC{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00e00010","RSC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00e00000","RSC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0ff00ff0","0x06100f10","SADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06100f90","SADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06100f30","SASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0fe00000","0x02c00000","SBC{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00c00010","SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00c00000","SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0fe00070","0x07a00050","SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1>","cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4",""
+"0x0ff00ff0","0x06800fb0","SEL<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4",""
+"0xfffffdff","0xf1010000","SETEND <endian_specifier>","1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)",""
+"0x0fffffff","0x0320f004","SEV<c>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0",""
+"0x0ff00ff0","0x06300f10","SHADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06300f90","SHADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06300f30","SHASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0ff00ff0","0x06300f50","SHSAX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06300f70","SHSUB16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4",""
+"0x0ff00ff0","0x06300ff0","SHSUB8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4",""
+"0x0ff00090","0x01000080","SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4",""
+"0x0ff000d0","0x07000010","SMLAD{X}<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4","SEE SMUAD"
+"0x0ff00090","0x01400080","SMLAL<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4",""
+"0x0ff000d0","0x07400010","SMLALD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4",""
+"0x0fe000f0","0x00e00090","SMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0ff000b0","0x01200080","SMLAW<y><c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4",""
+"0x0ff000d0","0x07000050","SMLSD{X}<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4","SEE SMUSD"
+"0x0ff000d0","0x07400050","SMLSLD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4",""
+"0x0ff000d0","0x07500010","SMMLA{R}<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4","SEE SMMUL"
+"0x0ff000d0","0x075000d0","SMMLS{R}<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4",""
+"0x0ff0f0d0","0x0750f010","SMMUL{R}<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4",""
+"0x0ff0f0d0","0x0700f010","SMUAD{X}<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4",""
+"0x0ff0f090","0x01600080","SMUL<x><y><c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4",""
+"0x0fe000f0","0x00c00090","SMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0ff0f0b0","0x012000a0","SMULW<y><c> <Rd>,<Rn>,<Rm>","cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4",""
+"0x0ff0f0d0","0x0700f050","SMUSD{X}<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4",""
+"0x0ff00ff0","0x06a00f30","SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn>","cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4",""
+"0x0fe00030","0x06a00010","SSAT<c> <Rd>,#<sat_imm5m1>,<Rn>{,<shift>}","cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4",""
+"0x0ff00ff0","0x06100f50","SSAX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06100f70","SSUB16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4",""
+"0x0ff00ff0","0x06100ff0","SSUB8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4",""
+"0x0fd00000","0x08800000","STM<c> <Rn>{!},<registers>","cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16",""
+"0x0fd00000","0x08000000","STMDA<c> <Rn>{!},<registers>","cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16",""
+"0x0fd00000","0x09000000","STMDB<c> <Rn>{!},<registers>","cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16","SEE PUSH"
+"0x0fd00000","0x09800000","STMIB<c> <Rn>{!},<registers>","cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16",""
+"0x0e500018","0x06000000","STR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!}","cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4","SEE STRT"
+"0x0e500000","0x04000000","STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!}","cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12","SEE STRT SEE PUSH"
+"0x0e500010","0x06400000","STRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!}","cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4","SEE STRBT"
+"0x0e500000","0x04400000","STRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!}","cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12","SEE STRBT"
+"0x0f700000","0x04600000","STRBT<c> <Rt>,[<Rn>],#+/-<imm12>","cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12",""
+"0x0f700010","0x06600000","STRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}","cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4",""
+"0x0e500ff0","0x000000f0","STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!}","cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4",""
+"0x0e5000f0","0x004000f0","STRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!}","cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4",""
+"0x0ff00ff0","0x01800f90","STREX<c> <Rd>,<Rt>,[<Rn>]","cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4",""
+"0x0ff00ff0","0x01c00f90","STREXB<c> <Rd>,<Rt>,[<Rn>]","cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4",""
+"0x0ff00ff0","0x01a00f90","STREXD<c> <Rd>,<Rt1>,<Rt2>,[<Rn>]","cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4",""
+"0x0ff00ff0","0x01e00f90","STREXH<c> <Rd>,<Rt>,[<Rn>]","cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4",""
+"0x0e500ff0","0x000000b0","STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!}","cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4","SEE STRHT"
+"0x0e5000f0","0x004000b0","STRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!}","cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4","SEE STRHT"
+"0x0f7000f0","0x006000b0","STRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>}","cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4",""
+"0x0f700ff0","0x002000b0","STRHT<c> <Rt>, [<Rn>], +/-<Rm>","cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4",""
+"0x0f700000","0x04200000","STRT<c> <Rt>, [<Rn>] {,#+/-<imm12>}","cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12",""
+"0x0f700010","0x06200000","STRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}","cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4",""
+"0x0fe00000","0x02400000","SUB{S}<c> <Rd>,<Rn>,#<const>","cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12","SEE ADR SEE SUB (SP minus immediate) SEE SUBS PC, LR and related instructions"
+"0x0fe00090","0x00400010","SUB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
+"0x0fe00010","0x00400000","SUB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions SEE SUB (SP minus register)"
+"0x0fef0000","0x024d0000","SUB{S}<c> <Rd>,SP,#<const>","cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12","SEE SUBS PC, LR and related instructions"
+"0x0fef0010","0x004d0000","SUB{S}<c> <Rd>,SP,<Rm>{,<shift>}","cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
+"0x0f000000","0x0f000000","SVC<c> #<imm24>","cond:4|1|1|1|1|imm24:24",""
+"0x0fb00ff0","0x01000090","SWP{B}<c> <Rt>,<Rm>,[<Rn>]","cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4",""
+"0x0ff003f0","0x06800070","SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4","SEE SXTB16"
+"0x0ff003f0","0x06a00070","SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4","SEE SXTB"
+"0x0ff003f0","0x06b00070","SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4","SEE SXTH"
+"0x0fff03f0","0x068f0070","SXTB16<c> <Rd>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4",""
+"0x0fff03f0","0x06af0070","SXTB<c> <Rd>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4",""
+"0x0fff03f0","0x06bf0070","SXTH<c> <Rd>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4",""
+"0x0ff0f000","0x03300000","TEQ<c> <Rn>,#<const>","cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12",""
+"0x0ff0f090","0x01300010","TEQ<c> <Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4",""
+"0x0ff0f010","0x01300000","TEQ<c> <Rn>,<Rm>{,<shift>}","cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4",""
+"0x0ff0f000","0x03100000","TST<c> <Rn>,#<const>","cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12",""
+"0x0ff0f090","0x01100010","TST<c> <Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4",""
+"0x0ff0f010","0x01100000","TST<c> <Rn>,<Rm>{,<shift>}","cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4",""
+"0x0ff00ff0","0x06500f10","UADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06500f90","UADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06500f30","UASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0fe00070","0x07e00050","UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1>","cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4",""
+"0x0ff00ff0","0x06700f10","UHADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06700f90","UHADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06700f30","UHASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0ff00ff0","0x06700f50","UHSAX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06700f70","UHSUB16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4",""
+"0x0ff00ff0","0x06700ff0","UHSUB8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4",""
+"0x0ff000f0","0x00400090","UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0fe000f0","0x00a00090","UMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0fe000f0","0x00800090","UMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>","cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4",""
+"0x0ff00ff0","0x06600f10","UQADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06600f90","UQADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
+"0x0ff00ff0","0x06600f30","UQASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
+"0x0ff00ff0","0x06600f50","UQSAX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06600f70","UQSUB16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4",""
+"0x0ff00ff0","0x06600ff0","UQSUB8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4",""
+"0x0ff0f0f0","0x0780f010","USAD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4",""
+"0x0ff000f0","0x07800010","USADA8<c> <Rd>,<Rn>,<Rm>,<Ra>","cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4","SEE USAD8"
+"0x0ff00ff0","0x06e00f30","USAT16<c> <Rd>,#<sat_imm4>,<Rn>","cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4",""
+"0x0fe00030","0x06e00010","USAT<c> <Rd>,#<sat_imm5>,<Rn>{,<shift>}","cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4",""
+"0x0ff00ff0","0x06500f50","USAX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4",""
+"0x0ff00ff0","0x06500f70","USUB16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4",""
+"0x0ff00ff0","0x06500ff0","USUB8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4",""
+"0x0ff003f0","0x06c00070","UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4","SEE UXTB16"
+"0x0ff003f0","0x06e00070","UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4","SEE UXTB"
+"0x0ff003f0","0x06f00070","UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4","SEE UXTH"
+"0x0fff03f0","0x06cf0070","UXTB16<c> <Rd>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4",""
+"0x0fff03f0","0x06ef0070","UXTB<c> <Rd>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4",""
+"0x0fff03f0","0x06ff0070","UXTH<c> <Rd>,<Rm>{,<rotation>}","cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4",""
+"0xff800f10","0xf3000110","V<BIF,BIT,BSL> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|op:2|Vn:4|Vd:4|0|0|0|1|N|Q|M|1|Vm:4","SEE VEOR"
+"0xffb00c10","0xf3b00800","V<TBL,TBX>.8 <Dd>, <list_len>, <Dm>","1|1|1|1|0|0|1|1|1|D|1|1|Vn:4|Vd:4|1|0|len:2|N|op|M|0|Vm:4",""
+"0xfe800a50","0xf2800040","V<MLA,MLS>.<dt> <Qd>, <Qn>, <Dm[x]>","1|1|1|1|0|0|1|Q|1|D|size:2|Vn:4|Vd:4|0|op|0|F|N|1|M|0|Vm:4","SEE “Related encodings”"
+"0xfe800f00","0xf2000600","V<MAX,MIN>.<dt> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|1|0|N|Q|M|op|Vm:4",""
+"0xfe800f10","0xf2000900","V<MLA,MLS>.<dt> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|op|0|D|size:2|Vn:4|Vd:4|1|0|0|1|N|Q|M|0|Vm:4",""
+"0xff800f10","0xf2000d10","V<MLA,MLS>.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|op|sz|Vn:4|Vd:4|1|1|0|1|N|Q|M|1|Vm:4",""
+"0xff800f10","0xf2000f00","V<MAX,MIN>.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|op|sz|Vn:4|Vd:4|1|1|1|1|N|Q|M|0|Vm:4",""
+"0xff800f10","0xf3000e10","VAC<GE,GT>.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|op|sz|Vn:4|Vd:4|1|1|1|0|N|Q|M|1|Vm:4",""
+"0x0fb00e10","0x0e000a00","V<MLA,MLS><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|0|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4","vfp"
+"0xfe801d50","0xf2800800","V<MLA,MLS>L.<dt> <Qd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|1|0|op|0|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xfe801b50","0xf2800240","V<MLA,MLS>L.<dt> <Qd>, <Dn>, <Dm[x]>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|0|op|1|0|N|1|M|0|Vm:4","SEE “Related encodings”"
+"0xfe800f10","0xf2000710","VABA.<dt_Usize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|1|1|N|Q|M|1|Vm:4",""
+"0xfe801f50","0xf2800500","VABAL.<dt_Usize> <Qd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|0|1|0|1|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xfe800f10","0xf2000700","VABD.<dt_Usize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|1|1|N|Q|M|0|Vm:4",""
+"0xffa00f10","0xf3200d00","VABD.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|1|sz|Vn:4|Vd:4|1|1|0|1|N|Q|M|0|Vm:4",""
+"0xfe801f50","0xf2800700","VABDL.<dt_Usize> <Qd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|0|1|1|1|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xffb30b90","0xf3b10300","VABS.<dt_Fsize> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|1|1|0|Q|M|0|Vm:4",""
+"0x0fbf0ed0","0x0eb00ac0","VABS<c>.F<32,64> <Sd,Dd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|1|1|M|0|Vm:4","vfp"
+"0xff800f10","0xf2000800","VADD.<dt_Isize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|size:2|Vn:4|Vd:4|1|0|0|0|N|Q|M|0|Vm:4",""
+"0xffa00f10","0xf2000d00","VADD.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|0|sz|Vn:4|Vd:4|1|1|0|1|N|Q|M|0|Vm:4",""
+"0x0fb00e50","0x0e300a00","VADD<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4","vfp"
+"0xff810f51","0xf2800400","VADDHN.<dt_Isize> <Dd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|1|D|size:2|Vn:4|Vd:4|0|1|0|0|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xfe801e50","0xf2800000","VADDL.<dt_Usize> <Qd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|0|0|0|op|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xffb00f10","0xf2000110","VAND <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|0|0|Vn:4|Vd:4|0|0|0|1|N|Q|M|1|Vm:4",""
+"0xffb00f10","0xf2100110","VBIC <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|0|1|Vn:4|Vd:4|0|0|0|1|N|Q|M|1|Vm:4",""
+"0xfeb800b0","0xf2800030","VBIC.<dt_simd> <Qd>, #<imm_simd1>","1|1|1|1|0|0|1|i|1|D|0|0|0|imm3:3|Vd:4|cmode:4|0|Q|1|1|imm4:4","SEE “Related encodings”"
+"0xffb30b90","0xf3b10100","VCEQ.<dt_Fsize> <Qd>, <Qm>, #0","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|0|1|0|Q|M|0|Vm:4",""
+"0xff800f10","0xf3000810","VCEQ.<dt_Isize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|size:2|Vn:4|Vd:4|1|0|0|0|N|Q|M|1|Vm:4",""
+"0xffa00f10","0xf2000e00","VCEQ.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|0|sz|Vn:4|Vd:4|1|1|1|0|N|Q|M|0|Vm:4",""
+"0xffb30b90","0xf3b10080","VCGE.<dt_Fsize> <Qd>, <Qm>, #0","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|0|0|1|Q|M|0|Vm:4",""
+"0xfe800f10","0xf2000310","VCGE.<dt_Isize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|0|1|1|N|Q|M|1|Vm:4",""
+"0xffa00f10","0xf3000e00","VCGE.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|0|sz|Vn:4|Vd:4|1|1|1|0|N|Q|M|0|Vm:4",""
+"0xffb30b90","0xf3b10000","VCGT.<dt_Fsize> <Qd>, <Qm>, #0","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|0|0|0|Q|M|0|Vm:4",""
+"0xfe800f10","0xf2000300","VCGT.<dt_Isize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|0|1|1|N|Q|M|0|Vm:4",""
+"0xffa00f10","0xf3200e00","VCGT.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|1|sz|Vn:4|Vd:4|1|1|1|0|N|Q|M|0|Vm:4",""
+"0xffb30b90","0xf3b10180","VCLE.<dt_Fsize> <Qd>, <Qm>, #0","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|0|1|1|Q|M|0|Vm:4",""
+"0xffb30f90","0xf3b00400","VCLS.<dt_Isize> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|0|0|0|Q|M|0|Vm:4",""
+"0xffb30b90","0xf3b10200","VCLT.<dt_Fsize> <Qd>, <Qm>, #0","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|1|0|0|Q|M|0|Vm:4",""
+"0xffb30f90","0xf3b00480","VCLZ.<dt_Isize> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|0|0|1|Q|M|0|Vm:4",""
+"0x0fbf0e7f","0x0eb50a40","VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0","cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0)","vfp"
+"0x0fbf0e50","0x0eb40a40","VCMP{E}<c>.F<32,64> <Sd,Dd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|0|1|0|0|Vd:4|1|0|1|sz|E|1|M|0|Vm:4","vfp"
+"0xffbf0f90","0xf3b00500","VCNT.8 <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|0|1|0|Q|M|0|Vm:4",""
+"0xffbf0e10","0xf3bb0600","VCVT.<Td>.<Tm_1> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|1|Vd:4|0|1|1|op:2|Q|M|0|Vm:4",""
+"0xfea00e90","0xf2a00e10","VCVT.<Td>.<Tm_2> <Qd>, <Qm>, #<fbits>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|1|1|1|op|0|Q|M|1|Vm:4","SEE “Related encodings”"
+"0x0fbe0e50","0x0eba0a40","VCVT<c>.F<32,64>.FX<S,U><16,32> <Sd,Dd>, <Sd,Dd>, #<fbits>","cond:4|1|1|1|0|1|D|1|1|1|0|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4","vfp"
+"0x0fbe0e50","0x0ebe0a40","VCVT<c>.FX<S,U><16,32>.F<32,64> <Sd,Dd>, <Sd,Dd>, #<fbits>","cond:4|1|1|1|0|1|D|1|1|1|1|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4","vfp"
+"0xffbf0ed0","0xf3b60600","VCVT.F32.F16 <Qd>, <Dm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|1|1|op|0|0|M|0|Vm:4",""
+"0x0fbf0ed0","0x0eb70ac0","VCVT<c>.<F64.F32,F32.F64> <Dd,Sd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|0|1|1|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4","vfp"
+"0x0fbe0f50","0x0eb20a40","VCVT<B,T><c>.<F32.F16,F16.F32> <Sd>, <Sm>","cond:4|1|1|1|0|1|D|1|1|0|0|1|op|Vd:4|1|0|1|0|T|1|M|0|Vm:4","vfp"
+"0x0fbf0e50","0x0eb80a40","VCVT<c>.F<32,64>.<U,S>32 <Sd,Dd>, <Sm>","cond:4|1|1|1|0|1|D|1|1|1|0|0|0|Vd:4|1|0|1|sz|op|1|M|0|Vm:4","vfp"
+"0x0fbe0e50","0x0ebc0a40","VCVT<R,><c>.<U,S>32.F<32,64> <Sd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|1|1|0|signed|Vd:4|1|0|1|sz|op|1|M|0|Vm:4","vfp"
+"0x0fb00e50","0x0e800a00","VDIV<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|1|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4","vfp"
+"0xffb00f90","0xf3b00c00","VDUP.<size_x> <Qd>, <Dm[size_x]>","1|1|1|1|0|0|1|1|1|D|1|1|imm4:4|Vd:4|1|1|0|0|0|Q|M|0|Vm:4",""
+"0x0f900f5f","0x0e800b10","VDUP<c>.<size_be> <Qd>, <Rt>","cond:4|1|1|1|0|1|b|Q|0|Vd:4|Rt:4|1|0|1|1|D|0|e|1|(0)|(0)|(0)|(0)",""
+"0xffb00f10","0xf3000110","VEOR <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|0|0|Vn:4|Vd:4|0|0|0|1|N|Q|M|1|Vm:4",""
+"0xffb00010","0xf2b00000","VEXT.8 <Qd>, <Qn>, <Qm>, #<imm4>","1|1|1|1|0|0|1|0|1|D|1|1|Vn:4|Vd:4|imm4:4|N|Q|M|0|Vm:4",""
+"0xfe800d10","0xf2000000","VH<ADD,SUB> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|0|op|0|N|Q|M|0|Vm:4",""
+"0xffb00200","0xf4200200","VLD1.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|1|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00f00","0xf4a00c00","VLD1.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|1|1|0|0|size:2|T|a|Rm:4",""
+"0xffb00300","0xf4a00000","VLD1.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|size:2|0|0|index_align:4|Rm:4","SEE VLD1 (single element to all lanes)"
+"0xffb00400","0xf4200000","VLD2.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|1|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00f00","0xf4a00d00","VLD2.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|1|1|0|1|size:2|T|a|Rm:4",""
+"0xffb00300","0xf4a00100","VLD2.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|size:2|0|1|index_align:4|Rm:4","SEE VLD2 (single 2-element structure to all lanes)"
+"0xffb00f10","0xf4a00e00","VLD3.<size> <list3t>, [<Rn>]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|1|1|1|0|size:2|T|a|Rm:4",""
+"0xffb00310","0xf4a00200","VLD3.<size> <list3>, [<Rn>]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|size:2|1|0|index_align:4|Rm:4","SEE VLD3 (single 3-element structure to all lanes)"
+"0xffb00e20","0xf4200400","VLD3.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|1|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00f00","0xf4a00f00","VLD4.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|1|1|1|1|size:2|T|a|Rm:4",""
+"0xffb00e00","0xf4200000","VLD4.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|1|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00300","0xf4a00300","VLD4.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|1|0|Rn:4|Vd:4|size:2|1|1|index_align:4|Rm:4","SEE VLD4 (single 4-element structure to all lanes)"
+"0x0f300e00","0x0d100a00","VLDR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}]","cond:4|1|1|0|1|U|D|0|1|Rn:4|Vd:4|1|0|1|sz|imm8:8","vfp"
+"0x0fe00fd0","0x0c400b10","VMOV<c> <Dm>, <Rt>, <Rt2>","cond:4|1|1|0|0|0|1|0|op|Rt2:4|Rt:4|1|0|1|1|0|0|M|1|Vm:4",""
+"0xffb00f10","0xf2200110","VMOV <Qd>, <Qm>","1|1|1|1|0|0|1|0|0|D|1|0|Vm:4|Vd:4|0|0|0|1|M|Q|M|1|Vm:4","SEE VORR (register)"
+"0x0fe00fd0","0x0c400a10","VMOV<c> <Sm>, <Sm1>, <Rt>, <Rt2>","cond:4|1|1|0|0|0|1|0|op|Rt2:4|Rt:4|1|0|1|0|0|0|M|1|Vm:4",""
+"0x0ff00f7f","0x0e000a10","VMOV<c> <Sn>, <Rt>","cond:4|1|1|1|0|0|0|0|0|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0","vfp"
+"0x0ff00f7f","0x0e100a10","VMOV<c> <Rt>, <Sn>","cond:4|1|1|1|0|0|0|0|1|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0","vfp"
+"0xfeb80090","0xf2800010","VMOV.<dt_simd> <Qd>, #<imm_simd>","1|1|1|1|0|0|1|i|1|D|0|0|0|imm3:3|Vd:4|cmode:4|0|Q|op|1|imm4:4","SEE VORR (immediate) SEE “Related encodings”"
+"0x0fd00f7f","0x0e100b10","VMOV<c>.32 <Rt>, <Dn[x]>","cond:4|1|1|1|0|0|0|opc1|1|Vn:4|Rt:4|1|0|1|1|N|0|0|1|0|0|0|0","vfp"
+"0x0fd00f7f","0x0e000b10","VMOV<c>.32 <Dd[x]>, <Rt>","cond:4|1|1|1|0|0|0|opc1|0|Vd:4|Rt:4|1|0|1|1|D|0|0|1|0|0|0|0","vfp"
+"0x0fb00ef0","0x0eb00a00","VMOV<c>.F<32,64> <Sd,Dd>, #<imm_vfp>","cond:4|1|1|1|0|1|D|1|1|imm4H:4|Vd:4|1|0|1|sz|0|0|0|0|imm4L:4","vfp"
+"0x0fbf0ed0","0x0eb00a40","VMOV<c>.F<32,64> <Sd,Dd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|0|1|M|0|Vm:4","vfp"
+"0xfe871fd0","0xf2800a10","VMOVL.<dt> <Qd>, <Dm>","1|1|1|1|0|0|1|U|1|D|imm3:3|0|0|0|Vd:4|1|0|1|0|0|0|M|1|Vm:4","SEE “Related encodings” SEE VSHLL"
+"0xffb30fd1","0xf3b20200","VMOVN.<dt> <Dd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|1|0|0|0|M|0|Vm:4",""
+"0x0fff0fff","0x0ef10a10","VMRS<c> <Rt_nzcv>, FPSCR","cond:4|1|1|1|0|1|1|1|1|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0","vfp"
+"0x0fff0fff","0x0ee10a10","VMSR<c> FPSCR, <Rt>","cond:4|1|1|1|0|1|1|1|0|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0","vfp"
+"0xfe800e50","0xf2800840","VMUL.<dt> <Qd>, <Qn>, <Dm[x]>","1|1|1|1|0|0|1|Q|1|D|size:2|Vn:4|Vd:4|1|0|0|F|N|1|M|0|Vm:4","SEE “Related encodings”"
+"0xfe800f10","0xf2000910","VMUL.<dt> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|op|0|D|size:2|Vn:4|Vd:4|1|0|0|1|N|Q|M|1|Vm:4",""
+"0xffa00f10","0xf3000d10","VMUL.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|0|sz|Vn:4|Vd:4|1|1|0|1|N|Q|M|1|Vm:4",""
+"0x0fb00e50","0x0e200a00","VMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4","vfp"
+"0xfe801d50","0xf2800c00","VMULL.<dt> <Qd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|1|1|op|0|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xfe801f50","0xf2800a40","VMULL.<dt> <Qd>, <Dn>, <Dm[x]>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|1|0|1|0|N|1|M|0|Vm:4","SEE “Related encodings”"
+"0xffbf0f90","0xf3b00580","VMVN <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|0|1|1|Q|M|0|Vm:4",""
+"0xfeb800b0","0xf2800030","VMVN.<dt> <Qd>, #<imm3>","1|1|1|1|0|0|1|i|1|D|0|0|0|imm3:3|Vd:4|cmode:4|0|Q|1|1|imm4:4","SEE “Related encodings”"
+"0xffb30b90","0xf3b10380","VNEG.<dt> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|1|Vd:4|0|F|1|1|1|Q|M|0|Vm:4",""
+"0x0fbf0ed0","0x0eb10a40","VNEG<c>.F<32,64> <Sd,Dd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|0|1|M|0|Vm:4","vfp"
+"0x0fb00e10","0x0e100a00","VN<MLS,MLA><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|0|D|0|1|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4","vfp"
+"0x0fb00e50","0x0e200a40","VNMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4","vfp"
+"0xffb00f10","0xf2300110","VORN <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|1|1|Vn:4|Vd:4|0|0|0|1|N|Q|M|1|Vm:4",""
+"0xffb00f10","0xf2200110","VORR <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|1|0|Vn:4|Vd:4|0|0|0|1|N|Q|M|1|Vm:4","SEE VMOV (register)"
+"0xfeb800b0","0xf2800010","VORR.<dt> <Qd>, #<imm3>","1|1|1|1|0|0|1|i|1|D|0|0|0|imm3:3|Vd:4|cmode:4|0|Q|0|1|imm4:4","SEE VMOV (immediate)"
+"0xfe800f00","0xf2000a00","VP<MIN,MAX>.<dt> <Dd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|1|0|1|0|N|Q|M|op|Vm:4",""
+"0xff800f10","0xf3000f00","VP<MIN,MAX>.F32 <Dd>, <Dn>, <Dm>","1|1|1|1|0|0|1|1|0|D|op|sz|Vn:4|Vd:4|1|1|1|1|N|Q|M|0|Vm:4",""
+"0xffb30f10","0xf3b00600","VPADAL.<dt> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|1|0|op|Q|M|0|Vm:4",""
+"0xff800f10","0xf2000b10","VPADD.<dt> <Dd>, <Dn>, <Dm>","1|1|1|1|0|0|1|0|0|D|size:2|Vn:4|Vd:4|1|0|1|1|N|Q|M|1|Vm:4",""
+"0xffa00f10","0xf3000d00","VPADD.F32 <Dd>, <Dn>, <Dm>","1|1|1|1|0|0|1|1|0|D|0|sz|Vn:4|Vd:4|1|1|0|1|N|Q|M|0|Vm:4",""
+"0xffb30f10","0xf3b00200","VPADDL.<dt> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|0|1|0|op|Q|M|0|Vm:4",""
+"0x0fbf0f00","0x0cbd0a00","VPOP <vlist32>","cond:4|1|1|0|0|1|D|1|1|1|1|0|1|Vd:4|1|0|1|0|imm8:8",""
+"0x0fbf0f00","0x0cbd0b00","VPOP <vlist64>","cond:4|1|1|0|0|1|D|1|1|1|1|0|1|Vd:4|1|0|1|1|imm8:8",""
+"0x0fbf0f00","0x0d2d0a00","VPUSH<c> <vlist32>","cond:4|1|1|0|1|0|D|1|0|1|1|0|1|Vd:4|1|0|1|0|imm8:8",""
+"0x0fbf0f00","0x0d2d0b00","VPUSH<c> <vlist64>","cond:4|1|1|0|1|0|D|1|0|1|1|0|1|Vd:4|1|0|1|1|imm8:8",""
+"0xffb30f90","0xf3b00700","VQABS.<dt> <Qd>,<Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|1|1|0|Q|M|0|Vm:4",""
+"0xfe800f10","0xf2000010","VQADD.<dt> <Qd>,<Qn>,<Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|0|0|0|N|Q|M|1|Vm:4",""
+"0xff801d50","0xf2800900","VQD<MLAL,MLSL>.<dt> <Qd>,<Dn>,<Dm>","1|1|1|1|0|0|1|0|1|D|size:2|Vn:4|Vd:4|1|0|op|1|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xff801b50","0xf2800340","VQD<MLAL,MLSL>.<dt> <Qd>,<Dn>,<Dm[x]>","1|1|1|1|0|0|1|0|1|D|size:2|Vn:4|Vd:4|0|op|1|1|N|1|M|0|Vm:4","SEE “Related encodings”"
+"0xfe800f50","0xf2800c40","VQDMULH.<dt> <Qd>,<Qn>,<Dm[x]>","1|1|1|1|0|0|1|Q|1|D|size:2|Vn:4|Vd:4|1|1|0|0|N|1|M|0|Vm:4",""
+"0xff800f10","0xf2000b00","VQDMULH.<dt> <Qd>,<Qn>,<Qm>","1|1|1|1|0|0|1|0|0|D|size:2|Vn:4|Vd:4|1|0|1|1|N|Q|M|0|Vm:4",""
+"0xff801f50","0xf2800d00","VQDMULL.<dt> <Qd>,<Dn>,<Dm>","1|1|1|1|0|0|1|0|1|D|size:2|Vn:4|Vd:4|1|1|0|1|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xff801f50","0xf2800b40","VQDMULL.<dt> <Qd>,<Dn>,<Dm[x]>","1|1|1|1|0|0|1|0|1|D|size:2|Vn:4|Vd:4|1|0|1|1|N|1|M|0|Vm:4","SEE “Related encodings”"
+"0xffb30f11","0xf3b20200","VQMOV{U}N.<type><size> <Dd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|1|0|op:2|M|0|Vm:4","SEE VMOVN"
+"0xffb30f90","0xf3b00780","VQNEG.<dt> <Qd>,<Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|1|1|1|1|Q|M|0|Vm:4",""
+"0xfe800f50","0xf2800d40","VQRDMULH.<dt> <Qd>,<Qn>,<Dm[x]>","1|1|1|1|0|0|1|Q|1|D|size:2|Vn:4|Vd:4|1|1|0|1|N|1|M|0|Vm:4",""
+"0xff800f10","0xf3000b00","VQRDMULH.<dt> <Qd>,<Qn>,<Qm>","1|1|1|1|0|0|1|1|0|D|size:2|Vn:4|Vd:4|1|0|1|1|N|Q|M|0|Vm:4",""
+"0xfe800f10","0xf2000510","VQRSHL.<type><size> <Qd>,<Qm>,<Qn>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|0|1|N|Q|M|1|Vm:4",""
+"0xfe800ed1","0xf2800850","VQRSHR{U}N.<type><size> <Dd>,<Qm>,#<imm6>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|1|0|0|op|0|1|M|1|Vm:4","SEE “Related encodings” SEE VRSHRN"
+"0xfe800f10","0xf2000410","VQSHL.<type><size> <Qd>,<Qm>,<Qn>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|0|0|N|Q|M|1|Vm:4",""
+"0xfe800e90","0xf2800690","VQSHL{U}.<type><size> <Qd>,<Qm>,#<imm6>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|0|1|1|op|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xfe800ed1","0xf2800810","VQSHR{U}N.<type><size> <Dd>,<Qm>,#<imm6>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|1|0|0|op|0|0|M|1|Vm:4","SEE “Related encodings” SEE VSHRN"
+"0xfe800f10","0xf2000210","VQSUB.<type><size> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|0|1|0|N|Q|M|1|Vm:4",""
+"0xff810f51","0xf3800400","VRADDHN.<dt> <Dd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|1|D|size:2|Vn:4|Vd:4|0|1|0|0|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xffbf0e90","0xf3bb0400","VRECPE.<dt> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|1|Vd:4|0|1|0|F|0|Q|M|0|Vm:4",""
+"0xffa00f10","0xf2000f10","VRECPS.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|0|sz|Vn:4|Vd:4|1|1|1|1|N|Q|M|1|Vm:4",""
+"0xffb30e10","0xf3b00000","VREV<n>.<size> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|0|0|Vd:4|0|0|0|op:2|Q|M|0|Vm:4",""
+"0xfe800f10","0xf2000100","VRHADD <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|0|0|1|N|Q|M|0|Vm:4",""
+"0xfe800f10","0xf2000500","VRSHL.<type><size> <Qd>, <Qm>, <Qn>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|0|1|N|Q|M|0|Vm:4",""
+"0xfe800f90","0xf2800290","VRSHR.<type><size> <Qd>, <Qm>, #<imm6>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|0|0|1|0|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xff800fd1","0xf2800850","VRSHRN.I<size> <Dd>, <Qm>, #<imm6>","1|1|1|1|0|0|1|0|1|D|imm6:6|Vd:4|1|0|0|0|0|1|M|1|Vm:4","SEE “Related encodings”"
+"0xffbf0e90","0xf3bb0480","VRSQRTE.<dt> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|1|Vd:4|0|1|0|F|1|Q|M|0|Vm:4",""
+"0xffa00f10","0xf2200f10","VRSQRTS.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|1|sz|Vn:4|Vd:4|1|1|1|1|N|Q|M|1|Vm:4",""
+"0xfe800f90","0xf2800390","VRSRA.<type><size> <Qd>, <Qm>, #<imm6>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|0|0|1|1|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xff810f51","0xf3800600","VRSUBHN.<dt> <Dd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|1|D|size:2|Vn:4|Vd:4|0|1|1|0|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xff800f90","0xf2800590","VSHL.I<size> <Qd>, <Qm>, #<imm6>","1|1|1|1|0|0|1|0|1|D|imm6:6|Vd:4|0|1|0|1|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xfe800f10","0xf2000400","VSHL.I<size> <Qd>, <Qm>, <Qn>","1|1|1|1|0|0|1|U|0|D|size:2|Vn:4|Vd:4|0|1|0|0|N|Q|M|0|Vm:4",""
+"0xffb31fd0","0xf3b20300","VSHLL.<type><size> <Qd>, <Dm>, #<immsize>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|1|1|0|0|M|0|Vm:4",""
+"0xfe801fd0","0xf2800a10","VSHLL.<type><size> <Qd>, <Dm>, #<imm6>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|1|0|1|0|0|0|M|1|Vm:4","SEE “Related encodings” SEE VMOVL"
+"0xfe800f90","0xf2800090","VSHR.<type><size_vs> <Qd>, <Qm>, #<imm_vs>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|0|0|0|0|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xff800fd1","0xf2800810","VSHRN.I<size_vsn> <Dd>, <Qm>, #<imm_vsn>","1|1|1|1|0|0|1|0|1|D|imm6:6|Vd:4|1|0|0|0|0|0|M|1|Vm:4","SEE “Related encodings”"
+"0xff800f90","0xf3800590","VSLI.<size_vs> <Qd>, <Qm>, #<imm_vs>","1|1|1|1|0|0|1|1|1|D|imm6:6|Vd:4|0|1|0|1|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0x0fbf0ed0","0x0eb10ac0","VSQRT<c>.F<32,64> <Sd,Dd>, <Sm,Dm>","cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4","vfp"
+"0xfe800f90","0xf2800190","VSRA.<type_U><size_vs> <Qd>, <Qm>, #<imm_vs>","1|1|1|1|0|0|1|U|1|D|imm6:6|Vd:4|0|0|0|1|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xff800f90","0xf3800490","VSRI.<size_vs> <Qd>, <Qm>, #<imm_vs>","1|1|1|1|0|0|1|1|1|D|imm6:6|Vd:4|0|1|0|0|L|Q|M|1|Vm:4","SEE “Related encodings”"
+"0xffb00200","0xf4000200","VST1.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|0|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00300","0xf4800000","VST1.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|0|0|Rn:4|Vd:4|size:2|0|0|index_align:4|Rm:4",""
+"0xffb00400","0xf4000000","VST2.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|0|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00300","0xf4800100","VST2.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|0|0|Rn:4|Vd:4|size:2|0|1|index_align:4|Rm:4",""
+"0xffb00300","0xf4800200","VST3.<size> <list4>, [<Rn>]{!}","1|1|1|1|0|1|0|0|1|D|0|0|Rn:4|Vd:4|size:2|1|0|index_align:4|Rm:4",""
+"0xffb00e20","0xf4000400","VST3.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|0|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00e00","0xf4000000","VST4.<size> <list4>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|0|D|0|0|Rn:4|Vd:4|type:4|size:2|align:2|Rm:4","SEE “Related encodings”"
+"0xffb00300","0xf4800300","VST4.<size> <list1>, [<Rn>{@<align>}]{!}","1|1|1|1|0|1|0|0|1|D|0|0|Rn:4|Vd:4|size:2|1|1|index_align:4|Rm:4",""
+"0x0f300e00","0x0d000a00","VSTR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}]","cond:4|1|1|0|1|U|D|0|0|Rn:4|Vd:4|1|0|1|sz|imm8:8","vfp"
+"0xff800f10","0xf3000800","VSUB.<dt_Isize> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|1|0|D|size:2|Vn:4|Vd:4|1|0|0|0|N|Q|M|0|Vm:4",""
+"0xffa00f10","0xf2200d00","VSUB.F32 <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|1|sz|Vn:4|Vd:4|1|1|0|1|N|Q|M|0|Vm:4",""
+"0x0fb00e50","0x0e300a40","VSUB<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm>","cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4","vfp"
+"0xff810f51","0xf2800600","VSUBHN.<dt_Isize> <Dd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|1|D|size:2|Vn:4|Vd:4|0|1|1|0|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xfe801e50","0xf2800200","VSUBL.<dt_Usize> <Qd>, <Dn>, <Dm>","1|1|1|1|0|0|1|U|1|D|size:2|Vn:4|Vd:4|0|0|1|op|N|0|M|0|Vm:4","SEE “Related encodings”"
+"0xffbf0f90","0xf3b20000","VSWP <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|0|0|0|Q|M|0|Vm:4",""
+"0xffb30f90","0xf3b20080","VTRN.<size_n> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|0|0|1|Q|M|0|Vm:4",""
+"0xff800f10","0xf2000810","VTST.<size_n> <Qd>, <Qn>, <Qm>","1|1|1|1|0|0|1|0|0|D|size:2|Vn:4|Vd:4|1|0|0|0|N|Q|M|1|Vm:4",""
+"0xffb30f90","0xf3b20100","VUZP.<size_n> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|0|1|0|Q|M|0|Vm:4",""
+"0xffb30f90","0xf3b20180","VZIP.<size_n> <Qd>, <Qm>","1|1|1|1|0|0|1|1|1|D|1|1|size:2|1|0|Vd:4|0|0|0|1|1|Q|M|0|Vm:4",""
+"0x0fffffff","0x0320f002","WFE<c>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0",""
+"0x0fffffff","0x0320f003","WFI<c>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1",""
+"0x0fffffff","0x0320f001","YIELD<c>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1",""
+"0xffffffff","0xf7fabcfd","UNDEF","1|1|1|1|0|1|1|1|1|1|1|1|1|0|1|0|1|0|1|1|1|1|0|0|1|1|1|1|1|1|0|1",""
diff --git a/arm/armasm/Makefile b/arm/armasm/Makefile
new file mode 100644
index 0000000..a3f5700
--- /dev/null
+++ b/arm/armasm/Makefile
@@ -0,0 +1,2 @@
+tables.go: ../armmap/map.go ../arm.csv
+ go run ../armmap/map.go -fmt=decoder ../arm.csv >_tables.go && gofmt _tables.go >tables.go && rm _tables.go
diff --git a/arm/armasm/decode.go b/arm/armasm/decode.go
new file mode 100644
index 0000000..6b4d738
--- /dev/null
+++ b/arm/armasm/decode.go
@@ -0,0 +1,567 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package armasm
+
+import (
+ "encoding/binary"
+ "fmt"
+)
+
+// An instFormat describes the format of an instruction encoding.
+// An instruction with 32-bit value x matches the format if x&mask == value
+// and the condition matches.
+// The condition matches if x>>28 == 0xF && value>>28==0xF
+// or if x>>28 != 0xF and value>>28 == 0.
+// If x matches the format, then the rest of the fields describe how to interpret x.
+// The opBits describe bits that should be extracted from x and added to the opcode.
+// For example opBits = 0x1234 means that the value
+// (2 bits at offset 1) followed by (4 bits at offset 3)
+// should be added to op.
+// Finally the args describe how to decode the instruction arguments.
+// args is stored as a fixed-size array; if there are fewer than len(args) arguments,
+// args[i] == 0 marks the end of the argument list.
+type instFormat struct {
+ mask uint32
+ value uint32
+ priority int8
+ op Op
+ opBits uint64
+ args instArgs
+}
+
+type instArgs [4]instArg
+
+var (
+ errMode = fmt.Errorf("unsupported execution mode")
+ errShort = fmt.Errorf("truncated instruction")
+ errUnknown = fmt.Errorf("unknown instruction")
+)
+
+var decoderCover []bool
+
+// Decode decodes the leading bytes in src as a single instruction.
+func Decode(src []byte, mode Mode) (inst Inst, err error) {
+ if mode != ModeARM {
+ return Inst{}, errMode
+ }
+ if len(src) < 4 {
+ return Inst{}, errShort
+ }
+
+ if decoderCover == nil {
+ decoderCover = make([]bool, len(instFormats))
+ }
+
+ x := binary.LittleEndian.Uint32(src)
+
+ // The instFormat table contains both conditional and unconditional instructions.
+ // Considering only the top 4 bits, the conditional instructions use mask=0, value=0,
+ // while the unconditional instructions use mask=f, value=f.
+ // Prepare a version of x with the condition cleared to 0 in conditional instructions
+ // and then assume mask=f during matching.
+ const condMask = 0xf0000000
+ xNoCond := x
+ if x&condMask != condMask {
+ xNoCond &^= condMask
+ }
+ var priority int8
+Search:
+ for i := range instFormats {
+ f := &instFormats[i]
+ if xNoCond&(f.mask|condMask) != f.value || f.priority <= priority {
+ continue
+ }
+ delta := uint32(0)
+ deltaShift := uint(0)
+ for opBits := f.opBits; opBits != 0; opBits >>= 16 {
+ n := uint(opBits & 0xFF)
+ off := uint((opBits >> 8) & 0xFF)
+ delta |= (x >> off) & (1<<n - 1) << deltaShift
+ deltaShift += n
+ }
+ op := f.op + Op(delta)
+
+ // Special case: BKPT encodes with condition but cannot have one.
+ if op&^15 == BKPT_EQ && op != BKPT {
+ continue Search
+ }
+
+ var args Args
+ for j, aop := range f.args {
+ if aop == 0 {
+ break
+ }
+ arg := decodeArg(aop, x)
+ if arg == nil { // cannot decode argument
+ continue Search
+ }
+ args[j] = arg
+ }
+
+ decoderCover[i] = true
+
+ inst = Inst{
+ Op: op,
+ Args: args,
+ Enc: x,
+ Len: 4,
+ }
+ priority = f.priority
+ continue Search
+ }
+ if inst.Op != 0 {
+ return inst, nil
+ }
+ return Inst{}, errUnknown
+}
+
+// An instArg describes the encoding of a single argument.
+// In the names used for arguments, _p_ means +, _m_ means -,
+// _pm_ means ± (usually keyed by the U bit).
+// The _W suffix indicates a general addressing mode based on the P and W bits.
+// The _offset and _postindex suffixes force the given addressing mode.
+// The rest should be somewhat self-explanatory, at least given
+// the decodeArg function.
+type instArg uint8
+
+const (
+ _ instArg = iota
+ arg_APSR
+ arg_FPSCR
+ arg_Dn_half
+ arg_R1_0
+ arg_R1_12
+ arg_R2_0
+ arg_R2_12
+ arg_R_0
+ arg_R_12
+ arg_R_12_nzcv
+ arg_R_16
+ arg_R_16_WB
+ arg_R_8
+ arg_R_rotate
+ arg_R_shift_R
+ arg_R_shift_imm
+ arg_SP
+ arg_Sd
+ arg_Sd_Dd
+ arg_Dd_Sd
+ arg_Sm
+ arg_Sm_Dm
+ arg_Sn
+ arg_Sn_Dn
+ arg_const
+ arg_endian
+ arg_fbits
+ arg_fp_0
+ arg_imm24
+ arg_imm5
+ arg_imm5_32
+ arg_imm5_nz
+ arg_imm_12at8_4at0
+ arg_imm_4at16_12at0
+ arg_imm_vfp
+ arg_label24
+ arg_label24H
+ arg_label_m_12
+ arg_label_p_12
+ arg_label_pm_12
+ arg_label_pm_4_4
+ arg_lsb_width
+ arg_mem_R
+ arg_mem_R_pm_R_W
+ arg_mem_R_pm_R_postindex
+ arg_mem_R_pm_R_shift_imm_W
+ arg_mem_R_pm_R_shift_imm_offset
+ arg_mem_R_pm_R_shift_imm_postindex
+ arg_mem_R_pm_imm12_W
+ arg_mem_R_pm_imm12_offset
+ arg_mem_R_pm_imm12_postindex
+ arg_mem_R_pm_imm8_W
+ arg_mem_R_pm_imm8_postindex
+ arg_mem_R_pm_imm8at0_offset
+ arg_option
+ arg_registers
+ arg_registers1
+ arg_registers2
+ arg_satimm4
+ arg_satimm5
+ arg_satimm4m1
+ arg_satimm5m1
+ arg_widthm1
+)
+
+// decodeArg decodes the arg described by aop from the instruction bits x.
+// It returns nil if x cannot be decoded according to aop.
+func decodeArg(aop instArg, x uint32) Arg {
+ switch aop {
+ default:
+ return nil
+
+ case arg_APSR:
+ return APSR
+ case arg_FPSCR:
+ return FPSCR
+
+ case arg_R_0:
+ return Reg(x & (1<<4 - 1))
+ case arg_R_8:
+ return Reg((x >> 8) & (1<<4 - 1))
+ case arg_R_12:
+ return Reg((x >> 12) & (1<<4 - 1))
+ case arg_R_16:
+ return Reg((x >> 16) & (1<<4 - 1))
+
+ case arg_R_12_nzcv:
+ r := Reg((x >> 12) & (1<<4 - 1))
+ if r == R15 {
+ return APSR_nzcv
+ }
+ return r
+
+ case arg_R_16_WB:
+ mode := AddrLDM
+ if (x>>21)&1 != 0 {
+ mode = AddrLDM_WB
+ }
+ return Mem{Base: Reg((x >> 16) & (1<<4 - 1)), Mode: mode}
+
+ case arg_R_rotate:
+ Rm := Reg(x & (1<<4 - 1))
+ typ, count := decodeShift(x)
+ // ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1.
+ if typ == RotateRightExt {
+ return Reg(Rm)
+ }
+ return RegShift{Rm, typ, uint8(count)}
+
+ case arg_R_shift_R:
+ Rm := Reg(x & (1<<4 - 1))
+ Rs := Reg((x >> 8) & (1<<4 - 1))
+ typ := Shift((x >> 5) & (1<<2 - 1))
+ return RegShiftReg{Rm, typ, Rs}
+
+ case arg_R_shift_imm:
+ Rm := Reg(x & (1<<4 - 1))
+ typ, count := decodeShift(x)
+ if typ == ShiftLeft && count == 0 {
+ return Reg(Rm)
+ }
+ return RegShift{Rm, typ, uint8(count)}
+
+ case arg_R1_0:
+ return Reg((x & (1<<4 - 1)))
+ case arg_R1_12:
+ return Reg(((x >> 12) & (1<<4 - 1)))
+ case arg_R2_0:
+ return Reg((x & (1<<4 - 1)) | 1)
+ case arg_R2_12:
+ return Reg(((x >> 12) & (1<<4 - 1)) | 1)
+
+ case arg_SP:
+ return SP
+
+ case arg_Sd_Dd:
+ v := (x >> 12) & (1<<4 - 1)
+ vx := (x >> 22) & 1
+ sz := (x >> 8) & 1
+ if sz != 0 {
+ return D0 + Reg(vx<<4+v)
+ } else {
+ return S0 + Reg(v<<1+vx)
+ }
+
+ case arg_Dd_Sd:
+ return decodeArg(arg_Sd_Dd, x^(1<<8))
+
+ case arg_Sd:
+ v := (x >> 12) & (1<<4 - 1)
+ vx := (x >> 22) & 1
+ return S0 + Reg(v<<1+vx)
+
+ case arg_Sm_Dm:
+ v := (x >> 0) & (1<<4 - 1)
+ vx := (x >> 5) & 1
+ sz := (x >> 8) & 1
+ if sz != 0 {
+ return D0 + Reg(vx<<4+v)
+ } else {
+ return S0 + Reg(v<<1+vx)
+ }
+
+ case arg_Sm:
+ v := (x >> 0) & (1<<4 - 1)
+ vx := (x >> 5) & 1
+ return S0 + Reg(v<<1+vx)
+
+ case arg_Dn_half:
+ v := (x >> 16) & (1<<4 - 1)
+ vx := (x >> 7) & 1
+ return RegX{D0 + Reg(vx<<4+v), int((x >> 21) & 1)}
+
+ case arg_Sn_Dn:
+ v := (x >> 16) & (1<<4 - 1)
+ vx := (x >> 7) & 1
+ sz := (x >> 8) & 1
+ if sz != 0 {
+ return D0 + Reg(vx<<4+v)
+ } else {
+ return S0 + Reg(v<<1+vx)
+ }
+
+ case arg_Sn:
+ v := (x >> 16) & (1<<4 - 1)
+ vx := (x >> 7) & 1
+ return S0 + Reg(v<<1+vx)
+
+ case arg_const:
+ v := x & (1<<8 - 1)
+ rot := (x >> 8) & (1<<4 - 1) * 2
+ if rot > 0 && v&3 == 0 {
+ // could rotate less
+ return ImmAlt{uint8(v), uint8(rot)}
+ }
+ if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v {
+ // could wrap around to rot==0.
+ return ImmAlt{uint8(v), uint8(rot)}
+ }
+ return Imm(v>>rot | v<<(32-rot))
+
+ case arg_endian:
+ return Endian((x >> 9) & 1)
+
+ case arg_fbits:
+ return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1))
+
+ case arg_fp_0:
+ return Imm(0)
+
+ case arg_imm24:
+ return Imm(x & (1<<24 - 1))
+
+ case arg_imm5:
+ return Imm((x >> 7) & (1<<5 - 1))
+
+ case arg_imm5_32:
+ x = (x >> 7) & (1<<5 - 1)
+ if x == 0 {
+ x = 32
+ }
+ return Imm(x)
+
+ case arg_imm5_nz:
+ x = (x >> 7) & (1<<5 - 1)
+ if x == 0 {
+ return nil
+ }
+ return Imm(x)
+
+ case arg_imm_4at16_12at0:
+ return Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1))
+
+ case arg_imm_12at8_4at0:
+ return Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1))
+
+ case arg_imm_vfp:
+ x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1)
+ return Imm(x)
+
+ case arg_label24:
+ imm := (x & (1<<24 - 1)) << 2
+ return PCRel(int32(imm<<6) >> 6)
+
+ case arg_label24H:
+ h := (x >> 24) & 1
+ imm := (x&(1<<24-1))<<2 | h<<1
+ return PCRel(int32(imm<<6) >> 6)
+
+ case arg_label_m_12:
+ d := int32(x & (1<<12 - 1))
+ return Mem{Base: PC, Mode: AddrOffset, Offset: int16(-d)}
+
+ case arg_label_p_12:
+ d := int32(x & (1<<12 - 1))
+ return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)}
+
+ case arg_label_pm_12:
+ d := int32(x & (1<<12 - 1))
+ u := (x >> 23) & 1
+ if u == 0 {
+ d = -d
+ }
+ return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)}
+
+ case arg_label_pm_4_4:
+ d := int32((x>>8)&(1<<4-1)<<4 | x&(1<<4-1))
+ u := (x >> 23) & 1
+ if u == 0 {
+ d = -d
+ }
+ return PCRel(d)
+
+ case arg_lsb_width:
+ lsb := (x >> 7) & (1<<5 - 1)
+ msb := (x >> 16) & (1<<5 - 1)
+ if msb < lsb || msb >= 32 {
+ return nil
+ }
+ return Imm(msb + 1 - lsb)
+
+ case arg_mem_R:
+ Rn := Reg((x >> 16) & (1<<4 - 1))
+ return Mem{Base: Rn, Mode: AddrOffset}
+
+ case arg_mem_R_pm_R_postindex:
+ // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!}
+ // by forcing shift bits to <<0 and P=0, W=0 (postindex=true).
+ return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5|1<<24|1<<21))
+
+ case arg_mem_R_pm_R_W:
+ // Treat [<Rn>,+/-<Rm>]{!} like [<Rn>,+/-<Rm>{,<shift>}]{!}
+ // by forcing shift bits to <<0.
+ return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5))
+
+ case arg_mem_R_pm_R_shift_imm_offset:
+ // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!}
+ // by forcing P=1, W=0 (index=false, wback=false).
+ return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<21)|1<<24)
+
+ case arg_mem_R_pm_R_shift_imm_postindex:
+ // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!}
+ // by forcing P=0, W=0 (postindex=true).
+ return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<24|1<<21))
+
+ case arg_mem_R_pm_R_shift_imm_W:
+ Rn := Reg((x >> 16) & (1<<4 - 1))
+ Rm := Reg(x & (1<<4 - 1))
+ typ, count := decodeShift(x)
+ u := (x >> 23) & 1
+ w := (x >> 21) & 1
+ p := (x >> 24) & 1
+ if p == 0 && w == 1 {
+ return nil
+ }
+ sign := int8(+1)
+ if u == 0 {
+ sign = -1
+ }
+ mode := AddrMode(uint8(p<<1) | uint8(w^1))
+ return Mem{Base: Rn, Mode: mode, Sign: sign, Index: Rm, Shift: typ, Count: count}
+
+ case arg_mem_R_pm_imm12_offset:
+ // Treat [<Rn>,#+/-<imm12>] like [<Rn>{,#+/-<imm12>}]{!}
+ // by forcing P=1, W=0 (index=false, wback=false).
+ return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24)
+
+ case arg_mem_R_pm_imm12_postindex:
+ // Treat [<Rn>],#+/-<imm12> like [<Rn>{,#+/-<imm12>}]{!}
+ // by forcing P=0, W=0 (postindex=true).
+ return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21))
+
+ case arg_mem_R_pm_imm12_W:
+ Rn := Reg((x >> 16) & (1<<4 - 1))
+ u := (x >> 23) & 1
+ w := (x >> 21) & 1
+ p := (x >> 24) & 1
+ if p == 0 && w == 1 {
+ return nil
+ }
+ sign := int8(+1)
+ if u == 0 {
+ sign = -1
+ }
+ imm := int16(x & (1<<12 - 1))
+ mode := AddrMode(uint8(p<<1) | uint8(w^1))
+ return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm}
+
+ case arg_mem_R_pm_imm8_postindex:
+ // Treat [<Rn>],#+/-<imm8> like [<Rn>{,#+/-<imm8>}]{!}
+ // by forcing P=0, W=0 (postindex=true).
+ return decodeArg(arg_mem_R_pm_imm8_W, x&^(1<<24|1<<21))
+
+ case arg_mem_R_pm_imm8_W:
+ Rn := Reg((x >> 16) & (1<<4 - 1))
+ u := (x >> 23) & 1
+ w := (x >> 21) & 1
+ p := (x >> 24) & 1
+ if p == 0 && w == 1 {
+ return nil
+ }
+ sign := int8(+1)
+ if u == 0 {
+ sign = -1
+ }
+ imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1))
+ mode := AddrMode(uint8(p<<1) | uint8(w^1))
+ return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm}
+
+ case arg_mem_R_pm_imm8at0_offset:
+ Rn := Reg((x >> 16) & (1<<4 - 1))
+ u := (x >> 23) & 1
+ sign := int8(+1)
+ if u == 0 {
+ sign = -1
+ }
+ imm := int16(x&(1<<8-1)) << 2
+ return Mem{Base: Rn, Mode: AddrOffset, Offset: int16(sign) * imm}
+
+ case arg_option:
+ return Imm(x & (1<<4 - 1))
+
+ case arg_registers:
+ return RegList(x & (1<<16 - 1))
+
+ case arg_registers2:
+ x &= 1<<16 - 1
+ n := 0
+ for i := 0; i < 16; i++ {
+ if x>>uint(i)&1 != 0 {
+ n++
+ }
+ }
+ if n < 2 {
+ return nil
+ }
+ return RegList(x)
+
+ case arg_registers1:
+ Rt := (x >> 12) & (1<<4 - 1)
+ return RegList(1 << Rt)
+
+ case arg_satimm4:
+ return Imm((x >> 16) & (1<<4 - 1))
+
+ case arg_satimm5:
+ return Imm((x >> 16) & (1<<5 - 1))
+
+ case arg_satimm4m1:
+ return Imm((x>>16)&(1<<4-1) + 1)
+
+ case arg_satimm5m1:
+ return Imm((x>>16)&(1<<5-1) + 1)
+
+ case arg_widthm1:
+ return Imm((x>>16)&(1<<5-1) + 1)
+
+ }
+}
+
+// decodeShift decodes the shift-by-immediate encoded in x.
+func decodeShift(x uint32) (Shift, uint8) {
+ count := (x >> 7) & (1<<5 - 1)
+ typ := Shift((x >> 5) & (1<<2 - 1))
+ switch typ {
+ case ShiftRight, ShiftRightSigned:
+ if count == 0 {
+ count = 32
+ }
+ case RotateRight:
+ if count == 0 {
+ typ = RotateRightExt
+ count = 1
+ }
+ }
+ return typ, uint8(count)
+}
diff --git a/arm/armasm/decode_test.go b/arm/armasm/decode_test.go
new file mode 100644
index 0000000..3d9da07
--- /dev/null
+++ b/arm/armasm/decode_test.go
@@ -0,0 +1,69 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package armasm
+
+import (
+ "encoding/hex"
+ "io/ioutil"
+ "strconv"
+ "strings"
+ "testing"
+)
+
+func TestDecode(t *testing.T) {
+ data, err := ioutil.ReadFile("testdata/decode.txt")
+ if err != nil {
+ t.Fatal(err)
+ }
+ all := string(data)
+ for strings.Contains(all, "\t\t") {
+ all = strings.Replace(all, "\t\t", "\t", -1)
+ }
+ for _, line := range strings.Split(all, "\n") {
+ line = strings.TrimSpace(line)
+ if line == "" || strings.HasPrefix(line, "#") {
+ continue
+ }
+ f := strings.SplitN(line, "\t", 4)
+ i := strings.Index(f[0], "|")
+ if i < 0 {
+ t.Errorf("parsing %q: missing | separator", f[0])
+ continue
+ }
+ if i%2 != 0 {
+ t.Errorf("parsing %q: misaligned | separator", f[0])
+ }
+ size := i / 2
+ code, err := hex.DecodeString(f[0][:i] + f[0][i+1:])
+ if err != nil {
+ t.Errorf("parsing %q: %v", f[0], err)
+ continue
+ }
+ mode, err := strconv.Atoi(f[1])
+ if err != nil {
+ t.Errorf("invalid mode %q in: %s", f[1], line)
+ continue
+ }
+ syntax, asm := f[2], f[3]
+ inst, err := Decode(code, Mode(mode))
+ var out string
+ if err != nil {
+ out = "error: " + err.Error()
+ } else {
+ switch syntax {
+ case "gnu":
+ out = GNUSyntax(inst)
+ case "plan9":
+ out = plan9Syntax(inst, 0, nil, nil)
+ default:
+ t.Errorf("unknown syntax %q", syntax)
+ continue
+ }
+ }
+ if out != asm || inst.Len != size {
+ t.Errorf("Decode(%s) [%s] = %s, %d, want %s, %d", f[0], syntax, out, inst.Len, asm, size)
+ }
+ }
+}
diff --git a/arm/armasm/ext_test.go b/arm/armasm/ext_test.go
new file mode 100644
index 0000000..d824f0a
--- /dev/null
+++ b/arm/armasm/ext_test.go
@@ -0,0 +1,614 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Support for testing against external disassembler program.
+// Copied and simplified from ../../x86/x86asm/ext_test.go.
+
+package armasm
+
+import (
+ "bufio"
+ "bytes"
+ "encoding/hex"
+ "flag"
+ "fmt"
+ "io/ioutil"
+ "log"
+ "math/rand"
+ "os"
+ "os/exec"
+ "regexp"
+ "runtime"
+ "strings"
+ "testing"
+ "time"
+)
+
+var (
+ printTests = flag.Bool("printtests", false, "print test cases that exercise new code paths")
+ dumpTest = flag.Bool("dump", false, "dump all encodings")
+ mismatch = flag.Bool("mismatch", false, "log allowed mismatches")
+ longTest = flag.Bool("long", false, "long test")
+ keep = flag.Bool("keep", false, "keep object files around")
+ debug = false
+)
+
+// A ExtInst represents a single decoded instruction parsed
+// from an external disassembler's output.
+type ExtInst struct {
+ addr uint32
+ enc [4]byte
+ nenc int
+ text string
+}
+
+func (r ExtInst) String() string {
+ return fmt.Sprintf("%#x: % x: %s", r.addr, r.enc, r.text)
+}
+
+// An ExtDis is a connection between an external disassembler and a test.
+type ExtDis struct {
+ Arch Mode
+ Dec chan ExtInst
+ File *os.File
+ Size int
+ KeepFile bool
+ Cmd *exec.Cmd
+}
+
+// Run runs the given command - the external disassembler - and returns
+// a buffered reader of its standard output.
+func (ext *ExtDis) Run(cmd ...string) (*bufio.Reader, error) {
+ if *keep {
+ log.Printf("%s\n", strings.Join(cmd, " "))
+ }
+ ext.Cmd = exec.Command(cmd[0], cmd[1:]...)
+ out, err := ext.Cmd.StdoutPipe()
+ if err != nil {
+ return nil, fmt.Errorf("stdoutpipe: %v", err)
+ }
+ if err := ext.Cmd.Start(); err != nil {
+ return nil, fmt.Errorf("exec: %v", err)
+ }
+
+ b := bufio.NewReaderSize(out, 1<<20)
+ return b, nil
+}
+
+// Wait waits for the command started with Run to exit.
+func (ext *ExtDis) Wait() error {
+ return ext.Cmd.Wait()
+}
+
+// testExtDis tests a set of byte sequences against an external disassembler.
+// The disassembler is expected to produce the given syntax and be run
+// in the given architecture mode (16, 32, or 64-bit).
+// The extdis function must start the external disassembler
+// and then parse its output, sending the parsed instructions on ext.Dec.
+// The generate function calls its argument f once for each byte sequence
+// to be tested. The generate function itself will be called twice, and it must
+// make the same sequence of calls to f each time.
+// When a disassembly does not match the internal decoding,
+// allowedMismatch determines whether this mismatch should be
+// allowed, or else considered an error.
+func testExtDis(
+ t *testing.T,
+ syntax string,
+ arch Mode,
+ extdis func(ext *ExtDis) error,
+ generate func(f func([]byte)),
+ allowedMismatch func(text string, size int, inst *Inst, dec ExtInst) bool,
+) {
+ start := time.Now()
+ ext := &ExtDis{
+ Dec: make(chan ExtInst),
+ Arch: arch,
+ }
+ errc := make(chan error)
+
+ // First pass: write instructions to input file for external disassembler.
+ file, f, size, err := writeInst(generate)
+ if err != nil {
+ t.Fatal(err)
+ }
+ ext.Size = size
+ ext.File = f
+ defer func() {
+ f.Close()
+ if !*keep {
+ os.Remove(file)
+ }
+ }()
+
+ // Second pass: compare disassembly against our decodings.
+ var (
+ totalTests = 0
+ totalSkips = 0
+ totalErrors = 0
+
+ errors = make([]string, 0, 100) // sampled errors, at most cap
+ )
+ go func() {
+ errc <- extdis(ext)
+ }()
+ generate(func(enc []byte) {
+ dec, ok := <-ext.Dec
+ if !ok {
+ t.Errorf("decoding stream ended early")
+ return
+ }
+ inst, text := disasm(syntax, arch, pad(enc))
+ totalTests++
+ if *dumpTest {
+ fmt.Printf("%x -> %s [%d]\n", enc[:len(enc)], dec.text, dec.nenc)
+ }
+ if text != dec.text || inst.Len != dec.nenc {
+ suffix := ""
+ if allowedMismatch(text, size, &inst, dec) {
+ totalSkips++
+ if !*mismatch {
+ return
+ }
+ suffix += " (allowed mismatch)"
+ }
+ totalErrors++
+ if len(errors) >= cap(errors) {
+ j := rand.Intn(totalErrors)
+ if j >= cap(errors) {
+ return
+ }
+ errors = append(errors[:j], errors[j+1:]...)
+ }
+ errors = append(errors, fmt.Sprintf("decode(%x) = %q, %d, want %q, %d%s", enc, text, inst.Len, dec.text, dec.nenc, suffix))
+ }
+ })
+
+ if *mismatch {
+ totalErrors -= totalSkips
+ }
+
+ for _, b := range errors {
+ t.Log(b)
+ }
+
+ if totalErrors > 0 {
+ t.Fail()
+ }
+ t.Logf("%d test cases, %d expected mismatches, %d failures; %.0f cases/second", totalTests, totalSkips, totalErrors, float64(totalTests)/time.Since(start).Seconds())
+
+ if err := <-errc; err != nil {
+ t.Fatal("external disassembler: %v", err)
+ }
+
+}
+
+const start = 0x8000 // start address of text
+
+// writeInst writes the generated byte sequences to a new file
+// starting at offset start. That file is intended to be the input to
+// the external disassembler.
+func writeInst(generate func(func([]byte))) (file string, f *os.File, size int, err error) {
+ f, err = ioutil.TempFile("", "armasm")
+ if err != nil {
+ return
+ }
+
+ file = f.Name()
+
+ f.Seek(start, 0)
+ w := bufio.NewWriter(f)
+ defer w.Flush()
+ size = 0
+ generate(func(x []byte) {
+ if len(x) > 4 {
+ x = x[:4]
+ }
+ if debug {
+ fmt.Printf("%#x: %x%x\n", start+size, x, zeros[len(x):])
+ }
+ w.Write(x)
+ w.Write(zeros[len(x):])
+ size += len(zeros)
+ })
+ return file, f, size, nil
+}
+
+var zeros = []byte{0, 0, 0, 0}
+
+// pad pads the code sequenc with pops.
+func pad(enc []byte) []byte {
+ if len(enc) < 4 {
+ enc = append(enc[:len(enc):len(enc)], zeros[:4-len(enc)]...)
+ }
+ return enc
+}
+
+// disasm returns the decoded instruction and text
+// for the given source bytes, using the given syntax and mode.
+func disasm(syntax string, mode Mode, src []byte) (inst Inst, text string) {
+ // If printTests is set, we record the coverage value
+ // before and after, and we write out the inputs for which
+ // coverage went up, in the format expected in testdata/decode.text.
+ // This produces a fairly small set of test cases that exercise nearly
+ // all the code.
+ var cover float64
+ if *printTests {
+ cover -= coverage()
+ }
+
+ inst, err := Decode(src, mode)
+ if err != nil {
+ text = "error: " + err.Error()
+ } else {
+ text = inst.String()
+ switch syntax {
+ //case "arm":
+ // text = ARMSyntax(inst)
+ case "gnu":
+ text = GNUSyntax(inst)
+ //case "plan9":
+ // text = plan9Syntax(inst, 0, nil)
+ default:
+ text = "error: unknown syntax " + syntax
+ }
+ }
+
+ if *printTests {
+ cover += coverage()
+ if cover > 0 {
+ max := len(src)
+ if max > 4 && inst.Len <= 4 {
+ max = 4
+ }
+ fmt.Printf("%x|%x\t%d\t%s\t%s\n", src[:inst.Len], src[inst.Len:max], mode, syntax, text)
+ }
+ }
+
+ return
+}
+
+// coverage returns a floating point number denoting the
+// test coverage until now. The number increases when new code paths are exercised,
+// both in the Go program and in the decoder byte code.
+func coverage() float64 {
+ /*
+ testing.Coverage is not in the main distribution.
+ The implementation, which must go in package testing, is:
+
+ // Coverage reports the current code coverage as a fraction in the range [0, 1].
+ func Coverage() float64 {
+ var n, d int64
+ for _, counters := range cover.Counters {
+ for _, c := range counters {
+ if c > 0 {
+ n++
+ }
+ d++
+ }
+ }
+ if d == 0 {
+ return 0
+ }
+ return float64(n) / float64(d)
+ }
+ */
+
+ var f float64
+ f += testing.Coverage()
+ f += decodeCoverage()
+ return f
+}
+
+func decodeCoverage() float64 {
+ n := 0
+ for _, t := range decoderCover {
+ if t {
+ n++
+ }
+ }
+ return float64(1+n) / float64(1+len(decoderCover))
+}
+
+// Helpers for writing disassembler output parsers.
+
+// hasPrefix reports whether any of the space-separated words in the text s
+// begins with any of the given prefixes.
+func hasPrefix(s string, prefixes ...string) bool {
+ for _, prefix := range prefixes {
+ for s := s; s != ""; {
+ if strings.HasPrefix(s, prefix) {
+ return true
+ }
+ i := strings.Index(s, " ")
+ if i < 0 {
+ break
+ }
+ s = s[i+1:]
+ }
+ }
+ return false
+}
+
+// contains reports whether the text s contains any of the given substrings.
+func contains(s string, substrings ...string) bool {
+ for _, sub := range substrings {
+ if strings.Contains(s, sub) {
+ return true
+ }
+ }
+ return false
+}
+
+// isHex reports whether b is a hexadecimal character (0-9A-Fa-f).
+func isHex(b byte) bool { return b == '0' || unhex[b] > 0 }
+
+// parseHex parses the hexadecimal byte dump in hex,
+// appending the parsed bytes to raw and returning the updated slice.
+// The returned bool signals whether any invalid hex was found.
+// Spaces and tabs between bytes are okay but any other non-hex is not.
+func parseHex(hex []byte, raw []byte) ([]byte, bool) {
+ hex = trimSpace(hex)
+ for j := 0; j < len(hex); {
+ for hex[j] == ' ' || hex[j] == '\t' {
+ j++
+ }
+ if j >= len(hex) {
+ break
+ }
+ if j+2 > len(hex) || !isHex(hex[j]) || !isHex(hex[j+1]) {
+ return nil, false
+ }
+ raw = append(raw, unhex[hex[j]]<<4|unhex[hex[j+1]])
+ j += 2
+ }
+ return raw, true
+}
+
+var unhex = [256]byte{
+ '0': 0,
+ '1': 1,
+ '2': 2,
+ '3': 3,
+ '4': 4,
+ '5': 5,
+ '6': 6,
+ '7': 7,
+ '8': 8,
+ '9': 9,
+ 'A': 10,
+ 'B': 11,
+ 'C': 12,
+ 'D': 13,
+ 'E': 14,
+ 'F': 15,
+ 'a': 10,
+ 'b': 11,
+ 'c': 12,
+ 'd': 13,
+ 'e': 14,
+ 'f': 15,
+}
+
+// index is like bytes.Index(s, []byte(t)) but avoids the allocation.
+func index(s []byte, t string) int {
+ i := 0
+ for {
+ j := bytes.IndexByte(s[i:], t[0])
+ if j < 0 {
+ return -1
+ }
+ i = i + j
+ if i+len(t) > len(s) {
+ return -1
+ }
+ for k := 1; k < len(t); k++ {
+ if s[i+k] != t[k] {
+ goto nomatch
+ }
+ }
+ return i
+ nomatch:
+ i++
+ }
+}
+
+// fixSpace rewrites runs of spaces, tabs, and newline characters into single spaces in s.
+// If s must be rewritten, it is rewritten in place.
+func fixSpace(s []byte) []byte {
+ s = trimSpace(s)
+ for i := 0; i < len(s); i++ {
+ if s[i] == '\t' || s[i] == '\n' || i > 0 && s[i] == ' ' && s[i-1] == ' ' {
+ goto Fix
+ }
+ }
+ return s
+
+Fix:
+ b := s
+ w := 0
+ for i := 0; i < len(s); i++ {
+ c := s[i]
+ if c == '\t' || c == '\n' {
+ c = ' '
+ }
+ if c == ' ' && w > 0 && b[w-1] == ' ' {
+ continue
+ }
+ b[w] = c
+ w++
+ }
+ if w > 0 && b[w-1] == ' ' {
+ w--
+ }
+ return b[:w]
+}
+
+// trimSpace trims leading and trailing space from s, returning a subslice of s.
+func trimSpace(s []byte) []byte {
+ j := len(s)
+ for j > 0 && (s[j-1] == ' ' || s[j-1] == '\t' || s[j-1] == '\n') {
+ j--
+ }
+ i := 0
+ for i < j && (s[i] == ' ' || s[i] == '\t') {
+ i++
+ }
+ return s[i:j]
+}
+
+// pcrel matches instructions using relative addressing mode.
+var (
+ pcrel = regexp.MustCompile(`^((?:.* )?(?:b|bl)x?(?:eq|ne|cs|cc|mi|pl|vs|vc|hi|ls|ge|lt|gt|le)?) 0x([0-9a-f]+)$`)
+)
+
+// Generators.
+//
+// The test cases are described as functions that invoke a callback repeatedly,
+// with a new input sequence each time. These helpers make writing those
+// a little easier.
+
+// condCases generates conditional instructions.
+func condCases(t *testing.T) func(func([]byte)) {
+ return func(try func([]byte)) {
+ // All the strides are relatively prime to 2 and therefore to 2²⁸,
+ // so we will not repeat any instructions until we have tried all 2²⁸.
+ // Using a stride other than 1 is meant to visit the instructions in a
+ // pseudorandom order, which gives better variety in the set of
+ // test cases chosen by -printtests.
+ stride := uint32(10007)
+ n := 1 << 28 / 7
+ if testing.Short() {
+ stride = 100003
+ n = 1 << 28 / 1001
+ } else if *longTest {
+ stride = 200000033
+ n = 1 << 28
+ }
+ x := uint32(0)
+ for i := 0; i < n; i++ {
+ enc := (x%15)<<28 | x&(1<<28-1)
+ try([]byte{byte(enc), byte(enc >> 8), byte(enc >> 16), byte(enc >> 24)})
+ x += stride
+ }
+ }
+}
+
+// uncondCases generates unconditional instructions.
+func uncondCases(t *testing.T) func(func([]byte)) {
+ return func(try func([]byte)) {
+ condCases(t)(func(enc []byte) {
+ enc[3] |= 0xF0
+ try(enc)
+ })
+ }
+}
+
+func countBits(x uint32) int {
+ n := 0
+ for ; x != 0; x >>= 1 {
+ n += int(x & 1)
+ }
+ return n
+}
+
+func expandBits(x, m uint32) uint32 {
+ var out uint32
+ for i := uint(0); i < 32; i++ {
+ out >>= 1
+ if m&1 != 0 {
+ out |= (x & 1) << 31
+ x >>= 1
+ }
+ m >>= 1
+ }
+ return out
+}
+
+func tryCondMask(mask, val uint32, try func([]byte)) {
+ n := countBits(^mask)
+ bits := uint32(0)
+ for i := 0; i < 1<<uint(n); i++ {
+ bits += 848251 // arbitrary prime
+ x := val | expandBits(bits, ^mask) | uint32(i)%15<<28
+ try([]byte{byte(x), byte(x >> 8), byte(x >> 16), byte(x >> 24)})
+ }
+}
+
+// vfpCases generates VFP instructions.
+func vfpCases(t *testing.T) func(func([]byte)) {
+ const (
+ vfpmask uint32 = 0xFF00FE10
+ vfp uint32 = 0x0E009A00
+ )
+ return func(try func([]byte)) {
+ tryCondMask(0xff00fe10, 0x0e009a00, try) // standard VFP instruction space
+ tryCondMask(0xffc00f7f, 0x0e000b10, try) // VFP MOV core reg to/from float64 half
+ tryCondMask(0xffe00f7f, 0x0e000a10, try) // VFP MOV core reg to/from float32
+ tryCondMask(0xffef0fff, 0x0ee10a10, try) // VFP MOV core reg to/from cond codes
+ }
+}
+
+// hexCases generates the cases written in hexadecimal in the encoded string.
+// Spaces in 'encoded' separate entire test cases, not individual bytes.
+func hexCases(t *testing.T, encoded string) func(func([]byte)) {
+ return func(try func([]byte)) {
+ for _, x := range strings.Fields(encoded) {
+ src, err := hex.DecodeString(x)
+ if err != nil {
+ t.Errorf("parsing %q: %v", x, err)
+ }
+ try(src)
+ }
+ }
+}
+
+// testdataCases generates the test cases recorded in testdata/decode.txt.
+// It only uses the inputs; it ignores the answers recorded in that file.
+func testdataCases(t *testing.T) func(func([]byte)) {
+ var codes [][]byte
+ data, err := ioutil.ReadFile("testdata/decode.txt")
+ if err != nil {
+ t.Fatal(err)
+ }
+ for _, line := range strings.Split(string(data), "\n") {
+ line = strings.TrimSpace(line)
+ if line == "" || strings.HasPrefix(line, "#") {
+ continue
+ }
+ f := strings.Fields(line)[0]
+ i := strings.Index(f, "|")
+ if i < 0 {
+ t.Errorf("parsing %q: missing | separator", f)
+ continue
+ }
+ if i%2 != 0 {
+ t.Errorf("parsing %q: misaligned | separator", f)
+ }
+ code, err := hex.DecodeString(f[:i] + f[i+1:])
+ if err != nil {
+ t.Errorf("parsing %q: %v", f, err)
+ continue
+ }
+ codes = append(codes, code)
+ }
+
+ return func(try func([]byte)) {
+ for _, code := range codes {
+ try(code)
+ }
+ }
+}
+
+func caller(skip int) string {
+ pc, _, _, _ := runtime.Caller(skip)
+ f := runtime.FuncForPC(pc)
+ name := "?"
+ if f != nil {
+ name = f.Name()
+ if i := strings.LastIndex(name, "."); i >= 0 {
+ name = name[i+1:]
+ }
+ }
+ return name
+}
diff --git a/arm/armasm/gnu.go b/arm/armasm/gnu.go
new file mode 100644
index 0000000..1a97a5a
--- /dev/null
+++ b/arm/armasm/gnu.go
@@ -0,0 +1,164 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package armasm
+
+import (
+ "bytes"
+ "fmt"
+ "strings"
+)
+
+var saveDot = strings.NewReplacer(
+ ".F16", "_dot_F16",
+ ".F32", "_dot_F32",
+ ".F64", "_dot_F64",
+ ".S32", "_dot_S32",
+ ".U32", "_dot_U32",
+ ".FXS", "_dot_S",
+ ".FXU", "_dot_U",
+ ".32", "_dot_32",
+)
+
+// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils.
+// This form typically matches the syntax defined in the ARM Reference Manual.
+func GNUSyntax(inst Inst) string {
+ var buf bytes.Buffer
+ op := inst.Op.String()
+ op = saveDot.Replace(op)
+ op = strings.Replace(op, ".", "", -1)
+ op = strings.Replace(op, "_dot_", ".", -1)
+ op = strings.ToLower(op)
+ buf.WriteString(op)
+ sep := " "
+ for i, arg := range inst.Args {
+ if arg == nil {
+ break
+ }
+ text := gnuArg(&inst, i, arg)
+ if text == "" {
+ continue
+ }
+ buf.WriteString(sep)
+ sep = ", "
+ buf.WriteString(text)
+ }
+ return buf.String()
+}
+
+func gnuArg(inst *Inst, argIndex int, arg Arg) string {
+ switch inst.Op &^ 15 {
+ case LDRD_EQ, LDREXD_EQ, STRD_EQ:
+ if argIndex == 1 {
+ // second argument in consecutive pair not printed
+ return ""
+ }
+ case STREXD_EQ:
+ if argIndex == 2 {
+ // second argument in consecutive pair not printed
+ return ""
+ }
+ }
+
+ switch arg := arg.(type) {
+ case Imm:
+ switch inst.Op &^ 15 {
+ case BKPT_EQ:
+ return fmt.Sprintf("%#04x", uint32(arg))
+ case SVC_EQ:
+ return fmt.Sprintf("%#08x", uint32(arg))
+ }
+ return fmt.Sprintf("#%d", int32(arg))
+
+ case ImmAlt:
+ return fmt.Sprintf("#%d, %d", arg.Val, arg.Rot)
+
+ case Mem:
+ R := gnuArg(inst, -1, arg.Base)
+ X := ""
+ if arg.Sign != 0 {
+ X = ""
+ if arg.Sign < 0 {
+ X = "-"
+ }
+ X += gnuArg(inst, -1, arg.Index)
+ if arg.Shift == ShiftLeft && arg.Count == 0 {
+ // nothing
+ } else if arg.Shift == RotateRightExt {
+ X += ", rrx"
+ } else {
+ X += fmt.Sprintf(", %s #%d", strings.ToLower(arg.Shift.String()), arg.Count)
+ }
+ } else {
+ X = fmt.Sprintf("#%d", arg.Offset)
+ }
+
+ switch arg.Mode {
+ case AddrOffset:
+ if X == "#0" {
+ return fmt.Sprintf("[%s]", R)
+ }
+ return fmt.Sprintf("[%s, %s]", R, X)
+ case AddrPreIndex:
+ return fmt.Sprintf("[%s, %s]!", R, X)
+ case AddrPostIndex:
+ return fmt.Sprintf("[%s], %s", R, X)
+ case AddrLDM:
+ if X == "#0" {
+ return R
+ }
+ case AddrLDM_WB:
+ if X == "#0" {
+ return R + "!"
+ }
+ }
+ return fmt.Sprintf("[%s Mode(%d) %s]", R, int(arg.Mode), X)
+
+ case PCRel:
+ return fmt.Sprintf(".%+#x", int32(arg)+4)
+
+ case Reg:
+ switch inst.Op &^ 15 {
+ case LDREX_EQ:
+ if argIndex == 0 {
+ return fmt.Sprintf("r%d", int32(arg))
+ }
+ }
+ switch arg {
+ case R10:
+ return "sl"
+ case R11:
+ return "fp"
+ case R12:
+ return "ip"
+ }
+
+ case RegList:
+ var buf bytes.Buffer
+ fmt.Fprintf(&buf, "{")
+ sep := ""
+ for i := 0; i < 16; i++ {
+ if arg&(1<<uint(i)) != 0 {
+ fmt.Fprintf(&buf, "%s%s", sep, gnuArg(inst, -1, Reg(i)))
+ sep = ", "
+ }
+ }
+ fmt.Fprintf(&buf, "}")
+ return buf.String()
+
+ case RegShift:
+ if arg.Shift == ShiftLeft && arg.Count == 0 {
+ return gnuArg(inst, -1, arg.Reg)
+ }
+ if arg.Shift == RotateRightExt {
+ return gnuArg(inst, -1, arg.Reg) + ", rrx"
+ }
+ return fmt.Sprintf("%s, %s #%d", gnuArg(inst, -1, arg.Reg), strings.ToLower(arg.Shift.String()), arg.Count)
+
+ case RegShiftReg:
+ return fmt.Sprintf("%s, %s %s", gnuArg(inst, -1, arg.Reg), strings.ToLower(arg.Shift.String()), gnuArg(inst, -1, arg.RegCount))
+
+ }
+ return strings.ToLower(arg.String())
+}
diff --git a/arm/armasm/inst.go b/arm/armasm/inst.go
new file mode 100644
index 0000000..60d633b
--- /dev/null
+++ b/arm/armasm/inst.go
@@ -0,0 +1,438 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package armasm
+
+import (
+ "bytes"
+ "fmt"
+)
+
+// A Mode is an instruction execution mode.
+type Mode int
+
+const (
+ _ Mode = iota
+ ModeARM
+ ModeThumb
+)
+
+func (m Mode) String() string {
+ switch m {
+ case ModeARM:
+ return "ARM"
+ case ModeThumb:
+ return "Thumb"
+ }
+ return fmt.Sprintf("Mode(%d)", int(m))
+}
+
+// An Op is an ARM opcode.
+type Op uint16
+
+// NOTE: The actual Op values are defined in tables.go.
+// They are chosen to simplify instruction decoding and
+// are not a dense packing from 0 to N, although the
+// density is high, probably at least 90%.
+
+func (op Op) String() string {
+ if op >= Op(len(opstr)) || opstr[op] == "" {
+ return fmt.Sprintf("Op(%d)", int(op))
+ }
+ return opstr[op]
+}
+
+// An Inst is a single instruction.
+type Inst struct {
+ Op Op // Opcode mnemonic
+ Enc uint32 // Raw encoding bits.
+ Len int // Length of encoding in bytes.
+ Args Args // Instruction arguments, in ARM manual order.
+}
+
+func (i Inst) String() string {
+ var buf bytes.Buffer
+ buf.WriteString(i.Op.String())
+ for j, arg := range i.Args {
+ if arg == nil {
+ break
+ }
+ if j == 0 {
+ buf.WriteString(" ")
+ } else {
+ buf.WriteString(", ")
+ }
+ buf.WriteString(arg.String())
+ }
+ return buf.String()
+}
+
+// An Args holds the instruction arguments.
+// If an instruction has fewer than 4 arguments,
+// the final elements in the array are nil.
+type Args [4]Arg
+
+// An Arg is a single instruction argument, one of these types:
+// Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg.
+type Arg interface {
+ IsArg()
+ String() string
+}
+
+type Float32Imm float32
+
+func (Float32Imm) IsArg() {}
+
+func (f Float32Imm) String() string {
+ return fmt.Sprintf("#%v", float32(f))
+}
+
+type Float64Imm float32
+
+func (Float64Imm) IsArg() {}
+
+func (f Float64Imm) String() string {
+ return fmt.Sprintf("#%v", float64(f))
+}
+
+// An Imm is an integer constant.
+type Imm uint32
+
+func (Imm) IsArg() {}
+
+func (i Imm) String() string {
+ return fmt.Sprintf("#%#x", uint32(i))
+}
+
+// A ImmAlt is an alternate encoding of an integer constant.
+type ImmAlt struct {
+ Val uint8
+ Rot uint8
+}
+
+func (ImmAlt) IsArg() {}
+
+func (i ImmAlt) Imm() Imm {
+ v := uint32(i.Val)
+ r := uint(i.Rot)
+ return Imm(v>>r | v<<(32-r))
+}
+
+func (i ImmAlt) String() string {
+ return fmt.Sprintf("#%#x, %d", i.Val, i.Rot)
+}
+
+// A Label is a text (code) address.
+type Label uint32
+
+func (Label) IsArg() {}
+
+func (i Label) String() string {
+ return fmt.Sprintf("%#x", uint32(i))
+}
+
+// A Reg is a single register.
+// The zero value denotes R0, not the absence of a register.
+type Reg uint8
+
+const (
+ R0 Reg = iota
+ R1
+ R2
+ R3
+ R4
+ R5
+ R6
+ R7
+ R8
+ R9
+ R10
+ R11
+ R12
+ R13
+ R14
+ R15
+
+ S0
+ S1
+ S2
+ S3
+ S4
+ S5
+ S6
+ S7
+ S8
+ S9
+ S10
+ S11
+ S12
+ S13
+ S14
+ S15
+ S16
+ S17
+ S18
+ S19
+ S20
+ S21
+ S22
+ S23
+ S24
+ S25
+ S26
+ S27
+ S28
+ S29
+ S30
+ S31
+
+ D0
+ D1
+ D2
+ D3
+ D4
+ D5
+ D6
+ D7
+ D8
+ D9
+ D10
+ D11
+ D12
+ D13
+ D14
+ D15
+ D16
+ D17
+ D18
+ D19
+ D20
+ D21
+ D22
+ D23
+ D24
+ D25
+ D26
+ D27
+ D28
+ D29
+ D30
+ D31
+
+ APSR
+ APSR_nzcv
+ FPSCR
+
+ SP = R13
+ LR = R14
+ PC = R15
+)
+
+func (Reg) IsArg() {}
+
+func (r Reg) String() string {
+ switch r {
+ case APSR:
+ return "APSR"
+ case APSR_nzcv:
+ return "APSR_nzcv"
+ case FPSCR:
+ return "FPSCR"
+ case SP:
+ return "SP"
+ case PC:
+ return "PC"
+ case LR:
+ return "LR"
+ }
+ if R0 <= r && r <= R15 {
+ return fmt.Sprintf("R%d", int(r-R0))
+ }
+ if S0 <= r && r <= S31 {
+ return fmt.Sprintf("S%d", int(r-S0))
+ }
+ if D0 <= r && r <= D31 {
+ return fmt.Sprintf("D%d", int(r-D0))
+ }
+ return fmt.Sprintf("Reg(%d)", int(r))
+}
+
+// A RegX represents a fraction of a multi-value register.
+// The Index field specifies the index number,
+// but the size of the fraction is not specified.
+// It must be inferred from the instruction and the register type.
+// For example, in a VMOV instruction, RegX{D5, 1} represents
+// the top 32 bits of the 64-bit D5 register.
+type RegX struct {
+ Reg Reg
+ Index int
+}
+
+func (RegX) IsArg() {}
+
+func (r RegX) String() string {
+ return fmt.Sprintf("%s[%d]", r.Reg, r.Index)
+}
+
+// A RegList is a register list.
+// Bits at indexes x = 0 through 15 indicate whether the corresponding Rx register is in the list.
+type RegList uint16
+
+func (RegList) IsArg() {}
+
+func (r RegList) String() string {
+ var buf bytes.Buffer
+ fmt.Fprintf(&buf, "{")
+ sep := ""
+ for i := 0; i < 16; i++ {
+ if r&(1<<uint(i)) != 0 {
+ fmt.Fprintf(&buf, "%s%s", sep, Reg(i).String())
+ sep = ","
+ }
+ }
+ fmt.Fprintf(&buf, "}")
+ return buf.String()
+}
+
+// An Endian is the argument to the SETEND instruction.
+type Endian uint8
+
+const (
+ LittleEndian Endian = 0
+ BigEndian Endian = 1
+)
+
+func (Endian) IsArg() {}
+
+func (e Endian) String() string {
+ if e != 0 {
+ return "BE"
+ }
+ return "LE"
+}
+
+// A Shift describes an ARM shift operation.
+type Shift uint8
+
+const (
+ ShiftLeft Shift = 0 // left shift
+ ShiftRight Shift = 1 // logical (unsigned) right shift
+ ShiftRightSigned Shift = 2 // arithmetic (signed) right shift
+ RotateRight Shift = 3 // right rotate
+ RotateRightExt Shift = 4 // right rotate through carry (Count will always be 1)
+)
+
+var shiftName = [...]string{
+ "LSL", "LSR", "ASR", "ROR", "RRX",
+}
+
+func (s Shift) String() string {
+ if s < 5 {
+ return shiftName[s]
+ }
+ return fmt.Sprintf("Shift(%d)", int(s))
+}
+
+// A RegShift is a register shifted by a constant.
+type RegShift struct {
+ Reg Reg
+ Shift Shift
+ Count uint8
+}
+
+func (RegShift) IsArg() {}
+
+func (r RegShift) String() string {
+ return fmt.Sprintf("%s %s #%d", r.Reg, r.Shift, r.Count)
+}
+
+// A RegShiftReg is a register shifted by a register.
+type RegShiftReg struct {
+ Reg Reg
+ Shift Shift
+ RegCount Reg
+}
+
+func (RegShiftReg) IsArg() {}
+
+func (r RegShiftReg) String() string {
+ return fmt.Sprintf("%s %s %s", r.Reg, r.Shift, r.RegCount)
+}
+
+// A PCRel describes a memory address (usually a code label)
+// as a distance relative to the program counter.
+// TODO(rsc): Define which program counter (PC+4? PC+8? PC?).
+type PCRel int32
+
+func (PCRel) IsArg() {}
+
+func (r PCRel) String() string {
+ return fmt.Sprintf("PC%+#x", int32(r))
+}
+
+// An AddrMode is an ARM addressing mode.
+type AddrMode uint8
+
+const (
+ _ AddrMode = iota
+ AddrPostIndex // [R], X – use address R, set R = R + X
+ AddrPreIndex // [R, X]! – use address R + X, set R = R + X
+ AddrOffset // [R, X] – use address R + X
+ AddrLDM // R – [R] but formats as R, for LDM/STM only
+ AddrLDM_WB // R! - [R], X where X is instruction-specific amount, for LDM/STM only
+)
+
+// A Mem is a memory reference made up of a base R and index expression X.
+// The effective memory address is R or R+X depending on AddrMode.
+// The index expression is X = Sign*(Index Shift Count) + Offset,
+// but in any instruction either Sign = 0 or Offset = 0.
+type Mem struct {
+ Base Reg
+ Mode AddrMode
+ Sign int8
+ Index Reg
+ Shift Shift
+ Count uint8
+ Offset int16
+}
+
+func (Mem) IsArg() {}
+
+func (m Mem) String() string {
+ R := m.Base.String()
+ X := ""
+ if m.Sign != 0 {
+ X = "+"
+ if m.Sign < 0 {
+ X = "-"
+ }
+ X += m.Index.String()
+ if m.Shift != ShiftLeft || m.Count != 0 {
+ X += fmt.Sprintf(", %s #%d", m.Shift, m.Count)
+ }
+ } else {
+ X = fmt.Sprintf("#%d", m.Offset)
+ }
+
+ switch m.Mode {
+ case AddrOffset:
+ if X == "#0" {
+ return fmt.Sprintf("[%s]", R)
+ }
+ return fmt.Sprintf("[%s, %s]", R, X)
+ case AddrPreIndex:
+ return fmt.Sprintf("[%s, %s]!", R, X)
+ case AddrPostIndex:
+ return fmt.Sprintf("[%s], %s", R, X)
+ case AddrLDM:
+ if X == "#0" {
+ return R
+ }
+ case AddrLDM_WB:
+ if X == "#0" {
+ return R + "!"
+ }
+ }
+ return fmt.Sprintf("[%s Mode(%d) %s]", R, int(m.Mode), X)
+}
diff --git a/arm/armasm/objdump_test.go b/arm/armasm/objdump_test.go
new file mode 100644
index 0000000..db51902
--- /dev/null
+++ b/arm/armasm/objdump_test.go
@@ -0,0 +1,268 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package armasm
+
+import (
+ "encoding/binary"
+ "strings"
+ "testing"
+)
+
+func TestObjdumpARMTestdata(t *testing.T) { testObjdumpARM(t, testdataCases(t)) }
+func TestObjdumpARMManual(t *testing.T) { testObjdumpARM(t, hexCases(t, objdumpManualTests)) }
+func TestObjdumpARMCond(t *testing.T) { testObjdumpARM(t, condCases(t)) }
+func TestObjdumpARMUncond(t *testing.T) { testObjdumpARM(t, uncondCases(t)) }
+func TestObjdumpARMVFP(t *testing.T) { testObjdumpARM(t, vfpCases(t)) }
+
+// objdumpManualTests holds test cases that will be run by TestObjdumpARMManual.
+// If you are debugging a few cases that turned up in a longer run, it can be useful
+// to list them here and then use -run=Manual, particularly with tracing enabled.
+// Note that these are byte sequences, so they must be reversed from the usual
+// word presentation.
+var objdumpManualTests = `
+002a9b1d
+001b9bed
+020b8ded
+003a9b1d
+060b8ded
+fcde1100
+b4de1100
+bc480000
+0b008de7
+0b00ade7
+fdbcfaf7
+`
+
+// allowedMismatchObjdump reports whether the mismatch between text and dec
+// should be allowed by the test.
+func allowedMismatchObjdump(text string, size int, inst *Inst, dec ExtInst) bool {
+ if hasPrefix(text, "error:") {
+ if hasPrefix(dec.text, unsupported...) || strings.Contains(dec.text, "invalid:") || strings.HasSuffix(dec.text, "^") || strings.Contains(dec.text, "f16.f64") || strings.Contains(dec.text, "f64.f16") {
+ return true
+ }
+ // word 4320F02C: libopcodes says 'nopmi {44}'.
+ if hasPrefix(dec.text, "nop") && strings.Contains(dec.text, "{") {
+ return true
+ }
+ }
+
+ if hasPrefix(dec.text, "error:") && text == "undef" && inst.Enc == 0xf7fabcfd {
+ return true
+ }
+
+ // word 00f02053: libopcodes says 'noppl {0}'.
+ if hasPrefix(dec.text, "nop") && hasPrefix(text, "nop") && dec.text == text+" {0}" {
+ return true
+ }
+
+ // word F57FF04F. we say 'dsb #15', libopcodes says 'dsb sy'.
+ if hasPrefix(text, "dsb") && hasPrefix(dec.text, "dsb") {
+ return true
+ }
+ // word F57FF06F. we say 'isb #15', libopcodes says 'isb sy'.
+ if hasPrefix(text, "isb") && hasPrefix(dec.text, "isb") {
+ return true
+ }
+ // word F57FF053. we say 'dmb #3', libopcodes says 'dmb osh'.
+ if hasPrefix(text, "dmb") && hasPrefix(dec.text, "dmb") {
+ return true
+ }
+
+ // word 992D0000. push/stmdb with no registers (undefined).
+ // we say 'stmdbls sp!, {}', libopcodes says 'pushls {}'.
+ if hasPrefix(text, "stmdb") && hasPrefix(dec.text, "push") && strings.Contains(text, "{}") && strings.Contains(dec.text, "{}") {
+ return true
+ }
+
+ // word 28BD0000. pop/ldm with no registers (undefined).
+ // we say 'ldmcs sp!, {}', libopcodes says 'popcs {}'.
+ if hasPrefix(text, "ldm") && hasPrefix(dec.text, "pop") && strings.Contains(text, "{}") && strings.Contains(dec.text, "{}") {
+ return true
+ }
+
+ // word 014640F0.
+ // libopcodes emits #-0 for negative zero; we don't.
+ if strings.Replace(dec.text, "#-0", "#0", -1) == text || strings.Replace(dec.text, ", #-0", "", -1) == text {
+ return true
+ }
+
+ // word 91EF90F0. we say 'strdls r9, [pc, #0]!' but libopcodes says 'strdls r9, [pc]'.
+ // word D16F60F0. we say 'strdle r6, [pc, #0]!' but libopcodes says 'strdle r6, [pc, #-0]'.
+ if strings.Replace(text, ", #0]!", "]", -1) == strings.Replace(dec.text, ", #-0]", "]", -1) {
+ return true
+ }
+
+ // word 510F4000. we say apsr, libopcodes says CPSR.
+ if strings.Replace(dec.text, "CPSR", "apsr", -1) == text {
+ return true
+ }
+
+ // word 06A4B059.
+ // for ssat and usat, libopcodes decodes asr #0 as asr #0 but the manual seems to say it should be asr #32.
+ // There is never an asr #0.
+ if strings.Replace(dec.text, ", asr #0", ", asr #32", -1) == text {
+ return true
+ }
+
+ if len(dec.enc) >= 4 {
+ raw := binary.LittleEndian.Uint32(dec.enc[:4])
+
+ // word 21FFF0B5.
+ // the manual is clear that this is pre-indexed mode (with !) but libopcodes generates post-index (without !).
+ if raw&0x01200000 == 0x01200000 && strings.Replace(text, "!", "", -1) == dec.text {
+ return true
+ }
+
+ // word C100543E: libopcodes says tst, but no evidence for that.
+ if strings.HasPrefix(dec.text, "tst") && raw&0x0ff00000 != 0x03100000 && raw&0x0ff00000 != 0x01100000 {
+ return true
+ }
+
+ // word C3203CE8: libopcodes says teq, but no evidence for that.
+ if strings.HasPrefix(dec.text, "teq") && raw&0x0ff00000 != 0x03300000 && raw&0x0ff00000 != 0x01300000 {
+ return true
+ }
+
+ // word D14C552E: libopcodes says cmp but no evidence for that.
+ if strings.HasPrefix(dec.text, "cmp") && raw&0x0ff00000 != 0x03500000 && raw&0x0ff00000 != 0x01500000 {
+ return true
+ }
+
+ // word 2166AA4A: libopcodes says cmn but no evidence for that.
+ if strings.HasPrefix(dec.text, "cmn") && raw&0x0ff00000 != 0x03700000 && raw&0x0ff00000 != 0x01700000 {
+ return true
+ }
+
+ // word E70AEEEF: libopcodes says str but no evidence for that.
+ if strings.HasPrefix(dec.text, "str") && len(dec.text) >= 5 && (dec.text[3] == ' ' || dec.text[5] == ' ') && raw&0x0e500018 != 0x06000000 && raw&0x0e500000 != 0x0400000 {
+ return true
+ }
+
+ // word B0AF48F4: libopcodes says strd but P=0,W=1 which is unpredictable.
+ if hasPrefix(dec.text, "ldr", "str") && raw&0x01200000 == 0x00200000 {
+ return true
+ }
+
+ // word B6CC1C76: libopcodes inexplicably says 'uxtab16lt r1, ip, r6, ROR #24' instead of 'uxtab16lt r1, ip, r6, ror #24'
+ if strings.ToLower(dec.text) == text {
+ return true
+ }
+
+ // word F410FDA1: libopcodes says PLDW but the manual is clear that PLDW is F5/F7, not F4.
+ // word F7D0FB17: libopcodes says PLDW but the manual is clear that PLDW has 0x10 clear
+ if hasPrefix(dec.text, "pld") && raw&0xfd000010 != 0xf5000000 {
+ return true
+ }
+
+ // word F650FE14: libopcodes says PLI but the manual is clear that PLI has 0x10 clear
+ if hasPrefix(dec.text, "pli") && raw&0xff000010 != 0xf6000000 {
+ return true
+ }
+ }
+
+ return false
+}
+
+// Instructions known to libopcodes (or xed) but not to us.
+// Most of these are floating point coprocessor instructions.
+var unsupported = strings.Fields(`
+ abs
+ acs
+ adf
+ aes
+ asn
+ atn
+ cdp
+ cf
+ cmf
+ cnf
+ cos
+ cps
+ crc32
+ dvf
+ eret
+ exp
+ fadd
+ fcmp
+ fcpy
+ fcvt
+ fdiv
+ fdv
+ fix
+ fld
+ flt
+ fmac
+ fmd
+ fml
+ fmr
+ fms
+ fmul
+ fmx
+ fneg
+ fnm
+ frd
+ fsit
+ fsq
+ fst
+ fsu
+ fto
+ fui
+ hlt
+ hvc
+ lda
+ ldc
+ ldf
+ lfm
+ lgn
+ log
+ mar
+ mcr
+ mcrr
+ mia
+ mnf
+ mra
+ mrc
+ mrrc
+ mrs
+ msr
+ msr
+ muf
+ mvf
+ nrm
+ pol
+ pow
+ rdf
+ rfc
+ rfe
+ rfs
+ rmf
+ rnd
+ rpw
+ rsf
+ sdiv
+ sev
+ sfm
+ sha1
+ sha256
+ sin
+ smc
+ sqt
+ srs
+ stc
+ stf
+ stl
+ suf
+ tan
+ udf
+ udiv
+ urd
+ vfma
+ vfms
+ vfnma
+ vfnms
+ vrint
+ wfc
+ wfs
+`)
diff --git a/arm/armasm/objdumpext_test.go b/arm/armasm/objdumpext_test.go
new file mode 100644
index 0000000..52497a5
--- /dev/null
+++ b/arm/armasm/objdumpext_test.go
@@ -0,0 +1,259 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Copied and simplified from ../../x86/x86asm/objdumpext_test.go.
+
+package armasm
+
+import (
+ "bytes"
+ "debug/elf"
+ "encoding/binary"
+ "fmt"
+ "io"
+ "log"
+ "os"
+ "strconv"
+ "strings"
+ "testing"
+)
+
+const objdumpPath = "/usr/local/bin/arm-linux-elf-objdump"
+
+func testObjdumpARM(t *testing.T, generate func(func([]byte))) {
+ testObjdumpArch(t, generate, ModeARM)
+}
+
+func testObjdumpArch(t *testing.T, generate func(func([]byte)), arch Mode) {
+ if _, err := os.Stat(objdumpPath); err != nil {
+ if !testing.Short() {
+ t.Fatal(err)
+ }
+ t.Skip(err)
+ }
+
+ testExtDis(t, "gnu", arch, objdump, generate, allowedMismatchObjdump)
+}
+
+func objdump(ext *ExtDis) error {
+ // File already written with instructions; add ELF header.
+ if ext.Arch == ModeARM {
+ if err := writeELF32(ext.File, ext.Size); err != nil {
+ return err
+ }
+ } else {
+ panic("unknown arch")
+ }
+
+ b, err := ext.Run(objdumpPath, "-d", "-z", ext.File.Name())
+ if err != nil {
+ return err
+ }
+
+ var (
+ nmatch int
+ reading bool
+ next uint32 = start
+ addr uint32
+ encbuf [4]byte
+ enc []byte
+ text string
+ )
+ flush := func() {
+ if addr == next {
+ if m := pcrel.FindStringSubmatch(text); m != nil {
+ targ, _ := strconv.ParseUint(m[2], 16, 64)
+ text = fmt.Sprintf("%s .%+#x", m[1], int32(uint32(targ)-addr-uint32(len(enc))))
+ }
+ if strings.HasPrefix(text, "stmia") {
+ text = "stm" + text[5:]
+ }
+ if strings.HasPrefix(text, "stmfd") {
+ text = "stmdb" + text[5:]
+ }
+ if strings.HasPrefix(text, "ldmfd") {
+ text = "ldm" + text[5:]
+ }
+ text = strings.Replace(text, "#0.0", "#0", -1)
+ if text == "undefined" && len(enc) == 4 {
+ text = "error: unknown instruction"
+ enc = nil
+ }
+ if len(enc) == 4 {
+ // prints as word but we want to record bytes
+ enc[0], enc[3] = enc[3], enc[0]
+ enc[1], enc[2] = enc[2], enc[1]
+ }
+ ext.Dec <- ExtInst{addr, encbuf, len(enc), text}
+ encbuf = [4]byte{}
+ enc = nil
+ next += 4
+ }
+ }
+ var textangle = []byte("<.text>:")
+ for {
+ line, err := b.ReadSlice('\n')
+ if err != nil {
+ if err == io.EOF {
+ break
+ }
+ return fmt.Errorf("reading objdump output: %v", err)
+ }
+ if bytes.Contains(line, textangle) {
+ reading = true
+ continue
+ }
+ if !reading {
+ continue
+ }
+ if debug {
+ os.Stdout.Write(line)
+ }
+ if enc1 := parseContinuation(line, encbuf[:len(enc)]); enc1 != nil {
+ enc = enc1
+ continue
+ }
+ flush()
+ nmatch++
+ addr, enc, text = parseLine(line, encbuf[:0])
+ if addr > next {
+ return fmt.Errorf("address out of sync expected <= %#x at %q in:\n%s", next, line, line)
+ }
+ }
+ flush()
+ if next != start+uint32(ext.Size) {
+ return fmt.Errorf("not enough results found [%d %d]", next, start+ext.Size)
+ }
+ if err := ext.Wait(); err != nil {
+ return fmt.Errorf("exec: %v", err)
+ }
+
+ return nil
+}
+
+var (
+ undefined = []byte("<UNDEFINED>")
+ unpredictable = []byte("<UNPREDICTABLE>")
+ illegalShifter = []byte("<illegal shifter operand>")
+)
+
+func parseLine(line []byte, encstart []byte) (addr uint32, enc []byte, text string) {
+ oline := line
+ i := index(line, ":\t")
+ if i < 0 {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ x, err := strconv.ParseUint(string(trimSpace(line[:i])), 16, 32)
+ if err != nil {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ addr = uint32(x)
+ line = line[i+2:]
+ i = bytes.IndexByte(line, '\t')
+ if i < 0 {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ enc, ok := parseHex(line[:i], encstart)
+ if !ok {
+ log.Fatalf("cannot parse disassembly: %q", oline)
+ }
+ line = trimSpace(line[i:])
+ if bytes.Contains(line, undefined) {
+ text = "undefined"
+ return
+ }
+ if bytes.Contains(line, illegalShifter) {
+ text = "undefined"
+ return
+ }
+ if false && bytes.Contains(line, unpredictable) {
+ text = "unpredictable"
+ return
+ }
+ if i := bytes.IndexByte(line, ';'); i >= 0 {
+ line = trimSpace(line[:i])
+ }
+ text = string(fixSpace(line))
+ return
+}
+
+func parseContinuation(line []byte, enc []byte) []byte {
+ i := index(line, ":\t")
+ if i < 0 {
+ return nil
+ }
+ line = line[i+1:]
+ enc, _ = parseHex(line, enc)
+ return enc
+}
+
+// writeELF32 writes an ELF32 header to the file,
+// describing a text segment that starts at start
+// and extends for size bytes.
+func writeELF32(f *os.File, size int) error {
+ f.Seek(0, 0)
+ var hdr elf.Header32
+ var prog elf.Prog32
+ var sect elf.Section32
+ var buf bytes.Buffer
+ binary.Write(&buf, binary.LittleEndian, &hdr)
+ off1 := buf.Len()
+ binary.Write(&buf, binary.LittleEndian, &prog)
+ off2 := buf.Len()
+ binary.Write(&buf, binary.LittleEndian, §)
+ off3 := buf.Len()
+ buf.Reset()
+ data := byte(elf.ELFDATA2LSB)
+ hdr = elf.Header32{
+ Ident: [16]byte{0x7F, 'E', 'L', 'F', 1, data, 1},
+ Type: 2,
+ Machine: uint16(elf.EM_ARM),
+ Version: 1,
+ Entry: start,
+ Phoff: uint32(off1),
+ Shoff: uint32(off2),
+ Flags: 0x05000002,
+ Ehsize: uint16(off1),
+ Phentsize: uint16(off2 - off1),
+ Phnum: 1,
+ Shentsize: uint16(off3 - off2),
+ Shnum: 3,
+ Shstrndx: 2,
+ }
+ binary.Write(&buf, binary.LittleEndian, &hdr)
+ prog = elf.Prog32{
+ Type: 1,
+ Off: start,
+ Vaddr: start,
+ Paddr: start,
+ Filesz: uint32(size),
+ Memsz: uint32(size),
+ Flags: 5,
+ Align: start,
+ }
+ binary.Write(&buf, binary.LittleEndian, &prog)
+ binary.Write(&buf, binary.LittleEndian, §) // NULL section
+ sect = elf.Section32{
+ Name: 1,
+ Type: uint32(elf.SHT_PROGBITS),
+ Addr: start,
+ Off: start,
+ Size: uint32(size),
+ Flags: uint32(elf.SHF_ALLOC | elf.SHF_EXECINSTR),
+ Addralign: 4,
+ }
+ binary.Write(&buf, binary.LittleEndian, §) // .text
+ sect = elf.Section32{
+ Name: uint32(len("\x00.text\x00")),
+ Type: uint32(elf.SHT_STRTAB),
+ Addr: 0,
+ Off: uint32(off2 + (off3-off2)*3),
+ Size: uint32(len("\x00.text\x00.shstrtab\x00")),
+ Addralign: 1,
+ }
+ binary.Write(&buf, binary.LittleEndian, §)
+ buf.WriteString("\x00.text\x00.shstrtab\x00")
+ f.Write(buf.Bytes())
+ return nil
+}
diff --git a/arm/armasm/plan9x.go b/arm/armasm/plan9x.go
new file mode 100644
index 0000000..73173fd
--- /dev/null
+++ b/arm/armasm/plan9x.go
@@ -0,0 +1,211 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package armasm
+
+import (
+ "bytes"
+ "encoding/binary"
+ "fmt"
+ "io"
+ "strings"
+)
+
+// plan9Syntax returns the Go assembler syntax for the instruction.
+// The syntax was originally defined by Plan 9.
+// The pc is the program counter of the instruction, used for expanding
+// PC-relative addresses into absolute ones.
+// The symname function queries the symbol table for the program
+// being disassembled. Given a target address it returns the name and base
+// address of the symbol containing the target, if any; otherwise it returns "", 0.
+// The reader r should read from the text segment using text addresses
+// as offsets; it is used to display pc-relative loads as constant loads.
+func plan9Syntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string {
+ if symname == nil {
+ symname = func(uint64) (string, uint64) { return "", 0 }
+ }
+
+ var args []string
+ for _, a := range inst.Args {
+ if a == nil {
+ break
+ }
+ args = append(args, plan9Arg(&inst, pc, symname, a))
+ }
+
+ op := inst.Op.String()
+
+ switch inst.Op &^ 15 {
+ case LDR_EQ, LDRB_EQ, LDRH_EQ:
+ // Check for RET
+ reg, _ := inst.Args[0].(Reg)
+ mem, _ := inst.Args[1].(Mem)
+ if inst.Op&^15 == LDR_EQ && reg == R15 && mem.Base == SP && mem.Sign == 0 && mem.Mode == AddrPostIndex {
+ return fmt.Sprintf("RET%s #%d", op[3:], mem.Offset)
+ }
+
+ // Check for PC-relative load.
+ if mem.Base == PC && mem.Sign == 0 && mem.Mode == AddrOffset && text != nil {
+ addr := uint32(pc) + 8 + uint32(mem.Offset)
+ buf := make([]byte, 4)
+ switch inst.Op &^ 15 {
+ case LDRB_EQ:
+ if _, err := text.ReadAt(buf[:1], int64(addr)); err != nil {
+ break
+ }
+ args[1] = fmt.Sprintf("$%#x", buf[0])
+
+ case LDRH_EQ:
+ if _, err := text.ReadAt(buf[:2], int64(addr)); err != nil {
+ break
+ }
+ args[1] = fmt.Sprintf("$%#x", binary.LittleEndian.Uint16(buf))
+
+ case LDR_EQ:
+ if _, err := text.ReadAt(buf, int64(addr)); err != nil {
+ break
+ }
+ x := binary.LittleEndian.Uint32(buf)
+ if s, base := symname(uint64(x)); s != "" && uint64(x) == base {
+ args[1] = fmt.Sprintf("$%s(SB)", s)
+ } else {
+ args[1] = fmt.Sprintf("$%#x", x)
+ }
+ }
+ }
+ }
+
+ // Move addressing mode into opcode suffix.
+ suffix := ""
+ switch inst.Op &^ 15 {
+ case LDR_EQ, LDRB_EQ, LDRH_EQ, STR_EQ, STRB_EQ, STRH_EQ:
+ mem, _ := inst.Args[1].(Mem)
+ switch mem.Mode {
+ case AddrOffset, AddrLDM:
+ // no suffix
+ case AddrPreIndex, AddrLDM_WB:
+ suffix = ".W"
+ case AddrPostIndex:
+ suffix = ".P"
+ }
+ off := ""
+ if mem.Offset != 0 {
+ off = fmt.Sprintf("%#x", mem.Offset)
+ }
+ base := fmt.Sprintf("(R%d)", int(mem.Base))
+ index := ""
+ if mem.Sign != 0 {
+ sign := ""
+ if mem.Sign < 0 {
+ sign = ""
+ }
+ shift := ""
+ if mem.Count != 0 {
+ shift = fmt.Sprintf("%s%d", plan9Shift[mem.Shift], mem.Count)
+ }
+ index = fmt.Sprintf("(%sR%d%s)", sign, int(mem.Index), shift)
+ }
+ args[1] = off + base + index
+ }
+
+ // Reverse args, placing dest last.
+ for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 {
+ args[i], args[j] = args[j], args[i]
+ }
+
+ switch inst.Op &^ 15 {
+ case MOV_EQ:
+ op = "MOVW" + op[3:]
+
+ case LDR_EQ:
+ op = "MOVW" + op[3:] + suffix
+ case LDRB_EQ:
+ op = "MOVB" + op[4:] + suffix
+ case LDRH_EQ:
+ op = "MOVH" + op[4:] + suffix
+
+ case STR_EQ:
+ op = "MOVW" + op[3:] + suffix
+ args[0], args[1] = args[1], args[0]
+ case STRB_EQ:
+ op = "MOVB" + op[4:] + suffix
+ args[0], args[1] = args[1], args[0]
+ case STRH_EQ:
+ op = "MOVH" + op[4:] + suffix
+ args[0], args[1] = args[1], args[0]
+ }
+
+ if args != nil {
+ op += " " + strings.Join(args, ", ")
+ }
+
+ return op
+}
+
+// assembler syntax for the various shifts.
+// @x> is a lie; the assembler uses @> 0
+// instead of @x> 1, but i wanted to be clear that it
+// was a different operation (rotate right extended, not rotate right).
+var plan9Shift = []string{"<<", ">>", "->", "@>", "@x>"}
+
+func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string {
+ switch a := arg.(type) {
+ case Endian:
+
+ case Imm:
+ return fmt.Sprintf("$%d", int(a))
+
+ case Mem:
+
+ case PCRel:
+ addr := uint32(pc) + 8 + uint32(a)
+ if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base {
+ return fmt.Sprintf("%s(SB)", s)
+ }
+ return fmt.Sprintf("%#x", addr)
+
+ case Reg:
+ if a < 16 {
+ return fmt.Sprintf("R%d", int(a))
+ }
+
+ case RegList:
+ var buf bytes.Buffer
+ start := -2
+ end := -2
+ fmt.Fprintf(&buf, "[")
+ flush := func() {
+ if start >= 0 {
+ if buf.Len() > 1 {
+ fmt.Fprintf(&buf, ",")
+ }
+ if start == end {
+ fmt.Fprintf(&buf, "R%d", start)
+ } else {
+ fmt.Fprintf(&buf, "R%d-R%d", start, end)
+ }
+ }
+ }
+ for i := 0; i < 16; i++ {
+ if a&(1<<uint(i)) != 0 {
+ if i == end+1 {
+ end++
+ continue
+ }
+ start = i
+ end = i
+ }
+ }
+ flush()
+ fmt.Fprintf(&buf, "]")
+ return buf.String()
+
+ case RegShift:
+ return fmt.Sprintf("R%d%s$%d", int(a.Reg), plan9Shift[a.Shift], int(a.Count))
+
+ case RegShiftReg:
+ return fmt.Sprintf("R%d%sR%d", int(a.Reg), plan9Shift[a.Shift], int(a.RegCount))
+ }
+ return strings.ToUpper(arg.String())
+}
diff --git a/arm/armasm/tables.go b/arm/armasm/tables.go
new file mode 100644
index 0000000..58f51fe
--- /dev/null
+++ b/arm/armasm/tables.go
@@ -0,0 +1,9448 @@
+package armasm
+
+const (
+ _ Op = iota
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ ADC_EQ
+ ADC_NE
+ ADC_CS
+ ADC_CC
+ ADC_MI
+ ADC_PL
+ ADC_VS
+ ADC_VC
+ ADC_HI
+ ADC_LS
+ ADC_GE
+ ADC_LT
+ ADC_GT
+ ADC_LE
+ ADC
+ ADC_ZZ
+ ADC_S_EQ
+ ADC_S_NE
+ ADC_S_CS
+ ADC_S_CC
+ ADC_S_MI
+ ADC_S_PL
+ ADC_S_VS
+ ADC_S_VC
+ ADC_S_HI
+ ADC_S_LS
+ ADC_S_GE
+ ADC_S_LT
+ ADC_S_GT
+ ADC_S_LE
+ ADC_S
+ ADC_S_ZZ
+ ADD_EQ
+ ADD_NE
+ ADD_CS
+ ADD_CC
+ ADD_MI
+ ADD_PL
+ ADD_VS
+ ADD_VC
+ ADD_HI
+ ADD_LS
+ ADD_GE
+ ADD_LT
+ ADD_GT
+ ADD_LE
+ ADD
+ ADD_ZZ
+ ADD_S_EQ
+ ADD_S_NE
+ ADD_S_CS
+ ADD_S_CC
+ ADD_S_MI
+ ADD_S_PL
+ ADD_S_VS
+ ADD_S_VC
+ ADD_S_HI
+ ADD_S_LS
+ ADD_S_GE
+ ADD_S_LT
+ ADD_S_GT
+ ADD_S_LE
+ ADD_S
+ ADD_S_ZZ
+ AND_EQ
+ AND_NE
+ AND_CS
+ AND_CC
+ AND_MI
+ AND_PL
+ AND_VS
+ AND_VC
+ AND_HI
+ AND_LS
+ AND_GE
+ AND_LT
+ AND_GT
+ AND_LE
+ AND
+ AND_ZZ
+ AND_S_EQ
+ AND_S_NE
+ AND_S_CS
+ AND_S_CC
+ AND_S_MI
+ AND_S_PL
+ AND_S_VS
+ AND_S_VC
+ AND_S_HI
+ AND_S_LS
+ AND_S_GE
+ AND_S_LT
+ AND_S_GT
+ AND_S_LE
+ AND_S
+ AND_S_ZZ
+ ASR_EQ
+ ASR_NE
+ ASR_CS
+ ASR_CC
+ ASR_MI
+ ASR_PL
+ ASR_VS
+ ASR_VC
+ ASR_HI
+ ASR_LS
+ ASR_GE
+ ASR_LT
+ ASR_GT
+ ASR_LE
+ ASR
+ ASR_ZZ
+ ASR_S_EQ
+ ASR_S_NE
+ ASR_S_CS
+ ASR_S_CC
+ ASR_S_MI
+ ASR_S_PL
+ ASR_S_VS
+ ASR_S_VC
+ ASR_S_HI
+ ASR_S_LS
+ ASR_S_GE
+ ASR_S_LT
+ ASR_S_GT
+ ASR_S_LE
+ ASR_S
+ ASR_S_ZZ
+ B_EQ
+ B_NE
+ B_CS
+ B_CC
+ B_MI
+ B_PL
+ B_VS
+ B_VC
+ B_HI
+ B_LS
+ B_GE
+ B_LT
+ B_GT
+ B_LE
+ B
+ B_ZZ
+ BFC_EQ
+ BFC_NE
+ BFC_CS
+ BFC_CC
+ BFC_MI
+ BFC_PL
+ BFC_VS
+ BFC_VC
+ BFC_HI
+ BFC_LS
+ BFC_GE
+ BFC_LT
+ BFC_GT
+ BFC_LE
+ BFC
+ BFC_ZZ
+ BFI_EQ
+ BFI_NE
+ BFI_CS
+ BFI_CC
+ BFI_MI
+ BFI_PL
+ BFI_VS
+ BFI_VC
+ BFI_HI
+ BFI_LS
+ BFI_GE
+ BFI_LT
+ BFI_GT
+ BFI_LE
+ BFI
+ BFI_ZZ
+ BIC_EQ
+ BIC_NE
+ BIC_CS
+ BIC_CC
+ BIC_MI
+ BIC_PL
+ BIC_VS
+ BIC_VC
+ BIC_HI
+ BIC_LS
+ BIC_GE
+ BIC_LT
+ BIC_GT
+ BIC_LE
+ BIC
+ BIC_ZZ
+ BIC_S_EQ
+ BIC_S_NE
+ BIC_S_CS
+ BIC_S_CC
+ BIC_S_MI
+ BIC_S_PL
+ BIC_S_VS
+ BIC_S_VC
+ BIC_S_HI
+ BIC_S_LS
+ BIC_S_GE
+ BIC_S_LT
+ BIC_S_GT
+ BIC_S_LE
+ BIC_S
+ BIC_S_ZZ
+ BKPT_EQ
+ BKPT_NE
+ BKPT_CS
+ BKPT_CC
+ BKPT_MI
+ BKPT_PL
+ BKPT_VS
+ BKPT_VC
+ BKPT_HI
+ BKPT_LS
+ BKPT_GE
+ BKPT_LT
+ BKPT_GT
+ BKPT_LE
+ BKPT
+ BKPT_ZZ
+ BL_EQ
+ BL_NE
+ BL_CS
+ BL_CC
+ BL_MI
+ BL_PL
+ BL_VS
+ BL_VC
+ BL_HI
+ BL_LS
+ BL_GE
+ BL_LT
+ BL_GT
+ BL_LE
+ BL
+ BL_ZZ
+ BLX_EQ
+ BLX_NE
+ BLX_CS
+ BLX_CC
+ BLX_MI
+ BLX_PL
+ BLX_VS
+ BLX_VC
+ BLX_HI
+ BLX_LS
+ BLX_GE
+ BLX_LT
+ BLX_GT
+ BLX_LE
+ BLX
+ BLX_ZZ
+ BX_EQ
+ BX_NE
+ BX_CS
+ BX_CC
+ BX_MI
+ BX_PL
+ BX_VS
+ BX_VC
+ BX_HI
+ BX_LS
+ BX_GE
+ BX_LT
+ BX_GT
+ BX_LE
+ BX
+ BX_ZZ
+ BXJ_EQ
+ BXJ_NE
+ BXJ_CS
+ BXJ_CC
+ BXJ_MI
+ BXJ_PL
+ BXJ_VS
+ BXJ_VC
+ BXJ_HI
+ BXJ_LS
+ BXJ_GE
+ BXJ_LT
+ BXJ_GT
+ BXJ_LE
+ BXJ
+ BXJ_ZZ
+ CLREX
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ CLZ_EQ
+ CLZ_NE
+ CLZ_CS
+ CLZ_CC
+ CLZ_MI
+ CLZ_PL
+ CLZ_VS
+ CLZ_VC
+ CLZ_HI
+ CLZ_LS
+ CLZ_GE
+ CLZ_LT
+ CLZ_GT
+ CLZ_LE
+ CLZ
+ CLZ_ZZ
+ CMN_EQ
+ CMN_NE
+ CMN_CS
+ CMN_CC
+ CMN_MI
+ CMN_PL
+ CMN_VS
+ CMN_VC
+ CMN_HI
+ CMN_LS
+ CMN_GE
+ CMN_LT
+ CMN_GT
+ CMN_LE
+ CMN
+ CMN_ZZ
+ CMP_EQ
+ CMP_NE
+ CMP_CS
+ CMP_CC
+ CMP_MI
+ CMP_PL
+ CMP_VS
+ CMP_VC
+ CMP_HI
+ CMP_LS
+ CMP_GE
+ CMP_LT
+ CMP_GT
+ CMP_LE
+ CMP
+ CMP_ZZ
+ DBG_EQ
+ DBG_NE
+ DBG_CS
+ DBG_CC
+ DBG_MI
+ DBG_PL
+ DBG_VS
+ DBG_VC
+ DBG_HI
+ DBG_LS
+ DBG_GE
+ DBG_LT
+ DBG_GT
+ DBG_LE
+ DBG
+ DBG_ZZ
+ DMB
+ DSB
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ EOR_EQ
+ EOR_NE
+ EOR_CS
+ EOR_CC
+ EOR_MI
+ EOR_PL
+ EOR_VS
+ EOR_VC
+ EOR_HI
+ EOR_LS
+ EOR_GE
+ EOR_LT
+ EOR_GT
+ EOR_LE
+ EOR
+ EOR_ZZ
+ EOR_S_EQ
+ EOR_S_NE
+ EOR_S_CS
+ EOR_S_CC
+ EOR_S_MI
+ EOR_S_PL
+ EOR_S_VS
+ EOR_S_VC
+ EOR_S_HI
+ EOR_S_LS
+ EOR_S_GE
+ EOR_S_LT
+ EOR_S_GT
+ EOR_S_LE
+ EOR_S
+ EOR_S_ZZ
+ ISB
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ LDM_EQ
+ LDM_NE
+ LDM_CS
+ LDM_CC
+ LDM_MI
+ LDM_PL
+ LDM_VS
+ LDM_VC
+ LDM_HI
+ LDM_LS
+ LDM_GE
+ LDM_LT
+ LDM_GT
+ LDM_LE
+ LDM
+ LDM_ZZ
+ LDMDA_EQ
+ LDMDA_NE
+ LDMDA_CS
+ LDMDA_CC
+ LDMDA_MI
+ LDMDA_PL
+ LDMDA_VS
+ LDMDA_VC
+ LDMDA_HI
+ LDMDA_LS
+ LDMDA_GE
+ LDMDA_LT
+ LDMDA_GT
+ LDMDA_LE
+ LDMDA
+ LDMDA_ZZ
+ LDMDB_EQ
+ LDMDB_NE
+ LDMDB_CS
+ LDMDB_CC
+ LDMDB_MI
+ LDMDB_PL
+ LDMDB_VS
+ LDMDB_VC
+ LDMDB_HI
+ LDMDB_LS
+ LDMDB_GE
+ LDMDB_LT
+ LDMDB_GT
+ LDMDB_LE
+ LDMDB
+ LDMDB_ZZ
+ LDMIB_EQ
+ LDMIB_NE
+ LDMIB_CS
+ LDMIB_CC
+ LDMIB_MI
+ LDMIB_PL
+ LDMIB_VS
+ LDMIB_VC
+ LDMIB_HI
+ LDMIB_LS
+ LDMIB_GE
+ LDMIB_LT
+ LDMIB_GT
+ LDMIB_LE
+ LDMIB
+ LDMIB_ZZ
+ LDR_EQ
+ LDR_NE
+ LDR_CS
+ LDR_CC
+ LDR_MI
+ LDR_PL
+ LDR_VS
+ LDR_VC
+ LDR_HI
+ LDR_LS
+ LDR_GE
+ LDR_LT
+ LDR_GT
+ LDR_LE
+ LDR
+ LDR_ZZ
+ LDRB_EQ
+ LDRB_NE
+ LDRB_CS
+ LDRB_CC
+ LDRB_MI
+ LDRB_PL
+ LDRB_VS
+ LDRB_VC
+ LDRB_HI
+ LDRB_LS
+ LDRB_GE
+ LDRB_LT
+ LDRB_GT
+ LDRB_LE
+ LDRB
+ LDRB_ZZ
+ LDRBT_EQ
+ LDRBT_NE
+ LDRBT_CS
+ LDRBT_CC
+ LDRBT_MI
+ LDRBT_PL
+ LDRBT_VS
+ LDRBT_VC
+ LDRBT_HI
+ LDRBT_LS
+ LDRBT_GE
+ LDRBT_LT
+ LDRBT_GT
+ LDRBT_LE
+ LDRBT
+ LDRBT_ZZ
+ LDRD_EQ
+ LDRD_NE
+ LDRD_CS
+ LDRD_CC
+ LDRD_MI
+ LDRD_PL
+ LDRD_VS
+ LDRD_VC
+ LDRD_HI
+ LDRD_LS
+ LDRD_GE
+ LDRD_LT
+ LDRD_GT
+ LDRD_LE
+ LDRD
+ LDRD_ZZ
+ LDREX_EQ
+ LDREX_NE
+ LDREX_CS
+ LDREX_CC
+ LDREX_MI
+ LDREX_PL
+ LDREX_VS
+ LDREX_VC
+ LDREX_HI
+ LDREX_LS
+ LDREX_GE
+ LDREX_LT
+ LDREX_GT
+ LDREX_LE
+ LDREX
+ LDREX_ZZ
+ LDREXB_EQ
+ LDREXB_NE
+ LDREXB_CS
+ LDREXB_CC
+ LDREXB_MI
+ LDREXB_PL
+ LDREXB_VS
+ LDREXB_VC
+ LDREXB_HI
+ LDREXB_LS
+ LDREXB_GE
+ LDREXB_LT
+ LDREXB_GT
+ LDREXB_LE
+ LDREXB
+ LDREXB_ZZ
+ LDREXD_EQ
+ LDREXD_NE
+ LDREXD_CS
+ LDREXD_CC
+ LDREXD_MI
+ LDREXD_PL
+ LDREXD_VS
+ LDREXD_VC
+ LDREXD_HI
+ LDREXD_LS
+ LDREXD_GE
+ LDREXD_LT
+ LDREXD_GT
+ LDREXD_LE
+ LDREXD
+ LDREXD_ZZ
+ LDREXH_EQ
+ LDREXH_NE
+ LDREXH_CS
+ LDREXH_CC
+ LDREXH_MI
+ LDREXH_PL
+ LDREXH_VS
+ LDREXH_VC
+ LDREXH_HI
+ LDREXH_LS
+ LDREXH_GE
+ LDREXH_LT
+ LDREXH_GT
+ LDREXH_LE
+ LDREXH
+ LDREXH_ZZ
+ LDRH_EQ
+ LDRH_NE
+ LDRH_CS
+ LDRH_CC
+ LDRH_MI
+ LDRH_PL
+ LDRH_VS
+ LDRH_VC
+ LDRH_HI
+ LDRH_LS
+ LDRH_GE
+ LDRH_LT
+ LDRH_GT
+ LDRH_LE
+ LDRH
+ LDRH_ZZ
+ LDRHT_EQ
+ LDRHT_NE
+ LDRHT_CS
+ LDRHT_CC
+ LDRHT_MI
+ LDRHT_PL
+ LDRHT_VS
+ LDRHT_VC
+ LDRHT_HI
+ LDRHT_LS
+ LDRHT_GE
+ LDRHT_LT
+ LDRHT_GT
+ LDRHT_LE
+ LDRHT
+ LDRHT_ZZ
+ LDRSB_EQ
+ LDRSB_NE
+ LDRSB_CS
+ LDRSB_CC
+ LDRSB_MI
+ LDRSB_PL
+ LDRSB_VS
+ LDRSB_VC
+ LDRSB_HI
+ LDRSB_LS
+ LDRSB_GE
+ LDRSB_LT
+ LDRSB_GT
+ LDRSB_LE
+ LDRSB
+ LDRSB_ZZ
+ LDRSBT_EQ
+ LDRSBT_NE
+ LDRSBT_CS
+ LDRSBT_CC
+ LDRSBT_MI
+ LDRSBT_PL
+ LDRSBT_VS
+ LDRSBT_VC
+ LDRSBT_HI
+ LDRSBT_LS
+ LDRSBT_GE
+ LDRSBT_LT
+ LDRSBT_GT
+ LDRSBT_LE
+ LDRSBT
+ LDRSBT_ZZ
+ LDRSH_EQ
+ LDRSH_NE
+ LDRSH_CS
+ LDRSH_CC
+ LDRSH_MI
+ LDRSH_PL
+ LDRSH_VS
+ LDRSH_VC
+ LDRSH_HI
+ LDRSH_LS
+ LDRSH_GE
+ LDRSH_LT
+ LDRSH_GT
+ LDRSH_LE
+ LDRSH
+ LDRSH_ZZ
+ LDRSHT_EQ
+ LDRSHT_NE
+ LDRSHT_CS
+ LDRSHT_CC
+ LDRSHT_MI
+ LDRSHT_PL
+ LDRSHT_VS
+ LDRSHT_VC
+ LDRSHT_HI
+ LDRSHT_LS
+ LDRSHT_GE
+ LDRSHT_LT
+ LDRSHT_GT
+ LDRSHT_LE
+ LDRSHT
+ LDRSHT_ZZ
+ LDRT_EQ
+ LDRT_NE
+ LDRT_CS
+ LDRT_CC
+ LDRT_MI
+ LDRT_PL
+ LDRT_VS
+ LDRT_VC
+ LDRT_HI
+ LDRT_LS
+ LDRT_GE
+ LDRT_LT
+ LDRT_GT
+ LDRT_LE
+ LDRT
+ LDRT_ZZ
+ LSL_EQ
+ LSL_NE
+ LSL_CS
+ LSL_CC
+ LSL_MI
+ LSL_PL
+ LSL_VS
+ LSL_VC
+ LSL_HI
+ LSL_LS
+ LSL_GE
+ LSL_LT
+ LSL_GT
+ LSL_LE
+ LSL
+ LSL_ZZ
+ LSL_S_EQ
+ LSL_S_NE
+ LSL_S_CS
+ LSL_S_CC
+ LSL_S_MI
+ LSL_S_PL
+ LSL_S_VS
+ LSL_S_VC
+ LSL_S_HI
+ LSL_S_LS
+ LSL_S_GE
+ LSL_S_LT
+ LSL_S_GT
+ LSL_S_LE
+ LSL_S
+ LSL_S_ZZ
+ LSR_EQ
+ LSR_NE
+ LSR_CS
+ LSR_CC
+ LSR_MI
+ LSR_PL
+ LSR_VS
+ LSR_VC
+ LSR_HI
+ LSR_LS
+ LSR_GE
+ LSR_LT
+ LSR_GT
+ LSR_LE
+ LSR
+ LSR_ZZ
+ LSR_S_EQ
+ LSR_S_NE
+ LSR_S_CS
+ LSR_S_CC
+ LSR_S_MI
+ LSR_S_PL
+ LSR_S_VS
+ LSR_S_VC
+ LSR_S_HI
+ LSR_S_LS
+ LSR_S_GE
+ LSR_S_LT
+ LSR_S_GT
+ LSR_S_LE
+ LSR_S
+ LSR_S_ZZ
+ MLA_EQ
+ MLA_NE
+ MLA_CS
+ MLA_CC
+ MLA_MI
+ MLA_PL
+ MLA_VS
+ MLA_VC
+ MLA_HI
+ MLA_LS
+ MLA_GE
+ MLA_LT
+ MLA_GT
+ MLA_LE
+ MLA
+ MLA_ZZ
+ MLA_S_EQ
+ MLA_S_NE
+ MLA_S_CS
+ MLA_S_CC
+ MLA_S_MI
+ MLA_S_PL
+ MLA_S_VS
+ MLA_S_VC
+ MLA_S_HI
+ MLA_S_LS
+ MLA_S_GE
+ MLA_S_LT
+ MLA_S_GT
+ MLA_S_LE
+ MLA_S
+ MLA_S_ZZ
+ MLS_EQ
+ MLS_NE
+ MLS_CS
+ MLS_CC
+ MLS_MI
+ MLS_PL
+ MLS_VS
+ MLS_VC
+ MLS_HI
+ MLS_LS
+ MLS_GE
+ MLS_LT
+ MLS_GT
+ MLS_LE
+ MLS
+ MLS_ZZ
+ MOV_EQ
+ MOV_NE
+ MOV_CS
+ MOV_CC
+ MOV_MI
+ MOV_PL
+ MOV_VS
+ MOV_VC
+ MOV_HI
+ MOV_LS
+ MOV_GE
+ MOV_LT
+ MOV_GT
+ MOV_LE
+ MOV
+ MOV_ZZ
+ MOV_S_EQ
+ MOV_S_NE
+ MOV_S_CS
+ MOV_S_CC
+ MOV_S_MI
+ MOV_S_PL
+ MOV_S_VS
+ MOV_S_VC
+ MOV_S_HI
+ MOV_S_LS
+ MOV_S_GE
+ MOV_S_LT
+ MOV_S_GT
+ MOV_S_LE
+ MOV_S
+ MOV_S_ZZ
+ MOVT_EQ
+ MOVT_NE
+ MOVT_CS
+ MOVT_CC
+ MOVT_MI
+ MOVT_PL
+ MOVT_VS
+ MOVT_VC
+ MOVT_HI
+ MOVT_LS
+ MOVT_GE
+ MOVT_LT
+ MOVT_GT
+ MOVT_LE
+ MOVT
+ MOVT_ZZ
+ MOVW_EQ
+ MOVW_NE
+ MOVW_CS
+ MOVW_CC
+ MOVW_MI
+ MOVW_PL
+ MOVW_VS
+ MOVW_VC
+ MOVW_HI
+ MOVW_LS
+ MOVW_GE
+ MOVW_LT
+ MOVW_GT
+ MOVW_LE
+ MOVW
+ MOVW_ZZ
+ MRS_EQ
+ MRS_NE
+ MRS_CS
+ MRS_CC
+ MRS_MI
+ MRS_PL
+ MRS_VS
+ MRS_VC
+ MRS_HI
+ MRS_LS
+ MRS_GE
+ MRS_LT
+ MRS_GT
+ MRS_LE
+ MRS
+ MRS_ZZ
+ MUL_EQ
+ MUL_NE
+ MUL_CS
+ MUL_CC
+ MUL_MI
+ MUL_PL
+ MUL_VS
+ MUL_VC
+ MUL_HI
+ MUL_LS
+ MUL_GE
+ MUL_LT
+ MUL_GT
+ MUL_LE
+ MUL
+ MUL_ZZ
+ MUL_S_EQ
+ MUL_S_NE
+ MUL_S_CS
+ MUL_S_CC
+ MUL_S_MI
+ MUL_S_PL
+ MUL_S_VS
+ MUL_S_VC
+ MUL_S_HI
+ MUL_S_LS
+ MUL_S_GE
+ MUL_S_LT
+ MUL_S_GT
+ MUL_S_LE
+ MUL_S
+ MUL_S_ZZ
+ MVN_EQ
+ MVN_NE
+ MVN_CS
+ MVN_CC
+ MVN_MI
+ MVN_PL
+ MVN_VS
+ MVN_VC
+ MVN_HI
+ MVN_LS
+ MVN_GE
+ MVN_LT
+ MVN_GT
+ MVN_LE
+ MVN
+ MVN_ZZ
+ MVN_S_EQ
+ MVN_S_NE
+ MVN_S_CS
+ MVN_S_CC
+ MVN_S_MI
+ MVN_S_PL
+ MVN_S_VS
+ MVN_S_VC
+ MVN_S_HI
+ MVN_S_LS
+ MVN_S_GE
+ MVN_S_LT
+ MVN_S_GT
+ MVN_S_LE
+ MVN_S
+ MVN_S_ZZ
+ NOP_EQ
+ NOP_NE
+ NOP_CS
+ NOP_CC
+ NOP_MI
+ NOP_PL
+ NOP_VS
+ NOP_VC
+ NOP_HI
+ NOP_LS
+ NOP_GE
+ NOP_LT
+ NOP_GT
+ NOP_LE
+ NOP
+ NOP_ZZ
+ ORR_EQ
+ ORR_NE
+ ORR_CS
+ ORR_CC
+ ORR_MI
+ ORR_PL
+ ORR_VS
+ ORR_VC
+ ORR_HI
+ ORR_LS
+ ORR_GE
+ ORR_LT
+ ORR_GT
+ ORR_LE
+ ORR
+ ORR_ZZ
+ ORR_S_EQ
+ ORR_S_NE
+ ORR_S_CS
+ ORR_S_CC
+ ORR_S_MI
+ ORR_S_PL
+ ORR_S_VS
+ ORR_S_VC
+ ORR_S_HI
+ ORR_S_LS
+ ORR_S_GE
+ ORR_S_LT
+ ORR_S_GT
+ ORR_S_LE
+ ORR_S
+ ORR_S_ZZ
+ PKHBT_EQ
+ PKHBT_NE
+ PKHBT_CS
+ PKHBT_CC
+ PKHBT_MI
+ PKHBT_PL
+ PKHBT_VS
+ PKHBT_VC
+ PKHBT_HI
+ PKHBT_LS
+ PKHBT_GE
+ PKHBT_LT
+ PKHBT_GT
+ PKHBT_LE
+ PKHBT
+ PKHBT_ZZ
+ PKHTB_EQ
+ PKHTB_NE
+ PKHTB_CS
+ PKHTB_CC
+ PKHTB_MI
+ PKHTB_PL
+ PKHTB_VS
+ PKHTB_VC
+ PKHTB_HI
+ PKHTB_LS
+ PKHTB_GE
+ PKHTB_LT
+ PKHTB_GT
+ PKHTB_LE
+ PKHTB
+ PKHTB_ZZ
+ PLD_W
+ PLD
+ PLI
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ POP_EQ
+ POP_NE
+ POP_CS
+ POP_CC
+ POP_MI
+ POP_PL
+ POP_VS
+ POP_VC
+ POP_HI
+ POP_LS
+ POP_GE
+ POP_LT
+ POP_GT
+ POP_LE
+ POP
+ POP_ZZ
+ PUSH_EQ
+ PUSH_NE
+ PUSH_CS
+ PUSH_CC
+ PUSH_MI
+ PUSH_PL
+ PUSH_VS
+ PUSH_VC
+ PUSH_HI
+ PUSH_LS
+ PUSH_GE
+ PUSH_LT
+ PUSH_GT
+ PUSH_LE
+ PUSH
+ PUSH_ZZ
+ QADD_EQ
+ QADD_NE
+ QADD_CS
+ QADD_CC
+ QADD_MI
+ QADD_PL
+ QADD_VS
+ QADD_VC
+ QADD_HI
+ QADD_LS
+ QADD_GE
+ QADD_LT
+ QADD_GT
+ QADD_LE
+ QADD
+ QADD_ZZ
+ QADD16_EQ
+ QADD16_NE
+ QADD16_CS
+ QADD16_CC
+ QADD16_MI
+ QADD16_PL
+ QADD16_VS
+ QADD16_VC
+ QADD16_HI
+ QADD16_LS
+ QADD16_GE
+ QADD16_LT
+ QADD16_GT
+ QADD16_LE
+ QADD16
+ QADD16_ZZ
+ QADD8_EQ
+ QADD8_NE
+ QADD8_CS
+ QADD8_CC
+ QADD8_MI
+ QADD8_PL
+ QADD8_VS
+ QADD8_VC
+ QADD8_HI
+ QADD8_LS
+ QADD8_GE
+ QADD8_LT
+ QADD8_GT
+ QADD8_LE
+ QADD8
+ QADD8_ZZ
+ QASX_EQ
+ QASX_NE
+ QASX_CS
+ QASX_CC
+ QASX_MI
+ QASX_PL
+ QASX_VS
+ QASX_VC
+ QASX_HI
+ QASX_LS
+ QASX_GE
+ QASX_LT
+ QASX_GT
+ QASX_LE
+ QASX
+ QASX_ZZ
+ QDADD_EQ
+ QDADD_NE
+ QDADD_CS
+ QDADD_CC
+ QDADD_MI
+ QDADD_PL
+ QDADD_VS
+ QDADD_VC
+ QDADD_HI
+ QDADD_LS
+ QDADD_GE
+ QDADD_LT
+ QDADD_GT
+ QDADD_LE
+ QDADD
+ QDADD_ZZ
+ QDSUB_EQ
+ QDSUB_NE
+ QDSUB_CS
+ QDSUB_CC
+ QDSUB_MI
+ QDSUB_PL
+ QDSUB_VS
+ QDSUB_VC
+ QDSUB_HI
+ QDSUB_LS
+ QDSUB_GE
+ QDSUB_LT
+ QDSUB_GT
+ QDSUB_LE
+ QDSUB
+ QDSUB_ZZ
+ QSAX_EQ
+ QSAX_NE
+ QSAX_CS
+ QSAX_CC
+ QSAX_MI
+ QSAX_PL
+ QSAX_VS
+ QSAX_VC
+ QSAX_HI
+ QSAX_LS
+ QSAX_GE
+ QSAX_LT
+ QSAX_GT
+ QSAX_LE
+ QSAX
+ QSAX_ZZ
+ QSUB_EQ
+ QSUB_NE
+ QSUB_CS
+ QSUB_CC
+ QSUB_MI
+ QSUB_PL
+ QSUB_VS
+ QSUB_VC
+ QSUB_HI
+ QSUB_LS
+ QSUB_GE
+ QSUB_LT
+ QSUB_GT
+ QSUB_LE
+ QSUB
+ QSUB_ZZ
+ QSUB16_EQ
+ QSUB16_NE
+ QSUB16_CS
+ QSUB16_CC
+ QSUB16_MI
+ QSUB16_PL
+ QSUB16_VS
+ QSUB16_VC
+ QSUB16_HI
+ QSUB16_LS
+ QSUB16_GE
+ QSUB16_LT
+ QSUB16_GT
+ QSUB16_LE
+ QSUB16
+ QSUB16_ZZ
+ QSUB8_EQ
+ QSUB8_NE
+ QSUB8_CS
+ QSUB8_CC
+ QSUB8_MI
+ QSUB8_PL
+ QSUB8_VS
+ QSUB8_VC
+ QSUB8_HI
+ QSUB8_LS
+ QSUB8_GE
+ QSUB8_LT
+ QSUB8_GT
+ QSUB8_LE
+ QSUB8
+ QSUB8_ZZ
+ RBIT_EQ
+ RBIT_NE
+ RBIT_CS
+ RBIT_CC
+ RBIT_MI
+ RBIT_PL
+ RBIT_VS
+ RBIT_VC
+ RBIT_HI
+ RBIT_LS
+ RBIT_GE
+ RBIT_LT
+ RBIT_GT
+ RBIT_LE
+ RBIT
+ RBIT_ZZ
+ REV_EQ
+ REV_NE
+ REV_CS
+ REV_CC
+ REV_MI
+ REV_PL
+ REV_VS
+ REV_VC
+ REV_HI
+ REV_LS
+ REV_GE
+ REV_LT
+ REV_GT
+ REV_LE
+ REV
+ REV_ZZ
+ REV16_EQ
+ REV16_NE
+ REV16_CS
+ REV16_CC
+ REV16_MI
+ REV16_PL
+ REV16_VS
+ REV16_VC
+ REV16_HI
+ REV16_LS
+ REV16_GE
+ REV16_LT
+ REV16_GT
+ REV16_LE
+ REV16
+ REV16_ZZ
+ REVSH_EQ
+ REVSH_NE
+ REVSH_CS
+ REVSH_CC
+ REVSH_MI
+ REVSH_PL
+ REVSH_VS
+ REVSH_VC
+ REVSH_HI
+ REVSH_LS
+ REVSH_GE
+ REVSH_LT
+ REVSH_GT
+ REVSH_LE
+ REVSH
+ REVSH_ZZ
+ ROR_EQ
+ ROR_NE
+ ROR_CS
+ ROR_CC
+ ROR_MI
+ ROR_PL
+ ROR_VS
+ ROR_VC
+ ROR_HI
+ ROR_LS
+ ROR_GE
+ ROR_LT
+ ROR_GT
+ ROR_LE
+ ROR
+ ROR_ZZ
+ ROR_S_EQ
+ ROR_S_NE
+ ROR_S_CS
+ ROR_S_CC
+ ROR_S_MI
+ ROR_S_PL
+ ROR_S_VS
+ ROR_S_VC
+ ROR_S_HI
+ ROR_S_LS
+ ROR_S_GE
+ ROR_S_LT
+ ROR_S_GT
+ ROR_S_LE
+ ROR_S
+ ROR_S_ZZ
+ RRX_EQ
+ RRX_NE
+ RRX_CS
+ RRX_CC
+ RRX_MI
+ RRX_PL
+ RRX_VS
+ RRX_VC
+ RRX_HI
+ RRX_LS
+ RRX_GE
+ RRX_LT
+ RRX_GT
+ RRX_LE
+ RRX
+ RRX_ZZ
+ RRX_S_EQ
+ RRX_S_NE
+ RRX_S_CS
+ RRX_S_CC
+ RRX_S_MI
+ RRX_S_PL
+ RRX_S_VS
+ RRX_S_VC
+ RRX_S_HI
+ RRX_S_LS
+ RRX_S_GE
+ RRX_S_LT
+ RRX_S_GT
+ RRX_S_LE
+ RRX_S
+ RRX_S_ZZ
+ RSB_EQ
+ RSB_NE
+ RSB_CS
+ RSB_CC
+ RSB_MI
+ RSB_PL
+ RSB_VS
+ RSB_VC
+ RSB_HI
+ RSB_LS
+ RSB_GE
+ RSB_LT
+ RSB_GT
+ RSB_LE
+ RSB
+ RSB_ZZ
+ RSB_S_EQ
+ RSB_S_NE
+ RSB_S_CS
+ RSB_S_CC
+ RSB_S_MI
+ RSB_S_PL
+ RSB_S_VS
+ RSB_S_VC
+ RSB_S_HI
+ RSB_S_LS
+ RSB_S_GE
+ RSB_S_LT
+ RSB_S_GT
+ RSB_S_LE
+ RSB_S
+ RSB_S_ZZ
+ RSC_EQ
+ RSC_NE
+ RSC_CS
+ RSC_CC
+ RSC_MI
+ RSC_PL
+ RSC_VS
+ RSC_VC
+ RSC_HI
+ RSC_LS
+ RSC_GE
+ RSC_LT
+ RSC_GT
+ RSC_LE
+ RSC
+ RSC_ZZ
+ RSC_S_EQ
+ RSC_S_NE
+ RSC_S_CS
+ RSC_S_CC
+ RSC_S_MI
+ RSC_S_PL
+ RSC_S_VS
+ RSC_S_VC
+ RSC_S_HI
+ RSC_S_LS
+ RSC_S_GE
+ RSC_S_LT
+ RSC_S_GT
+ RSC_S_LE
+ RSC_S
+ RSC_S_ZZ
+ SADD16_EQ
+ SADD16_NE
+ SADD16_CS
+ SADD16_CC
+ SADD16_MI
+ SADD16_PL
+ SADD16_VS
+ SADD16_VC
+ SADD16_HI
+ SADD16_LS
+ SADD16_GE
+ SADD16_LT
+ SADD16_GT
+ SADD16_LE
+ SADD16
+ SADD16_ZZ
+ SADD8_EQ
+ SADD8_NE
+ SADD8_CS
+ SADD8_CC
+ SADD8_MI
+ SADD8_PL
+ SADD8_VS
+ SADD8_VC
+ SADD8_HI
+ SADD8_LS
+ SADD8_GE
+ SADD8_LT
+ SADD8_GT
+ SADD8_LE
+ SADD8
+ SADD8_ZZ
+ SASX_EQ
+ SASX_NE
+ SASX_CS
+ SASX_CC
+ SASX_MI
+ SASX_PL
+ SASX_VS
+ SASX_VC
+ SASX_HI
+ SASX_LS
+ SASX_GE
+ SASX_LT
+ SASX_GT
+ SASX_LE
+ SASX
+ SASX_ZZ
+ SBC_EQ
+ SBC_NE
+ SBC_CS
+ SBC_CC
+ SBC_MI
+ SBC_PL
+ SBC_VS
+ SBC_VC
+ SBC_HI
+ SBC_LS
+ SBC_GE
+ SBC_LT
+ SBC_GT
+ SBC_LE
+ SBC
+ SBC_ZZ
+ SBC_S_EQ
+ SBC_S_NE
+ SBC_S_CS
+ SBC_S_CC
+ SBC_S_MI
+ SBC_S_PL
+ SBC_S_VS
+ SBC_S_VC
+ SBC_S_HI
+ SBC_S_LS
+ SBC_S_GE
+ SBC_S_LT
+ SBC_S_GT
+ SBC_S_LE
+ SBC_S
+ SBC_S_ZZ
+ SBFX_EQ
+ SBFX_NE
+ SBFX_CS
+ SBFX_CC
+ SBFX_MI
+ SBFX_PL
+ SBFX_VS
+ SBFX_VC
+ SBFX_HI
+ SBFX_LS
+ SBFX_GE
+ SBFX_LT
+ SBFX_GT
+ SBFX_LE
+ SBFX
+ SBFX_ZZ
+ SEL_EQ
+ SEL_NE
+ SEL_CS
+ SEL_CC
+ SEL_MI
+ SEL_PL
+ SEL_VS
+ SEL_VC
+ SEL_HI
+ SEL_LS
+ SEL_GE
+ SEL_LT
+ SEL_GT
+ SEL_LE
+ SEL
+ SEL_ZZ
+ SETEND
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ SEV_EQ
+ SEV_NE
+ SEV_CS
+ SEV_CC
+ SEV_MI
+ SEV_PL
+ SEV_VS
+ SEV_VC
+ SEV_HI
+ SEV_LS
+ SEV_GE
+ SEV_LT
+ SEV_GT
+ SEV_LE
+ SEV
+ SEV_ZZ
+ SHADD16_EQ
+ SHADD16_NE
+ SHADD16_CS
+ SHADD16_CC
+ SHADD16_MI
+ SHADD16_PL
+ SHADD16_VS
+ SHADD16_VC
+ SHADD16_HI
+ SHADD16_LS
+ SHADD16_GE
+ SHADD16_LT
+ SHADD16_GT
+ SHADD16_LE
+ SHADD16
+ SHADD16_ZZ
+ SHADD8_EQ
+ SHADD8_NE
+ SHADD8_CS
+ SHADD8_CC
+ SHADD8_MI
+ SHADD8_PL
+ SHADD8_VS
+ SHADD8_VC
+ SHADD8_HI
+ SHADD8_LS
+ SHADD8_GE
+ SHADD8_LT
+ SHADD8_GT
+ SHADD8_LE
+ SHADD8
+ SHADD8_ZZ
+ SHASX_EQ
+ SHASX_NE
+ SHASX_CS
+ SHASX_CC
+ SHASX_MI
+ SHASX_PL
+ SHASX_VS
+ SHASX_VC
+ SHASX_HI
+ SHASX_LS
+ SHASX_GE
+ SHASX_LT
+ SHASX_GT
+ SHASX_LE
+ SHASX
+ SHASX_ZZ
+ SHSAX_EQ
+ SHSAX_NE
+ SHSAX_CS
+ SHSAX_CC
+ SHSAX_MI
+ SHSAX_PL
+ SHSAX_VS
+ SHSAX_VC
+ SHSAX_HI
+ SHSAX_LS
+ SHSAX_GE
+ SHSAX_LT
+ SHSAX_GT
+ SHSAX_LE
+ SHSAX
+ SHSAX_ZZ
+ SHSUB16_EQ
+ SHSUB16_NE
+ SHSUB16_CS
+ SHSUB16_CC
+ SHSUB16_MI
+ SHSUB16_PL
+ SHSUB16_VS
+ SHSUB16_VC
+ SHSUB16_HI
+ SHSUB16_LS
+ SHSUB16_GE
+ SHSUB16_LT
+ SHSUB16_GT
+ SHSUB16_LE
+ SHSUB16
+ SHSUB16_ZZ
+ SHSUB8_EQ
+ SHSUB8_NE
+ SHSUB8_CS
+ SHSUB8_CC
+ SHSUB8_MI
+ SHSUB8_PL
+ SHSUB8_VS
+ SHSUB8_VC
+ SHSUB8_HI
+ SHSUB8_LS
+ SHSUB8_GE
+ SHSUB8_LT
+ SHSUB8_GT
+ SHSUB8_LE
+ SHSUB8
+ SHSUB8_ZZ
+ SMLABB_EQ
+ SMLABB_NE
+ SMLABB_CS
+ SMLABB_CC
+ SMLABB_MI
+ SMLABB_PL
+ SMLABB_VS
+ SMLABB_VC
+ SMLABB_HI
+ SMLABB_LS
+ SMLABB_GE
+ SMLABB_LT
+ SMLABB_GT
+ SMLABB_LE
+ SMLABB
+ SMLABB_ZZ
+ SMLABT_EQ
+ SMLABT_NE
+ SMLABT_CS
+ SMLABT_CC
+ SMLABT_MI
+ SMLABT_PL
+ SMLABT_VS
+ SMLABT_VC
+ SMLABT_HI
+ SMLABT_LS
+ SMLABT_GE
+ SMLABT_LT
+ SMLABT_GT
+ SMLABT_LE
+ SMLABT
+ SMLABT_ZZ
+ SMLATB_EQ
+ SMLATB_NE
+ SMLATB_CS
+ SMLATB_CC
+ SMLATB_MI
+ SMLATB_PL
+ SMLATB_VS
+ SMLATB_VC
+ SMLATB_HI
+ SMLATB_LS
+ SMLATB_GE
+ SMLATB_LT
+ SMLATB_GT
+ SMLATB_LE
+ SMLATB
+ SMLATB_ZZ
+ SMLATT_EQ
+ SMLATT_NE
+ SMLATT_CS
+ SMLATT_CC
+ SMLATT_MI
+ SMLATT_PL
+ SMLATT_VS
+ SMLATT_VC
+ SMLATT_HI
+ SMLATT_LS
+ SMLATT_GE
+ SMLATT_LT
+ SMLATT_GT
+ SMLATT_LE
+ SMLATT
+ SMLATT_ZZ
+ SMLAD_EQ
+ SMLAD_NE
+ SMLAD_CS
+ SMLAD_CC
+ SMLAD_MI
+ SMLAD_PL
+ SMLAD_VS
+ SMLAD_VC
+ SMLAD_HI
+ SMLAD_LS
+ SMLAD_GE
+ SMLAD_LT
+ SMLAD_GT
+ SMLAD_LE
+ SMLAD
+ SMLAD_ZZ
+ SMLAD_X_EQ
+ SMLAD_X_NE
+ SMLAD_X_CS
+ SMLAD_X_CC
+ SMLAD_X_MI
+ SMLAD_X_PL
+ SMLAD_X_VS
+ SMLAD_X_VC
+ SMLAD_X_HI
+ SMLAD_X_LS
+ SMLAD_X_GE
+ SMLAD_X_LT
+ SMLAD_X_GT
+ SMLAD_X_LE
+ SMLAD_X
+ SMLAD_X_ZZ
+ SMLAL_EQ
+ SMLAL_NE
+ SMLAL_CS
+ SMLAL_CC
+ SMLAL_MI
+ SMLAL_PL
+ SMLAL_VS
+ SMLAL_VC
+ SMLAL_HI
+ SMLAL_LS
+ SMLAL_GE
+ SMLAL_LT
+ SMLAL_GT
+ SMLAL_LE
+ SMLAL
+ SMLAL_ZZ
+ SMLAL_S_EQ
+ SMLAL_S_NE
+ SMLAL_S_CS
+ SMLAL_S_CC
+ SMLAL_S_MI
+ SMLAL_S_PL
+ SMLAL_S_VS
+ SMLAL_S_VC
+ SMLAL_S_HI
+ SMLAL_S_LS
+ SMLAL_S_GE
+ SMLAL_S_LT
+ SMLAL_S_GT
+ SMLAL_S_LE
+ SMLAL_S
+ SMLAL_S_ZZ
+ SMLALBB_EQ
+ SMLALBB_NE
+ SMLALBB_CS
+ SMLALBB_CC
+ SMLALBB_MI
+ SMLALBB_PL
+ SMLALBB_VS
+ SMLALBB_VC
+ SMLALBB_HI
+ SMLALBB_LS
+ SMLALBB_GE
+ SMLALBB_LT
+ SMLALBB_GT
+ SMLALBB_LE
+ SMLALBB
+ SMLALBB_ZZ
+ SMLALBT_EQ
+ SMLALBT_NE
+ SMLALBT_CS
+ SMLALBT_CC
+ SMLALBT_MI
+ SMLALBT_PL
+ SMLALBT_VS
+ SMLALBT_VC
+ SMLALBT_HI
+ SMLALBT_LS
+ SMLALBT_GE
+ SMLALBT_LT
+ SMLALBT_GT
+ SMLALBT_LE
+ SMLALBT
+ SMLALBT_ZZ
+ SMLALTB_EQ
+ SMLALTB_NE
+ SMLALTB_CS
+ SMLALTB_CC
+ SMLALTB_MI
+ SMLALTB_PL
+ SMLALTB_VS
+ SMLALTB_VC
+ SMLALTB_HI
+ SMLALTB_LS
+ SMLALTB_GE
+ SMLALTB_LT
+ SMLALTB_GT
+ SMLALTB_LE
+ SMLALTB
+ SMLALTB_ZZ
+ SMLALTT_EQ
+ SMLALTT_NE
+ SMLALTT_CS
+ SMLALTT_CC
+ SMLALTT_MI
+ SMLALTT_PL
+ SMLALTT_VS
+ SMLALTT_VC
+ SMLALTT_HI
+ SMLALTT_LS
+ SMLALTT_GE
+ SMLALTT_LT
+ SMLALTT_GT
+ SMLALTT_LE
+ SMLALTT
+ SMLALTT_ZZ
+ SMLALD_EQ
+ SMLALD_NE
+ SMLALD_CS
+ SMLALD_CC
+ SMLALD_MI
+ SMLALD_PL
+ SMLALD_VS
+ SMLALD_VC
+ SMLALD_HI
+ SMLALD_LS
+ SMLALD_GE
+ SMLALD_LT
+ SMLALD_GT
+ SMLALD_LE
+ SMLALD
+ SMLALD_ZZ
+ SMLALD_X_EQ
+ SMLALD_X_NE
+ SMLALD_X_CS
+ SMLALD_X_CC
+ SMLALD_X_MI
+ SMLALD_X_PL
+ SMLALD_X_VS
+ SMLALD_X_VC
+ SMLALD_X_HI
+ SMLALD_X_LS
+ SMLALD_X_GE
+ SMLALD_X_LT
+ SMLALD_X_GT
+ SMLALD_X_LE
+ SMLALD_X
+ SMLALD_X_ZZ
+ SMLAWB_EQ
+ SMLAWB_NE
+ SMLAWB_CS
+ SMLAWB_CC
+ SMLAWB_MI
+ SMLAWB_PL
+ SMLAWB_VS
+ SMLAWB_VC
+ SMLAWB_HI
+ SMLAWB_LS
+ SMLAWB_GE
+ SMLAWB_LT
+ SMLAWB_GT
+ SMLAWB_LE
+ SMLAWB
+ SMLAWB_ZZ
+ SMLAWT_EQ
+ SMLAWT_NE
+ SMLAWT_CS
+ SMLAWT_CC
+ SMLAWT_MI
+ SMLAWT_PL
+ SMLAWT_VS
+ SMLAWT_VC
+ SMLAWT_HI
+ SMLAWT_LS
+ SMLAWT_GE
+ SMLAWT_LT
+ SMLAWT_GT
+ SMLAWT_LE
+ SMLAWT
+ SMLAWT_ZZ
+ SMLSD_EQ
+ SMLSD_NE
+ SMLSD_CS
+ SMLSD_CC
+ SMLSD_MI
+ SMLSD_PL
+ SMLSD_VS
+ SMLSD_VC
+ SMLSD_HI
+ SMLSD_LS
+ SMLSD_GE
+ SMLSD_LT
+ SMLSD_GT
+ SMLSD_LE
+ SMLSD
+ SMLSD_ZZ
+ SMLSD_X_EQ
+ SMLSD_X_NE
+ SMLSD_X_CS
+ SMLSD_X_CC
+ SMLSD_X_MI
+ SMLSD_X_PL
+ SMLSD_X_VS
+ SMLSD_X_VC
+ SMLSD_X_HI
+ SMLSD_X_LS
+ SMLSD_X_GE
+ SMLSD_X_LT
+ SMLSD_X_GT
+ SMLSD_X_LE
+ SMLSD_X
+ SMLSD_X_ZZ
+ SMLSLD_EQ
+ SMLSLD_NE
+ SMLSLD_CS
+ SMLSLD_CC
+ SMLSLD_MI
+ SMLSLD_PL
+ SMLSLD_VS
+ SMLSLD_VC
+ SMLSLD_HI
+ SMLSLD_LS
+ SMLSLD_GE
+ SMLSLD_LT
+ SMLSLD_GT
+ SMLSLD_LE
+ SMLSLD
+ SMLSLD_ZZ
+ SMLSLD_X_EQ
+ SMLSLD_X_NE
+ SMLSLD_X_CS
+ SMLSLD_X_CC
+ SMLSLD_X_MI
+ SMLSLD_X_PL
+ SMLSLD_X_VS
+ SMLSLD_X_VC
+ SMLSLD_X_HI
+ SMLSLD_X_LS
+ SMLSLD_X_GE
+ SMLSLD_X_LT
+ SMLSLD_X_GT
+ SMLSLD_X_LE
+ SMLSLD_X
+ SMLSLD_X_ZZ
+ SMMLA_EQ
+ SMMLA_NE
+ SMMLA_CS
+ SMMLA_CC
+ SMMLA_MI
+ SMMLA_PL
+ SMMLA_VS
+ SMMLA_VC
+ SMMLA_HI
+ SMMLA_LS
+ SMMLA_GE
+ SMMLA_LT
+ SMMLA_GT
+ SMMLA_LE
+ SMMLA
+ SMMLA_ZZ
+ SMMLA_R_EQ
+ SMMLA_R_NE
+ SMMLA_R_CS
+ SMMLA_R_CC
+ SMMLA_R_MI
+ SMMLA_R_PL
+ SMMLA_R_VS
+ SMMLA_R_VC
+ SMMLA_R_HI
+ SMMLA_R_LS
+ SMMLA_R_GE
+ SMMLA_R_LT
+ SMMLA_R_GT
+ SMMLA_R_LE
+ SMMLA_R
+ SMMLA_R_ZZ
+ SMMLS_EQ
+ SMMLS_NE
+ SMMLS_CS
+ SMMLS_CC
+ SMMLS_MI
+ SMMLS_PL
+ SMMLS_VS
+ SMMLS_VC
+ SMMLS_HI
+ SMMLS_LS
+ SMMLS_GE
+ SMMLS_LT
+ SMMLS_GT
+ SMMLS_LE
+ SMMLS
+ SMMLS_ZZ
+ SMMLS_R_EQ
+ SMMLS_R_NE
+ SMMLS_R_CS
+ SMMLS_R_CC
+ SMMLS_R_MI
+ SMMLS_R_PL
+ SMMLS_R_VS
+ SMMLS_R_VC
+ SMMLS_R_HI
+ SMMLS_R_LS
+ SMMLS_R_GE
+ SMMLS_R_LT
+ SMMLS_R_GT
+ SMMLS_R_LE
+ SMMLS_R
+ SMMLS_R_ZZ
+ SMMUL_EQ
+ SMMUL_NE
+ SMMUL_CS
+ SMMUL_CC
+ SMMUL_MI
+ SMMUL_PL
+ SMMUL_VS
+ SMMUL_VC
+ SMMUL_HI
+ SMMUL_LS
+ SMMUL_GE
+ SMMUL_LT
+ SMMUL_GT
+ SMMUL_LE
+ SMMUL
+ SMMUL_ZZ
+ SMMUL_R_EQ
+ SMMUL_R_NE
+ SMMUL_R_CS
+ SMMUL_R_CC
+ SMMUL_R_MI
+ SMMUL_R_PL
+ SMMUL_R_VS
+ SMMUL_R_VC
+ SMMUL_R_HI
+ SMMUL_R_LS
+ SMMUL_R_GE
+ SMMUL_R_LT
+ SMMUL_R_GT
+ SMMUL_R_LE
+ SMMUL_R
+ SMMUL_R_ZZ
+ SMUAD_EQ
+ SMUAD_NE
+ SMUAD_CS
+ SMUAD_CC
+ SMUAD_MI
+ SMUAD_PL
+ SMUAD_VS
+ SMUAD_VC
+ SMUAD_HI
+ SMUAD_LS
+ SMUAD_GE
+ SMUAD_LT
+ SMUAD_GT
+ SMUAD_LE
+ SMUAD
+ SMUAD_ZZ
+ SMUAD_X_EQ
+ SMUAD_X_NE
+ SMUAD_X_CS
+ SMUAD_X_CC
+ SMUAD_X_MI
+ SMUAD_X_PL
+ SMUAD_X_VS
+ SMUAD_X_VC
+ SMUAD_X_HI
+ SMUAD_X_LS
+ SMUAD_X_GE
+ SMUAD_X_LT
+ SMUAD_X_GT
+ SMUAD_X_LE
+ SMUAD_X
+ SMUAD_X_ZZ
+ SMULBB_EQ
+ SMULBB_NE
+ SMULBB_CS
+ SMULBB_CC
+ SMULBB_MI
+ SMULBB_PL
+ SMULBB_VS
+ SMULBB_VC
+ SMULBB_HI
+ SMULBB_LS
+ SMULBB_GE
+ SMULBB_LT
+ SMULBB_GT
+ SMULBB_LE
+ SMULBB
+ SMULBB_ZZ
+ SMULBT_EQ
+ SMULBT_NE
+ SMULBT_CS
+ SMULBT_CC
+ SMULBT_MI
+ SMULBT_PL
+ SMULBT_VS
+ SMULBT_VC
+ SMULBT_HI
+ SMULBT_LS
+ SMULBT_GE
+ SMULBT_LT
+ SMULBT_GT
+ SMULBT_LE
+ SMULBT
+ SMULBT_ZZ
+ SMULTB_EQ
+ SMULTB_NE
+ SMULTB_CS
+ SMULTB_CC
+ SMULTB_MI
+ SMULTB_PL
+ SMULTB_VS
+ SMULTB_VC
+ SMULTB_HI
+ SMULTB_LS
+ SMULTB_GE
+ SMULTB_LT
+ SMULTB_GT
+ SMULTB_LE
+ SMULTB
+ SMULTB_ZZ
+ SMULTT_EQ
+ SMULTT_NE
+ SMULTT_CS
+ SMULTT_CC
+ SMULTT_MI
+ SMULTT_PL
+ SMULTT_VS
+ SMULTT_VC
+ SMULTT_HI
+ SMULTT_LS
+ SMULTT_GE
+ SMULTT_LT
+ SMULTT_GT
+ SMULTT_LE
+ SMULTT
+ SMULTT_ZZ
+ SMULL_EQ
+ SMULL_NE
+ SMULL_CS
+ SMULL_CC
+ SMULL_MI
+ SMULL_PL
+ SMULL_VS
+ SMULL_VC
+ SMULL_HI
+ SMULL_LS
+ SMULL_GE
+ SMULL_LT
+ SMULL_GT
+ SMULL_LE
+ SMULL
+ SMULL_ZZ
+ SMULL_S_EQ
+ SMULL_S_NE
+ SMULL_S_CS
+ SMULL_S_CC
+ SMULL_S_MI
+ SMULL_S_PL
+ SMULL_S_VS
+ SMULL_S_VC
+ SMULL_S_HI
+ SMULL_S_LS
+ SMULL_S_GE
+ SMULL_S_LT
+ SMULL_S_GT
+ SMULL_S_LE
+ SMULL_S
+ SMULL_S_ZZ
+ SMULWB_EQ
+ SMULWB_NE
+ SMULWB_CS
+ SMULWB_CC
+ SMULWB_MI
+ SMULWB_PL
+ SMULWB_VS
+ SMULWB_VC
+ SMULWB_HI
+ SMULWB_LS
+ SMULWB_GE
+ SMULWB_LT
+ SMULWB_GT
+ SMULWB_LE
+ SMULWB
+ SMULWB_ZZ
+ SMULWT_EQ
+ SMULWT_NE
+ SMULWT_CS
+ SMULWT_CC
+ SMULWT_MI
+ SMULWT_PL
+ SMULWT_VS
+ SMULWT_VC
+ SMULWT_HI
+ SMULWT_LS
+ SMULWT_GE
+ SMULWT_LT
+ SMULWT_GT
+ SMULWT_LE
+ SMULWT
+ SMULWT_ZZ
+ SMUSD_EQ
+ SMUSD_NE
+ SMUSD_CS
+ SMUSD_CC
+ SMUSD_MI
+ SMUSD_PL
+ SMUSD_VS
+ SMUSD_VC
+ SMUSD_HI
+ SMUSD_LS
+ SMUSD_GE
+ SMUSD_LT
+ SMUSD_GT
+ SMUSD_LE
+ SMUSD
+ SMUSD_ZZ
+ SMUSD_X_EQ
+ SMUSD_X_NE
+ SMUSD_X_CS
+ SMUSD_X_CC
+ SMUSD_X_MI
+ SMUSD_X_PL
+ SMUSD_X_VS
+ SMUSD_X_VC
+ SMUSD_X_HI
+ SMUSD_X_LS
+ SMUSD_X_GE
+ SMUSD_X_LT
+ SMUSD_X_GT
+ SMUSD_X_LE
+ SMUSD_X
+ SMUSD_X_ZZ
+ SSAT_EQ
+ SSAT_NE
+ SSAT_CS
+ SSAT_CC
+ SSAT_MI
+ SSAT_PL
+ SSAT_VS
+ SSAT_VC
+ SSAT_HI
+ SSAT_LS
+ SSAT_GE
+ SSAT_LT
+ SSAT_GT
+ SSAT_LE
+ SSAT
+ SSAT_ZZ
+ SSAT16_EQ
+ SSAT16_NE
+ SSAT16_CS
+ SSAT16_CC
+ SSAT16_MI
+ SSAT16_PL
+ SSAT16_VS
+ SSAT16_VC
+ SSAT16_HI
+ SSAT16_LS
+ SSAT16_GE
+ SSAT16_LT
+ SSAT16_GT
+ SSAT16_LE
+ SSAT16
+ SSAT16_ZZ
+ SSAX_EQ
+ SSAX_NE
+ SSAX_CS
+ SSAX_CC
+ SSAX_MI
+ SSAX_PL
+ SSAX_VS
+ SSAX_VC
+ SSAX_HI
+ SSAX_LS
+ SSAX_GE
+ SSAX_LT
+ SSAX_GT
+ SSAX_LE
+ SSAX
+ SSAX_ZZ
+ SSUB16_EQ
+ SSUB16_NE
+ SSUB16_CS
+ SSUB16_CC
+ SSUB16_MI
+ SSUB16_PL
+ SSUB16_VS
+ SSUB16_VC
+ SSUB16_HI
+ SSUB16_LS
+ SSUB16_GE
+ SSUB16_LT
+ SSUB16_GT
+ SSUB16_LE
+ SSUB16
+ SSUB16_ZZ
+ SSUB8_EQ
+ SSUB8_NE
+ SSUB8_CS
+ SSUB8_CC
+ SSUB8_MI
+ SSUB8_PL
+ SSUB8_VS
+ SSUB8_VC
+ SSUB8_HI
+ SSUB8_LS
+ SSUB8_GE
+ SSUB8_LT
+ SSUB8_GT
+ SSUB8_LE
+ SSUB8
+ SSUB8_ZZ
+ STM_EQ
+ STM_NE
+ STM_CS
+ STM_CC
+ STM_MI
+ STM_PL
+ STM_VS
+ STM_VC
+ STM_HI
+ STM_LS
+ STM_GE
+ STM_LT
+ STM_GT
+ STM_LE
+ STM
+ STM_ZZ
+ STMDA_EQ
+ STMDA_NE
+ STMDA_CS
+ STMDA_CC
+ STMDA_MI
+ STMDA_PL
+ STMDA_VS
+ STMDA_VC
+ STMDA_HI
+ STMDA_LS
+ STMDA_GE
+ STMDA_LT
+ STMDA_GT
+ STMDA_LE
+ STMDA
+ STMDA_ZZ
+ STMDB_EQ
+ STMDB_NE
+ STMDB_CS
+ STMDB_CC
+ STMDB_MI
+ STMDB_PL
+ STMDB_VS
+ STMDB_VC
+ STMDB_HI
+ STMDB_LS
+ STMDB_GE
+ STMDB_LT
+ STMDB_GT
+ STMDB_LE
+ STMDB
+ STMDB_ZZ
+ STMIB_EQ
+ STMIB_NE
+ STMIB_CS
+ STMIB_CC
+ STMIB_MI
+ STMIB_PL
+ STMIB_VS
+ STMIB_VC
+ STMIB_HI
+ STMIB_LS
+ STMIB_GE
+ STMIB_LT
+ STMIB_GT
+ STMIB_LE
+ STMIB
+ STMIB_ZZ
+ STR_EQ
+ STR_NE
+ STR_CS
+ STR_CC
+ STR_MI
+ STR_PL
+ STR_VS
+ STR_VC
+ STR_HI
+ STR_LS
+ STR_GE
+ STR_LT
+ STR_GT
+ STR_LE
+ STR
+ STR_ZZ
+ STRB_EQ
+ STRB_NE
+ STRB_CS
+ STRB_CC
+ STRB_MI
+ STRB_PL
+ STRB_VS
+ STRB_VC
+ STRB_HI
+ STRB_LS
+ STRB_GE
+ STRB_LT
+ STRB_GT
+ STRB_LE
+ STRB
+ STRB_ZZ
+ STRBT_EQ
+ STRBT_NE
+ STRBT_CS
+ STRBT_CC
+ STRBT_MI
+ STRBT_PL
+ STRBT_VS
+ STRBT_VC
+ STRBT_HI
+ STRBT_LS
+ STRBT_GE
+ STRBT_LT
+ STRBT_GT
+ STRBT_LE
+ STRBT
+ STRBT_ZZ
+ STRD_EQ
+ STRD_NE
+ STRD_CS
+ STRD_CC
+ STRD_MI
+ STRD_PL
+ STRD_VS
+ STRD_VC
+ STRD_HI
+ STRD_LS
+ STRD_GE
+ STRD_LT
+ STRD_GT
+ STRD_LE
+ STRD
+ STRD_ZZ
+ STREX_EQ
+ STREX_NE
+ STREX_CS
+ STREX_CC
+ STREX_MI
+ STREX_PL
+ STREX_VS
+ STREX_VC
+ STREX_HI
+ STREX_LS
+ STREX_GE
+ STREX_LT
+ STREX_GT
+ STREX_LE
+ STREX
+ STREX_ZZ
+ STREXB_EQ
+ STREXB_NE
+ STREXB_CS
+ STREXB_CC
+ STREXB_MI
+ STREXB_PL
+ STREXB_VS
+ STREXB_VC
+ STREXB_HI
+ STREXB_LS
+ STREXB_GE
+ STREXB_LT
+ STREXB_GT
+ STREXB_LE
+ STREXB
+ STREXB_ZZ
+ STREXD_EQ
+ STREXD_NE
+ STREXD_CS
+ STREXD_CC
+ STREXD_MI
+ STREXD_PL
+ STREXD_VS
+ STREXD_VC
+ STREXD_HI
+ STREXD_LS
+ STREXD_GE
+ STREXD_LT
+ STREXD_GT
+ STREXD_LE
+ STREXD
+ STREXD_ZZ
+ STREXH_EQ
+ STREXH_NE
+ STREXH_CS
+ STREXH_CC
+ STREXH_MI
+ STREXH_PL
+ STREXH_VS
+ STREXH_VC
+ STREXH_HI
+ STREXH_LS
+ STREXH_GE
+ STREXH_LT
+ STREXH_GT
+ STREXH_LE
+ STREXH
+ STREXH_ZZ
+ STRH_EQ
+ STRH_NE
+ STRH_CS
+ STRH_CC
+ STRH_MI
+ STRH_PL
+ STRH_VS
+ STRH_VC
+ STRH_HI
+ STRH_LS
+ STRH_GE
+ STRH_LT
+ STRH_GT
+ STRH_LE
+ STRH
+ STRH_ZZ
+ STRHT_EQ
+ STRHT_NE
+ STRHT_CS
+ STRHT_CC
+ STRHT_MI
+ STRHT_PL
+ STRHT_VS
+ STRHT_VC
+ STRHT_HI
+ STRHT_LS
+ STRHT_GE
+ STRHT_LT
+ STRHT_GT
+ STRHT_LE
+ STRHT
+ STRHT_ZZ
+ STRT_EQ
+ STRT_NE
+ STRT_CS
+ STRT_CC
+ STRT_MI
+ STRT_PL
+ STRT_VS
+ STRT_VC
+ STRT_HI
+ STRT_LS
+ STRT_GE
+ STRT_LT
+ STRT_GT
+ STRT_LE
+ STRT
+ STRT_ZZ
+ SUB_EQ
+ SUB_NE
+ SUB_CS
+ SUB_CC
+ SUB_MI
+ SUB_PL
+ SUB_VS
+ SUB_VC
+ SUB_HI
+ SUB_LS
+ SUB_GE
+ SUB_LT
+ SUB_GT
+ SUB_LE
+ SUB
+ SUB_ZZ
+ SUB_S_EQ
+ SUB_S_NE
+ SUB_S_CS
+ SUB_S_CC
+ SUB_S_MI
+ SUB_S_PL
+ SUB_S_VS
+ SUB_S_VC
+ SUB_S_HI
+ SUB_S_LS
+ SUB_S_GE
+ SUB_S_LT
+ SUB_S_GT
+ SUB_S_LE
+ SUB_S
+ SUB_S_ZZ
+ SVC_EQ
+ SVC_NE
+ SVC_CS
+ SVC_CC
+ SVC_MI
+ SVC_PL
+ SVC_VS
+ SVC_VC
+ SVC_HI
+ SVC_LS
+ SVC_GE
+ SVC_LT
+ SVC_GT
+ SVC_LE
+ SVC
+ SVC_ZZ
+ SWP_EQ
+ SWP_NE
+ SWP_CS
+ SWP_CC
+ SWP_MI
+ SWP_PL
+ SWP_VS
+ SWP_VC
+ SWP_HI
+ SWP_LS
+ SWP_GE
+ SWP_LT
+ SWP_GT
+ SWP_LE
+ SWP
+ SWP_ZZ
+ SWP_B_EQ
+ SWP_B_NE
+ SWP_B_CS
+ SWP_B_CC
+ SWP_B_MI
+ SWP_B_PL
+ SWP_B_VS
+ SWP_B_VC
+ SWP_B_HI
+ SWP_B_LS
+ SWP_B_GE
+ SWP_B_LT
+ SWP_B_GT
+ SWP_B_LE
+ SWP_B
+ SWP_B_ZZ
+ SXTAB_EQ
+ SXTAB_NE
+ SXTAB_CS
+ SXTAB_CC
+ SXTAB_MI
+ SXTAB_PL
+ SXTAB_VS
+ SXTAB_VC
+ SXTAB_HI
+ SXTAB_LS
+ SXTAB_GE
+ SXTAB_LT
+ SXTAB_GT
+ SXTAB_LE
+ SXTAB
+ SXTAB_ZZ
+ SXTAB16_EQ
+ SXTAB16_NE
+ SXTAB16_CS
+ SXTAB16_CC
+ SXTAB16_MI
+ SXTAB16_PL
+ SXTAB16_VS
+ SXTAB16_VC
+ SXTAB16_HI
+ SXTAB16_LS
+ SXTAB16_GE
+ SXTAB16_LT
+ SXTAB16_GT
+ SXTAB16_LE
+ SXTAB16
+ SXTAB16_ZZ
+ SXTAH_EQ
+ SXTAH_NE
+ SXTAH_CS
+ SXTAH_CC
+ SXTAH_MI
+ SXTAH_PL
+ SXTAH_VS
+ SXTAH_VC
+ SXTAH_HI
+ SXTAH_LS
+ SXTAH_GE
+ SXTAH_LT
+ SXTAH_GT
+ SXTAH_LE
+ SXTAH
+ SXTAH_ZZ
+ SXTB_EQ
+ SXTB_NE
+ SXTB_CS
+ SXTB_CC
+ SXTB_MI
+ SXTB_PL
+ SXTB_VS
+ SXTB_VC
+ SXTB_HI
+ SXTB_LS
+ SXTB_GE
+ SXTB_LT
+ SXTB_GT
+ SXTB_LE
+ SXTB
+ SXTB_ZZ
+ SXTB16_EQ
+ SXTB16_NE
+ SXTB16_CS
+ SXTB16_CC
+ SXTB16_MI
+ SXTB16_PL
+ SXTB16_VS
+ SXTB16_VC
+ SXTB16_HI
+ SXTB16_LS
+ SXTB16_GE
+ SXTB16_LT
+ SXTB16_GT
+ SXTB16_LE
+ SXTB16
+ SXTB16_ZZ
+ SXTH_EQ
+ SXTH_NE
+ SXTH_CS
+ SXTH_CC
+ SXTH_MI
+ SXTH_PL
+ SXTH_VS
+ SXTH_VC
+ SXTH_HI
+ SXTH_LS
+ SXTH_GE
+ SXTH_LT
+ SXTH_GT
+ SXTH_LE
+ SXTH
+ SXTH_ZZ
+ TEQ_EQ
+ TEQ_NE
+ TEQ_CS
+ TEQ_CC
+ TEQ_MI
+ TEQ_PL
+ TEQ_VS
+ TEQ_VC
+ TEQ_HI
+ TEQ_LS
+ TEQ_GE
+ TEQ_LT
+ TEQ_GT
+ TEQ_LE
+ TEQ
+ TEQ_ZZ
+ TST_EQ
+ TST_NE
+ TST_CS
+ TST_CC
+ TST_MI
+ TST_PL
+ TST_VS
+ TST_VC
+ TST_HI
+ TST_LS
+ TST_GE
+ TST_LT
+ TST_GT
+ TST_LE
+ TST
+ TST_ZZ
+ UADD16_EQ
+ UADD16_NE
+ UADD16_CS
+ UADD16_CC
+ UADD16_MI
+ UADD16_PL
+ UADD16_VS
+ UADD16_VC
+ UADD16_HI
+ UADD16_LS
+ UADD16_GE
+ UADD16_LT
+ UADD16_GT
+ UADD16_LE
+ UADD16
+ UADD16_ZZ
+ UADD8_EQ
+ UADD8_NE
+ UADD8_CS
+ UADD8_CC
+ UADD8_MI
+ UADD8_PL
+ UADD8_VS
+ UADD8_VC
+ UADD8_HI
+ UADD8_LS
+ UADD8_GE
+ UADD8_LT
+ UADD8_GT
+ UADD8_LE
+ UADD8
+ UADD8_ZZ
+ UASX_EQ
+ UASX_NE
+ UASX_CS
+ UASX_CC
+ UASX_MI
+ UASX_PL
+ UASX_VS
+ UASX_VC
+ UASX_HI
+ UASX_LS
+ UASX_GE
+ UASX_LT
+ UASX_GT
+ UASX_LE
+ UASX
+ UASX_ZZ
+ UBFX_EQ
+ UBFX_NE
+ UBFX_CS
+ UBFX_CC
+ UBFX_MI
+ UBFX_PL
+ UBFX_VS
+ UBFX_VC
+ UBFX_HI
+ UBFX_LS
+ UBFX_GE
+ UBFX_LT
+ UBFX_GT
+ UBFX_LE
+ UBFX
+ UBFX_ZZ
+ UHADD16_EQ
+ UHADD16_NE
+ UHADD16_CS
+ UHADD16_CC
+ UHADD16_MI
+ UHADD16_PL
+ UHADD16_VS
+ UHADD16_VC
+ UHADD16_HI
+ UHADD16_LS
+ UHADD16_GE
+ UHADD16_LT
+ UHADD16_GT
+ UHADD16_LE
+ UHADD16
+ UHADD16_ZZ
+ UHADD8_EQ
+ UHADD8_NE
+ UHADD8_CS
+ UHADD8_CC
+ UHADD8_MI
+ UHADD8_PL
+ UHADD8_VS
+ UHADD8_VC
+ UHADD8_HI
+ UHADD8_LS
+ UHADD8_GE
+ UHADD8_LT
+ UHADD8_GT
+ UHADD8_LE
+ UHADD8
+ UHADD8_ZZ
+ UHASX_EQ
+ UHASX_NE
+ UHASX_CS
+ UHASX_CC
+ UHASX_MI
+ UHASX_PL
+ UHASX_VS
+ UHASX_VC
+ UHASX_HI
+ UHASX_LS
+ UHASX_GE
+ UHASX_LT
+ UHASX_GT
+ UHASX_LE
+ UHASX
+ UHASX_ZZ
+ UHSAX_EQ
+ UHSAX_NE
+ UHSAX_CS
+ UHSAX_CC
+ UHSAX_MI
+ UHSAX_PL
+ UHSAX_VS
+ UHSAX_VC
+ UHSAX_HI
+ UHSAX_LS
+ UHSAX_GE
+ UHSAX_LT
+ UHSAX_GT
+ UHSAX_LE
+ UHSAX
+ UHSAX_ZZ
+ UHSUB16_EQ
+ UHSUB16_NE
+ UHSUB16_CS
+ UHSUB16_CC
+ UHSUB16_MI
+ UHSUB16_PL
+ UHSUB16_VS
+ UHSUB16_VC
+ UHSUB16_HI
+ UHSUB16_LS
+ UHSUB16_GE
+ UHSUB16_LT
+ UHSUB16_GT
+ UHSUB16_LE
+ UHSUB16
+ UHSUB16_ZZ
+ UHSUB8_EQ
+ UHSUB8_NE
+ UHSUB8_CS
+ UHSUB8_CC
+ UHSUB8_MI
+ UHSUB8_PL
+ UHSUB8_VS
+ UHSUB8_VC
+ UHSUB8_HI
+ UHSUB8_LS
+ UHSUB8_GE
+ UHSUB8_LT
+ UHSUB8_GT
+ UHSUB8_LE
+ UHSUB8
+ UHSUB8_ZZ
+ UMAAL_EQ
+ UMAAL_NE
+ UMAAL_CS
+ UMAAL_CC
+ UMAAL_MI
+ UMAAL_PL
+ UMAAL_VS
+ UMAAL_VC
+ UMAAL_HI
+ UMAAL_LS
+ UMAAL_GE
+ UMAAL_LT
+ UMAAL_GT
+ UMAAL_LE
+ UMAAL
+ UMAAL_ZZ
+ UMLAL_EQ
+ UMLAL_NE
+ UMLAL_CS
+ UMLAL_CC
+ UMLAL_MI
+ UMLAL_PL
+ UMLAL_VS
+ UMLAL_VC
+ UMLAL_HI
+ UMLAL_LS
+ UMLAL_GE
+ UMLAL_LT
+ UMLAL_GT
+ UMLAL_LE
+ UMLAL
+ UMLAL_ZZ
+ UMLAL_S_EQ
+ UMLAL_S_NE
+ UMLAL_S_CS
+ UMLAL_S_CC
+ UMLAL_S_MI
+ UMLAL_S_PL
+ UMLAL_S_VS
+ UMLAL_S_VC
+ UMLAL_S_HI
+ UMLAL_S_LS
+ UMLAL_S_GE
+ UMLAL_S_LT
+ UMLAL_S_GT
+ UMLAL_S_LE
+ UMLAL_S
+ UMLAL_S_ZZ
+ UMULL_EQ
+ UMULL_NE
+ UMULL_CS
+ UMULL_CC
+ UMULL_MI
+ UMULL_PL
+ UMULL_VS
+ UMULL_VC
+ UMULL_HI
+ UMULL_LS
+ UMULL_GE
+ UMULL_LT
+ UMULL_GT
+ UMULL_LE
+ UMULL
+ UMULL_ZZ
+ UMULL_S_EQ
+ UMULL_S_NE
+ UMULL_S_CS
+ UMULL_S_CC
+ UMULL_S_MI
+ UMULL_S_PL
+ UMULL_S_VS
+ UMULL_S_VC
+ UMULL_S_HI
+ UMULL_S_LS
+ UMULL_S_GE
+ UMULL_S_LT
+ UMULL_S_GT
+ UMULL_S_LE
+ UMULL_S
+ UMULL_S_ZZ
+ UNDEF
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ _
+ UQADD16_EQ
+ UQADD16_NE
+ UQADD16_CS
+ UQADD16_CC
+ UQADD16_MI
+ UQADD16_PL
+ UQADD16_VS
+ UQADD16_VC
+ UQADD16_HI
+ UQADD16_LS
+ UQADD16_GE
+ UQADD16_LT
+ UQADD16_GT
+ UQADD16_LE
+ UQADD16
+ UQADD16_ZZ
+ UQADD8_EQ
+ UQADD8_NE
+ UQADD8_CS
+ UQADD8_CC
+ UQADD8_MI
+ UQADD8_PL
+ UQADD8_VS
+ UQADD8_VC
+ UQADD8_HI
+ UQADD8_LS
+ UQADD8_GE
+ UQADD8_LT
+ UQADD8_GT
+ UQADD8_LE
+ UQADD8
+ UQADD8_ZZ
+ UQASX_EQ
+ UQASX_NE
+ UQASX_CS
+ UQASX_CC
+ UQASX_MI
+ UQASX_PL
+ UQASX_VS
+ UQASX_VC
+ UQASX_HI
+ UQASX_LS
+ UQASX_GE
+ UQASX_LT
+ UQASX_GT
+ UQASX_LE
+ UQASX
+ UQASX_ZZ
+ UQSAX_EQ
+ UQSAX_NE
+ UQSAX_CS
+ UQSAX_CC
+ UQSAX_MI
+ UQSAX_PL
+ UQSAX_VS
+ UQSAX_VC
+ UQSAX_HI
+ UQSAX_LS
+ UQSAX_GE
+ UQSAX_LT
+ UQSAX_GT
+ UQSAX_LE
+ UQSAX
+ UQSAX_ZZ
+ UQSUB16_EQ
+ UQSUB16_NE
+ UQSUB16_CS
+ UQSUB16_CC
+ UQSUB16_MI
+ UQSUB16_PL
+ UQSUB16_VS
+ UQSUB16_VC
+ UQSUB16_HI
+ UQSUB16_LS
+ UQSUB16_GE
+ UQSUB16_LT
+ UQSUB16_GT
+ UQSUB16_LE
+ UQSUB16
+ UQSUB16_ZZ
+ UQSUB8_EQ
+ UQSUB8_NE
+ UQSUB8_CS
+ UQSUB8_CC
+ UQSUB8_MI
+ UQSUB8_PL
+ UQSUB8_VS
+ UQSUB8_VC
+ UQSUB8_HI
+ UQSUB8_LS
+ UQSUB8_GE
+ UQSUB8_LT
+ UQSUB8_GT
+ UQSUB8_LE
+ UQSUB8
+ UQSUB8_ZZ
+ USAD8_EQ
+ USAD8_NE
+ USAD8_CS
+ USAD8_CC
+ USAD8_MI
+ USAD8_PL
+ USAD8_VS
+ USAD8_VC
+ USAD8_HI
+ USAD8_LS
+ USAD8_GE
+ USAD8_LT
+ USAD8_GT
+ USAD8_LE
+ USAD8
+ USAD8_ZZ
+ USADA8_EQ
+ USADA8_NE
+ USADA8_CS
+ USADA8_CC
+ USADA8_MI
+ USADA8_PL
+ USADA8_VS
+ USADA8_VC
+ USADA8_HI
+ USADA8_LS
+ USADA8_GE
+ USADA8_LT
+ USADA8_GT
+ USADA8_LE
+ USADA8
+ USADA8_ZZ
+ USAT_EQ
+ USAT_NE
+ USAT_CS
+ USAT_CC
+ USAT_MI
+ USAT_PL
+ USAT_VS
+ USAT_VC
+ USAT_HI
+ USAT_LS
+ USAT_GE
+ USAT_LT
+ USAT_GT
+ USAT_LE
+ USAT
+ USAT_ZZ
+ USAT16_EQ
+ USAT16_NE
+ USAT16_CS
+ USAT16_CC
+ USAT16_MI
+ USAT16_PL
+ USAT16_VS
+ USAT16_VC
+ USAT16_HI
+ USAT16_LS
+ USAT16_GE
+ USAT16_LT
+ USAT16_GT
+ USAT16_LE
+ USAT16
+ USAT16_ZZ
+ USAX_EQ
+ USAX_NE
+ USAX_CS
+ USAX_CC
+ USAX_MI
+ USAX_PL
+ USAX_VS
+ USAX_VC
+ USAX_HI
+ USAX_LS
+ USAX_GE
+ USAX_LT
+ USAX_GT
+ USAX_LE
+ USAX
+ USAX_ZZ
+ USUB16_EQ
+ USUB16_NE
+ USUB16_CS
+ USUB16_CC
+ USUB16_MI
+ USUB16_PL
+ USUB16_VS
+ USUB16_VC
+ USUB16_HI
+ USUB16_LS
+ USUB16_GE
+ USUB16_LT
+ USUB16_GT
+ USUB16_LE
+ USUB16
+ USUB16_ZZ
+ USUB8_EQ
+ USUB8_NE
+ USUB8_CS
+ USUB8_CC
+ USUB8_MI
+ USUB8_PL
+ USUB8_VS
+ USUB8_VC
+ USUB8_HI
+ USUB8_LS
+ USUB8_GE
+ USUB8_LT
+ USUB8_GT
+ USUB8_LE
+ USUB8
+ USUB8_ZZ
+ UXTAB_EQ
+ UXTAB_NE
+ UXTAB_CS
+ UXTAB_CC
+ UXTAB_MI
+ UXTAB_PL
+ UXTAB_VS
+ UXTAB_VC
+ UXTAB_HI
+ UXTAB_LS
+ UXTAB_GE
+ UXTAB_LT
+ UXTAB_GT
+ UXTAB_LE
+ UXTAB
+ UXTAB_ZZ
+ UXTAB16_EQ
+ UXTAB16_NE
+ UXTAB16_CS
+ UXTAB16_CC
+ UXTAB16_MI
+ UXTAB16_PL
+ UXTAB16_VS
+ UXTAB16_VC
+ UXTAB16_HI
+ UXTAB16_LS
+ UXTAB16_GE
+ UXTAB16_LT
+ UXTAB16_GT
+ UXTAB16_LE
+ UXTAB16
+ UXTAB16_ZZ
+ UXTAH_EQ
+ UXTAH_NE
+ UXTAH_CS
+ UXTAH_CC
+ UXTAH_MI
+ UXTAH_PL
+ UXTAH_VS
+ UXTAH_VC
+ UXTAH_HI
+ UXTAH_LS
+ UXTAH_GE
+ UXTAH_LT
+ UXTAH_GT
+ UXTAH_LE
+ UXTAH
+ UXTAH_ZZ
+ UXTB_EQ
+ UXTB_NE
+ UXTB_CS
+ UXTB_CC
+ UXTB_MI
+ UXTB_PL
+ UXTB_VS
+ UXTB_VC
+ UXTB_HI
+ UXTB_LS
+ UXTB_GE
+ UXTB_LT
+ UXTB_GT
+ UXTB_LE
+ UXTB
+ UXTB_ZZ
+ UXTB16_EQ
+ UXTB16_NE
+ UXTB16_CS
+ UXTB16_CC
+ UXTB16_MI
+ UXTB16_PL
+ UXTB16_VS
+ UXTB16_VC
+ UXTB16_HI
+ UXTB16_LS
+ UXTB16_GE
+ UXTB16_LT
+ UXTB16_GT
+ UXTB16_LE
+ UXTB16
+ UXTB16_ZZ
+ UXTH_EQ
+ UXTH_NE
+ UXTH_CS
+ UXTH_CC
+ UXTH_MI
+ UXTH_PL
+ UXTH_VS
+ UXTH_VC
+ UXTH_HI
+ UXTH_LS
+ UXTH_GE
+ UXTH_LT
+ UXTH_GT
+ UXTH_LE
+ UXTH
+ UXTH_ZZ
+ VABS_EQ_F32
+ VABS_NE_F32
+ VABS_CS_F32
+ VABS_CC_F32
+ VABS_MI_F32
+ VABS_PL_F32
+ VABS_VS_F32
+ VABS_VC_F32
+ VABS_HI_F32
+ VABS_LS_F32
+ VABS_GE_F32
+ VABS_LT_F32
+ VABS_GT_F32
+ VABS_LE_F32
+ VABS_F32
+ VABS_ZZ_F32
+ VABS_EQ_F64
+ VABS_NE_F64
+ VABS_CS_F64
+ VABS_CC_F64
+ VABS_MI_F64
+ VABS_PL_F64
+ VABS_VS_F64
+ VABS_VC_F64
+ VABS_HI_F64
+ VABS_LS_F64
+ VABS_GE_F64
+ VABS_LT_F64
+ VABS_GT_F64
+ VABS_LE_F64
+ VABS_F64
+ VABS_ZZ_F64
+ VADD_EQ_F32
+ VADD_NE_F32
+ VADD_CS_F32
+ VADD_CC_F32
+ VADD_MI_F32
+ VADD_PL_F32
+ VADD_VS_F32
+ VADD_VC_F32
+ VADD_HI_F32
+ VADD_LS_F32
+ VADD_GE_F32
+ VADD_LT_F32
+ VADD_GT_F32
+ VADD_LE_F32
+ VADD_F32
+ VADD_ZZ_F32
+ VADD_EQ_F64
+ VADD_NE_F64
+ VADD_CS_F64
+ VADD_CC_F64
+ VADD_MI_F64
+ VADD_PL_F64
+ VADD_VS_F64
+ VADD_VC_F64
+ VADD_HI_F64
+ VADD_LS_F64
+ VADD_GE_F64
+ VADD_LT_F64
+ VADD_GT_F64
+ VADD_LE_F64
+ VADD_F64
+ VADD_ZZ_F64
+ VCMP_EQ_F32
+ VCMP_NE_F32
+ VCMP_CS_F32
+ VCMP_CC_F32
+ VCMP_MI_F32
+ VCMP_PL_F32
+ VCMP_VS_F32
+ VCMP_VC_F32
+ VCMP_HI_F32
+ VCMP_LS_F32
+ VCMP_GE_F32
+ VCMP_LT_F32
+ VCMP_GT_F32
+ VCMP_LE_F32
+ VCMP_F32
+ VCMP_ZZ_F32
+ VCMP_EQ_F64
+ VCMP_NE_F64
+ VCMP_CS_F64
+ VCMP_CC_F64
+ VCMP_MI_F64
+ VCMP_PL_F64
+ VCMP_VS_F64
+ VCMP_VC_F64
+ VCMP_HI_F64
+ VCMP_LS_F64
+ VCMP_GE_F64
+ VCMP_LT_F64
+ VCMP_GT_F64
+ VCMP_LE_F64
+ VCMP_F64
+ VCMP_ZZ_F64
+ VCMP_E_EQ_F32
+ VCMP_E_NE_F32
+ VCMP_E_CS_F32
+ VCMP_E_CC_F32
+ VCMP_E_MI_F32
+ VCMP_E_PL_F32
+ VCMP_E_VS_F32
+ VCMP_E_VC_F32
+ VCMP_E_HI_F32
+ VCMP_E_LS_F32
+ VCMP_E_GE_F32
+ VCMP_E_LT_F32
+ VCMP_E_GT_F32
+ VCMP_E_LE_F32
+ VCMP_E_F32
+ VCMP_E_ZZ_F32
+ VCMP_E_EQ_F64
+ VCMP_E_NE_F64
+ VCMP_E_CS_F64
+ VCMP_E_CC_F64
+ VCMP_E_MI_F64
+ VCMP_E_PL_F64
+ VCMP_E_VS_F64
+ VCMP_E_VC_F64
+ VCMP_E_HI_F64
+ VCMP_E_LS_F64
+ VCMP_E_GE_F64
+ VCMP_E_LT_F64
+ VCMP_E_GT_F64
+ VCMP_E_LE_F64
+ VCMP_E_F64
+ VCMP_E_ZZ_F64
+ VCVT_EQ_F32_FXS16
+ VCVT_NE_F32_FXS16
+ VCVT_CS_F32_FXS16
+ VCVT_CC_F32_FXS16
+ VCVT_MI_F32_FXS16
+ VCVT_PL_F32_FXS16
+ VCVT_VS_F32_FXS16
+ VCVT_VC_F32_FXS16
+ VCVT_HI_F32_FXS16
+ VCVT_LS_F32_FXS16
+ VCVT_GE_F32_FXS16
+ VCVT_LT_F32_FXS16
+ VCVT_GT_F32_FXS16
+ VCVT_LE_F32_FXS16
+ VCVT_F32_FXS16
+ VCVT_ZZ_F32_FXS16
+ VCVT_EQ_F32_FXS32
+ VCVT_NE_F32_FXS32
+ VCVT_CS_F32_FXS32
+ VCVT_CC_F32_FXS32
+ VCVT_MI_F32_FXS32
+ VCVT_PL_F32_FXS32
+ VCVT_VS_F32_FXS32
+ VCVT_VC_F32_FXS32
+ VCVT_HI_F32_FXS32
+ VCVT_LS_F32_FXS32
+ VCVT_GE_F32_FXS32
+ VCVT_LT_F32_FXS32
+ VCVT_GT_F32_FXS32
+ VCVT_LE_F32_FXS32
+ VCVT_F32_FXS32
+ VCVT_ZZ_F32_FXS32
+ VCVT_EQ_F32_FXU16
+ VCVT_NE_F32_FXU16
+ VCVT_CS_F32_FXU16
+ VCVT_CC_F32_FXU16
+ VCVT_MI_F32_FXU16
+ VCVT_PL_F32_FXU16
+ VCVT_VS_F32_FXU16
+ VCVT_VC_F32_FXU16
+ VCVT_HI_F32_FXU16
+ VCVT_LS_F32_FXU16
+ VCVT_GE_F32_FXU16
+ VCVT_LT_F32_FXU16
+ VCVT_GT_F32_FXU16
+ VCVT_LE_F32_FXU16
+ VCVT_F32_FXU16
+ VCVT_ZZ_F32_FXU16
+ VCVT_EQ_F32_FXU32
+ VCVT_NE_F32_FXU32
+ VCVT_CS_F32_FXU32
+ VCVT_CC_F32_FXU32
+ VCVT_MI_F32_FXU32
+ VCVT_PL_F32_FXU32
+ VCVT_VS_F32_FXU32
+ VCVT_VC_F32_FXU32
+ VCVT_HI_F32_FXU32
+ VCVT_LS_F32_FXU32
+ VCVT_GE_F32_FXU32
+ VCVT_LT_F32_FXU32
+ VCVT_GT_F32_FXU32
+ VCVT_LE_F32_FXU32
+ VCVT_F32_FXU32
+ VCVT_ZZ_F32_FXU32
+ VCVT_EQ_F64_FXS16
+ VCVT_NE_F64_FXS16
+ VCVT_CS_F64_FXS16
+ VCVT_CC_F64_FXS16
+ VCVT_MI_F64_FXS16
+ VCVT_PL_F64_FXS16
+ VCVT_VS_F64_FXS16
+ VCVT_VC_F64_FXS16
+ VCVT_HI_F64_FXS16
+ VCVT_LS_F64_FXS16
+ VCVT_GE_F64_FXS16
+ VCVT_LT_F64_FXS16
+ VCVT_GT_F64_FXS16
+ VCVT_LE_F64_FXS16
+ VCVT_F64_FXS16
+ VCVT_ZZ_F64_FXS16
+ VCVT_EQ_F64_FXS32
+ VCVT_NE_F64_FXS32
+ VCVT_CS_F64_FXS32
+ VCVT_CC_F64_FXS32
+ VCVT_MI_F64_FXS32
+ VCVT_PL_F64_FXS32
+ VCVT_VS_F64_FXS32
+ VCVT_VC_F64_FXS32
+ VCVT_HI_F64_FXS32
+ VCVT_LS_F64_FXS32
+ VCVT_GE_F64_FXS32
+ VCVT_LT_F64_FXS32
+ VCVT_GT_F64_FXS32
+ VCVT_LE_F64_FXS32
+ VCVT_F64_FXS32
+ VCVT_ZZ_F64_FXS32
+ VCVT_EQ_F64_FXU16
+ VCVT_NE_F64_FXU16
+ VCVT_CS_F64_FXU16
+ VCVT_CC_F64_FXU16
+ VCVT_MI_F64_FXU16
+ VCVT_PL_F64_FXU16
+ VCVT_VS_F64_FXU16
+ VCVT_VC_F64_FXU16
+ VCVT_HI_F64_FXU16
+ VCVT_LS_F64_FXU16
+ VCVT_GE_F64_FXU16
+ VCVT_LT_F64_FXU16
+ VCVT_GT_F64_FXU16
+ VCVT_LE_F64_FXU16
+ VCVT_F64_FXU16
+ VCVT_ZZ_F64_FXU16
+ VCVT_EQ_F64_FXU32
+ VCVT_NE_F64_FXU32
+ VCVT_CS_F64_FXU32
+ VCVT_CC_F64_FXU32
+ VCVT_MI_F64_FXU32
+ VCVT_PL_F64_FXU32
+ VCVT_VS_F64_FXU32
+ VCVT_VC_F64_FXU32
+ VCVT_HI_F64_FXU32
+ VCVT_LS_F64_FXU32
+ VCVT_GE_F64_FXU32
+ VCVT_LT_F64_FXU32
+ VCVT_GT_F64_FXU32
+ VCVT_LE_F64_FXU32
+ VCVT_F64_FXU32
+ VCVT_ZZ_F64_FXU32
+ VCVT_EQ_F32_U32
+ VCVT_NE_F32_U32
+ VCVT_CS_F32_U32
+ VCVT_CC_F32_U32
+ VCVT_MI_F32_U32
+ VCVT_PL_F32_U32
+ VCVT_VS_F32_U32
+ VCVT_VC_F32_U32
+ VCVT_HI_F32_U32
+ VCVT_LS_F32_U32
+ VCVT_GE_F32_U32
+ VCVT_LT_F32_U32
+ VCVT_GT_F32_U32
+ VCVT_LE_F32_U32
+ VCVT_F32_U32
+ VCVT_ZZ_F32_U32
+ VCVT_EQ_F32_S32
+ VCVT_NE_F32_S32
+ VCVT_CS_F32_S32
+ VCVT_CC_F32_S32
+ VCVT_MI_F32_S32
+ VCVT_PL_F32_S32
+ VCVT_VS_F32_S32
+ VCVT_VC_F32_S32
+ VCVT_HI_F32_S32
+ VCVT_LS_F32_S32
+ VCVT_GE_F32_S32
+ VCVT_LT_F32_S32
+ VCVT_GT_F32_S32
+ VCVT_LE_F32_S32
+ VCVT_F32_S32
+ VCVT_ZZ_F32_S32
+ VCVT_EQ_F64_U32
+ VCVT_NE_F64_U32
+ VCVT_CS_F64_U32
+ VCVT_CC_F64_U32
+ VCVT_MI_F64_U32
+ VCVT_PL_F64_U32
+ VCVT_VS_F64_U32
+ VCVT_VC_F64_U32
+ VCVT_HI_F64_U32
+ VCVT_LS_F64_U32
+ VCVT_GE_F64_U32
+ VCVT_LT_F64_U32
+ VCVT_GT_F64_U32
+ VCVT_LE_F64_U32
+ VCVT_F64_U32
+ VCVT_ZZ_F64_U32
+ VCVT_EQ_F64_S32
+ VCVT_NE_F64_S32
+ VCVT_CS_F64_S32
+ VCVT_CC_F64_S32
+ VCVT_MI_F64_S32
+ VCVT_PL_F64_S32
+ VCVT_VS_F64_S32
+ VCVT_VC_F64_S32
+ VCVT_HI_F64_S32
+ VCVT_LS_F64_S32
+ VCVT_GE_F64_S32
+ VCVT_LT_F64_S32
+ VCVT_GT_F64_S32
+ VCVT_LE_F64_S32
+ VCVT_F64_S32
+ VCVT_ZZ_F64_S32
+ VCVT_EQ_F64_F32
+ VCVT_NE_F64_F32
+ VCVT_CS_F64_F32
+ VCVT_CC_F64_F32
+ VCVT_MI_F64_F32
+ VCVT_PL_F64_F32
+ VCVT_VS_F64_F32
+ VCVT_VC_F64_F32
+ VCVT_HI_F64_F32
+ VCVT_LS_F64_F32
+ VCVT_GE_F64_F32
+ VCVT_LT_F64_F32
+ VCVT_GT_F64_F32
+ VCVT_LE_F64_F32
+ VCVT_F64_F32
+ VCVT_ZZ_F64_F32
+ VCVT_EQ_F32_F64
+ VCVT_NE_F32_F64
+ VCVT_CS_F32_F64
+ VCVT_CC_F32_F64
+ VCVT_MI_F32_F64
+ VCVT_PL_F32_F64
+ VCVT_VS_F32_F64
+ VCVT_VC_F32_F64
+ VCVT_HI_F32_F64
+ VCVT_LS_F32_F64
+ VCVT_GE_F32_F64
+ VCVT_LT_F32_F64
+ VCVT_GT_F32_F64
+ VCVT_LE_F32_F64
+ VCVT_F32_F64
+ VCVT_ZZ_F32_F64
+ VCVT_EQ_FXS16_F32
+ VCVT_NE_FXS16_F32
+ VCVT_CS_FXS16_F32
+ VCVT_CC_FXS16_F32
+ VCVT_MI_FXS16_F32
+ VCVT_PL_FXS16_F32
+ VCVT_VS_FXS16_F32
+ VCVT_VC_FXS16_F32
+ VCVT_HI_FXS16_F32
+ VCVT_LS_FXS16_F32
+ VCVT_GE_FXS16_F32
+ VCVT_LT_FXS16_F32
+ VCVT_GT_FXS16_F32
+ VCVT_LE_FXS16_F32
+ VCVT_FXS16_F32
+ VCVT_ZZ_FXS16_F32
+ VCVT_EQ_FXS16_F64
+ VCVT_NE_FXS16_F64
+ VCVT_CS_FXS16_F64
+ VCVT_CC_FXS16_F64
+ VCVT_MI_FXS16_F64
+ VCVT_PL_FXS16_F64
+ VCVT_VS_FXS16_F64
+ VCVT_VC_FXS16_F64
+ VCVT_HI_FXS16_F64
+ VCVT_LS_FXS16_F64
+ VCVT_GE_FXS16_F64
+ VCVT_LT_FXS16_F64
+ VCVT_GT_FXS16_F64
+ VCVT_LE_FXS16_F64
+ VCVT_FXS16_F64
+ VCVT_ZZ_FXS16_F64
+ VCVT_EQ_FXS32_F32
+ VCVT_NE_FXS32_F32
+ VCVT_CS_FXS32_F32
+ VCVT_CC_FXS32_F32
+ VCVT_MI_FXS32_F32
+ VCVT_PL_FXS32_F32
+ VCVT_VS_FXS32_F32
+ VCVT_VC_FXS32_F32
+ VCVT_HI_FXS32_F32
+ VCVT_LS_FXS32_F32
+ VCVT_GE_FXS32_F32
+ VCVT_LT_FXS32_F32
+ VCVT_GT_FXS32_F32
+ VCVT_LE_FXS32_F32
+ VCVT_FXS32_F32
+ VCVT_ZZ_FXS32_F32
+ VCVT_EQ_FXS32_F64
+ VCVT_NE_FXS32_F64
+ VCVT_CS_FXS32_F64
+ VCVT_CC_FXS32_F64
+ VCVT_MI_FXS32_F64
+ VCVT_PL_FXS32_F64
+ VCVT_VS_FXS32_F64
+ VCVT_VC_FXS32_F64
+ VCVT_HI_FXS32_F64
+ VCVT_LS_FXS32_F64
+ VCVT_GE_FXS32_F64
+ VCVT_LT_FXS32_F64
+ VCVT_GT_FXS32_F64
+ VCVT_LE_FXS32_F64
+ VCVT_FXS32_F64
+ VCVT_ZZ_FXS32_F64
+ VCVT_EQ_FXU16_F32
+ VCVT_NE_FXU16_F32
+ VCVT_CS_FXU16_F32
+ VCVT_CC_FXU16_F32
+ VCVT_MI_FXU16_F32
+ VCVT_PL_FXU16_F32
+ VCVT_VS_FXU16_F32
+ VCVT_VC_FXU16_F32
+ VCVT_HI_FXU16_F32
+ VCVT_LS_FXU16_F32
+ VCVT_GE_FXU16_F32
+ VCVT_LT_FXU16_F32
+ VCVT_GT_FXU16_F32
+ VCVT_LE_FXU16_F32
+ VCVT_FXU16_F32
+ VCVT_ZZ_FXU16_F32
+ VCVT_EQ_FXU16_F64
+ VCVT_NE_FXU16_F64
+ VCVT_CS_FXU16_F64
+ VCVT_CC_FXU16_F64
+ VCVT_MI_FXU16_F64
+ VCVT_PL_FXU16_F64
+ VCVT_VS_FXU16_F64
+ VCVT_VC_FXU16_F64
+ VCVT_HI_FXU16_F64
+ VCVT_LS_FXU16_F64
+ VCVT_GE_FXU16_F64
+ VCVT_LT_FXU16_F64
+ VCVT_GT_FXU16_F64
+ VCVT_LE_FXU16_F64
+ VCVT_FXU16_F64
+ VCVT_ZZ_FXU16_F64
+ VCVT_EQ_FXU32_F32
+ VCVT_NE_FXU32_F32
+ VCVT_CS_FXU32_F32
+ VCVT_CC_FXU32_F32
+ VCVT_MI_FXU32_F32
+ VCVT_PL_FXU32_F32
+ VCVT_VS_FXU32_F32
+ VCVT_VC_FXU32_F32
+ VCVT_HI_FXU32_F32
+ VCVT_LS_FXU32_F32
+ VCVT_GE_FXU32_F32
+ VCVT_LT_FXU32_F32
+ VCVT_GT_FXU32_F32
+ VCVT_LE_FXU32_F32
+ VCVT_FXU32_F32
+ VCVT_ZZ_FXU32_F32
+ VCVT_EQ_FXU32_F64
+ VCVT_NE_FXU32_F64
+ VCVT_CS_FXU32_F64
+ VCVT_CC_FXU32_F64
+ VCVT_MI_FXU32_F64
+ VCVT_PL_FXU32_F64
+ VCVT_VS_FXU32_F64
+ VCVT_VC_FXU32_F64
+ VCVT_HI_FXU32_F64
+ VCVT_LS_FXU32_F64
+ VCVT_GE_FXU32_F64
+ VCVT_LT_FXU32_F64
+ VCVT_GT_FXU32_F64
+ VCVT_LE_FXU32_F64
+ VCVT_FXU32_F64
+ VCVT_ZZ_FXU32_F64
+ VCVTB_EQ_F32_F16
+ VCVTB_NE_F32_F16
+ VCVTB_CS_F32_F16
+ VCVTB_CC_F32_F16
+ VCVTB_MI_F32_F16
+ VCVTB_PL_F32_F16
+ VCVTB_VS_F32_F16
+ VCVTB_VC_F32_F16
+ VCVTB_HI_F32_F16
+ VCVTB_LS_F32_F16
+ VCVTB_GE_F32_F16
+ VCVTB_LT_F32_F16
+ VCVTB_GT_F32_F16
+ VCVTB_LE_F32_F16
+ VCVTB_F32_F16
+ VCVTB_ZZ_F32_F16
+ VCVTB_EQ_F16_F32
+ VCVTB_NE_F16_F32
+ VCVTB_CS_F16_F32
+ VCVTB_CC_F16_F32
+ VCVTB_MI_F16_F32
+ VCVTB_PL_F16_F32
+ VCVTB_VS_F16_F32
+ VCVTB_VC_F16_F32
+ VCVTB_HI_F16_F32
+ VCVTB_LS_F16_F32
+ VCVTB_GE_F16_F32
+ VCVTB_LT_F16_F32
+ VCVTB_GT_F16_F32
+ VCVTB_LE_F16_F32
+ VCVTB_F16_F32
+ VCVTB_ZZ_F16_F32
+ VCVTT_EQ_F32_F16
+ VCVTT_NE_F32_F16
+ VCVTT_CS_F32_F16
+ VCVTT_CC_F32_F16
+ VCVTT_MI_F32_F16
+ VCVTT_PL_F32_F16
+ VCVTT_VS_F32_F16
+ VCVTT_VC_F32_F16
+ VCVTT_HI_F32_F16
+ VCVTT_LS_F32_F16
+ VCVTT_GE_F32_F16
+ VCVTT_LT_F32_F16
+ VCVTT_GT_F32_F16
+ VCVTT_LE_F32_F16
+ VCVTT_F32_F16
+ VCVTT_ZZ_F32_F16
+ VCVTT_EQ_F16_F32
+ VCVTT_NE_F16_F32
+ VCVTT_CS_F16_F32
+ VCVTT_CC_F16_F32
+ VCVTT_MI_F16_F32
+ VCVTT_PL_F16_F32
+ VCVTT_VS_F16_F32
+ VCVTT_VC_F16_F32
+ VCVTT_HI_F16_F32
+ VCVTT_LS_F16_F32
+ VCVTT_GE_F16_F32
+ VCVTT_LT_F16_F32
+ VCVTT_GT_F16_F32
+ VCVTT_LE_F16_F32
+ VCVTT_F16_F32
+ VCVTT_ZZ_F16_F32
+ VCVTR_EQ_U32_F32
+ VCVTR_NE_U32_F32
+ VCVTR_CS_U32_F32
+ VCVTR_CC_U32_F32
+ VCVTR_MI_U32_F32
+ VCVTR_PL_U32_F32
+ VCVTR_VS_U32_F32
+ VCVTR_VC_U32_F32
+ VCVTR_HI_U32_F32
+ VCVTR_LS_U32_F32
+ VCVTR_GE_U32_F32
+ VCVTR_LT_U32_F32
+ VCVTR_GT_U32_F32
+ VCVTR_LE_U32_F32
+ VCVTR_U32_F32
+ VCVTR_ZZ_U32_F32
+ VCVTR_EQ_U32_F64
+ VCVTR_NE_U32_F64
+ VCVTR_CS_U32_F64
+ VCVTR_CC_U32_F64
+ VCVTR_MI_U32_F64
+ VCVTR_PL_U32_F64
+ VCVTR_VS_U32_F64
+ VCVTR_VC_U32_F64
+ VCVTR_HI_U32_F64
+ VCVTR_LS_U32_F64
+ VCVTR_GE_U32_F64
+ VCVTR_LT_U32_F64
+ VCVTR_GT_U32_F64
+ VCVTR_LE_U32_F64
+ VCVTR_U32_F64
+ VCVTR_ZZ_U32_F64
+ VCVTR_EQ_S32_F32
+ VCVTR_NE_S32_F32
+ VCVTR_CS_S32_F32
+ VCVTR_CC_S32_F32
+ VCVTR_MI_S32_F32
+ VCVTR_PL_S32_F32
+ VCVTR_VS_S32_F32
+ VCVTR_VC_S32_F32
+ VCVTR_HI_S32_F32
+ VCVTR_LS_S32_F32
+ VCVTR_GE_S32_F32
+ VCVTR_LT_S32_F32
+ VCVTR_GT_S32_F32
+ VCVTR_LE_S32_F32
+ VCVTR_S32_F32
+ VCVTR_ZZ_S32_F32
+ VCVTR_EQ_S32_F64
+ VCVTR_NE_S32_F64
+ VCVTR_CS_S32_F64
+ VCVTR_CC_S32_F64
+ VCVTR_MI_S32_F64
+ VCVTR_PL_S32_F64
+ VCVTR_VS_S32_F64
+ VCVTR_VC_S32_F64
+ VCVTR_HI_S32_F64
+ VCVTR_LS_S32_F64
+ VCVTR_GE_S32_F64
+ VCVTR_LT_S32_F64
+ VCVTR_GT_S32_F64
+ VCVTR_LE_S32_F64
+ VCVTR_S32_F64
+ VCVTR_ZZ_S32_F64
+ VCVT_EQ_U32_F32
+ VCVT_NE_U32_F32
+ VCVT_CS_U32_F32
+ VCVT_CC_U32_F32
+ VCVT_MI_U32_F32
+ VCVT_PL_U32_F32
+ VCVT_VS_U32_F32
+ VCVT_VC_U32_F32
+ VCVT_HI_U32_F32
+ VCVT_LS_U32_F32
+ VCVT_GE_U32_F32
+ VCVT_LT_U32_F32
+ VCVT_GT_U32_F32
+ VCVT_LE_U32_F32
+ VCVT_U32_F32
+ VCVT_ZZ_U32_F32
+ VCVT_EQ_U32_F64
+ VCVT_NE_U32_F64
+ VCVT_CS_U32_F64
+ VCVT_CC_U32_F64
+ VCVT_MI_U32_F64
+ VCVT_PL_U32_F64
+ VCVT_VS_U32_F64
+ VCVT_VC_U32_F64
+ VCVT_HI_U32_F64
+ VCVT_LS_U32_F64
+ VCVT_GE_U32_F64
+ VCVT_LT_U32_F64
+ VCVT_GT_U32_F64
+ VCVT_LE_U32_F64
+ VCVT_U32_F64
+ VCVT_ZZ_U32_F64
+ VCVT_EQ_S32_F32
+ VCVT_NE_S32_F32
+ VCVT_CS_S32_F32
+ VCVT_CC_S32_F32
+ VCVT_MI_S32_F32
+ VCVT_PL_S32_F32
+ VCVT_VS_S32_F32
+ VCVT_VC_S32_F32
+ VCVT_HI_S32_F32
+ VCVT_LS_S32_F32
+ VCVT_GE_S32_F32
+ VCVT_LT_S32_F32
+ VCVT_GT_S32_F32
+ VCVT_LE_S32_F32
+ VCVT_S32_F32
+ VCVT_ZZ_S32_F32
+ VCVT_EQ_S32_F64
+ VCVT_NE_S32_F64
+ VCVT_CS_S32_F64
+ VCVT_CC_S32_F64
+ VCVT_MI_S32_F64
+ VCVT_PL_S32_F64
+ VCVT_VS_S32_F64
+ VCVT_VC_S32_F64
+ VCVT_HI_S32_F64
+ VCVT_LS_S32_F64
+ VCVT_GE_S32_F64
+ VCVT_LT_S32_F64
+ VCVT_GT_S32_F64
+ VCVT_LE_S32_F64
+ VCVT_S32_F64
+ VCVT_ZZ_S32_F64
+ VDIV_EQ_F32
+ VDIV_NE_F32
+ VDIV_CS_F32
+ VDIV_CC_F32
+ VDIV_MI_F32
+ VDIV_PL_F32
+ VDIV_VS_F32
+ VDIV_VC_F32
+ VDIV_HI_F32
+ VDIV_LS_F32
+ VDIV_GE_F32
+ VDIV_LT_F32
+ VDIV_GT_F32
+ VDIV_LE_F32
+ VDIV_F32
+ VDIV_ZZ_F32
+ VDIV_EQ_F64
+ VDIV_NE_F64
+ VDIV_CS_F64
+ VDIV_CC_F64
+ VDIV_MI_F64
+ VDIV_PL_F64
+ VDIV_VS_F64
+ VDIV_VC_F64
+ VDIV_HI_F64
+ VDIV_LS_F64
+ VDIV_GE_F64
+ VDIV_LT_F64
+ VDIV_GT_F64
+ VDIV_LE_F64
+ VDIV_F64
+ VDIV_ZZ_F64
+ VLDR_EQ
+ VLDR_NE
+ VLDR_CS
+ VLDR_CC
+ VLDR_MI
+ VLDR_PL
+ VLDR_VS
+ VLDR_VC
+ VLDR_HI
+ VLDR_LS
+ VLDR_GE
+ VLDR_LT
+ VLDR_GT
+ VLDR_LE
+ VLDR
+ VLDR_ZZ
+ VMLA_EQ_F32
+ VMLA_NE_F32
+ VMLA_CS_F32
+ VMLA_CC_F32
+ VMLA_MI_F32
+ VMLA_PL_F32
+ VMLA_VS_F32
+ VMLA_VC_F32
+ VMLA_HI_F32
+ VMLA_LS_F32
+ VMLA_GE_F32
+ VMLA_LT_F32
+ VMLA_GT_F32
+ VMLA_LE_F32
+ VMLA_F32
+ VMLA_ZZ_F32
+ VMLA_EQ_F64
+ VMLA_NE_F64
+ VMLA_CS_F64
+ VMLA_CC_F64
+ VMLA_MI_F64
+ VMLA_PL_F64
+ VMLA_VS_F64
+ VMLA_VC_F64
+ VMLA_HI_F64
+ VMLA_LS_F64
+ VMLA_GE_F64
+ VMLA_LT_F64
+ VMLA_GT_F64
+ VMLA_LE_F64
+ VMLA_F64
+ VMLA_ZZ_F64
+ VMLS_EQ_F32
+ VMLS_NE_F32
+ VMLS_CS_F32
+ VMLS_CC_F32
+ VMLS_MI_F32
+ VMLS_PL_F32
+ VMLS_VS_F32
+ VMLS_VC_F32
+ VMLS_HI_F32
+ VMLS_LS_F32
+ VMLS_GE_F32
+ VMLS_LT_F32
+ VMLS_GT_F32
+ VMLS_LE_F32
+ VMLS_F32
+ VMLS_ZZ_F32
+ VMLS_EQ_F64
+ VMLS_NE_F64
+ VMLS_CS_F64
+ VMLS_CC_F64
+ VMLS_MI_F64
+ VMLS_PL_F64
+ VMLS_VS_F64
+ VMLS_VC_F64
+ VMLS_HI_F64
+ VMLS_LS_F64
+ VMLS_GE_F64
+ VMLS_LT_F64
+ VMLS_GT_F64
+ VMLS_LE_F64
+ VMLS_F64
+ VMLS_ZZ_F64
+ VMOV_EQ
+ VMOV_NE
+ VMOV_CS
+ VMOV_CC
+ VMOV_MI
+ VMOV_PL
+ VMOV_VS
+ VMOV_VC
+ VMOV_HI
+ VMOV_LS
+ VMOV_GE
+ VMOV_LT
+ VMOV_GT
+ VMOV_LE
+ VMOV
+ VMOV_ZZ
+ VMOV_EQ_32
+ VMOV_NE_32
+ VMOV_CS_32
+ VMOV_CC_32
+ VMOV_MI_32
+ VMOV_PL_32
+ VMOV_VS_32
+ VMOV_VC_32
+ VMOV_HI_32
+ VMOV_LS_32
+ VMOV_GE_32
+ VMOV_LT_32
+ VMOV_GT_32
+ VMOV_LE_32
+ VMOV_32
+ VMOV_ZZ_32
+ VMOV_EQ_F32
+ VMOV_NE_F32
+ VMOV_CS_F32
+ VMOV_CC_F32
+ VMOV_MI_F32
+ VMOV_PL_F32
+ VMOV_VS_F32
+ VMOV_VC_F32
+ VMOV_HI_F32
+ VMOV_LS_F32
+ VMOV_GE_F32
+ VMOV_LT_F32
+ VMOV_GT_F32
+ VMOV_LE_F32
+ VMOV_F32
+ VMOV_ZZ_F32
+ VMOV_EQ_F64
+ VMOV_NE_F64
+ VMOV_CS_F64
+ VMOV_CC_F64
+ VMOV_MI_F64
+ VMOV_PL_F64
+ VMOV_VS_F64
+ VMOV_VC_F64
+ VMOV_HI_F64
+ VMOV_LS_F64
+ VMOV_GE_F64
+ VMOV_LT_F64
+ VMOV_GT_F64
+ VMOV_LE_F64
+ VMOV_F64
+ VMOV_ZZ_F64
+ VMRS_EQ
+ VMRS_NE
+ VMRS_CS
+ VMRS_CC
+ VMRS_MI
+ VMRS_PL
+ VMRS_VS
+ VMRS_VC
+ VMRS_HI
+ VMRS_LS
+ VMRS_GE
+ VMRS_LT
+ VMRS_GT
+ VMRS_LE
+ VMRS
+ VMRS_ZZ
+ VMSR_EQ
+ VMSR_NE
+ VMSR_CS
+ VMSR_CC
+ VMSR_MI
+ VMSR_PL
+ VMSR_VS
+ VMSR_VC
+ VMSR_HI
+ VMSR_LS
+ VMSR_GE
+ VMSR_LT
+ VMSR_GT
+ VMSR_LE
+ VMSR
+ VMSR_ZZ
+ VMUL_EQ_F32
+ VMUL_NE_F32
+ VMUL_CS_F32
+ VMUL_CC_F32
+ VMUL_MI_F32
+ VMUL_PL_F32
+ VMUL_VS_F32
+ VMUL_VC_F32
+ VMUL_HI_F32
+ VMUL_LS_F32
+ VMUL_GE_F32
+ VMUL_LT_F32
+ VMUL_GT_F32
+ VMUL_LE_F32
+ VMUL_F32
+ VMUL_ZZ_F32
+ VMUL_EQ_F64
+ VMUL_NE_F64
+ VMUL_CS_F64
+ VMUL_CC_F64
+ VMUL_MI_F64
+ VMUL_PL_F64
+ VMUL_VS_F64
+ VMUL_VC_F64
+ VMUL_HI_F64
+ VMUL_LS_F64
+ VMUL_GE_F64
+ VMUL_LT_F64
+ VMUL_GT_F64
+ VMUL_LE_F64
+ VMUL_F64
+ VMUL_ZZ_F64
+ VNEG_EQ_F32
+ VNEG_NE_F32
+ VNEG_CS_F32
+ VNEG_CC_F32
+ VNEG_MI_F32
+ VNEG_PL_F32
+ VNEG_VS_F32
+ VNEG_VC_F32
+ VNEG_HI_F32
+ VNEG_LS_F32
+ VNEG_GE_F32
+ VNEG_LT_F32
+ VNEG_GT_F32
+ VNEG_LE_F32
+ VNEG_F32
+ VNEG_ZZ_F32
+ VNEG_EQ_F64
+ VNEG_NE_F64
+ VNEG_CS_F64
+ VNEG_CC_F64
+ VNEG_MI_F64
+ VNEG_PL_F64
+ VNEG_VS_F64
+ VNEG_VC_F64
+ VNEG_HI_F64
+ VNEG_LS_F64
+ VNEG_GE_F64
+ VNEG_LT_F64
+ VNEG_GT_F64
+ VNEG_LE_F64
+ VNEG_F64
+ VNEG_ZZ_F64
+ VNMLS_EQ_F32
+ VNMLS_NE_F32
+ VNMLS_CS_F32
+ VNMLS_CC_F32
+ VNMLS_MI_F32
+ VNMLS_PL_F32
+ VNMLS_VS_F32
+ VNMLS_VC_F32
+ VNMLS_HI_F32
+ VNMLS_LS_F32
+ VNMLS_GE_F32
+ VNMLS_LT_F32
+ VNMLS_GT_F32
+ VNMLS_LE_F32
+ VNMLS_F32
+ VNMLS_ZZ_F32
+ VNMLS_EQ_F64
+ VNMLS_NE_F64
+ VNMLS_CS_F64
+ VNMLS_CC_F64
+ VNMLS_MI_F64
+ VNMLS_PL_F64
+ VNMLS_VS_F64
+ VNMLS_VC_F64
+ VNMLS_HI_F64
+ VNMLS_LS_F64
+ VNMLS_GE_F64
+ VNMLS_LT_F64
+ VNMLS_GT_F64
+ VNMLS_LE_F64
+ VNMLS_F64
+ VNMLS_ZZ_F64
+ VNMLA_EQ_F32
+ VNMLA_NE_F32
+ VNMLA_CS_F32
+ VNMLA_CC_F32
+ VNMLA_MI_F32
+ VNMLA_PL_F32
+ VNMLA_VS_F32
+ VNMLA_VC_F32
+ VNMLA_HI_F32
+ VNMLA_LS_F32
+ VNMLA_GE_F32
+ VNMLA_LT_F32
+ VNMLA_GT_F32
+ VNMLA_LE_F32
+ VNMLA_F32
+ VNMLA_ZZ_F32
+ VNMLA_EQ_F64
+ VNMLA_NE_F64
+ VNMLA_CS_F64
+ VNMLA_CC_F64
+ VNMLA_MI_F64
+ VNMLA_PL_F64
+ VNMLA_VS_F64
+ VNMLA_VC_F64
+ VNMLA_HI_F64
+ VNMLA_LS_F64
+ VNMLA_GE_F64
+ VNMLA_LT_F64
+ VNMLA_GT_F64
+ VNMLA_LE_F64
+ VNMLA_F64
+ VNMLA_ZZ_F64
+ VNMUL_EQ_F32
+ VNMUL_NE_F32
+ VNMUL_CS_F32
+ VNMUL_CC_F32
+ VNMUL_MI_F32
+ VNMUL_PL_F32
+ VNMUL_VS_F32
+ VNMUL_VC_F32
+ VNMUL_HI_F32
+ VNMUL_LS_F32
+ VNMUL_GE_F32
+ VNMUL_LT_F32
+ VNMUL_GT_F32
+ VNMUL_LE_F32
+ VNMUL_F32
+ VNMUL_ZZ_F32
+ VNMUL_EQ_F64
+ VNMUL_NE_F64
+ VNMUL_CS_F64
+ VNMUL_CC_F64
+ VNMUL_MI_F64
+ VNMUL_PL_F64
+ VNMUL_VS_F64
+ VNMUL_VC_F64
+ VNMUL_HI_F64
+ VNMUL_LS_F64
+ VNMUL_GE_F64
+ VNMUL_LT_F64
+ VNMUL_GT_F64
+ VNMUL_LE_F64
+ VNMUL_F64
+ VNMUL_ZZ_F64
+ VSQRT_EQ_F32
+ VSQRT_NE_F32
+ VSQRT_CS_F32
+ VSQRT_CC_F32
+ VSQRT_MI_F32
+ VSQRT_PL_F32
+ VSQRT_VS_F32
+ VSQRT_VC_F32
+ VSQRT_HI_F32
+ VSQRT_LS_F32
+ VSQRT_GE_F32
+ VSQRT_LT_F32
+ VSQRT_GT_F32
+ VSQRT_LE_F32
+ VSQRT_F32
+ VSQRT_ZZ_F32
+ VSQRT_EQ_F64
+ VSQRT_NE_F64
+ VSQRT_CS_F64
+ VSQRT_CC_F64
+ VSQRT_MI_F64
+ VSQRT_PL_F64
+ VSQRT_VS_F64
+ VSQRT_VC_F64
+ VSQRT_HI_F64
+ VSQRT_LS_F64
+ VSQRT_GE_F64
+ VSQRT_LT_F64
+ VSQRT_GT_F64
+ VSQRT_LE_F64
+ VSQRT_F64
+ VSQRT_ZZ_F64
+ VSTR_EQ
+ VSTR_NE
+ VSTR_CS
+ VSTR_CC
+ VSTR_MI
+ VSTR_PL
+ VSTR_VS
+ VSTR_VC
+ VSTR_HI
+ VSTR_LS
+ VSTR_GE
+ VSTR_LT
+ VSTR_GT
+ VSTR_LE
+ VSTR
+ VSTR_ZZ
+ VSUB_EQ_F32
+ VSUB_NE_F32
+ VSUB_CS_F32
+ VSUB_CC_F32
+ VSUB_MI_F32
+ VSUB_PL_F32
+ VSUB_VS_F32
+ VSUB_VC_F32
+ VSUB_HI_F32
+ VSUB_LS_F32
+ VSUB_GE_F32
+ VSUB_LT_F32
+ VSUB_GT_F32
+ VSUB_LE_F32
+ VSUB_F32
+ VSUB_ZZ_F32
+ VSUB_EQ_F64
+ VSUB_NE_F64
+ VSUB_CS_F64
+ VSUB_CC_F64
+ VSUB_MI_F64
+ VSUB_PL_F64
+ VSUB_VS_F64
+ VSUB_VC_F64
+ VSUB_HI_F64
+ VSUB_LS_F64
+ VSUB_GE_F64
+ VSUB_LT_F64
+ VSUB_GT_F64
+ VSUB_LE_F64
+ VSUB_F64
+ VSUB_ZZ_F64
+ WFE_EQ
+ WFE_NE
+ WFE_CS
+ WFE_CC
+ WFE_MI
+ WFE_PL
+ WFE_VS
+ WFE_VC
+ WFE_HI
+ WFE_LS
+ WFE_GE
+ WFE_LT
+ WFE_GT
+ WFE_LE
+ WFE
+ WFE_ZZ
+ WFI_EQ
+ WFI_NE
+ WFI_CS
+ WFI_CC
+ WFI_MI
+ WFI_PL
+ WFI_VS
+ WFI_VC
+ WFI_HI
+ WFI_LS
+ WFI_GE
+ WFI_LT
+ WFI_GT
+ WFI_LE
+ WFI
+ WFI_ZZ
+ YIELD_EQ
+ YIELD_NE
+ YIELD_CS
+ YIELD_CC
+ YIELD_MI
+ YIELD_PL
+ YIELD_VS
+ YIELD_VC
+ YIELD_HI
+ YIELD_LS
+ YIELD_GE
+ YIELD_LT
+ YIELD_GT
+ YIELD_LE
+ YIELD
+ YIELD_ZZ
+)
+
+var opstr = [...]string{
+ ADC_EQ: "ADC.EQ",
+ ADC_NE: "ADC.NE",
+ ADC_CS: "ADC.CS",
+ ADC_CC: "ADC.CC",
+ ADC_MI: "ADC.MI",
+ ADC_PL: "ADC.PL",
+ ADC_VS: "ADC.VS",
+ ADC_VC: "ADC.VC",
+ ADC_HI: "ADC.HI",
+ ADC_LS: "ADC.LS",
+ ADC_GE: "ADC.GE",
+ ADC_LT: "ADC.LT",
+ ADC_GT: "ADC.GT",
+ ADC_LE: "ADC.LE",
+ ADC: "ADC",
+ ADC_ZZ: "ADC.ZZ",
+ ADC_S_EQ: "ADC.S.EQ",
+ ADC_S_NE: "ADC.S.NE",
+ ADC_S_CS: "ADC.S.CS",
+ ADC_S_CC: "ADC.S.CC",
+ ADC_S_MI: "ADC.S.MI",
+ ADC_S_PL: "ADC.S.PL",
+ ADC_S_VS: "ADC.S.VS",
+ ADC_S_VC: "ADC.S.VC",
+ ADC_S_HI: "ADC.S.HI",
+ ADC_S_LS: "ADC.S.LS",
+ ADC_S_GE: "ADC.S.GE",
+ ADC_S_LT: "ADC.S.LT",
+ ADC_S_GT: "ADC.S.GT",
+ ADC_S_LE: "ADC.S.LE",
+ ADC_S: "ADC.S",
+ ADC_S_ZZ: "ADC.S.ZZ",
+ ADD_EQ: "ADD.EQ",
+ ADD_NE: "ADD.NE",
+ ADD_CS: "ADD.CS",
+ ADD_CC: "ADD.CC",
+ ADD_MI: "ADD.MI",
+ ADD_PL: "ADD.PL",
+ ADD_VS: "ADD.VS",
+ ADD_VC: "ADD.VC",
+ ADD_HI: "ADD.HI",
+ ADD_LS: "ADD.LS",
+ ADD_GE: "ADD.GE",
+ ADD_LT: "ADD.LT",
+ ADD_GT: "ADD.GT",
+ ADD_LE: "ADD.LE",
+ ADD: "ADD",
+ ADD_ZZ: "ADD.ZZ",
+ ADD_S_EQ: "ADD.S.EQ",
+ ADD_S_NE: "ADD.S.NE",
+ ADD_S_CS: "ADD.S.CS",
+ ADD_S_CC: "ADD.S.CC",
+ ADD_S_MI: "ADD.S.MI",
+ ADD_S_PL: "ADD.S.PL",
+ ADD_S_VS: "ADD.S.VS",
+ ADD_S_VC: "ADD.S.VC",
+ ADD_S_HI: "ADD.S.HI",
+ ADD_S_LS: "ADD.S.LS",
+ ADD_S_GE: "ADD.S.GE",
+ ADD_S_LT: "ADD.S.LT",
+ ADD_S_GT: "ADD.S.GT",
+ ADD_S_LE: "ADD.S.LE",
+ ADD_S: "ADD.S",
+ ADD_S_ZZ: "ADD.S.ZZ",
+ AND_EQ: "AND.EQ",
+ AND_NE: "AND.NE",
+ AND_CS: "AND.CS",
+ AND_CC: "AND.CC",
+ AND_MI: "AND.MI",
+ AND_PL: "AND.PL",
+ AND_VS: "AND.VS",
+ AND_VC: "AND.VC",
+ AND_HI: "AND.HI",
+ AND_LS: "AND.LS",
+ AND_GE: "AND.GE",
+ AND_LT: "AND.LT",
+ AND_GT: "AND.GT",
+ AND_LE: "AND.LE",
+ AND: "AND",
+ AND_ZZ: "AND.ZZ",
+ AND_S_EQ: "AND.S.EQ",
+ AND_S_NE: "AND.S.NE",
+ AND_S_CS: "AND.S.CS",
+ AND_S_CC: "AND.S.CC",
+ AND_S_MI: "AND.S.MI",
+ AND_S_PL: "AND.S.PL",
+ AND_S_VS: "AND.S.VS",
+ AND_S_VC: "AND.S.VC",
+ AND_S_HI: "AND.S.HI",
+ AND_S_LS: "AND.S.LS",
+ AND_S_GE: "AND.S.GE",
+ AND_S_LT: "AND.S.LT",
+ AND_S_GT: "AND.S.GT",
+ AND_S_LE: "AND.S.LE",
+ AND_S: "AND.S",
+ AND_S_ZZ: "AND.S.ZZ",
+ ASR_EQ: "ASR.EQ",
+ ASR_NE: "ASR.NE",
+ ASR_CS: "ASR.CS",
+ ASR_CC: "ASR.CC",
+ ASR_MI: "ASR.MI",
+ ASR_PL: "ASR.PL",
+ ASR_VS: "ASR.VS",
+ ASR_VC: "ASR.VC",
+ ASR_HI: "ASR.HI",
+ ASR_LS: "ASR.LS",
+ ASR_GE: "ASR.GE",
+ ASR_LT: "ASR.LT",
+ ASR_GT: "ASR.GT",
+ ASR_LE: "ASR.LE",
+ ASR: "ASR",
+ ASR_ZZ: "ASR.ZZ",
+ ASR_S_EQ: "ASR.S.EQ",
+ ASR_S_NE: "ASR.S.NE",
+ ASR_S_CS: "ASR.S.CS",
+ ASR_S_CC: "ASR.S.CC",
+ ASR_S_MI: "ASR.S.MI",
+ ASR_S_PL: "ASR.S.PL",
+ ASR_S_VS: "ASR.S.VS",
+ ASR_S_VC: "ASR.S.VC",
+ ASR_S_HI: "ASR.S.HI",
+ ASR_S_LS: "ASR.S.LS",
+ ASR_S_GE: "ASR.S.GE",
+ ASR_S_LT: "ASR.S.LT",
+ ASR_S_GT: "ASR.S.GT",
+ ASR_S_LE: "ASR.S.LE",
+ ASR_S: "ASR.S",
+ ASR_S_ZZ: "ASR.S.ZZ",
+ B_EQ: "B.EQ",
+ B_NE: "B.NE",
+ B_CS: "B.CS",
+ B_CC: "B.CC",
+ B_MI: "B.MI",
+ B_PL: "B.PL",
+ B_VS: "B.VS",
+ B_VC: "B.VC",
+ B_HI: "B.HI",
+ B_LS: "B.LS",
+ B_GE: "B.GE",
+ B_LT: "B.LT",
+ B_GT: "B.GT",
+ B_LE: "B.LE",
+ B: "B",
+ B_ZZ: "B.ZZ",
+ BFC_EQ: "BFC.EQ",
+ BFC_NE: "BFC.NE",
+ BFC_CS: "BFC.CS",
+ BFC_CC: "BFC.CC",
+ BFC_MI: "BFC.MI",
+ BFC_PL: "BFC.PL",
+ BFC_VS: "BFC.VS",
+ BFC_VC: "BFC.VC",
+ BFC_HI: "BFC.HI",
+ BFC_LS: "BFC.LS",
+ BFC_GE: "BFC.GE",
+ BFC_LT: "BFC.LT",
+ BFC_GT: "BFC.GT",
+ BFC_LE: "BFC.LE",
+ BFC: "BFC",
+ BFC_ZZ: "BFC.ZZ",
+ BFI_EQ: "BFI.EQ",
+ BFI_NE: "BFI.NE",
+ BFI_CS: "BFI.CS",
+ BFI_CC: "BFI.CC",
+ BFI_MI: "BFI.MI",
+ BFI_PL: "BFI.PL",
+ BFI_VS: "BFI.VS",
+ BFI_VC: "BFI.VC",
+ BFI_HI: "BFI.HI",
+ BFI_LS: "BFI.LS",
+ BFI_GE: "BFI.GE",
+ BFI_LT: "BFI.LT",
+ BFI_GT: "BFI.GT",
+ BFI_LE: "BFI.LE",
+ BFI: "BFI",
+ BFI_ZZ: "BFI.ZZ",
+ BIC_EQ: "BIC.EQ",
+ BIC_NE: "BIC.NE",
+ BIC_CS: "BIC.CS",
+ BIC_CC: "BIC.CC",
+ BIC_MI: "BIC.MI",
+ BIC_PL: "BIC.PL",
+ BIC_VS: "BIC.VS",
+ BIC_VC: "BIC.VC",
+ BIC_HI: "BIC.HI",
+ BIC_LS: "BIC.LS",
+ BIC_GE: "BIC.GE",
+ BIC_LT: "BIC.LT",
+ BIC_GT: "BIC.GT",
+ BIC_LE: "BIC.LE",
+ BIC: "BIC",
+ BIC_ZZ: "BIC.ZZ",
+ BIC_S_EQ: "BIC.S.EQ",
+ BIC_S_NE: "BIC.S.NE",
+ BIC_S_CS: "BIC.S.CS",
+ BIC_S_CC: "BIC.S.CC",
+ BIC_S_MI: "BIC.S.MI",
+ BIC_S_PL: "BIC.S.PL",
+ BIC_S_VS: "BIC.S.VS",
+ BIC_S_VC: "BIC.S.VC",
+ BIC_S_HI: "BIC.S.HI",
+ BIC_S_LS: "BIC.S.LS",
+ BIC_S_GE: "BIC.S.GE",
+ BIC_S_LT: "BIC.S.LT",
+ BIC_S_GT: "BIC.S.GT",
+ BIC_S_LE: "BIC.S.LE",
+ BIC_S: "BIC.S",
+ BIC_S_ZZ: "BIC.S.ZZ",
+ BKPT_EQ: "BKPT.EQ",
+ BKPT_NE: "BKPT.NE",
+ BKPT_CS: "BKPT.CS",
+ BKPT_CC: "BKPT.CC",
+ BKPT_MI: "BKPT.MI",
+ BKPT_PL: "BKPT.PL",
+ BKPT_VS: "BKPT.VS",
+ BKPT_VC: "BKPT.VC",
+ BKPT_HI: "BKPT.HI",
+ BKPT_LS: "BKPT.LS",
+ BKPT_GE: "BKPT.GE",
+ BKPT_LT: "BKPT.LT",
+ BKPT_GT: "BKPT.GT",
+ BKPT_LE: "BKPT.LE",
+ BKPT: "BKPT",
+ BKPT_ZZ: "BKPT.ZZ",
+ BL_EQ: "BL.EQ",
+ BL_NE: "BL.NE",
+ BL_CS: "BL.CS",
+ BL_CC: "BL.CC",
+ BL_MI: "BL.MI",
+ BL_PL: "BL.PL",
+ BL_VS: "BL.VS",
+ BL_VC: "BL.VC",
+ BL_HI: "BL.HI",
+ BL_LS: "BL.LS",
+ BL_GE: "BL.GE",
+ BL_LT: "BL.LT",
+ BL_GT: "BL.GT",
+ BL_LE: "BL.LE",
+ BL: "BL",
+ BL_ZZ: "BL.ZZ",
+ BLX_EQ: "BLX.EQ",
+ BLX_NE: "BLX.NE",
+ BLX_CS: "BLX.CS",
+ BLX_CC: "BLX.CC",
+ BLX_MI: "BLX.MI",
+ BLX_PL: "BLX.PL",
+ BLX_VS: "BLX.VS",
+ BLX_VC: "BLX.VC",
+ BLX_HI: "BLX.HI",
+ BLX_LS: "BLX.LS",
+ BLX_GE: "BLX.GE",
+ BLX_LT: "BLX.LT",
+ BLX_GT: "BLX.GT",
+ BLX_LE: "BLX.LE",
+ BLX: "BLX",
+ BLX_ZZ: "BLX.ZZ",
+ BX_EQ: "BX.EQ",
+ BX_NE: "BX.NE",
+ BX_CS: "BX.CS",
+ BX_CC: "BX.CC",
+ BX_MI: "BX.MI",
+ BX_PL: "BX.PL",
+ BX_VS: "BX.VS",
+ BX_VC: "BX.VC",
+ BX_HI: "BX.HI",
+ BX_LS: "BX.LS",
+ BX_GE: "BX.GE",
+ BX_LT: "BX.LT",
+ BX_GT: "BX.GT",
+ BX_LE: "BX.LE",
+ BX: "BX",
+ BX_ZZ: "BX.ZZ",
+ BXJ_EQ: "BXJ.EQ",
+ BXJ_NE: "BXJ.NE",
+ BXJ_CS: "BXJ.CS",
+ BXJ_CC: "BXJ.CC",
+ BXJ_MI: "BXJ.MI",
+ BXJ_PL: "BXJ.PL",
+ BXJ_VS: "BXJ.VS",
+ BXJ_VC: "BXJ.VC",
+ BXJ_HI: "BXJ.HI",
+ BXJ_LS: "BXJ.LS",
+ BXJ_GE: "BXJ.GE",
+ BXJ_LT: "BXJ.LT",
+ BXJ_GT: "BXJ.GT",
+ BXJ_LE: "BXJ.LE",
+ BXJ: "BXJ",
+ BXJ_ZZ: "BXJ.ZZ",
+ CLREX: "CLREX",
+ CLZ_EQ: "CLZ.EQ",
+ CLZ_NE: "CLZ.NE",
+ CLZ_CS: "CLZ.CS",
+ CLZ_CC: "CLZ.CC",
+ CLZ_MI: "CLZ.MI",
+ CLZ_PL: "CLZ.PL",
+ CLZ_VS: "CLZ.VS",
+ CLZ_VC: "CLZ.VC",
+ CLZ_HI: "CLZ.HI",
+ CLZ_LS: "CLZ.LS",
+ CLZ_GE: "CLZ.GE",
+ CLZ_LT: "CLZ.LT",
+ CLZ_GT: "CLZ.GT",
+ CLZ_LE: "CLZ.LE",
+ CLZ: "CLZ",
+ CLZ_ZZ: "CLZ.ZZ",
+ CMN_EQ: "CMN.EQ",
+ CMN_NE: "CMN.NE",
+ CMN_CS: "CMN.CS",
+ CMN_CC: "CMN.CC",
+ CMN_MI: "CMN.MI",
+ CMN_PL: "CMN.PL",
+ CMN_VS: "CMN.VS",
+ CMN_VC: "CMN.VC",
+ CMN_HI: "CMN.HI",
+ CMN_LS: "CMN.LS",
+ CMN_GE: "CMN.GE",
+ CMN_LT: "CMN.LT",
+ CMN_GT: "CMN.GT",
+ CMN_LE: "CMN.LE",
+ CMN: "CMN",
+ CMN_ZZ: "CMN.ZZ",
+ CMP_EQ: "CMP.EQ",
+ CMP_NE: "CMP.NE",
+ CMP_CS: "CMP.CS",
+ CMP_CC: "CMP.CC",
+ CMP_MI: "CMP.MI",
+ CMP_PL: "CMP.PL",
+ CMP_VS: "CMP.VS",
+ CMP_VC: "CMP.VC",
+ CMP_HI: "CMP.HI",
+ CMP_LS: "CMP.LS",
+ CMP_GE: "CMP.GE",
+ CMP_LT: "CMP.LT",
+ CMP_GT: "CMP.GT",
+ CMP_LE: "CMP.LE",
+ CMP: "CMP",
+ CMP_ZZ: "CMP.ZZ",
+ DBG_EQ: "DBG.EQ",
+ DBG_NE: "DBG.NE",
+ DBG_CS: "DBG.CS",
+ DBG_CC: "DBG.CC",
+ DBG_MI: "DBG.MI",
+ DBG_PL: "DBG.PL",
+ DBG_VS: "DBG.VS",
+ DBG_VC: "DBG.VC",
+ DBG_HI: "DBG.HI",
+ DBG_LS: "DBG.LS",
+ DBG_GE: "DBG.GE",
+ DBG_LT: "DBG.LT",
+ DBG_GT: "DBG.GT",
+ DBG_LE: "DBG.LE",
+ DBG: "DBG",
+ DBG_ZZ: "DBG.ZZ",
+ DMB: "DMB",
+ DSB: "DSB",
+ EOR_EQ: "EOR.EQ",
+ EOR_NE: "EOR.NE",
+ EOR_CS: "EOR.CS",
+ EOR_CC: "EOR.CC",
+ EOR_MI: "EOR.MI",
+ EOR_PL: "EOR.PL",
+ EOR_VS: "EOR.VS",
+ EOR_VC: "EOR.VC",
+ EOR_HI: "EOR.HI",
+ EOR_LS: "EOR.LS",
+ EOR_GE: "EOR.GE",
+ EOR_LT: "EOR.LT",
+ EOR_GT: "EOR.GT",
+ EOR_LE: "EOR.LE",
+ EOR: "EOR",
+ EOR_ZZ: "EOR.ZZ",
+ EOR_S_EQ: "EOR.S.EQ",
+ EOR_S_NE: "EOR.S.NE",
+ EOR_S_CS: "EOR.S.CS",
+ EOR_S_CC: "EOR.S.CC",
+ EOR_S_MI: "EOR.S.MI",
+ EOR_S_PL: "EOR.S.PL",
+ EOR_S_VS: "EOR.S.VS",
+ EOR_S_VC: "EOR.S.VC",
+ EOR_S_HI: "EOR.S.HI",
+ EOR_S_LS: "EOR.S.LS",
+ EOR_S_GE: "EOR.S.GE",
+ EOR_S_LT: "EOR.S.LT",
+ EOR_S_GT: "EOR.S.GT",
+ EOR_S_LE: "EOR.S.LE",
+ EOR_S: "EOR.S",
+ EOR_S_ZZ: "EOR.S.ZZ",
+ ISB: "ISB",
+ LDM_EQ: "LDM.EQ",
+ LDM_NE: "LDM.NE",
+ LDM_CS: "LDM.CS",
+ LDM_CC: "LDM.CC",
+ LDM_MI: "LDM.MI",
+ LDM_PL: "LDM.PL",
+ LDM_VS: "LDM.VS",
+ LDM_VC: "LDM.VC",
+ LDM_HI: "LDM.HI",
+ LDM_LS: "LDM.LS",
+ LDM_GE: "LDM.GE",
+ LDM_LT: "LDM.LT",
+ LDM_GT: "LDM.GT",
+ LDM_LE: "LDM.LE",
+ LDM: "LDM",
+ LDM_ZZ: "LDM.ZZ",
+ LDMDA_EQ: "LDMDA.EQ",
+ LDMDA_NE: "LDMDA.NE",
+ LDMDA_CS: "LDMDA.CS",
+ LDMDA_CC: "LDMDA.CC",
+ LDMDA_MI: "LDMDA.MI",
+ LDMDA_PL: "LDMDA.PL",
+ LDMDA_VS: "LDMDA.VS",
+ LDMDA_VC: "LDMDA.VC",
+ LDMDA_HI: "LDMDA.HI",
+ LDMDA_LS: "LDMDA.LS",
+ LDMDA_GE: "LDMDA.GE",
+ LDMDA_LT: "LDMDA.LT",
+ LDMDA_GT: "LDMDA.GT",
+ LDMDA_LE: "LDMDA.LE",
+ LDMDA: "LDMDA",
+ LDMDA_ZZ: "LDMDA.ZZ",
+ LDMDB_EQ: "LDMDB.EQ",
+ LDMDB_NE: "LDMDB.NE",
+ LDMDB_CS: "LDMDB.CS",
+ LDMDB_CC: "LDMDB.CC",
+ LDMDB_MI: "LDMDB.MI",
+ LDMDB_PL: "LDMDB.PL",
+ LDMDB_VS: "LDMDB.VS",
+ LDMDB_VC: "LDMDB.VC",
+ LDMDB_HI: "LDMDB.HI",
+ LDMDB_LS: "LDMDB.LS",
+ LDMDB_GE: "LDMDB.GE",
+ LDMDB_LT: "LDMDB.LT",
+ LDMDB_GT: "LDMDB.GT",
+ LDMDB_LE: "LDMDB.LE",
+ LDMDB: "LDMDB",
+ LDMDB_ZZ: "LDMDB.ZZ",
+ LDMIB_EQ: "LDMIB.EQ",
+ LDMIB_NE: "LDMIB.NE",
+ LDMIB_CS: "LDMIB.CS",
+ LDMIB_CC: "LDMIB.CC",
+ LDMIB_MI: "LDMIB.MI",
+ LDMIB_PL: "LDMIB.PL",
+ LDMIB_VS: "LDMIB.VS",
+ LDMIB_VC: "LDMIB.VC",
+ LDMIB_HI: "LDMIB.HI",
+ LDMIB_LS: "LDMIB.LS",
+ LDMIB_GE: "LDMIB.GE",
+ LDMIB_LT: "LDMIB.LT",
+ LDMIB_GT: "LDMIB.GT",
+ LDMIB_LE: "LDMIB.LE",
+ LDMIB: "LDMIB",
+ LDMIB_ZZ: "LDMIB.ZZ",
+ LDR_EQ: "LDR.EQ",
+ LDR_NE: "LDR.NE",
+ LDR_CS: "LDR.CS",
+ LDR_CC: "LDR.CC",
+ LDR_MI: "LDR.MI",
+ LDR_PL: "LDR.PL",
+ LDR_VS: "LDR.VS",
+ LDR_VC: "LDR.VC",
+ LDR_HI: "LDR.HI",
+ LDR_LS: "LDR.LS",
+ LDR_GE: "LDR.GE",
+ LDR_LT: "LDR.LT",
+ LDR_GT: "LDR.GT",
+ LDR_LE: "LDR.LE",
+ LDR: "LDR",
+ LDR_ZZ: "LDR.ZZ",
+ LDRB_EQ: "LDRB.EQ",
+ LDRB_NE: "LDRB.NE",
+ LDRB_CS: "LDRB.CS",
+ LDRB_CC: "LDRB.CC",
+ LDRB_MI: "LDRB.MI",
+ LDRB_PL: "LDRB.PL",
+ LDRB_VS: "LDRB.VS",
+ LDRB_VC: "LDRB.VC",
+ LDRB_HI: "LDRB.HI",
+ LDRB_LS: "LDRB.LS",
+ LDRB_GE: "LDRB.GE",
+ LDRB_LT: "LDRB.LT",
+ LDRB_GT: "LDRB.GT",
+ LDRB_LE: "LDRB.LE",
+ LDRB: "LDRB",
+ LDRB_ZZ: "LDRB.ZZ",
+ LDRBT_EQ: "LDRBT.EQ",
+ LDRBT_NE: "LDRBT.NE",
+ LDRBT_CS: "LDRBT.CS",
+ LDRBT_CC: "LDRBT.CC",
+ LDRBT_MI: "LDRBT.MI",
+ LDRBT_PL: "LDRBT.PL",
+ LDRBT_VS: "LDRBT.VS",
+ LDRBT_VC: "LDRBT.VC",
+ LDRBT_HI: "LDRBT.HI",
+ LDRBT_LS: "LDRBT.LS",
+ LDRBT_GE: "LDRBT.GE",
+ LDRBT_LT: "LDRBT.LT",
+ LDRBT_GT: "LDRBT.GT",
+ LDRBT_LE: "LDRBT.LE",
+ LDRBT: "LDRBT",
+ LDRBT_ZZ: "LDRBT.ZZ",
+ LDRD_EQ: "LDRD.EQ",
+ LDRD_NE: "LDRD.NE",
+ LDRD_CS: "LDRD.CS",
+ LDRD_CC: "LDRD.CC",
+ LDRD_MI: "LDRD.MI",
+ LDRD_PL: "LDRD.PL",
+ LDRD_VS: "LDRD.VS",
+ LDRD_VC: "LDRD.VC",
+ LDRD_HI: "LDRD.HI",
+ LDRD_LS: "LDRD.LS",
+ LDRD_GE: "LDRD.GE",
+ LDRD_LT: "LDRD.LT",
+ LDRD_GT: "LDRD.GT",
+ LDRD_LE: "LDRD.LE",
+ LDRD: "LDRD",
+ LDRD_ZZ: "LDRD.ZZ",
+ LDREX_EQ: "LDREX.EQ",
+ LDREX_NE: "LDREX.NE",
+ LDREX_CS: "LDREX.CS",
+ LDREX_CC: "LDREX.CC",
+ LDREX_MI: "LDREX.MI",
+ LDREX_PL: "LDREX.PL",
+ LDREX_VS: "LDREX.VS",
+ LDREX_VC: "LDREX.VC",
+ LDREX_HI: "LDREX.HI",
+ LDREX_LS: "LDREX.LS",
+ LDREX_GE: "LDREX.GE",
+ LDREX_LT: "LDREX.LT",
+ LDREX_GT: "LDREX.GT",
+ LDREX_LE: "LDREX.LE",
+ LDREX: "LDREX",
+ LDREX_ZZ: "LDREX.ZZ",
+ LDREXB_EQ: "LDREXB.EQ",
+ LDREXB_NE: "LDREXB.NE",
+ LDREXB_CS: "LDREXB.CS",
+ LDREXB_CC: "LDREXB.CC",
+ LDREXB_MI: "LDREXB.MI",
+ LDREXB_PL: "LDREXB.PL",
+ LDREXB_VS: "LDREXB.VS",
+ LDREXB_VC: "LDREXB.VC",
+ LDREXB_HI: "LDREXB.HI",
+ LDREXB_LS: "LDREXB.LS",
+ LDREXB_GE: "LDREXB.GE",
+ LDREXB_LT: "LDREXB.LT",
+ LDREXB_GT: "LDREXB.GT",
+ LDREXB_LE: "LDREXB.LE",
+ LDREXB: "LDREXB",
+ LDREXB_ZZ: "LDREXB.ZZ",
+ LDREXD_EQ: "LDREXD.EQ",
+ LDREXD_NE: "LDREXD.NE",
+ LDREXD_CS: "LDREXD.CS",
+ LDREXD_CC: "LDREXD.CC",
+ LDREXD_MI: "LDREXD.MI",
+ LDREXD_PL: "LDREXD.PL",
+ LDREXD_VS: "LDREXD.VS",
+ LDREXD_VC: "LDREXD.VC",
+ LDREXD_HI: "LDREXD.HI",
+ LDREXD_LS: "LDREXD.LS",
+ LDREXD_GE: "LDREXD.GE",
+ LDREXD_LT: "LDREXD.LT",
+ LDREXD_GT: "LDREXD.GT",
+ LDREXD_LE: "LDREXD.LE",
+ LDREXD: "LDREXD",
+ LDREXD_ZZ: "LDREXD.ZZ",
+ LDREXH_EQ: "LDREXH.EQ",
+ LDREXH_NE: "LDREXH.NE",
+ LDREXH_CS: "LDREXH.CS",
+ LDREXH_CC: "LDREXH.CC",
+ LDREXH_MI: "LDREXH.MI",
+ LDREXH_PL: "LDREXH.PL",
+ LDREXH_VS: "LDREXH.VS",
+ LDREXH_VC: "LDREXH.VC",
+ LDREXH_HI: "LDREXH.HI",
+ LDREXH_LS: "LDREXH.LS",
+ LDREXH_GE: "LDREXH.GE",
+ LDREXH_LT: "LDREXH.LT",
+ LDREXH_GT: "LDREXH.GT",
+ LDREXH_LE: "LDREXH.LE",
+ LDREXH: "LDREXH",
+ LDREXH_ZZ: "LDREXH.ZZ",
+ LDRH_EQ: "LDRH.EQ",
+ LDRH_NE: "LDRH.NE",
+ LDRH_CS: "LDRH.CS",
+ LDRH_CC: "LDRH.CC",
+ LDRH_MI: "LDRH.MI",
+ LDRH_PL: "LDRH.PL",
+ LDRH_VS: "LDRH.VS",
+ LDRH_VC: "LDRH.VC",
+ LDRH_HI: "LDRH.HI",
+ LDRH_LS: "LDRH.LS",
+ LDRH_GE: "LDRH.GE",
+ LDRH_LT: "LDRH.LT",
+ LDRH_GT: "LDRH.GT",
+ LDRH_LE: "LDRH.LE",
+ LDRH: "LDRH",
+ LDRH_ZZ: "LDRH.ZZ",
+ LDRHT_EQ: "LDRHT.EQ",
+ LDRHT_NE: "LDRHT.NE",
+ LDRHT_CS: "LDRHT.CS",
+ LDRHT_CC: "LDRHT.CC",
+ LDRHT_MI: "LDRHT.MI",
+ LDRHT_PL: "LDRHT.PL",
+ LDRHT_VS: "LDRHT.VS",
+ LDRHT_VC: "LDRHT.VC",
+ LDRHT_HI: "LDRHT.HI",
+ LDRHT_LS: "LDRHT.LS",
+ LDRHT_GE: "LDRHT.GE",
+ LDRHT_LT: "LDRHT.LT",
+ LDRHT_GT: "LDRHT.GT",
+ LDRHT_LE: "LDRHT.LE",
+ LDRHT: "LDRHT",
+ LDRHT_ZZ: "LDRHT.ZZ",
+ LDRSB_EQ: "LDRSB.EQ",
+ LDRSB_NE: "LDRSB.NE",
+ LDRSB_CS: "LDRSB.CS",
+ LDRSB_CC: "LDRSB.CC",
+ LDRSB_MI: "LDRSB.MI",
+ LDRSB_PL: "LDRSB.PL",
+ LDRSB_VS: "LDRSB.VS",
+ LDRSB_VC: "LDRSB.VC",
+ LDRSB_HI: "LDRSB.HI",
+ LDRSB_LS: "LDRSB.LS",
+ LDRSB_GE: "LDRSB.GE",
+ LDRSB_LT: "LDRSB.LT",
+ LDRSB_GT: "LDRSB.GT",
+ LDRSB_LE: "LDRSB.LE",
+ LDRSB: "LDRSB",
+ LDRSB_ZZ: "LDRSB.ZZ",
+ LDRSBT_EQ: "LDRSBT.EQ",
+ LDRSBT_NE: "LDRSBT.NE",
+ LDRSBT_CS: "LDRSBT.CS",
+ LDRSBT_CC: "LDRSBT.CC",
+ LDRSBT_MI: "LDRSBT.MI",
+ LDRSBT_PL: "LDRSBT.PL",
+ LDRSBT_VS: "LDRSBT.VS",
+ LDRSBT_VC: "LDRSBT.VC",
+ LDRSBT_HI: "LDRSBT.HI",
+ LDRSBT_LS: "LDRSBT.LS",
+ LDRSBT_GE: "LDRSBT.GE",
+ LDRSBT_LT: "LDRSBT.LT",
+ LDRSBT_GT: "LDRSBT.GT",
+ LDRSBT_LE: "LDRSBT.LE",
+ LDRSBT: "LDRSBT",
+ LDRSBT_ZZ: "LDRSBT.ZZ",
+ LDRSH_EQ: "LDRSH.EQ",
+ LDRSH_NE: "LDRSH.NE",
+ LDRSH_CS: "LDRSH.CS",
+ LDRSH_CC: "LDRSH.CC",
+ LDRSH_MI: "LDRSH.MI",
+ LDRSH_PL: "LDRSH.PL",
+ LDRSH_VS: "LDRSH.VS",
+ LDRSH_VC: "LDRSH.VC",
+ LDRSH_HI: "LDRSH.HI",
+ LDRSH_LS: "LDRSH.LS",
+ LDRSH_GE: "LDRSH.GE",
+ LDRSH_LT: "LDRSH.LT",
+ LDRSH_GT: "LDRSH.GT",
+ LDRSH_LE: "LDRSH.LE",
+ LDRSH: "LDRSH",
+ LDRSH_ZZ: "LDRSH.ZZ",
+ LDRSHT_EQ: "LDRSHT.EQ",
+ LDRSHT_NE: "LDRSHT.NE",
+ LDRSHT_CS: "LDRSHT.CS",
+ LDRSHT_CC: "LDRSHT.CC",
+ LDRSHT_MI: "LDRSHT.MI",
+ LDRSHT_PL: "LDRSHT.PL",
+ LDRSHT_VS: "LDRSHT.VS",
+ LDRSHT_VC: "LDRSHT.VC",
+ LDRSHT_HI: "LDRSHT.HI",
+ LDRSHT_LS: "LDRSHT.LS",
+ LDRSHT_GE: "LDRSHT.GE",
+ LDRSHT_LT: "LDRSHT.LT",
+ LDRSHT_GT: "LDRSHT.GT",
+ LDRSHT_LE: "LDRSHT.LE",
+ LDRSHT: "LDRSHT",
+ LDRSHT_ZZ: "LDRSHT.ZZ",
+ LDRT_EQ: "LDRT.EQ",
+ LDRT_NE: "LDRT.NE",
+ LDRT_CS: "LDRT.CS",
+ LDRT_CC: "LDRT.CC",
+ LDRT_MI: "LDRT.MI",
+ LDRT_PL: "LDRT.PL",
+ LDRT_VS: "LDRT.VS",
+ LDRT_VC: "LDRT.VC",
+ LDRT_HI: "LDRT.HI",
+ LDRT_LS: "LDRT.LS",
+ LDRT_GE: "LDRT.GE",
+ LDRT_LT: "LDRT.LT",
+ LDRT_GT: "LDRT.GT",
+ LDRT_LE: "LDRT.LE",
+ LDRT: "LDRT",
+ LDRT_ZZ: "LDRT.ZZ",
+ LSL_EQ: "LSL.EQ",
+ LSL_NE: "LSL.NE",
+ LSL_CS: "LSL.CS",
+ LSL_CC: "LSL.CC",
+ LSL_MI: "LSL.MI",
+ LSL_PL: "LSL.PL",
+ LSL_VS: "LSL.VS",
+ LSL_VC: "LSL.VC",
+ LSL_HI: "LSL.HI",
+ LSL_LS: "LSL.LS",
+ LSL_GE: "LSL.GE",
+ LSL_LT: "LSL.LT",
+ LSL_GT: "LSL.GT",
+ LSL_LE: "LSL.LE",
+ LSL: "LSL",
+ LSL_ZZ: "LSL.ZZ",
+ LSL_S_EQ: "LSL.S.EQ",
+ LSL_S_NE: "LSL.S.NE",
+ LSL_S_CS: "LSL.S.CS",
+ LSL_S_CC: "LSL.S.CC",
+ LSL_S_MI: "LSL.S.MI",
+ LSL_S_PL: "LSL.S.PL",
+ LSL_S_VS: "LSL.S.VS",
+ LSL_S_VC: "LSL.S.VC",
+ LSL_S_HI: "LSL.S.HI",
+ LSL_S_LS: "LSL.S.LS",
+ LSL_S_GE: "LSL.S.GE",
+ LSL_S_LT: "LSL.S.LT",
+ LSL_S_GT: "LSL.S.GT",
+ LSL_S_LE: "LSL.S.LE",
+ LSL_S: "LSL.S",
+ LSL_S_ZZ: "LSL.S.ZZ",
+ LSR_EQ: "LSR.EQ",
+ LSR_NE: "LSR.NE",
+ LSR_CS: "LSR.CS",
+ LSR_CC: "LSR.CC",
+ LSR_MI: "LSR.MI",
+ LSR_PL: "LSR.PL",
+ LSR_VS: "LSR.VS",
+ LSR_VC: "LSR.VC",
+ LSR_HI: "LSR.HI",
+ LSR_LS: "LSR.LS",
+ LSR_GE: "LSR.GE",
+ LSR_LT: "LSR.LT",
+ LSR_GT: "LSR.GT",
+ LSR_LE: "LSR.LE",
+ LSR: "LSR",
+ LSR_ZZ: "LSR.ZZ",
+ LSR_S_EQ: "LSR.S.EQ",
+ LSR_S_NE: "LSR.S.NE",
+ LSR_S_CS: "LSR.S.CS",
+ LSR_S_CC: "LSR.S.CC",
+ LSR_S_MI: "LSR.S.MI",
+ LSR_S_PL: "LSR.S.PL",
+ LSR_S_VS: "LSR.S.VS",
+ LSR_S_VC: "LSR.S.VC",
+ LSR_S_HI: "LSR.S.HI",
+ LSR_S_LS: "LSR.S.LS",
+ LSR_S_GE: "LSR.S.GE",
+ LSR_S_LT: "LSR.S.LT",
+ LSR_S_GT: "LSR.S.GT",
+ LSR_S_LE: "LSR.S.LE",
+ LSR_S: "LSR.S",
+ LSR_S_ZZ: "LSR.S.ZZ",
+ MLA_EQ: "MLA.EQ",
+ MLA_NE: "MLA.NE",
+ MLA_CS: "MLA.CS",
+ MLA_CC: "MLA.CC",
+ MLA_MI: "MLA.MI",
+ MLA_PL: "MLA.PL",
+ MLA_VS: "MLA.VS",
+ MLA_VC: "MLA.VC",
+ MLA_HI: "MLA.HI",
+ MLA_LS: "MLA.LS",
+ MLA_GE: "MLA.GE",
+ MLA_LT: "MLA.LT",
+ MLA_GT: "MLA.GT",
+ MLA_LE: "MLA.LE",
+ MLA: "MLA",
+ MLA_ZZ: "MLA.ZZ",
+ MLA_S_EQ: "MLA.S.EQ",
+ MLA_S_NE: "MLA.S.NE",
+ MLA_S_CS: "MLA.S.CS",
+ MLA_S_CC: "MLA.S.CC",
+ MLA_S_MI: "MLA.S.MI",
+ MLA_S_PL: "MLA.S.PL",
+ MLA_S_VS: "MLA.S.VS",
+ MLA_S_VC: "MLA.S.VC",
+ MLA_S_HI: "MLA.S.HI",
+ MLA_S_LS: "MLA.S.LS",
+ MLA_S_GE: "MLA.S.GE",
+ MLA_S_LT: "MLA.S.LT",
+ MLA_S_GT: "MLA.S.GT",
+ MLA_S_LE: "MLA.S.LE",
+ MLA_S: "MLA.S",
+ MLA_S_ZZ: "MLA.S.ZZ",
+ MLS_EQ: "MLS.EQ",
+ MLS_NE: "MLS.NE",
+ MLS_CS: "MLS.CS",
+ MLS_CC: "MLS.CC",
+ MLS_MI: "MLS.MI",
+ MLS_PL: "MLS.PL",
+ MLS_VS: "MLS.VS",
+ MLS_VC: "MLS.VC",
+ MLS_HI: "MLS.HI",
+ MLS_LS: "MLS.LS",
+ MLS_GE: "MLS.GE",
+ MLS_LT: "MLS.LT",
+ MLS_GT: "MLS.GT",
+ MLS_LE: "MLS.LE",
+ MLS: "MLS",
+ MLS_ZZ: "MLS.ZZ",
+ MOV_EQ: "MOV.EQ",
+ MOV_NE: "MOV.NE",
+ MOV_CS: "MOV.CS",
+ MOV_CC: "MOV.CC",
+ MOV_MI: "MOV.MI",
+ MOV_PL: "MOV.PL",
+ MOV_VS: "MOV.VS",
+ MOV_VC: "MOV.VC",
+ MOV_HI: "MOV.HI",
+ MOV_LS: "MOV.LS",
+ MOV_GE: "MOV.GE",
+ MOV_LT: "MOV.LT",
+ MOV_GT: "MOV.GT",
+ MOV_LE: "MOV.LE",
+ MOV: "MOV",
+ MOV_ZZ: "MOV.ZZ",
+ MOV_S_EQ: "MOV.S.EQ",
+ MOV_S_NE: "MOV.S.NE",
+ MOV_S_CS: "MOV.S.CS",
+ MOV_S_CC: "MOV.S.CC",
+ MOV_S_MI: "MOV.S.MI",
+ MOV_S_PL: "MOV.S.PL",
+ MOV_S_VS: "MOV.S.VS",
+ MOV_S_VC: "MOV.S.VC",
+ MOV_S_HI: "MOV.S.HI",
+ MOV_S_LS: "MOV.S.LS",
+ MOV_S_GE: "MOV.S.GE",
+ MOV_S_LT: "MOV.S.LT",
+ MOV_S_GT: "MOV.S.GT",
+ MOV_S_LE: "MOV.S.LE",
+ MOV_S: "MOV.S",
+ MOV_S_ZZ: "MOV.S.ZZ",
+ MOVT_EQ: "MOVT.EQ",
+ MOVT_NE: "MOVT.NE",
+ MOVT_CS: "MOVT.CS",
+ MOVT_CC: "MOVT.CC",
+ MOVT_MI: "MOVT.MI",
+ MOVT_PL: "MOVT.PL",
+ MOVT_VS: "MOVT.VS",
+ MOVT_VC: "MOVT.VC",
+ MOVT_HI: "MOVT.HI",
+ MOVT_LS: "MOVT.LS",
+ MOVT_GE: "MOVT.GE",
+ MOVT_LT: "MOVT.LT",
+ MOVT_GT: "MOVT.GT",
+ MOVT_LE: "MOVT.LE",
+ MOVT: "MOVT",
+ MOVT_ZZ: "MOVT.ZZ",
+ MOVW_EQ: "MOVW.EQ",
+ MOVW_NE: "MOVW.NE",
+ MOVW_CS: "MOVW.CS",
+ MOVW_CC: "MOVW.CC",
+ MOVW_MI: "MOVW.MI",
+ MOVW_PL: "MOVW.PL",
+ MOVW_VS: "MOVW.VS",
+ MOVW_VC: "MOVW.VC",
+ MOVW_HI: "MOVW.HI",
+ MOVW_LS: "MOVW.LS",
+ MOVW_GE: "MOVW.GE",
+ MOVW_LT: "MOVW.LT",
+ MOVW_GT: "MOVW.GT",
+ MOVW_LE: "MOVW.LE",
+ MOVW: "MOVW",
+ MOVW_ZZ: "MOVW.ZZ",
+ MRS_EQ: "MRS.EQ",
+ MRS_NE: "MRS.NE",
+ MRS_CS: "MRS.CS",
+ MRS_CC: "MRS.CC",
+ MRS_MI: "MRS.MI",
+ MRS_PL: "MRS.PL",
+ MRS_VS: "MRS.VS",
+ MRS_VC: "MRS.VC",
+ MRS_HI: "MRS.HI",
+ MRS_LS: "MRS.LS",
+ MRS_GE: "MRS.GE",
+ MRS_LT: "MRS.LT",
+ MRS_GT: "MRS.GT",
+ MRS_LE: "MRS.LE",
+ MRS: "MRS",
+ MRS_ZZ: "MRS.ZZ",
+ MUL_EQ: "MUL.EQ",
+ MUL_NE: "MUL.NE",
+ MUL_CS: "MUL.CS",
+ MUL_CC: "MUL.CC",
+ MUL_MI: "MUL.MI",
+ MUL_PL: "MUL.PL",
+ MUL_VS: "MUL.VS",
+ MUL_VC: "MUL.VC",
+ MUL_HI: "MUL.HI",
+ MUL_LS: "MUL.LS",
+ MUL_GE: "MUL.GE",
+ MUL_LT: "MUL.LT",
+ MUL_GT: "MUL.GT",
+ MUL_LE: "MUL.LE",
+ MUL: "MUL",
+ MUL_ZZ: "MUL.ZZ",
+ MUL_S_EQ: "MUL.S.EQ",
+ MUL_S_NE: "MUL.S.NE",
+ MUL_S_CS: "MUL.S.CS",
+ MUL_S_CC: "MUL.S.CC",
+ MUL_S_MI: "MUL.S.MI",
+ MUL_S_PL: "MUL.S.PL",
+ MUL_S_VS: "MUL.S.VS",
+ MUL_S_VC: "MUL.S.VC",
+ MUL_S_HI: "MUL.S.HI",
+ MUL_S_LS: "MUL.S.LS",
+ MUL_S_GE: "MUL.S.GE",
+ MUL_S_LT: "MUL.S.LT",
+ MUL_S_GT: "MUL.S.GT",
+ MUL_S_LE: "MUL.S.LE",
+ MUL_S: "MUL.S",
+ MUL_S_ZZ: "MUL.S.ZZ",
+ MVN_EQ: "MVN.EQ",
+ MVN_NE: "MVN.NE",
+ MVN_CS: "MVN.CS",
+ MVN_CC: "MVN.CC",
+ MVN_MI: "MVN.MI",
+ MVN_PL: "MVN.PL",
+ MVN_VS: "MVN.VS",
+ MVN_VC: "MVN.VC",
+ MVN_HI: "MVN.HI",
+ MVN_LS: "MVN.LS",
+ MVN_GE: "MVN.GE",
+ MVN_LT: "MVN.LT",
+ MVN_GT: "MVN.GT",
+ MVN_LE: "MVN.LE",
+ MVN: "MVN",
+ MVN_ZZ: "MVN.ZZ",
+ MVN_S_EQ: "MVN.S.EQ",
+ MVN_S_NE: "MVN.S.NE",
+ MVN_S_CS: "MVN.S.CS",
+ MVN_S_CC: "MVN.S.CC",
+ MVN_S_MI: "MVN.S.MI",
+ MVN_S_PL: "MVN.S.PL",
+ MVN_S_VS: "MVN.S.VS",
+ MVN_S_VC: "MVN.S.VC",
+ MVN_S_HI: "MVN.S.HI",
+ MVN_S_LS: "MVN.S.LS",
+ MVN_S_GE: "MVN.S.GE",
+ MVN_S_LT: "MVN.S.LT",
+ MVN_S_GT: "MVN.S.GT",
+ MVN_S_LE: "MVN.S.LE",
+ MVN_S: "MVN.S",
+ MVN_S_ZZ: "MVN.S.ZZ",
+ NOP_EQ: "NOP.EQ",
+ NOP_NE: "NOP.NE",
+ NOP_CS: "NOP.CS",
+ NOP_CC: "NOP.CC",
+ NOP_MI: "NOP.MI",
+ NOP_PL: "NOP.PL",
+ NOP_VS: "NOP.VS",
+ NOP_VC: "NOP.VC",
+ NOP_HI: "NOP.HI",
+ NOP_LS: "NOP.LS",
+ NOP_GE: "NOP.GE",
+ NOP_LT: "NOP.LT",
+ NOP_GT: "NOP.GT",
+ NOP_LE: "NOP.LE",
+ NOP: "NOP",
+ NOP_ZZ: "NOP.ZZ",
+ ORR_EQ: "ORR.EQ",
+ ORR_NE: "ORR.NE",
+ ORR_CS: "ORR.CS",
+ ORR_CC: "ORR.CC",
+ ORR_MI: "ORR.MI",
+ ORR_PL: "ORR.PL",
+ ORR_VS: "ORR.VS",
+ ORR_VC: "ORR.VC",
+ ORR_HI: "ORR.HI",
+ ORR_LS: "ORR.LS",
+ ORR_GE: "ORR.GE",
+ ORR_LT: "ORR.LT",
+ ORR_GT: "ORR.GT",
+ ORR_LE: "ORR.LE",
+ ORR: "ORR",
+ ORR_ZZ: "ORR.ZZ",
+ ORR_S_EQ: "ORR.S.EQ",
+ ORR_S_NE: "ORR.S.NE",
+ ORR_S_CS: "ORR.S.CS",
+ ORR_S_CC: "ORR.S.CC",
+ ORR_S_MI: "ORR.S.MI",
+ ORR_S_PL: "ORR.S.PL",
+ ORR_S_VS: "ORR.S.VS",
+ ORR_S_VC: "ORR.S.VC",
+ ORR_S_HI: "ORR.S.HI",
+ ORR_S_LS: "ORR.S.LS",
+ ORR_S_GE: "ORR.S.GE",
+ ORR_S_LT: "ORR.S.LT",
+ ORR_S_GT: "ORR.S.GT",
+ ORR_S_LE: "ORR.S.LE",
+ ORR_S: "ORR.S",
+ ORR_S_ZZ: "ORR.S.ZZ",
+ PKHBT_EQ: "PKHBT.EQ",
+ PKHBT_NE: "PKHBT.NE",
+ PKHBT_CS: "PKHBT.CS",
+ PKHBT_CC: "PKHBT.CC",
+ PKHBT_MI: "PKHBT.MI",
+ PKHBT_PL: "PKHBT.PL",
+ PKHBT_VS: "PKHBT.VS",
+ PKHBT_VC: "PKHBT.VC",
+ PKHBT_HI: "PKHBT.HI",
+ PKHBT_LS: "PKHBT.LS",
+ PKHBT_GE: "PKHBT.GE",
+ PKHBT_LT: "PKHBT.LT",
+ PKHBT_GT: "PKHBT.GT",
+ PKHBT_LE: "PKHBT.LE",
+ PKHBT: "PKHBT",
+ PKHBT_ZZ: "PKHBT.ZZ",
+ PKHTB_EQ: "PKHTB.EQ",
+ PKHTB_NE: "PKHTB.NE",
+ PKHTB_CS: "PKHTB.CS",
+ PKHTB_CC: "PKHTB.CC",
+ PKHTB_MI: "PKHTB.MI",
+ PKHTB_PL: "PKHTB.PL",
+ PKHTB_VS: "PKHTB.VS",
+ PKHTB_VC: "PKHTB.VC",
+ PKHTB_HI: "PKHTB.HI",
+ PKHTB_LS: "PKHTB.LS",
+ PKHTB_GE: "PKHTB.GE",
+ PKHTB_LT: "PKHTB.LT",
+ PKHTB_GT: "PKHTB.GT",
+ PKHTB_LE: "PKHTB.LE",
+ PKHTB: "PKHTB",
+ PKHTB_ZZ: "PKHTB.ZZ",
+ PLD_W: "PLD.W",
+ PLD: "PLD",
+ PLI: "PLI",
+ POP_EQ: "POP.EQ",
+ POP_NE: "POP.NE",
+ POP_CS: "POP.CS",
+ POP_CC: "POP.CC",
+ POP_MI: "POP.MI",
+ POP_PL: "POP.PL",
+ POP_VS: "POP.VS",
+ POP_VC: "POP.VC",
+ POP_HI: "POP.HI",
+ POP_LS: "POP.LS",
+ POP_GE: "POP.GE",
+ POP_LT: "POP.LT",
+ POP_GT: "POP.GT",
+ POP_LE: "POP.LE",
+ POP: "POP",
+ POP_ZZ: "POP.ZZ",
+ PUSH_EQ: "PUSH.EQ",
+ PUSH_NE: "PUSH.NE",
+ PUSH_CS: "PUSH.CS",
+ PUSH_CC: "PUSH.CC",
+ PUSH_MI: "PUSH.MI",
+ PUSH_PL: "PUSH.PL",
+ PUSH_VS: "PUSH.VS",
+ PUSH_VC: "PUSH.VC",
+ PUSH_HI: "PUSH.HI",
+ PUSH_LS: "PUSH.LS",
+ PUSH_GE: "PUSH.GE",
+ PUSH_LT: "PUSH.LT",
+ PUSH_GT: "PUSH.GT",
+ PUSH_LE: "PUSH.LE",
+ PUSH: "PUSH",
+ PUSH_ZZ: "PUSH.ZZ",
+ QADD_EQ: "QADD.EQ",
+ QADD_NE: "QADD.NE",
+ QADD_CS: "QADD.CS",
+ QADD_CC: "QADD.CC",
+ QADD_MI: "QADD.MI",
+ QADD_PL: "QADD.PL",
+ QADD_VS: "QADD.VS",
+ QADD_VC: "QADD.VC",
+ QADD_HI: "QADD.HI",
+ QADD_LS: "QADD.LS",
+ QADD_GE: "QADD.GE",
+ QADD_LT: "QADD.LT",
+ QADD_GT: "QADD.GT",
+ QADD_LE: "QADD.LE",
+ QADD: "QADD",
+ QADD_ZZ: "QADD.ZZ",
+ QADD16_EQ: "QADD16.EQ",
+ QADD16_NE: "QADD16.NE",
+ QADD16_CS: "QADD16.CS",
+ QADD16_CC: "QADD16.CC",
+ QADD16_MI: "QADD16.MI",
+ QADD16_PL: "QADD16.PL",
+ QADD16_VS: "QADD16.VS",
+ QADD16_VC: "QADD16.VC",
+ QADD16_HI: "QADD16.HI",
+ QADD16_LS: "QADD16.LS",
+ QADD16_GE: "QADD16.GE",
+ QADD16_LT: "QADD16.LT",
+ QADD16_GT: "QADD16.GT",
+ QADD16_LE: "QADD16.LE",
+ QADD16: "QADD16",
+ QADD16_ZZ: "QADD16.ZZ",
+ QADD8_EQ: "QADD8.EQ",
+ QADD8_NE: "QADD8.NE",
+ QADD8_CS: "QADD8.CS",
+ QADD8_CC: "QADD8.CC",
+ QADD8_MI: "QADD8.MI",
+ QADD8_PL: "QADD8.PL",
+ QADD8_VS: "QADD8.VS",
+ QADD8_VC: "QADD8.VC",
+ QADD8_HI: "QADD8.HI",
+ QADD8_LS: "QADD8.LS",
+ QADD8_GE: "QADD8.GE",
+ QADD8_LT: "QADD8.LT",
+ QADD8_GT: "QADD8.GT",
+ QADD8_LE: "QADD8.LE",
+ QADD8: "QADD8",
+ QADD8_ZZ: "QADD8.ZZ",
+ QASX_EQ: "QASX.EQ",
+ QASX_NE: "QASX.NE",
+ QASX_CS: "QASX.CS",
+ QASX_CC: "QASX.CC",
+ QASX_MI: "QASX.MI",
+ QASX_PL: "QASX.PL",
+ QASX_VS: "QASX.VS",
+ QASX_VC: "QASX.VC",
+ QASX_HI: "QASX.HI",
+ QASX_LS: "QASX.LS",
+ QASX_GE: "QASX.GE",
+ QASX_LT: "QASX.LT",
+ QASX_GT: "QASX.GT",
+ QASX_LE: "QASX.LE",
+ QASX: "QASX",
+ QASX_ZZ: "QASX.ZZ",
+ QDADD_EQ: "QDADD.EQ",
+ QDADD_NE: "QDADD.NE",
+ QDADD_CS: "QDADD.CS",
+ QDADD_CC: "QDADD.CC",
+ QDADD_MI: "QDADD.MI",
+ QDADD_PL: "QDADD.PL",
+ QDADD_VS: "QDADD.VS",
+ QDADD_VC: "QDADD.VC",
+ QDADD_HI: "QDADD.HI",
+ QDADD_LS: "QDADD.LS",
+ QDADD_GE: "QDADD.GE",
+ QDADD_LT: "QDADD.LT",
+ QDADD_GT: "QDADD.GT",
+ QDADD_LE: "QDADD.LE",
+ QDADD: "QDADD",
+ QDADD_ZZ: "QDADD.ZZ",
+ QDSUB_EQ: "QDSUB.EQ",
+ QDSUB_NE: "QDSUB.NE",
+ QDSUB_CS: "QDSUB.CS",
+ QDSUB_CC: "QDSUB.CC",
+ QDSUB_MI: "QDSUB.MI",
+ QDSUB_PL: "QDSUB.PL",
+ QDSUB_VS: "QDSUB.VS",
+ QDSUB_VC: "QDSUB.VC",
+ QDSUB_HI: "QDSUB.HI",
+ QDSUB_LS: "QDSUB.LS",
+ QDSUB_GE: "QDSUB.GE",
+ QDSUB_LT: "QDSUB.LT",
+ QDSUB_GT: "QDSUB.GT",
+ QDSUB_LE: "QDSUB.LE",
+ QDSUB: "QDSUB",
+ QDSUB_ZZ: "QDSUB.ZZ",
+ QSAX_EQ: "QSAX.EQ",
+ QSAX_NE: "QSAX.NE",
+ QSAX_CS: "QSAX.CS",
+ QSAX_CC: "QSAX.CC",
+ QSAX_MI: "QSAX.MI",
+ QSAX_PL: "QSAX.PL",
+ QSAX_VS: "QSAX.VS",
+ QSAX_VC: "QSAX.VC",
+ QSAX_HI: "QSAX.HI",
+ QSAX_LS: "QSAX.LS",
+ QSAX_GE: "QSAX.GE",
+ QSAX_LT: "QSAX.LT",
+ QSAX_GT: "QSAX.GT",
+ QSAX_LE: "QSAX.LE",
+ QSAX: "QSAX",
+ QSAX_ZZ: "QSAX.ZZ",
+ QSUB_EQ: "QSUB.EQ",
+ QSUB_NE: "QSUB.NE",
+ QSUB_CS: "QSUB.CS",
+ QSUB_CC: "QSUB.CC",
+ QSUB_MI: "QSUB.MI",
+ QSUB_PL: "QSUB.PL",
+ QSUB_VS: "QSUB.VS",
+ QSUB_VC: "QSUB.VC",
+ QSUB_HI: "QSUB.HI",
+ QSUB_LS: "QSUB.LS",
+ QSUB_GE: "QSUB.GE",
+ QSUB_LT: "QSUB.LT",
+ QSUB_GT: "QSUB.GT",
+ QSUB_LE: "QSUB.LE",
+ QSUB: "QSUB",
+ QSUB_ZZ: "QSUB.ZZ",
+ QSUB16_EQ: "QSUB16.EQ",
+ QSUB16_NE: "QSUB16.NE",
+ QSUB16_CS: "QSUB16.CS",
+ QSUB16_CC: "QSUB16.CC",
+ QSUB16_MI: "QSUB16.MI",
+ QSUB16_PL: "QSUB16.PL",
+ QSUB16_VS: "QSUB16.VS",
+ QSUB16_VC: "QSUB16.VC",
+ QSUB16_HI: "QSUB16.HI",
+ QSUB16_LS: "QSUB16.LS",
+ QSUB16_GE: "QSUB16.GE",
+ QSUB16_LT: "QSUB16.LT",
+ QSUB16_GT: "QSUB16.GT",
+ QSUB16_LE: "QSUB16.LE",
+ QSUB16: "QSUB16",
+ QSUB16_ZZ: "QSUB16.ZZ",
+ QSUB8_EQ: "QSUB8.EQ",
+ QSUB8_NE: "QSUB8.NE",
+ QSUB8_CS: "QSUB8.CS",
+ QSUB8_CC: "QSUB8.CC",
+ QSUB8_MI: "QSUB8.MI",
+ QSUB8_PL: "QSUB8.PL",
+ QSUB8_VS: "QSUB8.VS",
+ QSUB8_VC: "QSUB8.VC",
+ QSUB8_HI: "QSUB8.HI",
+ QSUB8_LS: "QSUB8.LS",
+ QSUB8_GE: "QSUB8.GE",
+ QSUB8_LT: "QSUB8.LT",
+ QSUB8_GT: "QSUB8.GT",
+ QSUB8_LE: "QSUB8.LE",
+ QSUB8: "QSUB8",
+ QSUB8_ZZ: "QSUB8.ZZ",
+ RBIT_EQ: "RBIT.EQ",
+ RBIT_NE: "RBIT.NE",
+ RBIT_CS: "RBIT.CS",
+ RBIT_CC: "RBIT.CC",
+ RBIT_MI: "RBIT.MI",
+ RBIT_PL: "RBIT.PL",
+ RBIT_VS: "RBIT.VS",
+ RBIT_VC: "RBIT.VC",
+ RBIT_HI: "RBIT.HI",
+ RBIT_LS: "RBIT.LS",
+ RBIT_GE: "RBIT.GE",
+ RBIT_LT: "RBIT.LT",
+ RBIT_GT: "RBIT.GT",
+ RBIT_LE: "RBIT.LE",
+ RBIT: "RBIT",
+ RBIT_ZZ: "RBIT.ZZ",
+ REV_EQ: "REV.EQ",
+ REV_NE: "REV.NE",
+ REV_CS: "REV.CS",
+ REV_CC: "REV.CC",
+ REV_MI: "REV.MI",
+ REV_PL: "REV.PL",
+ REV_VS: "REV.VS",
+ REV_VC: "REV.VC",
+ REV_HI: "REV.HI",
+ REV_LS: "REV.LS",
+ REV_GE: "REV.GE",
+ REV_LT: "REV.LT",
+ REV_GT: "REV.GT",
+ REV_LE: "REV.LE",
+ REV: "REV",
+ REV_ZZ: "REV.ZZ",
+ REV16_EQ: "REV16.EQ",
+ REV16_NE: "REV16.NE",
+ REV16_CS: "REV16.CS",
+ REV16_CC: "REV16.CC",
+ REV16_MI: "REV16.MI",
+ REV16_PL: "REV16.PL",
+ REV16_VS: "REV16.VS",
+ REV16_VC: "REV16.VC",
+ REV16_HI: "REV16.HI",
+ REV16_LS: "REV16.LS",
+ REV16_GE: "REV16.GE",
+ REV16_LT: "REV16.LT",
+ REV16_GT: "REV16.GT",
+ REV16_LE: "REV16.LE",
+ REV16: "REV16",
+ REV16_ZZ: "REV16.ZZ",
+ REVSH_EQ: "REVSH.EQ",
+ REVSH_NE: "REVSH.NE",
+ REVSH_CS: "REVSH.CS",
+ REVSH_CC: "REVSH.CC",
+ REVSH_MI: "REVSH.MI",
+ REVSH_PL: "REVSH.PL",
+ REVSH_VS: "REVSH.VS",
+ REVSH_VC: "REVSH.VC",
+ REVSH_HI: "REVSH.HI",
+ REVSH_LS: "REVSH.LS",
+ REVSH_GE: "REVSH.GE",
+ REVSH_LT: "REVSH.LT",
+ REVSH_GT: "REVSH.GT",
+ REVSH_LE: "REVSH.LE",
+ REVSH: "REVSH",
+ REVSH_ZZ: "REVSH.ZZ",
+ ROR_EQ: "ROR.EQ",
+ ROR_NE: "ROR.NE",
+ ROR_CS: "ROR.CS",
+ ROR_CC: "ROR.CC",
+ ROR_MI: "ROR.MI",
+ ROR_PL: "ROR.PL",
+ ROR_VS: "ROR.VS",
+ ROR_VC: "ROR.VC",
+ ROR_HI: "ROR.HI",
+ ROR_LS: "ROR.LS",
+ ROR_GE: "ROR.GE",
+ ROR_LT: "ROR.LT",
+ ROR_GT: "ROR.GT",
+ ROR_LE: "ROR.LE",
+ ROR: "ROR",
+ ROR_ZZ: "ROR.ZZ",
+ ROR_S_EQ: "ROR.S.EQ",
+ ROR_S_NE: "ROR.S.NE",
+ ROR_S_CS: "ROR.S.CS",
+ ROR_S_CC: "ROR.S.CC",
+ ROR_S_MI: "ROR.S.MI",
+ ROR_S_PL: "ROR.S.PL",
+ ROR_S_VS: "ROR.S.VS",
+ ROR_S_VC: "ROR.S.VC",
+ ROR_S_HI: "ROR.S.HI",
+ ROR_S_LS: "ROR.S.LS",
+ ROR_S_GE: "ROR.S.GE",
+ ROR_S_LT: "ROR.S.LT",
+ ROR_S_GT: "ROR.S.GT",
+ ROR_S_LE: "ROR.S.LE",
+ ROR_S: "ROR.S",
+ ROR_S_ZZ: "ROR.S.ZZ",
+ RRX_EQ: "RRX.EQ",
+ RRX_NE: "RRX.NE",
+ RRX_CS: "RRX.CS",
+ RRX_CC: "RRX.CC",
+ RRX_MI: "RRX.MI",
+ RRX_PL: "RRX.PL",
+ RRX_VS: "RRX.VS",
+ RRX_VC: "RRX.VC",
+ RRX_HI: "RRX.HI",
+ RRX_LS: "RRX.LS",
+ RRX_GE: "RRX.GE",
+ RRX_LT: "RRX.LT",
+ RRX_GT: "RRX.GT",
+ RRX_LE: "RRX.LE",
+ RRX: "RRX",
+ RRX_ZZ: "RRX.ZZ",
+ RRX_S_EQ: "RRX.S.EQ",
+ RRX_S_NE: "RRX.S.NE",
+ RRX_S_CS: "RRX.S.CS",
+ RRX_S_CC: "RRX.S.CC",
+ RRX_S_MI: "RRX.S.MI",
+ RRX_S_PL: "RRX.S.PL",
+ RRX_S_VS: "RRX.S.VS",
+ RRX_S_VC: "RRX.S.VC",
+ RRX_S_HI: "RRX.S.HI",
+ RRX_S_LS: "RRX.S.LS",
+ RRX_S_GE: "RRX.S.GE",
+ RRX_S_LT: "RRX.S.LT",
+ RRX_S_GT: "RRX.S.GT",
+ RRX_S_LE: "RRX.S.LE",
+ RRX_S: "RRX.S",
+ RRX_S_ZZ: "RRX.S.ZZ",
+ RSB_EQ: "RSB.EQ",
+ RSB_NE: "RSB.NE",
+ RSB_CS: "RSB.CS",
+ RSB_CC: "RSB.CC",
+ RSB_MI: "RSB.MI",
+ RSB_PL: "RSB.PL",
+ RSB_VS: "RSB.VS",
+ RSB_VC: "RSB.VC",
+ RSB_HI: "RSB.HI",
+ RSB_LS: "RSB.LS",
+ RSB_GE: "RSB.GE",
+ RSB_LT: "RSB.LT",
+ RSB_GT: "RSB.GT",
+ RSB_LE: "RSB.LE",
+ RSB: "RSB",
+ RSB_ZZ: "RSB.ZZ",
+ RSB_S_EQ: "RSB.S.EQ",
+ RSB_S_NE: "RSB.S.NE",
+ RSB_S_CS: "RSB.S.CS",
+ RSB_S_CC: "RSB.S.CC",
+ RSB_S_MI: "RSB.S.MI",
+ RSB_S_PL: "RSB.S.PL",
+ RSB_S_VS: "RSB.S.VS",
+ RSB_S_VC: "RSB.S.VC",
+ RSB_S_HI: "RSB.S.HI",
+ RSB_S_LS: "RSB.S.LS",
+ RSB_S_GE: "RSB.S.GE",
+ RSB_S_LT: "RSB.S.LT",
+ RSB_S_GT: "RSB.S.GT",
+ RSB_S_LE: "RSB.S.LE",
+ RSB_S: "RSB.S",
+ RSB_S_ZZ: "RSB.S.ZZ",
+ RSC_EQ: "RSC.EQ",
+ RSC_NE: "RSC.NE",
+ RSC_CS: "RSC.CS",
+ RSC_CC: "RSC.CC",
+ RSC_MI: "RSC.MI",
+ RSC_PL: "RSC.PL",
+ RSC_VS: "RSC.VS",
+ RSC_VC: "RSC.VC",
+ RSC_HI: "RSC.HI",
+ RSC_LS: "RSC.LS",
+ RSC_GE: "RSC.GE",
+ RSC_LT: "RSC.LT",
+ RSC_GT: "RSC.GT",
+ RSC_LE: "RSC.LE",
+ RSC: "RSC",
+ RSC_ZZ: "RSC.ZZ",
+ RSC_S_EQ: "RSC.S.EQ",
+ RSC_S_NE: "RSC.S.NE",
+ RSC_S_CS: "RSC.S.CS",
+ RSC_S_CC: "RSC.S.CC",
+ RSC_S_MI: "RSC.S.MI",
+ RSC_S_PL: "RSC.S.PL",
+ RSC_S_VS: "RSC.S.VS",
+ RSC_S_VC: "RSC.S.VC",
+ RSC_S_HI: "RSC.S.HI",
+ RSC_S_LS: "RSC.S.LS",
+ RSC_S_GE: "RSC.S.GE",
+ RSC_S_LT: "RSC.S.LT",
+ RSC_S_GT: "RSC.S.GT",
+ RSC_S_LE: "RSC.S.LE",
+ RSC_S: "RSC.S",
+ RSC_S_ZZ: "RSC.S.ZZ",
+ SADD16_EQ: "SADD16.EQ",
+ SADD16_NE: "SADD16.NE",
+ SADD16_CS: "SADD16.CS",
+ SADD16_CC: "SADD16.CC",
+ SADD16_MI: "SADD16.MI",
+ SADD16_PL: "SADD16.PL",
+ SADD16_VS: "SADD16.VS",
+ SADD16_VC: "SADD16.VC",
+ SADD16_HI: "SADD16.HI",
+ SADD16_LS: "SADD16.LS",
+ SADD16_GE: "SADD16.GE",
+ SADD16_LT: "SADD16.LT",
+ SADD16_GT: "SADD16.GT",
+ SADD16_LE: "SADD16.LE",
+ SADD16: "SADD16",
+ SADD16_ZZ: "SADD16.ZZ",
+ SADD8_EQ: "SADD8.EQ",
+ SADD8_NE: "SADD8.NE",
+ SADD8_CS: "SADD8.CS",
+ SADD8_CC: "SADD8.CC",
+ SADD8_MI: "SADD8.MI",
+ SADD8_PL: "SADD8.PL",
+ SADD8_VS: "SADD8.VS",
+ SADD8_VC: "SADD8.VC",
+ SADD8_HI: "SADD8.HI",
+ SADD8_LS: "SADD8.LS",
+ SADD8_GE: "SADD8.GE",
+ SADD8_LT: "SADD8.LT",
+ SADD8_GT: "SADD8.GT",
+ SADD8_LE: "SADD8.LE",
+ SADD8: "SADD8",
+ SADD8_ZZ: "SADD8.ZZ",
+ SASX_EQ: "SASX.EQ",
+ SASX_NE: "SASX.NE",
+ SASX_CS: "SASX.CS",
+ SASX_CC: "SASX.CC",
+ SASX_MI: "SASX.MI",
+ SASX_PL: "SASX.PL",
+ SASX_VS: "SASX.VS",
+ SASX_VC: "SASX.VC",
+ SASX_HI: "SASX.HI",
+ SASX_LS: "SASX.LS",
+ SASX_GE: "SASX.GE",
+ SASX_LT: "SASX.LT",
+ SASX_GT: "SASX.GT",
+ SASX_LE: "SASX.LE",
+ SASX: "SASX",
+ SASX_ZZ: "SASX.ZZ",
+ SBC_EQ: "SBC.EQ",
+ SBC_NE: "SBC.NE",
+ SBC_CS: "SBC.CS",
+ SBC_CC: "SBC.CC",
+ SBC_MI: "SBC.MI",
+ SBC_PL: "SBC.PL",
+ SBC_VS: "SBC.VS",
+ SBC_VC: "SBC.VC",
+ SBC_HI: "SBC.HI",
+ SBC_LS: "SBC.LS",
+ SBC_GE: "SBC.GE",
+ SBC_LT: "SBC.LT",
+ SBC_GT: "SBC.GT",
+ SBC_LE: "SBC.LE",
+ SBC: "SBC",
+ SBC_ZZ: "SBC.ZZ",
+ SBC_S_EQ: "SBC.S.EQ",
+ SBC_S_NE: "SBC.S.NE",
+ SBC_S_CS: "SBC.S.CS",
+ SBC_S_CC: "SBC.S.CC",
+ SBC_S_MI: "SBC.S.MI",
+ SBC_S_PL: "SBC.S.PL",
+ SBC_S_VS: "SBC.S.VS",
+ SBC_S_VC: "SBC.S.VC",
+ SBC_S_HI: "SBC.S.HI",
+ SBC_S_LS: "SBC.S.LS",
+ SBC_S_GE: "SBC.S.GE",
+ SBC_S_LT: "SBC.S.LT",
+ SBC_S_GT: "SBC.S.GT",
+ SBC_S_LE: "SBC.S.LE",
+ SBC_S: "SBC.S",
+ SBC_S_ZZ: "SBC.S.ZZ",
+ SBFX_EQ: "SBFX.EQ",
+ SBFX_NE: "SBFX.NE",
+ SBFX_CS: "SBFX.CS",
+ SBFX_CC: "SBFX.CC",
+ SBFX_MI: "SBFX.MI",
+ SBFX_PL: "SBFX.PL",
+ SBFX_VS: "SBFX.VS",
+ SBFX_VC: "SBFX.VC",
+ SBFX_HI: "SBFX.HI",
+ SBFX_LS: "SBFX.LS",
+ SBFX_GE: "SBFX.GE",
+ SBFX_LT: "SBFX.LT",
+ SBFX_GT: "SBFX.GT",
+ SBFX_LE: "SBFX.LE",
+ SBFX: "SBFX",
+ SBFX_ZZ: "SBFX.ZZ",
+ SEL_EQ: "SEL.EQ",
+ SEL_NE: "SEL.NE",
+ SEL_CS: "SEL.CS",
+ SEL_CC: "SEL.CC",
+ SEL_MI: "SEL.MI",
+ SEL_PL: "SEL.PL",
+ SEL_VS: "SEL.VS",
+ SEL_VC: "SEL.VC",
+ SEL_HI: "SEL.HI",
+ SEL_LS: "SEL.LS",
+ SEL_GE: "SEL.GE",
+ SEL_LT: "SEL.LT",
+ SEL_GT: "SEL.GT",
+ SEL_LE: "SEL.LE",
+ SEL: "SEL",
+ SEL_ZZ: "SEL.ZZ",
+ SETEND: "SETEND",
+ SEV_EQ: "SEV.EQ",
+ SEV_NE: "SEV.NE",
+ SEV_CS: "SEV.CS",
+ SEV_CC: "SEV.CC",
+ SEV_MI: "SEV.MI",
+ SEV_PL: "SEV.PL",
+ SEV_VS: "SEV.VS",
+ SEV_VC: "SEV.VC",
+ SEV_HI: "SEV.HI",
+ SEV_LS: "SEV.LS",
+ SEV_GE: "SEV.GE",
+ SEV_LT: "SEV.LT",
+ SEV_GT: "SEV.GT",
+ SEV_LE: "SEV.LE",
+ SEV: "SEV",
+ SEV_ZZ: "SEV.ZZ",
+ SHADD16_EQ: "SHADD16.EQ",
+ SHADD16_NE: "SHADD16.NE",
+ SHADD16_CS: "SHADD16.CS",
+ SHADD16_CC: "SHADD16.CC",
+ SHADD16_MI: "SHADD16.MI",
+ SHADD16_PL: "SHADD16.PL",
+ SHADD16_VS: "SHADD16.VS",
+ SHADD16_VC: "SHADD16.VC",
+ SHADD16_HI: "SHADD16.HI",
+ SHADD16_LS: "SHADD16.LS",
+ SHADD16_GE: "SHADD16.GE",
+ SHADD16_LT: "SHADD16.LT",
+ SHADD16_GT: "SHADD16.GT",
+ SHADD16_LE: "SHADD16.LE",
+ SHADD16: "SHADD16",
+ SHADD16_ZZ: "SHADD16.ZZ",
+ SHADD8_EQ: "SHADD8.EQ",
+ SHADD8_NE: "SHADD8.NE",
+ SHADD8_CS: "SHADD8.CS",
+ SHADD8_CC: "SHADD8.CC",
+ SHADD8_MI: "SHADD8.MI",
+ SHADD8_PL: "SHADD8.PL",
+ SHADD8_VS: "SHADD8.VS",
+ SHADD8_VC: "SHADD8.VC",
+ SHADD8_HI: "SHADD8.HI",
+ SHADD8_LS: "SHADD8.LS",
+ SHADD8_GE: "SHADD8.GE",
+ SHADD8_LT: "SHADD8.LT",
+ SHADD8_GT: "SHADD8.GT",
+ SHADD8_LE: "SHADD8.LE",
+ SHADD8: "SHADD8",
+ SHADD8_ZZ: "SHADD8.ZZ",
+ SHASX_EQ: "SHASX.EQ",
+ SHASX_NE: "SHASX.NE",
+ SHASX_CS: "SHASX.CS",
+ SHASX_CC: "SHASX.CC",
+ SHASX_MI: "SHASX.MI",
+ SHASX_PL: "SHASX.PL",
+ SHASX_VS: "SHASX.VS",
+ SHASX_VC: "SHASX.VC",
+ SHASX_HI: "SHASX.HI",
+ SHASX_LS: "SHASX.LS",
+ SHASX_GE: "SHASX.GE",
+ SHASX_LT: "SHASX.LT",
+ SHASX_GT: "SHASX.GT",
+ SHASX_LE: "SHASX.LE",
+ SHASX: "SHASX",
+ SHASX_ZZ: "SHASX.ZZ",
+ SHSAX_EQ: "SHSAX.EQ",
+ SHSAX_NE: "SHSAX.NE",
+ SHSAX_CS: "SHSAX.CS",
+ SHSAX_CC: "SHSAX.CC",
+ SHSAX_MI: "SHSAX.MI",
+ SHSAX_PL: "SHSAX.PL",
+ SHSAX_VS: "SHSAX.VS",
+ SHSAX_VC: "SHSAX.VC",
+ SHSAX_HI: "SHSAX.HI",
+ SHSAX_LS: "SHSAX.LS",
+ SHSAX_GE: "SHSAX.GE",
+ SHSAX_LT: "SHSAX.LT",
+ SHSAX_GT: "SHSAX.GT",
+ SHSAX_LE: "SHSAX.LE",
+ SHSAX: "SHSAX",
+ SHSAX_ZZ: "SHSAX.ZZ",
+ SHSUB16_EQ: "SHSUB16.EQ",
+ SHSUB16_NE: "SHSUB16.NE",
+ SHSUB16_CS: "SHSUB16.CS",
+ SHSUB16_CC: "SHSUB16.CC",
+ SHSUB16_MI: "SHSUB16.MI",
+ SHSUB16_PL: "SHSUB16.PL",
+ SHSUB16_VS: "SHSUB16.VS",
+ SHSUB16_VC: "SHSUB16.VC",
+ SHSUB16_HI: "SHSUB16.HI",
+ SHSUB16_LS: "SHSUB16.LS",
+ SHSUB16_GE: "SHSUB16.GE",
+ SHSUB16_LT: "SHSUB16.LT",
+ SHSUB16_GT: "SHSUB16.GT",
+ SHSUB16_LE: "SHSUB16.LE",
+ SHSUB16: "SHSUB16",
+ SHSUB16_ZZ: "SHSUB16.ZZ",
+ SHSUB8_EQ: "SHSUB8.EQ",
+ SHSUB8_NE: "SHSUB8.NE",
+ SHSUB8_CS: "SHSUB8.CS",
+ SHSUB8_CC: "SHSUB8.CC",
+ SHSUB8_MI: "SHSUB8.MI",
+ SHSUB8_PL: "SHSUB8.PL",
+ SHSUB8_VS: "SHSUB8.VS",
+ SHSUB8_VC: "SHSUB8.VC",
+ SHSUB8_HI: "SHSUB8.HI",
+ SHSUB8_LS: "SHSUB8.LS",
+ SHSUB8_GE: "SHSUB8.GE",
+ SHSUB8_LT: "SHSUB8.LT",
+ SHSUB8_GT: "SHSUB8.GT",
+ SHSUB8_LE: "SHSUB8.LE",
+ SHSUB8: "SHSUB8",
+ SHSUB8_ZZ: "SHSUB8.ZZ",
+ SMLABB_EQ: "SMLABB.EQ",
+ SMLABB_NE: "SMLABB.NE",
+ SMLABB_CS: "SMLABB.CS",
+ SMLABB_CC: "SMLABB.CC",
+ SMLABB_MI: "SMLABB.MI",
+ SMLABB_PL: "SMLABB.PL",
+ SMLABB_VS: "SMLABB.VS",
+ SMLABB_VC: "SMLABB.VC",
+ SMLABB_HI: "SMLABB.HI",
+ SMLABB_LS: "SMLABB.LS",
+ SMLABB_GE: "SMLABB.GE",
+ SMLABB_LT: "SMLABB.LT",
+ SMLABB_GT: "SMLABB.GT",
+ SMLABB_LE: "SMLABB.LE",
+ SMLABB: "SMLABB",
+ SMLABB_ZZ: "SMLABB.ZZ",
+ SMLABT_EQ: "SMLABT.EQ",
+ SMLABT_NE: "SMLABT.NE",
+ SMLABT_CS: "SMLABT.CS",
+ SMLABT_CC: "SMLABT.CC",
+ SMLABT_MI: "SMLABT.MI",
+ SMLABT_PL: "SMLABT.PL",
+ SMLABT_VS: "SMLABT.VS",
+ SMLABT_VC: "SMLABT.VC",
+ SMLABT_HI: "SMLABT.HI",
+ SMLABT_LS: "SMLABT.LS",
+ SMLABT_GE: "SMLABT.GE",
+ SMLABT_LT: "SMLABT.LT",
+ SMLABT_GT: "SMLABT.GT",
+ SMLABT_LE: "SMLABT.LE",
+ SMLABT: "SMLABT",
+ SMLABT_ZZ: "SMLABT.ZZ",
+ SMLATB_EQ: "SMLATB.EQ",
+ SMLATB_NE: "SMLATB.NE",
+ SMLATB_CS: "SMLATB.CS",
+ SMLATB_CC: "SMLATB.CC",
+ SMLATB_MI: "SMLATB.MI",
+ SMLATB_PL: "SMLATB.PL",
+ SMLATB_VS: "SMLATB.VS",
+ SMLATB_VC: "SMLATB.VC",
+ SMLATB_HI: "SMLATB.HI",
+ SMLATB_LS: "SMLATB.LS",
+ SMLATB_GE: "SMLATB.GE",
+ SMLATB_LT: "SMLATB.LT",
+ SMLATB_GT: "SMLATB.GT",
+ SMLATB_LE: "SMLATB.LE",
+ SMLATB: "SMLATB",
+ SMLATB_ZZ: "SMLATB.ZZ",
+ SMLATT_EQ: "SMLATT.EQ",
+ SMLATT_NE: "SMLATT.NE",
+ SMLATT_CS: "SMLATT.CS",
+ SMLATT_CC: "SMLATT.CC",
+ SMLATT_MI: "SMLATT.MI",
+ SMLATT_PL: "SMLATT.PL",
+ SMLATT_VS: "SMLATT.VS",
+ SMLATT_VC: "SMLATT.VC",
+ SMLATT_HI: "SMLATT.HI",
+ SMLATT_LS: "SMLATT.LS",
+ SMLATT_GE: "SMLATT.GE",
+ SMLATT_LT: "SMLATT.LT",
+ SMLATT_GT: "SMLATT.GT",
+ SMLATT_LE: "SMLATT.LE",
+ SMLATT: "SMLATT",
+ SMLATT_ZZ: "SMLATT.ZZ",
+ SMLAD_EQ: "SMLAD.EQ",
+ SMLAD_NE: "SMLAD.NE",
+ SMLAD_CS: "SMLAD.CS",
+ SMLAD_CC: "SMLAD.CC",
+ SMLAD_MI: "SMLAD.MI",
+ SMLAD_PL: "SMLAD.PL",
+ SMLAD_VS: "SMLAD.VS",
+ SMLAD_VC: "SMLAD.VC",
+ SMLAD_HI: "SMLAD.HI",
+ SMLAD_LS: "SMLAD.LS",
+ SMLAD_GE: "SMLAD.GE",
+ SMLAD_LT: "SMLAD.LT",
+ SMLAD_GT: "SMLAD.GT",
+ SMLAD_LE: "SMLAD.LE",
+ SMLAD: "SMLAD",
+ SMLAD_ZZ: "SMLAD.ZZ",
+ SMLAD_X_EQ: "SMLAD.X.EQ",
+ SMLAD_X_NE: "SMLAD.X.NE",
+ SMLAD_X_CS: "SMLAD.X.CS",
+ SMLAD_X_CC: "SMLAD.X.CC",
+ SMLAD_X_MI: "SMLAD.X.MI",
+ SMLAD_X_PL: "SMLAD.X.PL",
+ SMLAD_X_VS: "SMLAD.X.VS",
+ SMLAD_X_VC: "SMLAD.X.VC",
+ SMLAD_X_HI: "SMLAD.X.HI",
+ SMLAD_X_LS: "SMLAD.X.LS",
+ SMLAD_X_GE: "SMLAD.X.GE",
+ SMLAD_X_LT: "SMLAD.X.LT",
+ SMLAD_X_GT: "SMLAD.X.GT",
+ SMLAD_X_LE: "SMLAD.X.LE",
+ SMLAD_X: "SMLAD.X",
+ SMLAD_X_ZZ: "SMLAD.X.ZZ",
+ SMLAL_EQ: "SMLAL.EQ",
+ SMLAL_NE: "SMLAL.NE",
+ SMLAL_CS: "SMLAL.CS",
+ SMLAL_CC: "SMLAL.CC",
+ SMLAL_MI: "SMLAL.MI",
+ SMLAL_PL: "SMLAL.PL",
+ SMLAL_VS: "SMLAL.VS",
+ SMLAL_VC: "SMLAL.VC",
+ SMLAL_HI: "SMLAL.HI",
+ SMLAL_LS: "SMLAL.LS",
+ SMLAL_GE: "SMLAL.GE",
+ SMLAL_LT: "SMLAL.LT",
+ SMLAL_GT: "SMLAL.GT",
+ SMLAL_LE: "SMLAL.LE",
+ SMLAL: "SMLAL",
+ SMLAL_ZZ: "SMLAL.ZZ",
+ SMLAL_S_EQ: "SMLAL.S.EQ",
+ SMLAL_S_NE: "SMLAL.S.NE",
+ SMLAL_S_CS: "SMLAL.S.CS",
+ SMLAL_S_CC: "SMLAL.S.CC",
+ SMLAL_S_MI: "SMLAL.S.MI",
+ SMLAL_S_PL: "SMLAL.S.PL",
+ SMLAL_S_VS: "SMLAL.S.VS",
+ SMLAL_S_VC: "SMLAL.S.VC",
+ SMLAL_S_HI: "SMLAL.S.HI",
+ SMLAL_S_LS: "SMLAL.S.LS",
+ SMLAL_S_GE: "SMLAL.S.GE",
+ SMLAL_S_LT: "SMLAL.S.LT",
+ SMLAL_S_GT: "SMLAL.S.GT",
+ SMLAL_S_LE: "SMLAL.S.LE",
+ SMLAL_S: "SMLAL.S",
+ SMLAL_S_ZZ: "SMLAL.S.ZZ",
+ SMLALBB_EQ: "SMLALBB.EQ",
+ SMLALBB_NE: "SMLALBB.NE",
+ SMLALBB_CS: "SMLALBB.CS",
+ SMLALBB_CC: "SMLALBB.CC",
+ SMLALBB_MI: "SMLALBB.MI",
+ SMLALBB_PL: "SMLALBB.PL",
+ SMLALBB_VS: "SMLALBB.VS",
+ SMLALBB_VC: "SMLALBB.VC",
+ SMLALBB_HI: "SMLALBB.HI",
+ SMLALBB_LS: "SMLALBB.LS",
+ SMLALBB_GE: "SMLALBB.GE",
+ SMLALBB_LT: "SMLALBB.LT",
+ SMLALBB_GT: "SMLALBB.GT",
+ SMLALBB_LE: "SMLALBB.LE",
+ SMLALBB: "SMLALBB",
+ SMLALBB_ZZ: "SMLALBB.ZZ",
+ SMLALBT_EQ: "SMLALBT.EQ",
+ SMLALBT_NE: "SMLALBT.NE",
+ SMLALBT_CS: "SMLALBT.CS",
+ SMLALBT_CC: "SMLALBT.CC",
+ SMLALBT_MI: "SMLALBT.MI",
+ SMLALBT_PL: "SMLALBT.PL",
+ SMLALBT_VS: "SMLALBT.VS",
+ SMLALBT_VC: "SMLALBT.VC",
+ SMLALBT_HI: "SMLALBT.HI",
+ SMLALBT_LS: "SMLALBT.LS",
+ SMLALBT_GE: "SMLALBT.GE",
+ SMLALBT_LT: "SMLALBT.LT",
+ SMLALBT_GT: "SMLALBT.GT",
+ SMLALBT_LE: "SMLALBT.LE",
+ SMLALBT: "SMLALBT",
+ SMLALBT_ZZ: "SMLALBT.ZZ",
+ SMLALTB_EQ: "SMLALTB.EQ",
+ SMLALTB_NE: "SMLALTB.NE",
+ SMLALTB_CS: "SMLALTB.CS",
+ SMLALTB_CC: "SMLALTB.CC",
+ SMLALTB_MI: "SMLALTB.MI",
+ SMLALTB_PL: "SMLALTB.PL",
+ SMLALTB_VS: "SMLALTB.VS",
+ SMLALTB_VC: "SMLALTB.VC",
+ SMLALTB_HI: "SMLALTB.HI",
+ SMLALTB_LS: "SMLALTB.LS",
+ SMLALTB_GE: "SMLALTB.GE",
+ SMLALTB_LT: "SMLALTB.LT",
+ SMLALTB_GT: "SMLALTB.GT",
+ SMLALTB_LE: "SMLALTB.LE",
+ SMLALTB: "SMLALTB",
+ SMLALTB_ZZ: "SMLALTB.ZZ",
+ SMLALTT_EQ: "SMLALTT.EQ",
+ SMLALTT_NE: "SMLALTT.NE",
+ SMLALTT_CS: "SMLALTT.CS",
+ SMLALTT_CC: "SMLALTT.CC",
+ SMLALTT_MI: "SMLALTT.MI",
+ SMLALTT_PL: "SMLALTT.PL",
+ SMLALTT_VS: "SMLALTT.VS",
+ SMLALTT_VC: "SMLALTT.VC",
+ SMLALTT_HI: "SMLALTT.HI",
+ SMLALTT_LS: "SMLALTT.LS",
+ SMLALTT_GE: "SMLALTT.GE",
+ SMLALTT_LT: "SMLALTT.LT",
+ SMLALTT_GT: "SMLALTT.GT",
+ SMLALTT_LE: "SMLALTT.LE",
+ SMLALTT: "SMLALTT",
+ SMLALTT_ZZ: "SMLALTT.ZZ",
+ SMLALD_EQ: "SMLALD.EQ",
+ SMLALD_NE: "SMLALD.NE",
+ SMLALD_CS: "SMLALD.CS",
+ SMLALD_CC: "SMLALD.CC",
+ SMLALD_MI: "SMLALD.MI",
+ SMLALD_PL: "SMLALD.PL",
+ SMLALD_VS: "SMLALD.VS",
+ SMLALD_VC: "SMLALD.VC",
+ SMLALD_HI: "SMLALD.HI",
+ SMLALD_LS: "SMLALD.LS",
+ SMLALD_GE: "SMLALD.GE",
+ SMLALD_LT: "SMLALD.LT",
+ SMLALD_GT: "SMLALD.GT",
+ SMLALD_LE: "SMLALD.LE",
+ SMLALD: "SMLALD",
+ SMLALD_ZZ: "SMLALD.ZZ",
+ SMLALD_X_EQ: "SMLALD.X.EQ",
+ SMLALD_X_NE: "SMLALD.X.NE",
+ SMLALD_X_CS: "SMLALD.X.CS",
+ SMLALD_X_CC: "SMLALD.X.CC",
+ SMLALD_X_MI: "SMLALD.X.MI",
+ SMLALD_X_PL: "SMLALD.X.PL",
+ SMLALD_X_VS: "SMLALD.X.VS",
+ SMLALD_X_VC: "SMLALD.X.VC",
+ SMLALD_X_HI: "SMLALD.X.HI",
+ SMLALD_X_LS: "SMLALD.X.LS",
+ SMLALD_X_GE: "SMLALD.X.GE",
+ SMLALD_X_LT: "SMLALD.X.LT",
+ SMLALD_X_GT: "SMLALD.X.GT",
+ SMLALD_X_LE: "SMLALD.X.LE",
+ SMLALD_X: "SMLALD.X",
+ SMLALD_X_ZZ: "SMLALD.X.ZZ",
+ SMLAWB_EQ: "SMLAWB.EQ",
+ SMLAWB_NE: "SMLAWB.NE",
+ SMLAWB_CS: "SMLAWB.CS",
+ SMLAWB_CC: "SMLAWB.CC",
+ SMLAWB_MI: "SMLAWB.MI",
+ SMLAWB_PL: "SMLAWB.PL",
+ SMLAWB_VS: "SMLAWB.VS",
+ SMLAWB_VC: "SMLAWB.VC",
+ SMLAWB_HI: "SMLAWB.HI",
+ SMLAWB_LS: "SMLAWB.LS",
+ SMLAWB_GE: "SMLAWB.GE",
+ SMLAWB_LT: "SMLAWB.LT",
+ SMLAWB_GT: "SMLAWB.GT",
+ SMLAWB_LE: "SMLAWB.LE",
+ SMLAWB: "SMLAWB",
+ SMLAWB_ZZ: "SMLAWB.ZZ",
+ SMLAWT_EQ: "SMLAWT.EQ",
+ SMLAWT_NE: "SMLAWT.NE",
+ SMLAWT_CS: "SMLAWT.CS",
+ SMLAWT_CC: "SMLAWT.CC",
+ SMLAWT_MI: "SMLAWT.MI",
+ SMLAWT_PL: "SMLAWT.PL",
+ SMLAWT_VS: "SMLAWT.VS",
+ SMLAWT_VC: "SMLAWT.VC",
+ SMLAWT_HI: "SMLAWT.HI",
+ SMLAWT_LS: "SMLAWT.LS",
+ SMLAWT_GE: "SMLAWT.GE",
+ SMLAWT_LT: "SMLAWT.LT",
+ SMLAWT_GT: "SMLAWT.GT",
+ SMLAWT_LE: "SMLAWT.LE",
+ SMLAWT: "SMLAWT",
+ SMLAWT_ZZ: "SMLAWT.ZZ",
+ SMLSD_EQ: "SMLSD.EQ",
+ SMLSD_NE: "SMLSD.NE",
+ SMLSD_CS: "SMLSD.CS",
+ SMLSD_CC: "SMLSD.CC",
+ SMLSD_MI: "SMLSD.MI",
+ SMLSD_PL: "SMLSD.PL",
+ SMLSD_VS: "SMLSD.VS",
+ SMLSD_VC: "SMLSD.VC",
+ SMLSD_HI: "SMLSD.HI",
+ SMLSD_LS: "SMLSD.LS",
+ SMLSD_GE: "SMLSD.GE",
+ SMLSD_LT: "SMLSD.LT",
+ SMLSD_GT: "SMLSD.GT",
+ SMLSD_LE: "SMLSD.LE",
+ SMLSD: "SMLSD",
+ SMLSD_ZZ: "SMLSD.ZZ",
+ SMLSD_X_EQ: "SMLSD.X.EQ",
+ SMLSD_X_NE: "SMLSD.X.NE",
+ SMLSD_X_CS: "SMLSD.X.CS",
+ SMLSD_X_CC: "SMLSD.X.CC",
+ SMLSD_X_MI: "SMLSD.X.MI",
+ SMLSD_X_PL: "SMLSD.X.PL",
+ SMLSD_X_VS: "SMLSD.X.VS",
+ SMLSD_X_VC: "SMLSD.X.VC",
+ SMLSD_X_HI: "SMLSD.X.HI",
+ SMLSD_X_LS: "SMLSD.X.LS",
+ SMLSD_X_GE: "SMLSD.X.GE",
+ SMLSD_X_LT: "SMLSD.X.LT",
+ SMLSD_X_GT: "SMLSD.X.GT",
+ SMLSD_X_LE: "SMLSD.X.LE",
+ SMLSD_X: "SMLSD.X",
+ SMLSD_X_ZZ: "SMLSD.X.ZZ",
+ SMLSLD_EQ: "SMLSLD.EQ",
+ SMLSLD_NE: "SMLSLD.NE",
+ SMLSLD_CS: "SMLSLD.CS",
+ SMLSLD_CC: "SMLSLD.CC",
+ SMLSLD_MI: "SMLSLD.MI",
+ SMLSLD_PL: "SMLSLD.PL",
+ SMLSLD_VS: "SMLSLD.VS",
+ SMLSLD_VC: "SMLSLD.VC",
+ SMLSLD_HI: "SMLSLD.HI",
+ SMLSLD_LS: "SMLSLD.LS",
+ SMLSLD_GE: "SMLSLD.GE",
+ SMLSLD_LT: "SMLSLD.LT",
+ SMLSLD_GT: "SMLSLD.GT",
+ SMLSLD_LE: "SMLSLD.LE",
+ SMLSLD: "SMLSLD",
+ SMLSLD_ZZ: "SMLSLD.ZZ",
+ SMLSLD_X_EQ: "SMLSLD.X.EQ",
+ SMLSLD_X_NE: "SMLSLD.X.NE",
+ SMLSLD_X_CS: "SMLSLD.X.CS",
+ SMLSLD_X_CC: "SMLSLD.X.CC",
+ SMLSLD_X_MI: "SMLSLD.X.MI",
+ SMLSLD_X_PL: "SMLSLD.X.PL",
+ SMLSLD_X_VS: "SMLSLD.X.VS",
+ SMLSLD_X_VC: "SMLSLD.X.VC",
+ SMLSLD_X_HI: "SMLSLD.X.HI",
+ SMLSLD_X_LS: "SMLSLD.X.LS",
+ SMLSLD_X_GE: "SMLSLD.X.GE",
+ SMLSLD_X_LT: "SMLSLD.X.LT",
+ SMLSLD_X_GT: "SMLSLD.X.GT",
+ SMLSLD_X_LE: "SMLSLD.X.LE",
+ SMLSLD_X: "SMLSLD.X",
+ SMLSLD_X_ZZ: "SMLSLD.X.ZZ",
+ SMMLA_EQ: "SMMLA.EQ",
+ SMMLA_NE: "SMMLA.NE",
+ SMMLA_CS: "SMMLA.CS",
+ SMMLA_CC: "SMMLA.CC",
+ SMMLA_MI: "SMMLA.MI",
+ SMMLA_PL: "SMMLA.PL",
+ SMMLA_VS: "SMMLA.VS",
+ SMMLA_VC: "SMMLA.VC",
+ SMMLA_HI: "SMMLA.HI",
+ SMMLA_LS: "SMMLA.LS",
+ SMMLA_GE: "SMMLA.GE",
+ SMMLA_LT: "SMMLA.LT",
+ SMMLA_GT: "SMMLA.GT",
+ SMMLA_LE: "SMMLA.LE",
+ SMMLA: "SMMLA",
+ SMMLA_ZZ: "SMMLA.ZZ",
+ SMMLA_R_EQ: "SMMLA.R.EQ",
+ SMMLA_R_NE: "SMMLA.R.NE",
+ SMMLA_R_CS: "SMMLA.R.CS",
+ SMMLA_R_CC: "SMMLA.R.CC",
+ SMMLA_R_MI: "SMMLA.R.MI",
+ SMMLA_R_PL: "SMMLA.R.PL",
+ SMMLA_R_VS: "SMMLA.R.VS",
+ SMMLA_R_VC: "SMMLA.R.VC",
+ SMMLA_R_HI: "SMMLA.R.HI",
+ SMMLA_R_LS: "SMMLA.R.LS",
+ SMMLA_R_GE: "SMMLA.R.GE",
+ SMMLA_R_LT: "SMMLA.R.LT",
+ SMMLA_R_GT: "SMMLA.R.GT",
+ SMMLA_R_LE: "SMMLA.R.LE",
+ SMMLA_R: "SMMLA.R",
+ SMMLA_R_ZZ: "SMMLA.R.ZZ",
+ SMMLS_EQ: "SMMLS.EQ",
+ SMMLS_NE: "SMMLS.NE",
+ SMMLS_CS: "SMMLS.CS",
+ SMMLS_CC: "SMMLS.CC",
+ SMMLS_MI: "SMMLS.MI",
+ SMMLS_PL: "SMMLS.PL",
+ SMMLS_VS: "SMMLS.VS",
+ SMMLS_VC: "SMMLS.VC",
+ SMMLS_HI: "SMMLS.HI",
+ SMMLS_LS: "SMMLS.LS",
+ SMMLS_GE: "SMMLS.GE",
+ SMMLS_LT: "SMMLS.LT",
+ SMMLS_GT: "SMMLS.GT",
+ SMMLS_LE: "SMMLS.LE",
+ SMMLS: "SMMLS",
+ SMMLS_ZZ: "SMMLS.ZZ",
+ SMMLS_R_EQ: "SMMLS.R.EQ",
+ SMMLS_R_NE: "SMMLS.R.NE",
+ SMMLS_R_CS: "SMMLS.R.CS",
+ SMMLS_R_CC: "SMMLS.R.CC",
+ SMMLS_R_MI: "SMMLS.R.MI",
+ SMMLS_R_PL: "SMMLS.R.PL",
+ SMMLS_R_VS: "SMMLS.R.VS",
+ SMMLS_R_VC: "SMMLS.R.VC",
+ SMMLS_R_HI: "SMMLS.R.HI",
+ SMMLS_R_LS: "SMMLS.R.LS",
+ SMMLS_R_GE: "SMMLS.R.GE",
+ SMMLS_R_LT: "SMMLS.R.LT",
+ SMMLS_R_GT: "SMMLS.R.GT",
+ SMMLS_R_LE: "SMMLS.R.LE",
+ SMMLS_R: "SMMLS.R",
+ SMMLS_R_ZZ: "SMMLS.R.ZZ",
+ SMMUL_EQ: "SMMUL.EQ",
+ SMMUL_NE: "SMMUL.NE",
+ SMMUL_CS: "SMMUL.CS",
+ SMMUL_CC: "SMMUL.CC",
+ SMMUL_MI: "SMMUL.MI",
+ SMMUL_PL: "SMMUL.PL",
+ SMMUL_VS: "SMMUL.VS",
+ SMMUL_VC: "SMMUL.VC",
+ SMMUL_HI: "SMMUL.HI",
+ SMMUL_LS: "SMMUL.LS",
+ SMMUL_GE: "SMMUL.GE",
+ SMMUL_LT: "SMMUL.LT",
+ SMMUL_GT: "SMMUL.GT",
+ SMMUL_LE: "SMMUL.LE",
+ SMMUL: "SMMUL",
+ SMMUL_ZZ: "SMMUL.ZZ",
+ SMMUL_R_EQ: "SMMUL.R.EQ",
+ SMMUL_R_NE: "SMMUL.R.NE",
+ SMMUL_R_CS: "SMMUL.R.CS",
+ SMMUL_R_CC: "SMMUL.R.CC",
+ SMMUL_R_MI: "SMMUL.R.MI",
+ SMMUL_R_PL: "SMMUL.R.PL",
+ SMMUL_R_VS: "SMMUL.R.VS",
+ SMMUL_R_VC: "SMMUL.R.VC",
+ SMMUL_R_HI: "SMMUL.R.HI",
+ SMMUL_R_LS: "SMMUL.R.LS",
+ SMMUL_R_GE: "SMMUL.R.GE",
+ SMMUL_R_LT: "SMMUL.R.LT",
+ SMMUL_R_GT: "SMMUL.R.GT",
+ SMMUL_R_LE: "SMMUL.R.LE",
+ SMMUL_R: "SMMUL.R",
+ SMMUL_R_ZZ: "SMMUL.R.ZZ",
+ SMUAD_EQ: "SMUAD.EQ",
+ SMUAD_NE: "SMUAD.NE",
+ SMUAD_CS: "SMUAD.CS",
+ SMUAD_CC: "SMUAD.CC",
+ SMUAD_MI: "SMUAD.MI",
+ SMUAD_PL: "SMUAD.PL",
+ SMUAD_VS: "SMUAD.VS",
+ SMUAD_VC: "SMUAD.VC",
+ SMUAD_HI: "SMUAD.HI",
+ SMUAD_LS: "SMUAD.LS",
+ SMUAD_GE: "SMUAD.GE",
+ SMUAD_LT: "SMUAD.LT",
+ SMUAD_GT: "SMUAD.GT",
+ SMUAD_LE: "SMUAD.LE",
+ SMUAD: "SMUAD",
+ SMUAD_ZZ: "SMUAD.ZZ",
+ SMUAD_X_EQ: "SMUAD.X.EQ",
+ SMUAD_X_NE: "SMUAD.X.NE",
+ SMUAD_X_CS: "SMUAD.X.CS",
+ SMUAD_X_CC: "SMUAD.X.CC",
+ SMUAD_X_MI: "SMUAD.X.MI",
+ SMUAD_X_PL: "SMUAD.X.PL",
+ SMUAD_X_VS: "SMUAD.X.VS",
+ SMUAD_X_VC: "SMUAD.X.VC",
+ SMUAD_X_HI: "SMUAD.X.HI",
+ SMUAD_X_LS: "SMUAD.X.LS",
+ SMUAD_X_GE: "SMUAD.X.GE",
+ SMUAD_X_LT: "SMUAD.X.LT",
+ SMUAD_X_GT: "SMUAD.X.GT",
+ SMUAD_X_LE: "SMUAD.X.LE",
+ SMUAD_X: "SMUAD.X",
+ SMUAD_X_ZZ: "SMUAD.X.ZZ",
+ SMULBB_EQ: "SMULBB.EQ",
+ SMULBB_NE: "SMULBB.NE",
+ SMULBB_CS: "SMULBB.CS",
+ SMULBB_CC: "SMULBB.CC",
+ SMULBB_MI: "SMULBB.MI",
+ SMULBB_PL: "SMULBB.PL",
+ SMULBB_VS: "SMULBB.VS",
+ SMULBB_VC: "SMULBB.VC",
+ SMULBB_HI: "SMULBB.HI",
+ SMULBB_LS: "SMULBB.LS",
+ SMULBB_GE: "SMULBB.GE",
+ SMULBB_LT: "SMULBB.LT",
+ SMULBB_GT: "SMULBB.GT",
+ SMULBB_LE: "SMULBB.LE",
+ SMULBB: "SMULBB",
+ SMULBB_ZZ: "SMULBB.ZZ",
+ SMULBT_EQ: "SMULBT.EQ",
+ SMULBT_NE: "SMULBT.NE",
+ SMULBT_CS: "SMULBT.CS",
+ SMULBT_CC: "SMULBT.CC",
+ SMULBT_MI: "SMULBT.MI",
+ SMULBT_PL: "SMULBT.PL",
+ SMULBT_VS: "SMULBT.VS",
+ SMULBT_VC: "SMULBT.VC",
+ SMULBT_HI: "SMULBT.HI",
+ SMULBT_LS: "SMULBT.LS",
+ SMULBT_GE: "SMULBT.GE",
+ SMULBT_LT: "SMULBT.LT",
+ SMULBT_GT: "SMULBT.GT",
+ SMULBT_LE: "SMULBT.LE",
+ SMULBT: "SMULBT",
+ SMULBT_ZZ: "SMULBT.ZZ",
+ SMULTB_EQ: "SMULTB.EQ",
+ SMULTB_NE: "SMULTB.NE",
+ SMULTB_CS: "SMULTB.CS",
+ SMULTB_CC: "SMULTB.CC",
+ SMULTB_MI: "SMULTB.MI",
+ SMULTB_PL: "SMULTB.PL",
+ SMULTB_VS: "SMULTB.VS",
+ SMULTB_VC: "SMULTB.VC",
+ SMULTB_HI: "SMULTB.HI",
+ SMULTB_LS: "SMULTB.LS",
+ SMULTB_GE: "SMULTB.GE",
+ SMULTB_LT: "SMULTB.LT",
+ SMULTB_GT: "SMULTB.GT",
+ SMULTB_LE: "SMULTB.LE",
+ SMULTB: "SMULTB",
+ SMULTB_ZZ: "SMULTB.ZZ",
+ SMULTT_EQ: "SMULTT.EQ",
+ SMULTT_NE: "SMULTT.NE",
+ SMULTT_CS: "SMULTT.CS",
+ SMULTT_CC: "SMULTT.CC",
+ SMULTT_MI: "SMULTT.MI",
+ SMULTT_PL: "SMULTT.PL",
+ SMULTT_VS: "SMULTT.VS",
+ SMULTT_VC: "SMULTT.VC",
+ SMULTT_HI: "SMULTT.HI",
+ SMULTT_LS: "SMULTT.LS",
+ SMULTT_GE: "SMULTT.GE",
+ SMULTT_LT: "SMULTT.LT",
+ SMULTT_GT: "SMULTT.GT",
+ SMULTT_LE: "SMULTT.LE",
+ SMULTT: "SMULTT",
+ SMULTT_ZZ: "SMULTT.ZZ",
+ SMULL_EQ: "SMULL.EQ",
+ SMULL_NE: "SMULL.NE",
+ SMULL_CS: "SMULL.CS",
+ SMULL_CC: "SMULL.CC",
+ SMULL_MI: "SMULL.MI",
+ SMULL_PL: "SMULL.PL",
+ SMULL_VS: "SMULL.VS",
+ SMULL_VC: "SMULL.VC",
+ SMULL_HI: "SMULL.HI",
+ SMULL_LS: "SMULL.LS",
+ SMULL_GE: "SMULL.GE",
+ SMULL_LT: "SMULL.LT",
+ SMULL_GT: "SMULL.GT",
+ SMULL_LE: "SMULL.LE",
+ SMULL: "SMULL",
+ SMULL_ZZ: "SMULL.ZZ",
+ SMULL_S_EQ: "SMULL.S.EQ",
+ SMULL_S_NE: "SMULL.S.NE",
+ SMULL_S_CS: "SMULL.S.CS",
+ SMULL_S_CC: "SMULL.S.CC",
+ SMULL_S_MI: "SMULL.S.MI",
+ SMULL_S_PL: "SMULL.S.PL",
+ SMULL_S_VS: "SMULL.S.VS",
+ SMULL_S_VC: "SMULL.S.VC",
+ SMULL_S_HI: "SMULL.S.HI",
+ SMULL_S_LS: "SMULL.S.LS",
+ SMULL_S_GE: "SMULL.S.GE",
+ SMULL_S_LT: "SMULL.S.LT",
+ SMULL_S_GT: "SMULL.S.GT",
+ SMULL_S_LE: "SMULL.S.LE",
+ SMULL_S: "SMULL.S",
+ SMULL_S_ZZ: "SMULL.S.ZZ",
+ SMULWB_EQ: "SMULWB.EQ",
+ SMULWB_NE: "SMULWB.NE",
+ SMULWB_CS: "SMULWB.CS",
+ SMULWB_CC: "SMULWB.CC",
+ SMULWB_MI: "SMULWB.MI",
+ SMULWB_PL: "SMULWB.PL",
+ SMULWB_VS: "SMULWB.VS",
+ SMULWB_VC: "SMULWB.VC",
+ SMULWB_HI: "SMULWB.HI",
+ SMULWB_LS: "SMULWB.LS",
+ SMULWB_GE: "SMULWB.GE",
+ SMULWB_LT: "SMULWB.LT",
+ SMULWB_GT: "SMULWB.GT",
+ SMULWB_LE: "SMULWB.LE",
+ SMULWB: "SMULWB",
+ SMULWB_ZZ: "SMULWB.ZZ",
+ SMULWT_EQ: "SMULWT.EQ",
+ SMULWT_NE: "SMULWT.NE",
+ SMULWT_CS: "SMULWT.CS",
+ SMULWT_CC: "SMULWT.CC",
+ SMULWT_MI: "SMULWT.MI",
+ SMULWT_PL: "SMULWT.PL",
+ SMULWT_VS: "SMULWT.VS",
+ SMULWT_VC: "SMULWT.VC",
+ SMULWT_HI: "SMULWT.HI",
+ SMULWT_LS: "SMULWT.LS",
+ SMULWT_GE: "SMULWT.GE",
+ SMULWT_LT: "SMULWT.LT",
+ SMULWT_GT: "SMULWT.GT",
+ SMULWT_LE: "SMULWT.LE",
+ SMULWT: "SMULWT",
+ SMULWT_ZZ: "SMULWT.ZZ",
+ SMUSD_EQ: "SMUSD.EQ",
+ SMUSD_NE: "SMUSD.NE",
+ SMUSD_CS: "SMUSD.CS",
+ SMUSD_CC: "SMUSD.CC",
+ SMUSD_MI: "SMUSD.MI",
+ SMUSD_PL: "SMUSD.PL",
+ SMUSD_VS: "SMUSD.VS",
+ SMUSD_VC: "SMUSD.VC",
+ SMUSD_HI: "SMUSD.HI",
+ SMUSD_LS: "SMUSD.LS",
+ SMUSD_GE: "SMUSD.GE",
+ SMUSD_LT: "SMUSD.LT",
+ SMUSD_GT: "SMUSD.GT",
+ SMUSD_LE: "SMUSD.LE",
+ SMUSD: "SMUSD",
+ SMUSD_ZZ: "SMUSD.ZZ",
+ SMUSD_X_EQ: "SMUSD.X.EQ",
+ SMUSD_X_NE: "SMUSD.X.NE",
+ SMUSD_X_CS: "SMUSD.X.CS",
+ SMUSD_X_CC: "SMUSD.X.CC",
+ SMUSD_X_MI: "SMUSD.X.MI",
+ SMUSD_X_PL: "SMUSD.X.PL",
+ SMUSD_X_VS: "SMUSD.X.VS",
+ SMUSD_X_VC: "SMUSD.X.VC",
+ SMUSD_X_HI: "SMUSD.X.HI",
+ SMUSD_X_LS: "SMUSD.X.LS",
+ SMUSD_X_GE: "SMUSD.X.GE",
+ SMUSD_X_LT: "SMUSD.X.LT",
+ SMUSD_X_GT: "SMUSD.X.GT",
+ SMUSD_X_LE: "SMUSD.X.LE",
+ SMUSD_X: "SMUSD.X",
+ SMUSD_X_ZZ: "SMUSD.X.ZZ",
+ SSAT_EQ: "SSAT.EQ",
+ SSAT_NE: "SSAT.NE",
+ SSAT_CS: "SSAT.CS",
+ SSAT_CC: "SSAT.CC",
+ SSAT_MI: "SSAT.MI",
+ SSAT_PL: "SSAT.PL",
+ SSAT_VS: "SSAT.VS",
+ SSAT_VC: "SSAT.VC",
+ SSAT_HI: "SSAT.HI",
+ SSAT_LS: "SSAT.LS",
+ SSAT_GE: "SSAT.GE",
+ SSAT_LT: "SSAT.LT",
+ SSAT_GT: "SSAT.GT",
+ SSAT_LE: "SSAT.LE",
+ SSAT: "SSAT",
+ SSAT_ZZ: "SSAT.ZZ",
+ SSAT16_EQ: "SSAT16.EQ",
+ SSAT16_NE: "SSAT16.NE",
+ SSAT16_CS: "SSAT16.CS",
+ SSAT16_CC: "SSAT16.CC",
+ SSAT16_MI: "SSAT16.MI",
+ SSAT16_PL: "SSAT16.PL",
+ SSAT16_VS: "SSAT16.VS",
+ SSAT16_VC: "SSAT16.VC",
+ SSAT16_HI: "SSAT16.HI",
+ SSAT16_LS: "SSAT16.LS",
+ SSAT16_GE: "SSAT16.GE",
+ SSAT16_LT: "SSAT16.LT",
+ SSAT16_GT: "SSAT16.GT",
+ SSAT16_LE: "SSAT16.LE",
+ SSAT16: "SSAT16",
+ SSAT16_ZZ: "SSAT16.ZZ",
+ SSAX_EQ: "SSAX.EQ",
+ SSAX_NE: "SSAX.NE",
+ SSAX_CS: "SSAX.CS",
+ SSAX_CC: "SSAX.CC",
+ SSAX_MI: "SSAX.MI",
+ SSAX_PL: "SSAX.PL",
+ SSAX_VS: "SSAX.VS",
+ SSAX_VC: "SSAX.VC",
+ SSAX_HI: "SSAX.HI",
+ SSAX_LS: "SSAX.LS",
+ SSAX_GE: "SSAX.GE",
+ SSAX_LT: "SSAX.LT",
+ SSAX_GT: "SSAX.GT",
+ SSAX_LE: "SSAX.LE",
+ SSAX: "SSAX",
+ SSAX_ZZ: "SSAX.ZZ",
+ SSUB16_EQ: "SSUB16.EQ",
+ SSUB16_NE: "SSUB16.NE",
+ SSUB16_CS: "SSUB16.CS",
+ SSUB16_CC: "SSUB16.CC",
+ SSUB16_MI: "SSUB16.MI",
+ SSUB16_PL: "SSUB16.PL",
+ SSUB16_VS: "SSUB16.VS",
+ SSUB16_VC: "SSUB16.VC",
+ SSUB16_HI: "SSUB16.HI",
+ SSUB16_LS: "SSUB16.LS",
+ SSUB16_GE: "SSUB16.GE",
+ SSUB16_LT: "SSUB16.LT",
+ SSUB16_GT: "SSUB16.GT",
+ SSUB16_LE: "SSUB16.LE",
+ SSUB16: "SSUB16",
+ SSUB16_ZZ: "SSUB16.ZZ",
+ SSUB8_EQ: "SSUB8.EQ",
+ SSUB8_NE: "SSUB8.NE",
+ SSUB8_CS: "SSUB8.CS",
+ SSUB8_CC: "SSUB8.CC",
+ SSUB8_MI: "SSUB8.MI",
+ SSUB8_PL: "SSUB8.PL",
+ SSUB8_VS: "SSUB8.VS",
+ SSUB8_VC: "SSUB8.VC",
+ SSUB8_HI: "SSUB8.HI",
+ SSUB8_LS: "SSUB8.LS",
+ SSUB8_GE: "SSUB8.GE",
+ SSUB8_LT: "SSUB8.LT",
+ SSUB8_GT: "SSUB8.GT",
+ SSUB8_LE: "SSUB8.LE",
+ SSUB8: "SSUB8",
+ SSUB8_ZZ: "SSUB8.ZZ",
+ STM_EQ: "STM.EQ",
+ STM_NE: "STM.NE",
+ STM_CS: "STM.CS",
+ STM_CC: "STM.CC",
+ STM_MI: "STM.MI",
+ STM_PL: "STM.PL",
+ STM_VS: "STM.VS",
+ STM_VC: "STM.VC",
+ STM_HI: "STM.HI",
+ STM_LS: "STM.LS",
+ STM_GE: "STM.GE",
+ STM_LT: "STM.LT",
+ STM_GT: "STM.GT",
+ STM_LE: "STM.LE",
+ STM: "STM",
+ STM_ZZ: "STM.ZZ",
+ STMDA_EQ: "STMDA.EQ",
+ STMDA_NE: "STMDA.NE",
+ STMDA_CS: "STMDA.CS",
+ STMDA_CC: "STMDA.CC",
+ STMDA_MI: "STMDA.MI",
+ STMDA_PL: "STMDA.PL",
+ STMDA_VS: "STMDA.VS",
+ STMDA_VC: "STMDA.VC",
+ STMDA_HI: "STMDA.HI",
+ STMDA_LS: "STMDA.LS",
+ STMDA_GE: "STMDA.GE",
+ STMDA_LT: "STMDA.LT",
+ STMDA_GT: "STMDA.GT",
+ STMDA_LE: "STMDA.LE",
+ STMDA: "STMDA",
+ STMDA_ZZ: "STMDA.ZZ",
+ STMDB_EQ: "STMDB.EQ",
+ STMDB_NE: "STMDB.NE",
+ STMDB_CS: "STMDB.CS",
+ STMDB_CC: "STMDB.CC",
+ STMDB_MI: "STMDB.MI",
+ STMDB_PL: "STMDB.PL",
+ STMDB_VS: "STMDB.VS",
+ STMDB_VC: "STMDB.VC",
+ STMDB_HI: "STMDB.HI",
+ STMDB_LS: "STMDB.LS",
+ STMDB_GE: "STMDB.GE",
+ STMDB_LT: "STMDB.LT",
+ STMDB_GT: "STMDB.GT",
+ STMDB_LE: "STMDB.LE",
+ STMDB: "STMDB",
+ STMDB_ZZ: "STMDB.ZZ",
+ STMIB_EQ: "STMIB.EQ",
+ STMIB_NE: "STMIB.NE",
+ STMIB_CS: "STMIB.CS",
+ STMIB_CC: "STMIB.CC",
+ STMIB_MI: "STMIB.MI",
+ STMIB_PL: "STMIB.PL",
+ STMIB_VS: "STMIB.VS",
+ STMIB_VC: "STMIB.VC",
+ STMIB_HI: "STMIB.HI",
+ STMIB_LS: "STMIB.LS",
+ STMIB_GE: "STMIB.GE",
+ STMIB_LT: "STMIB.LT",
+ STMIB_GT: "STMIB.GT",
+ STMIB_LE: "STMIB.LE",
+ STMIB: "STMIB",
+ STMIB_ZZ: "STMIB.ZZ",
+ STR_EQ: "STR.EQ",
+ STR_NE: "STR.NE",
+ STR_CS: "STR.CS",
+ STR_CC: "STR.CC",
+ STR_MI: "STR.MI",
+ STR_PL: "STR.PL",
+ STR_VS: "STR.VS",
+ STR_VC: "STR.VC",
+ STR_HI: "STR.HI",
+ STR_LS: "STR.LS",
+ STR_GE: "STR.GE",
+ STR_LT: "STR.LT",
+ STR_GT: "STR.GT",
+ STR_LE: "STR.LE",
+ STR: "STR",
+ STR_ZZ: "STR.ZZ",
+ STRB_EQ: "STRB.EQ",
+ STRB_NE: "STRB.NE",
+ STRB_CS: "STRB.CS",
+ STRB_CC: "STRB.CC",
+ STRB_MI: "STRB.MI",
+ STRB_PL: "STRB.PL",
+ STRB_VS: "STRB.VS",
+ STRB_VC: "STRB.VC",
+ STRB_HI: "STRB.HI",
+ STRB_LS: "STRB.LS",
+ STRB_GE: "STRB.GE",
+ STRB_LT: "STRB.LT",
+ STRB_GT: "STRB.GT",
+ STRB_LE: "STRB.LE",
+ STRB: "STRB",
+ STRB_ZZ: "STRB.ZZ",
+ STRBT_EQ: "STRBT.EQ",
+ STRBT_NE: "STRBT.NE",
+ STRBT_CS: "STRBT.CS",
+ STRBT_CC: "STRBT.CC",
+ STRBT_MI: "STRBT.MI",
+ STRBT_PL: "STRBT.PL",
+ STRBT_VS: "STRBT.VS",
+ STRBT_VC: "STRBT.VC",
+ STRBT_HI: "STRBT.HI",
+ STRBT_LS: "STRBT.LS",
+ STRBT_GE: "STRBT.GE",
+ STRBT_LT: "STRBT.LT",
+ STRBT_GT: "STRBT.GT",
+ STRBT_LE: "STRBT.LE",
+ STRBT: "STRBT",
+ STRBT_ZZ: "STRBT.ZZ",
+ STRD_EQ: "STRD.EQ",
+ STRD_NE: "STRD.NE",
+ STRD_CS: "STRD.CS",
+ STRD_CC: "STRD.CC",
+ STRD_MI: "STRD.MI",
+ STRD_PL: "STRD.PL",
+ STRD_VS: "STRD.VS",
+ STRD_VC: "STRD.VC",
+ STRD_HI: "STRD.HI",
+ STRD_LS: "STRD.LS",
+ STRD_GE: "STRD.GE",
+ STRD_LT: "STRD.LT",
+ STRD_GT: "STRD.GT",
+ STRD_LE: "STRD.LE",
+ STRD: "STRD",
+ STRD_ZZ: "STRD.ZZ",
+ STREX_EQ: "STREX.EQ",
+ STREX_NE: "STREX.NE",
+ STREX_CS: "STREX.CS",
+ STREX_CC: "STREX.CC",
+ STREX_MI: "STREX.MI",
+ STREX_PL: "STREX.PL",
+ STREX_VS: "STREX.VS",
+ STREX_VC: "STREX.VC",
+ STREX_HI: "STREX.HI",
+ STREX_LS: "STREX.LS",
+ STREX_GE: "STREX.GE",
+ STREX_LT: "STREX.LT",
+ STREX_GT: "STREX.GT",
+ STREX_LE: "STREX.LE",
+ STREX: "STREX",
+ STREX_ZZ: "STREX.ZZ",
+ STREXB_EQ: "STREXB.EQ",
+ STREXB_NE: "STREXB.NE",
+ STREXB_CS: "STREXB.CS",
+ STREXB_CC: "STREXB.CC",
+ STREXB_MI: "STREXB.MI",
+ STREXB_PL: "STREXB.PL",
+ STREXB_VS: "STREXB.VS",
+ STREXB_VC: "STREXB.VC",
+ STREXB_HI: "STREXB.HI",
+ STREXB_LS: "STREXB.LS",
+ STREXB_GE: "STREXB.GE",
+ STREXB_LT: "STREXB.LT",
+ STREXB_GT: "STREXB.GT",
+ STREXB_LE: "STREXB.LE",
+ STREXB: "STREXB",
+ STREXB_ZZ: "STREXB.ZZ",
+ STREXD_EQ: "STREXD.EQ",
+ STREXD_NE: "STREXD.NE",
+ STREXD_CS: "STREXD.CS",
+ STREXD_CC: "STREXD.CC",
+ STREXD_MI: "STREXD.MI",
+ STREXD_PL: "STREXD.PL",
+ STREXD_VS: "STREXD.VS",
+ STREXD_VC: "STREXD.VC",
+ STREXD_HI: "STREXD.HI",
+ STREXD_LS: "STREXD.LS",
+ STREXD_GE: "STREXD.GE",
+ STREXD_LT: "STREXD.LT",
+ STREXD_GT: "STREXD.GT",
+ STREXD_LE: "STREXD.LE",
+ STREXD: "STREXD",
+ STREXD_ZZ: "STREXD.ZZ",
+ STREXH_EQ: "STREXH.EQ",
+ STREXH_NE: "STREXH.NE",
+ STREXH_CS: "STREXH.CS",
+ STREXH_CC: "STREXH.CC",
+ STREXH_MI: "STREXH.MI",
+ STREXH_PL: "STREXH.PL",
+ STREXH_VS: "STREXH.VS",
+ STREXH_VC: "STREXH.VC",
+ STREXH_HI: "STREXH.HI",
+ STREXH_LS: "STREXH.LS",
+ STREXH_GE: "STREXH.GE",
+ STREXH_LT: "STREXH.LT",
+ STREXH_GT: "STREXH.GT",
+ STREXH_LE: "STREXH.LE",
+ STREXH: "STREXH",
+ STREXH_ZZ: "STREXH.ZZ",
+ STRH_EQ: "STRH.EQ",
+ STRH_NE: "STRH.NE",
+ STRH_CS: "STRH.CS",
+ STRH_CC: "STRH.CC",
+ STRH_MI: "STRH.MI",
+ STRH_PL: "STRH.PL",
+ STRH_VS: "STRH.VS",
+ STRH_VC: "STRH.VC",
+ STRH_HI: "STRH.HI",
+ STRH_LS: "STRH.LS",
+ STRH_GE: "STRH.GE",
+ STRH_LT: "STRH.LT",
+ STRH_GT: "STRH.GT",
+ STRH_LE: "STRH.LE",
+ STRH: "STRH",
+ STRH_ZZ: "STRH.ZZ",
+ STRHT_EQ: "STRHT.EQ",
+ STRHT_NE: "STRHT.NE",
+ STRHT_CS: "STRHT.CS",
+ STRHT_CC: "STRHT.CC",
+ STRHT_MI: "STRHT.MI",
+ STRHT_PL: "STRHT.PL",
+ STRHT_VS: "STRHT.VS",
+ STRHT_VC: "STRHT.VC",
+ STRHT_HI: "STRHT.HI",
+ STRHT_LS: "STRHT.LS",
+ STRHT_GE: "STRHT.GE",
+ STRHT_LT: "STRHT.LT",
+ STRHT_GT: "STRHT.GT",
+ STRHT_LE: "STRHT.LE",
+ STRHT: "STRHT",
+ STRHT_ZZ: "STRHT.ZZ",
+ STRT_EQ: "STRT.EQ",
+ STRT_NE: "STRT.NE",
+ STRT_CS: "STRT.CS",
+ STRT_CC: "STRT.CC",
+ STRT_MI: "STRT.MI",
+ STRT_PL: "STRT.PL",
+ STRT_VS: "STRT.VS",
+ STRT_VC: "STRT.VC",
+ STRT_HI: "STRT.HI",
+ STRT_LS: "STRT.LS",
+ STRT_GE: "STRT.GE",
+ STRT_LT: "STRT.LT",
+ STRT_GT: "STRT.GT",
+ STRT_LE: "STRT.LE",
+ STRT: "STRT",
+ STRT_ZZ: "STRT.ZZ",
+ SUB_EQ: "SUB.EQ",
+ SUB_NE: "SUB.NE",
+ SUB_CS: "SUB.CS",
+ SUB_CC: "SUB.CC",
+ SUB_MI: "SUB.MI",
+ SUB_PL: "SUB.PL",
+ SUB_VS: "SUB.VS",
+ SUB_VC: "SUB.VC",
+ SUB_HI: "SUB.HI",
+ SUB_LS: "SUB.LS",
+ SUB_GE: "SUB.GE",
+ SUB_LT: "SUB.LT",
+ SUB_GT: "SUB.GT",
+ SUB_LE: "SUB.LE",
+ SUB: "SUB",
+ SUB_ZZ: "SUB.ZZ",
+ SUB_S_EQ: "SUB.S.EQ",
+ SUB_S_NE: "SUB.S.NE",
+ SUB_S_CS: "SUB.S.CS",
+ SUB_S_CC: "SUB.S.CC",
+ SUB_S_MI: "SUB.S.MI",
+ SUB_S_PL: "SUB.S.PL",
+ SUB_S_VS: "SUB.S.VS",
+ SUB_S_VC: "SUB.S.VC",
+ SUB_S_HI: "SUB.S.HI",
+ SUB_S_LS: "SUB.S.LS",
+ SUB_S_GE: "SUB.S.GE",
+ SUB_S_LT: "SUB.S.LT",
+ SUB_S_GT: "SUB.S.GT",
+ SUB_S_LE: "SUB.S.LE",
+ SUB_S: "SUB.S",
+ SUB_S_ZZ: "SUB.S.ZZ",
+ SVC_EQ: "SVC.EQ",
+ SVC_NE: "SVC.NE",
+ SVC_CS: "SVC.CS",
+ SVC_CC: "SVC.CC",
+ SVC_MI: "SVC.MI",
+ SVC_PL: "SVC.PL",
+ SVC_VS: "SVC.VS",
+ SVC_VC: "SVC.VC",
+ SVC_HI: "SVC.HI",
+ SVC_LS: "SVC.LS",
+ SVC_GE: "SVC.GE",
+ SVC_LT: "SVC.LT",
+ SVC_GT: "SVC.GT",
+ SVC_LE: "SVC.LE",
+ SVC: "SVC",
+ SVC_ZZ: "SVC.ZZ",
+ SWP_EQ: "SWP.EQ",
+ SWP_NE: "SWP.NE",
+ SWP_CS: "SWP.CS",
+ SWP_CC: "SWP.CC",
+ SWP_MI: "SWP.MI",
+ SWP_PL: "SWP.PL",
+ SWP_VS: "SWP.VS",
+ SWP_VC: "SWP.VC",
+ SWP_HI: "SWP.HI",
+ SWP_LS: "SWP.LS",
+ SWP_GE: "SWP.GE",
+ SWP_LT: "SWP.LT",
+ SWP_GT: "SWP.GT",
+ SWP_LE: "SWP.LE",
+ SWP: "SWP",
+ SWP_ZZ: "SWP.ZZ",
+ SWP_B_EQ: "SWP.B.EQ",
+ SWP_B_NE: "SWP.B.NE",
+ SWP_B_CS: "SWP.B.CS",
+ SWP_B_CC: "SWP.B.CC",
+ SWP_B_MI: "SWP.B.MI",
+ SWP_B_PL: "SWP.B.PL",
+ SWP_B_VS: "SWP.B.VS",
+ SWP_B_VC: "SWP.B.VC",
+ SWP_B_HI: "SWP.B.HI",
+ SWP_B_LS: "SWP.B.LS",
+ SWP_B_GE: "SWP.B.GE",
+ SWP_B_LT: "SWP.B.LT",
+ SWP_B_GT: "SWP.B.GT",
+ SWP_B_LE: "SWP.B.LE",
+ SWP_B: "SWP.B",
+ SWP_B_ZZ: "SWP.B.ZZ",
+ SXTAB_EQ: "SXTAB.EQ",
+ SXTAB_NE: "SXTAB.NE",
+ SXTAB_CS: "SXTAB.CS",
+ SXTAB_CC: "SXTAB.CC",
+ SXTAB_MI: "SXTAB.MI",
+ SXTAB_PL: "SXTAB.PL",
+ SXTAB_VS: "SXTAB.VS",
+ SXTAB_VC: "SXTAB.VC",
+ SXTAB_HI: "SXTAB.HI",
+ SXTAB_LS: "SXTAB.LS",
+ SXTAB_GE: "SXTAB.GE",
+ SXTAB_LT: "SXTAB.LT",
+ SXTAB_GT: "SXTAB.GT",
+ SXTAB_LE: "SXTAB.LE",
+ SXTAB: "SXTAB",
+ SXTAB_ZZ: "SXTAB.ZZ",
+ SXTAB16_EQ: "SXTAB16.EQ",
+ SXTAB16_NE: "SXTAB16.NE",
+ SXTAB16_CS: "SXTAB16.CS",
+ SXTAB16_CC: "SXTAB16.CC",
+ SXTAB16_MI: "SXTAB16.MI",
+ SXTAB16_PL: "SXTAB16.PL",
+ SXTAB16_VS: "SXTAB16.VS",
+ SXTAB16_VC: "SXTAB16.VC",
+ SXTAB16_HI: "SXTAB16.HI",
+ SXTAB16_LS: "SXTAB16.LS",
+ SXTAB16_GE: "SXTAB16.GE",
+ SXTAB16_LT: "SXTAB16.LT",
+ SXTAB16_GT: "SXTAB16.GT",
+ SXTAB16_LE: "SXTAB16.LE",
+ SXTAB16: "SXTAB16",
+ SXTAB16_ZZ: "SXTAB16.ZZ",
+ SXTAH_EQ: "SXTAH.EQ",
+ SXTAH_NE: "SXTAH.NE",
+ SXTAH_CS: "SXTAH.CS",
+ SXTAH_CC: "SXTAH.CC",
+ SXTAH_MI: "SXTAH.MI",
+ SXTAH_PL: "SXTAH.PL",
+ SXTAH_VS: "SXTAH.VS",
+ SXTAH_VC: "SXTAH.VC",
+ SXTAH_HI: "SXTAH.HI",
+ SXTAH_LS: "SXTAH.LS",
+ SXTAH_GE: "SXTAH.GE",
+ SXTAH_LT: "SXTAH.LT",
+ SXTAH_GT: "SXTAH.GT",
+ SXTAH_LE: "SXTAH.LE",
+ SXTAH: "SXTAH",
+ SXTAH_ZZ: "SXTAH.ZZ",
+ SXTB_EQ: "SXTB.EQ",
+ SXTB_NE: "SXTB.NE",
+ SXTB_CS: "SXTB.CS",
+ SXTB_CC: "SXTB.CC",
+ SXTB_MI: "SXTB.MI",
+ SXTB_PL: "SXTB.PL",
+ SXTB_VS: "SXTB.VS",
+ SXTB_VC: "SXTB.VC",
+ SXTB_HI: "SXTB.HI",
+ SXTB_LS: "SXTB.LS",
+ SXTB_GE: "SXTB.GE",
+ SXTB_LT: "SXTB.LT",
+ SXTB_GT: "SXTB.GT",
+ SXTB_LE: "SXTB.LE",
+ SXTB: "SXTB",
+ SXTB_ZZ: "SXTB.ZZ",
+ SXTB16_EQ: "SXTB16.EQ",
+ SXTB16_NE: "SXTB16.NE",
+ SXTB16_CS: "SXTB16.CS",
+ SXTB16_CC: "SXTB16.CC",
+ SXTB16_MI: "SXTB16.MI",
+ SXTB16_PL: "SXTB16.PL",
+ SXTB16_VS: "SXTB16.VS",
+ SXTB16_VC: "SXTB16.VC",
+ SXTB16_HI: "SXTB16.HI",
+ SXTB16_LS: "SXTB16.LS",
+ SXTB16_GE: "SXTB16.GE",
+ SXTB16_LT: "SXTB16.LT",
+ SXTB16_GT: "SXTB16.GT",
+ SXTB16_LE: "SXTB16.LE",
+ SXTB16: "SXTB16",
+ SXTB16_ZZ: "SXTB16.ZZ",
+ SXTH_EQ: "SXTH.EQ",
+ SXTH_NE: "SXTH.NE",
+ SXTH_CS: "SXTH.CS",
+ SXTH_CC: "SXTH.CC",
+ SXTH_MI: "SXTH.MI",
+ SXTH_PL: "SXTH.PL",
+ SXTH_VS: "SXTH.VS",
+ SXTH_VC: "SXTH.VC",
+ SXTH_HI: "SXTH.HI",
+ SXTH_LS: "SXTH.LS",
+ SXTH_GE: "SXTH.GE",
+ SXTH_LT: "SXTH.LT",
+ SXTH_GT: "SXTH.GT",
+ SXTH_LE: "SXTH.LE",
+ SXTH: "SXTH",
+ SXTH_ZZ: "SXTH.ZZ",
+ TEQ_EQ: "TEQ.EQ",
+ TEQ_NE: "TEQ.NE",
+ TEQ_CS: "TEQ.CS",
+ TEQ_CC: "TEQ.CC",
+ TEQ_MI: "TEQ.MI",
+ TEQ_PL: "TEQ.PL",
+ TEQ_VS: "TEQ.VS",
+ TEQ_VC: "TEQ.VC",
+ TEQ_HI: "TEQ.HI",
+ TEQ_LS: "TEQ.LS",
+ TEQ_GE: "TEQ.GE",
+ TEQ_LT: "TEQ.LT",
+ TEQ_GT: "TEQ.GT",
+ TEQ_LE: "TEQ.LE",
+ TEQ: "TEQ",
+ TEQ_ZZ: "TEQ.ZZ",
+ TST_EQ: "TST.EQ",
+ TST_NE: "TST.NE",
+ TST_CS: "TST.CS",
+ TST_CC: "TST.CC",
+ TST_MI: "TST.MI",
+ TST_PL: "TST.PL",
+ TST_VS: "TST.VS",
+ TST_VC: "TST.VC",
+ TST_HI: "TST.HI",
+ TST_LS: "TST.LS",
+ TST_GE: "TST.GE",
+ TST_LT: "TST.LT",
+ TST_GT: "TST.GT",
+ TST_LE: "TST.LE",
+ TST: "TST",
+ TST_ZZ: "TST.ZZ",
+ UADD16_EQ: "UADD16.EQ",
+ UADD16_NE: "UADD16.NE",
+ UADD16_CS: "UADD16.CS",
+ UADD16_CC: "UADD16.CC",
+ UADD16_MI: "UADD16.MI",
+ UADD16_PL: "UADD16.PL",
+ UADD16_VS: "UADD16.VS",
+ UADD16_VC: "UADD16.VC",
+ UADD16_HI: "UADD16.HI",
+ UADD16_LS: "UADD16.LS",
+ UADD16_GE: "UADD16.GE",
+ UADD16_LT: "UADD16.LT",
+ UADD16_GT: "UADD16.GT",
+ UADD16_LE: "UADD16.LE",
+ UADD16: "UADD16",
+ UADD16_ZZ: "UADD16.ZZ",
+ UADD8_EQ: "UADD8.EQ",
+ UADD8_NE: "UADD8.NE",
+ UADD8_CS: "UADD8.CS",
+ UADD8_CC: "UADD8.CC",
+ UADD8_MI: "UADD8.MI",
+ UADD8_PL: "UADD8.PL",
+ UADD8_VS: "UADD8.VS",
+ UADD8_VC: "UADD8.VC",
+ UADD8_HI: "UADD8.HI",
+ UADD8_LS: "UADD8.LS",
+ UADD8_GE: "UADD8.GE",
+ UADD8_LT: "UADD8.LT",
+ UADD8_GT: "UADD8.GT",
+ UADD8_LE: "UADD8.LE",
+ UADD8: "UADD8",
+ UADD8_ZZ: "UADD8.ZZ",
+ UASX_EQ: "UASX.EQ",
+ UASX_NE: "UASX.NE",
+ UASX_CS: "UASX.CS",
+ UASX_CC: "UASX.CC",
+ UASX_MI: "UASX.MI",
+ UASX_PL: "UASX.PL",
+ UASX_VS: "UASX.VS",
+ UASX_VC: "UASX.VC",
+ UASX_HI: "UASX.HI",
+ UASX_LS: "UASX.LS",
+ UASX_GE: "UASX.GE",
+ UASX_LT: "UASX.LT",
+ UASX_GT: "UASX.GT",
+ UASX_LE: "UASX.LE",
+ UASX: "UASX",
+ UASX_ZZ: "UASX.ZZ",
+ UBFX_EQ: "UBFX.EQ",
+ UBFX_NE: "UBFX.NE",
+ UBFX_CS: "UBFX.CS",
+ UBFX_CC: "UBFX.CC",
+ UBFX_MI: "UBFX.MI",
+ UBFX_PL: "UBFX.PL",
+ UBFX_VS: "UBFX.VS",
+ UBFX_VC: "UBFX.VC",
+ UBFX_HI: "UBFX.HI",
+ UBFX_LS: "UBFX.LS",
+ UBFX_GE: "UBFX.GE",
+ UBFX_LT: "UBFX.LT",
+ UBFX_GT: "UBFX.GT",
+ UBFX_LE: "UBFX.LE",
+ UBFX: "UBFX",
+ UBFX_ZZ: "UBFX.ZZ",
+ UHADD16_EQ: "UHADD16.EQ",
+ UHADD16_NE: "UHADD16.NE",
+ UHADD16_CS: "UHADD16.CS",
+ UHADD16_CC: "UHADD16.CC",
+ UHADD16_MI: "UHADD16.MI",
+ UHADD16_PL: "UHADD16.PL",
+ UHADD16_VS: "UHADD16.VS",
+ UHADD16_VC: "UHADD16.VC",
+ UHADD16_HI: "UHADD16.HI",
+ UHADD16_LS: "UHADD16.LS",
+ UHADD16_GE: "UHADD16.GE",
+ UHADD16_LT: "UHADD16.LT",
+ UHADD16_GT: "UHADD16.GT",
+ UHADD16_LE: "UHADD16.LE",
+ UHADD16: "UHADD16",
+ UHADD16_ZZ: "UHADD16.ZZ",
+ UHADD8_EQ: "UHADD8.EQ",
+ UHADD8_NE: "UHADD8.NE",
+ UHADD8_CS: "UHADD8.CS",
+ UHADD8_CC: "UHADD8.CC",
+ UHADD8_MI: "UHADD8.MI",
+ UHADD8_PL: "UHADD8.PL",
+ UHADD8_VS: "UHADD8.VS",
+ UHADD8_VC: "UHADD8.VC",
+ UHADD8_HI: "UHADD8.HI",
+ UHADD8_LS: "UHADD8.LS",
+ UHADD8_GE: "UHADD8.GE",
+ UHADD8_LT: "UHADD8.LT",
+ UHADD8_GT: "UHADD8.GT",
+ UHADD8_LE: "UHADD8.LE",
+ UHADD8: "UHADD8",
+ UHADD8_ZZ: "UHADD8.ZZ",
+ UHASX_EQ: "UHASX.EQ",
+ UHASX_NE: "UHASX.NE",
+ UHASX_CS: "UHASX.CS",
+ UHASX_CC: "UHASX.CC",
+ UHASX_MI: "UHASX.MI",
+ UHASX_PL: "UHASX.PL",
+ UHASX_VS: "UHASX.VS",
+ UHASX_VC: "UHASX.VC",
+ UHASX_HI: "UHASX.HI",
+ UHASX_LS: "UHASX.LS",
+ UHASX_GE: "UHASX.GE",
+ UHASX_LT: "UHASX.LT",
+ UHASX_GT: "UHASX.GT",
+ UHASX_LE: "UHASX.LE",
+ UHASX: "UHASX",
+ UHASX_ZZ: "UHASX.ZZ",
+ UHSAX_EQ: "UHSAX.EQ",
+ UHSAX_NE: "UHSAX.NE",
+ UHSAX_CS: "UHSAX.CS",
+ UHSAX_CC: "UHSAX.CC",
+ UHSAX_MI: "UHSAX.MI",
+ UHSAX_PL: "UHSAX.PL",
+ UHSAX_VS: "UHSAX.VS",
+ UHSAX_VC: "UHSAX.VC",
+ UHSAX_HI: "UHSAX.HI",
+ UHSAX_LS: "UHSAX.LS",
+ UHSAX_GE: "UHSAX.GE",
+ UHSAX_LT: "UHSAX.LT",
+ UHSAX_GT: "UHSAX.GT",
+ UHSAX_LE: "UHSAX.LE",
+ UHSAX: "UHSAX",
+ UHSAX_ZZ: "UHSAX.ZZ",
+ UHSUB16_EQ: "UHSUB16.EQ",
+ UHSUB16_NE: "UHSUB16.NE",
+ UHSUB16_CS: "UHSUB16.CS",
+ UHSUB16_CC: "UHSUB16.CC",
+ UHSUB16_MI: "UHSUB16.MI",
+ UHSUB16_PL: "UHSUB16.PL",
+ UHSUB16_VS: "UHSUB16.VS",
+ UHSUB16_VC: "UHSUB16.VC",
+ UHSUB16_HI: "UHSUB16.HI",
+ UHSUB16_LS: "UHSUB16.LS",
+ UHSUB16_GE: "UHSUB16.GE",
+ UHSUB16_LT: "UHSUB16.LT",
+ UHSUB16_GT: "UHSUB16.GT",
+ UHSUB16_LE: "UHSUB16.LE",
+ UHSUB16: "UHSUB16",
+ UHSUB16_ZZ: "UHSUB16.ZZ",
+ UHSUB8_EQ: "UHSUB8.EQ",
+ UHSUB8_NE: "UHSUB8.NE",
+ UHSUB8_CS: "UHSUB8.CS",
+ UHSUB8_CC: "UHSUB8.CC",
+ UHSUB8_MI: "UHSUB8.MI",
+ UHSUB8_PL: "UHSUB8.PL",
+ UHSUB8_VS: "UHSUB8.VS",
+ UHSUB8_VC: "UHSUB8.VC",
+ UHSUB8_HI: "UHSUB8.HI",
+ UHSUB8_LS: "UHSUB8.LS",
+ UHSUB8_GE: "UHSUB8.GE",
+ UHSUB8_LT: "UHSUB8.LT",
+ UHSUB8_GT: "UHSUB8.GT",
+ UHSUB8_LE: "UHSUB8.LE",
+ UHSUB8: "UHSUB8",
+ UHSUB8_ZZ: "UHSUB8.ZZ",
+ UMAAL_EQ: "UMAAL.EQ",
+ UMAAL_NE: "UMAAL.NE",
+ UMAAL_CS: "UMAAL.CS",
+ UMAAL_CC: "UMAAL.CC",
+ UMAAL_MI: "UMAAL.MI",
+ UMAAL_PL: "UMAAL.PL",
+ UMAAL_VS: "UMAAL.VS",
+ UMAAL_VC: "UMAAL.VC",
+ UMAAL_HI: "UMAAL.HI",
+ UMAAL_LS: "UMAAL.LS",
+ UMAAL_GE: "UMAAL.GE",
+ UMAAL_LT: "UMAAL.LT",
+ UMAAL_GT: "UMAAL.GT",
+ UMAAL_LE: "UMAAL.LE",
+ UMAAL: "UMAAL",
+ UMAAL_ZZ: "UMAAL.ZZ",
+ UMLAL_EQ: "UMLAL.EQ",
+ UMLAL_NE: "UMLAL.NE",
+ UMLAL_CS: "UMLAL.CS",
+ UMLAL_CC: "UMLAL.CC",
+ UMLAL_MI: "UMLAL.MI",
+ UMLAL_PL: "UMLAL.PL",
+ UMLAL_VS: "UMLAL.VS",
+ UMLAL_VC: "UMLAL.VC",
+ UMLAL_HI: "UMLAL.HI",
+ UMLAL_LS: "UMLAL.LS",
+ UMLAL_GE: "UMLAL.GE",
+ UMLAL_LT: "UMLAL.LT",
+ UMLAL_GT: "UMLAL.GT",
+ UMLAL_LE: "UMLAL.LE",
+ UMLAL: "UMLAL",
+ UMLAL_ZZ: "UMLAL.ZZ",
+ UMLAL_S_EQ: "UMLAL.S.EQ",
+ UMLAL_S_NE: "UMLAL.S.NE",
+ UMLAL_S_CS: "UMLAL.S.CS",
+ UMLAL_S_CC: "UMLAL.S.CC",
+ UMLAL_S_MI: "UMLAL.S.MI",
+ UMLAL_S_PL: "UMLAL.S.PL",
+ UMLAL_S_VS: "UMLAL.S.VS",
+ UMLAL_S_VC: "UMLAL.S.VC",
+ UMLAL_S_HI: "UMLAL.S.HI",
+ UMLAL_S_LS: "UMLAL.S.LS",
+ UMLAL_S_GE: "UMLAL.S.GE",
+ UMLAL_S_LT: "UMLAL.S.LT",
+ UMLAL_S_GT: "UMLAL.S.GT",
+ UMLAL_S_LE: "UMLAL.S.LE",
+ UMLAL_S: "UMLAL.S",
+ UMLAL_S_ZZ: "UMLAL.S.ZZ",
+ UMULL_EQ: "UMULL.EQ",
+ UMULL_NE: "UMULL.NE",
+ UMULL_CS: "UMULL.CS",
+ UMULL_CC: "UMULL.CC",
+ UMULL_MI: "UMULL.MI",
+ UMULL_PL: "UMULL.PL",
+ UMULL_VS: "UMULL.VS",
+ UMULL_VC: "UMULL.VC",
+ UMULL_HI: "UMULL.HI",
+ UMULL_LS: "UMULL.LS",
+ UMULL_GE: "UMULL.GE",
+ UMULL_LT: "UMULL.LT",
+ UMULL_GT: "UMULL.GT",
+ UMULL_LE: "UMULL.LE",
+ UMULL: "UMULL",
+ UMULL_ZZ: "UMULL.ZZ",
+ UMULL_S_EQ: "UMULL.S.EQ",
+ UMULL_S_NE: "UMULL.S.NE",
+ UMULL_S_CS: "UMULL.S.CS",
+ UMULL_S_CC: "UMULL.S.CC",
+ UMULL_S_MI: "UMULL.S.MI",
+ UMULL_S_PL: "UMULL.S.PL",
+ UMULL_S_VS: "UMULL.S.VS",
+ UMULL_S_VC: "UMULL.S.VC",
+ UMULL_S_HI: "UMULL.S.HI",
+ UMULL_S_LS: "UMULL.S.LS",
+ UMULL_S_GE: "UMULL.S.GE",
+ UMULL_S_LT: "UMULL.S.LT",
+ UMULL_S_GT: "UMULL.S.GT",
+ UMULL_S_LE: "UMULL.S.LE",
+ UMULL_S: "UMULL.S",
+ UMULL_S_ZZ: "UMULL.S.ZZ",
+ UNDEF: "UNDEF",
+ UQADD16_EQ: "UQADD16.EQ",
+ UQADD16_NE: "UQADD16.NE",
+ UQADD16_CS: "UQADD16.CS",
+ UQADD16_CC: "UQADD16.CC",
+ UQADD16_MI: "UQADD16.MI",
+ UQADD16_PL: "UQADD16.PL",
+ UQADD16_VS: "UQADD16.VS",
+ UQADD16_VC: "UQADD16.VC",
+ UQADD16_HI: "UQADD16.HI",
+ UQADD16_LS: "UQADD16.LS",
+ UQADD16_GE: "UQADD16.GE",
+ UQADD16_LT: "UQADD16.LT",
+ UQADD16_GT: "UQADD16.GT",
+ UQADD16_LE: "UQADD16.LE",
+ UQADD16: "UQADD16",
+ UQADD16_ZZ: "UQADD16.ZZ",
+ UQADD8_EQ: "UQADD8.EQ",
+ UQADD8_NE: "UQADD8.NE",
+ UQADD8_CS: "UQADD8.CS",
+ UQADD8_CC: "UQADD8.CC",
+ UQADD8_MI: "UQADD8.MI",
+ UQADD8_PL: "UQADD8.PL",
+ UQADD8_VS: "UQADD8.VS",
+ UQADD8_VC: "UQADD8.VC",
+ UQADD8_HI: "UQADD8.HI",
+ UQADD8_LS: "UQADD8.LS",
+ UQADD8_GE: "UQADD8.GE",
+ UQADD8_LT: "UQADD8.LT",
+ UQADD8_GT: "UQADD8.GT",
+ UQADD8_LE: "UQADD8.LE",
+ UQADD8: "UQADD8",
+ UQADD8_ZZ: "UQADD8.ZZ",
+ UQASX_EQ: "UQASX.EQ",
+ UQASX_NE: "UQASX.NE",
+ UQASX_CS: "UQASX.CS",
+ UQASX_CC: "UQASX.CC",
+ UQASX_MI: "UQASX.MI",
+ UQASX_PL: "UQASX.PL",
+ UQASX_VS: "UQASX.VS",
+ UQASX_VC: "UQASX.VC",
+ UQASX_HI: "UQASX.HI",
+ UQASX_LS: "UQASX.LS",
+ UQASX_GE: "UQASX.GE",
+ UQASX_LT: "UQASX.LT",
+ UQASX_GT: "UQASX.GT",
+ UQASX_LE: "UQASX.LE",
+ UQASX: "UQASX",
+ UQASX_ZZ: "UQASX.ZZ",
+ UQSAX_EQ: "UQSAX.EQ",
+ UQSAX_NE: "UQSAX.NE",
+ UQSAX_CS: "UQSAX.CS",
+ UQSAX_CC: "UQSAX.CC",
+ UQSAX_MI: "UQSAX.MI",
+ UQSAX_PL: "UQSAX.PL",
+ UQSAX_VS: "UQSAX.VS",
+ UQSAX_VC: "UQSAX.VC",
+ UQSAX_HI: "UQSAX.HI",
+ UQSAX_LS: "UQSAX.LS",
+ UQSAX_GE: "UQSAX.GE",
+ UQSAX_LT: "UQSAX.LT",
+ UQSAX_GT: "UQSAX.GT",
+ UQSAX_LE: "UQSAX.LE",
+ UQSAX: "UQSAX",
+ UQSAX_ZZ: "UQSAX.ZZ",
+ UQSUB16_EQ: "UQSUB16.EQ",
+ UQSUB16_NE: "UQSUB16.NE",
+ UQSUB16_CS: "UQSUB16.CS",
+ UQSUB16_CC: "UQSUB16.CC",
+ UQSUB16_MI: "UQSUB16.MI",
+ UQSUB16_PL: "UQSUB16.PL",
+ UQSUB16_VS: "UQSUB16.VS",
+ UQSUB16_VC: "UQSUB16.VC",
+ UQSUB16_HI: "UQSUB16.HI",
+ UQSUB16_LS: "UQSUB16.LS",
+ UQSUB16_GE: "UQSUB16.GE",
+ UQSUB16_LT: "UQSUB16.LT",
+ UQSUB16_GT: "UQSUB16.GT",
+ UQSUB16_LE: "UQSUB16.LE",
+ UQSUB16: "UQSUB16",
+ UQSUB16_ZZ: "UQSUB16.ZZ",
+ UQSUB8_EQ: "UQSUB8.EQ",
+ UQSUB8_NE: "UQSUB8.NE",
+ UQSUB8_CS: "UQSUB8.CS",
+ UQSUB8_CC: "UQSUB8.CC",
+ UQSUB8_MI: "UQSUB8.MI",
+ UQSUB8_PL: "UQSUB8.PL",
+ UQSUB8_VS: "UQSUB8.VS",
+ UQSUB8_VC: "UQSUB8.VC",
+ UQSUB8_HI: "UQSUB8.HI",
+ UQSUB8_LS: "UQSUB8.LS",
+ UQSUB8_GE: "UQSUB8.GE",
+ UQSUB8_LT: "UQSUB8.LT",
+ UQSUB8_GT: "UQSUB8.GT",
+ UQSUB8_LE: "UQSUB8.LE",
+ UQSUB8: "UQSUB8",
+ UQSUB8_ZZ: "UQSUB8.ZZ",
+ USAD8_EQ: "USAD8.EQ",
+ USAD8_NE: "USAD8.NE",
+ USAD8_CS: "USAD8.CS",
+ USAD8_CC: "USAD8.CC",
+ USAD8_MI: "USAD8.MI",
+ USAD8_PL: "USAD8.PL",
+ USAD8_VS: "USAD8.VS",
+ USAD8_VC: "USAD8.VC",
+ USAD8_HI: "USAD8.HI",
+ USAD8_LS: "USAD8.LS",
+ USAD8_GE: "USAD8.GE",
+ USAD8_LT: "USAD8.LT",
+ USAD8_GT: "USAD8.GT",
+ USAD8_LE: "USAD8.LE",
+ USAD8: "USAD8",
+ USAD8_ZZ: "USAD8.ZZ",
+ USADA8_EQ: "USADA8.EQ",
+ USADA8_NE: "USADA8.NE",
+ USADA8_CS: "USADA8.CS",
+ USADA8_CC: "USADA8.CC",
+ USADA8_MI: "USADA8.MI",
+ USADA8_PL: "USADA8.PL",
+ USADA8_VS: "USADA8.VS",
+ USADA8_VC: "USADA8.VC",
+ USADA8_HI: "USADA8.HI",
+ USADA8_LS: "USADA8.LS",
+ USADA8_GE: "USADA8.GE",
+ USADA8_LT: "USADA8.LT",
+ USADA8_GT: "USADA8.GT",
+ USADA8_LE: "USADA8.LE",
+ USADA8: "USADA8",
+ USADA8_ZZ: "USADA8.ZZ",
+ USAT_EQ: "USAT.EQ",
+ USAT_NE: "USAT.NE",
+ USAT_CS: "USAT.CS",
+ USAT_CC: "USAT.CC",
+ USAT_MI: "USAT.MI",
+ USAT_PL: "USAT.PL",
+ USAT_VS: "USAT.VS",
+ USAT_VC: "USAT.VC",
+ USAT_HI: "USAT.HI",
+ USAT_LS: "USAT.LS",
+ USAT_GE: "USAT.GE",
+ USAT_LT: "USAT.LT",
+ USAT_GT: "USAT.GT",
+ USAT_LE: "USAT.LE",
+ USAT: "USAT",
+ USAT_ZZ: "USAT.ZZ",
+ USAT16_EQ: "USAT16.EQ",
+ USAT16_NE: "USAT16.NE",
+ USAT16_CS: "USAT16.CS",
+ USAT16_CC: "USAT16.CC",
+ USAT16_MI: "USAT16.MI",
+ USAT16_PL: "USAT16.PL",
+ USAT16_VS: "USAT16.VS",
+ USAT16_VC: "USAT16.VC",
+ USAT16_HI: "USAT16.HI",
+ USAT16_LS: "USAT16.LS",
+ USAT16_GE: "USAT16.GE",
+ USAT16_LT: "USAT16.LT",
+ USAT16_GT: "USAT16.GT",
+ USAT16_LE: "USAT16.LE",
+ USAT16: "USAT16",
+ USAT16_ZZ: "USAT16.ZZ",
+ USAX_EQ: "USAX.EQ",
+ USAX_NE: "USAX.NE",
+ USAX_CS: "USAX.CS",
+ USAX_CC: "USAX.CC",
+ USAX_MI: "USAX.MI",
+ USAX_PL: "USAX.PL",
+ USAX_VS: "USAX.VS",
+ USAX_VC: "USAX.VC",
+ USAX_HI: "USAX.HI",
+ USAX_LS: "USAX.LS",
+ USAX_GE: "USAX.GE",
+ USAX_LT: "USAX.LT",
+ USAX_GT: "USAX.GT",
+ USAX_LE: "USAX.LE",
+ USAX: "USAX",
+ USAX_ZZ: "USAX.ZZ",
+ USUB16_EQ: "USUB16.EQ",
+ USUB16_NE: "USUB16.NE",
+ USUB16_CS: "USUB16.CS",
+ USUB16_CC: "USUB16.CC",
+ USUB16_MI: "USUB16.MI",
+ USUB16_PL: "USUB16.PL",
+ USUB16_VS: "USUB16.VS",
+ USUB16_VC: "USUB16.VC",
+ USUB16_HI: "USUB16.HI",
+ USUB16_LS: "USUB16.LS",
+ USUB16_GE: "USUB16.GE",
+ USUB16_LT: "USUB16.LT",
+ USUB16_GT: "USUB16.GT",
+ USUB16_LE: "USUB16.LE",
+ USUB16: "USUB16",
+ USUB16_ZZ: "USUB16.ZZ",
+ USUB8_EQ: "USUB8.EQ",
+ USUB8_NE: "USUB8.NE",
+ USUB8_CS: "USUB8.CS",
+ USUB8_CC: "USUB8.CC",
+ USUB8_MI: "USUB8.MI",
+ USUB8_PL: "USUB8.PL",
+ USUB8_VS: "USUB8.VS",
+ USUB8_VC: "USUB8.VC",
+ USUB8_HI: "USUB8.HI",
+ USUB8_LS: "USUB8.LS",
+ USUB8_GE: "USUB8.GE",
+ USUB8_LT: "USUB8.LT",
+ USUB8_GT: "USUB8.GT",
+ USUB8_LE: "USUB8.LE",
+ USUB8: "USUB8",
+ USUB8_ZZ: "USUB8.ZZ",
+ UXTAB_EQ: "UXTAB.EQ",
+ UXTAB_NE: "UXTAB.NE",
+ UXTAB_CS: "UXTAB.CS",
+ UXTAB_CC: "UXTAB.CC",
+ UXTAB_MI: "UXTAB.MI",
+ UXTAB_PL: "UXTAB.PL",
+ UXTAB_VS: "UXTAB.VS",
+ UXTAB_VC: "UXTAB.VC",
+ UXTAB_HI: "UXTAB.HI",
+ UXTAB_LS: "UXTAB.LS",
+ UXTAB_GE: "UXTAB.GE",
+ UXTAB_LT: "UXTAB.LT",
+ UXTAB_GT: "UXTAB.GT",
+ UXTAB_LE: "UXTAB.LE",
+ UXTAB: "UXTAB",
+ UXTAB_ZZ: "UXTAB.ZZ",
+ UXTAB16_EQ: "UXTAB16.EQ",
+ UXTAB16_NE: "UXTAB16.NE",
+ UXTAB16_CS: "UXTAB16.CS",
+ UXTAB16_CC: "UXTAB16.CC",
+ UXTAB16_MI: "UXTAB16.MI",
+ UXTAB16_PL: "UXTAB16.PL",
+ UXTAB16_VS: "UXTAB16.VS",
+ UXTAB16_VC: "UXTAB16.VC",
+ UXTAB16_HI: "UXTAB16.HI",
+ UXTAB16_LS: "UXTAB16.LS",
+ UXTAB16_GE: "UXTAB16.GE",
+ UXTAB16_LT: "UXTAB16.LT",
+ UXTAB16_GT: "UXTAB16.GT",
+ UXTAB16_LE: "UXTAB16.LE",
+ UXTAB16: "UXTAB16",
+ UXTAB16_ZZ: "UXTAB16.ZZ",
+ UXTAH_EQ: "UXTAH.EQ",
+ UXTAH_NE: "UXTAH.NE",
+ UXTAH_CS: "UXTAH.CS",
+ UXTAH_CC: "UXTAH.CC",
+ UXTAH_MI: "UXTAH.MI",
+ UXTAH_PL: "UXTAH.PL",
+ UXTAH_VS: "UXTAH.VS",
+ UXTAH_VC: "UXTAH.VC",
+ UXTAH_HI: "UXTAH.HI",
+ UXTAH_LS: "UXTAH.LS",
+ UXTAH_GE: "UXTAH.GE",
+ UXTAH_LT: "UXTAH.LT",
+ UXTAH_GT: "UXTAH.GT",
+ UXTAH_LE: "UXTAH.LE",
+ UXTAH: "UXTAH",
+ UXTAH_ZZ: "UXTAH.ZZ",
+ UXTB_EQ: "UXTB.EQ",
+ UXTB_NE: "UXTB.NE",
+ UXTB_CS: "UXTB.CS",
+ UXTB_CC: "UXTB.CC",
+ UXTB_MI: "UXTB.MI",
+ UXTB_PL: "UXTB.PL",
+ UXTB_VS: "UXTB.VS",
+ UXTB_VC: "UXTB.VC",
+ UXTB_HI: "UXTB.HI",
+ UXTB_LS: "UXTB.LS",
+ UXTB_GE: "UXTB.GE",
+ UXTB_LT: "UXTB.LT",
+ UXTB_GT: "UXTB.GT",
+ UXTB_LE: "UXTB.LE",
+ UXTB: "UXTB",
+ UXTB_ZZ: "UXTB.ZZ",
+ UXTB16_EQ: "UXTB16.EQ",
+ UXTB16_NE: "UXTB16.NE",
+ UXTB16_CS: "UXTB16.CS",
+ UXTB16_CC: "UXTB16.CC",
+ UXTB16_MI: "UXTB16.MI",
+ UXTB16_PL: "UXTB16.PL",
+ UXTB16_VS: "UXTB16.VS",
+ UXTB16_VC: "UXTB16.VC",
+ UXTB16_HI: "UXTB16.HI",
+ UXTB16_LS: "UXTB16.LS",
+ UXTB16_GE: "UXTB16.GE",
+ UXTB16_LT: "UXTB16.LT",
+ UXTB16_GT: "UXTB16.GT",
+ UXTB16_LE: "UXTB16.LE",
+ UXTB16: "UXTB16",
+ UXTB16_ZZ: "UXTB16.ZZ",
+ UXTH_EQ: "UXTH.EQ",
+ UXTH_NE: "UXTH.NE",
+ UXTH_CS: "UXTH.CS",
+ UXTH_CC: "UXTH.CC",
+ UXTH_MI: "UXTH.MI",
+ UXTH_PL: "UXTH.PL",
+ UXTH_VS: "UXTH.VS",
+ UXTH_VC: "UXTH.VC",
+ UXTH_HI: "UXTH.HI",
+ UXTH_LS: "UXTH.LS",
+ UXTH_GE: "UXTH.GE",
+ UXTH_LT: "UXTH.LT",
+ UXTH_GT: "UXTH.GT",
+ UXTH_LE: "UXTH.LE",
+ UXTH: "UXTH",
+ UXTH_ZZ: "UXTH.ZZ",
+ VABS_EQ_F32: "VABS.EQ.F32",
+ VABS_NE_F32: "VABS.NE.F32",
+ VABS_CS_F32: "VABS.CS.F32",
+ VABS_CC_F32: "VABS.CC.F32",
+ VABS_MI_F32: "VABS.MI.F32",
+ VABS_PL_F32: "VABS.PL.F32",
+ VABS_VS_F32: "VABS.VS.F32",
+ VABS_VC_F32: "VABS.VC.F32",
+ VABS_HI_F32: "VABS.HI.F32",
+ VABS_LS_F32: "VABS.LS.F32",
+ VABS_GE_F32: "VABS.GE.F32",
+ VABS_LT_F32: "VABS.LT.F32",
+ VABS_GT_F32: "VABS.GT.F32",
+ VABS_LE_F32: "VABS.LE.F32",
+ VABS_F32: "VABS.F32",
+ VABS_ZZ_F32: "VABS.ZZ.F32",
+ VABS_EQ_F64: "VABS.EQ.F64",
+ VABS_NE_F64: "VABS.NE.F64",
+ VABS_CS_F64: "VABS.CS.F64",
+ VABS_CC_F64: "VABS.CC.F64",
+ VABS_MI_F64: "VABS.MI.F64",
+ VABS_PL_F64: "VABS.PL.F64",
+ VABS_VS_F64: "VABS.VS.F64",
+ VABS_VC_F64: "VABS.VC.F64",
+ VABS_HI_F64: "VABS.HI.F64",
+ VABS_LS_F64: "VABS.LS.F64",
+ VABS_GE_F64: "VABS.GE.F64",
+ VABS_LT_F64: "VABS.LT.F64",
+ VABS_GT_F64: "VABS.GT.F64",
+ VABS_LE_F64: "VABS.LE.F64",
+ VABS_F64: "VABS.F64",
+ VABS_ZZ_F64: "VABS.ZZ.F64",
+ VADD_EQ_F32: "VADD.EQ.F32",
+ VADD_NE_F32: "VADD.NE.F32",
+ VADD_CS_F32: "VADD.CS.F32",
+ VADD_CC_F32: "VADD.CC.F32",
+ VADD_MI_F32: "VADD.MI.F32",
+ VADD_PL_F32: "VADD.PL.F32",
+ VADD_VS_F32: "VADD.VS.F32",
+ VADD_VC_F32: "VADD.VC.F32",
+ VADD_HI_F32: "VADD.HI.F32",
+ VADD_LS_F32: "VADD.LS.F32",
+ VADD_GE_F32: "VADD.GE.F32",
+ VADD_LT_F32: "VADD.LT.F32",
+ VADD_GT_F32: "VADD.GT.F32",
+ VADD_LE_F32: "VADD.LE.F32",
+ VADD_F32: "VADD.F32",
+ VADD_ZZ_F32: "VADD.ZZ.F32",
+ VADD_EQ_F64: "VADD.EQ.F64",
+ VADD_NE_F64: "VADD.NE.F64",
+ VADD_CS_F64: "VADD.CS.F64",
+ VADD_CC_F64: "VADD.CC.F64",
+ VADD_MI_F64: "VADD.MI.F64",
+ VADD_PL_F64: "VADD.PL.F64",
+ VADD_VS_F64: "VADD.VS.F64",
+ VADD_VC_F64: "VADD.VC.F64",
+ VADD_HI_F64: "VADD.HI.F64",
+ VADD_LS_F64: "VADD.LS.F64",
+ VADD_GE_F64: "VADD.GE.F64",
+ VADD_LT_F64: "VADD.LT.F64",
+ VADD_GT_F64: "VADD.GT.F64",
+ VADD_LE_F64: "VADD.LE.F64",
+ VADD_F64: "VADD.F64",
+ VADD_ZZ_F64: "VADD.ZZ.F64",
+ VCMP_EQ_F32: "VCMP.EQ.F32",
+ VCMP_NE_F32: "VCMP.NE.F32",
+ VCMP_CS_F32: "VCMP.CS.F32",
+ VCMP_CC_F32: "VCMP.CC.F32",
+ VCMP_MI_F32: "VCMP.MI.F32",
+ VCMP_PL_F32: "VCMP.PL.F32",
+ VCMP_VS_F32: "VCMP.VS.F32",
+ VCMP_VC_F32: "VCMP.VC.F32",
+ VCMP_HI_F32: "VCMP.HI.F32",
+ VCMP_LS_F32: "VCMP.LS.F32",
+ VCMP_GE_F32: "VCMP.GE.F32",
+ VCMP_LT_F32: "VCMP.LT.F32",
+ VCMP_GT_F32: "VCMP.GT.F32",
+ VCMP_LE_F32: "VCMP.LE.F32",
+ VCMP_F32: "VCMP.F32",
+ VCMP_ZZ_F32: "VCMP.ZZ.F32",
+ VCMP_EQ_F64: "VCMP.EQ.F64",
+ VCMP_NE_F64: "VCMP.NE.F64",
+ VCMP_CS_F64: "VCMP.CS.F64",
+ VCMP_CC_F64: "VCMP.CC.F64",
+ VCMP_MI_F64: "VCMP.MI.F64",
+ VCMP_PL_F64: "VCMP.PL.F64",
+ VCMP_VS_F64: "VCMP.VS.F64",
+ VCMP_VC_F64: "VCMP.VC.F64",
+ VCMP_HI_F64: "VCMP.HI.F64",
+ VCMP_LS_F64: "VCMP.LS.F64",
+ VCMP_GE_F64: "VCMP.GE.F64",
+ VCMP_LT_F64: "VCMP.LT.F64",
+ VCMP_GT_F64: "VCMP.GT.F64",
+ VCMP_LE_F64: "VCMP.LE.F64",
+ VCMP_F64: "VCMP.F64",
+ VCMP_ZZ_F64: "VCMP.ZZ.F64",
+ VCMP_E_EQ_F32: "VCMP.E.EQ.F32",
+ VCMP_E_NE_F32: "VCMP.E.NE.F32",
+ VCMP_E_CS_F32: "VCMP.E.CS.F32",
+ VCMP_E_CC_F32: "VCMP.E.CC.F32",
+ VCMP_E_MI_F32: "VCMP.E.MI.F32",
+ VCMP_E_PL_F32: "VCMP.E.PL.F32",
+ VCMP_E_VS_F32: "VCMP.E.VS.F32",
+ VCMP_E_VC_F32: "VCMP.E.VC.F32",
+ VCMP_E_HI_F32: "VCMP.E.HI.F32",
+ VCMP_E_LS_F32: "VCMP.E.LS.F32",
+ VCMP_E_GE_F32: "VCMP.E.GE.F32",
+ VCMP_E_LT_F32: "VCMP.E.LT.F32",
+ VCMP_E_GT_F32: "VCMP.E.GT.F32",
+ VCMP_E_LE_F32: "VCMP.E.LE.F32",
+ VCMP_E_F32: "VCMP.E.F32",
+ VCMP_E_ZZ_F32: "VCMP.E.ZZ.F32",
+ VCMP_E_EQ_F64: "VCMP.E.EQ.F64",
+ VCMP_E_NE_F64: "VCMP.E.NE.F64",
+ VCMP_E_CS_F64: "VCMP.E.CS.F64",
+ VCMP_E_CC_F64: "VCMP.E.CC.F64",
+ VCMP_E_MI_F64: "VCMP.E.MI.F64",
+ VCMP_E_PL_F64: "VCMP.E.PL.F64",
+ VCMP_E_VS_F64: "VCMP.E.VS.F64",
+ VCMP_E_VC_F64: "VCMP.E.VC.F64",
+ VCMP_E_HI_F64: "VCMP.E.HI.F64",
+ VCMP_E_LS_F64: "VCMP.E.LS.F64",
+ VCMP_E_GE_F64: "VCMP.E.GE.F64",
+ VCMP_E_LT_F64: "VCMP.E.LT.F64",
+ VCMP_E_GT_F64: "VCMP.E.GT.F64",
+ VCMP_E_LE_F64: "VCMP.E.LE.F64",
+ VCMP_E_F64: "VCMP.E.F64",
+ VCMP_E_ZZ_F64: "VCMP.E.ZZ.F64",
+ VCVT_EQ_F32_FXS16: "VCVT.EQ.F32.FXS16",
+ VCVT_NE_F32_FXS16: "VCVT.NE.F32.FXS16",
+ VCVT_CS_F32_FXS16: "VCVT.CS.F32.FXS16",
+ VCVT_CC_F32_FXS16: "VCVT.CC.F32.FXS16",
+ VCVT_MI_F32_FXS16: "VCVT.MI.F32.FXS16",
+ VCVT_PL_F32_FXS16: "VCVT.PL.F32.FXS16",
+ VCVT_VS_F32_FXS16: "VCVT.VS.F32.FXS16",
+ VCVT_VC_F32_FXS16: "VCVT.VC.F32.FXS16",
+ VCVT_HI_F32_FXS16: "VCVT.HI.F32.FXS16",
+ VCVT_LS_F32_FXS16: "VCVT.LS.F32.FXS16",
+ VCVT_GE_F32_FXS16: "VCVT.GE.F32.FXS16",
+ VCVT_LT_F32_FXS16: "VCVT.LT.F32.FXS16",
+ VCVT_GT_F32_FXS16: "VCVT.GT.F32.FXS16",
+ VCVT_LE_F32_FXS16: "VCVT.LE.F32.FXS16",
+ VCVT_F32_FXS16: "VCVT.F32.FXS16",
+ VCVT_ZZ_F32_FXS16: "VCVT.ZZ.F32.FXS16",
+ VCVT_EQ_F32_FXS32: "VCVT.EQ.F32.FXS32",
+ VCVT_NE_F32_FXS32: "VCVT.NE.F32.FXS32",
+ VCVT_CS_F32_FXS32: "VCVT.CS.F32.FXS32",
+ VCVT_CC_F32_FXS32: "VCVT.CC.F32.FXS32",
+ VCVT_MI_F32_FXS32: "VCVT.MI.F32.FXS32",
+ VCVT_PL_F32_FXS32: "VCVT.PL.F32.FXS32",
+ VCVT_VS_F32_FXS32: "VCVT.VS.F32.FXS32",
+ VCVT_VC_F32_FXS32: "VCVT.VC.F32.FXS32",
+ VCVT_HI_F32_FXS32: "VCVT.HI.F32.FXS32",
+ VCVT_LS_F32_FXS32: "VCVT.LS.F32.FXS32",
+ VCVT_GE_F32_FXS32: "VCVT.GE.F32.FXS32",
+ VCVT_LT_F32_FXS32: "VCVT.LT.F32.FXS32",
+ VCVT_GT_F32_FXS32: "VCVT.GT.F32.FXS32",
+ VCVT_LE_F32_FXS32: "VCVT.LE.F32.FXS32",
+ VCVT_F32_FXS32: "VCVT.F32.FXS32",
+ VCVT_ZZ_F32_FXS32: "VCVT.ZZ.F32.FXS32",
+ VCVT_EQ_F32_FXU16: "VCVT.EQ.F32.FXU16",
+ VCVT_NE_F32_FXU16: "VCVT.NE.F32.FXU16",
+ VCVT_CS_F32_FXU16: "VCVT.CS.F32.FXU16",
+ VCVT_CC_F32_FXU16: "VCVT.CC.F32.FXU16",
+ VCVT_MI_F32_FXU16: "VCVT.MI.F32.FXU16",
+ VCVT_PL_F32_FXU16: "VCVT.PL.F32.FXU16",
+ VCVT_VS_F32_FXU16: "VCVT.VS.F32.FXU16",
+ VCVT_VC_F32_FXU16: "VCVT.VC.F32.FXU16",
+ VCVT_HI_F32_FXU16: "VCVT.HI.F32.FXU16",
+ VCVT_LS_F32_FXU16: "VCVT.LS.F32.FXU16",
+ VCVT_GE_F32_FXU16: "VCVT.GE.F32.FXU16",
+ VCVT_LT_F32_FXU16: "VCVT.LT.F32.FXU16",
+ VCVT_GT_F32_FXU16: "VCVT.GT.F32.FXU16",
+ VCVT_LE_F32_FXU16: "VCVT.LE.F32.FXU16",
+ VCVT_F32_FXU16: "VCVT.F32.FXU16",
+ VCVT_ZZ_F32_FXU16: "VCVT.ZZ.F32.FXU16",
+ VCVT_EQ_F32_FXU32: "VCVT.EQ.F32.FXU32",
+ VCVT_NE_F32_FXU32: "VCVT.NE.F32.FXU32",
+ VCVT_CS_F32_FXU32: "VCVT.CS.F32.FXU32",
+ VCVT_CC_F32_FXU32: "VCVT.CC.F32.FXU32",
+ VCVT_MI_F32_FXU32: "VCVT.MI.F32.FXU32",
+ VCVT_PL_F32_FXU32: "VCVT.PL.F32.FXU32",
+ VCVT_VS_F32_FXU32: "VCVT.VS.F32.FXU32",
+ VCVT_VC_F32_FXU32: "VCVT.VC.F32.FXU32",
+ VCVT_HI_F32_FXU32: "VCVT.HI.F32.FXU32",
+ VCVT_LS_F32_FXU32: "VCVT.LS.F32.FXU32",
+ VCVT_GE_F32_FXU32: "VCVT.GE.F32.FXU32",
+ VCVT_LT_F32_FXU32: "VCVT.LT.F32.FXU32",
+ VCVT_GT_F32_FXU32: "VCVT.GT.F32.FXU32",
+ VCVT_LE_F32_FXU32: "VCVT.LE.F32.FXU32",
+ VCVT_F32_FXU32: "VCVT.F32.FXU32",
+ VCVT_ZZ_F32_FXU32: "VCVT.ZZ.F32.FXU32",
+ VCVT_EQ_F64_FXS16: "VCVT.EQ.F64.FXS16",
+ VCVT_NE_F64_FXS16: "VCVT.NE.F64.FXS16",
+ VCVT_CS_F64_FXS16: "VCVT.CS.F64.FXS16",
+ VCVT_CC_F64_FXS16: "VCVT.CC.F64.FXS16",
+ VCVT_MI_F64_FXS16: "VCVT.MI.F64.FXS16",
+ VCVT_PL_F64_FXS16: "VCVT.PL.F64.FXS16",
+ VCVT_VS_F64_FXS16: "VCVT.VS.F64.FXS16",
+ VCVT_VC_F64_FXS16: "VCVT.VC.F64.FXS16",
+ VCVT_HI_F64_FXS16: "VCVT.HI.F64.FXS16",
+ VCVT_LS_F64_FXS16: "VCVT.LS.F64.FXS16",
+ VCVT_GE_F64_FXS16: "VCVT.GE.F64.FXS16",
+ VCVT_LT_F64_FXS16: "VCVT.LT.F64.FXS16",
+ VCVT_GT_F64_FXS16: "VCVT.GT.F64.FXS16",
+ VCVT_LE_F64_FXS16: "VCVT.LE.F64.FXS16",
+ VCVT_F64_FXS16: "VCVT.F64.FXS16",
+ VCVT_ZZ_F64_FXS16: "VCVT.ZZ.F64.FXS16",
+ VCVT_EQ_F64_FXS32: "VCVT.EQ.F64.FXS32",
+ VCVT_NE_F64_FXS32: "VCVT.NE.F64.FXS32",
+ VCVT_CS_F64_FXS32: "VCVT.CS.F64.FXS32",
+ VCVT_CC_F64_FXS32: "VCVT.CC.F64.FXS32",
+ VCVT_MI_F64_FXS32: "VCVT.MI.F64.FXS32",
+ VCVT_PL_F64_FXS32: "VCVT.PL.F64.FXS32",
+ VCVT_VS_F64_FXS32: "VCVT.VS.F64.FXS32",
+ VCVT_VC_F64_FXS32: "VCVT.VC.F64.FXS32",
+ VCVT_HI_F64_FXS32: "VCVT.HI.F64.FXS32",
+ VCVT_LS_F64_FXS32: "VCVT.LS.F64.FXS32",
+ VCVT_GE_F64_FXS32: "VCVT.GE.F64.FXS32",
+ VCVT_LT_F64_FXS32: "VCVT.LT.F64.FXS32",
+ VCVT_GT_F64_FXS32: "VCVT.GT.F64.FXS32",
+ VCVT_LE_F64_FXS32: "VCVT.LE.F64.FXS32",
+ VCVT_F64_FXS32: "VCVT.F64.FXS32",
+ VCVT_ZZ_F64_FXS32: "VCVT.ZZ.F64.FXS32",
+ VCVT_EQ_F64_FXU16: "VCVT.EQ.F64.FXU16",
+ VCVT_NE_F64_FXU16: "VCVT.NE.F64.FXU16",
+ VCVT_CS_F64_FXU16: "VCVT.CS.F64.FXU16",
+ VCVT_CC_F64_FXU16: "VCVT.CC.F64.FXU16",
+ VCVT_MI_F64_FXU16: "VCVT.MI.F64.FXU16",
+ VCVT_PL_F64_FXU16: "VCVT.PL.F64.FXU16",
+ VCVT_VS_F64_FXU16: "VCVT.VS.F64.FXU16",
+ VCVT_VC_F64_FXU16: "VCVT.VC.F64.FXU16",
+ VCVT_HI_F64_FXU16: "VCVT.HI.F64.FXU16",
+ VCVT_LS_F64_FXU16: "VCVT.LS.F64.FXU16",
+ VCVT_GE_F64_FXU16: "VCVT.GE.F64.FXU16",
+ VCVT_LT_F64_FXU16: "VCVT.LT.F64.FXU16",
+ VCVT_GT_F64_FXU16: "VCVT.GT.F64.FXU16",
+ VCVT_LE_F64_FXU16: "VCVT.LE.F64.FXU16",
+ VCVT_F64_FXU16: "VCVT.F64.FXU16",
+ VCVT_ZZ_F64_FXU16: "VCVT.ZZ.F64.FXU16",
+ VCVT_EQ_F64_FXU32: "VCVT.EQ.F64.FXU32",
+ VCVT_NE_F64_FXU32: "VCVT.NE.F64.FXU32",
+ VCVT_CS_F64_FXU32: "VCVT.CS.F64.FXU32",
+ VCVT_CC_F64_FXU32: "VCVT.CC.F64.FXU32",
+ VCVT_MI_F64_FXU32: "VCVT.MI.F64.FXU32",
+ VCVT_PL_F64_FXU32: "VCVT.PL.F64.FXU32",
+ VCVT_VS_F64_FXU32: "VCVT.VS.F64.FXU32",
+ VCVT_VC_F64_FXU32: "VCVT.VC.F64.FXU32",
+ VCVT_HI_F64_FXU32: "VCVT.HI.F64.FXU32",
+ VCVT_LS_F64_FXU32: "VCVT.LS.F64.FXU32",
+ VCVT_GE_F64_FXU32: "VCVT.GE.F64.FXU32",
+ VCVT_LT_F64_FXU32: "VCVT.LT.F64.FXU32",
+ VCVT_GT_F64_FXU32: "VCVT.GT.F64.FXU32",
+ VCVT_LE_F64_FXU32: "VCVT.LE.F64.FXU32",
+ VCVT_F64_FXU32: "VCVT.F64.FXU32",
+ VCVT_ZZ_F64_FXU32: "VCVT.ZZ.F64.FXU32",
+ VCVT_EQ_F32_U32: "VCVT.EQ.F32.U32",
+ VCVT_NE_F32_U32: "VCVT.NE.F32.U32",
+ VCVT_CS_F32_U32: "VCVT.CS.F32.U32",
+ VCVT_CC_F32_U32: "VCVT.CC.F32.U32",
+ VCVT_MI_F32_U32: "VCVT.MI.F32.U32",
+ VCVT_PL_F32_U32: "VCVT.PL.F32.U32",
+ VCVT_VS_F32_U32: "VCVT.VS.F32.U32",
+ VCVT_VC_F32_U32: "VCVT.VC.F32.U32",
+ VCVT_HI_F32_U32: "VCVT.HI.F32.U32",
+ VCVT_LS_F32_U32: "VCVT.LS.F32.U32",
+ VCVT_GE_F32_U32: "VCVT.GE.F32.U32",
+ VCVT_LT_F32_U32: "VCVT.LT.F32.U32",
+ VCVT_GT_F32_U32: "VCVT.GT.F32.U32",
+ VCVT_LE_F32_U32: "VCVT.LE.F32.U32",
+ VCVT_F32_U32: "VCVT.F32.U32",
+ VCVT_ZZ_F32_U32: "VCVT.ZZ.F32.U32",
+ VCVT_EQ_F32_S32: "VCVT.EQ.F32.S32",
+ VCVT_NE_F32_S32: "VCVT.NE.F32.S32",
+ VCVT_CS_F32_S32: "VCVT.CS.F32.S32",
+ VCVT_CC_F32_S32: "VCVT.CC.F32.S32",
+ VCVT_MI_F32_S32: "VCVT.MI.F32.S32",
+ VCVT_PL_F32_S32: "VCVT.PL.F32.S32",
+ VCVT_VS_F32_S32: "VCVT.VS.F32.S32",
+ VCVT_VC_F32_S32: "VCVT.VC.F32.S32",
+ VCVT_HI_F32_S32: "VCVT.HI.F32.S32",
+ VCVT_LS_F32_S32: "VCVT.LS.F32.S32",
+ VCVT_GE_F32_S32: "VCVT.GE.F32.S32",
+ VCVT_LT_F32_S32: "VCVT.LT.F32.S32",
+ VCVT_GT_F32_S32: "VCVT.GT.F32.S32",
+ VCVT_LE_F32_S32: "VCVT.LE.F32.S32",
+ VCVT_F32_S32: "VCVT.F32.S32",
+ VCVT_ZZ_F32_S32: "VCVT.ZZ.F32.S32",
+ VCVT_EQ_F64_U32: "VCVT.EQ.F64.U32",
+ VCVT_NE_F64_U32: "VCVT.NE.F64.U32",
+ VCVT_CS_F64_U32: "VCVT.CS.F64.U32",
+ VCVT_CC_F64_U32: "VCVT.CC.F64.U32",
+ VCVT_MI_F64_U32: "VCVT.MI.F64.U32",
+ VCVT_PL_F64_U32: "VCVT.PL.F64.U32",
+ VCVT_VS_F64_U32: "VCVT.VS.F64.U32",
+ VCVT_VC_F64_U32: "VCVT.VC.F64.U32",
+ VCVT_HI_F64_U32: "VCVT.HI.F64.U32",
+ VCVT_LS_F64_U32: "VCVT.LS.F64.U32",
+ VCVT_GE_F64_U32: "VCVT.GE.F64.U32",
+ VCVT_LT_F64_U32: "VCVT.LT.F64.U32",
+ VCVT_GT_F64_U32: "VCVT.GT.F64.U32",
+ VCVT_LE_F64_U32: "VCVT.LE.F64.U32",
+ VCVT_F64_U32: "VCVT.F64.U32",
+ VCVT_ZZ_F64_U32: "VCVT.ZZ.F64.U32",
+ VCVT_EQ_F64_S32: "VCVT.EQ.F64.S32",
+ VCVT_NE_F64_S32: "VCVT.NE.F64.S32",
+ VCVT_CS_F64_S32: "VCVT.CS.F64.S32",
+ VCVT_CC_F64_S32: "VCVT.CC.F64.S32",
+ VCVT_MI_F64_S32: "VCVT.MI.F64.S32",
+ VCVT_PL_F64_S32: "VCVT.PL.F64.S32",
+ VCVT_VS_F64_S32: "VCVT.VS.F64.S32",
+ VCVT_VC_F64_S32: "VCVT.VC.F64.S32",
+ VCVT_HI_F64_S32: "VCVT.HI.F64.S32",
+ VCVT_LS_F64_S32: "VCVT.LS.F64.S32",
+ VCVT_GE_F64_S32: "VCVT.GE.F64.S32",
+ VCVT_LT_F64_S32: "VCVT.LT.F64.S32",
+ VCVT_GT_F64_S32: "VCVT.GT.F64.S32",
+ VCVT_LE_F64_S32: "VCVT.LE.F64.S32",
+ VCVT_F64_S32: "VCVT.F64.S32",
+ VCVT_ZZ_F64_S32: "VCVT.ZZ.F64.S32",
+ VCVT_EQ_F64_F32: "VCVT.EQ.F64.F32",
+ VCVT_NE_F64_F32: "VCVT.NE.F64.F32",
+ VCVT_CS_F64_F32: "VCVT.CS.F64.F32",
+ VCVT_CC_F64_F32: "VCVT.CC.F64.F32",
+ VCVT_MI_F64_F32: "VCVT.MI.F64.F32",
+ VCVT_PL_F64_F32: "VCVT.PL.F64.F32",
+ VCVT_VS_F64_F32: "VCVT.VS.F64.F32",
+ VCVT_VC_F64_F32: "VCVT.VC.F64.F32",
+ VCVT_HI_F64_F32: "VCVT.HI.F64.F32",
+ VCVT_LS_F64_F32: "VCVT.LS.F64.F32",
+ VCVT_GE_F64_F32: "VCVT.GE.F64.F32",
+ VCVT_LT_F64_F32: "VCVT.LT.F64.F32",
+ VCVT_GT_F64_F32: "VCVT.GT.F64.F32",
+ VCVT_LE_F64_F32: "VCVT.LE.F64.F32",
+ VCVT_F64_F32: "VCVT.F64.F32",
+ VCVT_ZZ_F64_F32: "VCVT.ZZ.F64.F32",
+ VCVT_EQ_F32_F64: "VCVT.EQ.F32.F64",
+ VCVT_NE_F32_F64: "VCVT.NE.F32.F64",
+ VCVT_CS_F32_F64: "VCVT.CS.F32.F64",
+ VCVT_CC_F32_F64: "VCVT.CC.F32.F64",
+ VCVT_MI_F32_F64: "VCVT.MI.F32.F64",
+ VCVT_PL_F32_F64: "VCVT.PL.F32.F64",
+ VCVT_VS_F32_F64: "VCVT.VS.F32.F64",
+ VCVT_VC_F32_F64: "VCVT.VC.F32.F64",
+ VCVT_HI_F32_F64: "VCVT.HI.F32.F64",
+ VCVT_LS_F32_F64: "VCVT.LS.F32.F64",
+ VCVT_GE_F32_F64: "VCVT.GE.F32.F64",
+ VCVT_LT_F32_F64: "VCVT.LT.F32.F64",
+ VCVT_GT_F32_F64: "VCVT.GT.F32.F64",
+ VCVT_LE_F32_F64: "VCVT.LE.F32.F64",
+ VCVT_F32_F64: "VCVT.F32.F64",
+ VCVT_ZZ_F32_F64: "VCVT.ZZ.F32.F64",
+ VCVT_EQ_FXS16_F32: "VCVT.EQ.FXS16.F32",
+ VCVT_NE_FXS16_F32: "VCVT.NE.FXS16.F32",
+ VCVT_CS_FXS16_F32: "VCVT.CS.FXS16.F32",
+ VCVT_CC_FXS16_F32: "VCVT.CC.FXS16.F32",
+ VCVT_MI_FXS16_F32: "VCVT.MI.FXS16.F32",
+ VCVT_PL_FXS16_F32: "VCVT.PL.FXS16.F32",
+ VCVT_VS_FXS16_F32: "VCVT.VS.FXS16.F32",
+ VCVT_VC_FXS16_F32: "VCVT.VC.FXS16.F32",
+ VCVT_HI_FXS16_F32: "VCVT.HI.FXS16.F32",
+ VCVT_LS_FXS16_F32: "VCVT.LS.FXS16.F32",
+ VCVT_GE_FXS16_F32: "VCVT.GE.FXS16.F32",
+ VCVT_LT_FXS16_F32: "VCVT.LT.FXS16.F32",
+ VCVT_GT_FXS16_F32: "VCVT.GT.FXS16.F32",
+ VCVT_LE_FXS16_F32: "VCVT.LE.FXS16.F32",
+ VCVT_FXS16_F32: "VCVT.FXS16.F32",
+ VCVT_ZZ_FXS16_F32: "VCVT.ZZ.FXS16.F32",
+ VCVT_EQ_FXS16_F64: "VCVT.EQ.FXS16.F64",
+ VCVT_NE_FXS16_F64: "VCVT.NE.FXS16.F64",
+ VCVT_CS_FXS16_F64: "VCVT.CS.FXS16.F64",
+ VCVT_CC_FXS16_F64: "VCVT.CC.FXS16.F64",
+ VCVT_MI_FXS16_F64: "VCVT.MI.FXS16.F64",
+ VCVT_PL_FXS16_F64: "VCVT.PL.FXS16.F64",
+ VCVT_VS_FXS16_F64: "VCVT.VS.FXS16.F64",
+ VCVT_VC_FXS16_F64: "VCVT.VC.FXS16.F64",
+ VCVT_HI_FXS16_F64: "VCVT.HI.FXS16.F64",
+ VCVT_LS_FXS16_F64: "VCVT.LS.FXS16.F64",
+ VCVT_GE_FXS16_F64: "VCVT.GE.FXS16.F64",
+ VCVT_LT_FXS16_F64: "VCVT.LT.FXS16.F64",
+ VCVT_GT_FXS16_F64: "VCVT.GT.FXS16.F64",
+ VCVT_LE_FXS16_F64: "VCVT.LE.FXS16.F64",
+ VCVT_FXS16_F64: "VCVT.FXS16.F64",
+ VCVT_ZZ_FXS16_F64: "VCVT.ZZ.FXS16.F64",
+ VCVT_EQ_FXS32_F32: "VCVT.EQ.FXS32.F32",
+ VCVT_NE_FXS32_F32: "VCVT.NE.FXS32.F32",
+ VCVT_CS_FXS32_F32: "VCVT.CS.FXS32.F32",
+ VCVT_CC_FXS32_F32: "VCVT.CC.FXS32.F32",
+ VCVT_MI_FXS32_F32: "VCVT.MI.FXS32.F32",
+ VCVT_PL_FXS32_F32: "VCVT.PL.FXS32.F32",
+ VCVT_VS_FXS32_F32: "VCVT.VS.FXS32.F32",
+ VCVT_VC_FXS32_F32: "VCVT.VC.FXS32.F32",
+ VCVT_HI_FXS32_F32: "VCVT.HI.FXS32.F32",
+ VCVT_LS_FXS32_F32: "VCVT.LS.FXS32.F32",
+ VCVT_GE_FXS32_F32: "VCVT.GE.FXS32.F32",
+ VCVT_LT_FXS32_F32: "VCVT.LT.FXS32.F32",
+ VCVT_GT_FXS32_F32: "VCVT.GT.FXS32.F32",
+ VCVT_LE_FXS32_F32: "VCVT.LE.FXS32.F32",
+ VCVT_FXS32_F32: "VCVT.FXS32.F32",
+ VCVT_ZZ_FXS32_F32: "VCVT.ZZ.FXS32.F32",
+ VCVT_EQ_FXS32_F64: "VCVT.EQ.FXS32.F64",
+ VCVT_NE_FXS32_F64: "VCVT.NE.FXS32.F64",
+ VCVT_CS_FXS32_F64: "VCVT.CS.FXS32.F64",
+ VCVT_CC_FXS32_F64: "VCVT.CC.FXS32.F64",
+ VCVT_MI_FXS32_F64: "VCVT.MI.FXS32.F64",
+ VCVT_PL_FXS32_F64: "VCVT.PL.FXS32.F64",
+ VCVT_VS_FXS32_F64: "VCVT.VS.FXS32.F64",
+ VCVT_VC_FXS32_F64: "VCVT.VC.FXS32.F64",
+ VCVT_HI_FXS32_F64: "VCVT.HI.FXS32.F64",
+ VCVT_LS_FXS32_F64: "VCVT.LS.FXS32.F64",
+ VCVT_GE_FXS32_F64: "VCVT.GE.FXS32.F64",
+ VCVT_LT_FXS32_F64: "VCVT.LT.FXS32.F64",
+ VCVT_GT_FXS32_F64: "VCVT.GT.FXS32.F64",
+ VCVT_LE_FXS32_F64: "VCVT.LE.FXS32.F64",
+ VCVT_FXS32_F64: "VCVT.FXS32.F64",
+ VCVT_ZZ_FXS32_F64: "VCVT.ZZ.FXS32.F64",
+ VCVT_EQ_FXU16_F32: "VCVT.EQ.FXU16.F32",
+ VCVT_NE_FXU16_F32: "VCVT.NE.FXU16.F32",
+ VCVT_CS_FXU16_F32: "VCVT.CS.FXU16.F32",
+ VCVT_CC_FXU16_F32: "VCVT.CC.FXU16.F32",
+ VCVT_MI_FXU16_F32: "VCVT.MI.FXU16.F32",
+ VCVT_PL_FXU16_F32: "VCVT.PL.FXU16.F32",
+ VCVT_VS_FXU16_F32: "VCVT.VS.FXU16.F32",
+ VCVT_VC_FXU16_F32: "VCVT.VC.FXU16.F32",
+ VCVT_HI_FXU16_F32: "VCVT.HI.FXU16.F32",
+ VCVT_LS_FXU16_F32: "VCVT.LS.FXU16.F32",
+ VCVT_GE_FXU16_F32: "VCVT.GE.FXU16.F32",
+ VCVT_LT_FXU16_F32: "VCVT.LT.FXU16.F32",
+ VCVT_GT_FXU16_F32: "VCVT.GT.FXU16.F32",
+ VCVT_LE_FXU16_F32: "VCVT.LE.FXU16.F32",
+ VCVT_FXU16_F32: "VCVT.FXU16.F32",
+ VCVT_ZZ_FXU16_F32: "VCVT.ZZ.FXU16.F32",
+ VCVT_EQ_FXU16_F64: "VCVT.EQ.FXU16.F64",
+ VCVT_NE_FXU16_F64: "VCVT.NE.FXU16.F64",
+ VCVT_CS_FXU16_F64: "VCVT.CS.FXU16.F64",
+ VCVT_CC_FXU16_F64: "VCVT.CC.FXU16.F64",
+ VCVT_MI_FXU16_F64: "VCVT.MI.FXU16.F64",
+ VCVT_PL_FXU16_F64: "VCVT.PL.FXU16.F64",
+ VCVT_VS_FXU16_F64: "VCVT.VS.FXU16.F64",
+ VCVT_VC_FXU16_F64: "VCVT.VC.FXU16.F64",
+ VCVT_HI_FXU16_F64: "VCVT.HI.FXU16.F64",
+ VCVT_LS_FXU16_F64: "VCVT.LS.FXU16.F64",
+ VCVT_GE_FXU16_F64: "VCVT.GE.FXU16.F64",
+ VCVT_LT_FXU16_F64: "VCVT.LT.FXU16.F64",
+ VCVT_GT_FXU16_F64: "VCVT.GT.FXU16.F64",
+ VCVT_LE_FXU16_F64: "VCVT.LE.FXU16.F64",
+ VCVT_FXU16_F64: "VCVT.FXU16.F64",
+ VCVT_ZZ_FXU16_F64: "VCVT.ZZ.FXU16.F64",
+ VCVT_EQ_FXU32_F32: "VCVT.EQ.FXU32.F32",
+ VCVT_NE_FXU32_F32: "VCVT.NE.FXU32.F32",
+ VCVT_CS_FXU32_F32: "VCVT.CS.FXU32.F32",
+ VCVT_CC_FXU32_F32: "VCVT.CC.FXU32.F32",
+ VCVT_MI_FXU32_F32: "VCVT.MI.FXU32.F32",
+ VCVT_PL_FXU32_F32: "VCVT.PL.FXU32.F32",
+ VCVT_VS_FXU32_F32: "VCVT.VS.FXU32.F32",
+ VCVT_VC_FXU32_F32: "VCVT.VC.FXU32.F32",
+ VCVT_HI_FXU32_F32: "VCVT.HI.FXU32.F32",
+ VCVT_LS_FXU32_F32: "VCVT.LS.FXU32.F32",
+ VCVT_GE_FXU32_F32: "VCVT.GE.FXU32.F32",
+ VCVT_LT_FXU32_F32: "VCVT.LT.FXU32.F32",
+ VCVT_GT_FXU32_F32: "VCVT.GT.FXU32.F32",
+ VCVT_LE_FXU32_F32: "VCVT.LE.FXU32.F32",
+ VCVT_FXU32_F32: "VCVT.FXU32.F32",
+ VCVT_ZZ_FXU32_F32: "VCVT.ZZ.FXU32.F32",
+ VCVT_EQ_FXU32_F64: "VCVT.EQ.FXU32.F64",
+ VCVT_NE_FXU32_F64: "VCVT.NE.FXU32.F64",
+ VCVT_CS_FXU32_F64: "VCVT.CS.FXU32.F64",
+ VCVT_CC_FXU32_F64: "VCVT.CC.FXU32.F64",
+ VCVT_MI_FXU32_F64: "VCVT.MI.FXU32.F64",
+ VCVT_PL_FXU32_F64: "VCVT.PL.FXU32.F64",
+ VCVT_VS_FXU32_F64: "VCVT.VS.FXU32.F64",
+ VCVT_VC_FXU32_F64: "VCVT.VC.FXU32.F64",
+ VCVT_HI_FXU32_F64: "VCVT.HI.FXU32.F64",
+ VCVT_LS_FXU32_F64: "VCVT.LS.FXU32.F64",
+ VCVT_GE_FXU32_F64: "VCVT.GE.FXU32.F64",
+ VCVT_LT_FXU32_F64: "VCVT.LT.FXU32.F64",
+ VCVT_GT_FXU32_F64: "VCVT.GT.FXU32.F64",
+ VCVT_LE_FXU32_F64: "VCVT.LE.FXU32.F64",
+ VCVT_FXU32_F64: "VCVT.FXU32.F64",
+ VCVT_ZZ_FXU32_F64: "VCVT.ZZ.FXU32.F64",
+ VCVTB_EQ_F32_F16: "VCVTB.EQ.F32.F16",
+ VCVTB_NE_F32_F16: "VCVTB.NE.F32.F16",
+ VCVTB_CS_F32_F16: "VCVTB.CS.F32.F16",
+ VCVTB_CC_F32_F16: "VCVTB.CC.F32.F16",
+ VCVTB_MI_F32_F16: "VCVTB.MI.F32.F16",
+ VCVTB_PL_F32_F16: "VCVTB.PL.F32.F16",
+ VCVTB_VS_F32_F16: "VCVTB.VS.F32.F16",
+ VCVTB_VC_F32_F16: "VCVTB.VC.F32.F16",
+ VCVTB_HI_F32_F16: "VCVTB.HI.F32.F16",
+ VCVTB_LS_F32_F16: "VCVTB.LS.F32.F16",
+ VCVTB_GE_F32_F16: "VCVTB.GE.F32.F16",
+ VCVTB_LT_F32_F16: "VCVTB.LT.F32.F16",
+ VCVTB_GT_F32_F16: "VCVTB.GT.F32.F16",
+ VCVTB_LE_F32_F16: "VCVTB.LE.F32.F16",
+ VCVTB_F32_F16: "VCVTB.F32.F16",
+ VCVTB_ZZ_F32_F16: "VCVTB.ZZ.F32.F16",
+ VCVTB_EQ_F16_F32: "VCVTB.EQ.F16.F32",
+ VCVTB_NE_F16_F32: "VCVTB.NE.F16.F32",
+ VCVTB_CS_F16_F32: "VCVTB.CS.F16.F32",
+ VCVTB_CC_F16_F32: "VCVTB.CC.F16.F32",
+ VCVTB_MI_F16_F32: "VCVTB.MI.F16.F32",
+ VCVTB_PL_F16_F32: "VCVTB.PL.F16.F32",
+ VCVTB_VS_F16_F32: "VCVTB.VS.F16.F32",
+ VCVTB_VC_F16_F32: "VCVTB.VC.F16.F32",
+ VCVTB_HI_F16_F32: "VCVTB.HI.F16.F32",
+ VCVTB_LS_F16_F32: "VCVTB.LS.F16.F32",
+ VCVTB_GE_F16_F32: "VCVTB.GE.F16.F32",
+ VCVTB_LT_F16_F32: "VCVTB.LT.F16.F32",
+ VCVTB_GT_F16_F32: "VCVTB.GT.F16.F32",
+ VCVTB_LE_F16_F32: "VCVTB.LE.F16.F32",
+ VCVTB_F16_F32: "VCVTB.F16.F32",
+ VCVTB_ZZ_F16_F32: "VCVTB.ZZ.F16.F32",
+ VCVTT_EQ_F32_F16: "VCVTT.EQ.F32.F16",
+ VCVTT_NE_F32_F16: "VCVTT.NE.F32.F16",
+ VCVTT_CS_F32_F16: "VCVTT.CS.F32.F16",
+ VCVTT_CC_F32_F16: "VCVTT.CC.F32.F16",
+ VCVTT_MI_F32_F16: "VCVTT.MI.F32.F16",
+ VCVTT_PL_F32_F16: "VCVTT.PL.F32.F16",
+ VCVTT_VS_F32_F16: "VCVTT.VS.F32.F16",
+ VCVTT_VC_F32_F16: "VCVTT.VC.F32.F16",
+ VCVTT_HI_F32_F16: "VCVTT.HI.F32.F16",
+ VCVTT_LS_F32_F16: "VCVTT.LS.F32.F16",
+ VCVTT_GE_F32_F16: "VCVTT.GE.F32.F16",
+ VCVTT_LT_F32_F16: "VCVTT.LT.F32.F16",
+ VCVTT_GT_F32_F16: "VCVTT.GT.F32.F16",
+ VCVTT_LE_F32_F16: "VCVTT.LE.F32.F16",
+ VCVTT_F32_F16: "VCVTT.F32.F16",
+ VCVTT_ZZ_F32_F16: "VCVTT.ZZ.F32.F16",
+ VCVTT_EQ_F16_F32: "VCVTT.EQ.F16.F32",
+ VCVTT_NE_F16_F32: "VCVTT.NE.F16.F32",
+ VCVTT_CS_F16_F32: "VCVTT.CS.F16.F32",
+ VCVTT_CC_F16_F32: "VCVTT.CC.F16.F32",
+ VCVTT_MI_F16_F32: "VCVTT.MI.F16.F32",
+ VCVTT_PL_F16_F32: "VCVTT.PL.F16.F32",
+ VCVTT_VS_F16_F32: "VCVTT.VS.F16.F32",
+ VCVTT_VC_F16_F32: "VCVTT.VC.F16.F32",
+ VCVTT_HI_F16_F32: "VCVTT.HI.F16.F32",
+ VCVTT_LS_F16_F32: "VCVTT.LS.F16.F32",
+ VCVTT_GE_F16_F32: "VCVTT.GE.F16.F32",
+ VCVTT_LT_F16_F32: "VCVTT.LT.F16.F32",
+ VCVTT_GT_F16_F32: "VCVTT.GT.F16.F32",
+ VCVTT_LE_F16_F32: "VCVTT.LE.F16.F32",
+ VCVTT_F16_F32: "VCVTT.F16.F32",
+ VCVTT_ZZ_F16_F32: "VCVTT.ZZ.F16.F32",
+ VCVTR_EQ_U32_F32: "VCVTR.EQ.U32.F32",
+ VCVTR_NE_U32_F32: "VCVTR.NE.U32.F32",
+ VCVTR_CS_U32_F32: "VCVTR.CS.U32.F32",
+ VCVTR_CC_U32_F32: "VCVTR.CC.U32.F32",
+ VCVTR_MI_U32_F32: "VCVTR.MI.U32.F32",
+ VCVTR_PL_U32_F32: "VCVTR.PL.U32.F32",
+ VCVTR_VS_U32_F32: "VCVTR.VS.U32.F32",
+ VCVTR_VC_U32_F32: "VCVTR.VC.U32.F32",
+ VCVTR_HI_U32_F32: "VCVTR.HI.U32.F32",
+ VCVTR_LS_U32_F32: "VCVTR.LS.U32.F32",
+ VCVTR_GE_U32_F32: "VCVTR.GE.U32.F32",
+ VCVTR_LT_U32_F32: "VCVTR.LT.U32.F32",
+ VCVTR_GT_U32_F32: "VCVTR.GT.U32.F32",
+ VCVTR_LE_U32_F32: "VCVTR.LE.U32.F32",
+ VCVTR_U32_F32: "VCVTR.U32.F32",
+ VCVTR_ZZ_U32_F32: "VCVTR.ZZ.U32.F32",
+ VCVTR_EQ_U32_F64: "VCVTR.EQ.U32.F64",
+ VCVTR_NE_U32_F64: "VCVTR.NE.U32.F64",
+ VCVTR_CS_U32_F64: "VCVTR.CS.U32.F64",
+ VCVTR_CC_U32_F64: "VCVTR.CC.U32.F64",
+ VCVTR_MI_U32_F64: "VCVTR.MI.U32.F64",
+ VCVTR_PL_U32_F64: "VCVTR.PL.U32.F64",
+ VCVTR_VS_U32_F64: "VCVTR.VS.U32.F64",
+ VCVTR_VC_U32_F64: "VCVTR.VC.U32.F64",
+ VCVTR_HI_U32_F64: "VCVTR.HI.U32.F64",
+ VCVTR_LS_U32_F64: "VCVTR.LS.U32.F64",
+ VCVTR_GE_U32_F64: "VCVTR.GE.U32.F64",
+ VCVTR_LT_U32_F64: "VCVTR.LT.U32.F64",
+ VCVTR_GT_U32_F64: "VCVTR.GT.U32.F64",
+ VCVTR_LE_U32_F64: "VCVTR.LE.U32.F64",
+ VCVTR_U32_F64: "VCVTR.U32.F64",
+ VCVTR_ZZ_U32_F64: "VCVTR.ZZ.U32.F64",
+ VCVTR_EQ_S32_F32: "VCVTR.EQ.S32.F32",
+ VCVTR_NE_S32_F32: "VCVTR.NE.S32.F32",
+ VCVTR_CS_S32_F32: "VCVTR.CS.S32.F32",
+ VCVTR_CC_S32_F32: "VCVTR.CC.S32.F32",
+ VCVTR_MI_S32_F32: "VCVTR.MI.S32.F32",
+ VCVTR_PL_S32_F32: "VCVTR.PL.S32.F32",
+ VCVTR_VS_S32_F32: "VCVTR.VS.S32.F32",
+ VCVTR_VC_S32_F32: "VCVTR.VC.S32.F32",
+ VCVTR_HI_S32_F32: "VCVTR.HI.S32.F32",
+ VCVTR_LS_S32_F32: "VCVTR.LS.S32.F32",
+ VCVTR_GE_S32_F32: "VCVTR.GE.S32.F32",
+ VCVTR_LT_S32_F32: "VCVTR.LT.S32.F32",
+ VCVTR_GT_S32_F32: "VCVTR.GT.S32.F32",
+ VCVTR_LE_S32_F32: "VCVTR.LE.S32.F32",
+ VCVTR_S32_F32: "VCVTR.S32.F32",
+ VCVTR_ZZ_S32_F32: "VCVTR.ZZ.S32.F32",
+ VCVTR_EQ_S32_F64: "VCVTR.EQ.S32.F64",
+ VCVTR_NE_S32_F64: "VCVTR.NE.S32.F64",
+ VCVTR_CS_S32_F64: "VCVTR.CS.S32.F64",
+ VCVTR_CC_S32_F64: "VCVTR.CC.S32.F64",
+ VCVTR_MI_S32_F64: "VCVTR.MI.S32.F64",
+ VCVTR_PL_S32_F64: "VCVTR.PL.S32.F64",
+ VCVTR_VS_S32_F64: "VCVTR.VS.S32.F64",
+ VCVTR_VC_S32_F64: "VCVTR.VC.S32.F64",
+ VCVTR_HI_S32_F64: "VCVTR.HI.S32.F64",
+ VCVTR_LS_S32_F64: "VCVTR.LS.S32.F64",
+ VCVTR_GE_S32_F64: "VCVTR.GE.S32.F64",
+ VCVTR_LT_S32_F64: "VCVTR.LT.S32.F64",
+ VCVTR_GT_S32_F64: "VCVTR.GT.S32.F64",
+ VCVTR_LE_S32_F64: "VCVTR.LE.S32.F64",
+ VCVTR_S32_F64: "VCVTR.S32.F64",
+ VCVTR_ZZ_S32_F64: "VCVTR.ZZ.S32.F64",
+ VCVT_EQ_U32_F32: "VCVT.EQ.U32.F32",
+ VCVT_NE_U32_F32: "VCVT.NE.U32.F32",
+ VCVT_CS_U32_F32: "VCVT.CS.U32.F32",
+ VCVT_CC_U32_F32: "VCVT.CC.U32.F32",
+ VCVT_MI_U32_F32: "VCVT.MI.U32.F32",
+ VCVT_PL_U32_F32: "VCVT.PL.U32.F32",
+ VCVT_VS_U32_F32: "VCVT.VS.U32.F32",
+ VCVT_VC_U32_F32: "VCVT.VC.U32.F32",
+ VCVT_HI_U32_F32: "VCVT.HI.U32.F32",
+ VCVT_LS_U32_F32: "VCVT.LS.U32.F32",
+ VCVT_GE_U32_F32: "VCVT.GE.U32.F32",
+ VCVT_LT_U32_F32: "VCVT.LT.U32.F32",
+ VCVT_GT_U32_F32: "VCVT.GT.U32.F32",
+ VCVT_LE_U32_F32: "VCVT.LE.U32.F32",
+ VCVT_U32_F32: "VCVT.U32.F32",
+ VCVT_ZZ_U32_F32: "VCVT.ZZ.U32.F32",
+ VCVT_EQ_U32_F64: "VCVT.EQ.U32.F64",
+ VCVT_NE_U32_F64: "VCVT.NE.U32.F64",
+ VCVT_CS_U32_F64: "VCVT.CS.U32.F64",
+ VCVT_CC_U32_F64: "VCVT.CC.U32.F64",
+ VCVT_MI_U32_F64: "VCVT.MI.U32.F64",
+ VCVT_PL_U32_F64: "VCVT.PL.U32.F64",
+ VCVT_VS_U32_F64: "VCVT.VS.U32.F64",
+ VCVT_VC_U32_F64: "VCVT.VC.U32.F64",
+ VCVT_HI_U32_F64: "VCVT.HI.U32.F64",
+ VCVT_LS_U32_F64: "VCVT.LS.U32.F64",
+ VCVT_GE_U32_F64: "VCVT.GE.U32.F64",
+ VCVT_LT_U32_F64: "VCVT.LT.U32.F64",
+ VCVT_GT_U32_F64: "VCVT.GT.U32.F64",
+ VCVT_LE_U32_F64: "VCVT.LE.U32.F64",
+ VCVT_U32_F64: "VCVT.U32.F64",
+ VCVT_ZZ_U32_F64: "VCVT.ZZ.U32.F64",
+ VCVT_EQ_S32_F32: "VCVT.EQ.S32.F32",
+ VCVT_NE_S32_F32: "VCVT.NE.S32.F32",
+ VCVT_CS_S32_F32: "VCVT.CS.S32.F32",
+ VCVT_CC_S32_F32: "VCVT.CC.S32.F32",
+ VCVT_MI_S32_F32: "VCVT.MI.S32.F32",
+ VCVT_PL_S32_F32: "VCVT.PL.S32.F32",
+ VCVT_VS_S32_F32: "VCVT.VS.S32.F32",
+ VCVT_VC_S32_F32: "VCVT.VC.S32.F32",
+ VCVT_HI_S32_F32: "VCVT.HI.S32.F32",
+ VCVT_LS_S32_F32: "VCVT.LS.S32.F32",
+ VCVT_GE_S32_F32: "VCVT.GE.S32.F32",
+ VCVT_LT_S32_F32: "VCVT.LT.S32.F32",
+ VCVT_GT_S32_F32: "VCVT.GT.S32.F32",
+ VCVT_LE_S32_F32: "VCVT.LE.S32.F32",
+ VCVT_S32_F32: "VCVT.S32.F32",
+ VCVT_ZZ_S32_F32: "VCVT.ZZ.S32.F32",
+ VCVT_EQ_S32_F64: "VCVT.EQ.S32.F64",
+ VCVT_NE_S32_F64: "VCVT.NE.S32.F64",
+ VCVT_CS_S32_F64: "VCVT.CS.S32.F64",
+ VCVT_CC_S32_F64: "VCVT.CC.S32.F64",
+ VCVT_MI_S32_F64: "VCVT.MI.S32.F64",
+ VCVT_PL_S32_F64: "VCVT.PL.S32.F64",
+ VCVT_VS_S32_F64: "VCVT.VS.S32.F64",
+ VCVT_VC_S32_F64: "VCVT.VC.S32.F64",
+ VCVT_HI_S32_F64: "VCVT.HI.S32.F64",
+ VCVT_LS_S32_F64: "VCVT.LS.S32.F64",
+ VCVT_GE_S32_F64: "VCVT.GE.S32.F64",
+ VCVT_LT_S32_F64: "VCVT.LT.S32.F64",
+ VCVT_GT_S32_F64: "VCVT.GT.S32.F64",
+ VCVT_LE_S32_F64: "VCVT.LE.S32.F64",
+ VCVT_S32_F64: "VCVT.S32.F64",
+ VCVT_ZZ_S32_F64: "VCVT.ZZ.S32.F64",
+ VDIV_EQ_F32: "VDIV.EQ.F32",
+ VDIV_NE_F32: "VDIV.NE.F32",
+ VDIV_CS_F32: "VDIV.CS.F32",
+ VDIV_CC_F32: "VDIV.CC.F32",
+ VDIV_MI_F32: "VDIV.MI.F32",
+ VDIV_PL_F32: "VDIV.PL.F32",
+ VDIV_VS_F32: "VDIV.VS.F32",
+ VDIV_VC_F32: "VDIV.VC.F32",
+ VDIV_HI_F32: "VDIV.HI.F32",
+ VDIV_LS_F32: "VDIV.LS.F32",
+ VDIV_GE_F32: "VDIV.GE.F32",
+ VDIV_LT_F32: "VDIV.LT.F32",
+ VDIV_GT_F32: "VDIV.GT.F32",
+ VDIV_LE_F32: "VDIV.LE.F32",
+ VDIV_F32: "VDIV.F32",
+ VDIV_ZZ_F32: "VDIV.ZZ.F32",
+ VDIV_EQ_F64: "VDIV.EQ.F64",
+ VDIV_NE_F64: "VDIV.NE.F64",
+ VDIV_CS_F64: "VDIV.CS.F64",
+ VDIV_CC_F64: "VDIV.CC.F64",
+ VDIV_MI_F64: "VDIV.MI.F64",
+ VDIV_PL_F64: "VDIV.PL.F64",
+ VDIV_VS_F64: "VDIV.VS.F64",
+ VDIV_VC_F64: "VDIV.VC.F64",
+ VDIV_HI_F64: "VDIV.HI.F64",
+ VDIV_LS_F64: "VDIV.LS.F64",
+ VDIV_GE_F64: "VDIV.GE.F64",
+ VDIV_LT_F64: "VDIV.LT.F64",
+ VDIV_GT_F64: "VDIV.GT.F64",
+ VDIV_LE_F64: "VDIV.LE.F64",
+ VDIV_F64: "VDIV.F64",
+ VDIV_ZZ_F64: "VDIV.ZZ.F64",
+ VLDR_EQ: "VLDR.EQ",
+ VLDR_NE: "VLDR.NE",
+ VLDR_CS: "VLDR.CS",
+ VLDR_CC: "VLDR.CC",
+ VLDR_MI: "VLDR.MI",
+ VLDR_PL: "VLDR.PL",
+ VLDR_VS: "VLDR.VS",
+ VLDR_VC: "VLDR.VC",
+ VLDR_HI: "VLDR.HI",
+ VLDR_LS: "VLDR.LS",
+ VLDR_GE: "VLDR.GE",
+ VLDR_LT: "VLDR.LT",
+ VLDR_GT: "VLDR.GT",
+ VLDR_LE: "VLDR.LE",
+ VLDR: "VLDR",
+ VLDR_ZZ: "VLDR.ZZ",
+ VMLA_EQ_F32: "VMLA.EQ.F32",
+ VMLA_NE_F32: "VMLA.NE.F32",
+ VMLA_CS_F32: "VMLA.CS.F32",
+ VMLA_CC_F32: "VMLA.CC.F32",
+ VMLA_MI_F32: "VMLA.MI.F32",
+ VMLA_PL_F32: "VMLA.PL.F32",
+ VMLA_VS_F32: "VMLA.VS.F32",
+ VMLA_VC_F32: "VMLA.VC.F32",
+ VMLA_HI_F32: "VMLA.HI.F32",
+ VMLA_LS_F32: "VMLA.LS.F32",
+ VMLA_GE_F32: "VMLA.GE.F32",
+ VMLA_LT_F32: "VMLA.LT.F32",
+ VMLA_GT_F32: "VMLA.GT.F32",
+ VMLA_LE_F32: "VMLA.LE.F32",
+ VMLA_F32: "VMLA.F32",
+ VMLA_ZZ_F32: "VMLA.ZZ.F32",
+ VMLA_EQ_F64: "VMLA.EQ.F64",
+ VMLA_NE_F64: "VMLA.NE.F64",
+ VMLA_CS_F64: "VMLA.CS.F64",
+ VMLA_CC_F64: "VMLA.CC.F64",
+ VMLA_MI_F64: "VMLA.MI.F64",
+ VMLA_PL_F64: "VMLA.PL.F64",
+ VMLA_VS_F64: "VMLA.VS.F64",
+ VMLA_VC_F64: "VMLA.VC.F64",
+ VMLA_HI_F64: "VMLA.HI.F64",
+ VMLA_LS_F64: "VMLA.LS.F64",
+ VMLA_GE_F64: "VMLA.GE.F64",
+ VMLA_LT_F64: "VMLA.LT.F64",
+ VMLA_GT_F64: "VMLA.GT.F64",
+ VMLA_LE_F64: "VMLA.LE.F64",
+ VMLA_F64: "VMLA.F64",
+ VMLA_ZZ_F64: "VMLA.ZZ.F64",
+ VMLS_EQ_F32: "VMLS.EQ.F32",
+ VMLS_NE_F32: "VMLS.NE.F32",
+ VMLS_CS_F32: "VMLS.CS.F32",
+ VMLS_CC_F32: "VMLS.CC.F32",
+ VMLS_MI_F32: "VMLS.MI.F32",
+ VMLS_PL_F32: "VMLS.PL.F32",
+ VMLS_VS_F32: "VMLS.VS.F32",
+ VMLS_VC_F32: "VMLS.VC.F32",
+ VMLS_HI_F32: "VMLS.HI.F32",
+ VMLS_LS_F32: "VMLS.LS.F32",
+ VMLS_GE_F32: "VMLS.GE.F32",
+ VMLS_LT_F32: "VMLS.LT.F32",
+ VMLS_GT_F32: "VMLS.GT.F32",
+ VMLS_LE_F32: "VMLS.LE.F32",
+ VMLS_F32: "VMLS.F32",
+ VMLS_ZZ_F32: "VMLS.ZZ.F32",
+ VMLS_EQ_F64: "VMLS.EQ.F64",
+ VMLS_NE_F64: "VMLS.NE.F64",
+ VMLS_CS_F64: "VMLS.CS.F64",
+ VMLS_CC_F64: "VMLS.CC.F64",
+ VMLS_MI_F64: "VMLS.MI.F64",
+ VMLS_PL_F64: "VMLS.PL.F64",
+ VMLS_VS_F64: "VMLS.VS.F64",
+ VMLS_VC_F64: "VMLS.VC.F64",
+ VMLS_HI_F64: "VMLS.HI.F64",
+ VMLS_LS_F64: "VMLS.LS.F64",
+ VMLS_GE_F64: "VMLS.GE.F64",
+ VMLS_LT_F64: "VMLS.LT.F64",
+ VMLS_GT_F64: "VMLS.GT.F64",
+ VMLS_LE_F64: "VMLS.LE.F64",
+ VMLS_F64: "VMLS.F64",
+ VMLS_ZZ_F64: "VMLS.ZZ.F64",
+ VMOV_EQ: "VMOV.EQ",
+ VMOV_NE: "VMOV.NE",
+ VMOV_CS: "VMOV.CS",
+ VMOV_CC: "VMOV.CC",
+ VMOV_MI: "VMOV.MI",
+ VMOV_PL: "VMOV.PL",
+ VMOV_VS: "VMOV.VS",
+ VMOV_VC: "VMOV.VC",
+ VMOV_HI: "VMOV.HI",
+ VMOV_LS: "VMOV.LS",
+ VMOV_GE: "VMOV.GE",
+ VMOV_LT: "VMOV.LT",
+ VMOV_GT: "VMOV.GT",
+ VMOV_LE: "VMOV.LE",
+ VMOV: "VMOV",
+ VMOV_ZZ: "VMOV.ZZ",
+ VMOV_EQ_32: "VMOV.EQ.32",
+ VMOV_NE_32: "VMOV.NE.32",
+ VMOV_CS_32: "VMOV.CS.32",
+ VMOV_CC_32: "VMOV.CC.32",
+ VMOV_MI_32: "VMOV.MI.32",
+ VMOV_PL_32: "VMOV.PL.32",
+ VMOV_VS_32: "VMOV.VS.32",
+ VMOV_VC_32: "VMOV.VC.32",
+ VMOV_HI_32: "VMOV.HI.32",
+ VMOV_LS_32: "VMOV.LS.32",
+ VMOV_GE_32: "VMOV.GE.32",
+ VMOV_LT_32: "VMOV.LT.32",
+ VMOV_GT_32: "VMOV.GT.32",
+ VMOV_LE_32: "VMOV.LE.32",
+ VMOV_32: "VMOV.32",
+ VMOV_ZZ_32: "VMOV.ZZ.32",
+ VMOV_EQ_F32: "VMOV.EQ.F32",
+ VMOV_NE_F32: "VMOV.NE.F32",
+ VMOV_CS_F32: "VMOV.CS.F32",
+ VMOV_CC_F32: "VMOV.CC.F32",
+ VMOV_MI_F32: "VMOV.MI.F32",
+ VMOV_PL_F32: "VMOV.PL.F32",
+ VMOV_VS_F32: "VMOV.VS.F32",
+ VMOV_VC_F32: "VMOV.VC.F32",
+ VMOV_HI_F32: "VMOV.HI.F32",
+ VMOV_LS_F32: "VMOV.LS.F32",
+ VMOV_GE_F32: "VMOV.GE.F32",
+ VMOV_LT_F32: "VMOV.LT.F32",
+ VMOV_GT_F32: "VMOV.GT.F32",
+ VMOV_LE_F32: "VMOV.LE.F32",
+ VMOV_F32: "VMOV.F32",
+ VMOV_ZZ_F32: "VMOV.ZZ.F32",
+ VMOV_EQ_F64: "VMOV.EQ.F64",
+ VMOV_NE_F64: "VMOV.NE.F64",
+ VMOV_CS_F64: "VMOV.CS.F64",
+ VMOV_CC_F64: "VMOV.CC.F64",
+ VMOV_MI_F64: "VMOV.MI.F64",
+ VMOV_PL_F64: "VMOV.PL.F64",
+ VMOV_VS_F64: "VMOV.VS.F64",
+ VMOV_VC_F64: "VMOV.VC.F64",
+ VMOV_HI_F64: "VMOV.HI.F64",
+ VMOV_LS_F64: "VMOV.LS.F64",
+ VMOV_GE_F64: "VMOV.GE.F64",
+ VMOV_LT_F64: "VMOV.LT.F64",
+ VMOV_GT_F64: "VMOV.GT.F64",
+ VMOV_LE_F64: "VMOV.LE.F64",
+ VMOV_F64: "VMOV.F64",
+ VMOV_ZZ_F64: "VMOV.ZZ.F64",
+ VMRS_EQ: "VMRS.EQ",
+ VMRS_NE: "VMRS.NE",
+ VMRS_CS: "VMRS.CS",
+ VMRS_CC: "VMRS.CC",
+ VMRS_MI: "VMRS.MI",
+ VMRS_PL: "VMRS.PL",
+ VMRS_VS: "VMRS.VS",
+ VMRS_VC: "VMRS.VC",
+ VMRS_HI: "VMRS.HI",
+ VMRS_LS: "VMRS.LS",
+ VMRS_GE: "VMRS.GE",
+ VMRS_LT: "VMRS.LT",
+ VMRS_GT: "VMRS.GT",
+ VMRS_LE: "VMRS.LE",
+ VMRS: "VMRS",
+ VMRS_ZZ: "VMRS.ZZ",
+ VMSR_EQ: "VMSR.EQ",
+ VMSR_NE: "VMSR.NE",
+ VMSR_CS: "VMSR.CS",
+ VMSR_CC: "VMSR.CC",
+ VMSR_MI: "VMSR.MI",
+ VMSR_PL: "VMSR.PL",
+ VMSR_VS: "VMSR.VS",
+ VMSR_VC: "VMSR.VC",
+ VMSR_HI: "VMSR.HI",
+ VMSR_LS: "VMSR.LS",
+ VMSR_GE: "VMSR.GE",
+ VMSR_LT: "VMSR.LT",
+ VMSR_GT: "VMSR.GT",
+ VMSR_LE: "VMSR.LE",
+ VMSR: "VMSR",
+ VMSR_ZZ: "VMSR.ZZ",
+ VMUL_EQ_F32: "VMUL.EQ.F32",
+ VMUL_NE_F32: "VMUL.NE.F32",
+ VMUL_CS_F32: "VMUL.CS.F32",
+ VMUL_CC_F32: "VMUL.CC.F32",
+ VMUL_MI_F32: "VMUL.MI.F32",
+ VMUL_PL_F32: "VMUL.PL.F32",
+ VMUL_VS_F32: "VMUL.VS.F32",
+ VMUL_VC_F32: "VMUL.VC.F32",
+ VMUL_HI_F32: "VMUL.HI.F32",
+ VMUL_LS_F32: "VMUL.LS.F32",
+ VMUL_GE_F32: "VMUL.GE.F32",
+ VMUL_LT_F32: "VMUL.LT.F32",
+ VMUL_GT_F32: "VMUL.GT.F32",
+ VMUL_LE_F32: "VMUL.LE.F32",
+ VMUL_F32: "VMUL.F32",
+ VMUL_ZZ_F32: "VMUL.ZZ.F32",
+ VMUL_EQ_F64: "VMUL.EQ.F64",
+ VMUL_NE_F64: "VMUL.NE.F64",
+ VMUL_CS_F64: "VMUL.CS.F64",
+ VMUL_CC_F64: "VMUL.CC.F64",
+ VMUL_MI_F64: "VMUL.MI.F64",
+ VMUL_PL_F64: "VMUL.PL.F64",
+ VMUL_VS_F64: "VMUL.VS.F64",
+ VMUL_VC_F64: "VMUL.VC.F64",
+ VMUL_HI_F64: "VMUL.HI.F64",
+ VMUL_LS_F64: "VMUL.LS.F64",
+ VMUL_GE_F64: "VMUL.GE.F64",
+ VMUL_LT_F64: "VMUL.LT.F64",
+ VMUL_GT_F64: "VMUL.GT.F64",
+ VMUL_LE_F64: "VMUL.LE.F64",
+ VMUL_F64: "VMUL.F64",
+ VMUL_ZZ_F64: "VMUL.ZZ.F64",
+ VNEG_EQ_F32: "VNEG.EQ.F32",
+ VNEG_NE_F32: "VNEG.NE.F32",
+ VNEG_CS_F32: "VNEG.CS.F32",
+ VNEG_CC_F32: "VNEG.CC.F32",
+ VNEG_MI_F32: "VNEG.MI.F32",
+ VNEG_PL_F32: "VNEG.PL.F32",
+ VNEG_VS_F32: "VNEG.VS.F32",
+ VNEG_VC_F32: "VNEG.VC.F32",
+ VNEG_HI_F32: "VNEG.HI.F32",
+ VNEG_LS_F32: "VNEG.LS.F32",
+ VNEG_GE_F32: "VNEG.GE.F32",
+ VNEG_LT_F32: "VNEG.LT.F32",
+ VNEG_GT_F32: "VNEG.GT.F32",
+ VNEG_LE_F32: "VNEG.LE.F32",
+ VNEG_F32: "VNEG.F32",
+ VNEG_ZZ_F32: "VNEG.ZZ.F32",
+ VNEG_EQ_F64: "VNEG.EQ.F64",
+ VNEG_NE_F64: "VNEG.NE.F64",
+ VNEG_CS_F64: "VNEG.CS.F64",
+ VNEG_CC_F64: "VNEG.CC.F64",
+ VNEG_MI_F64: "VNEG.MI.F64",
+ VNEG_PL_F64: "VNEG.PL.F64",
+ VNEG_VS_F64: "VNEG.VS.F64",
+ VNEG_VC_F64: "VNEG.VC.F64",
+ VNEG_HI_F64: "VNEG.HI.F64",
+ VNEG_LS_F64: "VNEG.LS.F64",
+ VNEG_GE_F64: "VNEG.GE.F64",
+ VNEG_LT_F64: "VNEG.LT.F64",
+ VNEG_GT_F64: "VNEG.GT.F64",
+ VNEG_LE_F64: "VNEG.LE.F64",
+ VNEG_F64: "VNEG.F64",
+ VNEG_ZZ_F64: "VNEG.ZZ.F64",
+ VNMLS_EQ_F32: "VNMLS.EQ.F32",
+ VNMLS_NE_F32: "VNMLS.NE.F32",
+ VNMLS_CS_F32: "VNMLS.CS.F32",
+ VNMLS_CC_F32: "VNMLS.CC.F32",
+ VNMLS_MI_F32: "VNMLS.MI.F32",
+ VNMLS_PL_F32: "VNMLS.PL.F32",
+ VNMLS_VS_F32: "VNMLS.VS.F32",
+ VNMLS_VC_F32: "VNMLS.VC.F32",
+ VNMLS_HI_F32: "VNMLS.HI.F32",
+ VNMLS_LS_F32: "VNMLS.LS.F32",
+ VNMLS_GE_F32: "VNMLS.GE.F32",
+ VNMLS_LT_F32: "VNMLS.LT.F32",
+ VNMLS_GT_F32: "VNMLS.GT.F32",
+ VNMLS_LE_F32: "VNMLS.LE.F32",
+ VNMLS_F32: "VNMLS.F32",
+ VNMLS_ZZ_F32: "VNMLS.ZZ.F32",
+ VNMLS_EQ_F64: "VNMLS.EQ.F64",
+ VNMLS_NE_F64: "VNMLS.NE.F64",
+ VNMLS_CS_F64: "VNMLS.CS.F64",
+ VNMLS_CC_F64: "VNMLS.CC.F64",
+ VNMLS_MI_F64: "VNMLS.MI.F64",
+ VNMLS_PL_F64: "VNMLS.PL.F64",
+ VNMLS_VS_F64: "VNMLS.VS.F64",
+ VNMLS_VC_F64: "VNMLS.VC.F64",
+ VNMLS_HI_F64: "VNMLS.HI.F64",
+ VNMLS_LS_F64: "VNMLS.LS.F64",
+ VNMLS_GE_F64: "VNMLS.GE.F64",
+ VNMLS_LT_F64: "VNMLS.LT.F64",
+ VNMLS_GT_F64: "VNMLS.GT.F64",
+ VNMLS_LE_F64: "VNMLS.LE.F64",
+ VNMLS_F64: "VNMLS.F64",
+ VNMLS_ZZ_F64: "VNMLS.ZZ.F64",
+ VNMLA_EQ_F32: "VNMLA.EQ.F32",
+ VNMLA_NE_F32: "VNMLA.NE.F32",
+ VNMLA_CS_F32: "VNMLA.CS.F32",
+ VNMLA_CC_F32: "VNMLA.CC.F32",
+ VNMLA_MI_F32: "VNMLA.MI.F32",
+ VNMLA_PL_F32: "VNMLA.PL.F32",
+ VNMLA_VS_F32: "VNMLA.VS.F32",
+ VNMLA_VC_F32: "VNMLA.VC.F32",
+ VNMLA_HI_F32: "VNMLA.HI.F32",
+ VNMLA_LS_F32: "VNMLA.LS.F32",
+ VNMLA_GE_F32: "VNMLA.GE.F32",
+ VNMLA_LT_F32: "VNMLA.LT.F32",
+ VNMLA_GT_F32: "VNMLA.GT.F32",
+ VNMLA_LE_F32: "VNMLA.LE.F32",
+ VNMLA_F32: "VNMLA.F32",
+ VNMLA_ZZ_F32: "VNMLA.ZZ.F32",
+ VNMLA_EQ_F64: "VNMLA.EQ.F64",
+ VNMLA_NE_F64: "VNMLA.NE.F64",
+ VNMLA_CS_F64: "VNMLA.CS.F64",
+ VNMLA_CC_F64: "VNMLA.CC.F64",
+ VNMLA_MI_F64: "VNMLA.MI.F64",
+ VNMLA_PL_F64: "VNMLA.PL.F64",
+ VNMLA_VS_F64: "VNMLA.VS.F64",
+ VNMLA_VC_F64: "VNMLA.VC.F64",
+ VNMLA_HI_F64: "VNMLA.HI.F64",
+ VNMLA_LS_F64: "VNMLA.LS.F64",
+ VNMLA_GE_F64: "VNMLA.GE.F64",
+ VNMLA_LT_F64: "VNMLA.LT.F64",
+ VNMLA_GT_F64: "VNMLA.GT.F64",
+ VNMLA_LE_F64: "VNMLA.LE.F64",
+ VNMLA_F64: "VNMLA.F64",
+ VNMLA_ZZ_F64: "VNMLA.ZZ.F64",
+ VNMUL_EQ_F32: "VNMUL.EQ.F32",
+ VNMUL_NE_F32: "VNMUL.NE.F32",
+ VNMUL_CS_F32: "VNMUL.CS.F32",
+ VNMUL_CC_F32: "VNMUL.CC.F32",
+ VNMUL_MI_F32: "VNMUL.MI.F32",
+ VNMUL_PL_F32: "VNMUL.PL.F32",
+ VNMUL_VS_F32: "VNMUL.VS.F32",
+ VNMUL_VC_F32: "VNMUL.VC.F32",
+ VNMUL_HI_F32: "VNMUL.HI.F32",
+ VNMUL_LS_F32: "VNMUL.LS.F32",
+ VNMUL_GE_F32: "VNMUL.GE.F32",
+ VNMUL_LT_F32: "VNMUL.LT.F32",
+ VNMUL_GT_F32: "VNMUL.GT.F32",
+ VNMUL_LE_F32: "VNMUL.LE.F32",
+ VNMUL_F32: "VNMUL.F32",
+ VNMUL_ZZ_F32: "VNMUL.ZZ.F32",
+ VNMUL_EQ_F64: "VNMUL.EQ.F64",
+ VNMUL_NE_F64: "VNMUL.NE.F64",
+ VNMUL_CS_F64: "VNMUL.CS.F64",
+ VNMUL_CC_F64: "VNMUL.CC.F64",
+ VNMUL_MI_F64: "VNMUL.MI.F64",
+ VNMUL_PL_F64: "VNMUL.PL.F64",
+ VNMUL_VS_F64: "VNMUL.VS.F64",
+ VNMUL_VC_F64: "VNMUL.VC.F64",
+ VNMUL_HI_F64: "VNMUL.HI.F64",
+ VNMUL_LS_F64: "VNMUL.LS.F64",
+ VNMUL_GE_F64: "VNMUL.GE.F64",
+ VNMUL_LT_F64: "VNMUL.LT.F64",
+ VNMUL_GT_F64: "VNMUL.GT.F64",
+ VNMUL_LE_F64: "VNMUL.LE.F64",
+ VNMUL_F64: "VNMUL.F64",
+ VNMUL_ZZ_F64: "VNMUL.ZZ.F64",
+ VSQRT_EQ_F32: "VSQRT.EQ.F32",
+ VSQRT_NE_F32: "VSQRT.NE.F32",
+ VSQRT_CS_F32: "VSQRT.CS.F32",
+ VSQRT_CC_F32: "VSQRT.CC.F32",
+ VSQRT_MI_F32: "VSQRT.MI.F32",
+ VSQRT_PL_F32: "VSQRT.PL.F32",
+ VSQRT_VS_F32: "VSQRT.VS.F32",
+ VSQRT_VC_F32: "VSQRT.VC.F32",
+ VSQRT_HI_F32: "VSQRT.HI.F32",
+ VSQRT_LS_F32: "VSQRT.LS.F32",
+ VSQRT_GE_F32: "VSQRT.GE.F32",
+ VSQRT_LT_F32: "VSQRT.LT.F32",
+ VSQRT_GT_F32: "VSQRT.GT.F32",
+ VSQRT_LE_F32: "VSQRT.LE.F32",
+ VSQRT_F32: "VSQRT.F32",
+ VSQRT_ZZ_F32: "VSQRT.ZZ.F32",
+ VSQRT_EQ_F64: "VSQRT.EQ.F64",
+ VSQRT_NE_F64: "VSQRT.NE.F64",
+ VSQRT_CS_F64: "VSQRT.CS.F64",
+ VSQRT_CC_F64: "VSQRT.CC.F64",
+ VSQRT_MI_F64: "VSQRT.MI.F64",
+ VSQRT_PL_F64: "VSQRT.PL.F64",
+ VSQRT_VS_F64: "VSQRT.VS.F64",
+ VSQRT_VC_F64: "VSQRT.VC.F64",
+ VSQRT_HI_F64: "VSQRT.HI.F64",
+ VSQRT_LS_F64: "VSQRT.LS.F64",
+ VSQRT_GE_F64: "VSQRT.GE.F64",
+ VSQRT_LT_F64: "VSQRT.LT.F64",
+ VSQRT_GT_F64: "VSQRT.GT.F64",
+ VSQRT_LE_F64: "VSQRT.LE.F64",
+ VSQRT_F64: "VSQRT.F64",
+ VSQRT_ZZ_F64: "VSQRT.ZZ.F64",
+ VSTR_EQ: "VSTR.EQ",
+ VSTR_NE: "VSTR.NE",
+ VSTR_CS: "VSTR.CS",
+ VSTR_CC: "VSTR.CC",
+ VSTR_MI: "VSTR.MI",
+ VSTR_PL: "VSTR.PL",
+ VSTR_VS: "VSTR.VS",
+ VSTR_VC: "VSTR.VC",
+ VSTR_HI: "VSTR.HI",
+ VSTR_LS: "VSTR.LS",
+ VSTR_GE: "VSTR.GE",
+ VSTR_LT: "VSTR.LT",
+ VSTR_GT: "VSTR.GT",
+ VSTR_LE: "VSTR.LE",
+ VSTR: "VSTR",
+ VSTR_ZZ: "VSTR.ZZ",
+ VSUB_EQ_F32: "VSUB.EQ.F32",
+ VSUB_NE_F32: "VSUB.NE.F32",
+ VSUB_CS_F32: "VSUB.CS.F32",
+ VSUB_CC_F32: "VSUB.CC.F32",
+ VSUB_MI_F32: "VSUB.MI.F32",
+ VSUB_PL_F32: "VSUB.PL.F32",
+ VSUB_VS_F32: "VSUB.VS.F32",
+ VSUB_VC_F32: "VSUB.VC.F32",
+ VSUB_HI_F32: "VSUB.HI.F32",
+ VSUB_LS_F32: "VSUB.LS.F32",
+ VSUB_GE_F32: "VSUB.GE.F32",
+ VSUB_LT_F32: "VSUB.LT.F32",
+ VSUB_GT_F32: "VSUB.GT.F32",
+ VSUB_LE_F32: "VSUB.LE.F32",
+ VSUB_F32: "VSUB.F32",
+ VSUB_ZZ_F32: "VSUB.ZZ.F32",
+ VSUB_EQ_F64: "VSUB.EQ.F64",
+ VSUB_NE_F64: "VSUB.NE.F64",
+ VSUB_CS_F64: "VSUB.CS.F64",
+ VSUB_CC_F64: "VSUB.CC.F64",
+ VSUB_MI_F64: "VSUB.MI.F64",
+ VSUB_PL_F64: "VSUB.PL.F64",
+ VSUB_VS_F64: "VSUB.VS.F64",
+ VSUB_VC_F64: "VSUB.VC.F64",
+ VSUB_HI_F64: "VSUB.HI.F64",
+ VSUB_LS_F64: "VSUB.LS.F64",
+ VSUB_GE_F64: "VSUB.GE.F64",
+ VSUB_LT_F64: "VSUB.LT.F64",
+ VSUB_GT_F64: "VSUB.GT.F64",
+ VSUB_LE_F64: "VSUB.LE.F64",
+ VSUB_F64: "VSUB.F64",
+ VSUB_ZZ_F64: "VSUB.ZZ.F64",
+ WFE_EQ: "WFE.EQ",
+ WFE_NE: "WFE.NE",
+ WFE_CS: "WFE.CS",
+ WFE_CC: "WFE.CC",
+ WFE_MI: "WFE.MI",
+ WFE_PL: "WFE.PL",
+ WFE_VS: "WFE.VS",
+ WFE_VC: "WFE.VC",
+ WFE_HI: "WFE.HI",
+ WFE_LS: "WFE.LS",
+ WFE_GE: "WFE.GE",
+ WFE_LT: "WFE.LT",
+ WFE_GT: "WFE.GT",
+ WFE_LE: "WFE.LE",
+ WFE: "WFE",
+ WFE_ZZ: "WFE.ZZ",
+ WFI_EQ: "WFI.EQ",
+ WFI_NE: "WFI.NE",
+ WFI_CS: "WFI.CS",
+ WFI_CC: "WFI.CC",
+ WFI_MI: "WFI.MI",
+ WFI_PL: "WFI.PL",
+ WFI_VS: "WFI.VS",
+ WFI_VC: "WFI.VC",
+ WFI_HI: "WFI.HI",
+ WFI_LS: "WFI.LS",
+ WFI_GE: "WFI.GE",
+ WFI_LT: "WFI.LT",
+ WFI_GT: "WFI.GT",
+ WFI_LE: "WFI.LE",
+ WFI: "WFI",
+ WFI_ZZ: "WFI.ZZ",
+ YIELD_EQ: "YIELD.EQ",
+ YIELD_NE: "YIELD.NE",
+ YIELD_CS: "YIELD.CS",
+ YIELD_CC: "YIELD.CC",
+ YIELD_MI: "YIELD.MI",
+ YIELD_PL: "YIELD.PL",
+ YIELD_VS: "YIELD.VS",
+ YIELD_VC: "YIELD.VC",
+ YIELD_HI: "YIELD.HI",
+ YIELD_LS: "YIELD.LS",
+ YIELD_GE: "YIELD.GE",
+ YIELD_LT: "YIELD.LT",
+ YIELD_GT: "YIELD.GT",
+ YIELD_LE: "YIELD.LE",
+ YIELD: "YIELD",
+ YIELD_ZZ: "YIELD.ZZ",
+}
+
+var instFormats = [...]instFormat{
+ {0x0fe00000, 0x02a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00a00010, 4, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00a00000, 2, ADC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fe00000, 0x02800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ADD{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00800010, 4, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00800000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fef0000, 0x028d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // ADD{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12
+ {0x0fef0010, 0x008d0000, 2, ADD_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // ADD{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fe00000, 0x02000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // AND{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00000010, 4, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // AND{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00000000, 2, AND_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // AND{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fef0070, 0x01a00040, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // ASR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4
+ {0x0fef00f0, 0x01a00050, 4, ASR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ASR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4
+ {0x0f000000, 0x0a000000, 4, B_EQ, 0x1c04, instArgs{arg_label24}}, // B<c> <label24> cond:4|1|0|1|0|imm24:24
+ {0x0fe0007f, 0x07c0001f, 4, BFC_EQ, 0x1c04, instArgs{arg_R_12, arg_imm5, arg_lsb_width}}, // BFC<c> <Rd>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1
+ {0x0fe00070, 0x07c00010, 2, BFI_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_lsb_width}}, // BFI<c> <Rd>,<Rn>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4
+ {0x0fe00000, 0x03c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // BIC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x01c00010, 4, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x01c00000, 2, BIC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0ff000f0, 0x01200070, 4, BKPT_EQ, 0x1c04, instArgs{arg_imm_12at8_4at0}}, // BKPT<c> #<imm12+4> cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4
+ {0x0f000000, 0x0b000000, 4, BL_EQ, 0x1c04, instArgs{arg_label24}}, // BL<c> <label24> cond:4|1|0|1|1|imm24:24
+ {0xfe000000, 0xfa000000, 4, BLX, 0x0, instArgs{arg_label24H}}, // BLX <label24H> 1|1|1|1|1|0|1|H|imm24:24
+ {0x0ffffff0, 0x012fff30, 4, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x012fff30, 3, BLX_EQ, 0x1c04, instArgs{arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ffffff0, 0x012fff10, 4, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x012fff10, 3, BX_EQ, 0x1c04, instArgs{arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ffffff0, 0x012fff20, 4, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4
+ {0x0ff000f0, 0x012fff20, 3, BXJ_EQ, 0x1c04, instArgs{arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4
+ {0xffffffff, 0xf57ff01f, 4, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1)
+ {0xfff000f0, 0xf57ff01f, 3, CLREX, 0x0, instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1)
+ {0x0fff0ff0, 0x016f0f10, 4, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x016f0f10, 3, CLZ_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff0f000, 0x03700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff00000, 0x03700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff0f090, 0x01700010, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff00090, 0x01700010, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff0f010, 0x01700000, 4, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff00010, 0x01700000, 3, CMN_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff0f000, 0x03500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff00000, 0x03500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff0f090, 0x01500010, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff00090, 0x01500010, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff0f010, 0x01500000, 4, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff00010, 0x01500000, 3, CMP_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ffffff0, 0x0320f0f0, 4, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4
+ {0x0fff00f0, 0x0320f0f0, 3, DBG_EQ, 0x1c04, instArgs{arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4
+ {0xfffffff0, 0xf57ff050, 4, DMB, 0x0, instArgs{arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4
+ {0xfff000f0, 0xf57ff050, 3, DMB, 0x0, instArgs{arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4
+ {0xfffffff0, 0xf57ff040, 4, DSB, 0x0, instArgs{arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4
+ {0xfff000f0, 0xf57ff040, 3, DSB, 0x0, instArgs{arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4
+ {0x0fe00000, 0x02200000, 2, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // EOR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00200010, 4, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00200000, 2, EOR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0xfffffff0, 0xf57ff060, 4, ISB, 0x0, instArgs{arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4
+ {0xfff000f0, 0xf57ff060, 3, ISB, 0x0, instArgs{arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4
+ {0x0fd00000, 0x08900000, 2, LDM_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16
+ {0x0fd00000, 0x08100000, 4, LDMDA_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16
+ {0x0fd00000, 0x09100000, 4, LDMDB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16
+ {0x0fd00000, 0x09900000, 4, LDMIB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // LDMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16
+ {0x0f7f0000, 0x051f0000, 4, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12
+ {0x0e5f0000, 0x051f0000, 3, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12
+ {0x0e500010, 0x06100000, 2, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // LDR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0e500000, 0x04100000, 2, LDR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // LDR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12
+ {0x0f7f0000, 0x055f0000, 4, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12
+ {0x0e5f0000, 0x055f0000, 3, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12
+ {0x0e500010, 0x06500000, 2, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // LDRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0e500000, 0x04500000, 2, LDRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // LDRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12
+ {0x0f700000, 0x04700000, 4, LDRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // LDRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12
+ {0x0f700010, 0x06700000, 4, LDRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // LDRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0e500ff0, 0x000000d0, 4, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4
+ {0x0e5000f0, 0x000000d0, 3, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4
+ {0x0e5000f0, 0x004000d0, 2, LDRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_imm8_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4
+ {0x0ff00fff, 0x01900f9f, 4, LDREX_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff000f0, 0x01900f9f, 3, LDREX_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff00fff, 0x01d00f9f, 4, LDREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff000f0, 0x01d00f9f, 3, LDREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff00fff, 0x01b00f9f, 4, LDREXD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff000f0, 0x01b00f9f, 3, LDREXD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff00fff, 0x01f00f9f, 4, LDREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0ff000f0, 0x01f00f9f, 3, LDREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1)
+ {0x0e500ff0, 0x001000b0, 2, LDRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
+ {0x0e5000f0, 0x005000b0, 2, LDRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
+ {0x0f7000f0, 0x007000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
+ {0x0f700ff0, 0x003000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
+ {0x0e500ff0, 0x001000d0, 2, LDRSB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRSB<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4
+ {0x0e5000f0, 0x005000d0, 2, LDRSB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRSB<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4
+ {0x0f7000f0, 0x007000d0, 4, LDRSBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRSBT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4
+ {0x0f700ff0, 0x003000d0, 4, LDRSBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRSBT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4
+ {0x0e500ff0, 0x001000f0, 2, LDRSH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // LDRSH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4
+ {0x0e5000f0, 0x005000f0, 2, LDRSH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // LDRSH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4
+ {0x0f7000f0, 0x007000f0, 4, LDRSHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // LDRSHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4
+ {0x0f700ff0, 0x003000f0, 4, LDRSHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // LDRSHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4
+ {0x0f700000, 0x04300000, 4, LDRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // LDRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12
+ {0x0f700010, 0x06300000, 4, LDRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // LDRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0fef0070, 0x01a00000, 2, LSL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_nz}}, // LSL{S}<c> <Rd>,<Rm>,#<imm5_nz> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4
+ {0x0fef00f0, 0x01a00010, 4, LSL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // LSL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4
+ {0x0fef0070, 0x01a00020, 4, LSR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5_32}}, // LSR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4
+ {0x0fef00f0, 0x01a00030, 4, LSR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // LSR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4
+ {0x0fe000f0, 0x00200090, 4, MLA_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // MLA{S}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4
+ {0x0ff000f0, 0x00600090, 4, MLS_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // MLS<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4
+ {0x0ff00000, 0x03400000, 4, MOVT_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}}, // MOVT<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12
+ {0x0ff00000, 0x03000000, 4, MOVW_EQ, 0x1c04, instArgs{arg_R_12, arg_imm_4at16_12at0}}, // MOVW<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12
+ {0x0fef0000, 0x03a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MOV{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12
+ {0x0fef0ff0, 0x01a00000, 2, MOV_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // MOV{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4
+ {0x0fff0fff, 0x010f0000, 4, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0)
+ {0x0ff000f0, 0x010f0000, 3, MRS_EQ, 0x1c04, instArgs{arg_R_12, arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0)
+ {0x0fe0f0f0, 0x00000090, 4, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4
+ {0x0fe000f0, 0x00000090, 3, MUL_EQ, 0x14011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4
+ {0x0fef0000, 0x03e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12
+ {0x0fe00000, 0x03e00000, 1, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12
+ {0x0fef0090, 0x01e00010, 4, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00090, 0x01e00010, 3, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fef0010, 0x01e00000, 2, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fe00010, 0x01e00000, 1, MVN_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fffffff, 0x0320f000, 4, NOP_EQ, 0x1c04, instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0
+ {0x0fff00ff, 0x0320f000, 3, NOP_EQ, 0x1c04, instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0
+ {0x0fe00000, 0x03800000, 2, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // ORR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x01800010, 4, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x01800000, 2, ORR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0ff00030, 0x06800010, 4, PKHBT_EQ, 0x6011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // PKH<BT,TB><c> <Rd>,<Rn>,<Rm>{,LSL #<imm5>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4
+ {0xff7ff000, 0xf55ff000, 4, PLD, 0x0, instArgs{arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12
+ {0xff3f0000, 0xf55ff000, 3, PLD, 0x0, instArgs{arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12
+ {0xff30f000, 0xf510f000, 2, PLD_W, 0x1601, instArgs{arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
+ {0xff300000, 0xf510f000, 1, PLD_W, 0x1601, instArgs{arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
+ {0xff30f010, 0xf710f000, 4, PLD_W, 0x1601, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
+ {0xff300010, 0xf710f000, 3, PLD_W, 0x1601, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
+ {0xff70f000, 0xf450f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
+ {0xff700000, 0xf450f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12
+ {0xff70f010, 0xf650f000, 4, PLI, 0x0, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
+ {0xff700010, 0xf650f000, 3, PLI, 0x0, instArgs{arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4
+ {0x0fff0000, 0x08bd0000, 4, POP_EQ, 0x1c04, instArgs{arg_registers2}}, // POP<c> <registers2> cond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16
+ {0x0fff0fff, 0x049d0004, 4, POP_EQ, 0x1c04, instArgs{arg_registers1}}, // POP<c> <registers1> cond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0
+ {0x0fff0000, 0x092d0000, 4, PUSH_EQ, 0x1c04, instArgs{arg_registers2}}, // PUSH<c> <registers2> cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16
+ {0x0fff0fff, 0x052d0004, 4, PUSH_EQ, 0x1c04, instArgs{arg_registers1}}, // PUSH<c> <registers1> cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0
+ {0x0ff00ff0, 0x06200f10, 4, QADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x06200f10, 3, QADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06200f90, 4, QADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff000f0, 0x06200f90, 3, QADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff00ff0, 0x01000050, 4, QADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x01000050, 3, QADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06200f30, 4, QASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06200f30, 3, QASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff00ff0, 0x01400050, 4, QDADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x01400050, 3, QDADD_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x01600050, 4, QDSUB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QDSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06200f50, 4, QSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x06200f50, 3, QSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06200f70, 4, QSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff000f0, 0x06200f70, 3, QSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff00ff0, 0x06200ff0, 4, QSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x06200ff0, 3, QSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff00ff0, 0x01200050, 4, QSUB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_R_16}}, // QSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4
+ {0x0fff0ff0, 0x06ff0f30, 4, RBIT_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06ff0f30, 3, RBIT_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0fff0ff0, 0x06bf0fb0, 4, REV16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
+ {0x0ff000f0, 0x06bf0fb0, 3, REV16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
+ {0x0fff0ff0, 0x06bf0f30, 4, REV_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06bf0f30, 3, REV_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0fff0ff0, 0x06ff0fb0, 4, REVSH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
+ {0x0ff000f0, 0x06ff0fb0, 3, REVSH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
+ {0x0fef0070, 0x01a00060, 2, ROR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_imm5}}, // ROR{S}<c> <Rd>,<Rm>,#<imm5> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4
+ {0x0fef00f0, 0x01a00070, 4, ROR_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0, arg_R_8}}, // ROR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4
+ {0x0fef0ff0, 0x01a00060, 4, RRX_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_0}}, // RRX{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4
+ {0x0fe00000, 0x02600000, 2, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // RSB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00600010, 4, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00600000, 2, RSB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fe00000, 0x02e00000, 2, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // RSC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00e00010, 4, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00e00000, 2, RSC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0ff00ff0, 0x06100f10, 4, SADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x06100f10, 3, SADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06100f90, 4, SADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff000f0, 0x06100f90, 3, SADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06100f30, 4, SASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06100f30, 3, SASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0fe00000, 0x02c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // SBC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00c00010, 4, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fe00070, 0x07a00050, 4, SBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4
+ {0x0ff00ff0, 0x06800fb0, 4, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
+ {0x0ff000f0, 0x06800fb0, 3, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
+ {0xfffffdff, 0xf1010000, 4, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)
+ {0xfffffc00, 0xf1010000, 3, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)
+ {0x0fffffff, 0x0320f004, 4, SEV_EQ, 0x1c04, instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0
+ {0x0fff00ff, 0x0320f004, 3, SEV_EQ, 0x1c04, instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0
+ {0x0ff00ff0, 0x06300f10, 4, SHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x06300f10, 3, SHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06300f90, 4, SHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff000f0, 0x06300f90, 3, SHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06300f30, 4, SHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06300f30, 3, SHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff00ff0, 0x06300f50, 4, SHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x06300f50, 3, SHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06300f70, 4, SHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff000f0, 0x06300f70, 3, SHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff00ff0, 0x06300ff0, 4, SHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x06300ff0, 3, SHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff00090, 0x01000080, 4, SMLABB_EQ, 0x50106011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4
+ {0x0ff000d0, 0x07000010, 2, SMLAD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLAD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4
+ {0x0ff00090, 0x01400080, 4, SMLALBB_EQ, 0x50106011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLAL<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4
+ {0x0ff000d0, 0x07400010, 4, SMLALD_EQ, 0x5011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLALD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4
+ {0x0fe000f0, 0x00e00090, 4, SMLAL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
+ {0x0ff000b0, 0x01200080, 4, SMLAWB_EQ, 0x6011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLAW<y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4
+ {0x0ff000d0, 0x07000050, 2, SMLSD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMLSD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4
+ {0x0ff000d0, 0x07400050, 4, SMLSLD_EQ, 0x5011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMLSLD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4
+ {0x0ff000d0, 0x07500010, 2, SMMLA_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMMLA{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4
+ {0x0ff000d0, 0x075000d0, 4, SMMLS_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // SMMLS{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4
+ {0x0ff0f0d0, 0x0750f010, 4, SMMUL_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMMUL{R}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4
+ {0x0ff0f0d0, 0x0700f010, 4, SMUAD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUAD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4
+ {0x0ff0f090, 0x01600080, 4, SMULBB_EQ, 0x50106011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUL<x><y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4
+ {0x0fe000f0, 0x00c00090, 4, SMULL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // SMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
+ {0x0ff0f0b0, 0x012000a0, 4, SMULWB_EQ, 0x6011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMULW<y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4
+ {0x0ff0f0d0, 0x0700f050, 4, SMUSD_EQ, 0x5011c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SMUSD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4
+ {0x0ff00ff0, 0x06a00f30, 4, SSAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4m1, arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
+ {0x0ff000f0, 0x06a00f30, 3, SSAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4m1, arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
+ {0x0fe00030, 0x06a00010, 4, SSAT_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm5m1, arg_R_shift_imm}}, // SSAT<c> <Rd>,#<sat_imm5m1>,<Rn>{,<shift>} cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4
+ {0x0ff00ff0, 0x06100f50, 4, SSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x06100f50, 3, SSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06100f70, 4, SSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff000f0, 0x06100f70, 3, SSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff00ff0, 0x06100ff0, 4, SSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x06100ff0, 3, SSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0fd00000, 0x08800000, 4, STM_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16
+ {0x0fd00000, 0x08000000, 4, STMDA_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16
+ {0x0fd00000, 0x09000000, 2, STMDB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16
+ {0x0fd00000, 0x09800000, 4, STMIB_EQ, 0x1c04, instArgs{arg_R_16_WB, arg_registers}}, // STMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16
+ {0x0e500018, 0x06000000, 2, STR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // STR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0e500000, 0x04000000, 2, STR_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12
+ {0x0e500010, 0x06400000, 2, STRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_W}}, // STRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0e500000, 0x04400000, 2, STRB_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_W}}, // STRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12
+ {0x0f700000, 0x04600000, 4, STRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // STRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12
+ {0x0f700010, 0x06600000, 4, STRBT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // STRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0e500ff0, 0x000000f0, 4, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4
+ {0x0e5000f0, 0x000000f0, 3, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4
+ {0x0e5000f0, 0x004000f0, 4, STRD_EQ, 0x1c04, instArgs{arg_R1_12, arg_R2_12, arg_mem_R_pm_imm8_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4
+ {0x0ff00ff0, 0x01800f90, 4, STREX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREX<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
+ {0x0ff00ff0, 0x01c00f90, 4, STREXB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREXB<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
+ {0x0ff00ff0, 0x01a00f90, 4, STREXD_EQ, 0x1c04, instArgs{arg_R_12, arg_R1_0, arg_R2_0, arg_mem_R}}, // STREXD<c> <Rd>,<Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
+ {0x0ff00ff0, 0x01e00f90, 4, STREXH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // STREXH<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4
+ {0x0e500ff0, 0x000000b0, 2, STRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_W}}, // STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
+ {0x0e5000f0, 0x004000b0, 2, STRH_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_W}}, // STRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
+ {0x0f7000f0, 0x006000b0, 4, STRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}}, // STRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4
+ {0x0f700ff0, 0x002000b0, 4, STRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_postindex}}, // STRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4
+ {0x0f700000, 0x04200000, 4, STRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm12_postindex}}, // STRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12
+ {0x0f700010, 0x06200000, 4, STRT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_R_shift_imm_postindex}}, // STRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4
+ {0x0fe00000, 0x02400000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_const}}, // SUB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12
+ {0x0fe00090, 0x00400010, 4, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
+ {0x0fe00010, 0x00400000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0fef0000, 0x024d0000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_const}}, // SUB{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12
+ {0x0fef0010, 0x004d0000, 2, SUB_EQ, 0x14011c04, instArgs{arg_R_12, arg_SP, arg_R_shift_imm}}, // SUB{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4
+ {0x0f000000, 0x0f000000, 4, SVC_EQ, 0x1c04, instArgs{arg_imm24}}, // SVC<c> #<imm24> cond:4|1|1|1|1|imm24:24
+ {0x0fb00ff0, 0x01000090, 4, SWP_EQ, 0x16011c04, instArgs{arg_R_12, arg_R_0, arg_mem_R}}, // SWP{B}<c> <Rt>,<Rm>,[<Rn>] cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4
+ {0x0ff003f0, 0x06800070, 2, SXTAB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0ff003f0, 0x06a00070, 2, SXTAB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0ff003f0, 0x06b00070, 2, SXTAH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fff03f0, 0x068f0070, 4, SXTB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fff03f0, 0x06af0070, 4, SXTB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fff03f0, 0x06bf0070, 4, SXTH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // SXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0ff0f000, 0x03300000, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff00000, 0x03300000, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff0f090, 0x01300010, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff00090, 0x01300010, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff0f010, 0x01300000, 4, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff00010, 0x01300000, 3, TEQ_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff0f000, 0x03100000, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff00000, 0x03100000, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12
+ {0x0ff0f090, 0x01100010, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff00090, 0x01100010, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4
+ {0x0ff0f010, 0x01100000, 4, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff00010, 0x01100000, 3, TST_EQ, 0x1c04, instArgs{arg_R_16, arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4
+ {0x0ff00ff0, 0x06500f10, 4, UADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x06500f10, 3, UADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06500f90, 4, UADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff000f0, 0x06500f90, 3, UADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06500f30, 4, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06500f30, 3, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0fe00070, 0x07e00050, 4, UBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4
+ {0x0ff00ff0, 0x06700f10, 4, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x06700f10, 3, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06700f90, 4, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff000f0, 0x06700f90, 3, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06700f30, 4, UHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06700f30, 3, UHASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff00ff0, 0x06700f50, 4, UHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x06700f50, 3, UHSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06700f70, 4, UHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff000f0, 0x06700f70, 3, UHSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff00ff0, 0x06700ff0, 4, UHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x06700ff0, 3, UHSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x00400090, 4, UMAAL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
+ {0x0fe000f0, 0x00a00090, 4, UMLAL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
+ {0x0fe000f0, 0x00800090, 4, UMULL_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_0, arg_R_8}}, // UMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4
+ {0x0ff00ff0, 0x06600f10, 4, UQADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff000f0, 0x06600f10, 3, UQADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06600f90, 4, UQADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff000f0, 0x06600f90, 3, UQADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4
+ {0x0ff00ff0, 0x06600f30, 4, UQASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff000f0, 0x06600f30, 3, UQASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
+ {0x0ff00ff0, 0x06600f50, 4, UQSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x06600f50, 3, UQSAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06600f70, 4, UQSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff000f0, 0x06600f70, 3, UQSUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff00ff0, 0x06600ff0, 4, UQSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x06600ff0, 3, UQSUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff0f0f0, 0x0780f010, 4, USAD8_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // USAD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4
+ {0x0ff000f0, 0x07800010, 2, USADA8_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8, arg_R_12}}, // USADA8<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4
+ {0x0ff00ff0, 0x06e00f30, 4, USAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4, arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
+ {0x0ff000f0, 0x06e00f30, 3, USAT16_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm4, arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4
+ {0x0fe00030, 0x06e00010, 4, USAT_EQ, 0x1c04, instArgs{arg_R_12, arg_satimm5, arg_R_shift_imm}}, // USAT<c> <Rd>,#<sat_imm5>,<Rn>{,<shift>} cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4
+ {0x0ff00ff0, 0x06500f50, 4, USAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff000f0, 0x06500f50, 3, USAX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4
+ {0x0ff00ff0, 0x06500f70, 4, USUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff000f0, 0x06500f70, 3, USUB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4
+ {0x0ff00ff0, 0x06500ff0, 4, USUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff000f0, 0x06500ff0, 3, USUB8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4
+ {0x0ff003f0, 0x06c00070, 2, UXTAB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0ff003f0, 0x06e00070, 2, UXTAB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0ff003f0, 0x06f00070, 2, UXTAH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_rotate}}, // UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fff03f0, 0x06cf0070, 4, UXTB16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fff03f0, 0x06ef0070, 4, UXTB_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fff03f0, 0x06ff0070, 4, UXTH_EQ, 0x1c04, instArgs{arg_R_12, arg_R_rotate}}, // UXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4
+ {0x0fb00e10, 0x0e000a00, 4, VMLA_EQ_F32, 0x60108011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // V<MLA,MLS><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4
+ {0x0fbf0ed0, 0x0eb00ac0, 4, VABS_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VABS<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|1|1|M|0|Vm:4
+ {0x0fb00e50, 0x0e300a00, 4, VADD_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VADD<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4
+ {0x0fbf0e7f, 0x0eb50a40, 4, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0)
+ {0x0fbf0e70, 0x0eb50a40, 3, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0)
+ {0x0fbf0e50, 0x0eb40a40, 4, VCMP_EQ_F32, 0x70108011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|0|0|Vd:4|1|0|1|sz|E|1|M|0|Vm:4
+ {0x0fbe0e50, 0x0eba0a40, 4, VCVT_EQ_F32_FXS16, 0x801100107011c04, instArgs{arg_Sd_Dd, arg_Sd_Dd, arg_fbits}}, // VCVT<c>.F<32,64>.FX<S,U><16,32> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|0|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4
+ {0x0fbe0e50, 0x0ebe0a40, 4, VCVT_EQ_FXS16_F32, 0x1001070108011c04, instArgs{arg_Sd_Dd, arg_Sd_Dd, arg_fbits}}, // VCVT<c>.FX<S,U><16,32>.F<32,64> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|1|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4
+ {0x0fbf0ed0, 0x0eb70ac0, 4, VCVT_EQ_F64_F32, 0x8011c04, instArgs{arg_Dd_Sd, arg_Sm_Dm}}, // VCVT<c>.<F64.F32,F32.F64> <Dd,Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|1|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4
+ {0x0fbe0f50, 0x0eb20a40, 4, VCVTB_EQ_F32_F16, 0x70110011c04, instArgs{arg_Sd, arg_Sm}}, // VCVT<B,T><c>.<F32.F16,F16.F32> <Sd>, <Sm> cond:4|1|1|1|0|1|D|1|1|0|0|1|op|Vd:4|1|0|1|0|T|1|M|0|Vm:4
+ {0x0fbf0e50, 0x0eb80a40, 4, VCVT_EQ_F32_U32, 0x80107011c04, instArgs{arg_Sd_Dd, arg_Sm}}, // VCVT<c>.F<32,64>.<U,S>32 <Sd,Dd>, <Sm> cond:4|1|1|1|0|1|D|1|1|1|0|0|0|Vd:4|1|0|1|sz|op|1|M|0|Vm:4
+ {0x0fbe0e50, 0x0ebc0a40, 4, VCVTR_EQ_U32_F32, 0x701100108011c04, instArgs{arg_Sd, arg_Sm_Dm}}, // VCVT<R,><c>.<U,S>32.F<32,64> <Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|1|1|0|signed|Vd:4|1|0|1|sz|op|1|M|0|Vm:4
+ {0x0fb00e50, 0x0e800a00, 4, VDIV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VDIV<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|1|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4
+ {0x0f300e00, 0x0d100a00, 4, VLDR_EQ, 0x1c04, instArgs{arg_Sd_Dd, arg_mem_R_pm_imm8at0_offset}}, // VLDR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|1|Rn:4|Vd:4|1|0|1|sz|imm8:8
+ {0x0ff00f7f, 0x0e000a10, 4, VMOV_EQ, 0x1c04, instArgs{arg_Sn, arg_R_12}}, // VMOV<c> <Sn>, <Rt> cond:4|1|1|1|0|0|0|0|0|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0
+ {0x0ff00f7f, 0x0e100a10, 4, VMOV_EQ, 0x1c04, instArgs{arg_R_12, arg_Sn}}, // VMOV<c> <Rt>, <Sn> cond:4|1|1|1|0|0|0|0|1|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0
+ {0x0fd00f7f, 0x0e100b10, 4, VMOV_EQ_32, 0x1c04, instArgs{arg_R_12, arg_Dn_half}}, // VMOV<c>.32 <Rt>, <Dn[x]> cond:4|1|1|1|0|0|0|opc1|1|Vn:4|Rt:4|1|0|1|1|N|0|0|1|0|0|0|0
+ {0x0fd00f7f, 0x0e000b10, 4, VMOV_EQ_32, 0x1c04, instArgs{arg_Dn_half, arg_R_12}}, // VMOV<c>.32 <Dd[x]>, <Rt> cond:4|1|1|1|0|0|0|opc1|0|Vd:4|Rt:4|1|0|1|1|D|0|0|1|0|0|0|0
+ {0x0fb00ef0, 0x0eb00a00, 4, VMOV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_imm_vfp}}, // VMOV<c>.F<32,64> <Sd,Dd>, #<imm_vfp> cond:4|1|1|1|0|1|D|1|1|imm4H:4|Vd:4|1|0|1|sz|0|0|0|0|imm4L:4
+ {0x0fbf0ed0, 0x0eb00a40, 4, VMOV_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VMOV<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|0|1|M|0|Vm:4
+ {0x0fff0fff, 0x0ef10a10, 4, VMRS_EQ, 0x1c04, instArgs{arg_R_12_nzcv, arg_FPSCR}}, // VMRS<c> <Rt_nzcv>, FPSCR cond:4|1|1|1|0|1|1|1|1|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0
+ {0x0fff0fff, 0x0ee10a10, 4, VMSR_EQ, 0x1c04, instArgs{arg_FPSCR, arg_R_12}}, // VMSR<c> FPSCR, <Rt> cond:4|1|1|1|0|1|1|1|0|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0
+ {0x0fb00e50, 0x0e200a00, 4, VMUL_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4
+ {0x0fbf0ed0, 0x0eb10a40, 4, VNEG_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VNEG<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|0|1|M|0|Vm:4
+ {0x0fb00e10, 0x0e100a00, 4, VNMLS_EQ_F32, 0x60108011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VN<MLS,MLA><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|1|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4
+ {0x0fb00e50, 0x0e200a40, 4, VNMUL_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VNMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4
+ {0x0fbf0ed0, 0x0eb10ac0, 4, VSQRT_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sm_Dm}}, // VSQRT<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4
+ {0x0f300e00, 0x0d000a00, 4, VSTR_EQ, 0x1c04, instArgs{arg_Sd_Dd, arg_mem_R_pm_imm8at0_offset}}, // VSTR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|0|Rn:4|Vd:4|1|0|1|sz|imm8:8
+ {0x0fb00e50, 0x0e300a40, 4, VSUB_EQ_F32, 0x8011c04, instArgs{arg_Sd_Dd, arg_Sn_Dn, arg_Sm_Dm}}, // VSUB<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4
+ {0x0fffffff, 0x0320f002, 4, WFE_EQ, 0x1c04, instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0
+ {0x0fff00ff, 0x0320f002, 3, WFE_EQ, 0x1c04, instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0
+ {0x0fffffff, 0x0320f003, 4, WFI_EQ, 0x1c04, instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1
+ {0x0fff00ff, 0x0320f003, 3, WFI_EQ, 0x1c04, instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1
+ {0x0fffffff, 0x0320f001, 4, YIELD_EQ, 0x1c04, instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1
+ {0x0fff00ff, 0x0320f001, 3, YIELD_EQ, 0x1c04, instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1
+ {0xffffffff, 0xf7fabcfd, 4, UNDEF, 0x0, instArgs{}}, // UNDEF 1|1|1|1|0|1|1|1|1|1|1|1|1|0|1|0|1|0|1|1|1|1|0|0|1|1|1|1|1|1|0|1
+}
diff --git a/arm/armasm/testdata/Makefile b/arm/armasm/testdata/Makefile
new file mode 100644
index 0000000..1adab68
--- /dev/null
+++ b/arm/armasm/testdata/Makefile
@@ -0,0 +1,5 @@
+newdecode.txt:
+ cd ..; go test -cover -run 'ObjdumpARMCond' -v -timeout 10h -printtests -long 2>&1 | tee log
+ cd ..; go test -cover -run 'ObjdumpARMUncond' -v -timeout 10h -printtests -long 2>&1 | tee -a log
+ egrep ' (gnu|plan9) ' ../log |sort >newdecode.txt
+
diff --git a/arm/armasm/testdata/decode.txt b/arm/armasm/testdata/decode.txt
new file mode 100644
index 0000000..cc1ea0a
--- /dev/null
+++ b/arm/armasm/testdata/decode.txt
@@ -0,0 +1,306 @@
+000001f1| 1 gnu setend le
+00100f61| 1 gnu mrsvs r1, apsr
+00f02053| 1 gnu noppl
+00f0d4f4| 1 gnu pli [r4]
+01f020d3| 1 gnu yieldle
+02002d59| 1 gnu stmdbpl sp!, {r1}
+021da9d8| 1 gnu stmle r9!, {r1, r8, sl, fp, ip}
+02c0b071| 1 gnu movsvc ip, r2
+02f02073| 1 gnu wfevc
+03f02013| 1 gnu wfine
+03f05df7| 1 gnu pld [sp, -r3]
+04009d34| 1 gnu popcc {r0}
+043a52b1| 1 gnu cmplt r2, r4, lsl #20
+04402de5| 1 gnu push {r4}
+045b148d| 1 gnu vldrhi d5, [r4, #-16]
+04f02093| 1 gnu sevls
+0793eab0| 1 gnu rsclt r9, sl, r7, lsl #6
+079bfb9e| 1 gnu vmovls.f64 d25, #183
+0a4fc9d3| 1 gnu bicle r4, r9, #10, 30
+0bac7ab6| 1 gnu ldrbtlt sl, [sl], -fp, lsl #24
+0c2aee44| 1 gnu strbtmi r2, [lr], #2572
+0c4bb000| 1 gnu adcseq r4, r0, ip, lsl #22
+0e26d561| 1 gnu bicsvs r2, r5, lr, lsl #12
+0f0fa011| 1 gnu lslne r0, pc, #30
+0fa448e0| 1 gnu sub sl, r8, pc, lsl #8
+101af1de| 1 gnu vmrsle r1, fpscr
+108a0cee| 1 gnu vmov s24, r8
+108a1dae| 1 gnu vmovge r8, s26
+108ae14e| 1 gnu vmsrmi fpscr, r8
+10faf1ae| 1 gnu vmrsge apsr_nzcv, fpscr
+10fb052e| 1 gnu vmovcs.32 d5[0], pc
+11c902b7| 1 gnu smladlt r2, r1, r9, ip
+11ef5b16| 1 gnu uadd16ne lr, fp, r1
+12fa87a7| 1 gnu usad8ge r7, r2, sl
+135f2956| 1 gnu qadd16pl r5, r9, r3
+13de9aa1| 1 gnu orrsge sp, sl, r3, lsl lr
+145c0e40| 1 gnu andmi r5, lr, r4, lsl ip
+150f7fd6| 1 gnu uhadd16le r0, pc, r5
+15b9bf12| 1 gnu adcsne fp, pc, #344064
+16373391| 1 gnu teqls r3, r6, lsl r7
+19ef1966| 1 gnu sadd16vs lr, r9, r9
+1ab0b091| 1 gnu lslsls fp, sl, r0
+1b9f6fe6| 1 gnu uqadd16 r9, pc, fp
+1bb58557| 1 gnu usada8pl r5, fp, r5, fp
+1beff8e0| 1 gnu rscs lr, r8, fp, lsl pc
+1caff0e6| 1 gnu usat sl, #16, ip, lsl #30
+1d0f3d36| 1 gnu shadd16cc r0, sp, sp
+1dca1d52| 1 gnu andspl ip, sp, #118784
+1e4891d0| 1 gnu addsle r4, r1, lr, lsl r8
+1f0889e6| 1 gnu pkhbt r0, r9, pc, lsl #16
+1f1f6fe1| 1 gnu clz r1, pc
+1f26d157| 1 gnu bfcpl r2, #12, #6
+1ff07ff5| 1 gnu clrex
+1fff2fd1| 1 gnu bxle pc
+20f153f6| 1 gnu pli [r3, -r0, lsr #2]
+21047013| 1 gnu cmnne r0, #553648128
+21c2eb8b| 1 gnu blhi .-0x50f778
+21c2ebfb| 1 gnu blx .-0x50f776
+21fa62ee| 1 gnu vmul.f32 s31, s4, s3
+23005720| 1 gnu subscs r0, r7, r3, lsr #32
+236a303e| 1 gnu vaddcc.f32 s12, s0, s7
+23f055f6| 1 gnu pli [r5, -r3, lsr #32]
+2430a031| 1 gnu lsrcc r3, r4, #32
+245d0803| 1 gnu movweq r5, #36132
+251a86be| 1 gnu vdivlt.f32 s2, s12, s11
+25db7b81| 1 gnu cmnhi fp, r5, lsr #22
+26bc3553| 1 gnu teqpl r5, #9728
+277c2d69| 1 gnu pushvs {r0, r1, r2, r5, sl, fp, ip, sp, lr}
+29fc1cf5| 1 gnu pldw [ip, #-3113]
+29ff2fc1| 1 gnu bxjgt r9
+2decd9c0| 1 gnu sbcsgt lr, r9, sp, lsr #24
+30fa5e47| 1 gnu smmulrmi lr, r0, sl
+316f64d6| 1 gnu uqasxle r6, r4, r1
+323f5da6| 1 gnu uasxge r3, sp, r2
+327fe5e6| 1 gnu usat16 r7, #5, r2
+330151e3| 1 gnu cmp r1, #-1073741812
+34af2ae6| 1 gnu qasx sl, sl, r4
+35fd3710| 1 gnu eorsne pc, r7, r5, lsr sp
+36def1c1| 1 gnu mvnsgt sp, r6, lsr lr
+3801b061| 1 gnu lsrsvs r0, r8, r1
+38985477| 1 gnu smmlarvc r4, r8, r8, r9
+3a2fbfa6| 1 gnu revge r2, sl
+3a3f1b06| 1 gnu sasxeq r3, fp, sl
+3a7fa346| 1 gnu ssat16mi r7, #4, sl
+3a943b94| 1 gnu ldrtls r9, [fp], #-1082
+3bf505e7| 1 gnu smuadx r5, fp, r5
+3cef7086| 1 gnu uhasxhi lr, r0, ip
+3e5f3ec6| 1 gnu shasxgt r5, lr, lr
+3f4fff86| 1 gnu rbithi r4, pc
+3faf4717| 1 gnu smlaldxne sl, r7, pc, pc
+3fff2fc1| 1 gnu blxgt pc
+402bbf7e| 1 gnu vcvtvc.u16.f64 d2, d2, #16
+403ab5de| 1 gnu vcmple.f32 s6, #0
+40eb363e| 1 gnu vsubcc.f64 d14, d6, d0
+420f73d1| 1 gnu cmnle r3, r2, asr #30
+424a648e| 1 gnu vnmulhi.f32 s9, s8, s4
+4284d717| 1 gnu ldrbne r8, [r7, r2, asr #8]
+42a599c3| 1 gnu orrsgt sl, r9, #276824064
+42abf0be| 1 gnu vmovlt.f64 d26, d2
+446ea031| 1 gnu asrcc r6, r4, #28
+4a953557| 1 gnu ldrpl r9, [r5, -sl, asr #10]!
+4ab6f712| 1 gnu rscsne fp, r7, #77594624
+4af07ff5| 1 gnu dsb #10
+4df6def4| 1 gnu pli [lr, #1613]
+4efbf52e| 1 gnu vcmpcs.f64 d31, #0
+50aaac79| 1 gnu stmibvc ip!, {r4, r6, r9, fp, sp, pc}
+50caf011| 1 gnu mvnsne ip, r0, asr sl
+50f04961| 1 gnu qdaddvs pc, r0, r9
+51282008| 1 gnu stmdaeq r0!, {r0, r4, r6, fp, sp}
+52bf6576| 1 gnu uqsaxvc fp, r5, r2
+5345c9d0| 1 gnu sbcle r4, r9, r3, asr r5
+538f5e46| 1 gnu usaxmi r8, lr, r3
+54106d31| 1 gnu qdsubcc r1, r4, sp
+56e0e557| 1 gnu ubfxpl lr, r6, #0, #6
+57073d11| 1 gnu teqne sp, r7, asr r7
+58bb0aa9| 1 gnu stmdbge sl, {r3, r4, r6, r8, r9, fp, ip, sp, pc}
+58f007b1| 1 gnu qaddlt pc, r8, r7
+59fd0e77| 1 gnu smusdvc lr, r9, sp
+5ab7f1c5| 1 gnu ldrbgt fp, [r1, #1882]!
+5abf23c6| 1 gnu qsaxgt fp, r3, sl
+5b8f1c96| 1 gnu ssaxls r8, ip, fp
+5b98ab97| 1 gnu sbfxls r9, fp, #16, #12
+5bc9b041| 1 gnu asrsmi ip, fp, r9
+5bf07ff5| 1 gnu dmb #11
+5c102b81| 1 gnu qsubhi r1, ip, fp
+5caa49e1| 1 gnu qdadd sl, ip, r9
+5d3f7226| 1 gnu uhsaxcs r3, r2, sp
+5db55470| 1 gnu subsvc fp, r4, sp, asr r5
+5ef14387| 1 gnu smlsldhi pc, r3, lr, r1
+5f540a11| 1 gnu qaddne r5, pc, sl
+5f9079d1| 1 gnu cmnle r9, pc, asr r0
+5faf3f66| 1 gnu shsaxvs sl, pc, pc
+605071d7| 1 gnu ldrble r5, [r1, -r0, rrx]!
+614adc76| 1 gnu ldrbvc r4, [ip], r1, ror #20
+616b9e42| 1 gnu addsmi r6, lr, #99328
+62c84f15| 1 gnu strbne ip, [pc, #-2146]
+62f051f7| 1 gnu pld [r1, -r2, rrx]
+6346c393| 1 gnu bicls r4, r3, #103809024
+654abbae| 1 gnu vcvtge.f32.u16 s8, s8, #5
+65a5f0e3| 1 gnu mvns sl, #423624704
+65f796f7| 1 gnu pldw [r6, r5, ror #14]
+670bb12e| 1 gnu vnegcs.f64 d0, d23
+67903731| 1 gnu teqcc r7, r7, rrx
+68ddc637| 1 gnu strbcc sp, [r6, r8, ror #26]
+695b3ab6| 1 gnu ldrtlt r5, [sl], -r9, ror #22
+697cfc71| 1 gnu mvnsvc r7, r9, ror #24
+6a0ab3ee| 1 gnu vcvtb.f16.f32 s0, s21
+6ad9ad54| 1 gnu strtpl sp, [sp], #2410
+6af07ff5| 1 gnu isb #10
+6afa6f10| 1 gnu rsbne pc, pc, sl, ror #20
+6d5b19ee| 1 gnu vnmla.f64 d5, d9, d29
+6d60b071| 1 gnu rrxsvc r6, sp
+6df754f7| 1 gnu pld [r4, -sp, ror #14]
+70065821| 1 gnu cmpcs r8, r0, ror r6
+7050ed86| 1 gnu uxtabhi r5, sp, r0
+715f1186| 1 gnu ssub16hi r5, r1, r1
+716c9805| 1 gnu ldreq r6, [r8, #3185]
+718d5ab1| 1 gnu cmplt sl, r1, ror sp
+71c8cfb6| 1 gnu uxtb16lt ip, r1, ror #16
+7294af06| 1 gnu sxtbeq r9, r2, ror #8
+72c0bac6| 1 gnu sxtahgt ip, sl, r2
+730f6716| 1 gnu uqsub16ne r0, r7, r3
+73608f46| 1 gnu sxtb16mi r6, r3
+73687f22| 1 gnu rsbscs r6, pc, #7536640
+74308816| 1 gnu sxtab16ne r3, r8, r4
+757f3456| 1 gnu shsub16pl r7, r4, r5
+77788016| 1 gnu sxtab16ne r7, r0, r7, ror #16
+78061671| 1 gnu tstvc r6, r8, ror r6
+780a2fe1| 1 gnu bkpt 0xf0a8
+7850abd6| 1 gnu sxtable r5, fp, r8
+792cef26| 1 gnu uxtbcs r2, r9, ror #24
+799eb8e0| 1 gnu adcs r9, r8, r9, ror lr
+799f5726| 1 gnu usub16cs r9, r7, r9
+79d0bf16| 1 gnu sxthne sp, r9
+7a037ba1| 1 gnu cmnge fp, sl, ror r3
+7b0f2566| 1 gnu qsub16vs r0, r5, fp
+7b79dd51| 1 gnu bicspl r7, sp, fp, ror r9
+7b9a9f1d| 1 gnu vldrne s18, [pc, #492]
+7c70cea6| 1 gnu uxtab16ge r7, lr, ip
+7d48f966| 1 gnu uxtahvs r4, r9, sp, ror #16
+7d5c13a1| 1 gnu tstge r3, sp, ror ip
+7e0001f1| 1 gnu setend le
+7e1c0ba7| 1 gnu smlsdxge fp, lr, ip, r1
+7e567e40| 1 gnu rsbsmi r5, lr, lr, ror r6
+7e8f73b6| 1 gnu uhsub16lt r8, r3, lr
+7ef0ffd6| 1 gnu uxthle pc, lr
+7faaa011| 1 gnu rorne sl, pc, sl
+81f19af7| 1 gnu pldw [sl, r1, lsl #3]
+82033901| 1 gnu teqeq r9, r2, lsl #7
+82f316f5| 1 gnu pldw [r6, #-898]
+830201f1| 1 gnu setend be
+838a3b91| 1 gnu teqls fp, r3, lsl #21
+8408af2f| 1 gnu svccs 0x00af0884
+884201d1| 1 gnu smlabble r1, r8, r2, r4
+8aa12e31| 1 gnu smlawbcc lr, sl, r1, sl
+8b9b99c0| 1 gnu addsgt r9, r9, fp, lsl #23
+8c005c81| 1 gnu cmphi ip, ip, lsl #1
+8fb429c6| 1 gnu strtgt fp, [r9], -pc, lsl #9
+907b1f9e| 1 gnu vmovls.32 r7, d31[0]
+91975f25| 1 gnu ldrbcs r9, [pc, #-1937]
+91b010e3| 1 gnu tst r0, #145
+927facb1| 1 gnu strexdlt r7, r2, [ip]
+92904c91| 1 gnu swpbls r9, r2, [ip]
+92af1226| 1 gnu sadd8cs sl, r2, r2
+92b28c70| 1 gnu umullvc fp, ip, r2, r2
+945f68a6| 1 gnu uqadd8ge r5, r8, r4
+950b2560| 1 gnu mlavs r5, r5, fp, r0
+969fcf71| 1 gnu strexbvc r9, r6, [pc]
+96cf35e6| 1 gnu shadd8 ip, r5, r6
+98060eb0| 1 gnu mullt lr, r8, r6
+9843fb93| 1 gnu mvnsls r4, #152, 6
+9a3fe2b0| 1 gnu smlallt r3, r2, sl, pc
+9aef58b6| 1 gnu uadd8lt lr, r8, sl
+9afcdff5| 1 gnu pld [pc, #3226]
+9c221810| 1 gnu mulsne r8, ip, r2
+9c3bc9dd| 1 gnu vstrle d19, [r9, #624]
+9c5f2606| 1 gnu qadd8eq r5, r6, ip
+9d87dac0| 1 gnu smullsgt r8, sl, sp, r7
+9e0f7c86| 1 gnu uhadd8hi r0, ip, lr
+9e814560| 1 gnu umaalvs r8, r5, lr, r1
+9e9f8dc1| 1 gnu strexgt r9, lr, [sp]
+9ec3c9d7| 1 gnu bfile ip, lr, #7, #3
+9ed26d90| 1 gnu mlsls sp, lr, r2, sp
+9f7fd9c1| 1 gnu ldrexbgt r7, [r9]
+9f7fea91| 1 gnu strexhls r7, pc, [sl]
+9f9f9921| 1 gnu ldrexcs r9, [r9]
+9faffd21| 1 gnu ldrexhcs sl, [sp]
+9fcfbd61| 1 gnu ldrexdvs ip, [sp]
+9ff7a710| 1 gnu umlalne pc, r7, pc, r7
+a05459d3| 1 gnu cmple r9, #160, 8
+a3062be1| 1 gnu smulwb fp, r3, r6
+a68a92b1| 1 gnu orrslt r8, r2, r6, lsr #21
+abff55f6| 1 gnu pli [r5, -fp, lsr #31]
+addbf8ea| 1 gnu b .-0x1c9148
+ae79b021| 1 gnu lsrscs r7, lr, #19
+b590a3b1| 1 gnu strhlt r9, [r3, r5]!
+b5b2e390| 1 gnu strhtls fp, [r3], #37
+b6ac4e30| 1 gnu strhcc sl, [lr], #-198
+b73fff86| 1 gnu revshhi r3, r7
+b75fbfc6| 1 gnu rev16gt r5, r7
+b80b7c80| 1 gnu ldrhthi r0, [ip], #-184
+b82035e0| 1 gnu ldrht r2, [r5], -r8
+b8877391| 1 gnu ldrhls r8, [r3, #-120]!
+b9703e41| 1 gnu ldrhmi r7, [lr, -r9]!
+b9cf8c16| 1 gnu selne ip, ip, r9
+bd81bd58| 1 gnu poppl {r0, r2, r3, r4, r5, r7, r8, pc}
+bdfdb469| 1 gnu ldmibvs r4!, {r0, r2, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc}
+beb02500| 1 gnu strhteq fp, [r5], -lr
+bf1a5e42| 1 gnu subsmi r1, lr, #782336
+c19a4d5e| 1 gnu vmlspl.f32 s19, s27, s2
+c1aab15e| 1 gnu vsqrtpl.f32 s20, s2
+c354b003| 1 gnu movseq r5, #-1023410176
+c4091dc1| 1 gnu tstgt sp, r4, asr #19
+c50e13a9| 1 gnu ldmdbge r3, {r0, r2, r6, r7, r9, sl, fp}
+c68c8637| 1 gnu strcc r8, [r6, r6, asr #25]
+c6ad48e3| 1 gnu movt sl, #36294
+c6f65ff5| 1 gnu pld [pc, #-1734]
+c8a92f10| 1 gnu eorne sl, pc, r8, asr #19
+c9016b61| 1 gnu smulbtvs fp, r9, r1
+cadbf49e| 1 gnu vcmpels.f64 d29, d10
+ce9de476| 1 gnu strbtvc r9, [r4], lr, asr #27
+cf3c1ab1| 1 gnu tstlt sl, pc, asr #25
+d355aab6| 1 gnu ssatlt r5, #11, r3, asr #11
+d4f4df10| 1 gnu ldrsbne pc, [pc], #68
+d6530d61| 1 gnu ldrdvs r5, [sp, -r6]
+d74d7800| 1 gnu ldrsbteq r4, [r8], #-215
+d9703680| 1 gnu ldrsbthi r7, [r6], -r9
+dbe003c0| 1 gnu ldrdgt lr, [r3], -fp
+dc709561| 1 gnu ldrsbvs r7, [r5, ip]
+dcc3b9c8| 1 gnu ldmgt r9!, {r2, r3, r4, r6, r7, r8, r9, lr, pc}
+debfa0e5| 1 gnu str fp, [r0, #4062]!
+dee062a1| 1 gnu ldrdge lr, [r2, #-14]!
+dfa05ab7| 1 gnu smmlslt sl, pc, r0, sl
+e02ef011| 1 gnu mvnsne r2, r0, ror #29
+e4d41718| 1 gnu ldmdane r7, {r2, r5, r6, r7, sl, ip, lr, pc}
+e6d0fe34| 1 gnu ldrbtcc sp, [lr], #230
+e73bf7be| 1 gnu vcvtlt.f32.f64 s7, d23
+e74e72b3| 1 gnu cmnlt r2, #3696
+e80bf07e| 1 gnu vabsvc.f64 d16, d24
+e9b5b001| 1 gnu rorseq fp, r9, #11
+ea7bbdbe| 1 gnu vcvtlt.s32.f64 s14, d26
+ec063813| 1 gnu teqne r8, #236, 12
+ec0e49e1| 1 gnu smlaltt r0, r9, ip, lr
+ee4ab85e| 1 gnu vcvtpl.f32.s32 s8, s29
+ef461f25| 1 gnu ldrcs r4, [pc, #-1775]
+ef5fd002| 1 gnu sbcseq r5, r0, #956
+f4cf1d36| 1 gnu ssub8cc ip, sp, r4
+f67f73b6| 1 gnu uhsub8lt r7, r3, r6
+f6e09ca0| 1 gnu ldrshge lr, [ip], r6
+f7702e32| 1 gnu eorcc r7, lr, #247
+fa4dcf20| 1 gnu strdcs r4, [pc], #218
+fac03720| 1 gnu ldrshtcs ip, [r7], -sl
+fc0f64c6| 1 gnu uqsub8gt r0, r4, ip
+fc28f481| 1 gnu ldrshhi r2, [r4, #140]!
+fc300560| 1 gnu strdvs r3, [r5], -ip
+fcacfc70| 1 gnu ldrshtvc sl, [ip], #204
+fdbcfaf7| 1 gnu undef
+fddf5c86| 1 gnu usub8hi sp, ip, sp
+fdf02013| 1 gnu dbgne #13
+fe0319e3| 1 gnu tst r9, #-134217725
+fe7f3116| 1 gnu shsub8ne r7, r1, lr
+ff4f2ac6| 1 gnu qsub8gt r4, sl, pc
+ff818c71| 1 gnu strdvc r8, [ip, pc]
+|6b5721d3 1 gnu error: unknown instruction
+|76452001 1 gnu error: unknown instruction
+|97acd647 1 gnu error: unknown instruction
diff --git a/arm/armmap/map.go b/arm/armmap/map.go
new file mode 100644
index 0000000..9b4c85a
--- /dev/null
+++ b/arm/armmap/map.go
@@ -0,0 +1,756 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Armmap constructs the ARM opcode map from the instruction set CSV file.
+//
+// Usage:
+// armmap [-fmt=format] arm.csv
+//
+// The known output formats are:
+//
+// text (default) - print decoding tree in text form
+// decoder - print decoding tables for the armasm package
+package main
+
+import (
+ "bufio"
+ "encoding/csv"
+ "flag"
+ "fmt"
+ "log"
+ "os"
+ "sort"
+ "strconv"
+ "strings"
+)
+
+var format = flag.String("fmt", "text", "output format: text, decoder")
+
+var inputFile string
+
+func usage() {
+ fmt.Fprintf(os.Stderr, "usage: armmap [-fmt=format] x86.csv\n")
+ os.Exit(2)
+}
+
+func main() {
+ log.SetFlags(0)
+ log.SetPrefix("armmap: ")
+
+ flag.Usage = usage
+ flag.Parse()
+ if flag.NArg() != 1 {
+ usage()
+ }
+
+ inputFile = flag.Arg(0)
+
+ var print func(*Prog)
+ switch *format {
+ default:
+ log.Fatalf("unknown output format %q", *format)
+ case "text":
+ print = printText
+ case "decoder":
+ print = printDecoder
+ }
+
+ p, err := readCSV(flag.Arg(0))
+ if err != nil {
+ log.Fatal(err)
+ }
+
+ print(p)
+}
+
+// readCSV reads the CSV file and returns the corresponding Prog.
+// It may print details about problems to standard error using the log package.
+func readCSV(file string) (*Prog, error) {
+ // Read input.
+ // Skip leading blank and # comment lines.
+ f, err := os.Open(file)
+ if err != nil {
+ return nil, err
+ }
+ b := bufio.NewReader(f)
+ for {
+ c, err := b.ReadByte()
+ if err != nil {
+ break
+ }
+ if c == '\n' {
+ continue
+ }
+ if c == '#' {
+ b.ReadBytes('\n')
+ continue
+ }
+ b.UnreadByte()
+ break
+ }
+ table, err := csv.NewReader(b).ReadAll()
+ if err != nil {
+ return nil, fmt.Errorf("parsing %s: %v", file, err)
+ }
+ if len(table) == 0 {
+ return nil, fmt.Errorf("empty csv input")
+ }
+ if len(table[0]) < 5 {
+ return nil, fmt.Errorf("csv too narrow: need at least five columns")
+ }
+
+ p := &Prog{}
+ for _, row := range table {
+ add(p, row[0], row[1], row[2], row[3], row[4])
+ }
+ return p, nil
+}
+
+type Prog struct {
+ Inst []Inst
+ OpRanges map[string]string
+}
+
+type Inst struct {
+ Text string
+ Encoding string
+ Mask uint32
+ Value uint32
+ Priority int
+ OpBase string
+ OpBits uint64
+ Args []string
+}
+
+type Arg struct {
+ Name string
+ Bits uint64
+}
+
+// add adds the entry from the CSV described by maskstr, valuestr, text, encoding, tags
+// to the program p.
+func add(p *Prog, maskstr, valuestr, text, encoding, tags string) {
+ if strings.Contains(tags, "pseudo") {
+ return
+ }
+
+ // For now, ignore the VFP floating point instructions.
+ if strings.HasPrefix(text, "V") && !strings.Contains(tags, "vfp") {
+ // TODO
+ return
+ }
+
+ mask, err := strconv.ParseUint(maskstr, 0, 32)
+ if err != nil {
+ log.Printf("invalid mask %q", maskstr)
+ return
+ }
+ value, err := strconv.ParseUint(valuestr, 0, 32)
+ if err != nil {
+ log.Printf("invalid value %q", valuestr)
+ return
+ }
+
+ // Parse encoding, building size and offset of each field.
+ // The first field in the encoding is the largest offset.
+ fuzzy := uint32(0) // mask of 'should be' bits
+ fieldOffset := map[string]int{}
+ fieldWidth := map[string]int{}
+ off := 32
+ for _, f := range strings.Split(encoding, "|") {
+ n := 1
+ if i := strings.Index(f, ":"); i >= 0 {
+ n, _ = strconv.Atoi(f[i+1:])
+ }
+ off -= n
+ fieldOffset[f] = off
+ fieldWidth[f] = n
+ if f == "(0)" || f == "(1)" {
+ fuzzy |= 1 << uint(off)
+ }
+ }
+ if off != 0 {
+ fmt.Fprintf(os.Stderr, "%s: counted %d bits in %s\n", text, 32-off, encoding)
+ }
+
+ // Track which encoding fields we found uses for.
+ // If we do not find a use for a field, that's an error in the input tables.
+ fieldUsed := map[string]bool{}
+
+ // Split text into opcode and arguments.
+ var op, argstr string
+ if i := strings.Index(text, " "); i >= 0 {
+ op = text[:i]
+ argstr = text[i:]
+ } else {
+ op = text
+ }
+ op = strings.TrimSpace(op)
+ argstr = strings.TrimSpace(argstr)
+
+ // Parse opcode suffixes.
+ i := strings.Index(op, "<")
+ if i < 0 {
+ i = len(op)
+ }
+ if j := strings.Index(op, "{"); j >= 0 && j < i {
+ i = j
+ }
+ op, suffix := op[:i], op[i:]
+ if suffix != "" && opSuffix[suffix] == "" {
+ fmt.Fprintf(os.Stderr, "%s: invalid op suffix %q in %s\n", text, suffix, op+suffix)
+ }
+
+ // Make sure fields needed by opcode suffix are available.
+ for _, f := range strings.Split(opSuffix[suffix], ",") {
+ if f != "" && fieldWidth[f] == 0 {
+ fmt.Fprintf(os.Stderr, "%s: opsuffix %s missing %s in encoding %s\n", text, suffix, f, encoding)
+ }
+ fieldUsed[f] = true
+ }
+
+ // Build list of opcodes that can be generated by this suffix.
+ // For example, the opcodes generated by ADD<c> are ADD.EQ, ADD.NE, etc.
+ // To simplify the decoding of instruction opcodes, we arrange that this
+ // sequence aligns with the encoding, so that decoding amounts to extracting
+ // the right bits, concatenating them, and adding them to the first opcode in
+ // the sequence. If the condition code is present, we always place it in the
+ // low order bits, so that x&^15 == FOO_EQ tests whether x is any of the
+ // conditional FOO instructions.
+ ops := []string{op}
+ opBits := uint64(0) // record of bits to extract and add to opcode base
+ opFields := strings.Split(opSuffix[suffix], ",")
+ // First the optional elements, like {S} meaning "" or ".S".
+ for strings.HasPrefix(suffix, "{") {
+ i := strings.Index(suffix, "}")
+ var f, option string
+ option, suffix = suffix[1:i], suffix[i+1:]
+ f, opFields = opFields[0], opFields[1:]
+ if option == "W" {
+ // The {W} option on PLD{W} uses the R bit which is !W.
+ ops = cross(ops, "."+option, "")
+ } else {
+ ops = cross(ops, "", "."+option)
+ }
+ if fieldWidth[f] != 1 {
+ fmt.Fprintf(os.Stderr, "%s: have %d bits for {%s}\n", text, fieldWidth[f], option)
+ }
+ // opBits is a sequence of 16-bit chunks describing contiguous bit sections.
+ // Each chunk is 8-bit offset followed by 8-bit size.
+ opBits = opBits<<16 | uint64(fieldOffset[f])<<8 | 1
+ }
+ // Then the true field substitutions.
+ haveCond := false
+ for strings.Contains(suffix, "<") {
+ var f, literal, x string
+ if len(opFields) == 0 {
+ fmt.Fprintf(os.Stderr, "%s: ran out of suffix fields for <%s>\n", text, x)
+ break
+ }
+ f, opFields = opFields[0], opFields[1:]
+ i := strings.Index(suffix, "<")
+ j := strings.Index(suffix, ">")
+ literal, x, suffix = suffix[:i], suffix[i+1:j], suffix[j+1:]
+
+ // Add leading literal text to all opcodes.
+ ops = cross(ops, literal)
+
+ // The <c> condition can happen anywhere in the opcode text
+ // but we want to generate the actual variation in the low bits
+ // of the list index. Remember when and where we've seen <c> and apply
+ // it after the loop has finished.
+ if x == "c" && f == "cond:4" {
+ haveCond = true
+ ops = cross(ops, "_COND_")
+ continue
+ }
+
+ // Otherwise, choices[x] lists the possible expansions of <x>.
+ // If <x> is of the form <A,B,C> the choices are A, B, and C.
+ expand := choices[x]
+ if expand == nil && strings.Contains(x, ",") {
+ expand = strings.Split(x, ",")
+ }
+ if expand == nil {
+ fmt.Fprintf(os.Stderr, "%s: unknown choices for <%s>\n", text, x)
+ expand = []string{x}
+ } else if len(expand) != 1<<uint(fieldWidth[f]) {
+ fmt.Fprintf(os.Stderr, "%s: have %d choices for <%s> but %d bits\n", text, len(expand), x, fieldWidth[f])
+ }
+ opBits = opBits<<16 | uint64(fieldOffset[f])<<8 | uint64(fieldWidth[f])
+ ops = cross(ops, expand...)
+ }
+ if haveCond {
+ // Apply condtional suffix last.
+ opBits = opBits<<16 | 28<<8 | 4
+ ops = crossCond(ops)
+ }
+ ops = cross(ops, suffix)
+
+ // Now ops is a list of opcodes generated by this opcode pattern.
+ // We want to make sure that we can arrange for those opcodes to
+ // happen consecutively in the final opcode numbering.
+ // Record in p.OpRanges[op] the required consecutive sequence of
+ // opcode that includes op. To make searches easier, we record
+ // the sequence as a comma-separated list of strings with commas
+ // on both ends: [A, B] encodes as ",A,B,".
+ if p.OpRanges == nil {
+ p.OpRanges = make(map[string]string)
+ }
+ opstr := "," + strings.Join(ops, ",") + ","
+ for _, op := range ops {
+ if old := p.OpRanges[op]; old != "" && old != opstr {
+ if strings.Contains(old, opstr) {
+ opstr = old
+ } else if strings.Contains(opstr, old) {
+ // great, do nothing
+ } else {
+ // It would also be okay if there is some subsequence s such that
+ // old = x+s and opstr = s+y (or vice versa), in which case we should
+ // record opstr = x+s+y. However, this has not come up in practice.
+ // Failing that, we can't satisfy the sequencing requirements.
+ fmt.Fprintf(os.Stderr, "%s: %s appears in both %s and %s\n", text, op, old, opstr)
+ }
+ }
+ }
+ for _, op := range strings.Split(opstr, ",") {
+ if op != "" {
+ p.OpRanges[op] = opstr
+ }
+ }
+
+ // Process the arguments, building a list of argument descriptions.
+ // Each argument description has the form <argument>|field@off|field@off...
+ // where the |field@off suffixes give the name and location of the fields
+ // needed by the argument. Each such string maps to a different decoding
+ // type in the generated table, according to the argOps map.
+ var args []string
+ for argstr != "" {
+ // Find longest match among argSuffixes pieces.
+ best := 0
+ for a := range argSuffixes {
+ if argstr == a || strings.HasPrefix(argstr, a+",") {
+ if best < len(a) {
+ best = len(a)
+ }
+ }
+ }
+ if best == 0 {
+ fmt.Fprintf(os.Stderr, "%s: unknown arg %s\n", text, argstr)
+ break
+ }
+
+ var arg, desc string
+ arg, argstr = argstr[:best], strings.TrimSpace(strings.TrimLeft(argstr[best:], ","))
+ desc = arg
+ for _, f := range strings.Split(argSuffixes[desc], ",") {
+ if f == "" {
+ continue
+ }
+ if fieldWidth[f] == 0 {
+ fmt.Fprintf(os.Stderr, "%s: arg %s missing %s in encoding %s\n", text, arg, f, encoding)
+ }
+ fieldUsed[f] = true
+ desc += fmt.Sprintf("|%s@%d", f, fieldOffset[f])
+ }
+ args = append(args, desc)
+ }
+
+ // Check that all encoding fields were used by suffix or argument decoding.
+ for f := range fieldWidth {
+ switch f {
+ case "0", "1", "(0)", "(1)":
+ // ok
+ default:
+ if !fieldUsed[f] {
+ fmt.Fprintf(os.Stderr, "%s: encoding field %s not used in %s\n", text, f, encoding)
+ }
+ }
+ }
+
+ // Determine decoding priority. Instructions that say 'SEE X' in the tag
+ // are considered lower priority than ones that don't. In theory the
+ // structure described by the SEE tags might be richer than that, but
+ // in practice it only has those two levels.
+ // We leave space for two more priorities according to whether the
+ // fuzzy bits are set correctly. The full set of priorities then is:
+ //
+ // 4 - no SEE tag, fuzzy bits all match
+ // 3 - no SEE tag, some fuzzy bits don't match
+ // 2 - SEE tag, fuzzy bits all match
+ // 1 - SEE tag, some fuzzy bits don't match
+ //
+ // You could argue for swapping the middle two levels but so far
+ // it has not been an issue.
+ pri := 4
+ if strings.Contains(tags, "SEE") {
+ pri = 2
+ }
+
+ inst := Inst{
+ Text: text,
+ Encoding: encoding,
+ Mask: uint32(mask),
+ Value: uint32(value),
+ Priority: pri,
+ OpBase: ops[0],
+ OpBits: opBits,
+ Args: args,
+ }
+ p.Inst = append(p.Inst, inst)
+
+ if fuzzy != 0 {
+ inst.Mask &^= fuzzy
+ inst.Priority--
+ p.Inst = append(p.Inst, inst)
+ }
+}
+
+// opSuffix describes the encoding fields used to resolve a given opcode suffix.
+var opSuffix = map[string]string{
+ "<ADD,SUB>": "op",
+ "<BIF,BIT,BSL>": "op:2",
+ "<MLA,MLS><c>.F<32,64>": "op,cond:4,sz",
+ "<MLS,MLA><c>.F<32,64>": "op,cond:4,sz",
+ "<BT,TB><c>": "tb,cond:4",
+ "<TBL,TBX>.8": "op",
+ "<c>": "cond:4",
+ "<c>.32": "cond:4",
+ "<c>.F<32,64>": "cond:4,sz",
+ "<x><y><c>": "N,M,cond:4",
+ "<y><c>": "M,cond:4",
+ "{B}<c>": "B,cond:4",
+ "{E}<c>.F<32,64>": "E,cond:4,sz",
+ "{R}<c>": "R,cond:4",
+ "<c>.F<32,64>.<U,S>32": "cond:4,sz,op",
+ "<R,><c>.<U,S>32.F<32,64>": "op,cond:4,signed,sz",
+ "{S}<c>": "S,cond:4",
+ "{W}": "R",
+ "{X}<c>": "M,cond:4",
+ "<B,T><c>.<F32.F16,F16.F32>": "T,cond:4,op",
+ "<c>.<F64.F32,F32.F64>": "cond:4,sz",
+ "<c>.FX<S,U><16,32>.F<32,64>": "cond:4,U,sx,sz",
+ "<c>.F<32,64>.FX<S,U><16,32>": "cond:4,sz,U,sx",
+}
+
+// choices[x] describes the choices for filling in "<"+x+">" in an opcode suffix.
+// Opcodes that end up containing ZZ take up a numeric sequence value but are
+// not exported in the package API.
+var choices = map[string][]string{
+ "c": {".EQ", ".NE", ".CS", ".CC", ".MI", ".PL", ".VS", ".VC", ".HI", ".LS", ".GE", ".LT", ".GT", ".LE", "", ".ZZ"},
+ "x": {"B", "T"},
+ "y": {"B", "T"},
+}
+
+// argOps maps from argument descriptions to internal decoder name.
+var argOps = map[string]string{
+ // 4-bit register encodings
+ "<Rm>|Rm:4@0": "arg_R_0",
+ "<Rn>|Rn:4@0": "arg_R_0",
+ "<Rt>|Rt:4@0": "arg_R_0",
+ "<Rm>|Rm:4@8": "arg_R_8",
+ "<Ra>|Ra:4@12": "arg_R_12",
+ "<Rd>|Rd:4@12": "arg_R_12",
+ "<RdLo>|RdLo:4@12": "arg_R_12",
+ "<Rt>|Rt:4@12": "arg_R_12",
+ "<Rt_nzcv>|Rt:4@12": "arg_R_12_nzcv",
+ "<Rd>|Rd:4@16": "arg_R_16",
+ "<RdHi>|RdHi:4@16": "arg_R_16",
+ "<Rn>|Rn:4@16": "arg_R_16",
+
+ // first and second of consecutive register pair
+ "<Rt1>|Rt:4@0": "arg_R1_0",
+ "<Rt1>|Rt:4@12": "arg_R1_12",
+ "<Rt2>|Rt:4@0": "arg_R2_0",
+ "<Rt2>|Rt:4@12": "arg_R2_12",
+
+ // register arithmetic
+ "<Rm>,<type> <Rs>|Rm:4@0|Rs:4@8|type:2@5": "arg_R_shift_R",
+ "<Rm>{,<shift>}|Rm:4@0|imm5:5@7|type:2@5": "arg_R_shift_imm",
+ "<Rn>{,<shift>}|Rn:4@0|imm5:5@7|sh@6": "arg_R_shift_imm",
+ "<Rm>{,LSL #<imm5>}|Rm:4@0|imm5:5@7": "arg_R_shift_imm",
+ "<Rm>{,<rotation>}|Rm:4@0|rotate:2@10": "arg_R_rotate",
+
+ // memory references
+ "<Rn>{!}|Rn:4@16|W@21": "arg_R_16_WB",
+ "[<Rn>]|Rn:4@16": "arg_mem_R",
+ "[<Rn>,+/-<Rm>{, <shift>}]{!}|Rn:4@16|U@23|Rm:4@0|type:2@5|imm5:5@7|P@24|W@21": "arg_mem_R_pm_R_shift_imm_W",
+ "[<Rn>{,#+/-<imm8>}]{!}|Rn:4@16|P@24|U@23|W@21|imm4H:4@8|imm4L:4@0": "arg_mem_R_pm_imm8_W",
+ "[<Rn>] {,#+/-<imm8>}|Rn:4@16|U@23|imm4H:4@8|imm4L:4@0": "arg_mem_R_pm_imm8_postindex",
+ "[<Rn>{,#+/-<imm12>}]{!}|Rn:4@16|P@24|U@23|W@21|imm12:12@0": "arg_mem_R_pm_imm12_W",
+ "[<Rn>],#+/-<imm12>|Rn:4@16|imm12:12@0|U@23": "arg_mem_R_pm_imm12_postindex",
+ "[<Rn>,#+/-<imm12>]|Rn:4@16|U@23|imm12:12@0": "arg_mem_R_pm_imm12_offset",
+ "[<Rn>] {,#+/-<imm12>}|Rn:4@16|U@23|imm12:12@0": "arg_mem_R_pm_imm12_postindex",
+ "[<Rn>], +/-<Rm>|Rn:4@16|U@23|Rm:4@0": "arg_mem_R_pm_R_postindex",
+ "[<Rn>,+/-<Rm>]{!}|Rn:4@16|U@23|Rm:4@0|P@24|W@21": "arg_mem_R_pm_R_W",
+ "[<Rn>],+/-<Rm>{, <shift>}|Rn:4@16|Rm:4@0|imm5:5@7|type:2@5|U@23": "arg_mem_R_pm_R_shift_imm_postindex",
+ "[<Rn>,+/-<Rm>{, <shift>}]|Rn:4@16|U@23|Rm:4@0|type:2@5|imm5:5@7": "arg_mem_R_pm_R_shift_imm_offset",
+ "[<Rn>{,#+/-<imm8>}]|Rn:4@16|U@23|imm8:8@0": "arg_mem_R_pm_imm8at0_offset",
+
+ // pc-relative constants
+ "<label+12>|imm12:12@0": "arg_label_p_12",
+ "<label-12>|imm12:12@0": "arg_label_m_12",
+ "<label+/-12>|imm12:12@0|U@23": "arg_label_pm_12",
+ "<label+/-4+4>|imm4H:4@8|imm4L:4@0|U@23": "arg_label_pm_4_4",
+
+ // constants
+ "#<const>|imm12:12@0": "arg_const",
+ "#<imm5>|imm5:5@7": "arg_imm5",
+ "#<imm5_nz>|imm5:5@7": "arg_imm5_nz",
+ "#<imm5_32>|imm5:5@7": "arg_imm5_32",
+ "<label24>|imm24:24@0": "arg_label24",
+ "#<lsb>|lsb:5@7": "arg_imm5",
+ "#<width>|lsb:5@7|msb:5@16": "arg_lsb_width",
+ "#<imm12+4>|imm12:12@8|imm4:4@0": "arg_imm_12at8_4at0",
+ "#<imm12+4>|imm12:12@0|imm4:4@16": "arg_imm_4at16_12at0",
+ "<label24H>|imm24:24@0|H@24": "arg_label24H",
+ "#<option>|option:4@0": "arg_option",
+ "#<widthm1>|widthm1:5@16": "arg_widthm1",
+ "#<sat_imm4>|sat_imm:4@16": "arg_satimm4",
+ "#<sat_imm5>|sat_imm:5@16": "arg_satimm5",
+ "#<sat_imm4m1>|sat_imm:4@16": "arg_satimm4m1",
+ "#<sat_imm5m1>|sat_imm:5@16": "arg_satimm5m1",
+ "#<imm24>|imm24:24@0": "arg_imm24",
+
+ // special
+ "<registers>|register_list:16@0": "arg_registers",
+ "<registers2>|register_list:16@0": "arg_registers2",
+ "<registers1>|Rt:4@12": "arg_registers1",
+ "<endian_specifier>|E@9": "arg_endian",
+
+ "SP": "arg_SP",
+ "APSR": "arg_APSR",
+ "FPSCR": "arg_FPSCR",
+
+ // VFP floating point registers
+ "<Sd>|Vd:4@12|D@22": "arg_Sd",
+ "<Sd,Dd>|Vd:4@12|D@22|sz@8": "arg_Sd_Dd",
+ "<Dd,Sd>|Vd:4@12|D@22|sz@8": "arg_Dd_Sd",
+ "<Sn>|Vn:4@16|N@7": "arg_Sn",
+ "<Sn,Dn>|Vn:4@16|N@7|sz@8": "arg_Sn_Dn",
+ "<Sm>|Vm:4@0|M@5": "arg_Sm",
+ "<Sm,Dm>|Vm:4@0|M@5|sz@8": "arg_Sm_Dm",
+ "#0.0": "arg_fp_0",
+ "#<imm_vfp>|imm4H:4@16|imm4L:4@0|sz@8": "arg_imm_vfp",
+ "#<fbits>|sx@7|imm4:4@0|i@5": "arg_fbits",
+ "<Dn[x]>|N@7|Vn:4@16|opc1@21": "arg_Dn_half",
+ "<Dd[x]>|D@7|Vd:4@16|opc1@21": "arg_Dn_half",
+}
+
+// argSuffixes describes the encoding fields needed for a particular suffix.
+// The set of keys in argSuffixes also drives the identification of suffix pieces.
+// For example, <Rm> and <Rm>{, <type> <Rs>} are both keys in the map
+// and matching is done 'longest first', so "<Rm>, <Rm>{, <type> <Rs>}" is
+// parsed as just two arguments despite the extra ", ".
+// The field order in the map values must match the order expected in
+// the argument descriptions in argOps.
+var argSuffixes = map[string]string{
+ "#0": "",
+ "#0.0": "",
+ "#<const>": "imm12:12",
+ "#<fbits>": "sx,imm4:4,i",
+ "#<imm12+4>": "imm12:12,imm4:4",
+ "#<imm24>": "imm24:24",
+ "#<imm3>": "imm3:3",
+ "#<imm4>": "imm4:4",
+ "#<imm5>": "imm5:5",
+ "#<imm5_nz>": "imm5:5",
+ "#<imm5_32>": "imm5:5",
+ "#<imm6>": "imm6:6",
+ "#<immsize>": "size:2",
+ "#<imm_vfp>": "imm4H:4,imm4L:4,sz",
+ "#<sat_imm4>": "sat_imm:4",
+ "#<sat_imm5>": "sat_imm:5",
+ "#<sat_imm4m1>": "sat_imm:4",
+ "#<sat_imm5m1>": "sat_imm:5",
+ "#<lsb>": "lsb:5",
+ "#<option>": "option:4",
+ "#<width>": "lsb:5,msb:5",
+ "#<widthm1>": "widthm1:5",
+ "+/-<Rm>": "Rm:4,U",
+ "<Dd>": "D,Vd:4",
+ "<Dd[x]>": "D,Vd:4,opc1",
+ "<Dm>": "M,Vm:4",
+ "<Dm[x]>": "M,Vm:4,size:2",
+ "<Dn>": "N,Vn:4",
+ "<Dn[x]>": "N,Vn:4,opc1",
+ "<Dm[size_x]>": "imm4:4",
+ "<Qd>": "D,Vd:4",
+ "<Qm>": "M,Vm:4",
+ "<Qn>": "N,Vn:4",
+ "<Ra>": "Ra:4",
+ "<Rd>": "Rd:4",
+ "<RdHi>": "RdHi:4",
+ "<RdLo>": "RdLo:4",
+ "<Rm>": "Rm:4",
+ "<Rm>{,<rotation>}": "Rm:4,rotate:2",
+ "<Rm>{,<shift>}": "Rm:4,imm5:5,type:2",
+ "<Rm>{,LSL #<imm5>}": "Rm:4,imm5:5",
+ "<Rn>": "Rn:4",
+ "<Rn>{!}": "Rn:4,W",
+ "<Rn>{,<shift>}": "Rn:4,imm5:5,sh",
+ "<Rs>": "Rs:4",
+ "<Rt1>": "Rt:4",
+ "<Rt2>": "Rt:4",
+ "<Rt>": "Rt:4",
+ "<Rt_nzcv>": "Rt:4",
+ "<Sd>": "Vd:4,D",
+ "<Sm1>": "Vm:4,M",
+ "<Sm>": "Vm:4,M",
+ "<Sn>": "Vn:4,N",
+ "<Sd,Dd>": "Vd:4,D,sz",
+ "<Dd,Sd>": "Vd:4,D,sz",
+ "<Sn,Dn>": "Vn:4,N,sz",
+ "<Sm,Dm>": "Vm:4,M,sz",
+ "<endian_specifier>": "E",
+ "<label+/-12>": "imm12:12,U",
+ "<label+12>": "imm12:12",
+ "<label-12>": "imm12:12",
+ "<label24>": "imm24:24",
+ "<label24H>": "imm24:24,H",
+ "<label+/-4+4>": "imm4H:4,imm4L:4,U",
+ "<list4>": "D,Vd:4,type:4",
+ "<list3>": "D,Vd:4,index_align:4",
+ "<list3t>": "D,Vd:4,T",
+ "<list1>": "D,Vd:4",
+ "<list_len>": "N,Vn:4,len:2",
+ "<vlist32>": "D,Vd:4,imm8:8",
+ "<vlist64>": "D,Vd:4,imm8:8",
+ "<registers>": "register_list:16",
+ "<registers2>": "register_list:16",
+ "<registers1>": "Rt:4",
+ "APSR": "",
+ "<Rm>,<type> <Rs>": "Rm:4,Rs:4,type:2",
+ "FPSCR": "",
+ "SP": "",
+ "[<Rn>,#+/-<imm12>]": "Rn:4,U,imm12:12",
+ "[<Rn>,+/-<Rm>]{!}": "Rn:4,U,Rm:4,P,W",
+ "[<Rn>,+/-<Rm>{, <shift>}]": "Rn:4,U,Rm:4,type:2,imm5:5",
+ "[<Rn>,+/-<Rm>{, <shift>}]{!}": "Rn:4,U,Rm:4,type:2,imm5:5,P,W",
+ "[<Rn>] {,#+/-<imm12>}": "Rn:4,U,imm12:12",
+ "[<Rn>] {,#+/-<imm8>}": "Rn:4,U,imm4H:4,imm4L:4",
+ "[<Rn>]": "Rn:4",
+ "[<Rn>],#+/-<imm12>": "Rn:4,imm12:12,U",
+ "[<Rn>],+/-<Rm>{, <shift>}": "Rn:4,Rm:4,imm5:5,type:2,U",
+ "[<Rn>]{!}": "Rn:4,Rm:4",
+ "[<Rn>{@<align>}]{!}": "XXX",
+ "[<Rn>{,#+/-<imm12>}]{!}": "Rn:4,P,U,W,imm12:12",
+ "[<Rn>{,#+/-<imm8>}]{!}": "Rn:4,P,U,W,imm4H:4,imm4L:4",
+ "[<Rn>{,#+/-<imm8>}]": "Rn:4,U,imm8:8",
+ "[<Rn>], +/-<Rm>": "Rn:4,U,Rm:4",
+ "#<imm_simd1>": "i,imm3:3,imm4:4,cmode:4",
+ "#<imm_simd>": "op,i,imm3:3,imm4:4,cmode:4",
+ "#<imm_vs>": "L,imm6:6",
+ "#<imm_vsn>": "imm6:6",
+}
+
+// cross returns the string concatenation cross product of xs and ys.
+func cross(xs []string, ys ...string) []string {
+ var xys []string
+
+ for _, x := range xs {
+ for _, y := range ys {
+ xys = append(xys, x+y)
+ }
+ }
+ return xys
+}
+
+// crossCond returns the cross product of xs with all the possible
+// conditional execution suffixes. It is assumed that each string x in xs
+// contains a substring _COND_ marking where the conditional suffix
+// should be placed.
+func crossCond(xs []string) []string {
+ ys := choices["c"]
+ var xys []string
+
+ for _, x := range xs {
+ i := strings.Index(x, "_COND_")
+ pre, post := x[:i], x[i+6:]
+ for _, y := range ys {
+ xys = append(xys, pre+y+post)
+ }
+ }
+ return xys
+}
+
+// printText implements the -fmt=text mode, which is not implemented (yet?).
+func printText(p *Prog) {
+ log.Fatal("-fmt=text not implemented")
+}
+
+// printDecoder implements the -fmt=decoder mode.
+// It emits the tables.go for package armasm's decoder.
+func printDecoder(p *Prog) {
+ fmt.Printf("package armasm\n\n")
+
+ // Build list of opcodes sorted by name
+ // but preserving the sequential ranges needed for opcode decoding.
+ haveRange := make(map[string]string)
+ for _, r := range p.OpRanges {
+ haveRange[r] = r
+ }
+ var ranges []string
+ for _, r := range haveRange {
+ ranges = append(ranges, r)
+ }
+ sort.Strings(ranges)
+
+ // Emit const definitions for opcodes.
+ fmt.Printf("const (\n")
+ iota := 0
+ fmt.Printf("\t_ Op = iota\n")
+ iota++
+ for _, r := range ranges {
+ for _, op := range strings.Split(r, ",") {
+ if op == "" {
+ continue
+ }
+ // Assume if opcode says .EQ it is the start of a 16-wide
+ // iteration through the conditional suffixes. If so, emit
+ // blank names until the assigned value is 16-aligned.
+ if strings.Contains(op, ".EQ") {
+ for iota&15 != 0 {
+ fmt.Printf("\t_\n")
+ iota++
+ }
+ }
+ fmt.Printf("\t%s\n", strings.Replace(op, ".", "_", -1))
+ iota++
+ }
+ }
+ fmt.Printf(")\n")
+
+ // Emit slice mapping opcode number to name string.
+ fmt.Printf("\nvar opstr = [...]string{\n")
+ for _, r := range ranges {
+ for _, op := range strings.Split(r, ",") {
+ if op == "" {
+ continue
+ }
+ fmt.Printf("\t%s: %q,\n", strings.Replace(op, ".", "_", -1), op)
+ }
+ }
+ fmt.Printf("}\n")
+
+ // Emit decoding table.
+ unknown := map[string]bool{}
+ fmt.Printf("\nvar instFormats = [...]instFormat{\n")
+ for _, inst := range p.Inst {
+ fmt.Printf("\t{%#08x, %#08x, %d, %s, %#x, instArgs{", inst.Mask, inst.Value, inst.Priority, strings.Replace(inst.OpBase, ".", "_", -1), inst.OpBits)
+ for i, a := range inst.Args {
+ if i > 0 {
+ fmt.Printf(", ")
+ }
+ str := argOps[a]
+ if str == "" && !unknown[a] {
+ fmt.Fprintf(os.Stderr, "%s: unknown arg %s\n", inst.Text, a)
+ unknown[a] = true
+ }
+ fmt.Printf("%s", str)
+ }
+ fmt.Printf("}}, // %s %s\n", inst.Text, inst.Encoding)
+ }
+ fmt.Printf("}\n")
+}
diff --git a/arm/armspec/code.go b/arm/armspec/code.go
new file mode 100644
index 0000000..5269d21
--- /dev/null
+++ b/arm/armspec/code.go
@@ -0,0 +1,985 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package main
+
+import (
+ "bytes"
+ "fmt"
+ "reflect"
+ "strconv"
+ "strings"
+)
+
+var errSeeOther = fmt.Errorf("see other")
+var errStop = fmt.Errorf("stop")
+var errUndefined = fmt.Errorf("undefined")
+
+type StmtOp int
+
+const (
+ _ StmtOp = iota
+ Assign // 1
+ Return
+ Undefined
+ Unpredictable
+ See
+ ImplDefined
+ SubarchDefined
+ If
+ Repeat
+ While // 10
+ For
+ Case
+ Enum
+ Block
+ StmtExpr
+ Fndef
+ Assert
+)
+
+type Stmt struct {
+ Op StmtOp
+ X, Y, Z *Expr
+ List []*Expr
+ Text string
+ Body *Stmt
+ Else *Stmt
+ When []*When
+ ElseIf []*ElseIf
+ Block []*Stmt
+ Type *Type
+}
+
+type When struct {
+ Cond []*Expr
+ Body *Stmt
+}
+
+type ElseIf struct {
+ Cond *Expr
+ Body *Stmt
+}
+
+type ExprOp int
+
+const (
+ _ ExprOp = iota
+ Blank // 1
+ Const
+ Name
+ Decl
+ Unknown
+ Call
+ ExprTuple
+ Eq
+ NotEq
+ LtEq // 10
+ Lt
+ GtEq
+ Gt
+ BitIndex
+ IfElse
+ Not
+ AndAnd
+ OrOr
+ Eor
+ Colon // 20
+ And
+ Or
+ Plus
+ Minus
+ Add
+ Sub
+ Mul
+ Div
+ BigDIV
+ BigMOD // 30
+ BigAND
+ BigOR
+ BigEOR
+ TwoPow
+ Lsh
+ Rsh
+ Index
+ Dot
+)
+
+type Expr struct {
+ Op ExprOp
+ Text string
+ X, Y, Z *Expr
+ List []*Expr
+ Type *Type
+}
+
+type TypeOp int
+
+const (
+ _ TypeOp = iota
+ BoolType
+ BitType
+ IntegerType
+ NamedType
+ TupleType
+)
+
+type Type struct {
+ Op TypeOp
+ List []*Type
+ N int
+ NX *Expr
+ Text string
+}
+
+type Exec struct {
+ Vars map[string]Value
+}
+
+type Inconsistent struct {
+}
+
+func (Inconsistent) String() string {
+ return "INCONSISTENT"
+}
+
+type Bits struct {
+ N int
+ Val uint32
+ DontCare uint32
+}
+
+func (b Bits) String() string {
+ var buf bytes.Buffer
+ fmt.Fprintf(&buf, "`")
+ for i := b.N - 1; i >= 0; i-- {
+ if (b.DontCare>>uint(i))&1 != 0 {
+ fmt.Fprintf(&buf, "x")
+ } else if (b.Val>>uint(i))&1 != 0 {
+ fmt.Fprintf(&buf, "1")
+ } else {
+ fmt.Fprintf(&buf, "0")
+ }
+ }
+ fmt.Fprintf(&buf, "'")
+ return buf.String()
+}
+
+func (b Bits) Eq(v Value) bool {
+ c := v.(Bits)
+ if b.N != c.N {
+ panic(fmt.Errorf("compare of mismatched bit lengths %v and %v", b, c))
+ }
+ return b.Val&^c.DontCare == c.Val
+}
+
+func (b Bits) Lt(v Value) bool {
+ panic("less than on bits")
+}
+
+func (b Bits) Gt(v Value) bool {
+ panic("greater than on bits")
+}
+
+func isValid(inst *Inst, w uint32) bool {
+ var ctxt Exec
+ ctxt.Vars = make(map[string]Value)
+ off := 0
+ for _, b := range strings.Split(inst.Bits, "|") {
+ wid := 1
+ if i := strings.Index(b, ":"); i >= 0 {
+ wid, _ = strconv.Atoi(b[i+1:])
+ b = b[:i]
+ }
+ switch b {
+ case "1", "(1)":
+ if (w>>uint(31-off))&1 != 1 {
+ return false
+ }
+ case "0", "(0)":
+ if (w>>uint(31-off))&1 != 0 {
+ return false
+ }
+ default:
+ bits := Bits{N: wid, Val: (w >> uint(32-off-wid)) & (1<<uint(wid) - 1)}
+ // fmt.Print(b, " ", bits)
+ if old, ok := ctxt.Vars[b]; ok && old != bits {
+ ctxt.Define(b, Inconsistent{})
+ }
+ ctxt.Define(b, bits)
+ }
+ off += wid
+ }
+ // fmt.Println()
+
+ for _, stmt := range inst.Prog {
+ err := ctxt.stmt(stmt)
+ if err != nil {
+ if err == errSeeOther || err == errUndefined {
+ return false
+ }
+ if err == errStop {
+ break
+ }
+ panic(err)
+ }
+ }
+ return true
+}
+
+func (ctxt *Exec) Define(name string, value Value) {
+ ctxt.Vars[name] = value
+}
+
+func (ctxt *Exec) Assign(name string, value Value) error {
+ ctxt.Vars[name] = value
+ return nil
+}
+
+/*
+
+var global = map[string]Value{
+ "ConditionPassed": _ConditionPassed,
+ "UInt": _UInt,
+ "SInt": _SInt,
+}
+
+type Defn struct {
+ Name string
+ Value Value
+ Next *Defn
+}
+
+func (ctxt *Exec) Assign(name string, value Value) error {
+ for d := ctxt.Scope; d != nil; d = d.Next {
+ if d.Name == name {
+ d.Value = value
+ return nil
+ }
+ }
+ ctxt.Define(name, value)
+ return nil
+}
+
+func _ConditionPassed(ctxt *Exec, args []Value) (Value, error) {
+ return Bool(true), nil
+}
+*/
+
+type Int int64
+
+func (x Int) String() string {
+ return fmt.Sprint(int64(x))
+}
+
+func (x Int) Eq(y Value) bool { return x == y }
+func (x Int) Lt(y Value) bool { return x < y.(Int) }
+func (x Int) Gt(y Value) bool { return x > y.(Int) }
+
+func (x Int) Add(y Value) Value { return x + y.(Int) }
+func (x Int) Sub(y Value) Value { return x - y.(Int) }
+func (x Int) Mul(y Value) Value { return x * y.(Int) }
+
+func (x Int) Lsh(y Value) Value { return x << uint(y.(Int)) }
+func (x Int) Rsh(y Value) Value { return x >> uint(y.(Int)) }
+func (x Int) DIV(y Value) Value { return x / y.(Int) }
+
+func _UInt(_ *Exec, args []Value) (Value, error) {
+ if len(args) != 1 {
+ return nil, fmt.Errorf("UInt takes a single argument")
+ }
+ b, ok := args[0].(Bits)
+ if !ok {
+ return nil, fmt.Errorf("UInt takes a Bits, not %T", args[0])
+ }
+ if b.N > 63 {
+ return nil, fmt.Errorf("UInt cannot handle %d-bit Bits", b.N)
+ }
+ return Int(b.Val), nil
+}
+
+func _SInt(_ *Exec, args []Value) (Value, error) {
+ if len(args) != 1 {
+ return nil, fmt.Errorf("SInt takes a single argument")
+ }
+ b, ok := args[0].(Bits)
+ if !ok {
+ return nil, fmt.Errorf("SInt takes a Bits, not %T", args[0])
+ }
+ if b.N > 64 {
+ return nil, fmt.Errorf("SInt cannot handle %d-bit Bits", b.N)
+ }
+ return Int(int64(b.Val) << uint(64-b.N) >> uint(64-b.N)), nil
+}
+
+/*
+
+func (ctxt *Exec) Run(prog []*Stmt) error {
+ for _, stmt := range prog {
+ if err := ctxt.stmt(stmt); err != nil {
+ return err
+ }
+ }
+ return nil
+}
+
+*/
+
+func (ctxt *Exec) stmt(stmt *Stmt) error {
+ switch stmt.Op {
+ case If:
+ v, err := toBool(ctxt.expr(stmt.X))
+ if err != nil {
+ return err
+ }
+ if v {
+ return ctxt.stmt(stmt.Body)
+ }
+ for _, elseif := range stmt.ElseIf {
+ v, err := toBool(ctxt.expr(elseif.Cond))
+ if err != nil {
+ return err
+ }
+ if v {
+ return ctxt.stmt(elseif.Body)
+ }
+ }
+ if stmt.Else == nil {
+ return nil
+ }
+ return ctxt.stmt(stmt.Else)
+
+ case Case:
+ v, err := ctxt.expr(stmt.X)
+ if err != nil {
+ return err
+ }
+ vv, ok := v.(interface {
+ Eq(Value) bool
+ })
+ if !ok {
+ return fmt.Errorf("use of uncomparable value %T(%v) in case statement", v, v)
+ }
+ for _, when := range stmt.When {
+ for _, cond := range when.Cond {
+ w, err := ctxt.expr(cond)
+ if err != nil {
+ return err
+ }
+ if reflect.TypeOf(v) != reflect.TypeOf(w) {
+ return fmt.Errorf("mistyped comparison of %T(%v) and %T(%v) in case statement", v, v, w, w)
+ }
+ if vv.Eq(w) {
+ return ctxt.stmt(when.Body)
+ }
+ }
+ }
+ if stmt.Else == nil {
+ return nil
+ }
+ return ctxt.stmt(stmt.Else)
+
+ case Block:
+ for _, x := range stmt.Block {
+ if err := ctxt.stmt(x); err != nil {
+ return err
+ }
+ }
+ return nil
+
+ case See:
+ return errSeeOther
+
+ case Undefined:
+ return errUndefined
+
+ case Unpredictable, ImplDefined, SubarchDefined:
+ return errStop
+
+ case StmtExpr:
+ _, err := ctxt.expr(stmt.X)
+ return err
+
+ case Assign:
+ v, err := ctxt.expr(stmt.Y)
+ if err != nil {
+ return err
+ }
+ if stmt.X.Op == ExprTuple {
+ vv, ok := v.(Tuple)
+ if !ok {
+ return fmt.Errorf("assignment of non-tuple %T to tuple", v)
+ }
+ if len(stmt.X.List) != len(vv) {
+ return fmt.Errorf("%d = %d in tuple assignment", len(stmt.X.List), len(vv))
+ }
+ for i, x := range stmt.X.List {
+ if x.Op == Blank {
+ continue
+ }
+ if x.Op != Name {
+ return fmt.Errorf("cannot assign to expr op %d", x.Op)
+ }
+ if err := ctxt.Assign(x.Text, vv[i]); err != nil {
+ return err
+ }
+ }
+ return nil
+ }
+ x := stmt.X
+ if x.Op != Name {
+ return fmt.Errorf("cannot assign to expr op %d", x.Op)
+ }
+ return ctxt.Assign(x.Text, v)
+ }
+ return fmt.Errorf("unknown stmt op %d", stmt.Op)
+}
+
+func toBool(v Value, err error) (b Bool, xerr error) {
+ if err != nil {
+ return false, err
+ }
+ switch v := v.(type) {
+ case Bool:
+ return v, nil
+ default:
+ return false, fmt.Errorf("value of type %T used as bool", v)
+ }
+}
+
+type Value interface {
+ String() string
+}
+
+type Bool bool
+
+func (b Bool) Eq(v Value) bool { return b == v }
+
+func (b Bool) Not() Value { return !b }
+
+func (b Bool) String() string {
+ if b {
+ return "TRUE"
+ }
+ return "FALSE"
+}
+
+type Tuple []Value
+
+func (t Tuple) String() string {
+ var buf bytes.Buffer
+ fmt.Fprintf(&buf, "(")
+ for i, v := range t {
+ if i > 0 {
+ fmt.Fprintf(&buf, ", ")
+ }
+ fmt.Fprintf(&buf, v.String())
+ }
+ fmt.Fprintf(&buf, ")")
+ return buf.String()
+}
+
+func (ctxt *Exec) expr(x *Expr) (v Value, err error) {
+ switch x.Op {
+ case Call:
+ fn, err := ctxt.name(x.Text)
+ if err != nil {
+ return nil, err
+ }
+ var list []Value
+ for _, y := range x.List {
+ v, err := ctxt.expr(y)
+ if err != nil {
+ return nil, err
+ }
+ list = append(list, v)
+ }
+ return ctxt.call(x.Text, fn, list)
+
+ case ExprTuple:
+ var list []Value
+ for _, y := range x.List {
+ v, err := ctxt.expr(y)
+ if err != nil {
+ return nil, err
+ }
+ list = append(list, v)
+ }
+ if len(list) == 1 {
+ return list[0], nil
+ }
+ return Tuple(list), nil
+
+ case AndAnd:
+ v, err := toBool(ctxt.expr(x.X))
+ if err != nil {
+ return nil, err
+ }
+ if !v {
+ return v, nil
+ }
+ return ctxt.expr(x.Y)
+
+ case OrOr:
+ v, err := toBool(ctxt.expr(x.X))
+ if err != nil {
+ return nil, err
+ }
+ if v {
+ return v, nil
+ }
+ return ctxt.expr(x.Y)
+
+ case Colon:
+ v, err := ctxt.expr(x.X)
+ if err != nil {
+ return nil, err
+ }
+ y, err := ctxt.expr(x.Y)
+ if err != nil {
+ return nil, err
+ }
+ xb, ok := v.(Bits)
+ yb, ok2 := y.(Bits)
+ if !ok || !ok2 {
+ return nil, fmt.Errorf("colon operator requires bit strings")
+ }
+ b := xb
+ b.N += yb.N
+ b.Val <<= uint(yb.N)
+ b.DontCare <<= yb.DontCare
+ return b, nil
+
+ case Name:
+ return ctxt.name(x.Text)
+
+ case Const:
+ if (strings.HasPrefix(x.Text, "‘") || strings.HasPrefix(x.Text, "’")) && strings.HasSuffix(x.Text, "’") {
+ text := x.Text[len("‘") : len(x.Text)-len("’")]
+ var b Bits
+ b.N = len(text)
+ for _, c := range text {
+ b.Val <<= 1
+ b.DontCare <<= 1
+ if c == '1' {
+ b.Val |= 1
+ }
+ if c == 'x' {
+ b.DontCare |= 1
+ }
+ }
+ return b, nil
+ }
+ n, err := strconv.Atoi(x.Text)
+ if err == nil {
+ return Int(n), nil
+ }
+ println("const", x.Text)
+
+ case Not:
+ l, err := ctxt.expr(x.X)
+ if err != nil {
+ return nil, err
+ }
+ switch x.Op {
+ case Not:
+ ll, ok := l.(interface {
+ Not() Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support !", l)
+ }
+ return ll.Not(), nil
+ }
+
+ case Eq, NotEq, Lt, LtEq, Gt, GtEq, Add, Sub, Mul, Lsh, Rsh, BigDIV:
+ l, err := ctxt.expr(x.X)
+ if err != nil {
+ return nil, err
+ }
+ r, err := ctxt.expr(x.Y)
+ if err != nil {
+ return nil, err
+ }
+ tl := reflect.TypeOf(l)
+ tr := reflect.TypeOf(r)
+ if tl != tr {
+ return nil, fmt.Errorf("arithmetic (expr op %d) of %T(%v) with %T(%v)", x.Op, l, l, r, r)
+ }
+ switch x.Op {
+ case Eq:
+ ll, ok := l.(interface {
+ Eq(Value) bool
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support ==", l)
+ }
+ return Bool(ll.Eq(r)), nil
+ case NotEq:
+ ll, ok := l.(interface {
+ Eq(Value) bool
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support !=", l)
+ }
+ return Bool(!ll.Eq(r)), nil
+ case Lt:
+ ll, ok := l.(interface {
+ Lt(Value) bool
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support <", l)
+ }
+ return Bool(ll.Lt(r)), nil
+ case GtEq:
+ ll, ok := l.(interface {
+ Lt(Value) bool
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support >=", l)
+ }
+ return Bool(!ll.Lt(r)), nil
+ case Gt:
+ ll, ok := l.(interface {
+ Gt(Value) bool
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support >", l)
+ }
+ return Bool(ll.Gt(r)), nil
+ case LtEq:
+ ll, ok := l.(interface {
+ Gt(Value) bool
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support <=", l)
+ }
+ return Bool(!ll.Gt(r)), nil
+ case Add:
+ ll, ok := l.(interface {
+ Add(Value) Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support +", l)
+ }
+ return ll.Add(r), nil
+ case Sub:
+ ll, ok := l.(interface {
+ Sub(Value) Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support -", l)
+ }
+ return ll.Sub(r), nil
+ case Mul:
+ ll, ok := l.(interface {
+ Mul(Value) Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support *", l)
+ }
+ return ll.Mul(r), nil
+ case Lsh:
+ ll, ok := l.(interface {
+ Lsh(Value) Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support <<", l)
+ }
+ return ll.Lsh(r), nil
+ case Rsh:
+ ll, ok := l.(interface {
+ Rsh(Value) Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support >>", l)
+ }
+ return ll.Rsh(r), nil
+ case BigDIV:
+ ll, ok := l.(interface {
+ DIV(Value) Value
+ })
+ if !ok {
+ return nil, fmt.Errorf("type %T does not support DIV", l)
+ }
+ return ll.DIV(r), nil
+ }
+
+ case BitIndex:
+ l, err := ctxt.expr(x.X)
+ if err != nil {
+ return nil, err
+ }
+ b, ok := l.(Bits)
+ if !ok {
+ return nil, fmt.Errorf("bit index operator requires bitstring, not %T(%v)", l, l)
+ }
+ out := Bits{}
+ for _, ix := range x.List {
+ if ix.Op == Colon {
+ r1, err := ctxt.expr(ix.X)
+ if err != nil {
+ return nil, err
+ }
+ r2, err := ctxt.expr(ix.Y)
+ if err != nil {
+ return nil, err
+ }
+ i1, ok := r1.(Int)
+ i2, ok2 := r2.(Int)
+ if !ok || !ok2 {
+ return nil, fmt.Errorf("bit indexes must be int")
+ }
+ if i1 <= i2 {
+ return nil, fmt.Errorf("inverted bit indexes %d:%d", i1, i2)
+ }
+ w := int(i1 + 1 - i2)
+ out.N += w
+ out.Val <<= uint(w)
+ out.DontCare <<= uint(w)
+ out.Val |= (b.Val >> uint(i2)) & (1<<uint(w) - 1)
+ out.DontCare |= (b.DontCare >> uint(i2)) & (1<<uint(w) - 1)
+ } else {
+ r, err := ctxt.expr(ix)
+ if err != nil {
+ return nil, err
+ }
+ i, ok := r.(Int)
+ if !ok {
+ return nil, fmt.Errorf("bit index operator index must be int")
+ }
+ out.N++
+ out.Val <<= 1
+ out.DontCare <<= 1
+ out.Val |= (b.Val >> uint(i)) & 1
+ }
+ }
+ return out, nil
+
+ case IfElse:
+ v, err := toBool(ctxt.expr(x.X))
+ if err != nil {
+ return nil, err
+ }
+ if v {
+ return ctxt.expr(x.Y)
+ }
+ return ctxt.expr(x.Z)
+ }
+ return nil, fmt.Errorf("unknown expr op %d", x.Op)
+}
+
+type Func struct {
+ Name string
+ F func(*Exec, []Value) (Value, error)
+}
+
+func (f Func) String() string {
+ return f.Name
+}
+
+func (ctxt *Exec) call(name string, fn Value, args []Value) (Value, error) {
+ switch fn := fn.(type) {
+ case Func:
+ return fn.F(ctxt, args)
+ }
+ return nil, fmt.Errorf("cannot call %s of type %T", name, fn)
+}
+
+var global = map[string]Value{
+ "UInt": Func{"UInt", _UInt},
+ "DecodeImmShift": Func{"DecodeImmShift", _DecodeImmShift},
+ "ArchVersion": Func{"ArchVersion", _ArchVersion},
+ "ZeroExtend": Func{"ZeroExtend", _ZeroExtend},
+ "ARMExpandImm": Func{"ARMExpandImm", _ARMExpandImm},
+ "Zeros": Func{"Zeros", _Zeros},
+ "TRUE": Bool(true),
+ "FALSE": Bool(false),
+ "BitCount": Func{"BitCount", _BitCount},
+ "Consistent": Func{"Consistent", _Consistent},
+}
+
+func _Consistent(ctxt *Exec, args []Value) (Value, error) {
+ if len(args) != 1 {
+ return nil, fmt.Errorf("BitCount requires one argument")
+ }
+ _, inconsistent := args[0].(Inconsistent)
+ return Bool(!inconsistent), nil
+}
+
+func _BitCount(ctxt *Exec, args []Value) (Value, error) {
+ if len(args) != 1 {
+ return nil, fmt.Errorf("BitCount requires one argument")
+ }
+ b, ok1 := args[0].(Bits)
+ if !ok1 {
+ return nil, fmt.Errorf("BitCount requires bitstring argument")
+ }
+
+ n := 0
+ for i := 0; i < b.N; i++ {
+ if b.Val&(1<<uint(i)) != 0 {
+ n++
+ }
+ }
+ return Int(n), nil
+}
+
+func _ArchVersion(ctxt *Exec, args []Value) (Value, error) {
+ return Int(7), nil
+}
+
+func _ZeroExtend(ctxt *Exec, args []Value) (Value, error) {
+ if len(args) != 2 {
+ return nil, fmt.Errorf("ZeroExtend requires two arguments")
+ }
+ b, ok := args[0].(Bits)
+ n, ok2 := args[1].(Int)
+ if !ok || !ok2 {
+ return nil, fmt.Errorf("DecodeImmShift requires bitstring, int arguments")
+ }
+ b.N = int(n)
+ return b, nil
+}
+
+func _DecodeImmShift(ctxt *Exec, args []Value) (Value, error) {
+ if len(args) != 2 {
+ return nil, fmt.Errorf("DecodeImmShift requires two arguments")
+ }
+ b1, ok1 := args[0].(Bits)
+ b2, ok2 := args[1].(Bits)
+ if !ok1 || !ok2 {
+ return nil, fmt.Errorf("DecodeImmShift requires bitstring arguments")
+ }
+ _ = b1
+ _ = b2
+ // TODO
+ return Tuple{Int(0), Int(0)}, nil
+}
+
+func _ARMExpandImm(ctxt *Exec, args []Value) (Value, error) {
+ if len(args) != 1 {
+ return nil, fmt.Errorf("ARMExpandImm requires one argument")
+ }
+ b, ok1 := args[0].(Bits)
+ if !ok1 || b.N != 12 {
+ return nil, fmt.Errorf("ARMExpandImm requires 12-bit bitstring argument")
+ }
+ v := uint32(b.Val & 0xFF)
+ rot := uint(2 * ((b.Val >> 8) & 0xF))
+ v = v>>rot | v<<(32-rot)
+ return Bits{N: 32, Val: v}, nil
+}
+
+func _Zeros(ctxt *Exec, args []Value) (Value, error) {
+ if len(args) != 1 {
+ return nil, fmt.Errorf("Zeros requires one argument")
+ }
+ n, ok := args[0].(Int)
+ if !ok {
+ return nil, fmt.Errorf("Zeros requires int argument")
+ }
+ return Bits{N: int(n)}, nil
+}
+
+type Symbol string
+
+func (s Symbol) String() string { return string(s) }
+
+func (ctxt *Exec) name(name string) (v Value, err error) {
+ v, ok := ctxt.Vars[name]
+ if ok {
+ return v, nil
+ }
+ v, ok = global[name]
+ if ok {
+ return v, nil
+ }
+ return Symbol(name), nil
+ return nil, fmt.Errorf("unknown name %s", name)
+}
+
+/*
+func pseudoExec(base uint32, enc *Enc) {
+ var ctxt Exec
+ ctxt.Define("EncodingSpecificOperations", func(ctxt *Exec, args []Value) (Value, error) {
+ return nil, ctxt.Run(enc.Prog)
+ })
+
+ var n uint
+ for _, f := range enc.Fields {
+ switch f {
+ case "0", "1", "(0)", "(1)":
+ n++
+ default:
+ wid := size[f]
+ if wid == 0 {
+ panic("missing width for " + f)
+ }
+ ctxt.Define(f, Bits{N: wid, Val: (base>>(31-n))&(1<<uint(wid)-1)})
+ n += uint(wid)
+ }
+ }
+
+ if err := ctxt.Run(enc.Inst.Prog); err != nil {
+ log.Printf("%#x: %v", base, err)
+ }
+}
+
+func loadLibrary(data []byte) {
+ prog := parse("speclib.txt", string(data))
+ for _, stmt := range prog {
+ switch stmt.Op {
+ default:
+ log.Fatalf("unexpected statement in speclib.txt: %d", stmt.Op)
+ case Fndef:
+ global[stmt.Text] = funcImpl(stmt)
+ case Enum:
+ // TODO
+ }
+ }
+}
+
+func funcImpl(stmt *Stmt) func(*Exec, []Value) (Value, error) {
+ return func(ctxt *Exec, args []Value) (Value, error) {
+ ctxt1 := *ctxt
+ if len(args) != len(stmt.List) {
+ return nil, fmt.Errorf("calling %s: have %d arguments, want %d", stmt.Text, len(args), len(stmt.List))
+ }
+ for i, decl := range stmt.List {
+ v, err := convert(args[i], decl.Type)
+ if err != nil {
+ return nil, fmt.Errorf("calling %s: %v", stmt.Text, err)
+ }
+ ctxt1.Define(decl.Text, v)
+ }
+ err := ctxt1.stmt(stmt.Body)
+ if err != nil {
+ return nil, err
+ }
+ if ctxt1.ret == nil && stmt.Type != nil {
+ return nil, fmt.Errorf("calling %s: function body missing return", stmt.Text)
+ }
+ if ctxt1.ret != nil && stmt.Type == nil {
+ return nil, fmt.Errorf("calling %s: unexpected return value from function with no result", stmt.Text)
+ }
+ return ctxt1.ret, nil
+ }
+}
+
+func convert(v Value, typ *Type) (Value, error) {
+ switch typ.Op {
+ case BoolType:
+ if v, ok := v.(Bool); ok {
+ return v, nil
+ }
+ case BitType:
+ if v, ok := v.(Bits); ok && v.N == typ.N {
+ return v, nil
+ }
+ }
+ return nil, fmt.Errorf("cannot convert %s to type %v", v, typ)
+}
+
+*/
diff --git a/arm/armspec/pseudo.go b/arm/armspec/pseudo.go
new file mode 100644
index 0000000..20bcec8
--- /dev/null
+++ b/arm/armspec/pseudo.go
@@ -0,0 +1,264 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package main
+
+import (
+ "fmt"
+ "os"
+ "regexp"
+ "strings"
+)
+
+type Lexer struct {
+ input string
+ file string
+ lineno int
+ sym string
+ prog []*Stmt
+}
+
+type Line struct {
+ File string
+ Lineno int
+}
+
+func (l Line) String() string {
+ return fmt.Sprintf("%s:%d", l.File, l.Lineno)
+}
+
+var nerror int
+
+func (l Line) Errorf(format string, args ...interface{}) {
+ fmt.Printf("%s: %s\n", l, fmt.Sprintf(format, args...))
+ if nerror++; nerror > 20 {
+ fmt.Printf("too many errors\n")
+ os.Exit(1)
+ }
+}
+
+func re(s string) *regexp.Regexp {
+ return regexp.MustCompile(`\A(?:` + s + `)`)
+}
+
+var tokens = []struct {
+ re *regexp.Regexp
+ val int
+ fn func(*Lexer, string, *yySymType)
+}{
+ {re(`//[^\n]*`), -1, nil},
+ {re(`/\*(.|\n)*?\*/`), -1, nil},
+ {re(`[ \t\n]+`), -1, nil},
+ {re(`»`), _INDENT, nil},
+ {re(`«`), _UNINDENT, str},
+ {re(`return`), _RETURN, str},
+ {re(`UNDEFINED`), _UNDEFINED, str},
+ {re(`UNPREDICTABLE`), _UNPREDICTABLE, str},
+ {re(`SEE [^;]+`), _SEE, str},
+ {re(`IMPLEMENTATION_DEFINED( [^;]+)?`), _IMPLEMENTATION_DEFINED, str},
+ {re(`SUBARCHITECTURE_DEFINED( [^;]+)?`), _SUBARCHITECTURE_DEFINED, str},
+ {re(`if`), _IF, nil},
+ {re(`then`), _THEN, nil},
+ {re(`repeat`), _REPEAT, nil},
+ {re(`until`), _UNTIL, nil},
+ {re(`while`), _WHILE, nil},
+ {re(`case`), _CASE, nil},
+ {re(`for`), _FOR, nil},
+ {re(`to`), _TO, nil},
+ {re(`do`), _DO, nil},
+ {re(`of`), _OF, nil},
+ {re(`elsif`), _ELSIF, nil},
+ {re(`else`), _ELSE, nil},
+ {re(`otherwise`), _OTHERWISE, nil},
+ {re(`enumeration`), _ENUMERATION, nil},
+ {re(`when`), _WHEN, nil},
+ {re(`UNKNOWN`), _UNKNOWN, nil},
+ {re(`DIV`), _DIV, nil},
+ {re(`MOD`), _MOD, nil},
+ {re(`AND`), _AND, nil},
+ {re(`OR`), _OR, nil},
+ {re(`EOR`), _EOR, nil},
+ {re(`&&`), _ANDAND, nil},
+ {re(`\|\|`), _OROR, nil},
+ {re(`==`), _EQ, nil},
+ {re(`!=`), _NE, nil},
+ {re(` <`), _LT, nil},
+ {re(` ?<=`), _LE, nil},
+ {re(` ?>=`), _GE, nil},
+ {re(` >`), _GT, nil},
+ {re(`{`), '{', nil},
+ {re(`}`), '}', nil},
+ {re(`<`), '<', nil},
+ {re(`>`), '>', nil},
+ {re(`2^`), _TWOPOW, nil},
+ {re(` ?<<`), _LSH, nil},
+ {re(` ?>>`), _RSH, nil},
+ {re(`,`), ',', nil},
+ {re(`:`), ':', nil},
+ {re(`\+`), '+', nil},
+ {re(`\.`), '.', nil},
+ {re(`-`), '-', nil},
+ {re(`|`), '|', nil},
+ {re(`\^`), '^', nil},
+ {re(`\*`), '*', nil},
+ {re(`/`), '/', nil},
+ {re(`%`), '%', nil},
+ {re(`&`), '&', nil},
+ {re(`!`), '!', nil},
+ {re(`;`), ';', nil},
+ {re(`=`), '=', nil},
+ {re(`\(`), '(', nil},
+ {re(`\)`), ')', nil},
+ {re(`\[`), '[', nil},
+ {re(`\]`), ']', nil},
+ {re(`!`), '!', nil},
+ {re(`[0-9]+`), _CONST, str},
+ {re(`[0-9]+\.[0-9]+`), _CONST, str},
+ {re(`0x[0-9A-Fa-f]+`), _CONST, str},
+ {re("[‘’][ 0-9x]+’"), _CONST, strNoSpaces},
+ {re(`bit`), _BIT, str},
+ {re(`bits\(`), _BITS, str1x},
+ {re(`assert`), _ASSERT, str},
+ {re(`integer`), _INTEGER, nil},
+ {re(`boolean`), _BOOLEAN, nil},
+
+ {re(`[A-Za-z_][A-Za-z0-9_]*`), _NAME, str},
+ {re(`[A-Za-z_][A-Za-z0-9_]*\(`), _NAME_PAREN, str1x},
+}
+
+func (lx *Lexer) Lex(yy *yySymType) int {
+ if len(lx.input) == 0 {
+ return _EOF
+ }
+ var (
+ longest string
+ longestVal int
+ longestFn func(*Lexer, string, *yySymType)
+ )
+ for _, tok := range tokens {
+ s := tok.re.FindString(lx.input)
+ if len(s) > len(longest) {
+ longest = s
+ longestVal = tok.val
+ longestFn = tok.fn
+ }
+ }
+ if longest == "" {
+ lx.Error(fmt.Sprintf("lexer stuck at %.10q", lx.input))
+ return -1
+ }
+ //println(longest)
+ yy.line = lx.line()
+ if longestFn != nil {
+ lx.sym = longest
+ longestFn(lx, longest, yy)
+ }
+ lx.input = lx.input[len(longest):]
+ lx.lineno += strings.Count(longest, "\n")
+ if longestVal < 0 {
+ // skip
+ return lx.Lex(yy)
+ }
+ return longestVal
+}
+
+func (lx *Lexer) Error(s string) {
+ lx.line().Errorf("%s near %s", s, lx.sym)
+}
+
+func (lx *Lexer) line() Line {
+ return Line{lx.file, lx.lineno}
+}
+
+func nop(*Lexer, string, *yySymType) {
+ // having a function in the table
+ // will make the lexer save the string
+ // for use in error messages.
+ // nothing more to do.
+}
+
+func str(lx *Lexer, s string, yy *yySymType) {
+ yy.str = s
+}
+
+func str1(lx *Lexer, s string, yy *yySymType) {
+ yy.str = s[1:]
+}
+
+func str1x(lx *Lexer, s string, yy *yySymType) {
+ yy.str = s[:len(s)-1]
+}
+
+func strNoSpaces(lx *Lexer, s string, yy *yySymType) {
+ yy.str = strings.Replace(s, " ", "", -1)
+}
+
+func parse(name, text string) []*Stmt {
+ text = markup(text)
+ lx := &Lexer{
+ input: text,
+ file: name,
+ lineno: 1,
+ }
+ nerror = 0
+ yyParse(lx)
+ return lx.prog
+}
+
+func markup(text string) string {
+ prefix := ""
+
+ // Fix typos.
+ text = strings.Replace(text, "R[i}", "R[i]", -1)
+ text = strings.Replace(text, "R[n}", "R[n]", -1)
+ text = strings.Replace(text, "(1 << (3-UInt(op)-UInt(size));", "(1 << (3-UInt(op)-UInt(size)));", -1)
+ text = strings.Replace(text, "(D[n+r] AND NOT(D[m+r]);", "(D[n+r] AND NOT(D[m+r]));", -1)
+ text = strings.Replace(text, "(D[d+r] AND NOT(D[m+r]);", "(D[d+r] AND NOT(D[m+r]));", -1)
+ text = strings.Replace(text, "(D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]);", "(D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]));", -1)
+
+ // Add indent, unindent tags.
+ lines := strings.Split(text, "\n")
+ var indent []int
+ for j, line := range lines {
+ if i := strings.Index(line, "//"); i >= 0 {
+ line = line[:i]
+ }
+ if strings.TrimSpace(line) == "" {
+ continue
+ }
+ n := 0
+ for n < len(line) && line[n] == '\t' {
+ n++
+ }
+ if len(indent) == 0 {
+ indent = append(indent, n)
+ }
+ i := indent[len(indent)-1]
+ if i > n {
+ for i > n {
+ line = "«" + line
+ indent = indent[:len(indent)-1]
+ if len(indent) == 0 {
+ i = -1
+ } else {
+ i = indent[len(indent)-1]
+ }
+ }
+ if i == -1 {
+ indent = append(indent, n)
+ i = n
+ }
+ }
+ if i < n {
+ line = "»" + line
+ indent = append(indent, n)
+ }
+ lines[j] = line
+ }
+ n := len(indent) - 1
+ if n < 0 {
+ n = 0
+ }
+ return prefix + strings.Join(lines, "\n") + strings.Repeat("«", n)
+}
diff --git a/arm/armspec/pseudo.y b/arm/armspec/pseudo.y
new file mode 100644
index 0000000..6d9532f
--- /dev/null
+++ b/arm/armspec/pseudo.y
@@ -0,0 +1,553 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+%{
+package main
+
+import (
+ "strconv"
+)
+
+%}
+
+%union {
+ str string
+ line Line
+ stmt *Stmt
+ stmts []*Stmt
+ expr *Expr
+ exprs []*Expr
+ elseifs []*ElseIf
+ when *When
+ whens []*When
+ typ *Type
+ typs []*Type
+}
+
+%token _ASSERT
+%token _BITS
+%token _BIT
+%token _IF
+%token _EOF
+%token _NAME _NAME_PAREN
+%token _RETURN
+%token _UNDEFINED
+%token _UNPREDICTABLE
+%token _IMPLEMENTATION_DEFINED
+%token _SUBARCHITECTURE_DEFINED
+%token _ENUMERATION
+%token _DO
+%token _INDENT
+%token _UNINDENT
+%token _THEN
+%token _REPEAT
+%token _UNTIL
+%token _WHILE
+%token _CASE
+%token _FOR
+%token _TO
+%token _OF
+%token _ELSIF
+%token _ELSE
+%token _OTHERWISE
+%token _WHEN
+%token _CONST
+%token _UNKNOWN
+%token _EQ
+%token _NE
+%token _LE
+%token _GE
+%token _AND
+%token _OR
+%token _EOR
+%token _ANDAND
+%token _OROR
+%token _DIV
+%token _MOD
+%token _TWOPOW
+%token _LSH
+%token _RSH
+%token _INTEGER
+%token _BOOLEAN
+
+%token <str> _NAME _NAME_PAREN _CONST
+%token <str> _SEE
+
+%left last_resort
+%left '='
+%left ','
+%left _IF
+%left _ANDAND _OROR
+%left _LT _LE '>' _GE _GT _EQ _NE
+%left ':'
+%left '+' '-' '|' '^' _OR _EOR
+%left '*' '/' '%' '&' _LSH _RSH _DIV _MOD _AND
+%left _TWOPOW
+%left '.' '<' '['
+%left unary
+
+%type <stmts> stmt_list simple_stmt_list stmt_list_opt
+%type <stmt> stmt simple_stmt block simple_block otherwise enumeration
+%type <stmt> else_opt simple_else_opt else_end simple_else_end
+%type <elseifs> elsif_list simple_elsif_list
+%type <when> when
+%type <whens> when_list
+%type <exprs> expr_list_opt expr_list expr_minus_list const_list
+%type <expr> expr call_expr const
+%type <typ> unnamed_type
+
+%%
+
+top:
+ stmt_list_opt _EOF
+ {
+ yylex.(*Lexer).prog = $1
+ return 0
+ }
+
+simple_stmt:
+ expr '=' expr ';'
+ {
+ $$ = &Stmt{Op: Assign, X: $1, Y: $3}
+ }
+| expr _EQ expr ';'
+ {
+ $$ = &Stmt{Op: Assign, X: $1, Y: $3}
+ }
+| call_expr ';'
+ {
+ $$ = &Stmt{Op: StmtExpr, X: $1}
+ }
+| _RETURN expr_list_opt ';'
+ {
+ $$ = &Stmt{Op: Return, List: $2}
+ }
+| _UNDEFINED ';'
+ {
+ $$ = &Stmt{Op: Undefined}
+ }
+| _UNPREDICTABLE ';'
+ {
+ $$ = &Stmt{Op: Unpredictable}
+ }
+| _SEE ';'
+ {
+ $$ = &Stmt{Op: See, Text: $1}
+ }
+| _IMPLEMENTATION_DEFINED ';'
+ {
+ $$ = &Stmt{Op: ImplDefined}
+ }
+| _SUBARCHITECTURE_DEFINED ';'
+ {
+ $$ = &Stmt{Op: SubarchDefined}
+ }
+
+stmt:
+ simple_stmt
+| unnamed_type _NAME ';'
+ {
+ $$ = &Stmt{Op: StmtExpr, X: &Expr{Op: Decl, Type: $1, Text: $2}}
+ }
+| _IF expr _THEN block else_opt
+ {
+ $$ = &Stmt{Op: If, X: $2, Body: $4, ElseIf: $<elseifs>5, Else: $5}
+ }
+| _IF expr _THEN simple_stmt simple_else_opt
+ {
+ $$ = &Stmt{Op: If, X: $2, Body: $4, ElseIf: $<elseifs>5, Else: $5}
+ }
+| _REPEAT block _UNTIL expr ';'
+ {
+ $$ = &Stmt{Op: Repeat, Body: $2, X: $4}
+ }
+| _WHILE expr do block
+ {
+ $$ = &Stmt{Op: While, X: $2, Body: $4}
+ }
+| _FOR expr '=' expr _TO expr do block
+ {
+ $$ = &Stmt{Op: For, X: $2, Y: $4, Z: $6, Body: $8}
+ }
+| _CASE expr _OF _INDENT when_list otherwise _UNINDENT
+ {
+ $$ = &Stmt{Op: Case, X: $2, When: $5, Else: $6}
+ }
+| _ASSERT expr ';'
+ {
+ $$ = &Stmt{Op: Assert, X: $2}
+ }
+| block
+ {
+ $$ = $1
+ }
+| enumeration
+
+enumeration:
+ _ENUMERATION _NAME '{' expr_list '}' ';'
+ {
+ $$ = &Stmt{Op: Enum, Text: $2, List: $4}
+ }
+
+do:
+| _DO
+
+block:
+ _INDENT stmt_list _UNINDENT
+ {
+ $$ = &Stmt{Op: Block, Block: $2}
+ }
+
+simple_block:
+ simple_stmt_list
+ {
+ $$ = &Stmt{Op: Block, Block: $1}
+ }
+
+simple_stmt_list:
+ simple_stmt
+ {
+ $$ = []*Stmt{$1}
+ }
+| simple_stmt_list simple_stmt
+ {
+ $$ = append($1, $2)
+ }
+
+stmt_list:
+ stmt
+ {
+ $$ = []*Stmt{$1}
+ }
+| stmt_list stmt
+ {
+ $$ = append($1, $2)
+ }
+
+stmt_list_opt:
+ {
+ $$ = nil
+ }
+| stmt_list
+
+else_opt:
+ elsif_list else_end
+ {
+ $<elseifs>$ = $1
+ $$ = $2
+ }
+
+simple_else_opt:
+ simple_elsif_list simple_else_end
+ {
+ $<elseifs>$ = $1
+ $$ = $2
+ }
+
+elsif_list:
+ {
+ $$ = nil
+ }
+| elsif_list _ELSIF expr _THEN block
+ {
+ $$ = append($1, &ElseIf{Cond: $3, Body: $5})
+ }
+
+simple_elsif_list:
+ {
+ $$ = nil
+ }
+| simple_elsif_list _ELSIF expr _THEN simple_stmt
+ {
+ $$ = append($1, &ElseIf{Cond: $3, Body: $5})
+ }
+
+else_end:
+ {
+ $$ = nil
+ }
+| _ELSE block
+ {
+ $$ = $2
+ }
+| _ELSE simple_stmt
+ {
+ $$ = $2
+ }
+
+simple_else_end:
+ {
+ $$ = nil
+ }
+| _ELSE simple_stmt
+ {
+ $$ = $2
+ }
+
+when_list:
+ {
+ $$ = nil
+ }
+| when_list when
+ {
+ $$ = append($1, $2)
+ }
+
+when:
+ _WHEN const_list then block
+ {
+ $$ = &When{Cond: $2, Body: $4}
+ }
+| _WHEN const_list then simple_block
+ {
+ $$ = &When{Cond: $2, Body: $4}
+ }
+
+then:
+| _THEN
+
+otherwise:
+ {
+ $$ = nil
+ }
+| _OTHERWISE block
+ {
+ $$ = $2
+ }
+| _OTHERWISE simple_block
+ {
+ $$ = $2
+ }
+
+expr_list_opt:
+ {
+ $$ = nil
+ }
+| expr_list
+
+expr_list:
+ expr
+ {
+ $$ = []*Expr{$1}
+ }
+| expr_list ',' expr
+ {
+ $$ = append($1, $3)
+ }
+
+const_list:
+ const
+ {
+ $$ = []*Expr{$1}
+ }
+| const_list ',' const
+ {
+ $$ = append($1, $3)
+ }
+
+const:
+ _CONST
+ {
+ $$ = &Expr{Op: Const, Text: $1}
+ }
+| _NAME
+ {
+ $$ = &Expr{Op: Name, Text: $1}
+ }
+
+expr_minus_list:
+ expr
+ {
+ $$ = []*Expr{$1}
+ }
+| '-'
+ {
+ $$ = []*Expr{&Expr{Op: Blank}}
+ }
+| expr_minus_list ',' expr
+ {
+ $$ = append($1, $3)
+ }
+| expr_minus_list ',' '-'
+ {
+ $$ = append($1, &Expr{Op: Blank})
+ }
+
+expr:
+ _CONST
+ {
+ $$ = &Expr{Op: Const, Text: $1}
+ }
+| _NAME
+ {
+ $$ = &Expr{Op: Name, Text: $1}
+ }
+| unnamed_type _NAME
+ {
+ $$ = &Expr{Op: Decl, Type: $1, Text: $2}
+ }
+| _UNKNOWN
+ {
+ $$ = &Expr{Op: Unknown}
+ }
+| unnamed_type _UNKNOWN
+ {
+ $$ = &Expr{Op: Unknown, Type: $1}
+ }
+| call_expr
+| '(' expr_minus_list ')'
+ {
+ $$ = &Expr{Op: ExprTuple, List: $2}
+ }
+| expr _EQ expr
+ {
+ $$ = &Expr{Op: Eq, X: $1, Y: $3}
+ }
+| expr _NE expr
+ {
+ $$ = &Expr{Op: NotEq, X: $1, Y: $3}
+ }
+| expr _LE expr
+ {
+ $$ = &Expr{Op: LtEq, X: $1, Y: $3}
+ }
+| expr '<' expr_list '>'
+ {
+ $$ = &Expr{Op: BitIndex, X: $1, List: $3}
+ }
+| expr _LT expr
+ {
+ $$ = &Expr{Op: Lt, X: $1, Y: $3}
+ }
+| expr _GE expr
+ {
+ $$ = &Expr{Op: GtEq, X: $1, Y: $3}
+ }
+| expr _GT expr
+ {
+ $$ = &Expr{Op: Gt, X: $1, Y: $3}
+ }
+| _IF expr _THEN expr _ELSE expr %prec _IF
+ {
+ $$ = &Expr{Op: IfElse, X: $2, Y: $4, Z: $6}
+ }
+| '!' expr %prec unary
+ {
+ $$ = &Expr{Op: Not, X: $2}
+ }
+| expr _ANDAND expr
+ {
+ $$ = &Expr{Op: AndAnd, X: $1, Y: $3}
+ }
+| expr _OROR expr
+ {
+ $$ = &Expr{Op: OrOr, X: $1, Y: $3}
+ }
+| expr '^' expr
+ {
+ $$ = &Expr{Op: Eor, X: $1, Y: $3}
+ }
+| expr ':' expr
+ {
+ $$ = &Expr{Op: Colon, X: $1, Y: $3}
+ }
+| expr _AND expr
+ {
+ $$ = &Expr{Op: BigAND, X: $1, Y: $3}
+ }
+| expr _OR expr
+ {
+ $$ = &Expr{Op: BigOR, X: $1, Y: $3}
+ }
+| expr _EOR expr
+ {
+ $$ = &Expr{Op: BigEOR, X: $1, Y: $3}
+ }
+| '+' expr %prec unary
+ {
+ $$ = &Expr{Op: Plus, X: $2}
+ }
+| '-' expr %prec unary
+ {
+ $$ = &Expr{Op: Minus, X: $2}
+ }
+| expr '+' expr
+ {
+ $$ = &Expr{Op: Add, X: $1, Y: $3}
+ }
+| expr '-' expr
+ {
+ $$ = &Expr{Op: Sub, X: $1, Y: $3}
+ }
+| expr '*' expr
+ {
+ $$ = &Expr{Op: Mul, X: $1, Y: $3}
+ }
+| expr '/' expr
+ {
+ $$ = &Expr{Op: Div, X: $1, Y: $3}
+ }
+| expr _DIV expr
+ {
+ $$ = &Expr{Op: BigDIV, X: $1, Y: $3}
+ }
+| expr _MOD expr
+ {
+ $$ = &Expr{Op: BigMOD, X: $1, Y: $3}
+ }
+| _TWOPOW expr
+ {
+ $$ = &Expr{Op: TwoPow, X: $2}
+ }
+| expr _LSH expr
+ {
+ $$ = &Expr{Op: Lsh, X: $1, Y: $3}
+ }
+| expr _RSH expr
+ {
+ $$ = &Expr{Op: Rsh, X: $1, Y: $3}
+ }
+| expr '[' expr_list ']'
+ {
+ $$ = &Expr{Op: Index, X: $1, List: $3}
+ }
+| expr '.' _NAME
+ {
+ $$ = &Expr{Op: Dot, X: $1, Text: $3}
+ }
+| expr '=' expr %prec last_resort
+ {
+ $$ = &Expr{Op: Eq, X: $1, Y: $3}
+ }
+
+call_expr:
+ _NAME_PAREN expr_list_opt ')'
+ {
+ $$ = &Expr{Op: Call, Text: $1, List: $2}
+ }
+
+unnamed_type:
+ _BITS expr ')'
+ {
+ $$ = &Type{Op: BitType, NX: $2}
+ }
+| _BIT
+ {
+ $$ = &Type{Op: BitType, N: 1}
+ }
+| _INTEGER
+ {
+ $$ = &Type{Op: IntegerType}
+ }
+| _BOOLEAN
+ {
+ $$ = &Type{Op: BoolType}
+ }
+
+%%
+
+func parseIntConst(s string) int {
+ n, _ := strconv.Atoi(s)
+ return n
+}
diff --git a/arm/armspec/spec.go b/arm/armspec/spec.go
new file mode 100644
index 0000000..f76fab0
--- /dev/null
+++ b/arm/armspec/spec.go
@@ -0,0 +1,611 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Armspec reads the ``ARM Architecture Reference Manual''
+// to collect instruction encoding details and writes those details to standard output
+// in JSON format.
+//
+// Warning Warning Warning
+//
+// This program is unfinished. It is being published in this incomplete form
+// for interested readers, but do not expect it to be runnable or useful.
+//
+package main
+
+import (
+ "bufio"
+ "bytes"
+ "encoding/json"
+ "fmt"
+ "log"
+ "math"
+ "os"
+ "regexp"
+ "sort"
+ "strconv"
+ "strings"
+
+ "rsc.io/pdf"
+)
+
+type Inst struct {
+ Name string
+ ID string
+ Bits string
+ Arch string
+ Syntax []string
+ Code string
+}
+
+const debugPage = 0
+
+var stdout *bufio.Writer
+
+func main() {
+ log.SetFlags(0)
+ log.SetPrefix("armspec: ")
+
+ if len(os.Args) != 2 {
+ fmt.Fprintf(os.Stderr, "usage: armspec file.pdf\n")
+ os.Exit(2)
+ }
+
+ f, err := pdf.Open(os.Args[1])
+ if err != nil {
+ log.Fatal(err)
+ }
+
+ // Find instruction set reference in outline, to build instruction list.
+ instList := instHeadings(f.Outline())
+ if len(instList) < 200 {
+ log.Fatalf("only found %d instructions in table of contents", len(instList))
+ }
+
+ stdout = bufio.NewWriter(os.Stdout)
+ fmt.Fprintf(stdout, "[")
+ numTable := 0
+ defer stdout.Flush()
+
+ // Scan document looking for instructions.
+ // Must find exactly the ones in the outline.
+ n := f.NumPage()
+PageLoop:
+ for pageNum := 1; pageNum <= n; pageNum++ {
+ if debugPage > 0 && pageNum != debugPage {
+ continue
+ }
+ if pageNum > 1127 {
+ break
+ }
+ p := f.Page(pageNum)
+ name, table := parsePage(pageNum, p)
+ if name == "" {
+ continue
+ }
+ if len(table) < 1 {
+ if false {
+ fmt.Fprintf(os.Stderr, "no encodings for instruction %q (page %d)\n", name, pageNum)
+ }
+ continue
+ }
+ for _, inst := range table {
+ if numTable > 0 {
+ fmt.Fprintf(stdout, ",")
+ }
+ numTable++
+ js, _ := json.Marshal(inst)
+ fmt.Fprintf(stdout, "\n%s", jsFix.Replace(string(js)))
+ }
+ for j, headline := range instList {
+ if name == headline {
+ instList[j] = ""
+ continue PageLoop
+ }
+ }
+ fmt.Fprintf(os.Stderr, "unexpected instruction %q (page %d)\n", name, pageNum)
+ }
+
+ fmt.Fprintf(stdout, "\n]\n")
+ stdout.Flush()
+
+ if debugPage == 0 {
+ for _, headline := range instList {
+ if headline != "" {
+ switch headline {
+ default:
+ fmt.Fprintf(os.Stderr, "missing instruction %q\n", headline)
+ case "CHKA": // ThumbEE
+ case "CPS": // system instruction
+ case "CPY": // synonym for MOV
+ case "ENTERX": // ThumbEE
+ case "F* (former VFP instruction mnemonics)": // synonyms
+ case "HB, HBL, HBLP, HBP": // ThumbEE
+ case "LEAVEX": // ThumbEE
+ case "MOV (shifted register)": // pseudo instruction for ASR, LSL, LSR, ROR, and RRX
+ case "NEG": // synonym for RSB
+ case "RFE": // system instruction
+ case "SMC (previously SMI)": // system instruction
+ case "SRS": // system instruction
+ case "SUBS PC, LR and related instructions": // system instruction
+ case "VAND (immediate)": // pseudo instruction
+ case "VCLE (register)": // pseudo instruction
+ case "VCLT (register)": // pseudo instruction
+ case "VORN (immediate)": // pseudo instruction
+ }
+ }
+ }
+ }
+}
+
+func instHeadings(outline pdf.Outline) []string {
+ return appendInstHeadings(outline, nil)
+}
+
+var instRE = regexp.MustCompile(`A[\d.]+ Alphabetical list of instructions`)
+var childRE = regexp.MustCompile(`A[\d.]+ (.+)`)
+var sectionRE = regexp.MustCompile(`^A[\d.]+$`)
+var bitRE = regexp.MustCompile(`^( |[01]|\([01]\))*$`)
+
+func appendInstHeadings(outline pdf.Outline, list []string) []string {
+ if instRE.MatchString(outline.Title) {
+ for _, child := range outline.Child {
+ m := childRE.FindStringSubmatch(child.Title)
+ if m == nil {
+ fmt.Fprintf(os.Stderr, "cannot parse section title: %s\n", child.Title)
+ continue
+ }
+ list = append(list, m[1])
+ }
+ }
+ for _, child := range outline.Child {
+ list = appendInstHeadings(child, list)
+ }
+ return list
+}
+
+const inch = 72.0
+
+func parsePage(num int, p pdf.Page) (name string, table []Inst) {
+ content := p.Content()
+
+ var text []pdf.Text
+ for _, t := range content.Text {
+ if match(t, "Times-Roman", 7.2, "") {
+ t.FontSize = 9
+ }
+ if match(t, "Times-Roman", 6.72, "") && '0' <= t.S[0] && t.S[0] <= '9' {
+ t.S = string([]rune("⁰¹²³⁴⁵⁶⁷⁸⁹")[t.S[0]-'0'])
+ t.FontSize = 9
+ t.Y -= 2.28
+ }
+ if t.Font == "Gen_Arial" {
+ continue
+ }
+ text = append(text, t)
+ }
+
+ text = findWords(text)
+
+ for i, t := range text {
+ if t.Font == "Times" {
+ t.Font = "Times-Roman"
+ text[i] = t
+ }
+ }
+
+ if debugPage > 0 {
+ for _, t := range text {
+ fmt.Println(t)
+ }
+ for _, r := range content.Rect {
+ fmt.Println(r)
+ }
+ }
+
+ // Remove text we should ignore.
+ out := text[:0]
+ skip := false
+ for _, t := range text {
+ // skip page footer
+ if match(t, "Helvetica", 8, "A") || match(t, "Helvetica", 8, "ARM DDI") || match(t, "Helvetica-Oblique", 8, "Copyright") {
+ continue
+ }
+ // skip section header and body text
+ if match(t, "Helvetica-Bold", 12, "") && (sectionRE.MatchString(t.S) || t.S == "Alphabetical list of instructions") {
+ skip = true
+ continue
+ }
+ if skip && match(t, "Times-Roman", 9, "") {
+ continue
+ }
+ skip = false
+ out = append(out, t)
+ }
+ text = out
+
+ // Page header must say Instruction Details.
+ if len(text) == 0 || !match(text[0], "Helvetica-Oblique", 8, "Instruction Details") && !match(text[0], "Times-Roman", 9, "Instruction Details") {
+ return "", nil
+ }
+ text = text[1:]
+
+ isSection := func(text []pdf.Text, i int) int {
+ if i+2 <= len(text) && match(text[i], "Helvetica-Bold", 10, "") && sectionRE.MatchString(text[i].S) && match(text[i+1], "Helvetica-Bold", 10, "") {
+ return 2
+ }
+ if i+1 <= len(text) && match(text[i], "Helvetica-Bold", 10, "") && childRE.MatchString(text[i].S) {
+ return 1
+ }
+ return 0
+ }
+
+ // Skip dummy headlines and sections.
+ for d := isSection(text, 0); d != 0; d = isSection(text, 0) {
+ i := d
+ for i < len(text) && !match(text[i], "Helvetica-Bold", 9, "Encoding") && !match(text[i], "Helvetica-Bold", 10, "") {
+ i++
+ }
+ if isSection(text, i) == 0 {
+ break
+ }
+ text = text[i:]
+ }
+
+ // Next line is headline. Can wrap to multiple lines.
+ d := isSection(text, 0)
+ if d == 0 {
+ if debugPage > 0 {
+ fmt.Printf("non-inst-headline: %v\n", text[0])
+ }
+ checkNoEncodings(num, text)
+ return "", nil
+ }
+ if d == 2 {
+ name = text[1].S
+ text = text[2:]
+ } else if d == 1 {
+ m := childRE.FindStringSubmatch(text[0].S)
+ name = m[1]
+ text = text[1:]
+ }
+ for len(text) > 0 && match(text[0], "Helvetica-Bold", 10, "") {
+ name += " " + text[0].S
+ text = text[1:]
+ }
+
+ // Skip description.
+ for len(text) > 0 && (match(text[0], "Times-Roman", 9, "") || match(text[0], "LucidaSansTypewriteX", 6.48, "") || match(text[0], "Times-Bold", 10, "Note")) {
+ text = text[1:]
+ }
+
+ // Encodings follow.
+ warned := false
+ for i := 0; i < len(text); {
+ if match(text[i], "Helvetica-Bold", 10, "Assembler syntax") ||
+ match(text[i], "Helvetica-Bold", 9, "Modified operation in ThumbEE") ||
+ match(text[i], "Helvetica-Bold", 9, "Unallocated memory hints") ||
+ match(text[i], "Helvetica-Bold", 9, "Related encodings") ||
+ match(text[i], "Times-Roman", 9, "Figure A") ||
+ match(text[i], "Helvetica-Bold", 9, "Table A") ||
+ match(text[i], "Helvetica-Bold", 9, "VFP Instructions") ||
+ match(text[i], "Helvetica-Bold", 9, "VFP instructions") ||
+ match(text[i], "Helvetica-Bold", 9, "VFP vectors") ||
+ match(text[i], "Helvetica-Bold", 9, "FLDMX") ||
+ match(text[i], "Helvetica-Bold", 9, "FSTMX") ||
+ match(text[i], "Helvetica-Bold", 9, "Advanced SIMD and VFP") {
+ checkNoEncodings(num, text[i:])
+ break
+ }
+ if match(text[i], "Helvetica-Bold", 9, "Figure A") {
+ y := text[i].Y
+ i++
+ for i < len(text) && math.Abs(text[i].Y-y) < 2 {
+ i++
+ }
+ continue
+ }
+ if !match(text[i], "Helvetica-Bold", 9, "Encoding") {
+ if !warned {
+ warned = true
+ fmt.Fprintln(os.Stderr, "page", num, ": unexpected:", text[i])
+ }
+ i++
+ continue
+ }
+ inst := Inst{
+ Name: name,
+ }
+ enc := text[i].S
+ x := text[i].X
+ i++
+ // Possible subarchitecture notes.
+ for i < len(text) && text[i].X > x+36 {
+ if inst.Arch != "" {
+ inst.Arch += " "
+ }
+ inst.Arch += text[i].S
+ i++
+ }
+ // Encoding syntaxes.
+ for i < len(text) && (match(text[i], "LucidaSansTypewriteX", 6.48, "") || text[i].X > x+36) {
+ if text[i].X < x+0.25*inch {
+ inst.Syntax = append(inst.Syntax, text[i].S)
+ } else {
+ s := inst.Syntax[len(inst.Syntax)-1]
+ if !strings.Contains(s, "\t") {
+ s += "\t"
+ } else {
+ s += " "
+ }
+ s += text[i].S
+ inst.Syntax[len(inst.Syntax)-1] = s
+ }
+ i++
+ }
+
+ var bits, abits, aenc string
+ bits, i = readBitBox(inst.Name, inst.Syntax, content, text, i)
+ if strings.Contains(enc, " / ") {
+ if i < len(text) && match(text[i], "Times-Roman", 8, "") {
+ abits, i = readBitBox(inst.Name, inst.Syntax, content, text, i)
+ } else {
+ abits = bits
+ }
+ slash := strings.Index(enc, " / ")
+ aenc = "Encoding " + enc[slash+len(" / "):]
+ enc = enc[:slash]
+ }
+
+ // pseudocode
+ y0 := -1 * inch
+ tab := 0.0
+ for i < len(text) && match(text[i], "LucidaSansTypewriteX", 6.48, "") {
+ t := text[i]
+ i++
+ if math.Abs(t.Y-y0) < 3 {
+ // same line as last fragment, probably just two spaces
+ inst.Code += " " + t.S
+ continue
+ }
+ if inst.Code != "" {
+ inst.Code += "\n"
+ }
+ if t.X > x+0.1*inch {
+ if tab == 0 {
+ tab = t.X - x
+ }
+ inst.Code += strings.Repeat("\t", int((t.X-x)/tab+0.5))
+ } else {
+ tab = 0
+ }
+ inst.Code += t.S
+ y0 = t.Y
+ }
+
+ inst.ID = strings.TrimPrefix(enc, "Encoding ")
+ inst.Bits = bits
+ table = append(table, inst)
+ if abits != "" {
+ inst.ID = strings.TrimPrefix(aenc, "Encoding ")
+ inst.Bits = abits
+ table = append(table, inst)
+ }
+
+ }
+ return name, table
+}
+
+func readBitBox(name string, syntax []string, content pdf.Content, text []pdf.Text, i int) (string, int) {
+ // bit headings
+ y2 := 0.0
+ x1 := 0.0
+ x2 := 0.0
+ for i < len(text) && match(text[i], "Times-Roman", 8, "") {
+ if y2 == 0 {
+ y2 = text[i].Y
+ }
+ if x1 == 0 {
+ x1 = text[i].X
+ }
+ i++
+ }
+ // bit fields in box
+ y1 := 0.0
+ dy1 := 0.0
+ for i < len(text) && match(text[i], "Times-Roman", 9, "") {
+ if x2 < text[i].X+text[i].W {
+ x2 = text[i].X + text[i].W
+ }
+ y1 = text[i].Y
+ dy1 = text[i].FontSize
+ i++
+ }
+
+ if debugPage > 0 {
+ fmt.Println("encoding box", x1, y1, x2, y2)
+ }
+
+ // Find lines (thin rectangles) separating bit fields.
+ var bottom, top pdf.Rect
+ const (
+ yMargin = 0.25 * 72
+ xMargin = 2 * 72
+ )
+ for _, r := range content.Rect {
+ if r.Max.Y-r.Min.Y < 2 && x1-xMargin < r.Min.X && r.Min.X < x1 && x2 < r.Max.X && r.Max.X < x2+xMargin {
+ if y1-yMargin < r.Min.Y && r.Min.Y < y1 {
+ bottom = r
+ }
+ if y1+dy1 < r.Min.Y && r.Min.Y < y2 {
+ top = r
+ }
+ }
+ }
+
+ if debugPage > 0 {
+ fmt.Println("top", top, "bottom", bottom)
+ }
+
+ const ε = 0.1 * 72
+ var bars []pdf.Rect
+ for _, r := range content.Rect {
+ if r.Max.X-r.Min.X < 2 && math.Abs(r.Min.Y-bottom.Min.Y) < ε && math.Abs(r.Max.Y-top.Min.Y) < ε {
+ bars = append(bars, r)
+ }
+ }
+ sort.Sort(RectHorizontal(bars))
+
+ // There are 16-bit and 32-bit encodings.
+ // In practice, they are about 2.65 and 5.3 inches wide, respectively.
+ // Use 4 inches as a cutoff.
+ nbit := 32
+ dx := top.Max.X - top.Min.X
+ if top.Max.X-top.Min.X < 4*72 {
+ nbit = 16
+ }
+
+ total := 0
+ var buf bytes.Buffer
+ for i := 0; i < len(bars)-1; i++ {
+ if i > 0 {
+ fmt.Fprintf(&buf, "|")
+ }
+ var sub []pdf.Text
+ x1, x2 := bars[i].Min.X, bars[i+1].Min.X
+ for _, t := range content.Text {
+ tx := t.X + t.W/2
+ ty := t.Y + t.FontSize/2
+ if x1 < tx && tx < x2 && y1 < ty && ty < y2 {
+ sub = append(sub, t)
+ }
+ }
+ var str []string
+ for _, t := range findWords(sub) {
+ str = append(str, t.S)
+ }
+ s := strings.Join(str, " ")
+ s = strings.Replace(s, ")(", ") (", -1)
+ n := len(strings.Fields(s))
+ b := int(float64(nbit)*(x2-x1)/dx + 0.5)
+ if n == b {
+ for j, f := range strings.Fields(s) {
+ if j > 0 {
+ fmt.Fprintf(&buf, "|")
+ }
+ fmt.Fprintf(&buf, "%s", f)
+ }
+ } else {
+ if n != 1 {
+ fmt.Fprintf(os.Stderr, "%s - %s - multi-field %d-bit encoding: %s\n", name, syntax, n, s)
+ }
+ fmt.Fprintf(&buf, "%s:%d", s, b)
+ }
+ total += b
+ }
+
+ if total != nbit || total == 0 {
+ fmt.Fprintf(os.Stderr, "%s - %s - %d-bit encoding\n", name, syntax, total)
+ }
+ return buf.String(), i
+}
+
+type RectHorizontal []pdf.Rect
+
+func (x RectHorizontal) Swap(i, j int) { x[i], x[j] = x[j], x[i] }
+func (x RectHorizontal) Less(i, j int) bool { return x[i].Min.X < x[j].Min.X }
+func (x RectHorizontal) Len() int { return len(x) }
+
+func checkNoEncodings(num int, text []pdf.Text) {
+ for _, t := range text {
+ if match(t, "Helvetica-Bold", 9, "Encoding") {
+ fmt.Fprintf(os.Stderr, "page %d: unexpected encoding: %s\n", num, t.S)
+ }
+ }
+}
+
+func match(t pdf.Text, font string, size float64, substr string) bool {
+ return t.Font == font && math.Abs(t.FontSize-size) < 0.1 && strings.Contains(t.S, substr)
+}
+
+func findWords(chars []pdf.Text) (words []pdf.Text) {
+ // Sort by Y coordinate and normalize.
+ const nudge = 1
+ sort.Sort(pdf.TextVertical(chars))
+ old := -100000.0
+ for i, c := range chars {
+ if c.Y != old && math.Abs(old-c.Y) < nudge {
+ chars[i].Y = old
+ } else {
+ old = c.Y
+ }
+ }
+
+ // Sort by Y coordinate, breaking ties with X.
+ // This will bring letters in a single word together.
+ sort.Sort(pdf.TextVertical(chars))
+
+ // Loop over chars.
+ for i := 0; i < len(chars); {
+ // Find all chars on line.
+ j := i + 1
+ for j < len(chars) && chars[j].Y == chars[i].Y {
+ j++
+ }
+ var end float64
+ // Split line into words (really, phrases).
+ for k := i; k < j; {
+ ck := &chars[k]
+ s := ck.S
+ end = ck.X + ck.W
+ charSpace := ck.FontSize / 6
+ wordSpace := ck.FontSize * 2 / 3
+ l := k + 1
+ for l < j {
+ // Grow word.
+ cl := &chars[l]
+ if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+charSpace {
+ s += cl.S
+ end = cl.X + cl.W
+ l++
+ continue
+ }
+ // Add space to phrase before next word.
+ if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+wordSpace {
+ s += " " + cl.S
+ end = cl.X + cl.W
+ l++
+ continue
+ }
+ break
+ }
+ f := ck.Font
+ f = strings.TrimSuffix(f, ",Italic")
+ f = strings.TrimSuffix(f, "-Italic")
+ words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end - ck.X, s})
+ k = l
+ }
+ i = j
+ }
+
+ return words
+}
+
+func sameFont(f1, f2 string) bool {
+ f1 = strings.TrimSuffix(f1, ",Italic")
+ f1 = strings.TrimSuffix(f1, "-Italic")
+ f2 = strings.TrimSuffix(f1, ",Italic")
+ f2 = strings.TrimSuffix(f1, "-Italic")
+ return strings.TrimSuffix(f1, ",Italic") == strings.TrimSuffix(f2, ",Italic") || f1 == "Symbol" || f2 == "Symbol" || f1 == "TimesNewRoman" || f2 == "TimesNewRoman"
+}
+
+var jsFix = strings.NewReplacer(
+// `\u003c`, `<`,
+// `\u003e`, `>`,
+// `\u0026`, `&`,
+// `\u0009`, `\t`,
+)
+
+func printTable(name string, table []Inst) {
+ _ = strconv.Atoi
+}
diff --git a/arm/armspec/specmap.go b/arm/armspec/specmap.go
new file mode 100644
index 0000000..cfe29e0
--- /dev/null
+++ b/arm/armspec/specmap.go
@@ -0,0 +1,223 @@
+// Copyright 2014 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build ignore
+
+package main
+
+import (
+ "encoding/json"
+ "fmt"
+ "io/ioutil"
+ "log"
+ "os"
+ "regexp"
+ "strconv"
+ "strings"
+)
+
+var _ = os.Stdout
+var _ = fmt.Sprintf
+
+type Inst struct {
+ Name string
+ ID string
+ Bits string
+ Arch string
+ Syntax []string
+ Code string
+ Base uint32
+ Mask uint32
+ Prog []*Stmt
+}
+
+func main() {
+ data, err := ioutil.ReadFile("spec.json")
+ if err != nil {
+ log.Fatal(err)
+ }
+ var insts []Inst
+ if err := json.Unmarshal(data, &insts); err != nil {
+ log.Fatal(err)
+ }
+
+ var out []Inst
+ for _, inst := range insts {
+ inst.Prog = parse(inst.Name+" "+inst.ID, inst.Code)
+ if inst.ID[0] == 'A' && !strings.HasPrefix(inst.Syntax[0], "MSR<c>") && !strings.Contains(inst.Syntax[0], "<coproc>") && !strings.Contains(inst.Syntax[0], "VLDM") && !strings.Contains(inst.Syntax[0], "VSTM") {
+ out = append(out, inst)
+ }
+ }
+ insts = out
+
+ for i := range insts {
+ dosize(&insts[i])
+ }
+
+ var cond, special []Inst
+ for _, inst := range insts {
+ if inst.Base>>28 == 0xF {
+ special = append(special, inst)
+ } else {
+ cond = append(cond, inst)
+ }
+ }
+
+ fmt.Printf("special:\n")
+ split(special, 0xF0000000, 1)
+ fmt.Printf("cond:\n")
+ split(cond, 0xF0000000, 1)
+}
+
+func dosize(inst *Inst) {
+ var base, mask uint32
+ off := 0
+ for _, f := range strings.Split(inst.Bits, "|") {
+ if i := strings.Index(f, ":"); i >= 0 {
+ n, _ := strconv.Atoi(f[i+1:])
+ off += n
+ continue
+ }
+ for _, bit := range strings.Fields(f) {
+ switch bit {
+ case "0", "(0)":
+ mask |= 1 << uint(31-off)
+ case "1", "(1)":
+ base |= 1 << uint(31-off)
+ }
+ off++
+ }
+ }
+ if off != 16 && off != 32 {
+ log.Printf("incorrect bit count for %s %s: have %d", inst.Name, inst.Bits, off)
+ }
+ if off == 16 {
+ mask >>= 16
+ base >>= 16
+ }
+ mask |= base
+ inst.Mask = mask
+ inst.Base = base
+}
+
+func split(insts []Inst, used uint32, depth int) {
+Again:
+ if len(insts) <= 1 {
+ for _, inst := range insts {
+ fmt.Printf("%*s%#08x %#08x %s %s %v\n", depth*2+2, "", inst.Mask, inst.Base, inst.Syntax[0], inst.Bits, seeRE.FindAllString(inst.Code, -1))
+ }
+ return
+ }
+
+ m := ^used
+ for _, inst := range insts {
+ m &= inst.Mask
+ }
+ if m == 0 {
+ fmt.Printf("«%*s%#08x masked out (%d)\n", depth*2, "", used, len(insts))
+ for _, inst := range insts {
+ fmt.Printf("%*s%#08x %#08x %s %s %v\n", depth*2+2, "", inst.Mask, inst.Base, inst.Syntax[0], inst.Bits, seeRE.FindAllString(inst.Code, -1))
+ }
+ updated := false
+ for i := range insts {
+ if updateMask(&insts[i]) {
+ updated = true
+ }
+ }
+ fmt.Printf("»\n")
+ if updated {
+ goto Again
+ }
+ fmt.Printf("%*s%#08x masked out (%d)\n", depth*2, "", used, len(insts))
+ for _, inst := range insts {
+ fmt.Printf("%*s%#08x %#08x %s %s %v\n", depth*2+2, "", inst.Mask, inst.Base, inst.Syntax[0], inst.Bits, seeRE.FindAllString(inst.Code, -1))
+ }
+ //checkOverlap(used, insts)
+ return
+ }
+ for i := 31; i >= 0; i-- {
+ if m&(1<<uint(i)) != 0 {
+ m = 1 << uint(i)
+ break
+ }
+ }
+ var bit [2][]Inst
+ for _, inst := range insts {
+ b := (inst.Base / m) & 1
+ bit[b] = append(bit[b], inst)
+ }
+
+ for b, list := range bit {
+ if len(list) > 0 {
+ suffix := ""
+ if len(bit[1-b]) == 0 {
+ suffix = " (only)"
+ }
+ fmt.Printf("%*sbit %#08x = %d%s\n", depth*2, "", m, b, suffix)
+ split(list, used|m, depth+1)
+ }
+ }
+}
+
+var seeRE = regexp.MustCompile(`SEE ([^;\n]+)`)
+
+func updateMask(inst *Inst) bool {
+ defer func() {
+ if err := recover(); err != nil {
+ fmt.Println("PANIC:", err)
+ return
+ }
+ }()
+
+ print(".")
+ println(inst.Name, inst.ID, inst.Bits)
+ println(inst.Code)
+ wiggle := ^inst.Mask &^ 0xF0000000
+ n := countbits(wiggle)
+ m1 := ^uint32(0)
+ m2 := ^uint32(0)
+ for i := uint32(0); i < 1<<uint(n); i++ {
+ w := inst.Base | expand(i, wiggle)
+ if !isValid(inst, w) {
+ continue
+ }
+ m1 &= w
+ m2 &= ^w
+ }
+ m := m1 | m2
+ m &^= 0xF0000000
+ m |= 0xF0000000 & inst.Mask
+ if m&^inst.Mask != 0 {
+ fmt.Printf("%s %s: mask=%#x but decided %#x\n", inst.Name, inst.ID, inst.Mask, m)
+ inst.Mask = m
+ inst.Base = m1
+ return true
+ }
+ if inst.Mask&^m != 0 {
+ fmt.Printf("%s %s: mask=%#x but got %#x\n", inst.Name, inst.ID, inst.Mask, m)
+ panic("bad updateMask")
+ }
+ return false
+}
+
+func countbits(x uint32) int {
+ n := 0
+ for ; x != 0; x >>= 1 {
+ n += int(x & 1)
+ }
+ return n
+}
+
+func expand(x, m uint32) uint32 {
+ var out uint32
+ for i := uint(0); i < 32; i++ {
+ out >>= 1
+ if m&1 != 0 {
+ out |= (x & 1) << 31
+ x >>= 1
+ }
+ m >>= 1
+ }
+ return out
+}
diff --git a/arm/armspec/y.go b/arm/armspec/y.go
new file mode 100644
index 0000000..8a289ce
--- /dev/null
+++ b/arm/armspec/y.go
@@ -0,0 +1,1165 @@
+//line pseudo.y:2
+package main
+
+import __yyfmt__ "fmt"
+
+//line pseudo.y:2
+import (
+ "strconv"
+)
+
+//line pseudo.y:10
+type yySymType struct {
+ yys int
+ str string
+ line Line
+ stmt *Stmt
+ stmts []*Stmt
+ expr *Expr
+ exprs []*Expr
+ elseifs []*ElseIf
+ when *When
+ whens []*When
+ typ *Type
+ typs []*Type
+}
+
+const _ASSERT = 57346
+const _BITS = 57347
+const _BIT = 57348
+const _IF = 57349
+const _EOF = 57350
+const _NAME = 57351
+const _NAME_PAREN = 57352
+const _RETURN = 57353
+const _UNDEFINED = 57354
+const _UNPREDICTABLE = 57355
+const _IMPLEMENTATION_DEFINED = 57356
+const _SUBARCHITECTURE_DEFINED = 57357
+const _ENUMERATION = 57358
+const _DO = 57359
+const _INDENT = 57360
+const _UNINDENT = 57361
+const _THEN = 57362
+const _REPEAT = 57363
+const _UNTIL = 57364
+const _WHILE = 57365
+const _CASE = 57366
+const _FOR = 57367
+const _TO = 57368
+const _OF = 57369
+const _ELSIF = 57370
+const _ELSE = 57371
+const _OTHERWISE = 57372
+const _WHEN = 57373
+const _CONST = 57374
+const _UNKNOWN = 57375
+const _EQ = 57376
+const _NE = 57377
+const _LE = 57378
+const _GE = 57379
+const _AND = 57380
+const _OR = 57381
+const _EOR = 57382
+const _ANDAND = 57383
+const _OROR = 57384
+const _DIV = 57385
+const _MOD = 57386
+const _TWOPOW = 57387
+const _LSH = 57388
+const _RSH = 57389
+const _INTEGER = 57390
+const _BOOLEAN = 57391
+const _SEE = 57392
+const last_resort = 57393
+const _LT = 57394
+const _GT = 57395
+const unary = 57396
+
+var yyToknames = []string{
+ "_ASSERT",
+ "_BITS",
+ "_BIT",
+ "_IF",
+ "_EOF",
+ "_NAME",
+ "_NAME_PAREN",
+ "_RETURN",
+ "_UNDEFINED",
+ "_UNPREDICTABLE",
+ "_IMPLEMENTATION_DEFINED",
+ "_SUBARCHITECTURE_DEFINED",
+ "_ENUMERATION",
+ "_DO",
+ "_INDENT",
+ "_UNINDENT",
+ "_THEN",
+ "_REPEAT",
+ "_UNTIL",
+ "_WHILE",
+ "_CASE",
+ "_FOR",
+ "_TO",
+ "_OF",
+ "_ELSIF",
+ "_ELSE",
+ "_OTHERWISE",
+ "_WHEN",
+ "_CONST",
+ "_UNKNOWN",
+ "_EQ",
+ "_NE",
+ "_LE",
+ "_GE",
+ "_AND",
+ "_OR",
+ "_EOR",
+ "_ANDAND",
+ "_OROR",
+ "_DIV",
+ "_MOD",
+ "_TWOPOW",
+ "_LSH",
+ "_RSH",
+ "_INTEGER",
+ "_BOOLEAN",
+ "_SEE",
+ "last_resort",
+ " =",
+ " ,",
+ "_LT",
+ " >",
+ "_GT",
+ " :",
+ " +",
+ " -",
+ " |",
+ " ^",
+ " *",
+ " /",
+ " %",
+ " &",
+ " .",
+ " <",
+ " [",
+ "unary",
+}
+var yyStatenames = []string{}
+
+const yyEofCode = 1
+const yyErrCode = 2
+const yyMaxDepth = 200
+
+//line pseudo.y:544
+func parseIntConst(s string) int {
+ n, _ := strconv.Atoi(s)
+ return n
+}
+
+//line yacctab:1
+var yyExca = []int{
+ -1, 1,
+ 1, -1,
+ -2, 0,
+}
+
+const yyNprod = 107
+const yyPrivate = 57344
+
+var yyTokenNames []string
+var yyStates []string
+
+const yyLast = 1272
+
+var yyAct = []int{
+
+ 15, 190, 103, 44, 16, 134, 194, 16, 42, 5,
+ 47, 48, 49, 50, 140, 4, 13, 137, 79, 39,
+ 78, 138, 43, 6, 85, 46, 6, 181, 154, 134,
+ 133, 16, 96, 89, 91, 92, 93, 94, 79, 75,
+ 55, 74, 139, 134, 84, 83, 101, 82, 168, 81,
+ 6, 80, 108, 109, 110, 111, 79, 113, 114, 115,
+ 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
+ 126, 127, 128, 129, 130, 79, 112, 76, 134, 102,
+ 153, 77, 203, 3, 100, 188, 40, 27, 63, 150,
+ 16, 93, 132, 70, 71, 131, 72, 73, 143, 144,
+ 145, 16, 39, 147, 179, 180, 149, 142, 41, 6,
+ 41, 86, 68, 69, 141, 202, 75, 55, 74, 95,
+ 148, 98, 53, 54, 57, 63, 64, 65, 59, 60,
+ 70, 71, 38, 72, 73, 155, 87, 196, 79, 157,
+ 201, 56, 1, 58, 62, 66, 67, 164, 61, 68,
+ 69, 173, 174, 75, 55, 74, 193, 88, 156, 93,
+ 195, 170, 171, 167, 175, 178, 162, 176, 160, 172,
+ 169, 182, 161, 159, 185, 16, 14, 177, 16, 187,
+ 2, 184, 191, 16, 186, 0, 0, 0, 183, 192,
+ 0, 0, 0, 0, 0, 16, 189, 0, 0, 0,
+ 0, 200, 16, 207, 199, 16, 0, 0, 205, 208,
+ 0, 192, 0, 0, 204, 0, 0, 0, 206, 12,
+ 23, 24, 7, 0, 30, 37, 17, 18, 19, 21,
+ 22, 28, 0, 27, 136, 0, 8, 0, 9, 11,
+ 10, 0, 0, 0, 0, 0, 0, 29, 31, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 36, 0, 0, 25, 26, 20, 0, 0, 0, 0,
+ 0, 0, 0, 34, 35, 12, 23, 24, 7, 0,
+ 30, 37, 17, 18, 19, 21, 22, 28, 32, 27,
+ 33, 0, 8, 0, 9, 11, 10, 0, 0, 0,
+ 0, 0, 0, 29, 31, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 36, 0, 0, 25,
+ 26, 20, 0, 0, 0, 0, 0, 0, 0, 34,
+ 35, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 32, 0, 33, 98, 53, 54,
+ 57, 63, 64, 65, 59, 60, 70, 71, 0, 72,
+ 73, 0, 0, 0, 0, 99, 0, 56, 0, 58,
+ 62, 66, 67, 0, 61, 68, 69, 0, 0, 75,
+ 55, 74, 0, 0, 23, 24, 45, 135, 30, 37,
+ 17, 18, 19, 21, 22, 0, 0, 27, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 29, 31, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 36, 0, 0, 25, 26, 20,
+ 0, 0, 0, 0, 0, 0, 0, 34, 35, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 32, 0, 33, 98, 53, 54, 57, 63,
+ 64, 65, 59, 60, 70, 71, 0, 72, 73, 0,
+ 0, 0, 0, 99, 0, 56, 0, 58, 62, 66,
+ 67, 0, 61, 68, 69, 0, 0, 75, 55, 74,
+ 0, 165, 98, 53, 54, 57, 63, 64, 65, 59,
+ 60, 70, 71, 0, 72, 73, 0, 0, 0, 0,
+ 99, 0, 56, 0, 58, 62, 66, 67, 0, 61,
+ 68, 69, 0, 0, 75, 55, 74, 0, 151, 98,
+ 53, 54, 57, 63, 64, 65, 59, 60, 70, 71,
+ 0, 72, 73, 0, 0, 0, 0, 99, 0, 56,
+ 0, 58, 62, 66, 67, 0, 61, 68, 69, 0,
+ 0, 75, 55, 74, 0, 107, 23, 24, 45, 0,
+ 30, 37, 17, 18, 19, 21, 22, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 29, 31, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 36, 0, 0, 25,
+ 26, 20, 0, 0, 0, 0, 0, 0, 0, 34,
+ 35, 0, 0, 198, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 32, 0, 33, 98, 53, 54,
+ 57, 63, 64, 65, 59, 60, 70, 71, 0, 72,
+ 73, 0, 0, 0, 0, 99, 0, 56, 197, 58,
+ 62, 66, 67, 0, 61, 68, 69, 0, 0, 75,
+ 55, 74, 98, 53, 54, 57, 63, 64, 65, 59,
+ 60, 70, 71, 0, 72, 73, 0, 0, 0, 0,
+ 99, 104, 56, 0, 58, 62, 66, 67, 0, 61,
+ 68, 69, 0, 0, 75, 55, 74, 0, 98, 53,
+ 54, 57, 63, 64, 65, 59, 60, 70, 71, 0,
+ 72, 73, 0, 0, 0, 0, 99, 0, 56, 0,
+ 58, 62, 66, 67, 0, 61, 68, 69, 163, 0,
+ 75, 55, 74, 98, 53, 54, 57, 63, 64, 65,
+ 59, 60, 70, 71, 0, 72, 73, 0, 0, 0,
+ 0, 99, 0, 56, 0, 58, 62, 66, 67, 0,
+ 61, 68, 69, 166, 0, 75, 55, 74, 0, 0,
+ 0, 98, 53, 54, 57, 63, 64, 65, 59, 60,
+ 70, 71, 0, 72, 73, 0, 0, 0, 0, 99,
+ 0, 56, 0, 58, 62, 66, 67, 0, 61, 68,
+ 69, 163, 0, 75, 55, 74, 52, 53, 54, 57,
+ 63, 64, 65, 59, 60, 70, 71, 0, 72, 73,
+ 0, 0, 0, 0, 51, 0, 56, 146, 58, 62,
+ 66, 67, 0, 61, 68, 69, 0, 0, 75, 55,
+ 74, 98, 53, 54, 57, 63, 64, 65, 59, 60,
+ 70, 71, 0, 72, 73, 0, 0, 0, 0, 99,
+ 0, 56, 0, 58, 62, 66, 67, 0, 61, 68,
+ 69, 106, 0, 75, 55, 74, 0, 0, 98, 53,
+ 54, 57, 63, 64, 65, 59, 60, 70, 71, 0,
+ 72, 73, 0, 0, 0, 0, 99, 0, 56, 97,
+ 58, 62, 66, 67, 0, 61, 68, 69, 0, 0,
+ 75, 55, 74, 98, 53, 54, 57, 63, 64, 65,
+ 59, 60, 70, 71, 0, 72, 73, 0, 0, 0,
+ 0, 99, 0, 56, 0, 58, 62, 66, 67, 0,
+ 61, 68, 69, 0, 0, 75, 55, 74, 98, 53,
+ 54, 57, 63, 64, 65, 59, 60, 70, 71, 0,
+ 72, 73, 0, 0, 0, 0, 99, 0, 56, 0,
+ 58, 62, 66, 67, 0, 61, 68, 69, 0, 0,
+ 75, 55, 74, 98, 53, 54, 57, 63, 64, 65,
+ 59, 60, 70, 71, 0, 72, 73, 0, 0, 0,
+ 0, 105, 0, 56, 0, 58, 62, 66, 67, 0,
+ 61, 68, 69, 0, 0, 75, 55, 74, 52, 53,
+ 54, 57, 63, 64, 65, 59, 60, 70, 71, 0,
+ 72, 73, 0, 0, 0, 0, 51, 0, 56, 0,
+ 58, 62, 66, 67, 0, 61, 68, 69, 0, 0,
+ 75, 55, 74, 98, 53, 54, 57, 63, 64, 65,
+ 0, 0, 70, 71, 0, 72, 73, 23, 24, 45,
+ 0, 30, 37, 56, 0, 58, 62, 66, 67, 0,
+ 61, 68, 69, 0, 0, 75, 55, 74, 23, 24,
+ 45, 0, 30, 37, 29, 31, 23, 24, 45, 0,
+ 30, 37, 0, 0, 0, 0, 0, 36, 0, 0,
+ 25, 26, 0, 0, 0, 29, 31, 0, 0, 0,
+ 34, 35, 0, 29, 31, 0, 0, 0, 36, 0,
+ 0, 25, 26, 0, 0, 32, 36, 33, 0, 25,
+ 26, 34, 158, 0, 0, 0, 0, 0, 0, 34,
+ 90, 0, 0, 0, 0, 0, 32, 0, 33, 0,
+ 0, 0, 0, 0, 32, 0, 33, 63, 64, 65,
+ 0, 0, 70, 71, 0, 72, 73, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 62, 66, 67, 0,
+ 61, 68, 69, 0, 0, 75, 55, 74, 0, 152,
+ 63, 64, 65, 0, 0, 70, 71, 0, 72, 73,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 62,
+ 66, 67, 0, 61, 68, 69, 0, 0, 75, 55,
+ 74, 63, 64, 65, 0, 0, 70, 71, 0, 72,
+ 73, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 66, 67, 0, 61, 68, 69, 0, 0, 75,
+ 55, 74,
+}
+var yyPact = []int{
+
+ 271, -1000, 124, 271, -1000, -1000, 77, 1072, 69, 1072,
+ 1072, 1072, 1072, -1000, -1000, 994, 7, 1072, -19, -21,
+ -23, -25, -26, 1072, -1000, -1000, -1000, 271, 127, -1000,
+ -1000, -1000, 1101, 1072, 1072, 1072, 1072, 1072, -1000, -1000,
+ -38, -1000, 889, 75, -1000, 1072, 57, 674, 959, 854,
+ 495, 1072, 1072, 1072, 1072, 1072, 1072, 1072, 1072, 1072,
+ 1072, 1072, 1072, 1072, 1072, 1072, 1072, 1072, 1072, 1072,
+ 1072, 1072, 1072, 1072, 1072, 83, -1000, -40, -10, 924,
+ -1000, -1000, -1000, -1000, -1000, 313, 215, -54, -32, 924,
+ 1072, -1000, -1000, -1000, -27, -60, -1000, 379, 1072, 1072,
+ -1000, 817, 1072, 69, -1000, 1072, 71, -1000, 458, 1139,
+ 1172, 1172, 25, 1172, 1172, 1172, 1029, 1029, 50, 1203,
+ -27, 50, 50, 50, 50, -27, -27, -27, -27, -27,
+ -27, -48, -1000, -1000, 1072, -1000, -1000, 1072, 1093, -1000,
+ -1000, -1000, -1000, 782, 1172, 924, 1072, 421, -1000, 747,
+ -1000, -1000, -1000, -1000, -1000, 924, -24, 924, 1072, -1000,
+ 133, -1000, 123, 1072, 709, -1000, 1072, 74, -43, -1000,
+ 1072, 379, -1000, 1072, 561, 87, 674, 66, -1000, 379,
+ 128, -1000, 638, -1000, -1000, 603, -1000, 69, -1000, -1000,
+ -1000, 561, -1000, 62, -1000, -1000, -1000, 69, 561, -1000,
+ -1000, 379, 128, -1000, -1000, -1000, -1000, -1000, -1000,
+}
+var yyPgo = []int{
+
+ 0, 83, 182, 180, 15, 9, 16, 1, 177, 176,
+ 173, 172, 170, 169, 168, 166, 165, 163, 81, 20,
+ 157, 156, 0, 3, 6, 22, 142, 2, 140,
+}
+var yyR1 = []int{
+
+ 0, 26, 5, 5, 5, 5, 5, 5, 5, 5,
+ 5, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 9, 27, 27, 6, 7, 2, 2, 1,
+ 1, 3, 3, 10, 11, 14, 14, 15, 15, 12,
+ 12, 12, 13, 13, 17, 17, 16, 16, 28, 28,
+ 8, 8, 8, 18, 18, 19, 19, 21, 21, 24,
+ 24, 20, 20, 20, 20, 22, 22, 22, 22, 22,
+ 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
+ 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
+ 22, 22, 22, 22, 22, 22, 22, 22, 22, 22,
+ 22, 22, 23, 25, 25, 25, 25,
+}
+var yyR2 = []int{
+
+ 0, 2, 4, 4, 2, 3, 2, 2, 2, 2,
+ 2, 1, 3, 5, 5, 5, 4, 8, 7, 3,
+ 1, 1, 6, 0, 1, 3, 1, 1, 2, 1,
+ 2, 0, 1, 2, 2, 0, 5, 0, 5, 0,
+ 2, 2, 0, 2, 0, 2, 4, 4, 0, 1,
+ 0, 2, 2, 0, 1, 1, 3, 1, 3, 1,
+ 1, 1, 1, 3, 3, 1, 1, 2, 1, 2,
+ 1, 3, 3, 3, 3, 4, 3, 3, 3, 6,
+ 2, 3, 3, 3, 3, 3, 3, 3, 2, 2,
+ 3, 3, 3, 3, 3, 3, 2, 3, 3, 4,
+ 3, 3, 3, 3, 1, 1, 1,
+}
+var yyChk = []int{
+
+ -1000, -26, -3, -1, -4, -5, -25, 7, 21, 23,
+ 25, 24, 4, -6, -9, -22, -23, 11, 12, 13,
+ 50, 14, 15, 5, 6, 48, 49, 18, 16, 32,
+ 9, 33, 73, 75, 58, 59, 45, 10, 8, -4,
+ 9, 33, -22, -25, -23, 7, -6, -22, -22, -22,
+ -22, 52, 34, 35, 36, 67, 54, 37, 56, 41,
+ 42, 61, 57, 38, 39, 40, 58, 59, 62, 63,
+ 43, 44, 46, 47, 68, 66, 70, -18, -19, -22,
+ 70, 70, 70, 70, 70, -22, -1, 9, -20, -22,
+ 59, -22, -22, -22, -22, -18, 70, 20, 34, 52,
+ 9, -22, 22, -27, 17, 52, 27, 70, -22, -22,
+ -22, -22, -19, -22, -22, -22, -22, -22, -22, -22,
+ -22, -22, -22, -22, -22, -22, -22, -22, -22, -22,
+ -22, -19, 9, 70, 53, 74, 19, 71, 53, 74,
+ 74, -6, -5, -22, -22, -22, 20, -22, -6, -22,
+ 18, 70, 70, 55, 76, -22, -19, -22, 59, -10,
+ -14, -11, -15, 29, -22, 70, 26, -17, 72, -12,
+ 28, 29, -13, 28, 29, -22, -22, -8, -16, 30,
+ 31, 70, -22, -6, -5, -22, -5, -27, 19, -6,
+ -7, -2, -5, -21, -24, 32, 9, 20, 20, -6,
+ -5, -28, 53, 20, -6, -5, -6, -7, -24,
+}
+var yyDef = []int{
+
+ 31, -2, 0, 32, 29, 11, 0, 0, 0, 0,
+ 0, 0, 0, 20, 21, 0, 70, 53, 0, 0,
+ 0, 0, 0, 0, 104, 105, 106, 0, 0, 65,
+ 66, 68, 0, 0, 0, 0, 0, 53, 1, 30,
+ 67, 69, 0, 0, 70, 0, 0, 23, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 4, 0, 54, 55,
+ 6, 7, 8, 9, 10, 0, 0, 0, 0, 61,
+ 62, 80, 88, 89, 96, 0, 12, 0, 0, 0,
+ 67, 0, 0, 0, 24, 0, 0, 19, 101, 72,
+ 73, 74, 0, 76, 77, 78, 81, 82, 83, 84,
+ 85, 86, 87, 90, 91, 92, 93, 94, 95, 97,
+ 98, 0, 100, 5, 0, 103, 25, 0, 0, 71,
+ 102, 35, 37, 0, 72, 101, 0, 0, 16, 0,
+ 44, 2, 3, 75, 99, 56, 0, 63, 64, 13,
+ 39, 14, 42, 0, 0, 15, 0, 50, 0, 33,
+ 0, 0, 34, 0, 0, 79, 23, 0, 45, 0,
+ 0, 22, 0, 40, 41, 0, 43, 0, 18, 51,
+ 52, 26, 27, 48, 57, 59, 60, 0, 0, 17,
+ 28, 0, 0, 49, 36, 38, 46, 47, 58,
+}
+var yyTok1 = []int{
+
+ 1, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 75, 3, 3, 3, 64, 65, 3,
+ 73, 74, 62, 58, 53, 59, 66, 63, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 57, 70,
+ 67, 52, 55, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 68, 3, 76, 61, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 71, 60, 72,
+}
+var yyTok2 = []int{
+
+ 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
+ 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
+ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+ 54, 56, 69,
+}
+var yyTok3 = []int{
+ 0,
+}
+
+//line yaccpar:1
+
+/* parser for yacc output */
+
+var yyDebug = 0
+
+type yyLexer interface {
+ Lex(lval *yySymType) int
+ Error(s string)
+}
+
+const yyFlag = -1000
+
+func yyTokname(c int) string {
+ // 4 is TOKSTART above
+ if c >= 4 && c-4 < len(yyToknames) {
+ if yyToknames[c-4] != "" {
+ return yyToknames[c-4]
+ }
+ }
+ return __yyfmt__.Sprintf("tok-%v", c)
+}
+
+func yyStatname(s int) string {
+ if s >= 0 && s < len(yyStatenames) {
+ if yyStatenames[s] != "" {
+ return yyStatenames[s]
+ }
+ }
+ return __yyfmt__.Sprintf("state-%v", s)
+}
+
+func yylex1(lex yyLexer, lval *yySymType) int {
+ c := 0
+ char := lex.Lex(lval)
+ if char <= 0 {
+ c = yyTok1[0]
+ goto out
+ }
+ if char < len(yyTok1) {
+ c = yyTok1[char]
+ goto out
+ }
+ if char >= yyPrivate {
+ if char < yyPrivate+len(yyTok2) {
+ c = yyTok2[char-yyPrivate]
+ goto out
+ }
+ }
+ for i := 0; i < len(yyTok3); i += 2 {
+ c = yyTok3[i+0]
+ if c == char {
+ c = yyTok3[i+1]
+ goto out
+ }
+ }
+
+out:
+ if c == 0 {
+ c = yyTok2[1] /* unknown char */
+ }
+ if yyDebug >= 3 {
+ __yyfmt__.Printf("lex %s(%d)\n", yyTokname(c), uint(char))
+ }
+ return c
+}
+
+func yyParse(yylex yyLexer) int {
+ var yyn int
+ var yylval yySymType
+ var yyVAL yySymType
+ yyS := make([]yySymType, yyMaxDepth)
+
+ Nerrs := 0 /* number of errors */
+ Errflag := 0 /* error recovery flag */
+ yystate := 0
+ yychar := -1
+ yyp := -1
+ goto yystack
+
+ret0:
+ return 0
+
+ret1:
+ return 1
+
+yystack:
+ /* put a state and value onto the stack */
+ if yyDebug >= 4 {
+ __yyfmt__.Printf("char %v in %v\n", yyTokname(yychar), yyStatname(yystate))
+ }
+
+ yyp++
+ if yyp >= len(yyS) {
+ nyys := make([]yySymType, len(yyS)*2)
+ copy(nyys, yyS)
+ yyS = nyys
+ }
+ yyS[yyp] = yyVAL
+ yyS[yyp].yys = yystate
+
+yynewstate:
+ yyn = yyPact[yystate]
+ if yyn <= yyFlag {
+ goto yydefault /* simple state */
+ }
+ if yychar < 0 {
+ yychar = yylex1(yylex, &yylval)
+ }
+ yyn += yychar
+ if yyn < 0 || yyn >= yyLast {
+ goto yydefault
+ }
+ yyn = yyAct[yyn]
+ if yyChk[yyn] == yychar { /* valid shift */
+ yychar = -1
+ yyVAL = yylval
+ yystate = yyn
+ if Errflag > 0 {
+ Errflag--
+ }
+ goto yystack
+ }
+
+yydefault:
+ /* default state action */
+ yyn = yyDef[yystate]
+ if yyn == -2 {
+ if yychar < 0 {
+ yychar = yylex1(yylex, &yylval)
+ }
+
+ /* look through exception table */
+ xi := 0
+ for {
+ if yyExca[xi+0] == -1 && yyExca[xi+1] == yystate {
+ break
+ }
+ xi += 2
+ }
+ for xi += 2; ; xi += 2 {
+ yyn = yyExca[xi+0]
+ if yyn < 0 || yyn == yychar {
+ break
+ }
+ }
+ yyn = yyExca[xi+1]
+ if yyn < 0 {
+ goto ret0
+ }
+ }
+ if yyn == 0 {
+ /* error ... attempt to resume parsing */
+ switch Errflag {
+ case 0: /* brand new error */
+ yylex.Error("syntax error")
+ Nerrs++
+ if yyDebug >= 1 {
+ __yyfmt__.Printf("%s", yyStatname(yystate))
+ __yyfmt__.Printf(" saw %s\n", yyTokname(yychar))
+ }
+ fallthrough
+
+ case 1, 2: /* incompletely recovered error ... try again */
+ Errflag = 3
+
+ /* find a state where "error" is a legal shift action */
+ for yyp >= 0 {
+ yyn = yyPact[yyS[yyp].yys] + yyErrCode
+ if yyn >= 0 && yyn < yyLast {
+ yystate = yyAct[yyn] /* simulate a shift of "error" */
+ if yyChk[yystate] == yyErrCode {
+ goto yystack
+ }
+ }
+
+ /* the current p has no shift on "error", pop stack */
+ if yyDebug >= 2 {
+ __yyfmt__.Printf("error recovery pops state %d\n", yyS[yyp].yys)
+ }
+ yyp--
+ }
+ /* there is no state on the stack with an error shift ... abort */
+ goto ret1
+
+ case 3: /* no shift yet; clobber input char */
+ if yyDebug >= 2 {
+ __yyfmt__.Printf("error recovery discards %s\n", yyTokname(yychar))
+ }
+ if yychar == yyEofCode {
+ goto ret1
+ }
+ yychar = -1
+ goto yynewstate /* try again in the same state */
+ }
+ }
+
+ /* reduction by production yyn */
+ if yyDebug >= 2 {
+ __yyfmt__.Printf("reduce %v in:\n\t%v\n", yyn, yyStatname(yystate))
+ }
+
+ yynt := yyn
+ yypt := yyp
+ _ = yypt // guard against "declared and not used"
+
+ yyp -= yyR2[yyn]
+ yyVAL = yyS[yyp+1]
+
+ /* consult goto table to find next state */
+ yyn = yyR1[yyn]
+ yyg := yyPgo[yyn]
+ yyj := yyg + yyS[yyp].yys + 1
+
+ if yyj >= yyLast {
+ yystate = yyAct[yyg]
+ } else {
+ yystate = yyAct[yyj]
+ if yyChk[yystate] != -yyn {
+ yystate = yyAct[yyg]
+ }
+ }
+ // dummy call; replaced with literal code
+ switch yynt {
+
+ case 1:
+ //line pseudo.y:100
+ {
+ yylex.(*Lexer).prog = yyS[yypt-1].stmts
+ return 0
+ }
+ case 2:
+ //line pseudo.y:107
+ {
+ yyVAL.stmt = &Stmt{Op: Assign, X: yyS[yypt-3].expr, Y: yyS[yypt-1].expr}
+ }
+ case 3:
+ //line pseudo.y:111
+ {
+ yyVAL.stmt = &Stmt{Op: Assign, X: yyS[yypt-3].expr, Y: yyS[yypt-1].expr}
+ }
+ case 4:
+ //line pseudo.y:115
+ {
+ yyVAL.stmt = &Stmt{Op: StmtExpr, X: yyS[yypt-1].expr}
+ }
+ case 5:
+ //line pseudo.y:119
+ {
+ yyVAL.stmt = &Stmt{Op: Return, List: yyS[yypt-1].exprs}
+ }
+ case 6:
+ //line pseudo.y:123
+ {
+ yyVAL.stmt = &Stmt{Op: Undefined}
+ }
+ case 7:
+ //line pseudo.y:127
+ {
+ yyVAL.stmt = &Stmt{Op: Unpredictable}
+ }
+ case 8:
+ //line pseudo.y:131
+ {
+ yyVAL.stmt = &Stmt{Op: See, Text: yyS[yypt-1].str}
+ }
+ case 9:
+ //line pseudo.y:135
+ {
+ yyVAL.stmt = &Stmt{Op: ImplDefined}
+ }
+ case 10:
+ //line pseudo.y:139
+ {
+ yyVAL.stmt = &Stmt{Op: SubarchDefined}
+ }
+ case 11:
+ yyVAL.stmt = yyS[yypt-0].stmt
+ case 12:
+ //line pseudo.y:146
+ {
+ yyVAL.stmt = &Stmt{Op: StmtExpr, X: &Expr{Op: Decl, Type: yyS[yypt-2].typ, Text: yyS[yypt-1].str}}
+ }
+ case 13:
+ //line pseudo.y:150
+ {
+ yyVAL.stmt = &Stmt{Op: If, X: yyS[yypt-3].expr, Body: yyS[yypt-1].stmt, ElseIf: yyS[yypt-0].elseifs, Else: yyS[yypt-0].stmt}
+ }
+ case 14:
+ //line pseudo.y:154
+ {
+ yyVAL.stmt = &Stmt{Op: If, X: yyS[yypt-3].expr, Body: yyS[yypt-1].stmt, ElseIf: yyS[yypt-0].elseifs, Else: yyS[yypt-0].stmt}
+ }
+ case 15:
+ //line pseudo.y:158
+ {
+ yyVAL.stmt = &Stmt{Op: Repeat, Body: yyS[yypt-3].stmt, X: yyS[yypt-1].expr}
+ }
+ case 16:
+ //line pseudo.y:162
+ {
+ yyVAL.stmt = &Stmt{Op: While, X: yyS[yypt-2].expr, Body: yyS[yypt-0].stmt}
+ }
+ case 17:
+ //line pseudo.y:166
+ {
+ yyVAL.stmt = &Stmt{Op: For, X: yyS[yypt-6].expr, Y: yyS[yypt-4].expr, Z: yyS[yypt-2].expr, Body: yyS[yypt-0].stmt}
+ }
+ case 18:
+ //line pseudo.y:170
+ {
+ yyVAL.stmt = &Stmt{Op: Case, X: yyS[yypt-5].expr, When: yyS[yypt-2].whens, Else: yyS[yypt-1].stmt}
+ }
+ case 19:
+ //line pseudo.y:174
+ {
+ yyVAL.stmt = &Stmt{Op: Assert, X: yyS[yypt-1].expr}
+ }
+ case 20:
+ //line pseudo.y:178
+ {
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 21:
+ yyVAL.stmt = yyS[yypt-0].stmt
+ case 22:
+ //line pseudo.y:185
+ {
+ yyVAL.stmt = &Stmt{Op: Enum, Text: yyS[yypt-4].str, List: yyS[yypt-2].exprs}
+ }
+ case 25:
+ //line pseudo.y:194
+ {
+ yyVAL.stmt = &Stmt{Op: Block, Block: yyS[yypt-1].stmts}
+ }
+ case 26:
+ //line pseudo.y:200
+ {
+ yyVAL.stmt = &Stmt{Op: Block, Block: yyS[yypt-0].stmts}
+ }
+ case 27:
+ //line pseudo.y:206
+ {
+ yyVAL.stmts = []*Stmt{yyS[yypt-0].stmt}
+ }
+ case 28:
+ //line pseudo.y:210
+ {
+ yyVAL.stmts = append(yyS[yypt-1].stmts, yyS[yypt-0].stmt)
+ }
+ case 29:
+ //line pseudo.y:216
+ {
+ yyVAL.stmts = []*Stmt{yyS[yypt-0].stmt}
+ }
+ case 30:
+ //line pseudo.y:220
+ {
+ yyVAL.stmts = append(yyS[yypt-1].stmts, yyS[yypt-0].stmt)
+ }
+ case 31:
+ //line pseudo.y:225
+ {
+ yyVAL.stmts = nil
+ }
+ case 32:
+ yyVAL.stmts = yyS[yypt-0].stmts
+ case 33:
+ //line pseudo.y:232
+ {
+ yyVAL.elseifs = yyS[yypt-1].elseifs
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 34:
+ //line pseudo.y:239
+ {
+ yyVAL.elseifs = yyS[yypt-1].elseifs
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 35:
+ //line pseudo.y:245
+ {
+ yyVAL.elseifs = nil
+ }
+ case 36:
+ //line pseudo.y:249
+ {
+ yyVAL.elseifs = append(yyS[yypt-4].elseifs, &ElseIf{Cond: yyS[yypt-2].expr, Body: yyS[yypt-0].stmt})
+ }
+ case 37:
+ //line pseudo.y:254
+ {
+ yyVAL.elseifs = nil
+ }
+ case 38:
+ //line pseudo.y:258
+ {
+ yyVAL.elseifs = append(yyS[yypt-4].elseifs, &ElseIf{Cond: yyS[yypt-2].expr, Body: yyS[yypt-0].stmt})
+ }
+ case 39:
+ //line pseudo.y:263
+ {
+ yyVAL.stmt = nil
+ }
+ case 40:
+ //line pseudo.y:267
+ {
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 41:
+ //line pseudo.y:271
+ {
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 42:
+ //line pseudo.y:276
+ {
+ yyVAL.stmt = nil
+ }
+ case 43:
+ //line pseudo.y:280
+ {
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 44:
+ //line pseudo.y:285
+ {
+ yyVAL.whens = nil
+ }
+ case 45:
+ //line pseudo.y:289
+ {
+ yyVAL.whens = append(yyS[yypt-1].whens, yyS[yypt-0].when)
+ }
+ case 46:
+ //line pseudo.y:295
+ {
+ yyVAL.when = &When{Cond: yyS[yypt-2].exprs, Body: yyS[yypt-0].stmt}
+ }
+ case 47:
+ //line pseudo.y:299
+ {
+ yyVAL.when = &When{Cond: yyS[yypt-2].exprs, Body: yyS[yypt-0].stmt}
+ }
+ case 50:
+ //line pseudo.y:307
+ {
+ yyVAL.stmt = nil
+ }
+ case 51:
+ //line pseudo.y:311
+ {
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 52:
+ //line pseudo.y:315
+ {
+ yyVAL.stmt = yyS[yypt-0].stmt
+ }
+ case 53:
+ //line pseudo.y:320
+ {
+ yyVAL.exprs = nil
+ }
+ case 54:
+ yyVAL.exprs = yyS[yypt-0].exprs
+ case 55:
+ //line pseudo.y:327
+ {
+ yyVAL.exprs = []*Expr{yyS[yypt-0].expr}
+ }
+ case 56:
+ //line pseudo.y:331
+ {
+ yyVAL.exprs = append(yyS[yypt-2].exprs, yyS[yypt-0].expr)
+ }
+ case 57:
+ //line pseudo.y:337
+ {
+ yyVAL.exprs = []*Expr{yyS[yypt-0].expr}
+ }
+ case 58:
+ //line pseudo.y:341
+ {
+ yyVAL.exprs = append(yyS[yypt-2].exprs, yyS[yypt-0].expr)
+ }
+ case 59:
+ //line pseudo.y:347
+ {
+ yyVAL.expr = &Expr{Op: Const, Text: yyS[yypt-0].str}
+ }
+ case 60:
+ //line pseudo.y:351
+ {
+ yyVAL.expr = &Expr{Op: Name, Text: yyS[yypt-0].str}
+ }
+ case 61:
+ //line pseudo.y:357
+ {
+ yyVAL.exprs = []*Expr{yyS[yypt-0].expr}
+ }
+ case 62:
+ //line pseudo.y:361
+ {
+ yyVAL.exprs = []*Expr{&Expr{Op: Blank}}
+ }
+ case 63:
+ //line pseudo.y:365
+ {
+ yyVAL.exprs = append(yyS[yypt-2].exprs, yyS[yypt-0].expr)
+ }
+ case 64:
+ //line pseudo.y:369
+ {
+ yyVAL.exprs = append(yyS[yypt-2].exprs, &Expr{Op: Blank})
+ }
+ case 65:
+ //line pseudo.y:375
+ {
+ yyVAL.expr = &Expr{Op: Const, Text: yyS[yypt-0].str}
+ }
+ case 66:
+ //line pseudo.y:379
+ {
+ yyVAL.expr = &Expr{Op: Name, Text: yyS[yypt-0].str}
+ }
+ case 67:
+ //line pseudo.y:383
+ {
+ yyVAL.expr = &Expr{Op: Decl, Type: yyS[yypt-1].typ, Text: yyS[yypt-0].str}
+ }
+ case 68:
+ //line pseudo.y:387
+ {
+ yyVAL.expr = &Expr{Op: Unknown}
+ }
+ case 69:
+ //line pseudo.y:391
+ {
+ yyVAL.expr = &Expr{Op: Unknown, Type: yyS[yypt-1].typ}
+ }
+ case 70:
+ yyVAL.expr = yyS[yypt-0].expr
+ case 71:
+ //line pseudo.y:396
+ {
+ yyVAL.expr = &Expr{Op: ExprTuple, List: yyS[yypt-1].exprs}
+ }
+ case 72:
+ //line pseudo.y:400
+ {
+ yyVAL.expr = &Expr{Op: Eq, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 73:
+ //line pseudo.y:404
+ {
+ yyVAL.expr = &Expr{Op: NotEq, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 74:
+ //line pseudo.y:408
+ {
+ yyVAL.expr = &Expr{Op: LtEq, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 75:
+ //line pseudo.y:412
+ {
+ yyVAL.expr = &Expr{Op: BitIndex, X: yyS[yypt-3].expr, List: yyS[yypt-1].exprs}
+ }
+ case 76:
+ //line pseudo.y:416
+ {
+ yyVAL.expr = &Expr{Op: Lt, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 77:
+ //line pseudo.y:420
+ {
+ yyVAL.expr = &Expr{Op: GtEq, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 78:
+ //line pseudo.y:424
+ {
+ yyVAL.expr = &Expr{Op: Gt, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 79:
+ //line pseudo.y:428
+ {
+ yyVAL.expr = &Expr{Op: IfElse, X: yyS[yypt-4].expr, Y: yyS[yypt-2].expr, Z: yyS[yypt-0].expr}
+ }
+ case 80:
+ //line pseudo.y:432
+ {
+ yyVAL.expr = &Expr{Op: Not, X: yyS[yypt-0].expr}
+ }
+ case 81:
+ //line pseudo.y:436
+ {
+ yyVAL.expr = &Expr{Op: AndAnd, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 82:
+ //line pseudo.y:440
+ {
+ yyVAL.expr = &Expr{Op: OrOr, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 83:
+ //line pseudo.y:444
+ {
+ yyVAL.expr = &Expr{Op: Eor, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 84:
+ //line pseudo.y:448
+ {
+ yyVAL.expr = &Expr{Op: Colon, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 85:
+ //line pseudo.y:452
+ {
+ yyVAL.expr = &Expr{Op: BigAND, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 86:
+ //line pseudo.y:456
+ {
+ yyVAL.expr = &Expr{Op: BigOR, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 87:
+ //line pseudo.y:460
+ {
+ yyVAL.expr = &Expr{Op: BigEOR, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 88:
+ //line pseudo.y:464
+ {
+ yyVAL.expr = &Expr{Op: Plus, X: yyS[yypt-0].expr}
+ }
+ case 89:
+ //line pseudo.y:468
+ {
+ yyVAL.expr = &Expr{Op: Minus, X: yyS[yypt-0].expr}
+ }
+ case 90:
+ //line pseudo.y:472
+ {
+ yyVAL.expr = &Expr{Op: Add, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 91:
+ //line pseudo.y:476
+ {
+ yyVAL.expr = &Expr{Op: Sub, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 92:
+ //line pseudo.y:480
+ {
+ yyVAL.expr = &Expr{Op: Mul, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 93:
+ //line pseudo.y:484
+ {
+ yyVAL.expr = &Expr{Op: Div, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 94:
+ //line pseudo.y:488
+ {
+ yyVAL.expr = &Expr{Op: BigDIV, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 95:
+ //line pseudo.y:492
+ {
+ yyVAL.expr = &Expr{Op: BigMOD, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 96:
+ //line pseudo.y:496
+ {
+ yyVAL.expr = &Expr{Op: TwoPow, X: yyS[yypt-0].expr}
+ }
+ case 97:
+ //line pseudo.y:500
+ {
+ yyVAL.expr = &Expr{Op: Lsh, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 98:
+ //line pseudo.y:504
+ {
+ yyVAL.expr = &Expr{Op: Rsh, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 99:
+ //line pseudo.y:508
+ {
+ yyVAL.expr = &Expr{Op: Index, X: yyS[yypt-3].expr, List: yyS[yypt-1].exprs}
+ }
+ case 100:
+ //line pseudo.y:512
+ {
+ yyVAL.expr = &Expr{Op: Dot, X: yyS[yypt-2].expr, Text: yyS[yypt-0].str}
+ }
+ case 101:
+ //line pseudo.y:516
+ {
+ yyVAL.expr = &Expr{Op: Eq, X: yyS[yypt-2].expr, Y: yyS[yypt-0].expr}
+ }
+ case 102:
+ //line pseudo.y:522
+ {
+ yyVAL.expr = &Expr{Op: Call, Text: yyS[yypt-2].str, List: yyS[yypt-1].exprs}
+ }
+ case 103:
+ //line pseudo.y:528
+ {
+ yyVAL.typ = &Type{Op: BitType, NX: yyS[yypt-1].expr}
+ }
+ case 104:
+ //line pseudo.y:532
+ {
+ yyVAL.typ = &Type{Op: BitType, N: 1}
+ }
+ case 105:
+ //line pseudo.y:536
+ {
+ yyVAL.typ = &Type{Op: IntegerType}
+ }
+ case 106:
+ //line pseudo.y:540
+ {
+ yyVAL.typ = &Type{Op: BoolType}
+ }
+ }
+ goto yystack /* stack new state and value */
+}
